WO2014182135A1 - Appareil et procédé d'émission d'un signal de diffusion, appareil et procédé de réception d'un signal de diffusion - Google Patents

Appareil et procédé d'émission d'un signal de diffusion, appareil et procédé de réception d'un signal de diffusion Download PDF

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WO2014182135A1
WO2014182135A1 PCT/KR2014/004191 KR2014004191W WO2014182135A1 WO 2014182135 A1 WO2014182135 A1 WO 2014182135A1 KR 2014004191 W KR2014004191 W KR 2014004191W WO 2014182135 A1 WO2014182135 A1 WO 2014182135A1
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block
data
interleaving
interleaver
constellation
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PCT/KR2014/004191
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English (en)
Korean (ko)
Inventor
백종섭
김병길
김우찬
김재형
고우석
홍성룡
문철규
최진용
황재호
곽국연
정병국
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엘지전자 주식회사
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Priority to US14/759,604 priority Critical patent/US9577861B2/en
Priority to EP14795181.8A priority patent/EP2958319B1/fr
Publication of WO2014182135A1 publication Critical patent/WO2014182135A1/fr
Priority to US15/391,589 priority patent/US10924314B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/65—Arrangements characterised by transmission systems for broadcast
    • H04H20/71—Wireless systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
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    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2637—Modulators with direct modulation of individual subcarriers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
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    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3494—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems using non - square modulating pulses, e.g. using raised cosine pulses; Partial response QAM, i.e. with partial response pulse shaping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes

Definitions

  • the present invention relates to a broadcast signal transmission apparatus for transmitting a broadcast signal, a broadcast signal reception apparatus for receiving a broadcast signal, and a method for transmitting and receiving a broadcast signal.
  • the digital broadcast signal may include a larger amount of video / audio data than the analog broadcast signal, and may include various additional data in addition to the video / audio data.
  • the digital broadcasting system for digital broadcasting may provide HD (High Definition) level images, multi-channel sound, and various additional services.
  • HD High Definition
  • data transmission efficiency for high-capacity data transmission, robustness of the transmission / reception network, and flexibility of the network considering mobile reception equipment still need to be improved.
  • an object of the present invention is to transmit a broadcast signal for transmitting and receiving a broadcast signal for a future broadcast service (future broadcast service), a broadcast signal receiving device, and a broadcast signal for a future broadcast service (future broadcast service) And to provide a way to receive.
  • the present invention provides a method for transmitting a broadcast signal.
  • a method of transmitting a broadcast signal comprising: formatting input streams into a plurality of data pipes (DPs); Encoding data of the plurality of DPs according to a code rate for each DP, wherein encoding the data of the DP for each DP includes encoding LDPC (Low Density Parity Check) data of the plurality of DPs; Bit interleaving the encoded data, mapping the bit interleaved data to constellation according to the code rate, multi-input multi-duup (MIMO) encoding the mapped data, and the MIMO encoded Diagonal time interleaving the data; Mapping at least one signal of the encoded DP to generate at least one signal frame; And modulating data of the generated signal frame by an orthogonal frequency division multiplexing (OFDM) scheme and transmitting a broadcast signal including data of the modulated signal frame.
  • OFDM orthogonal frequency division multiplexing
  • said diagonal time interleaving comprises: performing a column wise write operation on said MIMO encoded data and storing it in a memory; and performing a diagonal wise read operation from said memory.
  • a method of transmitting a broadcast signal further comprising the step of performing interleaving may be proposed.
  • the generating of the signal frame may include performing frequency interleaving of data in the generated signal frame in units of pairs of OFDM symbols, and a method of transmitting a broadcast signal may be proposed.
  • the method of performing the frequency interleaving may be proposed a method of transmitting a broadcast signal, characterized in that for performing interleaving using two memories.
  • a method for transmitting a broadcast signal in which the constellation is QAM (Quadrature Amplitude Modulation) or NU-QAM (Non Uniform QAM) having a maximum capacity for each of the plurality of DPs may be proposed.
  • QAM Quadrature Amplitude Modulation
  • NU-QAM Non Uniform QAM
  • the encoding of the DP data by DP further comprises interleaving the data mapped to the constellation, and the interleaving the data mapped to the constellation, mapping to the constellation. Delaying the imaginary component by separating real and imaginary components of the data, and sequentially writing the delayed data, storing the stored data in a memory, and storing the data stored in the memory using a memory index.
  • a method of transmitting a broadcast signal the method may further include performing a reading operation.
  • the present invention provides a method for receiving a broadcast signal.
  • a method for receiving a broadcast signal according to the present invention includes: receiving a broadcast signal and demodulating data of a signal frame included in the received broadcast signal by an orthogonal frequency division multiplexing (OFDM) scheme; Parsing the signal frame by demapping data of a plurality of data pipes (DP); Decoding the data of the plurality of DPs according to a code rate for each DP, wherein decoding the data of the DP for each DP includes: diagonally time deinterleaving the data of the plurality of DPs, and time deinterleaved data.
  • OFDM orthogonal frequency division multiplexing
  • Decoding the MMO Multi Input Multi Ouput
  • the diagonal time deinterleaving comprises: performing a diagonal wise write operation on data of the plurality of DPs and storing the result in a memory; and reading a column wise from the memory.
  • Deinterleaving by performing a task may be proposed a method for receiving a broadcast signal further comprising.
  • the parsing of the signal frame may include performing frequency deinterleaving of data in the signal frame in pairs of OFDM symbols, and a method of receiving a broadcast signal may be proposed.
  • the performing of the frequency deinterleaving may include a method of receiving a broadcast signal, wherein the deinterleaving is performed using one memory.
  • a method of receiving a broadcast signal in which the constellation is a quadrature amplitude modulation (QAM) or a non uniform QAM (NU-QAM) having a maximum capacity for each of the plurality of DPs may be proposed.
  • QAM quadrature amplitude modulation
  • NU-QAM non uniform QAM
  • decoding the data of the DP for each DP further comprises deinterleaving the time deinterleaved data
  • deinterleaving the time deinterleaved data comprises: deinterleaving the time deinterleaved data. 0 is inserted into the memory index location that was ignored by the skip operation of data, the data is written using the memory index, stored in a single memory, and a read operation is performed on the data stored in the single memory.
  • the method may further include performing a reading, and delaying the real component by separating the real component and the imaginary component of the read data.
  • An apparatus for transmitting broadcast signals comprises: an input formatting module for formatting input streams into a plurality of DPs; A coding and modulation module for encoding data of the plurality of DPs according to a code rate for each DP, wherein the coding and modulation module is an LDPC encoding block for encoding low density parity check (LDPC) data of the plurality of DPs, and the LDPC encoding A bit interleaving block for bit interleaving the encoded data, a constellation mapping block for mapping the bit interleaved data to constellation according to the code rate, and a MIMO encoding for multi-input multi-upper (MIMO) encoding the mapped data.
  • LDPC low density parity check
  • a block and a diagonal time interleaving block for diagonal time interleaving the MIMO encoded data A frame generation module for generating at least one signal frame by mapping data of the encoded DP; And an OFDM module configured to modulate data of the generated signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) scheme and to transmit a broadcast signal including data of the modulated signal frame; It may be a broadcast signal transmission apparatus including a.
  • OFDM Orthogonal Frequency Division Multiplexing
  • the diagonal time interleaving block is interleaved by performing a column wise write operation on the MIMO encoded data and storing the result in a memory, and performing a diagonal wise read operation from the memory.
  • An apparatus for transmitting broadcast signals may be proposed.
  • the frame generation module may be proposed a broadcast signal transmission apparatus further includes a frequency interleaving block for performing frequency interleaving of data in the generated signal frame in units of pairs of OFDM symbols.
  • the frequency interleaving block may be proposed a broadcast signal transmission apparatus characterized in that to perform interleaving using two memories.
  • the broadcast signal transmission apparatus may be proposed that the constellation is QAM (Quadrature Amplitude Modulation) or NU-QAM (Non Uniform QAM) having a maximum capacity for each of the plurality of DPs.
  • QAM Quadrature Amplitude Modulation
  • NU-QAM Non Uniform QAM
  • the coding and modulation module further comprises an interleaving block for interleaving the data mapped to the constellation, and the interleaving block for interleaving the data mapped to the constellation, the data of the data mapped to the constellation.
  • the real and imaginary components are separated to delay the imaginary components, sequentially written to the delayed data, stored in the memory, and the data stored in the memory is read using a memory index.
  • An apparatus for receiving broadcast signals comprises: an OFDM module for receiving a broadcast signal and demodulating data of a signal frame included in the received broadcast signal by an orthogonal frequency division multiplexing (OFDM) scheme; A frame parsing module for parsing the signal frames by demapping data of a plurality of data pipes; A demapping and decoding module for decoding data of the plurality of DPs according to code rate for each DP, wherein the demapping and decoding module is a diagonal time deinterleaving block for diagonally time deinterleaving the data of the plurality of DPs; A MIMO decoding block that decodes the deinterleaved data into a Multi Input Multi Ouput (MIMO), a constellation demapping block that demaps the MIMO decoded data from a constellation according to the code rate, and demapping from the constellation A bit deinterleaving block for bit deinterleaving the data, and an OFDM module for receiving a broadcast signal and demodulating data of a signal frame included
  • the diagonal time deinterleaving block stores a memory in a memory by performing a diagonal wise write operation on the data of the plurality of DPs, and performs a column wise read operation from the memory.
  • a broadcast signal receiving apparatus may be proposed, which is characterized by deinterleaving.
  • the frame parsing module may be proposed a broadcast signal receiving apparatus further includes a frequency deinterleaving block for performing frequency deinterleaving of data in the signal frame in units of pairs of OFDM symbols.
  • the frequency deinterleaving block may be proposed a broadcast signal receiving apparatus, characterized in that for performing the deinterleaving using one memory.
  • a broadcast signal receiving apparatus may be proposed in which the constellation is QAM (Quadrature Amplitude Modulation) or NU-QAM (Non Uniform QAM) having a maximum capacity for each of the plurality of DPs.
  • QAM Quadrature Amplitude Modulation
  • NU-QAM Non Uniform QAM
  • the demapping & decoding module further includes a deinterleaving block for deinterleaving the time deinterleaved data, wherein the deinterleaving block for deinterleaving the time deinterleaved data comprises: deinterleaving the time deinterleaved data. 0 is inserted into the memory index location that was ignored by the skip operation of data, the data is written using the memory index, stored in a single memory, and a read operation is performed on the data stored in the single memory.
  • a broadcast signal receiving apparatus may be proposed which performs reading, and delays the real component by separating the real component and the imaginary component of the read data.
  • QoS can be adjusted for each service or service component by processing data according to characteristics of a service in order to provide various broadcasting services.
  • the present invention can secure transmission flexibility by transmitting various broadcast services through the same RF signal bandwidth.
  • the present invention can increase data transmission efficiency and increase robustness of transmitting and receiving broadcast signals by using a MIMO system.
  • FIG. 1 is a diagram illustrating a structure of a transmission apparatus for a next generation broadcast service according to an embodiment of the present invention.
  • FIG 2 illustrates an input formatting module according to an embodiment of the present invention.
  • FIG 3 illustrates an input formatting module according to another embodiment of the present invention.
  • FIG 4 illustrates an input formatting module according to another embodiment of the present invention.
  • FIG. 5 illustrates a coding and modulation module according to an embodiment of the present invention.
  • FIG. 6 is a diagram illustrating a frame structure module according to an embodiment of the present invention.
  • FIG. 7 illustrates a waveform generation module according to an embodiment of the present invention.
  • FIG. 8 is a diagram illustrating a structure of a reception device for a next generation broadcast service according to an embodiment of the present invention.
  • FIG. 9 illustrates a synchronization & demodulation module according to an embodiment of the present invention.
  • FIG. 10 illustrates a frame parsing module according to an embodiment of the present invention.
  • FIG. 11 illustrates a demapping & decoding module according to an embodiment of the present invention.
  • FIG 12 illustrates an output processor according to an embodiment of the present invention.
  • FIG 13 illustrates an output processor according to another embodiment of the present invention.
  • FIG. 14 illustrates a coding and modulation module according to another embodiment of the present invention.
  • FIG. 15 illustrates a demapping & decoding module according to another embodiment of the present invention.
  • FIG. 16 illustrates a coding & modulation module including a new rotation & I / Q interleaver block according to an embodiment of the present invention.
  • FIG. 17 illustrates a block by block I / Q interleaver according to an embodiment of the present invention.
  • FIG. 19 illustrates a writing process of an RPI according to an embodiment of the present invention.
  • FIG. 20 is a view illustrating a reading process of an RPI according to an embodiment of the present invention.
  • FIG. 21 is a mathematical representation of a memory index generation process for a RPI reading process according to an embodiment of the present invention.
  • FIG. 22 illustrates a process of generating a memory index of an RPI according to an embodiment of the present invention.
  • FIG. 23 illustrates a demapping & decoding module including a new I / Q deinterleaver & derotation block according to an embodiment of the present invention.
  • FIG. 24 illustrates a block by block I / Q deinterleaver according to an embodiment of the present invention.
  • 25 is a diagram illustrating an operation of inserting a zero value during an RPD operation according to an embodiment of the present invention.
  • FIG. 26 illustrates a deinterleaving process using a single memory during an RPD operation according to an embodiment of the present invention.
  • FIG. 27 is a diagram illustrating a memory index generation process during a read process of an RPD according to an embodiment of the present invention.
  • FIG. 28 is a mathematical representation of a memory index generation process for a RPD reading process according to an embodiment of the present invention.
  • 29 illustrates a process of generating a memory index of an RPD according to an embodiment of the present invention.
  • FIG. 30 is a diagram illustrating combinations of interleavers according to an embodiment of the present invention when no signal space diversity (SSD) is considered.
  • SSD signal space diversity
  • FIG. 31 illustrates a column wise writing operation of a block time interleaver and a diagonal time interleaver according to an embodiment of the present invention.
  • FIG. 32 is a diagram illustrating a first scenario S1 of a combination of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • FIG. 33 is a diagram illustrating a second scenario S2 among combinations of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • FIG. 34 is a diagram illustrating a third scenario S3 of a combination of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • FIG. 35 is a diagram illustrating a fourth scenario S4 of a combination of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • FIG 36 illustrates combinations of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 37 is a diagram illustrating a first scenario S1 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 38 is a diagram illustrating a first scenario S1 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 39 is a diagram illustrating a second scenario S2 among combinations of interleavers according to an embodiment of the present invention when considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 40 is a diagram illustrating a second scenario S2 among combinations of interleavers according to an embodiment of the present invention when considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 41 is a diagram illustrating a third scenario S3 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 42 illustrates a third scenario S3 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 43 is a diagram illustrating a fourth scenario S4 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 44 illustrates a fourth scenario S4 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG 45 is a diagram illustrating a fifth scenario S5 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 46 is a diagram illustrating a fifth scenario S5 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 47 is a diagram illustrating a sixth scenario S6 of a combination of interleavers according to an embodiment of the present invention when considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 48 is a diagram illustrating a sixth scenario S6 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • 49 is a diagram illustrating an entire transceiver unit by connecting a transmitter and a receiver according to an embodiment of the present invention.
  • FIG. 50 is a diagram illustrating binary reflected gray code (BRGC) and bit package allocation according to an embodiment of the present invention.
  • FIG. 51 is a view illustrating a 256 QAM constellation mapping process according to an embodiment of the present invention.
  • FIG. 52 illustrates a constellation shift method for generating a modified 256 QAM according to an embodiment of the present invention.
  • FIG. 53 illustrates a final constellation diagram of a modified 256 QAM according to an embodiment of the present invention.
  • 54 is a view illustrating constellation points corresponding to 0 and 1 in a 256 bit QAM constellation modified according to an embodiment of the present invention.
  • 55 is a diagram illustrating the performance when a modified 256 QAM is used according to an embodiment of the present invention.
  • FIG. 56 is a view illustrating constellations in which modified 256 QAM is further improved according to an embodiment of the present invention.
  • 57 is a view illustrating a constellation shift method of an improved modified 256 QAM according to an embodiment of the present invention as a coordinate value.
  • FIG. 58 is a diagram illustrating the capacity of an improved variant 256 QAM according to an embodiment of the present invention.
  • FIG. 59 illustrates a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • Embodiment # 1 is a flowchart of Embodiment # 1 of a method of generating a new non uniform constellation according to one embodiment of the present invention.
  • FIG. 61 is a flowchart of Embodiment # 2 of a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • FIG. 62 is a flowchart of Embodiment # 3 of a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • FIG. 63 is a flowchart of Embodiment # 4 of a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • FIG. 64 is a diagram illustrating modified Non-Uniform Modified 256 QAM according to the present invention compared to Modified 256 QAM when the SNR value is 22 dB.
  • FIG. 65 is a graph illustrating gain values of a Non Uniform Modified 256 QAM according to an embodiment of the present invention.
  • FIG. 66 is a view illustrating a capacity difference between a non uniform modified 256 QAM (Non Uniform modified 256 QAM) and a capacity of Shannon limit according to an embodiment of the present invention.
  • 67 is a diagram illustrating a method for transmitting a broadcast signal according to an embodiment of the present invention.
  • 68 is a diagram illustrating a method of receiving a broadcast signal according to an embodiment of the present invention.
  • the present invention is to provide an apparatus and method for transmitting and receiving broadcast signals for the next generation broadcast service.
  • the next generation broadcast service according to an embodiment of the present invention is a concept including a terrestrial broadcast service, a mobile broadcast service, and an ultra high definition television (UHDTV) service.
  • the broadcast signal for the next generation broadcast service may be processed using a non-MIMO (Multi Input Multi Output) method or a MIMO method.
  • the non-MIMO scheme according to an embodiment of the present invention may include a MISO (Multi Input Single Output), a SISO (Single Input Single Output) scheme, and the like.
  • multiple antennas of MISO or MIMO may be described with two antennas as an example for convenience of description, but the description of the present invention may be applied to a system using two or more antennas.
  • FIG. 1 is a diagram illustrating a structure of a transmission apparatus for a next generation broadcast service according to an embodiment of the present invention.
  • a transmission apparatus for a next generation broadcast service includes an input formatting module 1000, a coding and modulation module 1100, a frame structure module 1200, a waveform generation module 1300, and a signaling generation module ( 1400).
  • an input formatting module 1000 includes an input formatting module 1000, a coding and modulation module 1100, a frame structure module 1200, a waveform generation module 1300, and a signaling generation module ( 1400).
  • a transmission apparatus for a next generation broadcast service includes an MPEG-TS stream, an IP stream (v4 / v6), and a generic stream (GS) as input signals. ) Can be input.
  • the terminal may receive additional management information regarding the configuration of each stream constituting the input signal and generate a final physical layer signal by referring to the received additional information.
  • the input formatting module 1000 divides the input streams according to a criterion for performing coding and modulation or a service and service component criterion.
  • data pipes DP
  • the data pipe is a logical channel of the physical layer and can carry service data or related metadata.
  • the data pipe may carry one or a plurality of services or one or a plurality of service components.
  • data transmitted through a data pipe may be referred to as DP data.
  • the input formatting module 1000 divides each generated data pipe into block units necessary for performing coding and modulation, and performs a series of processes necessary for improving transmission efficiency or scheduling. Can be done. Details will be described later.
  • the coding and modulation module 1100 performs forward error correction (FEC) encoding on each data pipe received from the input formatting module 1000 to receive an error that may occur in a transport channel. Make corrections in
  • the coding and modulation module 1100 according to an embodiment of the present invention can correct the burst error due to the channel by converting the FEC output bit data into symbol data and performing interleaving.
  • the coding and modulation module 1100 according to an embodiment of the present invention may process the processed data for each antenna output. You can output it by dividing it by (data path).
  • the frame structure module 1200 may map data output from the coding and modulation module 1100 to a signal frame.
  • the frame structure module 1200 according to an embodiment of the present invention may perform mapping by using the scheduling information output from the input formatting module 1000, and may obtain data in a signal frame to obtain additional diversity gain. Interleaving may be performed with respect to.
  • the waveform generation module 1300 may convert the signal frames output from the frame structure module 1200 into a signal that can be finally transmitted.
  • the waveform generation module 1300 according to an embodiment of the present invention inserts a preamble signal (or preamble) for detection of a transmission system, and estimates a transmission channel to compensate for distortion. You can insert a reference signal.
  • the waveform generation module 1300 according to an embodiment of the present invention has a guard interval in order to cancel an influence caused by a channel delay spread due to multipath reception, and a specific sequence in a corresponding section. (sequence) can be inserted.
  • the waveform generation module 1300 according to an embodiment of the present invention additionally performs a process required for efficient transmission in consideration of signal characteristics such as peak to average power ratio of the output signal. can do.
  • the signaling generation module 1400 may input input management information and information generated from the input formatting module 1000, the coding and modulation module 1100, and the frame structure module 1200. Final signaling information is generated using the physical layer signaling. Therefore, the reception apparatus according to an embodiment of the present invention can decode the received signal by decoding the signaling information.
  • the transmitter for the next generation broadcast service may provide a terrestrial broadcast service, a mobile broadcast service, and a UHDTV service. Therefore, the apparatus for transmitting a next-generation broadcast service according to an embodiment of the present invention may multiplex signals for different services in a time domain and transmit the same.
  • FIG. 2 to 4 illustrate an embodiment of the input formatting module 1000 according to an embodiment of the present invention described with reference to FIG. 1. Each figure is demonstrated below.
  • FIG. 2 illustrates an input formatting module according to an embodiment of the present invention. 2 illustrates an input formatting module when the input signal is a single input stream.
  • an input formatting module may include a mode adaptation module 2000 and a stream adaptation module 2100.
  • the mode adaptation module 2000 may include an input interface block 2010, a CRC-8 encoder block 2020, and a BB header insertion block 2030. Each block is briefly described below.
  • the input interface block 2010 may output the input single input stream by dividing the input single input stream by a baseband (BB) frame length unit for performing FEC (BCH / LDPC).
  • BB baseband
  • the CRC-8 encoder block 2020 may add redundancy data by performing CRC encoding on each BB frame data.
  • the BB header insertion block 2030 may include a mode adaptation type (TS / GS / IP), a user packet length, a data field length, User Packet Sync Byte, Start Address of User Packet Sync Byte in Data Field, High Efficiency Mode Indicator, Input Stream Synchronization Field ( A header including information such as an input stream synchronization field) may be inserted into a BB frame.
  • a mode adaptation type TS / GS / IP
  • a user packet length a data field length
  • User Packet Sync Byte Start Address of User Packet Sync Byte in Data Field
  • High Efficiency Mode Indicator High Efficiency Mode Indicator
  • Input Stream Synchronization Field A header including information such as an input stream synchronization field may be inserted into a BB frame.
  • the stream adaptation module 2100 may include a padding insertion block 2110 and a BB scrambler block 2120. Each block is briefly described below.
  • the padding insertion block 2110 outputs a padding bit to have a required input data length when the data input from the mode adaptation module 2000 is smaller than the input data length required for FEC encoding. can do.
  • the BB scrambler block 2120 may randomize the input bit stream by performing an XOR operation on a PRBS pseudo random binary sequence.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • the input formatting module may finally output the data pipe to the coding and modulation module.
  • FIG. 3 illustrates an input formatting module according to another embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a mode adaptation module of an input formatting module when the input signal is multiple input streams.
  • the mode adaptation module of the input formatting module for processing multiple input streams may process each input stream independently.
  • the mode adaptation module 3000 for processing multiple input streams respectively includes an input interface block, an input stream synchronizer block, a delay compensation block, and null packet cancellation. packet deletion) block, CRC-8 encoder block, and BB header insertion block. Each block is briefly described below.
  • the input stream synchronization block 3100 may transmit input stream clock reference information to insert timing information necessary for recovering a TS or GS stream at the receiving end.
  • the delay compensation block 3200 may output the delayed input data so that the receiving device can synchronize the data when a delay occurs between data pipes according to data processing of the transmitting device together with timing information generated by the input stream synchronization block. have.
  • the null packet removal block 3300 may remove an input null packet to be transmitted unnecessarily, and insert and transmit the number of removed null packets according to the removed position.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • FIG 4 illustrates an input formatting module according to another embodiment of the present invention.
  • FIG. 4 is a diagram illustrating a stream adaptation module of the input formatting module when the input signals are multiple input streams.
  • the stream adaptation module of the input formatting module may include a scheduler 4000, a 1-frame delay block 4100, in-band signaling or padding insertion. or padding insertion) block 4200, physical layer signaling generation block 4300, and BB scrambler block 4400. The operation of each block will be described below.
  • the scheduler 4000 may perform scheduling for a MIMO system using multiple antennas including dual polarity.
  • the scheduler 4000 may be configured in signal processing blocks for each antenna path such as a bit to cell demux block, a cell interleaver block, and a time interleaver block in the coding & modulation module described with reference to FIG. 1. It can generate parameters to be used.
  • the 1-frame delay block 4100 delays the input data by one transmission frame so that scheduling information for the next frame can be transmitted in the current frame, for example, in in-band signaling to be inserted into the data pipe. Can be.
  • In band signaling or padding insertion block 4200 provides for physical layer signaling (PLS) -dynamic signaling that is not delayed to data delayed by one transmission frame. Information can be inserted.
  • PLS physical layer signaling
  • the in-band signaling or padding insertion block 4200 may insert a padding bit or insert in-band signaling information into the padding space when there is space for padding.
  • the scheduler 4000 may output physical layer signaling-dynamic signaling information for the current frame separately from in-band signaling. Therefore, a cell mapper, which will be described later, may map input cells according to scheduling information output from the scheduler 4000.
  • the physical layer signaling generation block 4300 may generate physical layer signaling data to be transmitted in a preamble symbol or a spread symbol of a transmission frame, except for in-band signaling, to be transmitted to a data symbol.
  • the physical layer signaling data according to an embodiment of the present invention may be referred to as signaling information.
  • the physical layer signaling data according to an embodiment of the present invention may be separated into PLS-pre information and PLS-post information.
  • the PLS-free information may include parameters required for encoding PLS-post information and static PLS signaling data
  • the PLS-post information may include parameters required for encoding a data pipe. .
  • the parameters required to encode the above-described data pipe may be separated into static PLS signaling data and dynamic PLS signaling data.
  • the static PLS signaling data is a parameter that can be commonly applied to all frames included in the super frame and can be changed in units of super frames.
  • the dynamic PLS signaling data is a parameter that can be applied differently for each frame included in the super frame and can be changed in units of frames. Therefore, the receiving device can decode the PLS-free information to obtain PLS-post information, and decode the PLS-post information to decode the desired data pipe.
  • the BB scrambler block 4400 may generate a random binary sequence (PRBS) so that the PAPR value of the output signal of the waveform generation block may be lowered to perform an XOR with the input bit string. As shown in FIG. 4, scrambling of the BB scrambler block 4400 may be applied to both data pipes and physical layer signaling.
  • PRBS random binary sequence
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • the stream adaptation module may finally output each data pipe to a coding and modulation module.
  • FIG. 5 illustrates a coding and modulation module according to an embodiment of the present invention.
  • the coding and modulation module of FIG. 5 corresponds to an embodiment of the coding and modulation module 1100 described with reference to FIG. 1.
  • the transmitter for the next generation broadcast service may provide a terrestrial broadcast service, a mobile broadcast service, and a UHDTV service.
  • the coding and modulation module may independently process SISO, MISO, and MIMO schemes for each path for input data pipes.
  • the transmission apparatus for the next generation broadcast service may adjust QoS for each service or service component transmitted through each data pipe.
  • the coding and modulation module includes a first block 5000 for the SISO scheme, a second block 5100 for the MISO scheme, a third block 5200 for the MIMO scheme, and a PLS pre / A fourth block 5300 for processing the post information may be included.
  • the coding and modulation module illustrated in FIG. 5 is only an example, and according to a designer's intention, the coding and modulation module may include only the first block 5000 and the fourth block 5300, and the second block 5100. ) And only the fourth block 5300, or may include only the third block 5200 and the fourth block 5300. That is, according to the designer's intention, the coding and modulation module may include blocks for processing each data pipe identically or differently.
  • the first block 5000 is a block for SISO processing the input data pipe, the FEC encoder block 5010, the bit interleaver block 5020, the bit to cell demux block 5030, the constellation It may include a mapper block 5040, a cell interleaver block 5050, and a time interleaver block 5060.
  • the FEC encoder block 5010 may add redundancy by performing BCH encoding and LDPC encoding on the input data pipe, and correct an error on a transmission channel at a receiving end.
  • the bit interleaver block 5020 may interleave the bit string of the data on which the FEC encoding is performed by an interleaving rule so as to be robust to burst errors that may occur in the transport channel. Therefore, when deep fading or erasure is applied to a QAM symbol, since interleaved bits are mapped to each QAM symbol, errors occur in successive bits among all codeword bits. Can be prevented.
  • the bit-to-cell demux block 5030 takes into account both the order of the input bit stream and the constellation mapping rule, so that each bit in the FEC block can be transmitted with appropriate robustness. Can be determined and output.
  • the constellation mapper block 5040 may map the input bit word to one constellation.
  • the constellation mapper block may additionally perform rotation & Q delay. That is, the constellation mapper block may delay only the quadrature phase component to an arbitrary value after dividing the input constellations according to a rotation angle and then dividing the constellation into an in phase component and a quadrature phase component. The paired I and Q components can then be used to map back to the new constellation.
  • the cell interleaver block 5050 randomly mixes and outputs cells corresponding to one FEC block, and outputs cells corresponding to each FEC block in a different order for each FEC block.
  • the time interleaver block 5060 may mix and output cells belonging to several FEC blocks. Accordingly, since cells of each FEC block are distributed and transmitted within an interval corresponding to a time interleaving depth, diversity gain can be obtained.
  • the second block 5100 is a block for MISO processing the input data pipe.
  • the second block 5100 is a FEC encoder block, a bit interleaver block, and a bit to cell demux as in the first block 5000.
  • the second block 5100 may include a cell demux block, a constellation mapper block, a cell interleaver block, and a time interleaver block, there is a difference in that it further includes a MISO processing block 5110.
  • the second block 5100 performs the same role process from the input to the time interleaver, and thus description of the same blocks will be omitted.
  • the MISO processing block 5110 may encode an input series of cells according to an MISO encoding matrix giving transmit diversity and output MISO processed data through two paths.
  • MISO processing according to an embodiment of the present invention may include orthogonal space time block coding (OSTBC) / orthogonal space frequency block coding (AKA Alamouti coding).
  • OSTBC orthogonal space time block coding
  • AKA Alamouti coding orthogonal space frequency block coding
  • the third block 5200 is a block for MIMO processing the input data pipe.
  • the third block 5200 is an FEC encoder block, a bit interleaver block, a bit-to-cell demux block, and a constellation in the same manner as the second block 5100.
  • it may include a mapper block, a cell interleaver block, and a time interleaver block, there is a difference in data processing in that it includes a MIMO processing block 5220.
  • the FEC encoder block and the bit interleaver block have different specific functions from those of the first and second blocks 5000 and 5100, but have the same basic role.
  • the bit-to-cell demux block 5210 may generate an output bit string equal to the number of inputs of the MIMO processing and output the same through the MIMO path for the MIMO processing.
  • the bit-to-cell demux block 5210 may be designed to optimize decoding performance of the receiver in consideration of characteristics of LDPC and MIMO processing.
  • the constellation mapper block, the cell interleaver block, and the time interleaver block may have different specific functions, the basic role is the same as described in the first and second blocks 5000 and 5100.
  • the constellation mapper block, the cell interleaver block, and the time interleaver blocks have a number of MIMO paths for MIMO processing to process an output bit string output from the bit-to-cell demux block. As many as may exist.
  • the constellation mapper block, the cell interleaver block, and the time interleaver block may operate identically or independently with respect to data input through each path.
  • the MIMO processing block 5220 may perform MIMO processing on the input two input cells using the MIMO encoding matrix and output the MIMO processed data through two paths.
  • the MIMO encoding matrix may include spatial multiplexing, golden code, full rate full diversity code, linear dispersion code, and the like. It may include.
  • the fourth block 5300 is a block for processing PLS pre / post information, and may perform SISO or MISO processing.
  • the bit interleaver block, the bit to cell demux block, the constellation mapper block, the cell interleaver block, the interleaver block, and the MISO processing block included in the fourth block 5300 may be blocks included in the second block 5100 described above.
  • the specific functions may be different, but the basic role is the same.
  • the Shortened / punctured FEC encoder block 5310 included in the fourth block 5300 is used for the PLS path in case the length of the input data is shorter than the length required to perform FEC encoding.
  • the FEC encoding method can be used to process PLS data. Specifically, the Shortened / punctured FEC encoder block performs BCH encoding on the input bit stream, then zero padding the length of the input bit string necessary for normal LDPC encoding, and performs LDPC encoding. The pared bit can then be removed to puncture the parity bits so that the effective code rate is equal to or lower than the data pipe.
  • the blocks included in the first block 5000 to the fourth block 5300 described above may be omitted or replaced by other blocks having similar or identical functions according to a designer's intention.
  • the coding and modulation module may finally output data pipes, PLS-free information, and PLS-post information processed for each path to the frame structure module.
  • FIG. 6 is a diagram illustrating a frame structure module according to an embodiment of the present invention.
  • the frame structure module illustrated in FIG. 6 corresponds to an embodiment of the frame structure module 1200 described with reference to FIG. 1.
  • the frame structure block includes at least one cell-mapper 6000, at least one delay compensation module 6100 and at least one block interleaver ( 6200).
  • the number of cell mapper 6000, delay compensation module 6100, and block interleaver 6200 may be changed according to a designer's intention. Hereinafter, the operation of each module will be described.
  • the cell mapper 6000 includes cells corresponding to SISO or MISO or MIMO processed data pipes output from a coding and modulation module, cells corresponding to common data that can be commonly applied between data pipes, and PLS-free / Cells corresponding to the post information may be allocated to the signal frame according to the scheduling information.
  • the common data refers to signaling information that may be commonly applied between all or some of the data pipes, and may be transmitted through a specific data pipe.
  • the data pipes that carry common data can be called common data pipes, which can be changed according to the designer's intention.
  • the mapper 6000 may perform pair wise cell mapping. That is, the cell mapper 6000 may process two consecutive cells with respect to the input cells as one unit and map them to the frame. Therefore, paired cells in an input path corresponding to an output path of each antenna may be allocated to positions adjacent to each other in a transmission frame.
  • the delay compensation block 6100 may delay the input PLS data cell for the next transmission frame by one frame to obtain PLS data corresponding to the current transmission frame.
  • the PLS data of the current frame may be transmitted through the preamble part in the current signal frame, and the PLS data for the next signal frame may perform in-band signaling in each data pipe of the preamble part or the current signal frame in the current signal frame. Can be sent through. This can be changed according to the designer's intention.
  • the block interleaver 6200 can obtain additional diversity gain by interleaving cells in a transmission block that is a unit of a signal frame.
  • the block interleaver 6200 may perform interleaving by processing two consecutive cells with respect to input cells as one unit. Accordingly, the cells output from the block interleaver 6200 may be the same two consecutive cells.
  • At least one cell mapper and at least one block interleaver operate equally with respect to data input through respective paths. Can be run independently or independently.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • FIG. 7 illustrates a waveform generation module according to an embodiment of the present invention.
  • the waveform generation module illustrated in FIG. 7 corresponds to an embodiment of the waveform generation module 1300 described with reference to FIG. 1.
  • the waveform generation module may modulate and transmit signal frames as many as the number of antennas for receiving and outputting signal frames output from the frame structure module described with reference to FIG. 6.
  • the waveform generation module illustrated in FIG. 7 is an embodiment of the waveform generation module of a transmission apparatus using m Tx antennas, and includes m processes for modulating and outputting frames input by m paths. It may include blocks. The m processing blocks may all perform the same processing. Hereinafter, the operation of the first processing block 7000 of the m processing blocks will be described.
  • the first processing block 7000 includes a reference signal insertion & PAPR reduction block 7100, an inverse waveform transform block 7200, and a PAPR reduction in time.
  • Block 7300 Guard Sequence Insertion Block 7400, Preamble Insertion Block 7500, Waveform Processing Block 7600, Other System Insertion Block 7700 and a digital analog converter (DAC) block 7800.
  • DAC digital analog converter
  • the reference signal insertion & PAPR reduction block 7100 inserts reference signals at a predetermined position for each signal block and applies a PAPR reduction scheme to lower the PAPR value in the time domain.
  • the broadcast transmission / reception system according to the embodiment of the present invention is an OFDM system
  • the reference signal insertion & PAPR reduction block 7100 may use a method of preserving without using a portion of an active subcarrier.
  • the reference signal insertion & PAPR reduction block 7100 may not use the PAPR reduction scheme as an optional feature according to a broadcast transmission / reception system.
  • the inverse waveform conversion block 7200 may convert and output the input signal in a manner of improving transmission efficiency and flexibility in consideration of the characteristics of the transmission channel and the system structure.
  • the broadcast transmission / reception system according to an embodiment of the present invention is an OFDM system
  • the inverse waveform transform block 7200 may use a method of converting a signal in a frequency domain into a time domain using an inverse FFT operation. have.
  • the broadcast transmission / reception system according to an embodiment of the present invention is a single carrier system, the inverse waveform transform block may not be used in the waveform generation module.
  • the PAPR reduction in time block 7300 may apply a method for lowering PAPR in the time domain with respect to the input signal.
  • the PAPR reduction in time block 7300 may simply use a method of clipping peak amplitude.
  • the PAPR reduction in time block 7300 is an optional feature and may not be used according to the broadcast transmission / reception system according to an embodiment of the present invention.
  • the guard sequence insertion block 7400 may put a guard interval between adjacent signal blocks and insert a specific sequence if necessary in order to minimize the influence of the delay spread of the transport channel. Therefore, the receiving device can easily perform synchronization or channel estimation.
  • the guard sequence insertion block 7400 may insert a cyclic prefix into the guard interval section of the OFDM symbol.
  • the preamble insertion block 7500 transmits a known type of signal (preamble or preamble symbol) between the transmitting and receiving devices so that the receiving device can quickly and efficiently detect a target system signal. Can be inserted into the signal.
  • the preamble insertion block 7500 may define a signal frame composed of several OFDM symbols and insert a preamble at the beginning of every signal frame. That is, the preamble may carry basic PLS data, and the preamble may be located at the beginning of the frame.
  • the waveform processing block 7600 may perform waveform processing on the input baseband signal to match the transmission characteristics of the channel.
  • the waveform processing block 7600 may use a method of performing square root raised cosine (SRRC) filtering to obtain a reference for out of band emission of a transmission signal as an embodiment.
  • SRRC square root raised cosine
  • the waveform processing block 7600 may not be used.
  • the other system insertion block 7700 may multiplex signals of a plurality of broadcast transmission / reception systems in a time domain so that data of a broadcast transmission / reception system providing two or more different broadcast services within the same RF signal bandwidth may be transmitted together.
  • two or more different systems refer to a system for transmitting different broadcast services.
  • Different broadcast services may refer to terrestrial broadcast services or mobile broadcast services.
  • data related to each broadcast service may be transmitted through different frames.
  • the digital analog converter block 7800 may convert an input digital signal into an analog signal and output the analog signal.
  • the signal output from the digital analog converter block 7800 may be transmitted through m output antennas.
  • a transmission antenna according to an embodiment of the present invention may have vertical or horizontal polarity.
  • FIG. 8 is a diagram illustrating a structure of a reception device for a next generation broadcast service according to an embodiment of the present invention.
  • the reception device for the next generation broadcast service may correspond to the transmission device for the next generation broadcast service described with reference to FIG. 1.
  • a reception apparatus for a next generation broadcast service according to an embodiment of the present invention includes a synchronization & demodulation module 8000, a frame parsing module 8100, a demapping & decoding module 8200, and an output. It may include a processor 8300 and a signaling decoding module 8400. Hereinafter, the operation of each module will be described.
  • the synchronization & demodulation module 8000 receives an input signal through m reception antennas, performs signal detection and synchronization on a system corresponding to the reception device, and performs the transmission at the transmitting end. Demodulation corresponding to the inverse process can be performed.
  • the frame parsing module 8100 may parse the input signal frame and extract data for transmitting a service selected by the user. If the frame parsing module 8100 performs interleaving in the transmitting apparatus, the frame parsing module 8100 may perform deinterleaving as a reverse process. In this case, the position of the signal and data to be extracted may be obtained by decoding the data output from the signaling decoding module 8400 and restoring scheduling information performed by the transmitting apparatus.
  • the demapping & decoding module 8200 can perform the deinterleaving process if necessary after converting the input signal into bit domain data.
  • the demapping & decoding module 8200 can demap the mapping applied for transmission efficiency and perform error correction through decoding on an error generated during the transport channel.
  • the demapping & decoding module 8200 can decode the data output from the signaling decoding module 8400 to obtain transmission parameters necessary for demapping and decoding.
  • the output processor 8300 may perform a reverse process of various compression / signal processing processes applied by the transmitter to increase transmission efficiency.
  • the output processor 8300 may obtain necessary control information from data output from the signaling decoding module 8400.
  • the final output of the output processor 8300 corresponds to a signal input to the transmitting device, and may be MPEG-TS, IP stream (v4 or v6), and generic stream.
  • the signaling decoding module 8400 can obtain PLS information from the demodulated signal. As described above, the frame parsing module 8100, the demapping & decoding module 8200, and the output processor 8300 may perform functions of the corresponding module by using data output from the signaling decoding module 8400. .
  • FIG. 9 is a diagram illustrating a synchronization & demodulation module according to an embodiment of the present invention.
  • the synchronization & demodulation module illustrated in FIG. 9 corresponds to an embodiment of the synchronization & demodulation module described with reference to FIG. 8.
  • the synchronization & demodulation module illustrated in FIG. 9 may perform a reverse operation of the waveform generation module described with reference to FIG. 7.
  • the synchronization & demodulation module is an embodiment of the synchronization & demodulation module of a receiving apparatus using m Rx antennas, and receives signals input by m paths. It may include m processing blocks for demodulation and output. The m processing blocks may all perform the same processing. Hereinafter, the operation of the first processing block 9000 among the m processing blocks will be described.
  • the first processing block 9000 includes a tuner 9100, an analog to digital converter (ADC) block 9200, a preamble detector 9300, a guard sequence detector 9400, a waveform transform. transmform block 9500, time / freq sync block 9600, reference signal detector 9700, channel equalizer 9800, and inverse waveform transform waveform transform) block 9900.
  • ADC analog to digital converter
  • the tuner 9100 selects a desired frequency band and compensates the magnitude of the received signal and outputs the signal to the analog-to-digital converter (ADC) block 9200.
  • ADC analog-to-digital converter
  • the analog-to-digital converter (ADC) block 9200 may convert a signal output from the tuner 9100 into a digital signal.
  • the preamble detector 9300 may detect a preamble (or a preamble signal or a preamble symbol) to determine whether the digital signal is a signal of a system corresponding to the receiving device. In this case, the preamble detector 9300 may decode basic transmission parameters received through the preamble.
  • the guard sequence detector 9400 can detect the guard sequence in the digital signal.
  • the time / frequency synchronization block 9600 can perform time / frequency synchronization using the detected guard sequence, and the channel equalizer 9800 uses the detected guard sequence to channel through the received / restored sequences. It can be estimated.
  • the waveform transform block 9500 may perform an inverse transform process when an inverse waveform transform is performed at the transmitter.
  • the waveform side block 9500 may perform an FFT conversion process.
  • the broadcast transmission / reception system according to an embodiment of the present invention is a single carrier system, when a received time domain signal is used to process in the frequency domain or is processed in the time domain, the waveform The side block 9500 may not be used.
  • the time / frequency synchronization block 9600 receives output data of the preamble detector 9300, the guard sequence detector 9400, and the reference signal detector 9700, and provides guard sequence detection and block for the detected signal. Carrier frequency synchronization and time synchronization may be performed including block window positioning. In this case, the time / frequency synchronization block 9600 may feed back the output signal of the waveform side block 9500 for frequency synchronization.
  • the reference signal detector 9700 may detect the received reference signal. Accordingly, the reception device according to an embodiment of the present invention may perform synchronization or channel estimation.
  • the channel equalizer 9800 may estimate a transmission channel from each transmission antenna to each reception antenna from a guard sequence or reference signal, and perform channel compensation on each received data using the estimated channel.
  • the inverse waveform transform block 9900 restores the original waveform to the original received data area when the waveform transform block 9500 performs waveform conversion in order to efficiently perform synchronization and channel estimation / compensation. Can be.
  • the waveform conversion block 9500 may perform an FFT to perform synchronization / channel estimation / compensation in the frequency domain, and inverse waveform conversion Block 9900 may recover the transmitted data symbols by performing IFFT on the signal for which channel compensation is completed.
  • the broadcast transmission / reception system according to an embodiment of the present invention is a multicarrier system, the inverse waveform conversion block 9900 may not be used.
  • FIG. 10 illustrates a frame parsing module according to an embodiment of the present invention.
  • the frame parsing module illustrated in FIG. 10 corresponds to an embodiment of the frame parsing module described with reference to FIG. 8.
  • the frame parsing module illustrated in FIG. 10 may perform a reverse operation of the frame structure module described with reference to FIG. 6.
  • the frame parsing module may include at least one block deinterleaver 10000 and at least one cell demapper 10100.
  • the block deinterleaver 10000 may perform deinterleaving on data in units of signal blocks for data input to each data path of m reception antennas and processed by the synchronization & demodulation module. In this case, as described with reference to FIG. 8, when pair wise interleaving is performed at the transmitting side, the block deinterleaver 10000 performs a pair of two consecutive data for each input path. Can be processed as a pair. Accordingly, the block deinterleaver 10000 may output two consecutive output data even when deinterleaving is performed. In addition, the block deinterleaver 10000 may perform an inverse process of the interleaving process performed by the transmitter to output the original data in order.
  • the cell demapper 10100 may extract cells corresponding to common data, cells corresponding to a data pipe, and cells corresponding to PLS data from the received signal frame. If necessary, the cell demapper 10100 may output data in one stream by merging the data transmitted by being distributed into several parts. In addition, as described in FIG. 6, when two consecutive cell input data are processed and mapped as a pair at the transmitting end, the cell demapper 10100 processes two consecutive input cells as one unit in a reverse process corresponding thereto. Pair wise cell demapping may be performed.
  • the cell demapper 10100 may extract and output both PLS signaling data received through the current frame as PLS-free & PLS-post data, respectively.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • FIG. 11 illustrates a demapping & decoding module according to an embodiment of the present invention.
  • the demapping & decoding module illustrated in FIG. 11 corresponds to an embodiment of the demapping & decoding module described with reference to FIG. 8.
  • the demapping & decoding module illustrated in FIG. 11 may perform a reverse operation of the coding and modulation module described with reference to FIG. 5.
  • the coding and modulation module of the transmitting apparatus may independently apply and process SISO, MISO and MIMO schemes for each path to input data pipes. Accordingly, the demapping & decoding module illustrated in FIG. 11 may also include blocks for SISO, MISO, and MIMO processing of data output from the frame parser in response to the transmitting apparatus.
  • the demapping & decoding module includes a first block 11000 for the SISO scheme, a second block 11100 for the MISO scheme, and a third for the MIMO scheme.
  • a block 11200 and a fourth block 11300 for processing PLS pre / post information may be included.
  • the demapping & decoding module shown in FIG. 11 is only an embodiment, and according to the designer's intention, the demapping & decoding module may include only the first block 11000 and the fourth block 11300, and the second block. Only the first block 11100 and the fourth block 11300 may be included, or only the third block 11200 and the fourth block 11300 may be included. That is, according to the designer's intention, the demapping & decoding module can include blocks for processing each data pipe identically or differently.
  • the first block 11000 is a block for SISO processing the input data pipe, and includes a time deinterleaver block 11010, a cell deinterleaver block 11020, and a constellation demapper.
  • the block 11030, a cell to bit mux block 11040, a bit deinterleaver block 1050, and an FEC decoder block 11060 may be included.
  • the time deinterleaver block 11010 may perform a reverse process of the time interleaver block 5060 described with reference to FIG. 5. That is, the time deinterleaver block 11010 may deinterleave the interleaved input symbols to their original positions in the time domain.
  • the cell deinterleaver block 11020 may perform a reverse process of the cell interleaver block 5050 described with reference to FIG. 5. That is, the cell deinterleaver block 11020 may deinterleave the positions of cells spread within one FEC block to the original positions.
  • the constellation demapper block 11030 may perform a reverse process of the constellation mapper block 5040 described with reference to FIG. 5. That is, the constellation demapper block 11030 may demap an input signal of a symbol domain into data of a bit domain. Also, the constellation demapper block 11030 may perform hard decision to output the decited bit data, and each bit corresponding to a soft decision value or a probabilistic value. The LLR (Log likelihood ratio) can be output. If a constellation rotation is applied to obtain additional diversity gain at the transmitter, the constellation demapper block 11030 may perform corresponding two-dimensional LLR demapping. In this case, when the LLR is calculated, the constellation demapper block 11030 may perform calculation to compensate for the delay value performed on the I or Q component in the transmitting apparatus.
  • LLR Log likelihood ratio
  • the cell to bit mux block 11040 may perform a reverse process of the bit to cell demux block 5030 described with reference to FIG. 5. That is, the cell to bit mux block 11040 may restore the bit data mapped in the bit to cell demux block 5030 to the original bit stream form.
  • the bit deinterleaver block 11050 may perform a reverse process of the bit interleaver block 5020 described with reference to FIG. 5. That is, the bit deinterleaver block 11050 may deinterleave the bit stream output from the cell-to-bit mux block 11040 in the original order.
  • the FEC decoder block 11060 may perform an inverse process of the FEC encoder block 5010 described with reference to FIG. 5. That is, the FEC decoder block 11060 may correct an error generated on a transport channel by performing LDPC decoding and BCH decoding.
  • the second block 11100 is a block for MISO processing the input data pipe, and the time deinterleaver block, the cell deinterleaver block, and the constellation demapper block are the same as the first block 11000 as shown in FIG. 11. , But may include a cell-to-bit mux block, a bit deinterleaver block, and an FEC decoder block, except that the MISO decoding block 1110 is further included. Like the first block 11000, the second block 11100 performs the same role from the time deinterleaver to the output, and thus description of the same blocks will be omitted.
  • the MISO decoding block 11110 may perform an inverse process of the MISO processing block 5110 described with reference to FIG. 5.
  • the MISO decoding block 11110 may perform Alamouti decoding.
  • the third block 11200 is a block for MIMO processing the input data pipe, and as shown in FIG. 11, the time deinterleaver block, the cell deinterleaver block, and the constellation demapper block are the same as the second block 11100. It may include a cell-to-bit mux block, a bit deinterleaver block, and an FEC decoder block, but there is a difference in data processing in that it includes a MIMO decoding block 1112.
  • the operations of the time deinterleaver, the cell deinterleaver, the constellation demapper, the cell-to-bit mux, and the bit deinterleaver blocks included in the third block 11200 may be performed in the corresponding blocks included in the first to second blocks 11000-11100. Their operation and specific function may be different, but the basic role is the same.
  • the MIMO decoding block 1112 may receive output data of the cell deinterleaver for m reception antenna input signals, and perform MIMO decoding as a reverse process of the MIMO processing block 5220 described with reference to FIG. 5.
  • the MIMO decoding block 1210 may perform maximum likelihood decoding, or perform sphere decoding with reduced complexity, in order to obtain the best decoding performance.
  • the MIMO decoding block 1112 may perform MMSE detection or combine iterative decoding together to secure improved decoding performance.
  • the fourth block 11300 is a block for processing PLS pre / post information and may perform SISO or MISO decoding.
  • the fourth block 11300 may perform a reverse process of the fourth block 5300 described with reference to FIG. 5.
  • the operations of the time deinterleaver, the cell deinterleaver, the constellation demapper, the cell-to-bit mux, and the bit deinterleaver blocks included in the fourth block 11300 may be performed in the corresponding blocks included in the first to third blocks 11000-11200. Their operation and specific function may be different, but the basic role is the same.
  • the Shortened / Punctured FEC decoder 11310 included in the fourth block 11300 may perform the reverse process of the Shortened / punctured FEC encoder block 5310 described with reference to FIG. 5. have. That is, the Shortened / Punctured FEC decoder 11310 is shortened / punctured according to the length of the PLS data to perform de-shortening and de-puncturing on the received data. After that, FEC decoding may be performed. In this case, since the FEC decoder used for the data pipe can be used for the PLS in the same way, since there is no need for a separate FEC decoder hardware for the PLS, there is an advantage in that system design is easy and efficient coding is possible.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • the demapping & decoding module can output data pipes and PLS information processed for each path to an output processor.
  • FIG 12 illustrates an output processor according to an embodiment of the present invention.
  • the output processor illustrated in FIG. 12 corresponds to an embodiment of the output processor described with reference to FIG. 8.
  • the output processor illustrated in FIG. 12 receives a single data pipe output from the demapping & decoding module to output a single output stream, and can perform a reverse operation of the input formatting module described with reference to FIG. 2.
  • the output processor illustrated in FIG. 12 may include a BB scrambler block 12000, a padding removal block 12100, a CRC-8 decoder block 12200, and a BB frame processor block 12300.
  • the BB scrambler block 12000 may generate the same PRBS as used in the transmitter for the input bit stream, and perform descrambling by XORing the bit string.
  • the padding removal block 12100 may remove the padding bit inserted in the transmitter.
  • the CRC-8 decoder block 12200 may check a block error by performing CRC decoding on the bit stream received from the padding removal block 12100.
  • the BB frame processor block 12300 may decode the information transmitted in the BB frame header and restore the MPEG-TS, the IP stream (v4 or v6) or the generic stream using the decoded information.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • FIG 13 illustrates an output processor according to another embodiment of the present invention.
  • the output processor illustrated in FIG. 13 corresponds to an embodiment of the output processor described with reference to FIG. 8.
  • the output processor illustrated in FIG. 13 corresponds to a case of receiving multiple data pipes output from the demapping & decoding module. Decoding for multiple data pipes is performed when the common data that can be commonly applied to multiple data pipes and their associated data pipes are decoded, or when the receiving device has multiple services or service components (scalable video services). service)) may be simultaneously decoded.
  • the output processor illustrated in FIG. 13 may include a BB descrambler block, a padding removal block, a CRC-8 decoder block, and a BB frame processor block as in the output processor described with reference to FIG. 12.
  • the operation of the blocks and the specific operation may be different, but the basic role is the same.
  • the de-jitter buffer block 13000 included in the output processor illustrated in FIG. 13 recovers delays arbitrarily inserted at a transmitter for synchronization between multiple data pipes. You can compensate according to the parameters.
  • null packet insertion block 13100 may restore the null packet removed in the stream by referring to the recovered null packet (DNP) information and output common data.
  • DNP recovered null packet
  • the TS clock regeneration block 13200 may restore the detailed time synchronization of the output packet based on the input stream time reference (ISCR) information.
  • ISCR input stream time reference
  • the TS recombining block 13300 recombines the common data and the associated data pipes output from the null packet insertion block 13100 to reconstruct the original MPEG-TS, IP stream (v4 or v6) or generic stream. It can be restored to (Generic stream) and printed. TTO, DNP, and ISCR information may all be obtained through a BB frame header.
  • the in-band signaling decoder block 13400 may restore and output in-band physical layer signaling information transmitted through a padding bit field in each FEC frame of the data pipe.
  • the output processor shown in FIG. 13 descrambles the PLS-free information and the PLS-post information input according to the PLS-free path and PLS-post path, respectively, and decodes the descrambled data. You can restore the original PLS data by doing
  • the recovered PLS data is delivered to a system controller in the receiving device, and the system controller can supply the necessary parameters to the synchronization & demodulation module, the frame parsing module, the demapping & decoding module, and the output processor module of the receiving device.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • FIG. 14 illustrates a coding and modulation module according to another embodiment of the present invention.
  • the coding and modulation module illustrated in FIG. 14 corresponds to another embodiment of the coding and modulation module described with reference to FIGS. 1 and 5.
  • the module in order to adjust QoS for each service or service component transmitted through each data pipe, the module includes a first block 14000 for an SISO scheme and an MISO scheme. It may include a second block 14100 for, a third block 14200 for MIMO scheme, and a fourth block 14300 for processing PLS pre / post information.
  • the coding and modulation module according to an embodiment of the present invention may include blocks for processing the same or different data pipes according to the designer's intention as described above.
  • the first to fourth blocks 14000-14300 illustrated in FIG. 14 include blocks that are substantially the same as the first to fourth blocks 5000-5300 described with reference to FIG. 5.
  • the function of the constellation mapper block 14010 included in the first to third blocks 14000-14200 is the constellation mapper block included in the first to third blocks 5000-5200 of FIG. 5.
  • a rotation & I / Q interleaver block 1420 is included between the cell interleaver and the time interleaver of the first to fourth blocks 14000-14300.
  • the configuration of the third block 14200 for the point and the MIMO scheme is different in that the configuration of the third block 5200 for the MIMO scheme shown in FIG. 5 is different.
  • a description of the same blocks as in FIG. 5 will be omitted and the description will be given based on the above-described differences.
  • the constellation mapper block 14010 illustrated in FIG. 14 may map an input bit word into a complex symbol. However, unlike the constellation mapper block 5040 illustrated in FIG. 5, constellation rotation may not be performed.
  • the constellation mapper block 14010 illustrated in FIG. 14 may be commonly applied to the first to third blocks 14000-14200 as described above.
  • the rotation & I / Q interleaver block 1420 may independently interleave the in phase and quadrature phase components of each complex symbol of the cell interleaved data output from the cell interleaver and output them in symbol units.
  • the number of input data and output symbols of the rotation & I / Q interleaver block 14020 is two or more, which can be changed according to the designer's intention.
  • the rotation & I / Q interleaver block 1420 may not interleave the in phase component.
  • the rotation & I / Q interleaver block 1420 may be commonly applied to the first to fourth blocks 14000-14300 as described above. In this case, whether the rotation & I / Q interleaver block 1420 is applied to the fourth block 14300 for processing PLS pre / post information may be signaled through the above-described preamble.
  • the third block 14200 for the MIMO scheme may include a Q block interleaver block 14210 and a complex symbol generator block 1422.
  • the Q block interleaver block 14210 may perform permutation on the parity part of the FEC block on which the FEC encoding received from the FEC encoder is performed. Through this, the parity part of the LDPC H matrix can be made into a cyclic structure in the same manner as the information part.
  • the Q block interleaver block 14210 permutates the order of output bit blocks having a Q size of the LDPC H matrix, and then performs a row-column block interleaving to generate a final bit string. Can be output.
  • the complex symbol generator block 1422 may receive the bit streams output from the Q block interleaver block 14210, and map the bit strings to complex symbols. In this case, the complex symbol generator block 1422 may output symbols through at least two paths. This can be changed according to the designer's intention.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • the coding and modulation module may output data pipes, PLS-free information, and PLS-post information processed for each path to the frame structure module. have.
  • FIG. 15 illustrates a demapping & decoding module according to another embodiment of the present invention.
  • the demapping & decoding module illustrated in FIG. 15 corresponds to another embodiment of the demapping & decoding module described with reference to FIGS. 8 and 11.
  • the demapping & decoding module illustrated in FIG. 15 may perform a reverse operation of the coding and modulation module described with reference to FIG. 14.
  • the demapping & decoding module includes a first block 15000 for the SISO method, a second block 15100 for the MISO method, and a third for the MIMO method.
  • a block 15200 and a fourth block 15300 for processing PLS pre / post information may be included.
  • the demapping & decoding module according to an embodiment of the present invention may include blocks for processing the same or different data pipes according to the designer's intention as described above.
  • the first to fourth blocks 15000-15300 illustrated in FIG. 15 include blocks that are substantially the same as the first to fourth blocks 11000-11300 described with reference to FIG. 11.
  • an I / Q deinterleaver & derotation block 15010 is included between the time deinterleaver and the cell deinterleaver of the first to fourth blocks 15000-15300.
  • the constellation mapper block 11030 included in the first to third blocks 11000-11200 of FIG. 11 has the function of the constellation demapper block 15020 included in the first to third blocks 15000-15200.
  • the configuration of the third block 15200 for the MIMO scheme differs in the configuration of the third block 11200 for the MIMO scheme illustrated in FIG. 11.
  • the description of the same blocks as in FIG. 11 will be omitted and the description will be given based on the above-described differences.
  • the I / Q deinterleaver & derotation block 15010 may perform a reverse process of the rotation & I / Q interleaver block 1140 described with reference to FIG. 14. That is, the I / Q deinterleaver & derotation block 15010 may deinterleave the I and Q components transmitted by I / Q interleaving at the transmitting end, respectively, and perform complex symbol having the reconstructed I / Q component. You can derotate and output it again.
  • the I / Q deinterleaver & derotation block 15010 may be commonly applied to the first to fourth blocks 15000-15300 as described above. In this case, whether the I / Q deinterleaver & derotation block 15010 is applied to the fourth block 15300 for processing the PLS pre / post information may be signaled through the above-described preamble.
  • the constellation demapper block 15020 may perform a reverse process of the constellation mapper block 14010 described with reference to FIG. 14. That is, the constellation demapper block 15020 may perform demapping on cell deinterleaved data without performing derotation.
  • the third block 15200 for the MIMO scheme may include a complex symbol parsing block 15210 and a Q block deinterleaver block 15220. .
  • the complex symbol parsing block 15210 may perform a reverse process of the complex symbol generator block 1422 described with reference to FIG. 14. In other words, the complex data symbol may be parsed, demapping into bit data, and output. In this case, the complex symbol parsing block 15210 may receive complex data symbols through at least two paths.
  • the Q block deinterleaver block 15220 may perform a reverse process of the Q block interleaver block 14210 described with reference to FIG. 14. That is, the Q block deinterleaver block 15220 restores the Q size blocks by row-column deinterleaving, restores the order of each permutated block in the original order, and then parity deinterleaving. Through the parity bits (parity bits) can be restored to the original position and output.
  • the aforementioned blocks may be omitted or replaced by other blocks having similar or identical functions according to the designer's intention.
  • the demapping & decoding module may output data pipes and PLS information processed for each path to an output processor.
  • the above-described cell interleaver and cell deinterleaver may be omitted according to an embodiment.
  • the block corresponding to the cell interleaver / cell deinterleaver may be omitted or replaced by another block having the same / similar operation.
  • cell interleaving / cell deinterleaving may be performed in other blocks that are not independent. That is, cell interleaving / cell deinterleaving may be performed together in separate blocks.
  • the interleaving method used for the cell interleaving / cell deinterleaving described above may be used for another interleaving object.
  • the Q delay and the I delay may be omitted in some embodiments.
  • the blocks corresponding to the Q delay and the I delay may be omitted or replaced by another block having the same / similar operation.
  • the Q delay and the I delay may be performed in other blocks that are not independent. That is, the operations of the Q delay and the I delay may be performed together in separate blocks.
  • FIG. 16 illustrates a coding & modulation module including a new rotation & I / Q interleaver block according to an embodiment of the present invention.
  • the present invention proposes block by block I / Q interleaving and deinterleaving.
  • Block by block I / Q interleaving and deinterleaving may be interleaving and deinterleaving applying different interleaving patterns to every FEC block.
  • different interleaving patterns may have the same property.
  • Block-by-block I / Q interleaving and deinterleaving can improve signal space diversity (SSD) performance.
  • SSD signal space diversity
  • Block by block I / Q interleaving and deinterleaving may be performed in the coding and modulation module described above. Specifically, the block by block I / Q interleaving and deinterleaving is performed by a new rotation & I / Q interleaver block corresponding to the above-described rotation & I / Q interleaver block 14020 and I / Q deinterleaver & derotation block 15010. And I / Q deinterleaver & derotation block.
  • the new rotation & I / Q interleaver block may be positioned between the cell interleaver and the time interleaver described above.
  • another embodiment of the present invention according to the case where the cell interleaver is omitted may include a new rotation & I / Q interleaver block after the constellation mapper.
  • another embodiment of the present invention according to the case where the cell interleaver is omitted may include a new rotation & I / Q interleaver block after MIMO encoding.
  • the new rotation & I / Q interleaver block can perform constellation rotation and block by block I / Q interleaving.
  • Block by block I / Q interleaving may independently interleave the real component (I component, In phase component) and imaginary component (Q component, Quad component phase) of the complex symbol.
  • the real component may not be interleaved.
  • the number of input and output symbols of the new rotation & I / Q interleaver block can be two, three, four or more.
  • the operation of the new rotation & I / Q interleaver block may not be performed in a separate block or may be performed in another block.
  • the operation of the new rotation & I / Q interleaver block may be performed in the time interleaver.
  • the new rotation & I / Q interleaver block can be omitted or replaced by another block with the same or similar functionality.
  • block by block I / Q interleaving and deinterleaving may be omitted or may be performed on other blocks.
  • block by block I / Q interleaving may be performed in the time interleaver.
  • FIG. 17 illustrates a block by block I / Q interleaver according to an embodiment of the present invention.
  • the block by block I / Q interleaver may mean a block that performs block by block I / Q interleaving. As described above, block by block I / Q interleaving may be included in a new rotation & I / Q interleaver block.
  • the block by block I / Q interleaver may include a Q1 / Q2 delay and / or a block by block relative prime interleaver (block by block RPI).
  • the Block by Block Reactive Prime Interleaver may be referred to as Block by Block RPI or RPI.
  • the Q1 / Q2 delay divides the complex symbol into a real component (In phase component) and a imaginary component (component), and may delay only the imaginary component.
  • the number of delays may be determined according to whether 2D SSD (2-Dimensional Signal Space Diversity) or 4D SSD (4-Dimensional Signal Diversity) is performed. When the 2D SSD is performed, the delay may be 1 cell. When the 4D SSD is performed, the delay may be 2 cells.
  • the RPI can interleave real and imaginary components.
  • the real component may not be interleaved.
  • RPI may have periodicity.
  • RPI can linearly write the output signal of the Q1 / Q2 delay into memory.
  • the RPI can periodically read a signal written to the memory.
  • the interleaving pattern may be different for every FEC block. However, each interleaving pattern may have the same property.
  • the period applied during the read operation may be determined depending on which of the 2D SSD and the 4D SSD is performed. When the 2D SSD is performed, the period may be two. When the 4D SSD is performed, the period may be four.
  • the writing process may be called interleaving in a broad sense in some cases.
  • the interleaving pattern may be referred to as an interleaving seed.
  • Different interleaving seeds may be from one mother interleaving seed.
  • the interleaving seed may be referred to as the sub interleaving seed of the mother interleaving seed.
  • the present invention proposes an RPI method as a method for creating a single mother interleaving seed, and then a method for creating a sub interleaving seed.
  • RPI method proposes an RPI method as a method for creating a single mother interleaving seed, and then a method for creating a sub interleaving seed.
  • the RPI can be used as a mother interleaver, and the initial offset value of the RPI can be changed for each block.
  • the use of single memory may vary depending on how the initial offset value of the RPI is generated.
  • the size of the memory and the number of input cells may be assumed to be N.
  • the Q component can be delayed by one cell through the Q1 delay. That is, the Q1 delay can delay only the imaginary component (Q component) by one cell while leaving the real component (I component) intact. Since the Q1 delay performs cyclic shifting, the N-1 th Q component may be paired with the first 0 th I component. The output signal of the Q1 delay can be input to the RPI.
  • the size of the memory and the number of input cells may be assumed to be N.
  • the Q component can be delayed by two cells through the Q2 delay. That is, the Q2 delay can delay only the imaginary component (Q component) by two cells while leaving the real component (I component) as it is. Since the Q2 delay performs cyclic shifting, the N-2 and N-1th Q components may be paired with the first 0 and 1st I components.
  • the output signal of the Q2 delay can be input to the RPI.
  • New I component and Q component pairs generated by delaying Q components by one or two cells may be new cells. These new cells can be named x 0, j , x 1, j , x 2, j , ... x N-1, j .
  • x k, j may mean the k-th cell of the j-th FEC block.
  • FIG. 19 illustrates a writing process of an RPI according to an embodiment of the present invention.
  • This figure shows an embodiment of a write process of the RPI in the case of applying the 2D SSD technology.
  • the writing process of the RPI may be operated similarly to the case of applying the 2D SSD technology.
  • the input FEC block may be an output signal of the Q1 / Q2 delay described above.
  • Total number of FEC block can be represented by N FEC_NUM, the number of cells constituting one FEC block may be represented by N Cell_NUM.
  • D SSD may mean a relative prime.
  • the D SSD may mean a dimension of the SSD.
  • V Cell_NUM may refer to the number of virtual cells in one FEC block.
  • V Cell_NUM may be determined in consideration of SSD dimensions.
  • the relative prime value and the N Cell_NUM may not have a mutual relationship. If the two do not have a mutual relationship, the normal operation of the RPI may be impossible.
  • the RPI may operate using V Cell_NUM instead of N Cell_NUM in an operation process.
  • V Cell_NUM When operating using V Cell_NUM , the receiver requires additional memory as much as (D SSD -1), but the amount of additional memory increase is negligible.
  • D SSD -1 the amount of additional memory increase is negligible.
  • V Cell_NUM 9.
  • V Cell_NUM 11.
  • FIG. 4B a virtual memory value, is indicated. This is to facilitate the description of the RPI operation using V Cell_NUM and is not considered in the actual write operation.
  • FIG. 20 is a view illustrating a reading process of an RPI according to an embodiment of the present invention.
  • (A) of the figure shows a memory index generated using the RPI algorithm to perform a read process for every FEC block.
  • This memory index may be referred to as an output memory index or an output memory index.
  • the zeroth initial offset value may be determined as zero.
  • the last output memory index value of the RPI applied to every FEC block may be set to the initial offset value of the RPI applied to the next FEC block. For example, since the last output memory index value of the # 0 FEC block is 7, the 0th output memory index value of the next # 1 FEC block may also be 7.
  • a unit corresponding to each FEC block number may be referred to as a sub RPI.
  • (B) of this figure may be a result of the RPI performing a read process using the memory index generated in (a).
  • x 2,0 may be at index 2 and x 4,0 at index 4. In this way, if the RPI performs the reading process, the maximum spreading value can be 4.
  • the RPI may perform a skip operation. That is, when the index exceeds 7 (in this case, the index is 8), the corresponding memory value may be skipped and not read. This skip operation may be performed for D SSD ⁇ 1 values exceeding N Cell_NUM . By skipping, the input FEC block length and the output FEC length can be the same. Also, even when the skip operation is performed, the maximum dispersion value may be maintained.
  • the above-described operation of the RPI may be performed for each FEC block (block by block).
  • the operation of the RPI may be performed in consideration of the initial offset of the RPI to enable single memory deinterleaving at the receiver.
  • FIG. 21 is a mathematical representation of a memory index generation process for a RPI reading process according to an embodiment of the present invention.
  • I j may refer to the initial offset of the j th sub RPI.
  • mod may mean a modulus operation. May denote an output memory index of the k th input cell index of the j th FEC block (interleaving output memory index (RPI output value)).
  • C cnt, j may mean a counter of the actual output memory index of the j th FEC block.
  • This mathematical expression may be a result of formulating a memory index generator for performing RPI on the output FEC blocks of sequentially received Q1 / Q2 delays.
  • the portion indicated by the dotted line may represent the conditional formula for the skip operation described above.
  • FIG. 22 illustrates a process of generating a memory index of an RPI according to an embodiment of the present invention.
  • the memory index generation process of the RPI includes determining an initial value (s22010), generating a temporary RPI memory index (s22020), evaluating the usefulness of the generated RPI memory index (s22030), and / or a final RPI memory index. It may include generating (s22040).
  • FIG. 23 illustrates a demapping & decoding module including a new I / Q deinterleaver & derotation block according to an embodiment of the present invention.
  • Block by block I / Q deinterleaving proposed by the present invention is a technique corresponding to the above-described block by block I / Q interleaving.
  • Block by block I / Q deinterleaving may be performed using a single memory.
  • Block by block I / Q deinterleaving may be performed in the demapping & decoding module described above. Specifically, the block by block I / Q deinterleaving may be performed in a new I / Q deinterleaver & derotation block corresponding to the aforementioned I / Q deinterleaver & derotation block 15010.
  • the new I / Q deinterleaver & derotation block may be positioned between the time deinterleaver and the cell deinterleaver described above.
  • another embodiment of the present invention according to the case where the cell deinterleaver is omitted may include a constellation demapper after the new I / Q deinterleaver & derotation block.
  • another embodiment of the present invention according to the case where the cell deinterleaver is omitted may include a MIMO decoder after the new I / Q deinterleaver & derotation block.
  • the new I / Q deinterleaver & derotation block performs I / Q interleaved block-block I / Q deinterleaving on the transmitted I and Q components, respectively, and rerotates the complex symbols with recovered I and Q components. Can be performed.
  • the number of input and output symbols of the new I / Q deinterleaver & derotation block can be two, three, four or more.
  • the new I / Q deinterleaver & derotation block may not be performed in a separate block or may be performed in another block.
  • the new I / Q deinterleaver & derotation block can be omitted or replaced by another block with the same or similar functionality.
  • block by block I / Q deinterleaving may be omitted or may be performed on other blocks.
  • FIG. 24 illustrates a block by block I / Q deinterleaver according to an embodiment of the present invention.
  • the block by block I / Q deinterleaver may mean a block that performs block by block I / Q deinterleaving. As described above, block by block I / Q deinterleaving may be included in a new I / Q deinterleaver & derotation block. Overall, the block by block I / Q deinterleaving process may follow the inverse of the block by block I / Q interleaving process.
  • the block by block I / Q deinterleaver may include a block by block relative prime deinterleaver (block by block RPD) and / or an I1 / I2 delay.
  • the Block by Block Reactive Prime Deinterleaver may be referred to as Block by Block RPD or RPD.
  • Block by block RPD may follow the reverse process of RPI.
  • RPD can operate using a single memory.
  • the output of the RPD can be input to the I1 / I2 delay.
  • the RPD may include inserting 0 into a memory index location where a skip operation was performed and / or deinterleaving FEC blocks that are continuously input using a single memory.
  • the deinterleaving of the FEC blocks may further include performing a write / read operation on the first input block and simultaneously performing a write and read operation on the input blocks. Detailed operation will be described later.
  • the reading process may be called deinterleaving in a broad sense in some cases.
  • the I1 / I2 delay may delay only the I component after dividing the I component (In phase component) and Q component (Quadrature phase component) of the input complex symbol.
  • the delay number may be determined depending on whether a 2D SSD (2 dimension signal space diversity) or a 4D SSD (4 dimension signal space diversity) is performed. When the 2D SSD is performed, the delay may be 1 cell. When the 4D SSD is performed, the delay may be 2 cells. As a result, the influence of the Q1 / Q2 delay operated at the transmitter may be canceled through the I1 / I2 delay.
  • 25 is a diagram illustrating an operation of inserting a zero value during an RPD operation according to an embodiment of the present invention.
  • the RPD may perform an operation of inserting 0 into a memory index position that was ignored by a skip operation of the transmitter.
  • an identifiable value may be inserted instead of 0.
  • FIG. 26 illustrates a deinterleaving process using a single memory during an RPD operation according to an embodiment of the present invention.
  • (A) of the figure shows values stored in a single memory according to every input FEC block.
  • the values stored in the single memory may be a result of performing a read process on a previous FEC block and simultaneously writing a cell of a currently input FEC block.
  • the read process may be performed using a memory index.
  • (B) of this figure may represent a memory index required to perform a read process on values stored in a single memory. If the RPD performs deinterleaving according to the memory index (meaning a read process here), the signal may be restored. The generation process of the memory index will be described later.
  • the deinterleaving process using a single memory may include performing a write / read operation on a first input block and simultaneously performing a write and read operation on subsequent input blocks.
  • the input FEC block may be an FEC block inserted with 0 (or an identifiable value).
  • a write process may be performed on the # 0 FEC block.
  • # 0 FEC blocks can be written to a single memory. In this case, the writing process may be performed by generating a memory index by the RPD generator corresponding to the RPI of the transmitter.
  • memory indexes may be sequentially generated in the stored # 0 FEC block to perform a read process (linear reading).
  • the sequential memory index may mean a memory index such as 0, 1, 2. That is, the reverse process of the RPI of the transmitter may be performed for the first input FEC block. If a memory value is identified as 0 (or an identifiable value) in a read process, a skip operation for ignoring the memory value may be performed. A read operation may be performed on the # 0 FEC block and a write operation may be performed on the # 1 FEC block.
  • the RPD can perform a read process by generating a memory index for the stored # 1 FEC block. Since the receiver uses a single memory, it may not be possible to perform a read process using the sub interleaving seed applied to every FEC block by the transmitter. Generation of a memory index for a read process will be described later. As in the first process, when a memory value is identified as 0 (or an identifiable value) in a read process, a skip operation for ignoring the memory value may be performed.
  • a read process may be performed on the stored # 1 FEC block and a write process may be performed on the next FEC block.
  • Simultaneously performing write and read operations on the input blocks may be repeatedly performed on the input blocks.
  • FIG. 27 is a diagram illustrating a memory index generation process during a read process of an RPD according to an embodiment of the present invention.
  • the relation prime and initial offset values are variables of the RPD.
  • the initial offset value may mean the 0 th memory index of the FEC block, and the reactive prime value may mean the difference between the memory indexes. That is, because the case of block # 0 is I 0 value is zero, the 0th memory index is zero.
  • the relation prime value is 1, the first memory index is 1, the next memory index is 2, ..., and so on.
  • the FEC blocks can be effectively read from a single memory by changing the RPD and initial offset values of the RPD every FEC blocks.
  • the relative prime value used in every FEC block can be easily calculated by the power of p.
  • the initial offset value may be determined as follows.
  • This value may be the same value as the first generated value during the memory index generation for the # 0 input FEC block. That is, since the first memory index of the # 0 input FEC block is 1, the 0th memory index (initial offset value) of the # 1 input FEC block may be 1, which is the same value.
  • the RPD stores the first memory index value generated when the memory index is generated for the # 0 input FEC block, and can be used later when generating the memory index for the # 1 input FEC block.
  • the initial offset value to be used for the current FEC input block may use a value stored when a memory index for the previous FEC input block is generated.
  • the algorithm for notifying the location to be stored may be expressed as follows, as shown in the figure.
  • the memory index generation process of the above-described RPD reading process can be mathematically modeled as follows.
  • FIG. 28 is a mathematical representation of a memory index generation process for a RPD reading process according to an embodiment of the present invention.
  • Is It can mean the memory value at. May mean an initial offset (initial offset) value in the j th FEC block. May mean the k th memory index of the j th FEC block. May mean the g j th memory index of the j th FEC block. C cnt, j may mean a counter of the actual output memory index of the j th FEC block.
  • This mathematical expression may represent a memory index generator capable of performing an operation of a single memory.
  • the portion indicated by the dotted line may represent the conditional formula for the skip operation described above.
  • 29 illustrates a process of generating a memory index of an RPD according to an embodiment of the present invention.
  • the memory index generation process of the RPD includes determining an initial value (s29010), generating a temporary RPD memory index (s29020), evaluating the usefulness of a cell value in the generated RPD memory index (s29030), and / or the final value.
  • the method may include generating an RPD memory index (s29040).
  • FIG. 30 is a diagram illustrating combinations of interleavers according to an embodiment of the present invention when no signal space diversity (SSD) is considered.
  • SSD signal space diversity
  • each scenario may include a combination of the cell interleaver, time interleaver and / or block interleaver described above.
  • the invention is not limited to the combinations of interleavers shown, but can propose various additional combinations in which interleavers have been replaced, deleted, or added.
  • the combination of these additional interleavers can be determined by considering the system performance, receiver operation, memory complexity, robustness, and the like as a whole.
  • a new scenario in which the cell interleaver is omitted in each of the four proposed scenarios may be additionally proposed.
  • this additional scenario has not been described, it is within the scope of the present invention, and the operation of the scenario may be equal to the sum of the operations of the respective component interleavers.
  • the diagonal time interleaver and the block time interleaver may be interleavers corresponding to the above-described time interleaver.
  • the pair wise frequency interleaver may be an interleaver corresponding to the aforementioned block interleaver.
  • Each interleaver may be a cell interleaver, a time interleaver and / or a block interleaver, or a cell interleaver, a time interleaver and / or a block interleaver newly proposed by the present invention.
  • the four scenarios described above may include a combination of existing interleavers and newly proposed interleavers.
  • the shaded interleavers may represent a newly proposed interleaver or an interleaver that performs a different role as an existing interleaver.
  • the above table summarizes the interleavers that can be used in the above four scenarios.
  • the Types item defines the type of each interleaver.
  • the cell interleaver may have type A and type B, and the block time interleaver may also have type A and type B.
  • Development Status shows the development status of each interleaver.
  • a type A cell interleaver may be a cell interleaver newly proposed by the present invention (New)
  • a type B cell interleaver may be a conventional cell interleaver (Conventional).
  • the interleaving seed variation item means whether the interleaving seed of each interleaver can be changed, and in the case of YES, it can be changed.
  • the single memory deinterleaving item may be an item indicating whether a deinterleaver corresponding to each interleaver provides single memory deinterleaving. YES means that single memory deinterleaving is provided.
  • the type B cell interleaver may correspond to the frequency interleaver used in the existing technologies (T2, NGH), the type A block time interleaver is DVB-T2, and the type B block time interleaver is DVB-NGH. It may correspond to the interleaver that was used.
  • the above table describes Type A cell interleaver, Type B cell interleaver, and frequency interleaver.
  • the frequency interleaver may correspond to the aforementioned block interleaver.
  • the cell interleaver may interleave and output cells corresponding to one FEC block. In this case, cells corresponding to each FEC block may be output in different orders for each FEC block.
  • the cell deinterleaver may deinterleave the positions of the interleaved cells in the original FEC block.
  • the cell interleaver and cell deinterleaver may be omitted as described above or may be replaced by another block / module having the same or similar function.
  • the type A cell interleaver is an interleaver newly proposed by the present invention and may perform interleaving by applying different interleaving seeds to each FEC block.
  • cells corresponding to one FEC block may be interleaved and output according to an arbitrary period.
  • the type A cell deinterleaver may perform deinterleaving using a single memory.
  • the type B cell interleaver may be an interleaver using an interleaver used as a frequency interleaver as a cell interleaver in the conventional technologies T2 and NGH.
  • the type B cell interleaver may interleave and output cells corresponding to one FEC block.
  • the type B cell interleaver may perform interleaving by applying different interleaving seeds to even (even) FEC blocks and odd (odd) FEC blocks. Accordingly, the type B cell interleaver has a limitation in that it does not apply different interleaving seeds to each FEC block when compared to the type A cell interleaver.
  • the type B cell deinterleaver may perform deinterleaving using a single memory.
  • the general frequency interleaver may correspond to the aforementioned block interleaver.
  • the basic operation of the block interleaver (frequency interleaver) is as described above.
  • the block interleaver may obtain additional diversity gain by interleaving cells in a transmission block that is a unit of a transmission frame.
  • the pair-wise block interleaver may perform interleaving by processing two consecutively input cells as one unit. Accordingly, the output cells of the pair-wise block interleaver may be the same two consecutive cells, and these output cells may operate identically for two antenna paths or may operate independently.
  • the operation of the general block deinterleaver may also be the same as the basic operation of the block deinterleaver described above.
  • the block deinterleaver may reverse the operation of the block interleaver to restore the original data order.
  • the block deinterleaver may perform deinterleaving on data in units of transmission blocks. When the pair-wise block interleaver is used at the transmitter, the block deinterleaver may deinterleave two consecutive data into one pair for each input path. When deinterleaving is performed in pairs, the output data may be two consecutive data.
  • the block interleaver and block deinterleaver may be omitted as described above or replaced by another block / module having the same or similar function.
  • the pair wise frequency interleaver shown in the table may be a new frequency interleaver proposed by the present invention.
  • This new frequency interleaver may perform an operation modified from the basic operation of the aforementioned block interleaver.
  • the new frequency interleaver may operate by applying different interleaving seeds for every OFDM symbol according to an embodiment.
  • interleaving may be performed by grouping OFDM symbols in pairs. In this case, different interleaving seeds may be applied to one OFDM symbol pair. That is, the interleaving seeds may be the same among paired OFDM symbols.
  • An OFDM symbol pair may be generated by combining two consecutive OFDM symbols.
  • interleaving may be performed by pairing two data carriers of an OFDM symbol instead of an OFDM symbol.
  • the new frequency interleaver can interleave using two memories.
  • the even pair may be interleaved using the first memory
  • the odd pair may be interleaved using the second memory.
  • the pairwise frequency deinterleaver may perform deinterleaving using a single memory.
  • the pair-wise frequency deinterleaver may mean a new frequency deinterleaver corresponding to the new frequency interleaver.
  • the above table describes Type A Block Time Interleaver, Type B Block Time Interleaver, Type A Diagonal Time Interleaver, and Type B Diagonal Time Interleaver.
  • the diagonal time interleaver and the block time interleaver may be interleavers corresponding to the above-described time interleaver.
  • a general time interleaver may perform a process of mixing and outputting cells belonging to a plurality of FEC blocks. Through time interleaving, cells in each FEC block may be transmitted by being distributed by a time interleaving depth. Diversity gain can be obtained through time interleaving.
  • the general time deinterleaver may perform a reverse process of the operation of the time interleaver.
  • the time deinterleaver may deinterleave cells interleaved in the time domain to their original positions.
  • the time interleaver and time deinterleaver may be omitted as described above or may be replaced by another block / module having the same or similar function.
  • the block time interleaver shown in the table may perform an operation similar to the time interleaver used in the existing technologies T2 and NGH.
  • the type A block time interleaver may mean an interleaver having an interleaving depth of 2 or more for one input FEC block.
  • the type B block time interleaver may mean an interleaver having an interleaving depth of 1 for one input FEC block.
  • the interleaving depth may mean a period of column wise writing.
  • the diagonal time interleaver shown in the table may be a time interleaver newly proposed by the present invention.
  • the diagonal time interleaver may perform a reading operation diagonally differently from the above-described block time interleaver. That is, the diagonal time interleaver may perform a column wise writing operation to store the FEC block in a memory, and perform a diagonal wise reading operation to read cells stored in the memory.
  • the memory used herein may be two according to embodiments.
  • Diagonal-wise read operation may refer to an operation of reading cells spaced diagonally apart from each other in an interleaving array stored in a memory. Interleaving may be performed through the Diagonal Wise read operation.
  • the diagonal time interleaver may be called a twisted row column block interleaver.
  • the type A diagonal time interleaver may mean an interleaver having an interleaving depth of 2 or more for one input FEC block.
  • the type B diagonal time interleaver may mean an interleaver having an interleaving depth of 1 for one input FEC block.
  • the interleaving depth may mean a period of column wise writing.
  • FIG. 31 illustrates a column wise writing operation of a block time interleaver and a diagonal time interleaver according to an embodiment of the present invention.
  • the interleaving depth may be 2 or more.
  • the interleaving depth may be 1, as shown in the figure.
  • the interleaving depth may mean a period of column wise writing.
  • FIG. 32 is a diagram illustrating a first scenario S1 of a combination of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • the interleaving structure of the first scenario may include a type B cell interleaver, a type A or type B diagonal time interleaver, and / or a pair wise frequency interleaver.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the type B cell interleaver may randomly mix and output cells corresponding to one FEC block. In this case, cells corresponding to each FEC block may be output in different orders for each FEC block. As described above, the Type B cell interleaver may perform interleaving using different interleaving seeds for odd-numbered and even-numbered input FEC blocks. Such cell interleaving may be realized by performing a writing operation at the same time as writing data into a memory.
  • the type A and type B diagonal time interleaver may perform column wise writing and diagonal wise reading operations on cells belonging to a plurality of FEC blocks. Through such diagonal time interleaving, cells positioned at different positions in each FEC block are distributed and transmitted in a section corresponding to a diagonal interleaving depth, thereby obtaining diversity gain.
  • the output of the diagonal time interleaver may be input to the pairwise frequency interleaver through other blocks / modules such as the aforementioned cell mapper.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver. Accordingly, as described above, the pairwise frequency interleaver (new frequency interleaver) may provide additional diversity gain by interleaving cells in an OFDM symbol.
  • the deinterleaving structure of the first scenario may include a pair wise frequency deinterleaver, a type A or type B diagonal time deinterleaver, and / or a type B cell deinterleaver.
  • the pair-wise frequency deinterleaver may be a new frequency deinterleaver corresponding to the new frequency interleaver described above.
  • the pairwise frequency deinterleaver may perform deinterleaving on data by performing a reverse process of the operation of the new frequency interleaver described above.
  • the output of the pairwise frequency deinterleaver may be input to the Type A, Type B diagonal time deinterleaver through other blocks / modules such as the cell demapper described above.
  • the type A and type B diagonal time deinterleaver may perform a reverse process of operations of the type A and type B diagonal time interleavers of the transmitter.
  • type A and type B diagonal time deinterleaver may perform time deinterleaving using a single memory.
  • the type B cell deinterleaver may deinterleave the positions of the interleaved cells in one FEC block to the original positions.
  • FIG. 33 is a diagram illustrating a second scenario S2 among combinations of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • the interleaving structure of the second scenario may include a type A cell interleaver, a type A or type B block time interleaver, and / or a pair wise frequency interleaver.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the type A cell interleaver may perform interleaving using different interleaving seeds for each input FEC block.
  • the Type A and Type B block time interleaver may perform interleaving of cells belonging to the plurality of FEC blocks through a column wise writing operation and a row wise reading operation. Cells placed in different positions are distributed and transmitted within an interval equal to an interleaving depth, thereby obtaining diversity gain.
  • the output of the block time interleaver may be input to the pairwise frequency interleaver through other blocks / modules such as the aforementioned cell mapper.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver. Accordingly, as described above, the pairwise frequency interleaver (new frequency interleaver) may provide additional diversity gain by interleaving cells in an OFDM symbol.
  • the deinterleaving structure of the second scenario may include a pair wise frequency deinterleaver, a type A or type B block time deinterleaver, and / or a type A cell deinterleaver.
  • the pair-wise frequency deinterleaver may be a new frequency deinterleaver corresponding to the new frequency interleaver described above.
  • the pairwise frequency deinterleaver may perform deinterleaving on data by performing a reverse process of the operation of the new frequency interleaver described above.
  • the output of the pairwise frequency deinterleaver may be input to the type A and type B block time deinterleaver through other blocks / modules such as the aforementioned cell demapper.
  • the type A and type B block time deinterleaver may perform a reverse process of operations of the type A and type B block time interleaver of the transmitter.
  • the type A and type B block time deinterleaver may perform time deinterleaving using a single memory.
  • the type A cell deinterleaver may deinterleave the positions of the interleaved cells in the original FEC block.
  • FIG. 34 is a diagram illustrating a third scenario S3 of a combination of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • the interleaving structure of the third scenario may include a type A cell interleaver, a type A or type B diagonal time interleaver, and / or a pair wise frequency interleaver.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • type A cell interleaver type A, type B diagonal time interleaver and pairwise frequency interleaver may be as described above.
  • the deinterleaving structure of the third scenario may include a pair wise frequency deinterleaver, a type A or type B diagonal time deinterleaver, and / or a type A cell deinterleaver.
  • the pair-wise frequency deinterleaver may be a new frequency deinterleaver corresponding to the new frequency interleaver described above.
  • the operation of the pairwise frequency deinterleaver, the type A or type B diagonal time deinterleaver, and the type A cell deinterleaver may be as described above.
  • FIG. 35 is a diagram illustrating a fourth scenario S4 of a combination of interleavers according to an embodiment of the present invention when the signal space diversity (SSD) is not considered.
  • SSD signal space diversity
  • the interleaving structure of the fourth scenario may include a type A or type B diagonal time interleaver, and / or a pair wise frequency interleaver.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the operation of the type A, type B diagonal time interleaver and the pairwise frequency interleaver may be as described above.
  • the deinterleaving structure of the fourth scenario may include a pair wise frequency deinterleaver, and / or a type A or type B diagonal time deinterleaver.
  • the pair-wise frequency deinterleaver may be a new frequency deinterleaver corresponding to the new frequency interleaver described above.
  • the operation of the pairwise frequency deinterleaver, and the type A or type B diagonal time deinterleaver may be as described above.
  • FIG 36 illustrates combinations of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • the combinations of interleavers may be represented by the six scenarios shown (S1 to S6).
  • Each scenario may include a combination of the cell interleaver, rotation & I / Q interleaver, time interleaver and / or block interleaver described above.
  • the invention is not limited to the combinations of interleavers shown, but can propose various additional combinations in which interleavers have been replaced, deleted, or added.
  • the combination of these additional interleavers can be determined by considering the system performance, receiver operation, memory complexity, robustness, and the like as a whole.
  • a new scenario in which the cell interleaver is omitted in each of the six proposed scenarios may be additionally proposed.
  • this additional scenario has not been described, it is within the scope of the present invention, and the operation of the scenario may be equal to the sum of the operations of the respective component interleavers.
  • the six scenarios currently proposed may be proposed even when the SSD is omitted.
  • Each interleaver is a cell interleaver, rotation & I / Q interleaver, time interleaver and / or block interleaver, or the cell interleaver, rotation & I / Q interleaver, time interleaver and / or block interleaver newly proposed by the present invention.
  • the six scenarios described above may include a combination of existing interleavers and newly proposed interleavers.
  • the shaded interleavers may represent a newly proposed interleaver or an interleaver that performs a different role as an existing interleaver.
  • the above table summarizes the Q1 / Q2 delay and I / Q interleaver that can be used in the six scenarios described above.
  • interleaving using Q1 delay may be an existing technique
  • interleaving using Q2 delay may be a technique newly proposed by the present invention.
  • the I / Q interleaver can be divided into type A and type B, both of which are newly proposed by the present invention, and interleaving seed variation may be possible.
  • Type A I / Q interleaver supports single memory deinterleaving, but type B I / Q interleaver may not support single memory deinterleaving.
  • the cell interleaver (type A, B), block time interleaver (type A, B), diagonal time interleaver (type A, B), and / or the new frequency interleaver may be used. Can be used.
  • the cell interleaver (types A and B), the block time interleaver (types A and B), the diagonal time interleaver (types A and B) and the new frequency interleaver have been described above.
  • the table describes the Q1 / Q2 delays and the I / Q interleaver.
  • the Q1 / Q2 delay may be a preceding block / module for independently interleaving the I and Q components of the complex symbol. As described above, the Q1 / Q2 delay may perform an operation of delaying only the Q component after dividing the I component and the Q component of the complex symbol. The delay may be determined as 1 cell in the case of 2D SSD and 2 cells in the case of 4D SSD. After the delay operation is completed, a later process may be performed on the newly paired I and Q components.
  • the I / Q interleaver shown in the table may correspond to the I / Q interleaver except the rotation among the above-described rotation & I / Q interleaver.
  • a general I / Q interleaver may independently interleave I and Q components.
  • the number of input symbols and output symbols of a general I / Q interleaver may be two, three, four, or more.
  • the I component may not be interleaved.
  • a general I / Q deinterleaver may deinterleave the transmitted I and Q components, respectively.
  • the type A and type B I / Q interleaver may be an interleaver newly proposed by the present invention.
  • Type A and Type B I / Q interleavers are similar to general I / Q interleavers, with differences.
  • Type A and Type B I / Q interleavers can accept input signals with Q1 / Q2 delays.
  • Type A I / Q interleaver may interleave by applying different interleaving seeds to the output signal of the Q1 / Q2 delay.
  • the type A I / Q interleaver linearly writes an output signal of the Q1 / Q2 delay into a memory and periodically reads data stored in the memory.
  • the type A I / Q interleaver may perform interleaving by applying different interleaving patterns having the same property to every block.
  • the period applied during the read operation may vary depending on the dimensions of the SSD. When the block length of the output signal of the Q1 / Q2 delay is N, the period of the read operation when using the 2D SSD may be set to N / 2, and the period of the read operation when using the 4D SSD may be set to N / 4.
  • the type A I / Q deinterleaver on the receiving side may perform deinterleaving using a single memory.
  • the type B I / Q interleaver may interleave by applying different interleaving seeds to the output signal of the Q1 / Q2 delay.
  • the type B I / Q interleaver may periodically write an output signal of the Q1 / Q2 delay into a memory and randomly read data stored in the memory.
  • the period applied during the read operation may vary depending on the dimensions of the SSD.
  • the block length of the output signal of the Q1 / Q2 delay is N
  • the period of the read operation when using the 2D SSD may be set to N / 2
  • the period of the read operation when using the 4D SSD may be set to N / 4.
  • the type B I / Q deinterleaver on the receiving side may perform deinterleaving using two memories.
  • the I / Q interleaver described above may be omitted or replaced by another block having the same or similar function.
  • FIG. 37 is a diagram illustrating a first scenario S1 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 1 shows a combination of interleavers according to the prior art.
  • Cell interleaver, rotation & I / Q interleaver, type B block time interleaver and frequency interleaver.
  • Each interleaver is an interleaver according to the existing technology.
  • (B) of this figure shows an interleaving structure according to the first scenario.
  • the interleaving structure of the first scenario is a type B cell interleaver, a constellation rotation block, a Q1 / Q2 delay, a type AI / Q interleaver, a type B block time interleaver and / or a pair wise frequency interleaver.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the constellation rotation block may rotate the constellations according to the rotation angle.
  • the type A I / Q interleaver operates as described above, and may serve to maximize the separation distance between the I and Q components, that is, the spreading property. As described above, the Type A I / Q interleaver may perform interleaving using different interleaving seeds while maintaining a spreading property for every FEC block.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the interleaving structure according to the existing technology is compared with the interleaving structure according to the first scenario.
  • the cell interleaver operates using different random interleaving seeds for each FEC blocks, and requires two memories corresponding to the input FEC block length for performing the corresponding deinterleaving.
  • the rotation & I / Q interleaver block it operates using one interleaving seed, and performing the corresponding deinterleaving requires one memory corresponding to the input FEC block length.
  • three memories corresponding to the input FEC block length are required to perform cell deinterleaving and I / Q deinterleaving & derotation.
  • the pairwise frequency interleaver may perform random interleaving by performing a reading operation simultaneously with a writing operation in a memory on an input OFDM symbol.
  • the receiving side needs one memory corresponding to the input FEC block length for the corresponding deinterleaving.
  • PLP reception performance transmitted through a specific frequency bin having a poor channel condition is always degraded.
  • the receiving side may need one memory corresponding to the input FEC block length to perform a corresponding deinterleaving.
  • the Q1 / Q2 delay and type AI / Q interleaver operate using different interleaving seeds for each FEC block, and the receiving side may need one memory corresponding to the input FEC block length to perform the corresponding deinterleaving. have.
  • two memories corresponding to the input FEC block length may be needed at the receiving side. Therefore, memory use is more efficient than the interleaving structure according to the conventional technology.
  • the pairwise frequency interleaver corresponds to the new frequency interleaver described above, which may operate using a different interleaving seed for every input OFDM symbol.
  • the receiving side may need one memory corresponding to the input OFDM symbol length in order to perform the corresponding deinterleaving.
  • FIG. 38 is a diagram illustrating a first scenario S1 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • (A) of this figure shows a combination of deinterleavers according to the prior art.
  • Frequency deinterleaver type B block time deinterleaver, I / Q deinterleaver & derotation block, and cell deinterleaver.
  • Each deinterleaver is a deinterleaver according to the existing technology.
  • (B) of this figure shows a deinterleaving structure according to the first scenario.
  • the pairwise frequency deinterleaver may perform a reverse process of the operation of the new frequency interleaver described above.
  • the type A I / Q deinterleaver may perform a reverse process of the operation of the type A I / Q interleaver.
  • the I1 / I2 delay divides the complex symbol into I and Q components, and then delays only the I component.
  • the delay may vary depending on the dimensions of the SSD.
  • the I component may be delayed by 1 cell for 2D SSDs and 2 cells for 4D SSDs.
  • the constellation derotation block may perform an operation of rotating the constellation rotated on the transmitting side and returning it to its original position.
  • FIG. 39 is a diagram illustrating a second scenario S2 among combinations of interleavers according to an embodiment of the present invention when considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 1 shows a combination of interleavers according to the prior art.
  • Cell interleaver, rotation & I / Q interleaver, type B block time interleaver and frequency interleaver.
  • Each interleaver is an interleaver according to the existing technology.
  • FIG. (B) of this figure shows an interleaving structure according to the second scenario.
  • the interleaving structure according to the second scenario may not use the cell interleaver unlike the interleaving structure according to the first scenario.
  • the type B I / Q interleaver operates as described above and may serve to maximize a separation distance between the I and Q components, that is, the spreading property.
  • the type B I / Q interleaver may perform interleaving using different interleaving seeds while maintaining a spreading property for every FEC block.
  • the type B I / Q interleaver may perform the function of a cell interleaver that randomly mixes cells. That is, the type B I / Q interleaver may simultaneously perform the functions of the cell interleaver and the I / Q interleaver.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the interleaving structure according to the existing technology and the interleaving structure according to the second scenario are compared.
  • the Q1 / Q2 delay and the Type B I / Q interleaver operate using different random interleaving seeds for every FEC block, and two memories corresponding to the input FEC block length may be required to perform the corresponding deinterleaving. As a result, two memories corresponding to the input FEC block length may be needed at the receiving side. Therefore, the memory usage is more efficient than the interleaving structure according to the conventional technology.
  • the interleaving structure of the second scenario can use the aforementioned new frequency interleaver as the pairwise frequency interleaver similarly to the first scenario. Therefore, since a different interleaving seed is applied to every OFDM symbol, the above-described problem that the interleaving structure according to the conventional technology suffers in the static channel environment can be solved.
  • FIG. 40 is a diagram illustrating a second scenario S2 among combinations of interleavers according to an embodiment of the present invention when considering signal space diversity (SSD).
  • SSD signal space diversity
  • (A) of this figure shows a combination of deinterleavers according to the prior art.
  • Frequency deinterleaver type B block time deinterleaver, I / Q deinterleaver & derotation block, and cell deinterleaver.
  • Each deinterleaver is a deinterleaver according to the existing technology.
  • (B) of this figure shows a deinterleaving structure according to the second scenario.
  • the pairwise frequency deinterleaver may perform a reverse process of the operation of the new frequency interleaver described above.
  • the type B I / Q deinterleaver may perform a reverse process of the operation of the type B I / Q interleaver.
  • the type B I / Q deinterleaver may perform deinterleaving using a double memory since the interleaving seed is randomly generated.
  • FIG. 41 is a diagram illustrating a third scenario S3 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 1 shows a combination of interleavers according to the prior art.
  • Cell interleaver, rotation & I / Q interleaver, type B block time interleaver and frequency interleaver.
  • Each interleaver is an interleaver according to the existing technology.
  • FIG. (B) of this figure shows an interleaving structure according to the third scenario.
  • the interleaving structure according to the third scenario may not use the I / Q interleaver.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the type A and B diagonal time interleaver may perform a column-wise write operation and a diagonal-wise read operation.
  • the type A, B diagonal time interleaver is a function of the cell interleaver that mixes cells located at different positions in each FEC block through a diagonal wise reading method, and the separation between the I component and the Q component. It can perform some functions of the I / Q interleaver to increase the distance.
  • the interleaving structure according to the existing technology and the interleaving structure according to the third scenario are compared.
  • the receiving side may need one memory corresponding to the input FEC block length to perform the corresponding deinterleaving. have. As a result, memory usage is much more efficient than conventional architectures.
  • the aforementioned new frequency interleaver can be used as the pairwise frequency interleaver. Therefore, since a different interleaving seed is applied to every OFDM symbol, the above-described problem that the interleaving structure according to the conventional technology suffers in the static channel environment can be solved.
  • some functions of the cell interleaver and some functions of the I / Q interleaver may be performed by the diagonal-wise read operation of the diagonal time interleaver. According to the separation distance adjustment can be compensated.
  • FIG. 42 illustrates a third scenario S3 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • (A) of this figure shows a combination of deinterleavers according to the prior art.
  • Frequency deinterleaver type B block time deinterleaver, I / Q deinterleaver & derotation block, and cell deinterleaver.
  • Each deinterleaver is a deinterleaver according to the existing technology.
  • (B) of this figure shows a deinterleaving structure according to the third scenario.
  • the pairwise frequency deinterleaver may perform a reverse process of the operation of the new frequency interleaver described above.
  • the type A and B diagonal time interleavers may perform a reverse process of the operation of the type A and B diagonal time interleavers.
  • Type A and B diagonal time deinterleaver may deinterleave the interleaved input symbols to their original positions in the time domain. At this time, time deinterleaving may be performed using a single memory.
  • FIG. 43 is a diagram illustrating a fourth scenario S4 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 1 shows a combination of interleavers according to the prior art.
  • Cell interleaver, rotation & I / Q interleaver, type B block time interleaver and frequency interleaver.
  • Each interleaver is an interleaver according to the existing technology.
  • FIG. (B) of this figure shows an interleaving structure according to the fourth scenario.
  • the interleaving structure according to the fourth scenario may not use the I / Q interleaver unlike the interleaving structure according to the first scenario.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the interleaving structure according to the existing technology and the interleaving structure according to the fourth scenario are compared.
  • one memory corresponding to the input FEC block length may be required to perform deinterleaving corresponding to the type A cell interleaver at the receiving side. Therefore, the memory usage may be much more effective than the interleaving structure according to the existing technology.
  • the interleaving structure of the fourth scenario can use the aforementioned new frequency interleaver as the pairwise frequency interleaver similarly to the first scenario. Therefore, since a different interleaving seed is applied to every OFDM symbol, the above-described problem that the interleaving structure according to the conventional technology suffers in the static channel environment can be solved.
  • FIG. 44 illustrates a fourth scenario S4 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • (A) of this figure shows a combination of deinterleavers according to the prior art.
  • Frequency deinterleaver type B block time deinterleaver, I / Q deinterleaver & derotation block, and cell deinterleaver.
  • Each deinterleaver is a deinterleaver according to the existing technology.
  • (B) of this figure shows a deinterleaving structure according to the fourth scenario.
  • pairwise frequency deinterleaver type A, B block time deinterleaver, type A cell deinterleaver, I1 / I2 delay, and constellation derotation block has been described above.
  • the pairwise frequency deinterleaver may perform a reverse process of the operation of the new frequency interleaver described above.
  • FIG 45 is a diagram illustrating a fifth scenario S5 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 1 shows a combination of interleavers according to the prior art.
  • Cell interleaver, rotation & I / Q interleaver, type B block time interleaver and frequency interleaver.
  • Each interleaver is an interleaver according to the existing technology.
  • FIG. (B) of this figure shows an interleaving structure according to the fifth scenario.
  • the interleaving structure according to the fifth scenario may not use the I / Q interleaver unlike the interleaving structure according to the first scenario.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the interleaving structure according to the existing technology and the interleaving structure according to the fifth scenario are compared.
  • the interleaving structure of the fifth scenario uses the new frequency interleaver as the pairwise frequency interleaver as in the first scenario, the aforementioned problem that may occur in the static channel environment can be solved.
  • FIG. 46 is a diagram illustrating a fifth scenario S5 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • (A) of this figure shows a combination of deinterleavers according to the prior art.
  • Frequency deinterleaver type B block time deinterleaver, I / Q deinterleaver & derotation block, and cell deinterleaver.
  • Each deinterleaver is a deinterleaver according to the existing technology.
  • (B) of this figure shows a deinterleaving structure according to the fifth scenario.
  • pairwise frequency deinterleaver type A, B diagonal time deinterleaver, type A cell deinterleaver, I1 / I2 delay and constellation derotation block has been described above.
  • the pairwise frequency deinterleaver may perform a reverse process of the operation of the new frequency interleaver described above.
  • FIG. 47 is a diagram illustrating a sixth scenario S6 of a combination of interleavers according to an embodiment of the present invention when considering signal space diversity (SSD).
  • SSD signal space diversity
  • FIG. 1 shows a combination of interleavers according to the prior art.
  • Cell interleaver, rotation & I / Q interleaver, type B block time interleaver and frequency interleaver.
  • Each interleaver is an interleaver according to the existing technology.
  • FIG. (B) of this figure shows an interleaving structure according to the sixth scenario.
  • the interleaving structure according to the second scenario may not use the cell interleaver and the I / Q interleaver unlike the interleaving structure according to the first scenario.
  • the pair-wise frequency interleaver may be the aforementioned new frequency interleaver.
  • the interleaving structure according to the existing technology and the interleaving structure according to the sixth scenario are compared.
  • the roles of the cell interleaver and the I / Q interleaver may be performed only with the diagonal time interleaver. Therefore, the memory usage efficiency at the receiver side can be maximized.
  • the interleaving structure of the sixth scenario uses the aforementioned new frequency interleaver as the pairwise frequency interleaver, the above-described problems that may occur in the static channel environment can be solved.
  • FIG. 48 is a diagram illustrating a sixth scenario S6 of a combination of interleavers according to an embodiment of the present invention in the case of considering signal space diversity (SSD).
  • SSD signal space diversity
  • (A) of this figure shows a combination of deinterleavers according to the prior art.
  • Frequency deinterleaver type B block time deinterleaver, I / Q deinterleaver & derotation block, and cell deinterleaver.
  • Each deinterleaver is a deinterleaver according to the existing technology.
  • (B) of this figure shows a deinterleaving structure according to the sixth scenario.
  • pairwise frequency deinterleaver type A, B diagonal time deinterleaver, the I1 / I2 delay and the constellation derotation block has been described above.
  • the pairwise frequency deinterleaver may perform a reverse process of the operation of the new frequency interleaver described above.
  • 49 is a diagram illustrating an entire transceiver unit by connecting a transmitter and a receiver according to an embodiment of the present invention.
  • the channel block 4910 may be a block in which distortion of a transmission signal and noise are added.
  • the signal at point (A) may be a bit signal.
  • the signal at point (B) may be a received bit signal or information associated with the bit signal.
  • Information associated with the bit signal may be a log likelyhood ratio (LLR).
  • LLR log likelyhood ratio
  • Signals at points (A) and (B) may lose their correlation between signals while passing through several blocks between the two points.
  • the signals at points (A) and (B) may lose correlation between signals while passing through the bit interleaver and the bit deinterleaver. Since the correlation between signals is lost, each bit can be thought of as having been transmitted and received through an independent channel.
  • the signals at points (A) and (B) can be independent of each other.
  • a bit to cell demux block may map a predetermined set of bits into one cell.
  • the amount of information transmitted from point (A) to point (B) may vary according to the mapping method of the constellation mapper.
  • the amount of information transmitted may be referred to as capacity and may indicate the number of bits that can be sent per cell.
  • the bit-to-cell demux block may be omitted. If the bit to cell demux block is omitted, an operation of mapping bits to cells in another block may be performed.
  • the total capacity can be determined by adding the capacity values of each bit and then adding them. This overall capacity may be referred to as parallel decoding capacity.
  • the present invention proposes a new constellation generation method with improved performance in terms of parallel decoding capacity.
  • the present invention may relate to the structure and method of the bit-to-cell demux and / or constellation mapper in the aforementioned coding and modulation module.
  • the present invention may relate to another block and / or constellation mapper structure and method for performing an operation of mapping a bit to a cell.
  • the present invention proposes a new constellation mapping method that can increase the capacity.
  • FIG. 50 is a diagram illustrating binary reflected gray code (BRGC) and bit package allocation according to an embodiment of the present invention.
  • the present invention can determine the arrangement order of a bundle of bits using binary reflected gray code (BRGC). This embodiment may illustrate the case of 256 QAM.
  • BRGC binary reflected gray code
  • (A) of this figure may show the order of arrangement of bits according to the BRGC.
  • 256 QAM can transmit a total of 8 bits. These eight bits may be allocated four bits to the I component and the Q component, respectively.
  • the arrangement of each bit assigned to the I component and the Q component may be according to the BRGC.
  • the b0 bits may be arranged in a reflective manner as shown in (1).
  • b0 may be first reflected and arranged, and then the values 0 and 1 of b1 may be arranged as shown in the figure.
  • the b2 / b1 / b0 bundle can be arranged by reflecting b1 / b0 and then arranging the value of b2.
  • the b3 / b2 / b1 / b0 bundle can also be arranged by reflecting b2 / b1 / b0 after b2 / b1 / b0 in accordance with the same rule, and then matching the b3 value.
  • (B) of this figure may show how the bit package is allocated to each of 4 bits of I and Q.
  • the size of a bit package can be 8 bits.
  • bb7 / bb6 / bb5 / bb4 / bb3 / bb2 / bb1 / bb0 may be an 8-bit package (a bundle of one bits) to be assigned to each of 4 bits of I and Q.
  • b7 / b6 / b5 / b4 / b3 / b2 / b1 / b0 may represent 4 bits of I and Q, respectively.
  • an 8 bit package can be assigned to each of the 4 bits of I and Q in each of 1), 2) or 3).
  • schemes 1), 2), and 3) shown in the figure may be allocated in other manners.
  • bb7 can be connected to b7, bb6 to b6, bb5 to b5, bb4 to b4, bb3 to b3, bb2 to b2, bb1 to b1, and bb0 to b0.
  • Bb7 can be connected to b7, bb6 to b3, bb5 to b6, bb4 to b2, bb3 to b5, bb2 to b1, bb1 to b4, and bb0 to b0.
  • FIG. 51 is a view illustrating a 256 QAM constellation mapping process according to an embodiment of the present invention.
  • Bits mapped to bits b7 to b0 of I and Q may be mapped to constellation points by the BRGC rule. Constellation mapping may be performed by the value of each input bit. Each constellation point in this figure may be a value before normalizing the average power to one.
  • I, Q may have values of -15, -13, -11, -9, -7, -5, -3, -1, 1, 3, 5, 7, 9, 11, 13, and 15, respectively. .
  • I and Q may determine which constellation points have values by the bit values of b7 / b6 / b5 / b4 / b3 / b2 / b1 / b0.
  • a constellation may refer to a set of constellation points, but depending on the context, a constellation point may be referred to as a constellation.
  • the present invention proposes a method of improving the above-described constellation mapping process in a direction of increasing capacity.
  • FIG. 52 illustrates a constellation shift method for generating a modified 256 QAM according to an embodiment of the present invention.
  • the constellation movement method may follow the rules of (1) and (2) of (a) of this figure.
  • the rules in (1) and (2) are equally applicable to the 2/3/4 quadrant. However, as shown by the arrows in the figure, the quadrant rule may be applied while rotating counterclockwise by 90 degrees. This allows square 256 QAM (previous 256 QAM) to be transformed into a modified 256 QAM.
  • (B) of this figure may indicate a constellation movement method by a coordinate value.
  • I component, Q component is displayed in the same manner, the I component may be a horizontal axis, the Q component may represent a vertical axis. The formula for moving these coordinates will be described later.
  • Changing the constellation can increase the distance between adjacent constellation points when the average power is normalized to one.
  • the average signal power before normalization may be 170.0 for 256 QAM, and the modified 256 QAM may be 163.5.
  • Each constellation point can be normalized by dividing by the square root of the average signal power.
  • the distance between adjacent constellation points may be about 1.019683947, a square root of 170.0 / 163.5. The distance between adjacent constellation points increases, making them more robust to noise.
  • FIG. 53 illustrates a final constellation diagram of a modified 256 QAM according to an embodiment of the present invention.
  • the modified 256 QAM can obtain shaping gain by changing the shape of the constellation.
  • Equations for a method of moving the above-described coordinates may be as follows.
  • d may be 2 * a.
  • d may refer to a distance between constellation points as shown in the drawing.
  • a 1 is assumed.
  • 54 is a view illustrating constellation points corresponding to 0 and 1 in a 256 bit QAM constellation modified according to an embodiment of the present invention.
  • This figure shows the modified 256 QAM constellation for each bit, from MSB to LSB of each axis, and may show constellation points corresponding to values of 0 and 1 when the value of each bit is 0 and 1.
  • FIG. assigning values of 0 and 1 to each constellation point for each bit is called labeling, and the set is called label.
  • black points may indicate constellation points when the bit value is 0 and white points may indicate constellation points when the bit value is 1.
  • the distribution of 0 and 1 for each bit and the characteristics of its boundaries can affect the LLR value. Therefore, the FEC decoding performance may be affected by the boundaries of 0 and 1 of each bit.
  • B7 to b0 of this figure may be the same as b7 to b0 used in the above description of the BRGC and 256 QAM.
  • b7 and b3 can be MSB and b4 and b0 can be LSB, respectively.
  • the modified 256 QAM may have a good performance section and a bad section according to the amount of noise compared to the existing 256 QAM. In the case of good performance, the modified 256 QAM can replace the existing 256 QAM.
  • 55 is a diagram illustrating the performance when a modified 256 QAM is used according to an embodiment of the present invention.
  • (A) of this figure shows BICM capacity or parallel decoding capacity.
  • 'Shannon' can mean capacity based on Shannon's theory. Capacity based on Shannon's theory may be the ideal capacity.
  • 'qamBRGC' may mean capacity according to the existing 256 QAM.
  • 'mqamBRGC' may mean capacity according to the modified 256 QAM.
  • (B) of this figure shows the capacity gap (difference) between capacity based on Shannon's theory and BICM capacity.
  • 'gap (qamBRGC)' may be a value obtained by subtracting the 'qamBRGC' value from the 'Shannon' value of (a).
  • 'gap (mqamBRGC)' may be a value obtained by subtracting the 'mqamBRGC' value from the 'Shannon' value of (a).
  • (B) shows that the difference between the capacity according to 256 QAM and the capacity according to Shannon is smaller than the difference between the capacity according to 256 QAM and Shannon according to the modified SNR greater than about 14.5 dB. . This result shows that in the SNR period larger than about 14.5dB, the modified 256 QAM can transmit more information than the conventional 256 QAM.
  • FIG. 56 is a view illustrating constellations in which modified 256 QAM is further improved according to an embodiment of the present invention.
  • (A) of this figure shows the modified 256 QAM described above.
  • (B) and (c) of this figure show the constellations which improved the modified 256 QAM mentioned above.
  • the constellations of (b) and (c) of this figure may be constellations in which d values are increased by further moving constellation points indicated by e1 to e4 in the modified 256 QAM described above. d may mean the shortest distance between constellation points indicated by e1 to e4 and adjacent constellation points.
  • the constellation of (b) of this figure is' improved modified 256 QAM # 1 (New m256 QAM # 1) ', and the constellation of (c) of this figure is' improved modified 256 QAM # 2 (New m256 QAM #). 2) can be called.
  • the present invention proposes an improved modified 256 QAM that uses a value of d greater than 2 * a in the modified 256 QAM.
  • changing the characteristic of the constellation by changing the d value of the regions e1 to e4 may be equally applied to not only the modified 256 QAM but also more constellation numbers. Especially when the code rate of the FEC is high, the performance can be further improved.
  • modified 256 QAM # 1 and # 2 can be obtained from the existing 256 QAM, respectively.
  • the Na component may be added.
  • 57 is a view illustrating a constellation shift method of an improved modified 256 QAM according to an embodiment of the present invention as a coordinate value.
  • (A) of the figure shows a method of moving the modified 256 QAM as coordinate values, as described above.
  • I component, Q component is displayed in the same manner, the I component may be a horizontal axis, the Q component may represent a vertical axis.
  • (B) of this figure may represent the constellation shift method of the improved modified 256 QAM as a coordinate value.
  • (17, x) and (x, 17) may be changed to (18, x) and (x, 18).
  • (17, x) and (x, 17) may be changed to (19, x) and (x, 19).
  • a method of moving to the changed coordinates while maintaining the integer value was used.
  • FIG. 58 is a diagram illustrating the capacity of an improved variant 256 QAM according to an embodiment of the present invention.
  • This figure may illustrate the difference between the capacity based on Shannon's theory and the capacity according to the improved variant 256 QAM, depending on the SNR.
  • 'gap (qamBRGC)' and 'gap (mqamBRGC)' are as described above.
  • the graph of this figure shows that the improved modified 256 QAM # 1, # 2 is closer to Shannon limit than the existing 256 QAM in most SNR intervals.
  • the range of poor performance compared to the existing 256 QAM is about 14.5 dB for the modified 256 QAM, while about 11 dB and 12.5 dB for the modified 256 QAM # 1 and # 2.
  • the improved variant 256 QAM has better capacity performance than the existing 256 QAM over a wider SNR range.
  • the modified 256 QAM has an average power ratio of 0.96176, 0.97785 for the improved variant 256 QAM # 1, and 0.99485 for the improved variant 256 QAM # 2, all higher than 1. small. Therefore, it can be seen that it still has shaping gain compared to the existing 256 QAM.
  • the ratio of the average power may mean the average power of the modified 256 QAM (or the improved modified 256 QAM # 1, # 2) divided by the average power of the existing 256 QAM.
  • FIG. 59 illustrates a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • the constellation mapper described above may modulate the input cell word using QPSK, QAM-16, non uniform QAM, non uniform constellation, or the like.
  • Non-uniform QAM can be abbreviated as NUQ (Non uniform QAM).
  • Non-uniform constellation can be abbreviated as NUC (Non uniform Constellation).
  • Non-uniform QAMs may include NUQ-64, NUQ-256, NUQ-1024, and the like.
  • Non-uniform constellations may include NUC-16, NUC-64, NUC-256, NUC-1024, and the like. Constellation mapping can be applied to DP. NUQ and NUC can be determined for each code rate.
  • This figure may define new parameters in the constellation of the modified 256 QAM described above. These new parameters may be to find the ideal constellation with the maximum parallel decoding capacity.
  • the horizontal axis of the illustrated constellation can be defined as the x axis and the vertical axis as the y axis.
  • Each constellation point becomes a point on the x-y coordinate and can be represented by x and y values.
  • the positions corresponding to the x values of the constellation points with positive x values are expressed from a to i.
  • the distance from the y axis to the position a can be defined as da.
  • the distance from the y axis to the positions b, c, ... i can be defined as db, dc, ... di respectively.
  • Negative constellation points on the x-axis are each symmetric with positive constellation points.
  • the value can be-da,-db, ...,-di.
  • the values on the y-axis follow the definition of the x-axis, so the distance between the x-axis and each constellation point is-di,-dh, ...,-da, da, ..., dh, di
  • Each can have a value (in order from lowest to lowest).
  • the constellation points generated by the above definition can be symmetric about both the x and y axes.
  • the constellation with the highest parallel decoding capacity may be determined by the value of constellation points found while changing the da to di values previously defined. According to this scheme, the present invention presents a constellation having the highest value of parallel decoding capacity for each SNR and its gain (da to di). In addition, the present invention separately presents a gain value suitable for real hardware implemented in a binary system.
  • Embodiment # 1 is a flowchart of Embodiment # 1 of a method of generating a new non uniform constellation according to one embodiment of the present invention.
  • Embodiment # 1 of the method for generating a new non-uniform constellation may refer to an embodiment of a method of determining an optimal non-uniform constellation of the modified 256 QAM.
  • the gain values corresponding to the optimal constellation may be represented by da_max, db_max, ..., di_max, respectively.
  • da_max ⁇ di_max can be set to 0 once at the start.
  • sda may be a positive value.
  • the maximum value of da is mda, and da may be equal to or greater than sda.
  • cap_max may mean a capacity value when da to di have da_max to di_max values, respectively.
  • the cap_max value can be set to zero once at startup.
  • the parallel decoding capacity can be found.
  • the parallel decoding capacity of each combination can be stored in the cap_new variable. If the cap_new value is larger than the already stored cap_max value, cap_max and da_max to di_max can be updated to the value of the corresponding combination.
  • the da_max to di_max values obtained through the above-described process may be a value at which parallel decoding capacity becomes maximum in a given SNR (target SNR).
  • SNR_target is an SNR value that is a target to be searched and may be an input variable for parallel decoding capacity calculation.
  • SNR may be a signal power to noise power ratio. If the target SNR is changed, the optimal da_max to di_max values may change accordingly. Therefore, the above-described da_max to di_max can be found for each desired SNR.
  • the step value may be set to a value sufficiently smaller than 1 so that the gain value can be found in one search process.
  • s 0.1 was set. Step values less than 0.1 may not make a significant difference in determining the capacity value.
  • the step values for da to di may be the same.
  • the sda to sdi values can all be set to 0.0 so that the smallest gain can be found.
  • mda to mdi values may be set to max_d equally.
  • the max_d value can be set to a value sufficiently larger than the expected value of di. In this example, a value of 25.0 or more was used.
  • all values between 0 and max_d may be searched for da to di, respectively.
  • the search time may take a long time.
  • the number of times to calculate the capacity in the above-described search process may be expressed as (max_d / step) ⁇ 9, which is the number of calculations per each gain value da to di. Therefore, the number of calculations can be greatly increased in 9 power units according to the values of max_d and step.
  • FIG. 61 is a flowchart of Embodiment # 2 of a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • Embodiment # 2 of the method for generating a new non-uniform constellation may refer to an embodiment of a method of determining an optimal non-uniform constellation of the modified 256 QAM.
  • Example # 2 is similar to the above-described embodiment # 1, except that a mechanism for reducing the number of searches may be added. That is, the first embodiment is different from the first embodiment, in order to reduce the number of searches, when the search operation is performed while changing the gain values by the for statement after the start, the initial values of the gains (sda to sdi) May be linked to and organically changed.
  • the soffset value may be set to a value equal to or greater than 0. In this embodiment, 1.0 is used.
  • FIG. 62 is a flowchart of Embodiment # 3 of a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • Embodiment # 3 of the method for generating a new non-uniform constellation may refer to an embodiment of a method of determining an optimal non-uniform constellation of the modified 256 QAM.
  • Embodiment # 3 may be another embodiment for further reducing the number of capacity calculations.
  • Example # 3 may relate to a method that may be additionally applied to Example # 1 and Example # 2.
  • the description of Embodiment # 3 will be described based only on the above-described Embodiment # 2, only the portion added or changed compared to Embodiment # 2.
  • Example # 3 the initial value s of step may be set to a larger value than that of Example # 2.
  • the value of (mda-sda) / step which is the number of iterations of the for statement to find each gain, may be made smaller.
  • the db ⁇ di value the number of iterations of the for statement can be reduced.
  • the old step may be a rather large step value before the change.
  • sden may be a value used to reduce the step.
  • the sdb to sdi and mdb to m values can also be reset in the same way.
  • the process of searching for da_max to di_max values again may be performed using the reset variable values. As such, changing the value of step from a large value to a small value and reducing the search range can reduce the total capacity calculation count.
  • the initial step value s may be set to 0.4 or 0.8.
  • the number of times the search process is repeated according to the change of the step value may be determined by the initial step values s, sden, and smin.
  • the smin value can be any value greater than zero and less than one.
  • FIG. 63 is a flowchart of Embodiment # 4 of a method of generating a new non uniform constellation according to an embodiment of the present invention.
  • Embodiment # 4 of the method for generating a new non-uniform constellation may refer to an embodiment of a method of determining an optimal non-uniform constellation of the modified 256 QAM.
  • Embodiment # 4 may be another embodiment for further reducing the number of capacity calculations.
  • Example # 4 may relate to a method that may be additionally applied to Example # 1 and Example # 2.
  • the following description of Embodiment # 4 describes a method for more efficiently implementing Embodiment # 3 based on the above-described Embodiment # 3.
  • Embodiment # 4 may be according to a method of differently setting the step values used in the embodiment # 3 for each gain.
  • a gain with a wide range of values increases the step value, and a gain such as da having a relatively small range decreases the step value, so that the da_max to di_max values can be found more efficiently.
  • the stepa to stepi values may mean gain values for each gain for finding da_max to di_max, respectively. That is, the case # 3 may be the case where all of the stepa to stepi values are the same.
  • the gain values of the Non Uniform Modified 256 QAM (described below) may be determined using a method of setting adjacent gains to have gain step values. The method of grouping adjacent gains can be arbitrarily determined, but it is more efficient to group adjacent gains to have the same step value.
  • the smallest value among the updated gain step values when exiting the entire search loop, the smallest value among the updated gain step values may be smaller than the smin value.
  • the entire search loop when the largest value among the updated gain step values is smaller than the smin value, the entire search loop may be exited.
  • FIG. 64 is a diagram illustrating modified Non-Uniform Modified 256 QAM according to the present invention compared to Modified 256 QAM when the SNR value is 22 dB.
  • (A) of this figure shows the modified 256 QAM described above.
  • (B) of this figure shows Non Uniform modified 256 QAM.
  • the constellation of (b) may be drawn using da_max to di_max values determined by the method of Example # 4 mentioned above.
  • the SNR value is 22 dB
  • the constellation of (b) may be a constellation before power normalization is performed.
  • (B) of this figure may represent a constellation having the maximum parallel decoding capacity in the corresponding SNR determined by the above-described calculation process.
  • the constellation of (b) may be different from the constellation of (a) with uniform intervals.
  • FIG. 65 is a graph illustrating gain values of a Non Uniform Modified 256 QAM according to an embodiment of the present invention.
  • the x-axis of the graph may be an SNR value, and the y-axis may mean a gain value.
  • the gain values of the graph may be values determined in the manner of Example # 4 described above. In the case of some SNR values 12, 16, 20, 22, and 24 dB, the graph may show gain values for each SNR.
  • the table may be da to di values for each SNR value. Constellations using the da to di values shown may have the maximum parallel decoding capacity in the corresponding SNR. For other SNR values, da to di values for maximizing capacity can be obtained according to the aforementioned schemes.
  • the foregoing scheme may also be applied to constellations with modified 1024-QAM and higher constellation numbers.
  • the present invention may suggest a modified non-uniform 256 QAM.
  • FIG. 66 is a view illustrating a capacity difference between a non uniform modified 256 QAM (Non Uniform modified 256 QAM) and a capacity of Shannon limit according to an embodiment of the present invention.
  • '256mqamBRGC_NUM' in (a) of this figure shows the parallel decoding capacity calculated using the gain values of the modified non-uniformity 256 QAM.
  • the graph of '256mqamBRGC_NUM' is located closer to the Shannon limit compared to 'qamBRGC' and 'mqamBRGC' described above. This means that the modified non-uniform 256 QAM can transmit more information volume under the same conditions than other constellations.
  • (B) of this figure shows how far the capacity value of the modified non-uniformity 256 QAM is from Shannon limit.
  • 'gap (NUC_mqamBRGC)' may mean the difference between the capacity and Shannon limit according to the changed non-uniform 256 QAM. As shown, 'gap (NUC_mqamBRGC)' may have a smaller value than 'gap (qamBRGC)' and 'gap (mqamBRGC)'.
  • 67 is a diagram illustrating a method for transmitting a broadcast signal according to an embodiment of the present invention.
  • the method for transmitting a broadcast signal comprises the steps of: formatting the input streams into a plurality of data pipes (DP), encoding data of the DP for each DP, mapping data of the encoded DP to generate a signal frame And / or modulating data of the signal frame by an OFDM scheme and transmitting a broadcast signal.
  • DP data pipes
  • Formatting the input streams into a plurality of data pipes may be a step in which the above-described input formatting module formats / processes the input streams into the plurality of DPs.
  • DP may be called PLP (Physical Layer Pipes).
  • the encoding of the data of the DP for each DP may be a step in which the aforementioned coding and modulation module encodes the data in the DP for each DP according to a code rate.
  • the method may include: low density parity check (LDPC) encoding of data of a plurality of DPs, bit interleaving LDPC encoded data, mapping bit interleaved data to constellation according to code rate, Multi-Input Multi Ouput (MIMO) encoding of the mapped data, and / or diagonal time interleaving of the MIMO-encoded data.
  • LDPC low density parity check
  • MIMO Multi-Input Multi Ouput
  • the LDPC encoding of data of the plurality of DPs may be a step in which the aforementioned LDPC encoding is performed.
  • LDPC encoding may be performed according to the code rate.
  • Bit interleaving the LDPC encoded data may be a step in which the aforementioned bit interleaver block performs bit interleaving as described above.
  • the mapping of the bit interleaved data to the constellation according to the code rate may be a step in which the aforementioned constellation mapper block maps the data to the constellation according to the code rate.
  • the constellation may be a constellation of QAM, NUQ, NUC, and the like described above. The constellation can vary depending on the code rate.
  • the multi-input multi-output (MIMO) encoding of the mapped data may be a step in which the aforementioned MIMO processing block performs MIMO encoding.
  • MIMO encoding may be performed by a MIMO encoding matrix.
  • Diagonally time interleaving the MIMO encoded data may be a step in which the aforementioned time interleaver block performs time interleaving as described above.
  • the generating of the signal frame by mapping the data of the encoded DP may be the step of generating the frame by the above-described frame structure module.
  • Modulating the data of the signal frame by the OFDM scheme and transmitting the broadcast signal may be a step in which the above-described waveform generation module performs data modulation and broadcast signal transmission.
  • a method of transmitting a broadcast signal wherein the step of diagonal time interleaving performs a column wise write operation on MIMO encoded data and stores the result in a memory; And interleaving by performing a wise read operation.
  • the method may be a method of transmitting a broadcast signal.
  • the diagonal time interleaving may be a step in which the above-described diagonal time interleaver performs time interleaving.
  • the diagonal time interleaver may be a type A or type B diagonal time interleaver.
  • a method for transmitting a broadcast signal includes: generating a signal frame, further comprising performing frequency interleaving of data in the generated signal frame in pairs of OFDM symbols; It may be a method of transmitting a signal.
  • the performing of the frequency interleaving may be a step in which the aforementioned new frequency interleaver performs frequency interleaving.
  • the method of transmitting a broadcast signal may be a method of transmitting a broadcast signal, wherein the step of performing frequency interleaving performs interleaving using two memories.
  • the new frequency interleaver may perform frequency interleaving using two memories at the transmitting end.
  • the new frequency deinterleaver of the receiver may perform deinterleaving using a single memory.
  • a method for transmitting a broadcast signal includes the above-mentioned constellation being a quantum DP (Quadrature Amplitude Modulation) or NU-QAM (Non-QAM) having a maximum capacity. It may be a method of transmitting a broadcast signal.
  • the constellation for each DP may be QAM, NU-QAM, or non uniform constellation (NUC).
  • NU-QAM having the largest capacity may be NU-QAM determined by the method of finding the non-uniform constellation having the maximum capacity described above.
  • This non-uniform constellation may be a modified non-uniform constellation having a maximum capacity determined by the method of generating the new non-uniform uniform constellation described above.
  • the method for transmitting a broadcast signal may further include encoding the data of the DP for each DP and interleaving the data mapped to the constellation.
  • the interleaving of the data mapped to the constellation may include delaying the imaginary component by separating real and imaginary components of the data mapped to the constellation, and sequentially writing the delayed data. Storing the data in the memory and reading the data stored in the memory using a memory index.
  • the operation of delaying the imaginary component by separating the real component and the imaginary component may be an operation of the above-described Q delay.
  • the write operation and the read operation using the memory index may correspond to the above-described block by block I / Q interleaving.
  • block by block I / Q interleaving may not be performed in a separate block or may be performed in another block.
  • block by block I / Q interleaving may be omitted or replaced by another block having the same or similar function.
  • the memory index may be a memory index used for a read operation in the above-described block by block I / Q interleaving.
  • 68 is a diagram illustrating a method of receiving a broadcast signal according to an embodiment of the present invention.
  • a method of receiving a broadcast signal includes receiving a broadcast signal, demodulating data of a signal frame by an OFDM scheme, and parsing the signal frame by demapping data of a plurality of DPs. Decoding DP data for each DP and / or deformatting the DP data into an output stream.
  • Receiving the broadcast signal and demodulating the data of the signal frame by the OFDM scheme may be a step in which the above-described synchronization & demodulation module receives the broadcast signal and demodulates the data.
  • Parsing a signal frame by demapping data of the plurality of DPs may be a step in which the aforementioned frame parsing module parses the signal frame.
  • the decoding of the DP data by DP may be a step in which the above-described demapping & decoding module decodes the DP data by DP path.
  • Decoding the DP data by DP may include: diagonally deinterleaving the data of the plurality of DPs, multi-input multi-duup (MIMO) decoding of the time deinterleaved data, and decoding the MIMO decoded data according to a code rate. Demapping from constellations, bit deinterleaving the demapped data from the constellations, and / or low density parity check (LDPC) decoding the bit deinterleaved data.
  • MIMO multi-input multi-duup
  • Diagonally time deinterleaving the data of the plurality of DPs may be a step of time deinterleaving the aforementioned time deinterleaver block. This step may be a step in which the aforementioned diagonal time deinterleaver performs diagonal time deinterleaving.
  • the diagonal time deinterleaver may be Type A or Type B.
  • the MIMO decoding of the time deinterleaved data may be a step in which the aforementioned MIMO decoding block performs MIMO decoding.
  • the MIMO decoding block may perform the reverse process of the MIMO processing block.
  • Demapping the MIMO decoded data from the constellation according to the code rate may be a step in which the aforementioned constellation demapper block demaps the data from the constellation.
  • the constellation may be different for each DP path.
  • the constellation may be QAM, NU-QAM, NUC, as described above.
  • the constellation may vary depending on the code rate as described above.
  • Bit deinterleaving the demapped data from the constellation may be a step in which the aforementioned bit deinterleaver block performs bit deinterleaving as described above.
  • Low-density parity check (LDPC) decoding of the bit deinterleaved data may be a step in which LDPC decoding is performed on the data as described above.
  • LDPC decoding may be performed according to the code rate.
  • Deformatting data of the DP into an output stream may be a step in which the aforementioned output processor performs output processing.
  • a method for receiving a broadcast signal wherein the step of diagonal time deinterleaving comprises: performing a diagonal wise write operation on data of a plurality of DPs and storing the result in a memory; And performing a column wise read operation from a memory to deinterleave the method.
  • the Diagonal-wise write operation and the column-wise read operation may be operations of the diagonal time deinterleaver described above.
  • the diagonal time deinterleaver may be a type A or type B diagonal time deinterleaver.
  • a method of receiving a broadcast signal wherein parsing the signal frame further includes performing frequency deinterleaving of data in the signal frame in pairs of OFDM symbols. It may be a method of receiving.
  • the frequency deinterleaving may be an operation of the aforementioned new frequency deinterleaver.
  • the step of performing frequency deinterleaving may be a method for receiving a broadcast signal, wherein the deinterleaving is performed using one memory.
  • the new frequency deinterleaver may perform frequency deinterleaving using a single memory.
  • a broadcast signal in which the constellation is QAM (Quadrature Amplitude Modulation) or NU-QAM (Non Uniform QAM) having a maximum capacity for each of a plurality of DPs It may be a method of receiving.
  • the constellation used may vary by DP.
  • the constellation may be QAM, NU-QAM, or NUC.
  • NU-QAM having the largest capacity may be NU-QAM determined by the method of finding the non-uniform constellation having the maximum capacity described above.
  • This non-uniform constellation may be a modified non-uniform constellation having a maximum capacity determined by the method of generating the new non-uniform uniform constellation described above.
  • the method of receiving a broadcast signal may further include deinterleaving the time deinterleaved data.
  • the deinterleaving of the time deinterleaved data may include inserting 0 into a memory index location that was ignored by a skip operation of the time deinterleaved data, and writing data using the memory index. Storing the data in a single memory and performing a reading operation on the data stored in the single memory, and separating the real component and the imaginary component of the read data and delaying the real component. It may be a method of receiving a broadcast signal.
  • the operation of delaying the real component by separating the real component and the imaginary component may be the operation of the above-described I delay.
  • the 0 insert, write, and read operations may correspond to the above-described block by block I / Q deinterleaving.
  • block by block I / Q deinterleaving may not be performed on an independent block or may be performed on other blocks.
  • block by block I / Q deinterleaving may be omitted or replaced by another block having the same or similar function.
  • the memory index may be a memory index used in the aforementioned block by block I / Q deinterleaving.
  • Apparatus and method according to the present invention is not limited to the configuration and method of the embodiments described as described above, the above-described embodiments may be selectively all or part of each embodiment so that various modifications can be made It may be configured in combination.
  • the processor-readable recording medium includes all kinds of recording devices that store data that can be read by the processor. Examples of a processor-readable recording medium include ROM, RAM, CD ROM, magnetic tape, floppy disk, optical data storage device, and the like, and also include a carrier wave such as transmission through the Internet.
  • the processor-readable recording medium can also be distributed over network coupled computer systems so that the processor-readable code is stored and executed in a distributed fashion.
  • the present invention has industrial applicability in the field of broadcasting and communication.

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Abstract

La présente invention concerne un procédé d'émission d'un signal de diffusion. Le procédé d'émission du signal de diffusion d'après la présente invention peut comprendre les étapes consistant à : formater des flux d'entrée dans de multiples voies de communication de données (DP) ; coder des données des multiples DP en fonction d'un taux de code pour chaque DP ; générer au moins une trame de signal en mappant les données codées des multiples DP ; puis moduler les données de la trame de signal générée selon une technique de multiplexage par répartition orthogonale de la fréquence (OFDM) et émettre le signal de diffusion contenant les données de la trame de signal modulée.
PCT/KR2014/004191 2013-05-09 2014-05-09 Appareil et procédé d'émission d'un signal de diffusion, appareil et procédé de réception d'un signal de diffusion WO2014182135A1 (fr)

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EP14795181.8A EP2958319B1 (fr) 2013-05-09 2014-05-09 Appareil et procédé d'émission et de réception d'un signal de diffusion
US15/391,589 US10924314B2 (en) 2013-05-09 2016-12-27 Broadcast signal transmission apparatus, broadcast signal reception apparatus, broadcast signal transmission method, and broadcast signal reception method

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US201361825531P 2013-05-21 2013-05-21
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WO2016111429A1 (fr) * 2015-01-05 2016-07-14 엘지전자(주) Appareil de transmission de signaux de diffusion, appareil de réception de signaux de diffusion, procédé de transmission de signaux de diffusion, et procédé de réception de signaux de diffusion
US9602321B2 (en) 2015-01-05 2017-03-21 Lg Electronics Inc. Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method
US9722846B2 (en) 2015-01-05 2017-08-01 Lg Electronics Inc. Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method
US10263822B2 (en) 2015-01-05 2019-04-16 Lg Electronics Inc. Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method
US10601625B2 (en) 2015-01-05 2020-03-24 Lg Electronics Inc. Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method
US10855507B2 (en) 2015-01-05 2020-12-01 Lg Electronics Inc. Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method

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US10924314B2 (en) 2021-02-16
EP2958319A1 (fr) 2015-12-23
US20150349997A1 (en) 2015-12-03
US9577861B2 (en) 2017-02-21
US20170111200A1 (en) 2017-04-20
EP2958319A4 (fr) 2016-12-21
EP2958319B1 (fr) 2018-10-31

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