WO2014161258A1 - Array substrate, display apparatus, and manufacturing method for array substrate - Google Patents

Array substrate, display apparatus, and manufacturing method for array substrate Download PDF

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Publication number
WO2014161258A1
WO2014161258A1 PCT/CN2013/081835 CN2013081835W WO2014161258A1 WO 2014161258 A1 WO2014161258 A1 WO 2014161258A1 CN 2013081835 W CN2013081835 W CN 2013081835W WO 2014161258 A1 WO2014161258 A1 WO 2014161258A1
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WIPO (PCT)
Prior art keywords
common electrode
array substrate
substrate
line
insulating layer
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PCT/CN2013/081835
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French (fr)
Chinese (zh)
Inventor
吴洪江
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Publication of WO2014161258A1 publication Critical patent/WO2014161258A1/en

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • Embodiments of the present invention relate to an array substrate, a display device, and a method of fabricating an array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD display modes mainly include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, and AD-SDS (ADvanced).
  • TN Transmission Nematic
  • VA Very Alignment
  • IPS In-Plane-Switching
  • AD-SDS ADvanced
  • Super Dimension Switch advanced super-dimensional field conversion technology, cartridge ADS
  • the display based on the ADS mode forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals in the liquid crystal cell are directly above the slit electrode and above the electrode.
  • the molecules are capable of rotating, thereby improving the efficiency of the liquid crystal and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push-free water ripple (push Mura), etc. advantage.
  • FIG. 1 is a schematic structural view of a TFT-LCD array substrate of an ADS mode in the prior art, FIG. 1 is a plan view; FIG. 2 is a schematic cross-sectional view of the AA plane of FIG. 1, and the internal structure of the array substrate can be better seen from FIG.
  • the structure includes: a village substrate 1, a common electrode 3 (ie, a plate electrode) formed on the substrate substrate 1, a common electrode line 2, and a scan line 12 (including the gate 4). ) , wherein the common electrode line 2 is electrically connected to the common electrode 3 .
  • a common electrode 3 ie, a plate electrode
  • scan line 12 including the gate 4
  • the structure further includes a gate insulating layer 5, an active layer 7, a data line 11, a source 8, a drain 9, a passivation layer 6, and a plurality of pixel electrodes 10 (i.e., slit electrodes).
  • Each of the array substrates includes a plurality of parallel scan lines 12 and a plurality of parallel data lines 11 perpendicular to the scan lines 12, and a rectangular area formed by the intersection of the data lines 11 and the scan lines 12 is called a pixel area, and each pixel area
  • a thin film transistor in which a thin film transistor is provided with a scanning line connected to the gate of the thin film transistor of the row. As shown in FIG.
  • a schematic structural diagram of a TFT-LCD liquid crystal cell of the prior art ADS mode that is, a structure diagram of a color filter substrate and an array substrate pair box.
  • the color filter layer 21 in the color filter substrate covers the pixel region with a color photoresist as a filter film layer, and each color filter layer can transmit light of one of the primary colors of the red, green and blue primary colors, and the black matrix 22 needs to be covered.
  • the scanning line 12, the data line 11, and the common electrode line 2 light leakage between the pixels is prevented, and the contrast of the three primary colors can be increased.
  • a disadvantage of the prior art is that the black matrix on the color film substrate is overlaid on the common electrode line due to the presence of the common electrode line on the array substrate, resulting in a lower aperture ratio and transmittance of the panel.
  • One object of the present invention is to provide an array substrate, a display device, and an array substrate manufacturing method for increasing the aperture ratio and transmittance of the panel, thereby improving the brightness of the panel.
  • an array substrate including:
  • a drain of the thin film transistor is electrically connected to the pixel electrode, and a source of the thin film transistor is electrically connected to the data line;
  • the projection of the scan line on the substrate substrate and the projection of the common electrode line on the substrate substrate at least partially overlap.
  • the projection of the scan line on the substrate substrate may completely fall within the projection of the common electrode line on the substrate substrate, or the common electrode line is on the substrate substrate.
  • the projection on the top can fall completely within the projection of the scan line on the substrate.
  • the insulating layer is also disposed between the pixel electrode and the common electrode. In one example, the insulating layer covers the common electrode line, the common electrode, and the substrate substrate; the plurality of thin film transistors are located on the insulating layer, and the scan line is located at the common electrode Above the line.
  • the common electrode is located on both sides of the common electrode line and is common to the common The electrode wires are electrically connected.
  • the insulating layer is made of silicon nitride.
  • the array substrate further includes: a passivation layer covering the thin film transistor; the pixel electrode is on the passivation layer, and the pixel electrode is located above the common electrode.
  • the pixel electrode is the same material as the common electrode.
  • the material of the common electrode is indium tin oxide.
  • the thin film transistor includes a gate insulating layer, and the gate insulating layer is further located between the pixel electrode and the common electrode.
  • a display device comprising an array substrate according to any of the embodiments of the present invention and a color filter substrate disposed opposite the array substrate.
  • a black matrix is formed on the color filter substrate, and the black matrix is formed at least in a region opposite to the thin film transistor and the scan line on the array substrate.
  • a further embodiment of the present invention provides a method of fabricating an array substrate, including:
  • a thin film transistor is formed on the insulating layer.
  • the method further includes: forming a passivation layer on the thin film transistor;
  • a plurality of pixel electrodes are formed over the passivation layer over the common electrode.
  • the insulating layer is made of silicon nitride.
  • the projection of the scan line on the substrate substrate and the projection of the common electrode line on the substrate substrate at least partially overlap, and the scan line and the common electrode line are used.
  • the insulating layer is insulated. Therefore, the black matrix of the color filter substrate can only cover the scanning line, so that the line width of the black matrix can be correspondingly reduced, thereby increasing the panel aperture ratio and transmittance.
  • an insulating layer is added over the common electrode, the storage capacitance can be effectively reduced, thereby reducing the charging time of the pixel, and also facilitating the production of a high resolution product.
  • FIG. 1 is a schematic structural view of a TFT-LCD array substrate of a prior art ADS mode
  • Figure 2 is a schematic cross-sectional view of the A-A surface of Figure 1;
  • FIG. 3 is a schematic structural view of a TFT-LCD liquid crystal cell of the prior art ADS mode
  • FIG. 4 is a schematic structural view of an embodiment of an array substrate according to the present invention.
  • Figure 5 is a schematic cross-sectional view of the B-B surface of Figure 4.
  • Figure 6 is a schematic structural view of a liquid crystal cell of the present invention.
  • FIG. 7 is a schematic structural view of another embodiment of the array substrate of the present invention. detailed description
  • an embodiment of the present invention provides an array substrate, a display device, and a method of fabricating an array substrate.
  • the common electrode line is located below the scan line, the line width of the black matrix on the color filter substrate can be correspondingly reduced, thereby increasing the panel aperture ratio and transmittance, and in the scan line and the common
  • the insulation between the electrode lines is used to effectively reduce the storage capacitance, which in turn shortens the charging time of the pixels.
  • the array substrate of the embodiment of the present invention includes a substrate substrate 1 and a plurality of thin film transistors arranged in an array, and further includes:
  • At least one common electrode 3 electrically connected to the common electrode line 2 on the substrate 1;
  • the plurality of thin film transistors are located on the insulating layer 13 and are gated with each row of thin film transistors
  • the four connected scan lines 12 are located above the common electrode line 2.
  • the black matrix 22 of the corresponding color filter substrate only needs to be covered on the scan line 12.
  • the scan line 12 and the common electrode line 2 are arranged in parallel, and the black matrix 22 needs to be over the scan line 12 and the common electrode line 2 . Therefore, the embodiment of the present invention is adopted.
  • the technical solution can effectively reduce the line width of the black matrix in the direction of the scanning line (the dotted line in FIG.
  • the panel aperture ratio and transmittance increase the brightness of the panel. Further, an insulating layer 13 is added to the common electrode 3, so that the storage capacitance can be effectively reduced, thereby reducing the charging time of the pixel, which is advantageous for the manufacture of the high resolution panel.
  • the "lower” and “above” as described herein are relative to the lamination order of the layers from the substrate of the substrate, for example, the layers on the substrate of the substrate are sequentially deposited from bottom to top.
  • the array substrate includes mutually intersecting gate lines 12 and data lines 11 on the substrate substrate 1, and the gate lines 12 and the data lines 11 define a plurality of pixel regions.
  • the above thin film transistors are respectively located in each of the pixel regions.
  • Each of the pixel regions further includes a pixel electrode and a common electrode, and a drain electrode 9 of the thin film transistor is electrically connected to the pixel electrode 10, and a source electrode 8 of the thin film transistor is electrically connected to the data line 11.
  • FIG. 7 is a schematic structural view of an array substrate according to another embodiment of the present invention, in which the common electrode 3 is located on both sides of the common electrode line 2 and electrically connected to the common electrode line 2.
  • each of the common electrode lines 2 can be electrically connected to the common electrodes 3 on both sides thereof, the utilization ratio of the common electrode lines 2 can be improved, and the number of the common electrode lines 2 can be reduced.
  • the material of the insulating layer 13 is silicon nitride.
  • the material of the insulating layer 13 can be variously selected. As long as the common electrode line 2 and the scanning line are prevented from being insulated, a plurality of insulating materials may be selected, preferably silicon nitride is used as the insulating layer 13, for example, An insulating layer is formed by chemical vapor deposition.
  • the array substrate of the embodiment of the present invention further includes:
  • the pixel electrode 10 and the common electrode 3 serve as two plates of the storage capacitor.
  • the insulating layer 13, the gate insulating layer 5, and the passivation layer 6 between the two form a storage capacitor as an insulating medium.
  • the array substrate includes a substrate substrate 1 on the insulating layer 13 on the substrate substrate 1, and may further include: a gate electrode 4 (a part of the scan line), a gate insulating layer 5, and Source layer 7 and so on.
  • the thin film transistor may be a top gate type or a bottom gate type, and an array substrate formed by a bottom gate type thin film transistor as shown in FIG.
  • a scan line layer (a scan line of the scan line layer is in each A pixel region includes a gate electrode 4) formed on the insulating layer 13, a gate insulating layer 5 formed on the scan line layer, an active layer 7 formed on the gate insulating layer 5, and a data line layer formed thereon.
  • the passivation layer 6 covers the entire substrate, and a pixel electrode is formed over the passivation layer 6, above the common electrode 3, and forms a storage capacitor with the common electrode 3.
  • the pixel electrode 10 and the common electrode 3 are made of the same material.
  • the pixel electrode 10 and the common electrode 3 are used as the plates of the storage capacitor, and may be made of a material of the same material, for example, a transparent conductive film, because the common electrode 3 and the pixel electrode 10 above thereof correspond to the pixel region. A higher light transmittance is required, so a transparent conductive film can be selected as the material.
  • the material of the common electrode 3 is indium tin oxide.
  • the material of the pixel electrode 10 and the common electrode 3 may be selected from a transparent conductive material such as indium tin oxide because indium tin oxide has good transmittance and electrical conductivity.
  • the embodiment of the invention further provides a display device comprising any one of the above array substrates.
  • a black matrix is formed on the color filter substrate, and the black matrix is formed at least in a region opposite to the thin film transistor and the scanning line on the array substrate.
  • the display device may be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the display device of the embodiment of the present invention may be a TN mode, a VA mode, an IPS mode, or an ADS mode.
  • the display device formed by the array substrate of the present invention is particularly suitable for the IPS mode and the ADS mode.
  • the embodiment of the invention further relates to a method for manufacturing an array substrate, comprising:
  • Step 101 forming a common electrode layer on the substrate of the village, and forming a common electrode by a mask patterning process
  • Step 102 forming a common electrode line on the substrate substrate at a set scan line position;
  • Step 103 forming an insulating layer covering the common electrode, the common electrode line, and the substrate substrate;
  • Step 104 in the A thin film transistor is formed on the insulating layer.
  • a common electrode is first formed on the array substrate, and a common electrode line is formed at a position of the set scan line, and the common electrode is electrically connected to the common electrode line, and the common electrode line can provide a common voltage to the common electrode.
  • a scan line is formed above the common electrode line, so that the scan line and the common electrode line are in a state of being parallel to each other, and the width of the common electrode line corresponding to the black matrix of the color filter substrate can be reduced, thereby improving the opening of the panel Rate and transmittance, which in turn increases the brightness of the panel.
  • an insulating layer is required to insulate between the common electrode line and the scan line. Therefore, the thickness of the insulating medium between the common electrode and the pixel electrode is increased, the storage capacitance is reduced, and the charging time of the pixel is shortened, which is advantageous for high. Design and production of resolution products.
  • the method further includes:
  • a plurality of pixel electrodes are formed over the passivation layer over the common electrode.
  • the thin film transistor may be of a bottom gate type or a top gate type, as long as the common electrode line is designed under the scan line.
  • the common electrode and the plurality of pixel electrodes above thereof form a storage capacitor. Since the thickness of the insulating medium of the storage capacitor is increased, the storage capacitor is effectively reduced, thereby reducing the charging time of the pixel; the material of the passivation layer can be selected as a transparent resin material. , used to further increase the transmittance.
  • the material of the insulating layer is silicon nitride.
  • the array substrate of the embodiment shown in FIG. 5 has the following main manufacturing processes:
  • a common electrode layer is formed on the substrate of the village, and can be formed by sputtering deposition.
  • the common electrode layer is preferably made of indium tin oxide, and the substrate is selected as a glass substrate; for example, deposited on a glass substrate by sputtering.
  • Depositing a common electrode layer and forming a common through the first mask patterning process (the mask patterning process usually includes cleaning, film formation, coating, exposure, development, dry or wet etching, photoresist stripping, etc.) Electrode
  • a common electrode line at a position of a scan line set on a substrate of the village, for example, depositing a common electrode line layer by sputtering, and forming a common electrode line array at a position corresponding to the scan line by a second mask patterning process grid;
  • the insulating layer is made of silicon nitride (SiNx); for example, forming a layer of nitride by chemical vapor deposition, exposure, etching, and stripping processes.
  • Silicon insulating layer According to a conventional process, a scan line (including a gate electrode) is formed on the insulating layer, and a gate insulating layer covering the scan line, an active layer, a source/drain electrode layer, a passivation layer, and a pixel electrode are sequentially formed in accordance with a conventional process to complete a subsequent process. The entire array substrate is fabricated.
  • the material of the pixel electrode may be indium tin oxide, and the material of the passivation layer may be silicon nitride.
  • the scanning lines and the common electrode lines are arranged in parallel below, so that the line width of the black matrix is reduced, the aperture ratio and transmittance of the panel are improved, and an interlayer insulating layer is formed, thereby increasing the gap between the common electrode and the pixel electrode.
  • the thickness of the insulating medium effectively reduces the storage capacitance, thereby shortening the charging time of the pixel.
  • the present invention is not limited to the specific structure described above.
  • the common electrode line can also be placed above the scan line.
  • the total area occupied by the common electrode line and the scanning line can also be reduced, so that the line width of the black matrix can be reduced.
  • the projection of the scan line on the substrate substrate at least partially overlaps the projection of the common electrode line on the substrate.
  • the projection of the scan line on the substrate of the village may completely fall within the projection of the common electrode line on the substrate of the village, or the projection of the common electrode line on the substrate of the village may completely fall.
  • the entrance scan line is within the projection on the substrate of the village.

Abstract

An array substrate, a display apparatus, and a manufacturing method for the array substrate are provided. The array substrate comprises: an underlayer substrate (1); scanning lines (12) and data lines (11) that cross each other and are located on the underlayer substrate (1), the scanning lines (12) and the data lines (11) defining multiple pixel areas; multiple thin film transistors, arranged in an array and respectively located in each pixel area; pixel electrodes (10), located in the pixel areas, and a common electrode (3); an insulation layer (13), located between the common electrode (3) and the scanning lines (12), an projection of the scanning lines (12) on the underlayer substrate (1) at least partially overlapping an projection of a common electrode line (2) on the underlayer substrate (1).

Description

阵列基板、 显示装置及阵列基板的制造方法 技术领域  Array substrate, display device, and manufacturing method of array substrate
本发明的实施例涉及一种阵列基板、 显示装置及阵列基板的制造方法。 背景技术  Embodiments of the present invention relate to an array substrate, a display device, and a method of fabricating an array substrate. Background technique
在平板显示装置中， 薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, 筒称 TFT-LCD )具有体积小、 功耗低、 制造成本相对较低 和无辐射等特点， 在当前的平板显示器市场占据了主导地位。  Among flat panel display devices, Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, relatively low manufacturing cost and no radiation, and is occupied by the current flat panel display market. The dominant position.
目前， TFT-LCD的显示模式主要有 TN ( Twisted Nematic, 扭曲向列 ) 模式、 VA ( Vertical Alignment, 垂直取向）模式、 IPS ( In-Plane-Switching, 平面方向转换）模式和 AD-SDS ( ADvanced Super Dimension Switch , 高级超 维场转换技术， 筒称 ADS )模式等。  Currently, TFT-LCD display modes mainly include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, and AD-SDS (ADvanced). Super Dimension Switch, advanced super-dimensional field conversion technology, cartridge ADS) mode.
基于 ADS模式的显示器通过同一平面内狭缝电极边缘所产生的电场以 及狭缝电极层与板状电极层间产生的电场形成多维电场， 使液晶盒内狭缝电 极间、 电极正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作 效率并增大了透光效率。 高级超维场转换技术可以提高 TFT-LCD产品的画 面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（ push Mura )等优点。  The display based on the ADS mode forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals in the liquid crystal cell are directly above the slit electrode and above the electrode. The molecules are capable of rotating, thereby improving the efficiency of the liquid crystal and increasing the light transmission efficiency. Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push-free water ripple (push Mura), etc. advantage.
图 1为现有技术的 ADS模式的 TFT-LCD阵列基板结构示意图， 图 1为 俯视图； 图 2为图 1的 A-A面的断面结构示意图， 从图 2可以更好地看到阵 列基板内部结构。 如图 1和图 2所示， 其结构包括： 村底基板 1 , 形成于村 底基板 1之上的公共电极 3 (即板状电极 )、公共电极线 2以及扫描线 12 (包 括栅极 4 ) , 其中， 公共电极线 2与公共电极 3电连接。 该结构还包括栅极 绝缘层 5, 有源层 7, 数据线 11 , 源极 8, 漏极 9, 钝化层 6, 多个像素电极 10 (即狭缝电极） 。 每一个阵列基板包括多条平行的扫描线 12和与扫描线 12垂直的多条平行的数据线 11 ,由数据线 11和扫描线 12交叉形成的矩形区 称为像素区， 每一个像素区内有一个薄膜晶体管， 一行薄膜晶体管设置有一 条与这行的薄膜晶体管的栅极连接的扫描线。 如图 3所示， 现有技术 ADS模式的 TFT-LCD液晶盒的结构示意图， 即 彩膜基板和阵列基板对盒的结构示意图。彩膜基板内的彩色滤光层 21以彩色 光阻作为滤光膜层覆盖于像素区， 每个彩色滤光层可以透过红绿蓝三原色其 中一种原色的光， 而黑矩阵 22需要覆盖在薄膜晶体管、 扫描线 12、 数据线 11及公共电极线 2上以防各像素间漏光， 并且能增加三原色的对比度。 1 is a schematic structural view of a TFT-LCD array substrate of an ADS mode in the prior art, FIG. 1 is a plan view; FIG. 2 is a schematic cross-sectional view of the AA plane of FIG. 1, and the internal structure of the array substrate can be better seen from FIG. As shown in FIG. 1 and FIG. 2, the structure includes: a village substrate 1, a common electrode 3 (ie, a plate electrode) formed on the substrate substrate 1, a common electrode line 2, and a scan line 12 (including the gate 4). ) , wherein the common electrode line 2 is electrically connected to the common electrode 3 . The structure further includes a gate insulating layer 5, an active layer 7, a data line 11, a source 8, a drain 9, a passivation layer 6, and a plurality of pixel electrodes 10 (i.e., slit electrodes). Each of the array substrates includes a plurality of parallel scan lines 12 and a plurality of parallel data lines 11 perpendicular to the scan lines 12, and a rectangular area formed by the intersection of the data lines 11 and the scan lines 12 is called a pixel area, and each pixel area There is a thin film transistor in which a thin film transistor is provided with a scanning line connected to the gate of the thin film transistor of the row. As shown in FIG. 3, a schematic structural diagram of a TFT-LCD liquid crystal cell of the prior art ADS mode, that is, a structure diagram of a color filter substrate and an array substrate pair box. The color filter layer 21 in the color filter substrate covers the pixel region with a color photoresist as a filter film layer, and each color filter layer can transmit light of one of the primary colors of the red, green and blue primary colors, and the black matrix 22 needs to be covered. On the thin film transistor, the scanning line 12, the data line 11, and the common electrode line 2, light leakage between the pixels is prevented, and the contrast of the three primary colors can be increased.
现有技术存在的缺陷在于， 由于阵列基板上公共电极线的存在， 彩膜基 板上黑矩阵就要覆盖在公共电极线上方， 导致面板的开口率和透过率较低。 发明内容  A disadvantage of the prior art is that the black matrix on the color film substrate is overlaid on the common electrode line due to the presence of the common electrode line on the array substrate, resulting in a lower aperture ratio and transmittance of the panel. Summary of the invention
本发明的目的之一是提供一种阵列基板、 显示装置及阵列基板的制造方 法， 用以提高面板的开口率和透过率， 进而提高面板的亮度。  SUMMARY OF THE INVENTION One object of the present invention is to provide an array substrate, a display device, and an array substrate manufacturing method for increasing the aperture ratio and transmittance of the panel, thereby improving the brightness of the panel.
根据本发明的一个实施例提供一种阵列基板， 包括：  According to an embodiment of the invention, an array substrate is provided, including:
村底基板；  Village substrate;
位于所述村底基板上的相互交叉的栅线和数据线， 所述栅线和所述数据 线限定出多个像素区；  Intersecting gate lines and data lines on the substrate of the village, the gate lines and the data lines defining a plurality of pixel regions;
阵列排布的多个薄膜晶体管， 分别位于每个像素区内；  a plurality of thin film transistors arranged in the array, respectively located in each pixel region;
位于每个像素区内的像素电极和公共电极， 所述薄膜晶体管的漏极与所 述像素电极电相连， 所述薄膜晶体管的源极与所述数据线电相连；  a pixel electrode and a common electrode located in each pixel region, a drain of the thin film transistor is electrically connected to the pixel electrode, and a source of the thin film transistor is electrically connected to the data line;
公共电极线， 与所述公共电极电连接；  a common electrode line electrically connected to the common electrode;
绝缘层， 位于所述公共电极和所述扫描线之间，  An insulating layer between the common electrode and the scan line,
其中， 所述扫描线在所述村底基板上的投影与所述公共电极线在所述村 底基板上的投影至少部分重叠。  The projection of the scan line on the substrate substrate and the projection of the common electrode line on the substrate substrate at least partially overlap.
在一个示例中， 所述扫描线在所述村底基板上的投影可以完全落入所述 公共电极线在所述村底基板上的投影内， 或者所述公共电极线在所述村底基 板上的投影可以完全落入所述扫描线在所述村底基板上的投影内。  In one example, the projection of the scan line on the substrate substrate may completely fall within the projection of the common electrode line on the substrate substrate, or the common electrode line is on the substrate substrate. The projection on the top can fall completely within the projection of the scan line on the substrate.
在一个示例中 ,所述绝缘层还设置于所述像素电极和所述公共电极之间。 在一个示例中， 所述绝缘层覆盖所述公共电极线、 所述公共电极和所述 村底基板； 所述多个薄膜晶体管位于所述绝缘层上， 并且所述扫描线位于所 述公共电极线的上方。  In one example, the insulating layer is also disposed between the pixel electrode and the common electrode. In one example, the insulating layer covers the common electrode line, the common electrode, and the substrate substrate; the plurality of thin film transistors are located on the insulating layer, and the scan line is located at the common electrode Above the line.
在一个示例中， 所述公共电极位于所述公共电极线的两侧并与所述公共 电极线电连接。 In one example, the common electrode is located on both sides of the common electrode line and is common to the common The electrode wires are electrically connected.
在一个示例中， 所述绝缘层的材质为氮化硅。  In one example, the insulating layer is made of silicon nitride.
在一个示例中， 该阵列基板还包括： 覆盖所述薄膜晶体管的钝化层； 所 述像素电极位于所述钝化层上， 且所述像素电极位于所述公共电极的上方。  In one example, the array substrate further includes: a passivation layer covering the thin film transistor; the pixel electrode is on the passivation layer, and the pixel electrode is located above the common electrode.
在一个示例中， 所述像素电极与所述公共电极的材质相同。  In one example, the pixel electrode is the same material as the common electrode.
在一个示例中， 所述公共电极的材质为氧化铟锡。  In one example, the material of the common electrode is indium tin oxide.
在一个示例中， 所述薄膜晶体管包括栅极绝缘层， 且所述栅极绝缘层还 位于所述像素电极和所述公共电极之间。  In one example, the thin film transistor includes a gate insulating layer, and the gate insulating layer is further located between the pixel electrode and the common electrode.
根据本发明的另一个实施例提供一种显示装置， 包括根据本发明任一实 施例的阵列基板以及与所述阵列基板相对设置的彩膜基板。  According to another embodiment of the present invention, there is provided a display device comprising an array substrate according to any of the embodiments of the present invention and a color filter substrate disposed opposite the array substrate.
在一个示例中， 所述彩膜基板上形成有黑矩阵， 所述黑矩阵的形成区域 至少与所述阵列基板上的薄膜晶体管和扫描线相对。  In one example, a black matrix is formed on the color filter substrate, and the black matrix is formed at least in a region opposite to the thin film transistor and the scan line on the array substrate.
本发明的再一个实施例提供一种阵列基板的制造方法， 包括：  A further embodiment of the present invention provides a method of fabricating an array substrate, including:
形成位于村底基板之上的公共电极层， 并通过掩模构图工艺形成公共电 极；  Forming a common electrode layer on the substrate of the substrate, and forming a common electrode by a mask patterning process;
在设定的扫描线位置形成位于所述村底基板上的公共电极线；  Forming a common electrode line on the substrate of the village at a set scan line position;
形成覆盖所述公共电极、 公共电极线和村底基板的绝缘层；  Forming an insulating layer covering the common electrode, the common electrode line, and the substrate substrate;
在所述绝缘层上形成薄膜晶体管。  A thin film transistor is formed on the insulating layer.
在一个示例中， 在所述绝缘层上形成薄膜晶体管之后， 该方法还包括： 形成位于所述薄膜晶体管上的钝化层；  In one example, after forming a thin film transistor on the insulating layer, the method further includes: forming a passivation layer on the thin film transistor;
形成位于所述钝化层之上， 位于所述公共电极上方的多个像素电极。 在一个示例中， 所述绝缘层的材质为氮化硅。  A plurality of pixel electrodes are formed over the passivation layer over the common electrode. In one example, the insulating layer is made of silicon nitride.
在本发明实施例的阵列基板中， 由于扫描线在所述村底基板上的投影与 所述公共电极线在所述村底基板上的投影至少部分重叠， 并且扫描线与公共 电极线间采用绝缘层进行绝缘， 因此， 彩膜基板的黑矩阵只覆盖至扫描线上 方即可， 因此黑矩阵的线宽可以相应减小，进而提高了面板开口率和透过率。 此外， 由于公共电极上方增加了一层绝缘层， 因此， 可以有效降低存储电容， 从而减小像素的充电时间， 也利于制作高解像度的产品。 附图说明 为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。 In the array substrate of the embodiment of the present invention, the projection of the scan line on the substrate substrate and the projection of the common electrode line on the substrate substrate at least partially overlap, and the scan line and the common electrode line are used. The insulating layer is insulated. Therefore, the black matrix of the color filter substrate can only cover the scanning line, so that the line width of the black matrix can be correspondingly reduced, thereby increasing the panel aperture ratio and transmittance. In addition, since an insulating layer is added over the common electrode, the storage capacitance can be effectively reduced, thereby reducing the charging time of the pixel, and also facilitating the production of a high resolution product. DRAWINGS In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, rather than to the present invention. limit.
图 1为现有技术 ADS模式的 TFT-LCD阵列基板结构示意图；  1 is a schematic structural view of a TFT-LCD array substrate of a prior art ADS mode;
图 2为图 1的 A-A面的断面结构示意图；  Figure 2 is a schematic cross-sectional view of the A-A surface of Figure 1;
图 3为现有技术 ADS模式的 TFT-LCD液晶盒的结构示意图；  3 is a schematic structural view of a TFT-LCD liquid crystal cell of the prior art ADS mode;
图 4为本发明阵列基板一实施例结构示意图；  4 is a schematic structural view of an embodiment of an array substrate according to the present invention;
图 5为图 4的 B-B面的断面结构示意图；  Figure 5 is a schematic cross-sectional view of the B-B surface of Figure 4;
图 6为本发明液晶盒的结构示意图；  Figure 6 is a schematic structural view of a liquid crystal cell of the present invention;
图 7为本发明阵列基板另一实施例结构示意图。 具体实施方式  FIG. 7 is a schematic structural view of another embodiment of the array substrate of the present invention. detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
为了提高面板开口率， 本发明实施例提供了一种阵列基板、 显示装置及 阵列基板的制造方法。在该技术方案中， 由于公共电极线位于扫描线的下方， 因此， 彩膜基板上的黑矩阵的线宽可以相应减小， 进而提高了面板开口率和 透过率， 并且在扫描线和公共电极线之间采用绝缘层隔离， 有效降低了存储 电容， 进而缩短了像素的充电时间。 为使本发明的目的、 技术方案和优点更 加清楚， 以下举具体实施例对本发明作进一步详细说明。  In order to increase the panel aperture ratio, an embodiment of the present invention provides an array substrate, a display device, and a method of fabricating an array substrate. In this technical solution, since the common electrode line is located below the scan line, the line width of the black matrix on the color filter substrate can be correspondingly reduced, thereby increasing the panel aperture ratio and transmittance, and in the scan line and the common The insulation between the electrode lines is used to effectively reduce the storage capacitance, which in turn shortens the charging time of the pixels. In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below.
图 4为根据本发明实施例的阵列基板的结构示意图， 图 5为图 4的 B-B 面的断面结构示意图。 结合图 4和图 5所示， 本发明实施例的阵列基板包括 村底基板 1和阵列排布的多个薄膜晶体管， 还包括：  4 is a schematic structural view of an array substrate according to an embodiment of the present invention, and FIG. 5 is a schematic cross-sectional structural view of the B-B surface of FIG. 4. As shown in FIG. 4 and FIG. 5, the array substrate of the embodiment of the present invention includes a substrate substrate 1 and a plurality of thin film transistors arranged in an array, and further includes:
位于村底基板 1上的公共电极线 2;  a common electrode line 2 located on the substrate 1 of the village;
位于村底基板 1上与公共电极线 2电连接的至少一个公共电极 3;  At least one common electrode 3 electrically connected to the common electrode line 2 on the substrate 1;
覆盖公共电极线 2、 公共电极 3和村底基板 1的绝缘层 13;  Covering the common electrode line 2, the common electrode 3 and the insulating layer 13 of the substrate substrate 1;
所述多个薄膜晶体管位于绝缘层 13上，并且与每一行薄膜晶体管的栅极 4连接的扫描线 12位于公共电极线 2的上方。 The plurality of thin film transistors are located on the insulating layer 13 and are gated with each row of thin film transistors The four connected scan lines 12 are located above the common electrode line 2.
在本发明实施例中， 由于公共电极线 2位于扫描线 12的下方， 因此， 如 图 6所示，本发明液晶盒结构示意图，对应的彩膜基板的黑矩阵 22只需覆盖 在扫描线 12的上方， 而现有技术中， 如图 1所示， 扫描线 12和公共电极线 2平行排列， 黑矩阵 22需要覆盖在扫描线 12和公共电极线 2的上方， 因此， 采用本发明实施例的技术方案，可以有效减小黑矩阵在扫描线方向的线宽（图 6 中的虚线部分为现有技术的黑矩阵的宽度， 可见本发明实施例的黑矩阵的 线宽相应减少） ， 提高了面板开口率和透过率， 进而提高了面板的亮度。 此 夕卜， 公共电极 3上增加了一层绝缘层 13 , 因此， 可以有效降低存储电容， 进 而减少像素的充电时间， 利于高解像度面板的制造。  In the embodiment of the present invention, since the common electrode line 2 is located below the scan line 12, as shown in FIG. 6, the structure of the liquid crystal cell of the present invention, the black matrix 22 of the corresponding color filter substrate only needs to be covered on the scan line 12. In the prior art, as shown in FIG. 1 , the scan line 12 and the common electrode line 2 are arranged in parallel, and the black matrix 22 needs to be over the scan line 12 and the common electrode line 2 . Therefore, the embodiment of the present invention is adopted. The technical solution can effectively reduce the line width of the black matrix in the direction of the scanning line (the dotted line in FIG. 6 is the width of the black matrix of the prior art, and the line width of the black matrix in the embodiment of the present invention is correspondingly reduced), The panel aperture ratio and transmittance increase the brightness of the panel. Further, an insulating layer 13 is added to the common electrode 3, so that the storage capacitance can be effectively reduced, thereby reducing the charging time of the pixel, which is advantageous for the manufacture of the high resolution panel.
这里所述的 "下方" 和 "上方" 是相对于从村底基板上各层的层叠顺序 而言的， 例如， 村底基板上的各层从下至上依次沉积。  The "lower" and "above" as described herein are relative to the lamination order of the layers from the substrate of the substrate, for example, the layers on the substrate of the substrate are sequentially deposited from bottom to top.
例如，该阵列基板包括位于村底基板 1上的相互交叉的栅线 12和数据线 11 , 栅线 12和数据线 11限定出多个像素区。 上述薄膜晶体管分别位于每个 像素区内。 每个像素区还包括像素电极和公共电极， 薄膜晶体管的漏极 9与 像素电极 10电连接， 薄膜晶体管的源极 8与数据线 11电连接。  For example, the array substrate includes mutually intersecting gate lines 12 and data lines 11 on the substrate substrate 1, and the gate lines 12 and the data lines 11 define a plurality of pixel regions. The above thin film transistors are respectively located in each of the pixel regions. Each of the pixel regions further includes a pixel electrode and a common electrode, and a drain electrode 9 of the thin film transistor is electrically connected to the pixel electrode 10, and a source electrode 8 of the thin film transistor is electrically connected to the data line 11.
例如， 图 7为本发明另一实施例的阵列基板的结构示意图， 其中公共电 极 3位于公共电极线 2的两侧并与公共电极线 2电连接。  For example, FIG. 7 is a schematic structural view of an array substrate according to another embodiment of the present invention, in which the common electrode 3 is located on both sides of the common electrode line 2 and electrically connected to the common electrode line 2.
在本发明实施例中， 每一条公共电极线 2可以与它两侧的公共电极 3电 连接， 可以提高公共电极线 2的利用率， 并可以减少公共电极线 2的制作个 数。  In the embodiment of the present invention, each of the common electrode lines 2 can be electrically connected to the common electrodes 3 on both sides thereof, the utilization ratio of the common electrode lines 2 can be improved, and the number of the common electrode lines 2 can be reduced.
例如， 如图 5所示， 绝缘层 13的材质为氮化硅。  For example, as shown in Fig. 5, the material of the insulating layer 13 is silicon nitride.
在本发明实施例中，绝缘层 13的材质可以有多种选择，只要防止公共电 极线 2和扫描线绝缘即可， 所以可以选用多种绝缘材料， 优选氮化硅作为绝 缘层 13, 例如可以采用化学气相沉积的方法形成绝缘层。  In the embodiment of the present invention, the material of the insulating layer 13 can be variously selected. As long as the common electrode line 2 and the scanning line are prevented from being insulated, a plurality of insulating materials may be selected, preferably silicon nitride is used as the insulating layer 13, for example, An insulating layer is formed by chemical vapor deposition.
例如， 如图 5所示， 本发明实施例的阵列基板， 还包括：  For example, as shown in FIG. 5, the array substrate of the embodiment of the present invention further includes:
覆盖薄膜晶体管的钝化层 6;  Covering the passivation layer of the thin film transistor 6;
位于钝化层 6上的多个像素电极 10, 像素电极 10位于公共电极 3的上 方。  A plurality of pixel electrodes 10 on the passivation layer 6, the pixel electrodes 10 being located above the common electrode 3.
在本发明实施例中， 像素电极 10和公共电极 3作为存储电容两个极板， 两者之间的绝缘层 13、栅极绝缘层 5及钝化层 6作为绝缘介质形成存储电容。 如图 5所示， 所述阵列基板包括村底基板 1 , 在村底基板 1上的绝缘层 13之 上， 可进一步包括： 栅极 4 (扫描线的一部分） 、 栅极绝缘层 5、 有源层 7 等。 所述薄膜晶体管可以为顶栅型， 也可以为底栅型， 如图 5所示的底栅型 薄膜晶体管形成的阵列基板， 其结构具体为： 扫描线层（扫描线层的扫描线 在每一个像素区内包括栅极 4 )形成于绝缘层 13之上， 栅极绝缘层 5形成于 扫描线层之上， 有源层 7形成于栅极绝缘层 5之上， 数据线层形成于有源层 7之上， 钝化层 6覆盖整个基板， 像素电极形成于钝化层 6之上， 位于公共 电极 3的上方， 并与公共电极 3形成存储电容。 In the embodiment of the present invention, the pixel electrode 10 and the common electrode 3 serve as two plates of the storage capacitor. The insulating layer 13, the gate insulating layer 5, and the passivation layer 6 between the two form a storage capacitor as an insulating medium. As shown in FIG. 5, the array substrate includes a substrate substrate 1 on the insulating layer 13 on the substrate substrate 1, and may further include: a gate electrode 4 (a part of the scan line), a gate insulating layer 5, and Source layer 7 and so on. The thin film transistor may be a top gate type or a bottom gate type, and an array substrate formed by a bottom gate type thin film transistor as shown in FIG. 5, and the structure thereof is specifically: a scan line layer (a scan line of the scan line layer is in each A pixel region includes a gate electrode 4) formed on the insulating layer 13, a gate insulating layer 5 formed on the scan line layer, an active layer 7 formed on the gate insulating layer 5, and a data line layer formed thereon. Above the source layer 7, the passivation layer 6 covers the entire substrate, and a pixel electrode is formed over the passivation layer 6, above the common electrode 3, and forms a storage capacitor with the common electrode 3.
例如， 如图 6所示， 像素电极 10与公共电极 3的材质相同。  For example, as shown in Fig. 6, the pixel electrode 10 and the common electrode 3 are made of the same material.
在本发明实施例中，像素电极 10和公共电极 3作为存储电容的极板，可 以选用同一材质的材料制成， 例如为透明导电膜， 由于公共电极 3及其上方 的像素电极 10对应像素区，需要较高的光透过率， 因此可以选用透明的导电 膜作为其材质。  In the embodiment of the present invention, the pixel electrode 10 and the common electrode 3 are used as the plates of the storage capacitor, and may be made of a material of the same material, for example, a transparent conductive film, because the common electrode 3 and the pixel electrode 10 above thereof correspond to the pixel region. A higher light transmittance is required, so a transparent conductive film can be selected as the material.
例如， 公共电极 3的材质为氧化铟锡。  For example, the material of the common electrode 3 is indium tin oxide.
在本发明实施例中，像素电极 10和公共电极 3的材质都可以选用透明导 电材料， 例如氧化铟锡， 因为氧化铟锡具有良好的透过率和导电性能。  In the embodiment of the present invention, the material of the pixel electrode 10 and the common electrode 3 may be selected from a transparent conductive material such as indium tin oxide because indium tin oxide has good transmittance and electrical conductivity.
本发明实施例还提供了一种显示装置， 其包括上述任意一种阵列基板。 例如， 所述彩膜基板上形成有黑矩阵， 所述黑矩阵的形成区域至少与所述阵 列基板上的薄膜晶体管和扫描线相对。  The embodiment of the invention further provides a display device comprising any one of the above array substrates. For example, a black matrix is formed on the color filter substrate, and the black matrix is formed at least in a region opposite to the thin film transistor and the scanning line on the array substrate.
所述显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液 晶显示器、 数码相框、 手机、 平板电脑等具有任何显示功能的产品或部件。 本发明实施例的显示装置可以为 TN模式、 VA模式、 IPS模式或 ADS模式 等。 本发明的阵列基板形成的显示装置尤其适用于 IPS模式和 ADS模式。  The display device may be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like. The display device of the embodiment of the present invention may be a TN mode, a VA mode, an IPS mode, or an ADS mode. The display device formed by the array substrate of the present invention is particularly suitable for the IPS mode and the ADS mode.
本发明实施例还涉及一种阵列基板的制造方法， 包括：  The embodiment of the invention further relates to a method for manufacturing an array substrate, comprising:
步骤 101、 形成位于村底基板之上的公共电极层， 并通过掩模构图工艺 形成公共电极；  Step 101, forming a common electrode layer on the substrate of the village, and forming a common electrode by a mask patterning process;
步骤 102、在设定的扫描线位置形成位于所述村底基板上的公共电极线； 步骤 103、 形成覆盖所述公共电极、 公共电极线和村底基板的绝缘层； 步骤 104、 在所述绝缘层上形成薄膜晶体管。 在本发明实施例中， 首先在阵列基板上形成公共电极， 并在设定的扫描 线的位置形成公共电极线， 公共电极与公共电极线电连接， 公共电极线可以 提供给公共电极一个公共电压， 在公共电极线的上方形成扫描线， 这样就使 得扫描线和公共电极线处于上下平行的状态， 彩膜基板黑矩阵本应对应的公 共电极线的宽度可以减少， 因此， 可以提高面板的开口率和透过率， 进而提 高面板的亮度。 此外， 公共电极线和扫描线之间需采用绝缘层将两者绝缘， 因此， 公共电极和像素电极间的绝缘介质的厚度增加， 降低了存储电容， 进 而缩短了像素的充电时间， 有利于高解像度产品的设计和制作。 Step 102, forming a common electrode line on the substrate substrate at a set scan line position; Step 103, forming an insulating layer covering the common electrode, the common electrode line, and the substrate substrate; Step 104, in the A thin film transistor is formed on the insulating layer. In the embodiment of the present invention, a common electrode is first formed on the array substrate, and a common electrode line is formed at a position of the set scan line, and the common electrode is electrically connected to the common electrode line, and the common electrode line can provide a common voltage to the common electrode. A scan line is formed above the common electrode line, so that the scan line and the common electrode line are in a state of being parallel to each other, and the width of the common electrode line corresponding to the black matrix of the color filter substrate can be reduced, thereby improving the opening of the panel Rate and transmittance, which in turn increases the brightness of the panel. In addition, an insulating layer is required to insulate between the common electrode line and the scan line. Therefore, the thickness of the insulating medium between the common electrode and the pixel electrode is increased, the storage capacitance is reduced, and the charging time of the pixel is shortened, which is advantageous for high. Design and production of resolution products.
例如， 所述的阵列基板的制造方法， 在所述绝缘层上形成薄膜晶体管之 后， 还包括：  For example, after the method for fabricating the array substrate, after the thin film transistor is formed on the insulating layer, the method further includes:
形成位于所述薄膜晶体管上的钝化层；  Forming a passivation layer on the thin film transistor;
形成位于所述钝化层之上， 位于所述公共电极上方的多个像素电极。 在本发明实施例中， 薄膜晶体管的制作方法与现有技术一致， 薄膜晶体 管可以为底栅型， 也可以为顶栅型的， 只要将公共电极线设计在扫描线的下 方即可。 公共电极及其上方的多个像素电极形成存储电容， 由于存储电容的 绝缘介质的厚度增加， 因此， 存储电容有效降低， 进而减少了像素的充电时 间； 钝化层的材质可以选为透明树脂材料， 用于进一步提高透过率。  A plurality of pixel electrodes are formed over the passivation layer over the common electrode. In the embodiment of the present invention, the fabrication method of the thin film transistor is consistent with the prior art. The thin film transistor may be of a bottom gate type or a top gate type, as long as the common electrode line is designed under the scan line. The common electrode and the plurality of pixel electrodes above thereof form a storage capacitor. Since the thickness of the insulating medium of the storage capacitor is increased, the storage capacitor is effectively reduced, thereby reducing the charging time of the pixel; the material of the passivation layer can be selected as a transparent resin material. , used to further increase the transmittance.
例如， 在所述的阵列基板的制造方法中， 所述绝缘层的材质为氮化硅。 图 5中所示实施例的阵列基板， 其主要制作工艺流程如下：  For example, in the method of manufacturing an array substrate, the material of the insulating layer is silicon nitride. The array substrate of the embodiment shown in FIG. 5 has the following main manufacturing processes:
在村底基板上形成一层公共电极层， 可以采用溅射沉积的方法形成， 公 共电极层优选的材质为氧化铟锡， 村底基板选为玻璃基板； 例如， 通过溅射 沉积在玻璃基板上沉积一层公共电极层， 并通过第一次掩模构图工艺 （掩模 构图工艺通常包括清洗、 成膜、 涂布、 曝光、 显影、 干刻或湿刻、 光刻胶剥 离等工序）形成公共电极；  A common electrode layer is formed on the substrate of the village, and can be formed by sputtering deposition. The common electrode layer is preferably made of indium tin oxide, and the substrate is selected as a glass substrate; for example, deposited on a glass substrate by sputtering. Depositing a common electrode layer and forming a common through the first mask patterning process (the mask patterning process usually includes cleaning, film formation, coating, exposure, development, dry or wet etching, photoresist stripping, etc.) Electrode
在村底基板上设定的扫描线的位置形成公共电极线， 例如， 通过溅射沉 积一层公共电极线层， 并通过第二次掩模构图工艺在扫描线对应的位置形成 公共电极线阵列网格；  Forming a common electrode line at a position of a scan line set on a substrate of the village, for example, depositing a common electrode line layer by sputtering, and forming a common electrode line array at a position corresponding to the scan line by a second mask patterning process grid;
形成覆盖公共电极、 公共电极线及村底基板的绝缘层， 例如， 绝缘层的 材质为氮化硅（SiNx )； 例如， 通过化学气相沉积、 曝光、 刻蚀、 剥离工艺， 形成一层氮化硅绝缘层； 按传统工艺， 在绝缘层上形成扫描线（包括栅极） ， 并按传统工艺依次 形成覆盖扫描线的栅绝缘层、 有源层、 源漏电极层、 钝化层及像素电极完成 后续工艺从而完成整个阵列基板制作， 其中， 像素电极的材质可以为氧化铟 锡， 钝化层的材质可以为氮化硅。 Forming an insulating layer covering the common electrode, the common electrode line, and the substrate substrate. For example, the insulating layer is made of silicon nitride (SiNx); for example, forming a layer of nitride by chemical vapor deposition, exposure, etching, and stripping processes. Silicon insulating layer; According to a conventional process, a scan line (including a gate electrode) is formed on the insulating layer, and a gate insulating layer covering the scan line, an active layer, a source/drain electrode layer, a passivation layer, and a pixel electrode are sequentially formed in accordance with a conventional process to complete a subsequent process. The entire array substrate is fabricated. The material of the pixel electrode may be indium tin oxide, and the material of the passivation layer may be silicon nitride.
可见， 扫描线和公共电极线上下平行排列， 使得黑矩阵的线宽减小， 提 高了面板的开口率和透过率， 并且由于制作了一层绝缘层， 因此增加了公共 电极和像素电极间的绝缘介质的厚度， 有效降低了存储电容， 进而缩短了像 素的充电时间。  It can be seen that the scanning lines and the common electrode lines are arranged in parallel below, so that the line width of the black matrix is reduced, the aperture ratio and transmittance of the panel are improved, and an interlayer insulating layer is formed, thereby increasing the gap between the common electrode and the pixel electrode. The thickness of the insulating medium effectively reduces the storage capacitance, thereby shortening the charging time of the pixel.
虽然以上实施例中以扫描线位于公共电极线上方的示例进行了说明， 然 而， 本发明并不限于上述具体结构。 例如， 公共电极线也可以设置在扫描线 的上方。 在公共电极线在扫描线的上方的情况下， 也可以减少公共电极线和 扫描线所占的总面积， 从而能够减少黑矩阵的线宽。 因此， 根据本发明的实 施例， 扫描线在村底基板上的投影与公共电极线在村底基板上的投影至少部 分重叠。 例如， 为了进一步减少黑矩阵的线宽， 扫描线在村底基板上的投影 可以完全落入公共电极线在村底基板上的投影内， 或者公共电极线在村底基 板上的投影可以完全落入扫描线在村底基板上的投影内。  Although the above embodiment has been described with an example in which the scanning line is located above the common electrode line, the present invention is not limited to the specific structure described above. For example, the common electrode line can also be placed above the scan line. In the case where the common electrode line is above the scanning line, the total area occupied by the common electrode line and the scanning line can also be reduced, so that the line width of the black matrix can be reduced. Thus, in accordance with an embodiment of the present invention, the projection of the scan line on the substrate substrate at least partially overlaps the projection of the common electrode line on the substrate. For example, in order to further reduce the line width of the black matrix, the projection of the scan line on the substrate of the village may completely fall within the projection of the common electrode line on the substrate of the village, or the projection of the common electrode line on the substrate of the village may completely fall. The entrance scan line is within the projection on the substrate of the village.
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。  The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

权利要求书 claims
1、 一种阵列基板， 包括： 1. An array substrate, including:
村底基板； Village base board;
位于所述村底基板上的相互交叉的栅线和数据线， 所述栅线和所述数据 线限定出多个像素区； Intersecting gate lines and data lines located on the base substrate, the gate lines and the data lines defining a plurality of pixel areas;
阵列排布的多个薄膜晶体管， 分别位于每个像素区内； Multiple thin film transistors arranged in an array are located in each pixel area;
位于每个像素区内的像素电极和公共电极， 所述薄膜晶体管的漏极与所 述像素电极电相连， 所述薄膜晶体管的源极与所述数据线电相连； The pixel electrode and the common electrode located in each pixel area, the drain of the thin film transistor is electrically connected to the pixel electrode, and the source of the thin film transistor is electrically connected to the data line;
公共电极线， 与所述公共电极电连接； A common electrode line, electrically connected to the common electrode;
绝缘层， 位于所述公共电极和所述扫描线之间， Insulating layer, located between the common electrode and the scan line,
其中， 所述扫描线在所述村底基板上的投影与所述公共电极线在所述村 底基板上的投影至少部分重叠。 Wherein, the projection of the scan line on the base substrate at least partially overlaps with the projection of the common electrode line on the base substrate.
2、 根据权利要求 1所述的阵列基板， 其中， 2. The array substrate according to claim 1, wherein,
所述扫描线在所述村底基板上的投影可以完全落入所述公共电极线在所 述村底基板上的投影内， 或者所述公共电极线在所述村底基板上的投影可以 完全落入所述扫描线在所述村底基板上的投影内。 The projection of the scan line on the bottom substrate may completely fall within the projection of the common electrode line on the bottom substrate, or the projection of the common electrode line on the bottom substrate may completely fall within the projection of the common electrode line on the bottom substrate. falls within the projection of the scan line on the bottom substrate.
3、 根据权利要求 1或 2所述的阵列基板， 其中， 3. The array substrate according to claim 1 or 2, wherein,
所述绝缘层还设置于所述像素电极和所述公共电极之间。 The insulating layer is also disposed between the pixel electrode and the common electrode.
4、 根据权利要求 1-3中任一项所述的阵列基板， 其中， 4. The array substrate according to any one of claims 1-3, wherein,
所述绝缘层覆盖所述公共电极线、 所述公共电极和所述村底基板； 所述多个薄膜晶体管位于所述绝缘层上， 并且所述扫描线位于所述公共 电极线的上方。 The insulating layer covers the common electrode line, the common electrode and the base substrate; the plurality of thin film transistors are located on the insulating layer, and the scan line is located above the common electrode line.
5、 如权利要求 1-4中任一项所述的阵列基板， 其中， 所述公共电极位于 所述公共电极线的两侧并与所述公共电极线电连接。 5. The array substrate according to any one of claims 1 to 4, wherein the common electrode is located on both sides of the common electrode line and is electrically connected to the common electrode line.
6、 如权利要求 1-5中任一项所述的阵列基板， 其中， 所述绝缘层的材质 为氮化娃。 6. The array substrate according to any one of claims 1 to 5, wherein the material of the insulating layer is silicon nitride.
7、 如权利要求 1-6中任一项所述的阵列基板， 还包括： 7. The array substrate according to any one of claims 1-6, further comprising:
覆盖所述薄膜晶体管的钝化层； a passivation layer covering the thin film transistor;
所述像素电极位于所述钝化层上， 且所述像素电极位于所述公共电极的 上方。 The pixel electrode is located on the passivation layer, and the pixel electrode is located on the common electrode. above.
8、 如权利要求 1-7中任一项所述的阵列基板， 其中， 所述像素电极与所 述公共电极的材质相同。 8. The array substrate according to any one of claims 1 to 7, wherein the pixel electrode and the common electrode are made of the same material.
9、 如权利要求 1-8中任一项所述的阵列基板， 其中， 所述公共电极的材 质为氧化铟锡。 9. The array substrate according to any one of claims 1 to 8, wherein the common electrode is made of indium tin oxide.
10、 如权利要求 7所述的阵列基板， 其中， 所述薄膜晶体管包括栅极绝 缘层， 且所述栅极绝缘层还位于所述像素电极和所述公共电极之间。 10. The array substrate of claim 7, wherein the thin film transistor includes a gate insulating layer, and the gate insulating layer is further located between the pixel electrode and the common electrode.
11、一种显示装置， 包括如权利要求 1-10中任一项所述的阵列基板以及 与所述阵列基板相对设置的彩膜基板。 11. A display device, comprising the array substrate according to any one of claims 1-10 and a color filter substrate arranged opposite to the array substrate.
12、如权利要求 11所述的显示装置， 其中， 所述彩膜基板上形成有黑矩 阵， 所述黑矩阵的形成区域至少与所述阵列基板上的薄膜晶体管和扫描线相 对。 12. The display device according to claim 11, wherein a black matrix is formed on the color filter substrate, and the formation area of the black matrix is at least opposite to the thin film transistors and scanning lines on the array substrate.
13、 一种阵列基板的制造方法， 包括： 13. A method for manufacturing an array substrate, including:
形成位于村底基板之上的公共电极层， 并通过掩模构图工艺形成公共电 极； Form a common electrode layer located on the bottom substrate, and form the common electrode through a mask patterning process;
在设定的扫描线位置形成位于所述村底基板上的公共电极线； 形成覆盖所述公共电极、 公共电极线和村底基板的绝缘层； Forming a common electrode line on the bottom substrate at a set scan line position; forming an insulating layer covering the common electrode, the common electrode line and the bottom substrate;
在所述绝缘层上形成薄膜晶体管。 A thin film transistor is formed on the insulating layer.
14、如权利要求 13所述的阵列基板的制造方法， 其中， 在所述绝缘层上 形成薄膜晶体管之后， 该方法还包括： 14. The method of manufacturing an array substrate according to claim 13, wherein after forming a thin film transistor on the insulating layer, the method further includes:
形成位于所述薄膜晶体管上的钝化层； forming a passivation layer on the thin film transistor;
形成位于所述钝化层之上， 位于所述公共电极上方的多个像素电极。 A plurality of pixel electrodes are formed on the passivation layer and above the common electrode.
15、 如权利要求 13或 14所述的阵列基板的制造方法， 其中， 所述绝缘 层的材质为氮化硅。 15. The method of manufacturing an array substrate according to claim 13 or 14, wherein the material of the insulating layer is silicon nitride.
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