WO2014153797A1 - Drive circuit, drive method and display device - Google Patents

Drive circuit, drive method and display device Download PDF

Info

Publication number
WO2014153797A1
WO2014153797A1 PCT/CN2013/074491 CN2013074491W WO2014153797A1 WO 2014153797 A1 WO2014153797 A1 WO 2014153797A1 CN 2013074491 W CN2013074491 W CN 2013074491W WO 2014153797 A1 WO2014153797 A1 WO 2014153797A1
Authority
WO
WIPO (PCT)
Prior art keywords
shift register
gate
display area
driving circuit
lines
Prior art date
Application number
PCT/CN2013/074491
Other languages
French (fr)
Chinese (zh)
Inventor
胡理科
祁小敬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2014153797A1 publication Critical patent/WO2014153797A1/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0221—Addressing of scan or signal lines with use of split matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a driving circuit, a driving method, and a display device. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • OLED Organic Light Emitting Display
  • the refresh rate is the number of times the screen is refreshed per second. Different display devices have different refresh rate requirements. For large displays such as 50-inch displays, higher refresh rates are required to meet better visual needs.
  • the refresh rate is related to the structure of the drive circuit on the array substrate, that is, the drive mode.
  • the driving circuit of the existing array substrate includes:
  • a plurality of pixel thin film transistors TFT distributed in a matrix a plurality of gate scan lines (G1, G2, G3, G4, G5 Gm) respectively connected to the respective pixels and a plurality of data lines (D1, D2, D3, D4D ( N-3), D(n-2), D(n-1), D(n)), the gate scan lines and the data lines are arranged in a matrix.
  • the driving circuit of the existing array substrate further includes a gate driving circuit 10 and a source driving circuit 20, the gate driving circuit 10 includes a shift register, and the shift register includes m and the plurality of Gate scan line - corresponding to the connected shift register unit, namely: a first shift register unit, a second shift register unit mth shift register unit, the source drive circuit 20 and all data The signal lines are connected.
  • the driving method of the existing driving circuit is: the timing controller controls the shift register to scan the gate scan line progressively; when a gate scan line is turned on, the timing controller controls the source driving circuit to input the data corresponding to the current gate scan line. signal.
  • the timing controller controls the shift register to scan the gate scan line progressively; when a gate scan line is turned on, the timing controller controls the source driving circuit to input the data corresponding to the current gate scan line. signal.
  • m scan lines and n data lines For a large-sized display device, it takes a long time to scan one frame of image (corresponding to m rows and n columns of pixels), and accordingly, the refresh rate of the display device is higher.
  • Embodiments of the present invention provide a driving circuit, a driving method, and a display device for improving a refresh rate of a display device.
  • the embodiment of the present invention provides a driving circuit for driving pixels on an array substrate to realize image display, the array substrate includes a first display area and a second display area, and the driving circuit includes:
  • a gate driving circuit connected to the first m gate scan lines and the second m gate scan lines;
  • a first source driving circuit connected to the first n data signal lines of the first display area and a second source driving circuit connected to the second n data signal lines of the second display area;
  • the gate driving circuit simultaneously scans the first m gate scan lines of the first display region and the second m gate scan lines of the second display region, so that the first m gates are simultaneously One of the gate scan lines and one of the second m gate scan lines output a scan signal, and the first source drive circuit and the second source drive circuit
  • the respective data signals are respectively output to the respective connected data signal lines, wherein the m and n are positive integers.
  • the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein
  • the first m shift register units connected to the first m gate scan lines of the first display area constitute a first shift register, respectively connected to the second m gate scan lines of the second display area
  • the second m shift register unit constitutes a second shift register
  • a first shift register unit of the first shift register is coupled to a first or mth shift register unit of the second shift register;
  • the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein a first m shifts of the first m gate scan lines of the first display area
  • the memory unit constitutes a first shift register
  • the second m shift register units respectively connected to the second m gate scan lines of the second display area constitute a second shift register;
  • the mth shift register unit in the first shift register is connected to the first or mth shift register unit in the second shift register;
  • the gate driving circuit is composed of m shift register units respectively connected to the first m gate scan lines of the first display area, and the The m shift register units are also respectively connected to the second m gate scan lines of the second display area, wherein the m shift register units are cascaded.
  • the gate driving circuit is a gate driving chip, and the gate driving chip is connected to the first m gate scanning lines of the first display region;
  • first m gate scan lines of the first display area and the second m gate scan lines of the second display area are correspondingly connected.
  • the control gate driving circuit simultaneously scans the first m gate scan lines of the first display area and the second m gate scan lines of the second display area line by line, so that Each time the scan signal is output, a scan signal is simultaneously outputted to one of the first m gate scan lines and one of the second m gate scan lines.
  • the first source driving circuit connected to the data signal line of the first display area and the second source driving circuit connected to the data signal line of the second display area are output to the data signal lines connected thereto. The respective data signals.
  • the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein
  • the first m shift register units connected to the first m gate scan lines of the first display area constitute a first shift register, respectively connected to the second m gate scan lines of the second display area
  • the second m shift register unit constitutes a second shift register; the first shift register unit in the first shift register and the first or mth shift register in the second shift register
  • the unit is connected; wherein, the m shift register units in each shift register are cascaded, and in the process of displaying one frame of image, the driving method is specifically:
  • the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein
  • the first m shift register units connected to the first m gate scan lines of the first display area constitute a first shift register, respectively connected to the second m gate scan lines of the second display area
  • the second m shift register unit constitutes a second shift register; the first shift register unit in the first shift register and the first or mth shift register in the second shift register
  • the unit is connected; wherein, the m shift register units in each shift register are cascaded, and in the process of displaying one frame of image, the driving method is specifically:
  • the pole drive circuit outputs respective data signals
  • the pole drive circuit outputs respective data signals
  • the gate driving circuit is composed of m shift register units, the m shifts
  • the register units are respectively connected to the first m gate scan lines of the first display area, and the m shift register units are respectively corresponding to the second m gate scan lines of the second display area.
  • the driving method is specifically:
  • the first source drive circuit and the second source drive circuit are controlled to output respective data signals.
  • the gate driving circuit is a gate driving chip, and the gate driving chip is connected to the first m gate scanning lines of the first display area; and, the first display area is One m gate scan lines and the second m gate scan lines of the second display area are correspondingly connected; in the process of displaying one frame image, the driving method is specifically:
  • Embodiments of the present invention provide a display device including the above driving circuit.
  • the driving circuit simultaneously drives one row of pixels of the first display area on the array substrate and one row of pixels of the second display area, thereby forming the existing array shown in FIG.
  • the refresh rate of the display device can be doubled under the condition that the refresh frequency of the scanning signal is constant.
  • the control gate driving circuit simultaneously drives the m gate scan lines of the first display area and the m gate scan lines of the second display area row by row, so that each Outputting a scan signal to the gate scan line of one of the first m gate scan lines and one of the second m gate scan lines to output a scan signal line by line at a time.
  • the first source driving circuit controlling the first display area and the second source driving circuit of the second display area output respective data signals to the data signal lines connected thereto, thereby realizing a high refresh rate.
  • FIG. 1 is a schematic structural view of a driving circuit of a prior art driving array substrate
  • FIG. 2 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention.
  • FIG. 4 is a second schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of a driving circuit according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic structural diagram of a driving circuit according to Embodiment 3 of the present invention.
  • FIG. 7 is a timing chart corresponding to the driving circuit shown in FIG. 3;
  • Fig. 8 is a timing chart corresponding to the drive circuit shown in Fig. 4. detailed description
  • Embodiments of the present invention provide a driving circuit, a driving method, and a display device for improving a refresh rate of a display device.
  • the array substrate provided by the present invention includes a pixel of the first display area and a pixel of the second display area.
  • the driving circuit provided by the embodiment of the present invention simultaneously drives a row of pixels of the first display area and a row of pixels of the second display area, thereby Compared with the driving circuit of the conventional array substrate shown in FIG. 1, the refresh rate of the display device can be doubled under the condition that the refresh frequency of the scanning signal is constant, or the refresh rate of the display device is inconvenient.
  • the charging time of one row of pixels connected to each gate scan line can be extended to two times.
  • the gate scan lines of the first display area are scanned line by line while the gate scan lines of the second display area are scanned line by line, and one gate in the first display area is simultaneously turned on in each scan pulse period.
  • the scan line and one gate scan line of the second display area improve the refresh rate of the display image displayed by the display device. Illuminated display field, etc.
  • the driving circuit on the array substrate mainly includes a timing control circuit, a gate driving circuit (ie, a scanning driving circuit), and a source driving circuit (ie, a data driving circuit), and each of the gate scanning lines and the data signals. line.
  • an array substrate includes: a substrate 1; and a pixel array formed by a plurality of pixels 2 on the substrate 1 (a pixel array formed by 2 m rows and n columns of pixels, wherein the m and n are positive Integer).
  • the first m rows and n columns of pixels form the first display area 3 (as in the dotted line frame circuit), and the rear m rows and n columns of pixels form the second display area 4 (as shown in the dotted line frame circuit);
  • the driving circuit for driving the array substrate to realize image display according to the embodiment of the present invention differs depending on the gate driving circuit, and is described below for different gate driving circuits.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the driving circuit provided in the first embodiment includes:
  • m gate scan lines such as G1U, G2U, G3U G(ml) U, GmU in FIG. 3 located in the first display area 3 and respectively connected to the pixels of the first m rows, and the first n data signal lines ( Figure 3, D1U, D2U, D3U, D4U D(n-3)U, D(n-2)U, D(nl)U,
  • m gate scan lines such as G1D, G2D, G3D G(m-1)D, GmD in FIG. 3 located in the second display area 4 and respectively connected to the rear m rows of pixels, and the second n pieces of data Signal line (such as DID, D2D, D3D, D4D D(n-3)D, D(n-2)D, D(n-1)D,
  • the gate driving circuit provided in the first embodiment is composed of 2m shift register units (Shift Register), wherein the m shift register units corresponding to the first display area 3 constitute the first shift register 31; and the second display The m shift register units corresponding to the area 4 constitute the second shift register 41.
  • the first shift register unit in the first shift register 31 is coupled to the first shift register unit in the second shift register 41.
  • m shift register units are cascaded; that is, the first shift register unit in the first shift register 31 is cascaded to the mth shift register unit ( That is, the first shift register unit in the second shift register 41 is cascaded to the mth shift register unit.
  • the first shift register unit in the first shift register 31 is connected to the mth shift register unit in the second shift register 41.
  • m shift register units are also cascaded; that is, the first shift register unit in the first shift register 31 to the mth shift register
  • the cells are cascaded (ie, connected end to end in sequence); the mth shift register unit in the second shift register 41 is cascaded to the first shift register unit.
  • the mth shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41.
  • the m shift register units are also cascaded; that is, the mth shift register unit in the first shift register 31 is cascaded to the first shift register unit. (ie, connected end to end in sequence); the first shift register unit in the second shift register 41 is cascaded to the mth shift register unit.
  • the 2m shift register units are respectively connected to the 2m gate scan lines--that is, the m shift register units in the first shift register 31 are respectively connected to the first m-row pixels.
  • the m gate scan lines are connected, and the m shift register units in the second shift register 41 are respectively connected to m gate scan lines connected to the rear m rows of pixels.
  • the gate driving circuit Under the control of the timing controller (illustrated by STV in FIG. 3), the gate driving circuit simultaneously drives the first m rows of pixels and the last m rows of pixels in the first display region 3 and the second display region 4 row by row in order to realize Image display.
  • 3 is a driving circuit in which the first shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41.
  • 4 is a drive circuit in which the mth shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41.
  • the driving method of the driving circuit shown in the first embodiment includes: controlling the first shift register unit in the first shift register and displaying the image of each frame.
  • the first shift register unit in the second shift register simultaneously outputs the scan signal, and controls the first source driving circuit and the second source driving circuit to output respective data signals;
  • the timing controller only needs to simultaneously input the first shift register unit in the first shift register and the first shift register unit in the second shift register.
  • the output of the first shift register unit in each shift register is the input of the second shift register unit;
  • the output of the two shift register units is the input of the third shift register unit; and so on, the output of the m-1th shift register unit is the input of the mth shift register unit.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the gate driving circuit is composed of a shift register composed of m cascaded shift register units, and the m shift register units and the first display area, respectively.
  • the m gate scan lines of 3 are correspondingly connected, and are respectively connected to the m gate scan lines in the second display area 4, respectively.
  • the first gate scan line of the first display area is connected to the first gate scan line of the second display area, and the second gate scan line of the first display area is second.
  • a second gate scan line of the display area is connected until the mth gate scan line of the first display area is connected to the mth gate scan line of the second display area, and the timing controller is to the first shift register
  • the unit inputs the scan signal.
  • the driving method of the driving circuit shown in FIG. 5 includes:
  • the first shift register unit is controlled to output a scan signal to the two gate scan lines connected thereto, and the first source drive circuit and the second source drive circuit are controlled to output respective ones.
  • the first source drive circuit and the second source drive circuit are controlled to output respective data signals.
  • the timing controller only needs to input the scan signal to the first shift register unit. Since the shift register unit is cascaded, the shift register unit of the previous stage is used. The output is the input to the next shift register unit.
  • the driving circuit shown in FIG. 5 may be modified such that the first gate scan line of the first display area is connected to the mth gate scan line of the second display area, and the second line of the first display area
  • the gate scan line is connected to the (m-1)th gate scan line of the second display area until the mth gate scan line of the first display area is connected to the first gate scan line of the second display area
  • the timing controller inputs a scan signal to the first shift register unit.
  • the scanning mode shown in FIG. 5 is a progressive scanning from top to bottom, but the scanning method may also be a progressive scanning from bottom to top.
  • the timing controller When the scan mode is a page-by-row scan from bottom to top, the timing controller inputs a scan signal to the mth shift register unit.
  • the mth shift register unit is cascaded to the first shift register unit.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the gate driving circuit is a gate driving chip 6, and the gate driving chip 6 is respectively connected to 2m gate scanning lines;
  • the m gate scan lines in the first display area 3 and the m gate scan lines in the second display area 4 are correspondingly connected.
  • the first gate scan line in the first display area 3 is connected to the first gate scan line of the second display area, and the second gate scan line of the first display area and the second display area are The two gate scan lines are connected, and so on, until the mth gate scan line of the first display area is connected to the mth gate scan line of the second display area.
  • the first gate scan line of the first display area is connected to the mth gate scan line of the second display area
  • the second gate scan line of the first display area and the second display area are (m-1) gate scan lines are connected, and so on, until the mth gate scan line of the first display area is connected to the first gate scan line of the second display area.
  • the driving method of the driving circuit shown in FIG. 6 includes:
  • the gate scanning lines in the first display area 3 and the second display area 4 are arranged in a plurality of rows, and the data signal lines in the first display area 3 and the second display area 4 are large. Column arrangement. Specifically, all the gate scan lines in the first display area 3 are sequentially adjacent, and all the gate scan lines in the second display area 4 are sequentially adjacent.
  • the n data signal lines in the first display area 3 are arranged to cross the m gate scanning lines in the first display area.
  • the n data signal lines in the second display area 3 are arranged to intersect with the m gate scanning lines in the second display area.
  • the first source driving circuit and the second source driving circuit are located in the peripheral region of the entire array substrate, and do not affect the aperture ratio of the display device.
  • Such a setting method facilitates the wiring of the circuit structure and improves the display quality of the image of the display device.
  • the gate driving circuit can be implemented by a shift register formed on the array substrate, or can be realized by an integrated circuit card (IC).
  • IC integrated circuit card
  • the driving circuit provided in Embodiments 1 to 3 of the present invention is not limited to the structure shown in FIG. 3 to FIG. 6, and may further include modules such as a reference voltage source and a voltage source conversion circuit.
  • the gate driving circuit of the present invention is for sequentially outputting an appropriate gate voltage to a specific gate scan line to drive a pixel connected to the gate scan line; the source driving circuit will connect each of the gate scan lines The pixel voltage corresponding to the pixel is input to each pixel connected to the gate scan line.
  • the present invention simultaneously turns on two gate scan lines in one pulse period and simultaneously inputs data signals to the data signal lines corresponding to the two gate scan lines.
  • the refresh rate of the display image of the display device is constant
  • the number of times of opening each of the gate scanning lines on the array substrate is halved.
  • the charging time of each row of pixels is increased; on the other hand, in the case where the number of times of opening of each gate scanning line on the array substrate is constant, the refresh rate of the image displayed by the display device can be doubled.
  • the embodiment of the invention provides a driving method for driving the array substrate to realize image display, which includes:
  • the control gate driving circuit In the process of displaying one frame of image, the control gate driving circuit simultaneously scans the m gate scan lines of the first display area and the m gate scan lines of the second display area line by line, so that each output scan is performed. And outputting a scan signal to one of the m gate scan lines of the first display area and one of the m gate scan lines of the second display area. Controlling the first source driving circuit of the first display area every time the scanning signal is output The second source driving circuit and the second display region output respective data signals to the respective data signal lines connected thereto.
  • Fig. 7 is a timing chart showing the timing controller corresponding to the drive circuit shown in Fig. 3. Controlling the first gate scan line G1U in the first display region and the first gate scan line G1D in the second display region at a first scan pulse period of the display time of one frame of image On, the remaining gate scan lines are off at a low level;
  • the third scan pulse period controls that the third gate scan line G3U in the first display area and the third gate scan line G3D in the second display area are turned on at a high level, and the remaining gate scan lines are low. Closed
  • the m-1th scan pulse period controlling the m-1th gate scan line G(ml)U in the first display area and the second gate scan line G in the second display area (m-1) D high level is turned on, and the remaining gate scan lines are turned off at low level;
  • the mth scan pulse period controlling the mth gate scan line GmU in the first display area and the mth gate scan line GmD in the second display area to be turned on at a high level, and the remaining gate scan lines are low. Flat closed.
  • the gate scan lines in the first display area and the second display area are scanned within the display time of one frame of image.
  • Fig. 8 is a timing chart showing the timing controller corresponding to the drive circuit shown in Fig. 4. Controlling the mth gate scan line GmU in the first display area and the first gate scan line G1D in the second display area to be high during the first scan pulse period during the display time of one frame of image Level (corresponding to the high level on state in Figure 8), the remaining gate scan lines are low;
  • G(m-l)U and the second gate scan line G2D in the second display area are at a high level, and the remaining gate scan lines are at a low level;
  • a third scan pulse period controlling the m-2th gate scan line G(m-2)U in the first display area and the third gate scan line G3D in the second display area to be at a high level , the remaining gate scan lines are low;
  • the m-1th scan pulse period controlling the second grid in the first display area
  • the pole scan line G2U and the m-1th gate scan line G(m-1)D in the second display region are at a high level, and the remaining gate scan lines are at a low level;
  • the gate scan lines in the first display area and the second display area are scanned within the display time of one frame of image.
  • the refresh rate of the image is doubled.
  • the charging time of the pixel is doubled.
  • the array substrate and the driving method provided by the embodiments of the present invention are preferably applied to an array substrate with higher integration, for example, low temperature poly-silicon (LTPS).
  • LTPS low temperature poly-silicon
  • the embodiment of the present invention further provides a display device, which includes the driving circuit provided by the embodiment of the present invention, and the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, an organic electroluminescence display OLED panel, an OLED display, A display device such as an OLED television or an electronic paper.
  • the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, an organic electroluminescence display OLED panel, an OLED display, A display device such as an OLED television or an electronic paper.
  • the embodiment of the invention improves the refresh rate of the image display of the array substrate by setting two display regions (the first display region and the second display region) to simultaneously drive the pixel array on the array substrate.
  • the first group of gate scan lines of the first display area in the circuit are turned on line by line
  • the second group of gate scan lines of the second display area in the circuit are turned on line by line
  • the first display area is turned on in the first display area.
  • one of the first group of gate scan lines scans the line
  • one of the second group of gate scan lines in the second display area is simultaneously turned on, that is, simultaneously at the same time
  • Two different gate scan lines on the array substrate are turned on, and the two gate scan lines are respectively connected to two different source driving circuits.
  • the two source driving circuits are respectively input.
  • the data signals corresponding to the respective data signal lines realize image display.
  • the refresh rate of the image displayed on the array substrate is at least twice as large as the pulse width of the conventional scanning signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A drive circuit, a drive method and a display device for increasing the refresh frequency of a scanning signal of the drive circuit. The drive circuit is used for driving a pixel on an array substrate for realizing image display. The array substrate comprises a first display area (3) and a second display area (4). The drive circuit comprises first m gate electrode scanning lines (G1U-GmU) and first n data signal lines (D1U-DnU) which are connected to a pixel in the first display area (3), second m gate electrode scanning lines (G1D-GmD) and second n data signal lines (D1D-DnD) which are connected to a pixel in the second display area (4), gate drive circuit (31, 41) which is connected to the first m gate electrode scanning lines (G1U-GmU) and the second m gate electrode scanning lines (G1D-GmD), and a first source electrode drive circuit (32) and a second source electrode drive circuit (42) which are used for driving the pixel on the array substrate. The gate drive circuit (31, 41) outputs a scanning signal simultaneously to one gate electrode scanning line in the first m gate electrode scanning lines (G1U-GmU) and one gate electrode scanning line in the second m gate electrode scanning lines (G1D-GmD), and meanwhile, the first source electrode drive circuit (32) and the second source electrode drive circuit (42) output respective data signals respectively to the respectively connected data signal lines, wherein m and n are positive integers.

Description

驱动电路、 驱动方法及显示装置 技术领域  Driving circuit, driving method and display device
本发明涉及显示技术领域， 尤其涉及一种驱动电路、 驱动方法及显示装 置。 背景技术  The present invention relates to the field of display technologies, and in particular, to a driving circuit, a driving method, and a display device. Background technique
在显示技术领域， 薄膜晶体管液晶显示器 （Thin Film Transistor-Liquid Crystal Display, TFT-LCD )和有机发光显示器（ Organic Light Emitting Display, OLED )是两种主要的平板显示装置。  In the field of display technology, Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Organic Light Emitting Display (OLED) are two main flat panel display devices.
随着人们对大尺寸、 高分辨率的显示装置的需求不断增加， 大尺寸的显 示装置也得到较快的发展。 目前制约高性能、 高分辨率的大尺寸显示装置的 因素之一为刷新率。 刷新率为屏幕每秒画面被刷新的次数， 不同尺寸的显示 装置刷新率要求不同， 针对大尺寸例如 50英寸以上的显示屏， 要求更高的刷 新率以满足较佳的视觉需求。  As the demand for large-sized, high-resolution display devices continues to increase, large-sized display devices have also been rapidly developed. One of the factors that currently restrict high-performance, high-resolution large-size display devices is the refresh rate. The refresh rate is the number of times the screen is refreshed per second. Different display devices have different refresh rate requirements. For large displays such as 50-inch displays, higher refresh rates are required to meet better visual needs.
刷新率与阵列基板上驱动电路的结构有关， 即与驱动方式有关。  The refresh rate is related to the structure of the drive circuit on the array substrate, that is, the drive mode.
如图 1所示， 为现有阵列基板的驱动电路， 包括：  As shown in FIG. 1 , the driving circuit of the existing array substrate includes:
呈矩阵分布的多个像素薄膜晶体管 TFT、 分别与各像素相连的多条栅极 扫描线（Gl、 G2、 G3、 G4、 G5 Gm )和多条数据线（Dl、 D2、 D3、 D4 D ( n-3 )、 D(n-2)、 D(n-1)、 D(n) ), 栅极扫描线和数据线呈行列交 叉分布。  a plurality of pixel thin film transistors TFT distributed in a matrix, a plurality of gate scan lines (G1, G2, G3, G4, G5 Gm) respectively connected to the respective pixels and a plurality of data lines (D1, D2, D3, D4D ( N-3), D(n-2), D(n-1), D(n)), the gate scan lines and the data lines are arranged in a matrix.
此夕卜，现有阵列基板的驱动电路还包括栅极驱动电路 10和源极驱动电路 20, 所述栅极驱动电路 10包括移位寄存器， 所述移位寄存器由 m个与所述 多条栅极扫描线——对应相连的移位寄存器单元组成， 即： 第一个移位寄存 器单元、 第二个移位寄存器单元 第 m个移位寄存器单元， 所述源极 驱动电路 20与所有数据信号线相连。  Further, the driving circuit of the existing array substrate further includes a gate driving circuit 10 and a source driving circuit 20, the gate driving circuit 10 includes a shift register, and the shift register includes m and the plurality of Gate scan line - corresponding to the connected shift register unit, namely: a first shift register unit, a second shift register unit mth shift register unit, the source drive circuit 20 and all data The signal lines are connected.
现有驱动电路的驱动方法为： 时序控制器控制移位寄存器逐行扫描栅极 扫描线； 在一条栅极扫描线开启时， 时序控制器控制源极驱动电路输入当前 栅极扫描线对应的数据信号。 假设有 m条扫描线， n条数据线， 对于大尺寸 的显示装置， 扫描完一帧图像（对应 m行 n列像素）需要较长的时间， 相应 地， 该显示装置的刷新率就较^^ 发明内容 The driving method of the existing driving circuit is: the timing controller controls the shift register to scan the gate scan line progressively; when a gate scan line is turned on, the timing controller controls the source driving circuit to input the data corresponding to the current gate scan line. signal. Suppose there are m scan lines and n data lines. For a large-sized display device, it takes a long time to scan one frame of image (corresponding to m rows and n columns of pixels), and accordingly, the refresh rate of the display device is higher. ^ Summary of the invention
本发明实施例提供了一种驱动电路、 驱动方法及显示装置， 用以提高显 示装置的刷新率。  Embodiments of the present invention provide a driving circuit, a driving method, and a display device for improving a refresh rate of a display device.
本发明实施例提供了一种用于驱动阵列基板上的像素以实现图像显示的 驱动电路， 所述阵列基板包括第一显示区域和第二显示区域， 所述驱动电路 包括：  The embodiment of the present invention provides a driving circuit for driving pixels on an array substrate to realize image display, the array substrate includes a first display area and a second display area, and the driving circuit includes:
与所述第一显示区域中的像素相连的第一 m条栅极扫描线和第一 n条数 据信号线；  a first m gate scan lines and first n data signal lines connected to pixels in the first display area;
与所述第二显示区域中的像素相连的第二 m条栅极扫描线和第二 n条数 据信号线；  a second m gate scan line and a second n data signal line connected to the pixels in the second display area;
与所述第一 m条栅极扫描线和所述第二 m条栅极扫描线相连的栅极驱动 电路；  a gate driving circuit connected to the first m gate scan lines and the second m gate scan lines;
与第一显示区域的第一 n条数据信号线相连的第一源极驱动电路和与第 二显示区域的第二 n条数据信号线相连的第二源极驱动电路；  a first source driving circuit connected to the first n data signal lines of the first display area and a second source driving circuit connected to the second n data signal lines of the second display area;
所述栅极驱动电路同时对第一显示区域的第一 m条栅极扫描线和第二显 示区域的第二 m条栅极扫描线进行逐行扫描，使得同时向所述第一 m条栅极 扫描线中的一条栅极扫描线和所述第二 m条栅极扫描线中的一条栅极扫描线 输出扫描信号， 同时所述第一源极驱动电路和所述第二源极驱动电路分别向 各自所连接的数据信号线输出各自的数据信号，其中，所述 m和 n为正整数。  The gate driving circuit simultaneously scans the first m gate scan lines of the first display region and the second m gate scan lines of the second display region, so that the first m gates are simultaneously One of the gate scan lines and one of the second m gate scan lines output a scan signal, and the first source drive circuit and the second source drive circuit The respective data signals are respectively output to the respective connected data signal lines, wherein the m and n are positive integers.
较佳地，所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移 位寄存器单元包括第一 m个移位寄存器单元和第二 m个移位寄存器单元，其 中 ,分别与所述第一显示区域的第一 m条栅极扫描线相连的第一 m个移位寄 存器单元构成第一移位寄存器， 分别与所述第二显示区域的第二 m条栅极扫 描线相连的第二 m个移位寄存器单元构成第二移位寄存器；  Preferably, the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein The first m shift register units connected to the first m gate scan lines of the first display area constitute a first shift register, respectively connected to the second m gate scan lines of the second display area The second m shift register unit constitutes a second shift register;
所述第一移位寄存器中的第一个移位寄存器单元与第二移位寄存器中的 第一个或第 m个移位寄存器单元相连；  a first shift register unit of the first shift register is coupled to a first or mth shift register unit of the second shift register;
其中， 每个移位寄存器单元中的 m个移位寄存器单元级联。  Wherein, m shift register units in each shift register unit are cascaded.
较佳地，所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移 位寄存器单元包括第一 m个移位寄存器单元和第二 m个移位寄存器单元，其 中，分别与所述第一显示区域的第一 m条栅极扫描线相连的第一 m个移位寄 存器单元构成第一移位寄存器， 分别与所述第二显示区域的第二 m条栅极扫 描线相连的第二 m个移位寄存器单元构成第二移位寄存器； Preferably, the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein a first m shifts of the first m gate scan lines of the first display area The memory unit constitutes a first shift register, and the second m shift register units respectively connected to the second m gate scan lines of the second display area constitute a second shift register;
所述第一移位寄存器中的第 m个移位寄存器单元与第二移位寄存器中的 第一个或第 m个移位寄存器单元相连；  The mth shift register unit in the first shift register is connected to the first or mth shift register unit in the second shift register;
其中， 每个移位寄存器单元中的 m个移位寄存器单元级联。  Wherein, m shift register units in each shift register unit are cascaded.
较佳地，所述栅极驱动电路由 m个移位寄存器单元组成，所述 m个移位 寄存器单元分别与第一显示区域的第一 m条栅极扫描线——对应相连， 并且 所述 m个移位寄存器单元还分别与第二显示区域的第二 m条栅极扫描线—— 对应相连， 其中， 所述 m个移位寄存器单元级联。  Preferably, the gate driving circuit is composed of m shift register units respectively connected to the first m gate scan lines of the first display area, and the The m shift register units are also respectively connected to the second m gate scan lines of the second display area, wherein the m shift register units are cascaded.
较佳地， 所述栅极驱动电路为栅极驱动芯片， 所述栅极驱动芯片与所述 第一显示区域的第一 m条栅极扫描线相连；  Preferably, the gate driving circuit is a gate driving chip, and the gate driving chip is connected to the first m gate scanning lines of the first display region;
并且，所述第一显示区域的第一 m条栅极扫描线和第二显示区域的第二 m条栅极扫描线——对应相连。  Moreover, the first m gate scan lines of the first display area and the second m gate scan lines of the second display area are correspondingly connected.
本发明实施例提供的一种上述驱动电路的驱动方法， 包括：  A driving method for the above driving circuit provided by an embodiment of the present invention includes:
在显示一帧图像的过程中， 控制栅极驱动电路同时对第一显示区域的第 一 m条栅极扫描线和第二显示区域的第二 m条栅极扫描线进行逐行扫描，使 得在每一次输出扫描信号时都同时向所述第一 m条栅极扫描线中的一条栅极 扫描线和所述第二 m条栅极扫描线中的一条栅极扫描线输出扫描信号， 在每 一次输出扫描信号时， 控制与第一显示区域的数据信号线相连的第一源极驱 动电路和第二显示区域的数据信号线相连的第二源极驱动电路向与各自相连 的数据信号线输出各自的数据信号。  In the process of displaying one frame of image, the control gate driving circuit simultaneously scans the first m gate scan lines of the first display area and the second m gate scan lines of the second display area line by line, so that Each time the scan signal is output, a scan signal is simultaneously outputted to one of the first m gate scan lines and one of the second m gate scan lines. When the scan signal is outputted once, the first source driving circuit connected to the data signal line of the first display area and the second source driving circuit connected to the data signal line of the second display area are output to the data signal lines connected thereto. The respective data signals.
较佳地，所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移 位寄存器单元包括第一 m个移位寄存器单元和第二 m个移位寄存器单元，其 中 ,分别与所述第一显示区域的第一 m条栅极扫描线相连的第一 m个移位寄 存器单元构成第一移位寄存器， 分别与所述第二显示区域的第二 m条栅极扫 描线相连的第二 m个移位寄存器单元构成第二移位寄存器； 所述第一移位寄 存器中的第一个移位寄存器单元与第二移位寄存器中的第一个或第 m个移位 寄存器单元相连； 其中， 每个移位寄存器中的 m个移位寄存器单元级联， 在 显示一帧图像的过程中， 所述驱动方法具体为：  Preferably, the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein The first m shift register units connected to the first m gate scan lines of the first display area constitute a first shift register, respectively connected to the second m gate scan lines of the second display area The second m shift register unit constitutes a second shift register; the first shift register unit in the first shift register and the first or mth shift register in the second shift register The unit is connected; wherein, the m shift register units in each shift register are cascaded, and in the process of displaying one frame of image, the driving method is specifically:
控制第一移位寄存器中的第一个移位寄存器单元和第二移位寄存器中的 第一个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号； Controlling a first shift register unit in the first shift register and a first shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the first The two source driving circuits output respective data signals;
控制第一移位寄存器中的第二个移位寄存器单元和第二移位寄存器中的 第二个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号；  Controlling a second shift register unit in the first shift register and a second shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the second source driving The circuit outputs respective data signals;
控制第一移位寄存器中的第三个移位寄存器单元和第二移位寄存器中的 第三个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号；  Controlling a third shift register unit in the first shift register and a third shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the second source driving The circuit outputs respective data signals;
以此类推， 直到控制第一移位寄存器中的第 m个移位寄存器单元和第二 移位寄存器中的第 m个移位寄存器单元同时输出所述扫描信号， 控制第一源 极驱动电路和第二源极驱动电路输出各自的数据信号。  And so on, until the mth shift register unit in the first shift register and the mth shift register unit in the second shift register simultaneously output the scan signal, controlling the first source driving circuit and The second source driving circuit outputs respective data signals.
较佳地，所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移 位寄存器单元包括第一 m个移位寄存器单元和第二 m个移位寄存器单元，其 中 ,分别与所述第一显示区域的第一 m条栅极扫描线相连的第一 m个移位寄 存器单元构成第一移位寄存器， 分别与所述第二显示区域的第二 m条栅极扫 描线相连的第二 m个移位寄存器单元构成第二移位寄存器； 所述第一移位寄 存器中的第一个移位寄存器单元与第二移位寄存器中的第一个或第 m个移位 寄存器单元相连； 其中， 每个移位寄存器中的 m个移位寄存器单元级联， 在 显示一帧图像的过程中， 所述驱动方法具体为：  Preferably, the gate driving circuit is composed of 2m shift register units, and the 2m shift register unit includes a first m shift register unit and a second m shift register unit, wherein The first m shift register units connected to the first m gate scan lines of the first display area constitute a first shift register, respectively connected to the second m gate scan lines of the second display area The second m shift register unit constitutes a second shift register; the first shift register unit in the first shift register and the first or mth shift register in the second shift register The unit is connected; wherein, the m shift register units in each shift register are cascaded, and in the process of displaying one frame of image, the driving method is specifically:
控制第一移位寄存器中的第一个移位寄存器单元和第二移位寄存器中的 第 m个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号；  Controlling a first shift register unit in the first shift register and an mth shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the second source driving The circuit outputs respective data signals;
控制第一移位寄存器中的第二个移位寄存器单元和第二移位寄存器中的 第 m-1个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和 第二源极驱动电路输出各自的数据信号；  Controlling a second shift register unit in the first shift register and an m-1th shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the second source The pole drive circuit outputs respective data signals;
控制第一移位寄存器中的第三个移位寄存器单元和第二移位寄存器中的 第 m-2个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和 第二源极驱动电路输出各自的数据信号；  Controlling a third shift register unit in the first shift register and an m-2th shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the second source The pole drive circuit outputs respective data signals;
以此类推，直到控制第一移位寄存器中的第 m个移位寄存器单元和第二 移位寄存器中的第一个移位寄存器单元同时输出所述扫描信号， 控制第一源 极驱动电路和第二源极驱动电路输出各自的数据信号。  And so on, until the mth shift register unit in the first shift register and the first shift register unit in the second shift register are simultaneously outputting the scan signal, controlling the first source driving circuit and The second source driving circuit outputs respective data signals.
较佳地，所述栅极驱动电路由 m个移位寄存器单元组成，所述 m个移位 寄存器单元分别与第一显示区域的第一 m条栅极扫描线——对应相连， 并且 所述 m个移位寄存器单元还分别与第二显示区域的第二 m条栅极扫描线—— 对应相连， 其中， 所述 m个移位寄存器单元级联； 在显示一帧图像的过程中， 所述驱动方法具体为： Preferably, the gate driving circuit is composed of m shift register units, the m shifts The register units are respectively connected to the first m gate scan lines of the first display area, and the m shift register units are respectively corresponding to the second m gate scan lines of the second display area. Connected, wherein the m shift register units are cascaded; in the process of displaying an image of one frame, the driving method is specifically:
控制第一个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号；  Controlling the first shift register unit to output a scan signal to the two gate scan lines connected thereto, and controlling the first source drive circuit and the second source drive circuit to output respective data signals;
控制第二个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号；  Controlling the second shift register unit to output a scan signal to the two gate scan lines connected thereto, and controlling the first source drive circuit and the second source drive circuit to output respective data signals;
控制第三个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号；  Controlling the third shift register unit to output a scan signal to the two gate scan lines connected thereto, and controlling the first source drive circuit and the second source drive circuit to output respective data signals;
以此类推， 直到控制第 m个移位寄存器单元向与之相连的两条栅极扫描 线输出扫描信号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数 据信号。  By analogy, until the mth shift register unit is controlled to output a scan signal to the two gate scan lines connected thereto, the first source drive circuit and the second source drive circuit are controlled to output respective data signals.
较佳地， 所述栅极驱动电路为栅极驱动芯片， 所述栅极驱动芯片与所述 第一显示区域的第一 m条栅极扫描线相连； 并且， 所述第一显示区域的第一 m条栅极扫描线和第二显示区域的第二 m条栅极扫描线——对应相连； 在显 示一帧图像的过程中， 所述驱动方法具体为：  Preferably, the gate driving circuit is a gate driving chip, and the gate driving chip is connected to the first m gate scanning lines of the first display area; and, the first display area is One m gate scan lines and the second m gate scan lines of the second display area are correspondingly connected; in the process of displaying one frame image, the driving method is specifically:
控制所述栅极驱动芯片逐行向第一显示区域的栅极扫描线和第二显示区 域的栅极扫描线输出扫描信号， 同时控制第一源极驱动电路和第二源极驱动 电路输出各自的数据信号。  Controlling the gate driving chip to output a scan signal to the gate scan line of the first display area and the gate scan line of the second display area row by row, and simultaneously controlling the output of the first source driving circuit and the second source driving circuit Data signal.
本发明实施例提供一种显示装置， 包括上述驱动电路。  Embodiments of the present invention provide a display device including the above driving circuit.
本发明实施例通过在阵列基板上设置两个显示区域， 驱动电路同时驱动 阵列基板上的第一显示区域的一行像素和第二显示区域的一行像素， 从而与 图 1 中所示的现有阵列基板的驱动电路相比， 在扫描信号的刷新频率不变的 情况下可以将显示装置的刷新率提高至两倍。 具体地， 在显示一帧图像的过 程中， 控制栅极驱动电路同时对第一显示区域的 m条栅极扫描线和第二显示 区域的 m条栅极扫描线进行逐行驱动， 使得在每一次输出扫描信号时都同时 向所述第一 m条栅极扫描线中的一条栅极扫描线和所述第二 m条栅极扫描线 中的一条栅极扫描线逐行输出扫描信号， 在每一次输出扫描信号时， 控制第 一显示区域的第一源极驱动电路和第二显示区域的第二源极驱动电路向与各 自相连的数据信号线输出各自的数据信号， 实现高刷新率的图像显示。 附图说明 In the embodiment of the present invention, by providing two display areas on the array substrate, the driving circuit simultaneously drives one row of pixels of the first display area on the array substrate and one row of pixels of the second display area, thereby forming the existing array shown in FIG. Compared with the driving circuit of the substrate, the refresh rate of the display device can be doubled under the condition that the refresh frequency of the scanning signal is constant. Specifically, in the process of displaying one frame of image, the control gate driving circuit simultaneously drives the m gate scan lines of the first display area and the m gate scan lines of the second display area row by row, so that each Outputting a scan signal to the gate scan line of one of the first m gate scan lines and one of the second m gate scan lines to output a scan signal line by line at a time. Each time the scan signal is output, the first source driving circuit controlling the first display area and the second source driving circuit of the second display area output respective data signals to the data signal lines connected thereto, thereby realizing a high refresh rate. Image display. DRAWINGS
图 1为现有技术驱动阵列基板的驱动电路的结构示意图；  1 is a schematic structural view of a driving circuit of a prior art driving array substrate;
图 2为本发明实施例一提供的阵列基板的结构示意图；  2 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present invention;
图 3为本发明实施例一提供的驱动电路的结构示意图之一；  3 is a schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention;
图 4为本发明实施例一提供的驱动电路的结构示意图之二；  4 is a second schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention;
图 5为本发明实施例二提供的驱动电路的结构示意图；  FIG. 5 is a schematic structural diagram of a driving circuit according to Embodiment 2 of the present invention; FIG.
图 6为本发明实施例三提供的驱动电路的结构示意图；  6 is a schematic structural diagram of a driving circuit according to Embodiment 3 of the present invention;
图 7为图 3所示的驱动电路对应的时序图；  7 is a timing chart corresponding to the driving circuit shown in FIG. 3;
图 8为图 4所示的驱动电路对应的时序图。 具体实施方式  Fig. 8 is a timing chart corresponding to the drive circuit shown in Fig. 4. detailed description
本发明实施例提供了一种驱动电路、 驱动方法及显示装置， 用以提高显 示装置的刷新率。  Embodiments of the present invention provide a driving circuit, a driving method, and a display device for improving a refresh rate of a display device.
本发明提供的阵列基板包括第一显示区域的像素和第二显示区域的像 素， 本发明实施例提供的驱动电路同时驱动所述第一显示区域的一行像素和 第二显示区域的一行像素， 从而与图 1 中所示的现有阵列基板的驱动电路相 比， 在扫描信号的刷新频率不变的情况下可以将显示装置的刷新率提高至两 倍， 或者在显示装置的刷新率不便的情况下可以将与每一条栅极扫描线相连 的一行像素的充电时间延长至两倍。  The array substrate provided by the present invention includes a pixel of the first display area and a pixel of the second display area. The driving circuit provided by the embodiment of the present invention simultaneously drives a row of pixels of the first display area and a row of pixels of the second display area, thereby Compared with the driving circuit of the conventional array substrate shown in FIG. 1, the refresh rate of the display device can be doubled under the condition that the refresh frequency of the scanning signal is constant, or the refresh rate of the display device is inconvenient. The charging time of one row of pixels connected to each gate scan line can be extended to two times.
具体地， 逐行扫描第一显示区域的栅极扫描线， 同时逐行扫描第二显示 区域的栅极扫描线， 并且在每一个扫描脉沖时间段内同时开启第一显示区域 中的一条栅极扫描线和第二显示区域的一条栅极扫描线， 从而提高显示装置 显示图像的刷新率。 发光显示领域等。  Specifically, the gate scan lines of the first display area are scanned line by line while the gate scan lines of the second display area are scanned line by line, and one gate in the first display area is simultaneously turned on in each scan pulse period. The scan line and one gate scan line of the second display area improve the refresh rate of the display image displayed by the display device. Illuminated display field, etc.
在具体实施过程中， 阵列基板上的驱动电路主要包括时序控制电路， 栅 极驱动电路（即扫描驱动电路）、 和源极驱动电路（即数据驱动电路）， 以及 各栅极扫描线和数据信号线。  In a specific implementation process, the driving circuit on the array substrate mainly includes a timing control circuit, a gate driving circuit (ie, a scanning driving circuit), and a source driving circuit (ie, a data driving circuit), and each of the gate scanning lines and the data signals. line.
下面通过附图首先具体说明本发明实施例提供的阵列基板、 驱动电路和 驱动方法。 参见图 2, 本发明实施例提供的阵列基板， 包括： 基板 1; 以及基板 1 上的由多个像素 2形成的像素阵列（2m行 n列像素形成的像素阵列， 所述 m 和 n为正整数 )。 The array substrate, the driving circuit and the driving method provided by the embodiments of the present invention are first described in detail below with reference to the accompanying drawings. Referring to FIG. 2, an array substrate according to an embodiment of the present invention includes: a substrate 1; and a pixel array formed by a plurality of pixels 2 on the substrate 1 (a pixel array formed by 2 m rows and n columns of pixels, wherein the m and n are positive Integer).
其中， 前 m行 n列像素形成第一显示区域 3 (如上虚线框内电路）， 后 m 行 n列像素形成第二显示区域 4 (如下虚线框内电路）；  Wherein, the first m rows and n columns of pixels form the first display area 3 (as in the dotted line frame circuit), and the rear m rows and n columns of pixels form the second display area 4 (as shown in the dotted line frame circuit);
本发明实施例提供的驱动上述阵列基板实现图像显示的驱动电路因栅极 驱动电路的不同而不同， 下面针对不同的栅极驱动电路分别说明。  The driving circuit for driving the array substrate to realize image display according to the embodiment of the present invention differs depending on the gate driving circuit, and is described below for different gate driving circuits.
实施例一：  Embodiment 1:
参见图 3, 本实施例一提供的驱动电路包括：  Referring to FIG. 3, the driving circuit provided in the first embodiment includes:
位于第一显示区域 3中并且分别与所述前 m行像素相连的 m条栅极扫描 线（如图 3中 G1U、 G2U、 G3U G(m-l)U、 GmU )、 第一 n条数据信号 线（如图 3中 D1U、 D2U、 D3U、 D4U D(n-3)U、 D(n-2)U、 D(n-l)U、 m gate scan lines (such as G1U, G2U, G3U G(ml) U, GmU in FIG. 3) located in the first display area 3 and respectively connected to the pixels of the first m rows, and the first n data signal lines (Figure 3, D1U, D2U, D3U, D4U D(n-3)U, D(n-2)U, D(nl)U,
DnU ) , 以及与所述第一 n条数据信号线相连的第一源极驱动电路 32; DnU), and a first source driving circuit 32 connected to the first n data signal lines;
位于第二显示区域 4中并且分别与所述后 m行像素相连的 m条栅极扫描 线（如图 3中 G1D、 G2D、 G3D G(m-1)D、 GmD )、 第二 n条数据信号 线（如图 3中 DID, D2D、 D3D、 D4D D(n-3)D、 D(n-2)D、 D(n-1)D、 m gate scan lines (such as G1D, G2D, G3D G(m-1)D, GmD in FIG. 3) located in the second display area 4 and respectively connected to the rear m rows of pixels, and the second n pieces of data Signal line (such as DID, D2D, D3D, D4D D(n-3)D, D(n-2)D, D(n-1)D,
DnD ) , 以及与所述第二 n条数据信号线相连的第二源极驱动电路 42。 DnD), and a second source driving circuit 42 connected to the second n data signal lines.
实施例一提供的栅极驱动电路由 2m个移位寄存器单元（ Shift Register ) 组成， 其中， 与第一显示区域 3对应的 m个移位寄存器单元构成第一移位寄 存器 31 ;与第二显示区域 4对应的 m个移位寄存器单元构成第二移位寄存器 41。  The gate driving circuit provided in the first embodiment is composed of 2m shift register units (Shift Register), wherein the m shift register units corresponding to the first display area 3 constitute the first shift register 31; and the second display The m shift register units corresponding to the area 4 constitute the second shift register 41.
第一移位寄存器 31中的第一个移位寄存器单元与第二移位寄存器 41中 的第一个移位寄存器单元相连。  The first shift register unit in the first shift register 31 is coupled to the first shift register unit in the second shift register 41.
在此情况下，对于每一个移位寄存器，其中的 m个移位寄存器单元级联； 即第一移位寄存器 31 中的第一个移位寄存器单元至第 m个移位寄存器单元 级联（即依次首尾相连）； 第二移位寄存器 41 中的第一个移位寄存器单元至 第 m个移位寄存器单元级联。  In this case, for each shift register, m shift register units are cascaded; that is, the first shift register unit in the first shift register 31 is cascaded to the mth shift register unit ( That is, the first shift register unit in the second shift register 41 is cascaded to the mth shift register unit.
可替代地，第一移位寄存器 31中的第一个移位寄存器单元与第二移位寄 存器 41中的第 m个移位寄存器单元相连。  Alternatively, the first shift register unit in the first shift register 31 is connected to the mth shift register unit in the second shift register 41.
在此情况下， 对于每一个移位寄存器， 其中的 m个移位寄存器单元也级 联； 即第一移位寄存器 31 中的第一个移位寄存器单元至第 m个移位寄存器 单元级联 (即依次首尾相连）； 第二移位寄存器 41中的第 m个移位寄存器单 元至第一个移位寄存器单元级联。 In this case, for each shift register, m shift register units are also cascaded; that is, the first shift register unit in the first shift register 31 to the mth shift register The cells are cascaded (ie, connected end to end in sequence); the mth shift register unit in the second shift register 41 is cascaded to the first shift register unit.
可替代地， 第一移位寄存器 31 中的第 m个移位寄存器单元与第二移位 寄存器 41中的第一个移位寄存器单元相连。  Alternatively, the mth shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41.
在此情况下， 对于每一个移位寄存器， 其中的 m个移位寄存器单元也级 联； 即第一移位寄存器 31 中的第 m个移位寄存器单元至第一个移位寄存器 单元级联 (即依次首尾相连）； 第二移位寄存器 41 中的第一个移位寄存器单 元至第 m个移位寄存器单元级联。  In this case, for each shift register, the m shift register units are also cascaded; that is, the mth shift register unit in the first shift register 31 is cascaded to the first shift register unit. (ie, connected end to end in sequence); the first shift register unit in the second shift register 41 is cascaded to the mth shift register unit.
所述 2m个移位寄存器单元分别与所述 2m条栅极扫描线——对应相连； 即所述第一移位寄存器 31中的 m个移位寄存器单元分别和与所述前 m行像 素相连的 m条栅极扫描线相连， 所述第二移位寄存器 41中的 m个移位寄存 器单元分别和与所述后 m行像素相连的 m条栅极扫描线相连。  The 2m shift register units are respectively connected to the 2m gate scan lines--that is, the m shift register units in the first shift register 31 are respectively connected to the first m-row pixels. The m gate scan lines are connected, and the m shift register units in the second shift register 41 are respectively connected to m gate scan lines connected to the rear m rows of pixels.
在时序控制器（如图 3中的 STV所示意）的控制下， 栅极驱动电路同时 逐行驱动第一显示区域 3和第二显示区域 4中的前 m行像素和后 m行像素以 便实现图像显示。  Under the control of the timing controller (illustrated by STV in FIG. 3), the gate driving circuit simultaneously drives the first m rows of pixels and the last m rows of pixels in the first display region 3 and the second display region 4 row by row in order to realize Image display.
图 3为第一移位寄存器 31中的第一个移位寄存器单元与第二移位寄存器 41中的第一个移位寄存器单元相连的驱动电路。  3 is a driving circuit in which the first shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41.
图 4为第一移位寄存器 31中的第 m个移位寄存器单元与第二移位寄存 器 41中的第一个移位寄存器单元相连的驱动电路。  4 is a drive circuit in which the mth shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41.
以图 3所示的阵列基板为例，实施例一所示的驱动电路的驱动方法包括： 在显示每一帧图像的过程中， 控制第一移位寄存器中的第一个移位寄存 器单元和第二移位寄存器中的第一个移位寄存器单元同时输出所述扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号；  Taking the array substrate shown in FIG. 3 as an example, the driving method of the driving circuit shown in the first embodiment includes: controlling the first shift register unit in the first shift register and displaying the image of each frame. The first shift register unit in the second shift register simultaneously outputs the scan signal, and controls the first source driving circuit and the second source driving circuit to output respective data signals;
控制第一移位寄存器中的第二个移位寄存器单元和第二移位寄存器中的 第二个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号；  Controlling a second shift register unit in the first shift register and a second shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the second source driving The circuit outputs respective data signals;
控制第一移位寄存器中的第三个移位寄存器单元和第二移位寄存器中的 第三个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号；  Controlling a third shift register unit in the first shift register and a third shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driving circuit and the second source driving The circuit outputs respective data signals;
以此类推， 直到控制第一移位寄存器中的第 m个移位寄存器单元和第二 移位寄存器中的第 m个移位寄存器单元同时输出所述扫描信号， 控制第一源 极驱动电路和第二源极驱动电路输出各自的数据信号为止。 And so on, until the mth shift register unit in the first shift register and the mth shift register unit in the second shift register simultaneously output the scan signal, controlling the first source The pole drive circuit and the second source drive circuit output respective data signals.
图 3所示的驱动电路， 在具体实施过程中， 时序控制器只需要向第一移 位寄存器中的第一个移位寄存器单元和第二移位寄存器中的第一个移位寄存 器单元同时输入扫描信号即可， 由于与每一个显示区域对应的移位寄存器单 元级联， 因此每一个移位寄存器中的第一个移位寄存器单元的输出为第二个 移位寄存器单元的输入； 第二个移位寄存器单元的输出为第三个移位寄存器 单元的输入； 以此类推， 第 m-1个移位寄存器单元的输出为第 m个移位寄存 器单元的输入。  In the driving circuit shown in FIG. 3, in a specific implementation, the timing controller only needs to simultaneously input the first shift register unit in the first shift register and the first shift register unit in the second shift register. Inputting the scan signal, since the shift register unit corresponding to each display area is cascaded, the output of the first shift register unit in each shift register is the input of the second shift register unit; The output of the two shift register units is the input of the third shift register unit; and so on, the output of the m-1th shift register unit is the input of the mth shift register unit.
实施例二：  Embodiment 2:
参见图 5 , 栅极驱动电路由一个移位寄存器组成， 该移位寄存器由 m个 级联的移位寄存器单元组成， 所述 m个移位寄存器单元分别与第一显示区域 Referring to FIG. 5, the gate driving circuit is composed of a shift register composed of m cascaded shift register units, and the m shift register units and the first display area, respectively.
3中的 m条栅极扫描线——对应相连， 并且同时分别与第二显示区域 4中的 m条栅极扫描线——对应相连。 The m gate scan lines of 3 are correspondingly connected, and are respectively connected to the m gate scan lines in the second display area 4, respectively.
图 5所示的驱动电路， 第一显示区域的第一条栅极扫描线与第二显示区 域的第一条栅极扫描线相连， 第一显示区域的第二条栅极扫描线与第二显示 区域的第二条栅极扫描线相连， 直到第一显示区域的第 m条栅极扫描线与第 二显示区域的第 m条栅极扫描线相连， 时序控制器向第一个移位寄存器单元 输入扫描信号。  In the driving circuit shown in FIG. 5, the first gate scan line of the first display area is connected to the first gate scan line of the second display area, and the second gate scan line of the first display area is second. a second gate scan line of the display area is connected until the mth gate scan line of the first display area is connected to the mth gate scan line of the second display area, and the timing controller is to the first shift register The unit inputs the scan signal.
图 5所示的驱动电路的驱动方法， 包括：  The driving method of the driving circuit shown in FIG. 5 includes:
在显示每一帧图像的过程中， 控制第一个移位寄存器单元向与之相连的 两条栅极扫描线输出扫描信号， 控制第一源极驱动电路和第二源极驱动电路 输出各自的数据信号；  During the process of displaying each frame of image, the first shift register unit is controlled to output a scan signal to the two gate scan lines connected thereto, and the first source drive circuit and the second source drive circuit are controlled to output respective ones. Data signal
控制第二个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号；  Controlling the second shift register unit to output a scan signal to the two gate scan lines connected thereto, and controlling the first source drive circuit and the second source drive circuit to output respective data signals;
控制第三个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号；  Controlling the third shift register unit to output a scan signal to the two gate scan lines connected thereto, and controlling the first source drive circuit and the second source drive circuit to output respective data signals;
以此类推， 直到控制第 m个移位寄存器单元向与之相连的两条栅极扫描 线输出扫描信号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数 据信号。  By analogy, until the mth shift register unit is controlled to output a scan signal to the two gate scan lines connected thereto, the first source drive circuit and the second source drive circuit are controlled to output respective data signals.
同理， 在具体实施过程中， 时序控制器只需要向第一个移位寄存器单元 输入扫描信号即可， 由于移位寄存器单元级联， 因此上一级移位寄存器单元 的输出是下一移位寄存器单元的输入。 Similarly, in the specific implementation process, the timing controller only needs to input the scan signal to the first shift register unit. Since the shift register unit is cascaded, the shift register unit of the previous stage is used. The output is the input to the next shift register unit.
可替代地， 可以修改图 5所示的驱动电路， 使得第一显示区域的第一条 栅极扫描线与第二显示区域的第 m条栅极扫描线相连， 第一显示区域的第二 条栅极扫描线与第二显示区域的第 (m-1)条栅极扫描线相连， 直到第一显示区 域的第 m条栅极扫描线与第二显示区域的第一条栅极扫描线相连， 时序控制 器向第一个移位寄存器单元输入扫描信号。  Alternatively, the driving circuit shown in FIG. 5 may be modified such that the first gate scan line of the first display area is connected to the mth gate scan line of the second display area, and the second line of the first display area The gate scan line is connected to the (m-1)th gate scan line of the second display area until the mth gate scan line of the first display area is connected to the first gate scan line of the second display area The timing controller inputs a scan signal to the first shift register unit.
针对第一源极驱动电路而言，图 5所示的扫描方式为从上到下逐行扫描， 但是所述扫描方式也可以为从下到上逐行扫描。  For the first source driving circuit, the scanning mode shown in FIG. 5 is a progressive scanning from top to bottom, but the scanning method may also be a progressive scanning from bottom to top.
扫描方式为从下到上逐行扫描时， 时序控制器向第 m个移位寄存器单元 输入扫描信号。 在此情况下， 所述第 m个移位寄存器单元到所述第一个移位 寄存器单元级联。  When the scan mode is a page-by-row scan from bottom to top, the timing controller inputs a scan signal to the mth shift register unit. In this case, the mth shift register unit is cascaded to the first shift register unit.
实施例三：  Embodiment 3:
参见图 6, 栅极驱动电路为栅极驱动芯片 6, 栅极驱动芯片 6分别与 2m 条栅极扫描线相连；  Referring to FIG. 6, the gate driving circuit is a gate driving chip 6, and the gate driving chip 6 is respectively connected to 2m gate scanning lines;
其中，第一显示区域 3中的 m条栅极扫描线和第二显示区域 4中的 m条 栅极扫描线——对应相连。  The m gate scan lines in the first display area 3 and the m gate scan lines in the second display area 4 are correspondingly connected.
例如， 第一显示区域 3中的第一条栅极扫描线与第二显示区域的第一条 栅极扫描线相连， 第一显示区域的第二条栅极扫描线与第二显示区域的第二 条栅极扫描线相连， 依此类推， 直到第一显示区域的第 m条栅极扫描线与第 二显示区域的第 m条栅极扫描线相连。  For example, the first gate scan line in the first display area 3 is connected to the first gate scan line of the second display area, and the second gate scan line of the first display area and the second display area are The two gate scan lines are connected, and so on, until the mth gate scan line of the first display area is connected to the mth gate scan line of the second display area.
可替代地， 第一显示区域的第一条栅极扫描线与第二显示区域的第 m条 栅极扫描线相连， 第一显示区域的第二条栅极扫描线与第二显示区域的第 (m-1)条栅极扫描线相连，依此类推， 直到第一显示区域的第 m条栅极扫描线 与第二显示区域的第一条栅极扫描线相连。  Alternatively, the first gate scan line of the first display area is connected to the mth gate scan line of the second display area, and the second gate scan line of the first display area and the second display area are (m-1) gate scan lines are connected, and so on, until the mth gate scan line of the first display area is connected to the first gate scan line of the second display area.
图 6所示的驱动电路的驱动方法包括：  The driving method of the driving circuit shown in FIG. 6 includes:
控制所述栅极驱动芯片逐行向第一显示区域的栅极扫描线和第二显示区 域的栅极扫描线输出扫描信号， 同时控制第一源极驱动电路和第二源极驱动 电路输出各自的数据信号。  Controlling the gate driving chip to output a scan signal to the gate scan line of the first display area and the gate scan line of the second display area row by row, and simultaneously controlling the output of the first source driving circuit and the second source driving circuit Data signal.
图 3至图 6所示驱动电路， 第一显示区域 3和第二显示区域 4中的栅极 扫描线呈多行排列， 第一显示区域 3和第二显示区域 4中的数据信号线呈多 列排列。 具体地， 第一显示区域 3中的所有栅极扫描线依次相邻， 第二显示区域 4中的所有栅极扫描线依次相邻。 In the driving circuit shown in FIG. 3 to FIG. 6, the gate scanning lines in the first display area 3 and the second display area 4 are arranged in a plurality of rows, and the data signal lines in the first display area 3 and the second display area 4 are large. Column arrangement. Specifically, all the gate scan lines in the first display area 3 are sequentially adjacent, and all the gate scan lines in the second display area 4 are sequentially adjacent.
第一显示区域 3中的 n条数据信号线与第一显示区域中的 m条栅极扫描 线交叉排列。  The n data signal lines in the first display area 3 are arranged to cross the m gate scanning lines in the first display area.
第二显示区域 3中的 n条数据信号线与第二显示区域中的 m条栅极扫描 线交叉排列。  The n data signal lines in the second display area 3 are arranged to intersect with the m gate scanning lines in the second display area.
相应地， 图 3-图 6所示的栅极驱动电路， 第一源极驱动电路和第二源极 驱动电路位于整个阵列基板的***区域， 不影响显示装置的开口率。 这样的 设置方式便于电路结构的布线， 提高显示装置图像的显示品质。  Accordingly, in the gate driving circuit shown in FIGS. 3 to 6, the first source driving circuit and the second source driving circuit are located in the peripheral region of the entire array substrate, and do not affect the aperture ratio of the display device. Such a setting method facilitates the wiring of the circuit structure and improves the display quality of the image of the display device.
较佳地， 所述栅极驱动电路可以通过制作在阵列基板上的移位寄存器实 现， 也可以通过栅极驱动芯片（Integrated Circuit Card, IC)实现。  Preferably, the gate driving circuit can be implemented by a shift register formed on the array substrate, or can be realized by an integrated circuit card (IC).
需要说明的是， 本发明实施例一至实施例三提供的驱动电路不限于图 3- 图 6所示的结构， 还可以包括参考电压源和电压源转换电路等模块。  It should be noted that the driving circuit provided in Embodiments 1 to 3 of the present invention is not limited to the structure shown in FIG. 3 to FIG. 6, and may further include modules such as a reference voltage source and a voltage source conversion circuit.
下面结合图 7和图 8所示的时序电路图具体说明本发明实施例提供的驱 动电路的驱动方法。  The driving method of the driving circuit provided by the embodiment of the present invention will be specifically described below with reference to the timing circuit diagrams shown in FIG. 7 and FIG.
本发明栅极驱动电路用于循序地对特定的栅极扫描线输出适当的栅极电 压以驱动与该栅极扫描线相连的像素； 源极驱动电路将与该栅极扫描线相连 的每个像素对应的像素电压输入到与该栅极扫描线相连的每个像素。  The gate driving circuit of the present invention is for sequentially outputting an appropriate gate voltage to a specific gate scan line to drive a pixel connected to the gate scan line; the source driving circuit will connect each of the gate scan lines The pixel voltage corresponding to the pixel is input to each pixel connected to the gate scan line.
本发明通过在一个脉沖时间段内同时开启两条栅极扫描线， 并同时输入 数据信号至这两条栅极扫描线所对应的数据信号线。 这样， 与图 1 中所示的 现有阵列基板的驱动电路相比，在显示装置显示图像的刷新率不变的情况下， 阵列基板上的每条栅极扫描线的开启次数就减半， 换句话说， 增加了了每行 像素的充电时间； 另一方面， 在阵列基板上的每条栅极扫描线的开启次数不 变的情况下， 显示装置显示图像的刷新率就可以加倍。  The present invention simultaneously turns on two gate scan lines in one pulse period and simultaneously inputs data signals to the data signal lines corresponding to the two gate scan lines. Thus, compared with the driving circuit of the conventional array substrate shown in FIG. 1, in the case where the refresh rate of the display image of the display device is constant, the number of times of opening each of the gate scanning lines on the array substrate is halved. In other words, the charging time of each row of pixels is increased; on the other hand, in the case where the number of times of opening of each gate scanning line on the array substrate is constant, the refresh rate of the image displayed by the display device can be doubled.
本发明实施例提供了一种驱动上述阵列基板实现图像显示的驱动方法， 包括：  The embodiment of the invention provides a driving method for driving the array substrate to realize image display, which includes:
在显示一帧图像的过程中， 控制栅极驱动电路同时对第一显示区域的 m 条栅极扫描线和第二显示区域的 m条栅极扫描线进行逐行扫描， 使得在每一 次输出扫描信号时都同时向所述第一显示区域的 m条栅极扫描线中的一条栅 极扫描线和所述第二显示区域的 m条栅极扫描线中的一条栅极扫描线输出扫 描信号， 在每一次输出扫描信号时， 控制第一显示区域的第一源极驱动电路 和第二显示区域的第二源极驱动电路向与各自相连的数据信号线输出各自的 数据信号。 In the process of displaying one frame of image, the control gate driving circuit simultaneously scans the m gate scan lines of the first display area and the m gate scan lines of the second display area line by line, so that each output scan is performed. And outputting a scan signal to one of the m gate scan lines of the first display area and one of the m gate scan lines of the second display area. Controlling the first source driving circuit of the first display area every time the scanning signal is output The second source driving circuit and the second display region output respective data signals to the respective data signal lines connected thereto.
图 7为与图 3所示的驱动电路对应的时序控制器的时序信号示意图。 在一帧图像的显示时间内的第一个扫描脉沖时间段， 控制第一显示区域 中的第一条栅极扫描线 G1U和第二显示区域中的第一条栅极扫描线 G1D高 电平开启， 其余栅极扫描线低电平关闭；  Fig. 7 is a timing chart showing the timing controller corresponding to the drive circuit shown in Fig. 3. Controlling the first gate scan line G1U in the first display region and the first gate scan line G1D in the second display region at a first scan pulse period of the display time of one frame of image On, the remaining gate scan lines are off at a low level;
第二个扫描脉沖时间段， 控制第一显示区域中的第二条栅极扫描线 G2U 和第二显示区域中的第二条栅极扫描线 G2D高电平开启，其余栅极扫描线低 电平关闭；  a second scan pulse period, controlling the second gate scan line G2U in the first display area and the second gate scan line G2D in the second display area to be turned on at a high level, and the remaining gate scan lines are low. Closed
第三个扫描脉沖时间段， 控制第一显示区域中的第三条栅极扫描线 G3U 和第二显示区域中的第三条栅极扫描线 G3D高电平开启，其余栅极扫描线低 电平关闭；  The third scan pulse period controls that the third gate scan line G3U in the first display area and the third gate scan line G3D in the second display area are turned on at a high level, and the remaining gate scan lines are low. Closed
以此类推， 第 m-1个扫描脉沖时间段， 控制第一显示区域中的第 m-1条 栅极扫描线 G(m-l)U和第二显示区域中的第二条栅极扫描线 G(m-1)D高电平 开启， 其余栅极扫描线低电平关闭；  And so on, the m-1th scan pulse period, controlling the m-1th gate scan line G(ml)U in the first display area and the second gate scan line G in the second display area (m-1) D high level is turned on, and the remaining gate scan lines are turned off at low level;
第 m个扫描脉沖时间段,控制第一显示区域中的第 m条栅极扫描线 GmU 和第二显示区域中的第 m条栅极扫描线 GmD高电平开启， 其余栅极扫描线 低电平关闭。  The mth scan pulse period, controlling the mth gate scan line GmU in the first display area and the mth gate scan line GmD in the second display area to be turned on at a high level, and the remaining gate scan lines are low. Flat closed.
第一显示区域和第二显示区域中的栅极扫描线在一帧图像的显示时间内 扫描完毕。  The gate scan lines in the first display area and the second display area are scanned within the display time of one frame of image.
图 8为与图 4所示的驱动电路对应的时序控制器的时序信号示意图。 在一帧图像的显示时间内， 在第一个扫描脉沖时间段， 控制第一显示区 域中的第 m条栅极扫描线 GmU和第二显示区域中的第一条栅极扫描线 G1D 为高电平 (对应图 8中的高电平开启状态）， 其余栅极扫描线低电平；  Fig. 8 is a timing chart showing the timing controller corresponding to the drive circuit shown in Fig. 4. Controlling the mth gate scan line GmU in the first display area and the first gate scan line G1D in the second display area to be high during the first scan pulse period during the display time of one frame of image Level (corresponding to the high level on state in Figure 8), the remaining gate scan lines are low;
第二个扫描脉沖时间段， 控制第一显示区域中的第 m-1 条栅极扫描线 a second scan pulse period, controlling the m-1th gate scan line in the first display area
G(m-l)U和第二显示区域中的第二条栅极扫描线 G2D为高电平， 其余栅极扫 描线低电平； G(m-l)U and the second gate scan line G2D in the second display area are at a high level, and the remaining gate scan lines are at a low level;
第三个扫描脉沖时间段， 控制第一显示区域中的第 m-2 条栅极扫描线 G(m-2)U和第二显示区域中的第三条栅极扫描线 G3D为高电平， 其余栅极扫 描线低电平；  a third scan pulse period, controlling the m-2th gate scan line G(m-2)U in the first display area and the third gate scan line G3D in the second display area to be at a high level , the remaining gate scan lines are low;
以此类推， 第 m-1个扫描脉沖时间段， 控制第一显示区域中的第二条栅 极扫描线 G2U和第二显示区域中的第 m-1条栅极扫描线 G(m-1)D为高电平， 其余栅极扫描线低电平； And so on, the m-1th scan pulse period, controlling the second grid in the first display area The pole scan line G2U and the m-1th gate scan line G(m-1)D in the second display region are at a high level, and the remaining gate scan lines are at a low level;
直到第 m个扫描脉沖时间段，控制第一显示区域中的第一条栅极扫描线 G1U和第二显示区域中的第 m条栅极扫描线 GmD为高电平， 其余栅极扫描 线氏电平；  Up to the mth scan pulse period, controlling the first gate scan line G1U in the first display region and the mth gate scan line GmD in the second display region to be at a high level, and the remaining gate scan lines Level
第一显示区域和第二显示区域中的栅极扫描线在一帧图像的显示时间内 扫描完毕。  The gate scan lines in the first display area and the second display area are scanned within the display time of one frame of image.
当与现有扫描信号脉沖宽度相同的情况下， 图像的刷新率提高一倍。 当 与现有刷新率相同的情况下， 像素的充电时间提高了一倍。  When the pulse width of the existing scan signal is the same, the refresh rate of the image is doubled. When the same refresh rate as the existing one, the charging time of the pixel is doubled.
本发明实施例提供的阵列基板和驱动方法优选适用于集成度较高的阵列 基板， 例如适用于低温多晶硅技术（ Low Temperature Poly-silicon, LTPS )。  The array substrate and the driving method provided by the embodiments of the present invention are preferably applied to an array substrate with higher integration, for example, low temperature poly-silicon (LTPS).
本发明实施例还提供一种显示装置， 该显示装置包括本发明实施例提供 的驱动电路， 所述显示装置可以是液晶面板、 液晶显示器、 液晶电视、 有机 电致发光显示 OLED面板、 OLED显示器、 OLED电视或电子纸等显示装置。  The embodiment of the present invention further provides a display device, which includes the driving circuit provided by the embodiment of the present invention, and the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, an organic electroluminescence display OLED panel, an OLED display, A display device such as an OLED television or an electronic paper.
本发明实施例通过设置两个显示区域（第一显示区域和第二显示区域） 同时驱动阵列基板上的像素阵列， 提高阵列基板图像显示的刷新率。 具体地， 逐行开启该电路中第一显示区域的第一组栅极扫描线， 逐行开启该电路中第 二显示区域的第二组栅极扫描线， 在开启第一显示区域中所述第一组栅极扫 描线中的某一条栅极扫描线时， 也同时开启第二显示区域中所述第二组栅极 扫描线中的一条栅极扫描线， 也就是说， 在同一时刻同时开启阵列基板上的 两条不同栅极扫描线， 这两条栅极扫描线分别与两个不同的源极驱动电路连 接， 当两条栅极扫描线开启时， 两个源极驱动电路分别输入各条数据信号线 对应的数据信号， 实现图像显示。 由上可知， 在与现有扫描信号脉沖宽度相 同的情况下， 阵列基板显示图像的刷新率至少为原来的二倍。  The embodiment of the invention improves the refresh rate of the image display of the array substrate by setting two display regions (the first display region and the second display region) to simultaneously drive the pixel array on the array substrate. Specifically, the first group of gate scan lines of the first display area in the circuit are turned on line by line, and the second group of gate scan lines of the second display area in the circuit are turned on line by line, and the first display area is turned on in the first display area. When one of the first group of gate scan lines scans the line, one of the second group of gate scan lines in the second display area is simultaneously turned on, that is, simultaneously at the same time Two different gate scan lines on the array substrate are turned on, and the two gate scan lines are respectively connected to two different source driving circuits. When the two gate scan lines are turned on, the two source driving circuits are respectively input. The data signals corresponding to the respective data signal lines realize image display. As can be seen from the above, the refresh rate of the image displayed on the array substrate is at least twice as large as the pulse width of the conventional scanning signal.
显然， 本领域的技术人员可以对本发明进行各种改动和变型而不脱离本 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。。  It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of the inventions .

Claims

权 利 要 求 书 claims
1、一种用于驱动阵列基板上的像素以实现图像显示的驱动电路，其特征 在于， 所述阵列基板包括第一显示区域和第二显示区域， 所述驱动电路包括： 与所述第一显示区域中的像素相连的第一 m条栅极扫描线和第一 n条数 据信号线； 1. A driving circuit for driving pixels on an array substrate to achieve image display, characterized in that the array substrate includes a first display area and a second display area, and the driving circuit includes: and the first display area. The first m gate scanning lines and the first n data signal lines connected to the pixels in the display area;
与所述第二显示区域中的像素相连的第二 m条栅极扫描线和第二 n条数 据信号线； The second m gate scanning lines and the second n data signal lines connected to the pixels in the second display area;
与所述第一 m条栅极扫描线和所述第二 m条栅极扫描线相连的栅极驱动 电路； A gate drive circuit connected to the first m gate scan lines and the second m gate scan lines;
与第一显示区域的第一 n条数据信号线相连的第一源极驱动电路和与第 二显示区域的第二 n条数据信号线相连的第二源极驱动电路； a first source driving circuit connected to the first n data signal lines of the first display area and a second source driving circuit connected to the second n data signal lines of the second display area;
所述栅极驱动电路同时对第一显示区域的第一 m条栅极扫描线和第二显 示区域的第二 m条栅极扫描线进行逐行扫描，使得同时向所述第一 m条栅极 扫描线中的一条栅极扫描线和所述第二 m条栅极扫描线中的一条栅极扫描线 输出扫描信号， 同时所述第一源极驱动电路和所述第二源极驱动电路分别向 各自所连接的数据信号线输出各自的数据信号，其中，所述 m和 n为正整数。 The gate driving circuit simultaneously performs line-by-line scanning on the first m gate scanning lines of the first display area and the second m gate scanning lines of the second display area, so that the first m gate scanning lines are simultaneously scanned line by line. One of the gate scanning lines and one of the second m gate scanning lines output scanning signals, and at the same time, the first source driving circuit and the second source driving circuit Respective data signals are output to respective connected data signal lines, where m and n are positive integers.
2、根据权利要求 1所述的驱动电路， 其特征在于， 所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移位寄存器单元包括第一 m个移位寄 存器单元和第二 m个移位寄存器单元， 其中， 分别与所述第一显示区域的第 一 m条栅极扫描线相连的第一 m个移位寄存器单元构成第一移位寄存器，分 别与所述第二显示区域的第二 m条栅极扫描线相连的第二 m个移位寄存器单 元构成第二移位寄存器； 2. The drive circuit according to claim 1, characterized in that, the gate drive circuit is composed of 2m shift register units, and the 2m shift register units include the first m shift register unit and the mth shift register unit. Two m shift register units, wherein the first m shift register units respectively connected to the first m gate scan lines of the first display area constitute a first shift register, and are respectively connected to the second m shift register units. The second m shift register units connected to the second m gate scan lines of the display area constitute a second shift register;
所述第一移位寄存器中的第一个移位寄存器单元与第二移位寄存器中的 第一个或第 m个移位寄存器单元相连； The first shift register unit in the first shift register is connected to the first or mth shift register unit in the second shift register;
其中， 每个移位寄存器中的 m个移位寄存器单元级联。 Among them, m shift register units in each shift register are cascaded.
3、根据权利要求 1所述的驱动电路， 其特征在于， 所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移位寄存器单元包括第一 m个移位寄 存器单元和第二 m个移位寄存器单元， 其中， 分别与所述第一显示区域的第 一 m条栅极扫描线相连的第一 m个移位寄存器单元构成第一移位寄存器，分 别与所述第二显示区域的第二 m条栅极扫描线相连的第二 m个移位寄存器单 元构成第二移位寄存器； 3. The drive circuit according to claim 1, characterized in that, the gate drive circuit is composed of 2m shift register units, and the 2m shift register units include the first m shift register unit and the mth shift register unit. Two m shift register units, wherein the first m shift register units respectively connected to the first m gate scan lines of the first display area constitute a first shift register, and are respectively connected to the second m shift register units. The second m shift register units connected to the second m gate scan lines of the display area elements constitute the second shift register;
所述第一移位寄存器中的第 m个移位寄存器单元与第二移位寄存器中的 第一个或第 m个移位寄存器单元相连； The m-th shift register unit in the first shift register is connected to the first or m-th shift register unit in the second shift register;
其中， 每个移位寄存器单元中的 m个移位寄存器单元级联。 Among them, m shift register units in each shift register unit are cascaded.
4、根据权利要求 1所述的驱动电路， 其特征在于， 所述栅极驱动电路由 m个移位寄存器单元组成， 所述 m个移位寄存器单元分别与第一显示区域的 第一 m条栅极扫描线——对应相连，并且所述 m个移位寄存器单元还分别与 第二显示区域的第二 m条栅极扫描线——对应相连， 其中， 所述 m个移位寄 存器单元级联。 4. The drive circuit according to claim 1, characterized in that, the gate drive circuit is composed of m shift register units, and the m shift register units are respectively connected to the first m lines of the first display area. The gate scan lines are connected correspondingly, and the m shift register units are also respectively connected to the second m gate scan lines of the second display area, where, the m shift register units are Union.
5、根据权利要求 1所述的驱动电路， 其特征在于， 所述栅极驱动电路为 栅极驱动芯片， 所述栅极驱动芯片与所述第一显示区域的第一 m条栅极扫描 线相连； 5. The driving circuit of claim 1, wherein the gate driving circuit is a gate driving chip, and the gate driving chip is connected to the first m gate scanning lines of the first display area. connected; connected
并且，所述第一显示区域的第一 m条栅极扫描线和第二显示区域的第二 m条栅极扫描线——对应相连。 Furthermore, the first m gate scanning lines of the first display area and the second m gate scanning lines of the second display area are connected correspondingly.
6、 一种权利要求 1所述的驱动电路的驱动方法， 其特征在于， 包括： 在显示一帧图像的过程中， 控制栅极驱动电路同时对第一显示区域的第 一 m条栅极扫描线和第二显示区域的第二 m条栅极扫描线进行逐行扫描，使 得在每一次输出扫描信号时都同时向所述第一 m条栅极扫描线中的一条栅极 扫描线和所述第二 m条栅极扫描线中的一条栅极扫描线输出所述扫描信号， 以及 6. A driving method for a driving circuit according to claim 1, characterized by comprising: during the process of displaying a frame of image, controlling the gate driving circuit to simultaneously scan the first m gates of the first display area. Lines and the second m gate scan lines of the second display area are scanned line by line, so that each time a scan signal is output, one of the first m gate scan lines and all the gate scan lines are simultaneously scanned. One of the second m gate scanning lines outputs the scanning signal, and
在每一次输出扫描信号时， 控制与第一显示区域的数据信号线相连的第 一源极驱动电路和第二显示区域的数据信号线相连的第二源极驱动电路向与 各自相连的数据信号线输出各自的数据信号。 Each time a scanning signal is output, the first source driving circuit connected to the data signal line of the first display area and the second source driving circuit connected to the data signal line of the second display area are controlled to provide the data signals connected to each other. lines output their respective data signals.
7、根据权利要求 6所述的驱动方法， 其特征在于， 所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移位寄存器单元包括第一 m个移位寄 存器单元和第二 m个移位寄存器单元， 其中， 分别与所述第一显示区域的第 一 m条栅极扫描线相连的第一 m个移位寄存器单元构成第一移位寄存器，分 别与所述第二显示区域的第二 m条栅极扫描线相连的第二 m个移位寄存器单 元构成第二移位寄存器； 所述第一移位寄存器中的第一个移位寄存器单元与 第二移位寄存器中的第一个或第 m个移位寄存器单元相连； 其中， 每个移位 寄存器中的 m个移位寄存器单元级联， 在显示一帧图像的过程中， 所述驱动方法具体为： 7. The driving method according to claim 6, wherein the gate driving circuit is composed of 2m shift register units, and the 2m shift register units include a first m shift register unit and a first m shift register unit. Two m shift register units, wherein the first m shift register units respectively connected to the first m gate scan lines of the first display area constitute a first shift register, and are respectively connected to the second m shift register units. The second m shift register units connected to the second m gate scan lines of the display area constitute a second shift register; the first shift register unit in the first shift register and the second shift register The first or mth shift register unit in is connected; where, m shift register units in each shift register are cascaded, In the process of displaying one frame of image, the driving method is specifically:
控制第一移位寄存器中的第一个移位寄存器单元和第二移位寄存器中的 第一个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号； Control the first shift register unit in the first shift register and the first shift register unit in the second shift register to simultaneously output the scan signal, and control the first source driver circuit and the second source driver The circuits output respective data signals;
控制第一移位寄存器中的第二个移位寄存器单元和第二移位寄存器中的 第二个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号； Control the second shift register unit in the first shift register and the second shift register unit in the second shift register to simultaneously output the scan signal, control the first source driver circuit and the second source driver The circuits output respective data signals;
控制第一移位寄存器中的第三个移位寄存器单元和第二移位寄存器中的 第三个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号； Control the third shift register unit in the first shift register and the third shift register unit in the second shift register to simultaneously output the scan signal, control the first source driver circuit and the second source driver The circuits output respective data signals;
以此类推， 直到控制第一移位寄存器中的第 m个移位寄存器单元和第二 移位寄存器中的第 m个移位寄存器单元同时输出所述扫描信号， 控制第一源 极驱动电路和第二源极驱动电路输出各自的数据信号为止。 By analogy, until the m-th shift register unit in the first shift register and the m-th shift register unit in the second shift register are controlled to simultaneously output the scan signal, the first source driving circuit and until the second source driving circuit outputs respective data signals.
8、根据权利要求 6所述的驱动方法， 其特征在于， 所述栅极驱动电路由 2m个移位寄存器单元组成，所述 2m个移位寄存器单元包括第一 m个移位寄 存器单元和第二 m个移位寄存器单元， 其中， 分别与所述第一显示区域的第 一 m条栅极扫描线相连的第一 m个移位寄存器单元构成第一移位寄存器，分 别与所述第二显示区域的第二 m条栅极扫描线相连的第二 m个移位寄存器单 元构成第二移位寄存器； 所述第一移位寄存器中的第一个移位寄存器单元与 第二移位寄存器中的第一个或第 m个移位寄存器单元相连； 其中， 每个移位 寄存器中的 m个移位寄存器单元级联， 8. The driving method according to claim 6, characterized in that, the gate driving circuit is composed of 2m shift register units, and the 2m shift register units include a first m shift register unit and a first m shift register unit. Two m shift register units, wherein the first m shift register units respectively connected to the first m gate scan lines of the first display area constitute a first shift register, and are respectively connected to the second m shift register units. The second m shift register units connected to the second m gate scan lines of the display area constitute a second shift register; the first shift register unit in the first shift register and the second shift register The first or mth shift register unit in is connected; where, m shift register units in each shift register are cascaded,
在显示一帧图像的过程中， 所述方法具体为： In the process of displaying a frame of image, the method is specifically:
控制第一移位寄存器中的第一个移位寄存器单元和第二移位寄存器中的 第 m个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和第 二源极驱动电路输出各自的数据信号； Control the first shift register unit in the first shift register and the m-th shift register unit in the second shift register to simultaneously output the scan signal, and control the first source driver circuit and the second source driver The circuits output respective data signals;
控制第一移位寄存器中的第二个移位寄存器单元和第二移位寄存器中的 第 m-1个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和 第二源极驱动电路输出各自的数据信号； Control the second shift register unit in the first shift register and the m-1th shift register unit in the second shift register to simultaneously output the scan signal, control the first source driver circuit and the second source The pole drive circuit outputs respective data signals;
控制第一移位寄存器中的第三个移位寄存器单元和第二移位寄存器中的 第 m-2个移位寄存器单元同时输出所述扫描信号， 控制第一源极驱动电路和 第二源极驱动电路输出各自的数据信号； 以此类推， 直到控制第一移位寄存器中的第 m个移位寄存器单元和第二 移位寄存器中的第一个移位寄存器单元同时输出所述扫描信号， 控制第一源 极驱动电路和第二源极驱动电路输出各自的数据信号。 Control the third shift register unit in the first shift register and the m-2th shift register unit in the second shift register to simultaneously output the scan signal, control the first source driver circuit and the second source The pole drive circuit outputs respective data signals; By analogy, until the mth shift register unit in the first shift register and the first shift register unit in the second shift register are controlled to simultaneously output the scan signal, the first source driving circuit and The second source driving circuit outputs respective data signals.
9、根据权利要求 6所述的驱动方法， 其特征在于， 所述栅极驱动电路由 m个移位寄存器单元组成， 所述 m个移位寄存器单元分别与第一显示区域的 第一 m条栅极扫描线——对应相连，并且所述 m个移位寄存器单元还分别与 第二显示区域的第二 m条栅极扫描线——对应相连， 其中， 所述 m个移位寄 存器单元级联； 在显示一帧图像的过程中， 所述驱动方法具体为： 9. The driving method according to claim 6, characterized in that the gate driving circuit is composed of m shift register units, and the m shift register units are respectively connected to the first m lines of the first display area. The gate scan lines are connected correspondingly, and the m shift register units are also respectively connected to the second m gate scan lines of the second display area, where, the m shift register units are In the process of displaying one frame of image, the driving method is specifically:
控制第一个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号； Controlling the first shift register unit to output scanning signals to the two gate scanning lines connected thereto, and controlling the first source driving circuit and the second source driving circuit to output respective data signals;
控制第二个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号； Controlling the second shift register unit to output scanning signals to the two gate scanning lines connected thereto, and controlling the first source driving circuit and the second source driving circuit to output respective data signals;
控制第三个移位寄存器单元向与之相连的两条栅极扫描线输出扫描信 号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数据信号； Controlling the third shift register unit to output scanning signals to the two gate scanning lines connected thereto, and controlling the first source driving circuit and the second source driving circuit to output respective data signals;
以此类推， 直到控制第 m个移位寄存器单元向与之相连的两条栅极扫描 线输出扫描信号， 控制第一源极驱动电路和第二源极驱动电路输出各自的数 据信号。 By analogy, the mth shift register unit is controlled to output scanning signals to the two gate scanning lines connected thereto, and the first source driving circuit and the second source driving circuit are controlled to output respective data signals.
10、 根据权利要求 6所述的方法， 其特征在于， 所述栅极驱动电路为栅 极驱动芯片， 所述栅极驱动芯片与所述第一显示区域的第一 m条栅极扫描线 相连； 并且， 所述第一显示区域的第一 m条栅极扫描线和第二显示区域的第 二 m条栅极扫描线——对应相连； 在显示一帧图像的过程中， 所述驱动方法 具体为： 10. The method of claim 6, wherein the gate driving circuit is a gate driving chip, and the gate driving chip is connected to the first m gate scanning lines of the first display area. ; And, the first m gate scanning lines of the first display area and the second m gate scanning lines of the second display area are connected correspondingly; In the process of displaying a frame of image, the driving method Specifically:
控制所述栅极驱动芯片逐行向第一显示区域的栅极扫描线和第二显示区 域的栅极扫描线输出扫描信号， 同时控制第一源极驱动电路和第二源极驱动 电路输出各自的数据信号。 The gate driver chip is controlled to output scanning signals row by row to the gate scanning lines of the first display area and the gate scanning lines of the second display area, and at the same time, the first source driving circuit and the second source driving circuit are controlled to output respective data signal.
11、 一种显示装置， 其特征在于， 包括权利要求 1-5任一所述的驱动电 路。 11. A display device, characterized by comprising the drive circuit described in any one of claims 1-5.
PCT/CN2013/074491 2013-03-26 2013-04-22 Drive circuit, drive method and display device WO2014153797A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310098987.0A CN103208250B (en) 2013-03-26 2013-03-26 A kind of driving circuit, driving method and display device
CN201310098987.0 2013-03-26

Publications (1)

Publication Number Publication Date
WO2014153797A1 true WO2014153797A1 (en) 2014-10-02

Family

ID=48755462

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/074491 WO2014153797A1 (en) 2013-03-26 2013-04-22 Drive circuit, drive method and display device

Country Status (2)

Country Link
CN (1) CN103208250B (en)
WO (1) WO2014153797A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10235952B2 (en) 2016-07-18 2019-03-19 Samsung Display Co., Ltd. Display panel having self-refresh capability

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347044B (en) * 2013-08-06 2017-07-21 瀚宇彩晶股份有限公司 Gate driving circuit
KR102089326B1 (en) 2013-10-01 2020-03-17 엘지디스플레이 주식회사 Display Device
CN104575347A (en) * 2013-10-10 2015-04-29 冠捷投资有限公司 Flat panel displayer and drive circuit thereof
CN103971644A (en) * 2014-05-22 2014-08-06 张家港亚楠汽车电器有限公司 Method for scanning LED displayer
CN104658466B (en) * 2015-01-27 2017-05-10 京东方科技集团股份有限公司 GOA circuit and driving method thereof, as well as display panel and display device
CN104809998A (en) * 2015-05-11 2015-07-29 武汉华星光电技术有限公司 Array substrate and display device
CN105161059B (en) * 2015-06-30 2018-09-07 京东方科技集团股份有限公司 Display drive method, display panel and preparation method thereof, display device
CN105976759B (en) 2016-07-29 2019-09-06 京东方科技集团股份有限公司 Driving circuit, display panel, display equipment and driving method
CN107293267B (en) * 2017-07-19 2020-05-05 深圳市华星光电半导体显示技术有限公司 Display panel and control method of display panel grid signals
CN107817635A (en) 2017-10-27 2018-03-20 北京京东方显示技术有限公司 A kind of array base palte and its driving method, display device
CN107749276B (en) * 2017-11-28 2020-06-23 上海天马有机发光显示技术有限公司 Organic light-emitting display panel and organic light-emitting display device
WO2019127256A1 (en) * 2017-12-28 2019-07-04 深圳市柔宇科技有限公司 Array substrate, display panel and terminal
CN108877634B (en) * 2018-08-08 2021-06-15 武汉天马微电子有限公司 Synchronous controller, display device and control method thereof
CN109346008A (en) * 2018-12-17 2019-02-15 武汉华星光电半导体显示技术有限公司 Organic LED display device
CN109584770B (en) * 2018-12-17 2022-02-08 武汉天马微电子有限公司 Display panel and display device
CN109686296B (en) * 2019-03-05 2022-05-20 合肥鑫晟光电科技有限公司 Shift register module, driving method and grid driving circuit
CN109859694B (en) * 2019-03-19 2021-04-20 京东方科技集团股份有限公司 Display panel, driving control method and driving control circuit thereof, and display device
CN110459576B (en) * 2019-08-21 2023-04-11 京东方科技集团股份有限公司 Display panel, display equipment and driving method
CN111028762B (en) * 2019-12-31 2022-09-30 厦门天马微电子有限公司 Display device
CN113785265A (en) 2020-02-27 2021-12-10 京东方科技集团股份有限公司 Display panel and display device
CN111477185A (en) * 2020-04-30 2020-07-31 上海中航光电子有限公司 Array substrate, display panel and display device
CN113870757B (en) * 2020-06-30 2023-07-04 京东方科技集团股份有限公司 Driving method, driving circuit and display device of display panel
CN112233604A (en) 2020-10-15 2021-01-15 Tcl华星光电技术有限公司 Display panel and display device
CN114420025A (en) * 2020-10-28 2022-04-29 北京京东方显示技术有限公司 Display panel driving method, driving device and display device
CN112735341A (en) * 2020-12-30 2021-04-30 Tcl华星光电技术有限公司 Pixel driving circuit and display device
CN112837628A (en) * 2021-01-21 2021-05-25 维沃移动通信有限公司 Display device and electronic apparatus
CN112967694A (en) * 2021-03-01 2021-06-15 惠科股份有限公司 Data driver, driving method thereof, display panel and display device
CN113362779A (en) * 2021-06-28 2021-09-07 武汉华星光电技术有限公司 Display panel and display device
CN115708151A (en) * 2021-08-18 2023-02-21 北京京东方显示技术有限公司 Display device and driving method thereof
CN114333677A (en) * 2021-12-31 2022-04-12 昆山国显光电有限公司 Display panel, driving method and display device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000098334A (en) * 1998-09-28 2000-04-07 Alps Electric Co Ltd Liquid crystal display device
CN1450516A (en) * 2002-04-04 2003-10-22 Lg电子株式会社 Dual scan method of matrix display panel
CN1617210A (en) * 2003-11-13 2005-05-18 东北先锋电子股份有限公司 Self light emission display device
CN1719501A (en) * 2004-07-08 2006-01-11 东北先锋电子股份有限公司 Self light emitting display panel and drive control method therefor
CN1728204A (en) * 2004-07-30 2006-02-01 冲电气工业株式会社 Scanning method of display panel and a display unit
CN1734539A (en) * 2004-08-02 2006-02-15 冲电气工业株式会社 Dual scan display panel driver
CN101017644A (en) * 2006-02-10 2007-08-15 奇晶光电股份有限公司 Driving method of double-scanning display and its related display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000098334A (en) * 1998-09-28 2000-04-07 Alps Electric Co Ltd Liquid crystal display device
CN1450516A (en) * 2002-04-04 2003-10-22 Lg电子株式会社 Dual scan method of matrix display panel
CN1617210A (en) * 2003-11-13 2005-05-18 东北先锋电子股份有限公司 Self light emission display device
CN1719501A (en) * 2004-07-08 2006-01-11 东北先锋电子股份有限公司 Self light emitting display panel and drive control method therefor
CN1728204A (en) * 2004-07-30 2006-02-01 冲电气工业株式会社 Scanning method of display panel and a display unit
CN1734539A (en) * 2004-08-02 2006-02-15 冲电气工业株式会社 Dual scan display panel driver
CN101017644A (en) * 2006-02-10 2007-08-15 奇晶光电股份有限公司 Driving method of double-scanning display and its related display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10235952B2 (en) 2016-07-18 2019-03-19 Samsung Display Co., Ltd. Display panel having self-refresh capability

Also Published As

Publication number Publication date
CN103208250A (en) 2013-07-17
CN103208250B (en) 2015-08-05

Similar Documents

Publication Publication Date Title
WO2014153797A1 (en) Drive circuit, drive method and display device
US7508479B2 (en) Liquid crystal display
JP3622592B2 (en) Liquid crystal display
KR101862347B1 (en) Display and display set having the same
WO2016188257A1 (en) Array substrate, display panel and display device
TWI494912B (en) Liquid crystal display device including inspection circuit and inspection method thereof
KR20050000105A (en) Liquid crystal display and driving method thereof
JP2006267999A (en) Drive circuit chip and display device
CN107633827B (en) Display panel driving method and display device
JP2016539365A (en) Liquid crystal panel driving circuit, driving method, and liquid crystal display device
WO2019227947A1 (en) Array substrate, display panel, and display device
WO2014000384A1 (en) Display panel as well as drive method and display device thereof
US20070146269A1 (en) Image display device and image display method
US20210065645A1 (en) Row drive circuit of array substrate and display device
CN111883074A (en) Grid driving circuit, display module and display device
US20150269889A1 (en) Organic light-emitting diode display device and driving method thereof
WO2019007085A1 (en) Scan drive circuit and drive method, array substrate and display apparatus
CN105527737A (en) Liquid crystal display panel and driving method thereof
KR20150005259A (en) Display panel and display apparatus having the same
CN113870762A (en) Display panel, driving method thereof and display device
JP2002297109A (en) Liquid crystal display device and driving circuit therefor
WO2014110769A1 (en) Gate driver and liquid crystal display
JP2001051643A (en) Display device and driving method
JP2007334283A (en) Liquid crystal display device and its driving method
TWM327032U (en) On-glass single chip liquid crystal display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13880584

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 21/01/2016)

122 Ep: pct application non-entry in european phase

Ref document number: 13880584

Country of ref document: EP

Kind code of ref document: A1