WO2014153792A1 - 一种液晶面板的驱动电路、液晶面板和一种驱动方法 - Google Patents
一种液晶面板的驱动电路、液晶面板和一种驱动方法 Download PDFInfo
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- WO2014153792A1 WO2014153792A1 PCT/CN2013/073782 CN2013073782W WO2014153792A1 WO 2014153792 A1 WO2014153792 A1 WO 2014153792A1 CN 2013073782 W CN2013073782 W CN 2013073782W WO 2014153792 A1 WO2014153792 A1 WO 2014153792A1
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- liquid crystal
- crystal panel
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims description 13
- 238000012544 monitoring process Methods 0.000 claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims description 27
- 230000003111 delayed effect Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
Definitions
- the present invention relates to the field of liquid crystal panels, and more particularly to a driving circuit for a liquid crystal panel, a liquid crystal panel, and a driving method.
- the signal output from the data chip has a trace before reaching the data line.
- the difference between the length of the traces at the two ends of the liquid crystal panel and the middle trace becomes larger and larger, and further The impedance difference is also getting larger and larger, and the impedance difference affects the degree of distortion of the data signal.
- it is implemented by using a serpentine trace. As shown in Figure 1, the gold finger of the data drive module of the COF (chip on Aim) package is pressed to The lead of the glass is then connected to the pixels of the liquid crystal panel through a winding.
- the liquid crystal panel is moving toward the narrow frame, so the winding space is gradually reduced.
- such compensation cannot reduce the impedance difference caused by the difference in distance, thus causing the display signal of the output channel at both ends of the data chip to reach the data line of the liquid crystal panel.
- the technical problem to be solved by the present invention is to provide a novel driving circuit, a liquid crystal panel and a driving method for a liquid crystal panel which can improve display signal delay, particularly for a multi-output channel data driving module.
- a driving circuit for a liquid crystal panel includes a plurality of data lines and leads connected to the data lines, the driving circuit includes a monitoring module and a data driving module, and the data driving module includes a lead coupled to the liquid crystal panel a data latch unit; the monitoring module outputs a timing signal to control the The data latch unit outputs a display signal to the data line, the driving circuit of the liquid crystal panel further includes a delay unit corresponding to the data line, the timing signal is coupled to the data latch unit through the delay unit; After reaching the predetermined delay trigger time, the control data latch unit outputs a display signal to the corresponding data line; the delay trigger time of the longer lead coupled delay unit is less than the delay trigger time of the shorter lead coupled delay unit.
- the data line of the liquid crystal panel is coupled with pixels, and the delay unit controls that the display signals output by each data latch unit reach the same row of pixels for the same time. This completely solves the problem of displaying signal delay and achieving the best display.
- the delay unit includes a plurality of cascaded D flip-flops, an output of each D flip-flop is coupled to a data latch unit and coupled to an input of a next-stage D flip-flop; A counter corresponding to the D flip-flop is further included; a trigger end of the D flip-flop is coupled to a unified clock signal through the counter.
- the timing signal is high, the D flip-flop generates a timing signal step by step with the frequency of the clock signal.
- the pulse signal at the trigger end of the D flip-flop can be generated by the counter clock signal. Therefore, by changing the counter, different pulse signals can be generated, thereby generating timing signals with different delays.
- the D flip-flop can realize the signal delay output, and has 4 good follow-up characteristics, and the cost is low, which is beneficial to reduce the cost; the delay output time of the D flip-flop can be flexibly set by the counter.
- the data latch unit includes a data buffer, a digital-to-analog conversion module coupled to the data buffer, and the digital-to-analog conversion module converts the display signal into an analog signal and outputs the data to a corresponding data line.
- This is a specific data latch unit structure.
- the display signal is transmitted from the data register to the digital-to-analog conversion module; when the timing signal is at a low level, the digital-to-analog conversion mode is converted.
- the display signal is output to the corresponding data line.
- the data line of the liquid crystal panel is coupled with pixels, and the delay unit controls that the display signals output by the data latch unit reach the same row of pixels for the same time;
- the delay unit includes a plurality of cascaded D flip-flops, each The outputs of the D flip-flops are coupled to a data latch unit and coupled to the lower An output of the first stage D flip-flop;
- the delay unit further includes a counter corresponding to the D flip-flop;
- the trigger end of the D flip-flop is coupled to the unified clock signal through the counter;
- the data The latch unit includes a data buffer, a digital-to-analog conversion module coupled to the data register, and the digital-to-analog conversion module converts the display signal into an analog signal and outputs the data to a corresponding data line;
- the timing signal is high When the level is low, the display signal is transmitted from the data buffer to the digital-to-analog conversion module; when the timing signal is low, the digital-to-analog conversion mode outputs the converted
- a liquid crystal panel device comprising a driving circuit of a liquid crystal panel according to the present invention.
- a driving method of a liquid crystal panel driving circuit includes a plurality of data lines, a data driving module coupled to the data lines, and a monitoring module coupled to the data driving module;
- the data driving module includes data corresponding to the data lines a latch unit and a delay unit;
- the driving method includes the steps of:
- the timing signal of the monitoring module is coupled to the data latch unit through the delay unit;
- the delay triggering time of the longer lead coupled delay unit is less than the delay triggering time of the shorter lead coupled delay unit; after the delay unit reaches a predetermined delay trigger time, the timing signal is converted to a low level The status is sent to the data latch unit, and the control data latch unit outputs a display signal to the corresponding data line.
- the step B includes: controlling the delay triggering time of the delay unit, so that the display signals output by each data latch unit reach the pixels of the same row of liquid crystal panels for the same time. This completely solves the problem of display signal delay and achieves the best display.
- the step B includes: using a D flip-flop to control the delay time.
- D flip-flop can achieve signal delay output, and has good follow-up characteristics, and low cost, which is beneficial to reduce costs.
- the data of each channel of the general data driving module is simultaneously output, that is, the display signal of each data latch unit is simultaneously loaded into the data line.
- the existing data driving module is generally controlled by a timing signal, and the action logic is: timing signal At its rising edge, the display signal is latched to the data latch unit, and at its falling edge, the display signal is pushed into the liquid crystal panel.
- the present invention employs a delay unit to control the time when the falling edge of the timing signal arrives at each data latch unit, and converts the timing signal to a low state after the delay unit reaches a predetermined delay trigger time. And sent to the data latch unit, the control data latch unit outputs the display signal to the corresponding lead, and then reaches the data line connected to the lead; the delay lead triggering time of the longer lead coupled delay unit is less than the shorter lead coupling Delay delay time of the delay unit, so that the time difference of the display signal reaching the same row of pixels can be reduced, thereby improving the display signal delay and improving the display quality; in addition, the present invention has no relationship with the distance, as long as the delay time of different delay units is controlled. , can achieve the problem of improving the display signal delay, suitable for multi-output channel data drive module.
- FIG. 1 is a schematic diagram of a conventional liquid crystal panel driving circuit
- FIG. 2 is a waveform diagram of an output of a conventional data driving module
- FIG. 3 is a schematic view showing the principle of a driving circuit of the liquid crystal panel of the present invention.
- FIG. 5 is a schematic diagram of timing signal delay in the first embodiment of the present invention.
- FIG. 6 is a schematic diagram showing waveforms of a timing signal and a sub-timing signal in Embodiment 1 of the present invention.
- FIG. 7 is a schematic diagram showing waveforms of an output of a data driving module according to Embodiment 1 of the present invention.
- FIG. 8 is a schematic circuit diagram of a delay unit according to Embodiment 1 of the present invention.
- Embodiment 9 is a schematic flow chart of a method according to Embodiment 2 of the present invention.
- the present invention discloses a driving circuit for a liquid crystal panel.
- the liquid crystal panel includes a plurality of data lines 31, and leads 33 connected to the data lines.
- the driving circuit includes a monitoring module 10 and a data driving module 20, and the data driving module 20 A data latch unit 21 corresponding to the lead 33 of the liquid crystal panel 30 is included;
- the control module 10 outputs a timing signal to control the data latch unit 21 to output a display signal to the data line.
- the driving circuit of the liquid crystal panel further includes a delay unit 24 corresponding to the data line, and the timing signal is coupled to the data latch unit 21 through the delay unit 24; After the unit 24 reaches the predetermined delay trigger time, the control data latch unit 21 outputs a display signal to the corresponding data line 31;
- the delay lead time of the longer lead 33 coupled delay unit 24 is less than the delay trigger time of the shorter lead 33 coupled delay unit 24.
- the data of each channel of the general data driving module is simultaneously output, that is, the display signal of each data latching unit is simultaneously loaded into the data line, as shown in FIG. 2 .
- the data driving module has 2n output channels, n is the channel closest to the data column, so the impedance of the lead to the data column is the smallest, and the impedance of the left and right channels is symmetrically distributed, increasing sequentially, and the signal reaches the panel data line.
- the degree of delay is also gradually increased, and the charging time of the data column corresponding to the panel is gradually reduced.
- the existing data driving module is generally controlled by a timing signal, and the action logic is: the timing signal latches the display signal to the data latch unit at its rising edge, and pushes the display signal into the liquid crystal panel at the falling edge thereof. .
- the present invention employs a delay unit to control the time at which the falling edge of the timing signal arrives at each data latch unit, and when the delay unit reaches a predetermined delay trigger time, the timing signal is converted to a low level ( The logic 0) state is sent to the data latch unit, and the control data latch unit outputs a display signal to the corresponding lead to reach the data line connected to the lead; the delay lead triggering time of the longer lead coupled delay unit is less than the shorter
- the delay triggering time of the lead-coupled delay unit can reduce the time difference of the display signal reaching the same row of pixels, thereby improving the display signal delay and improving the display quality.
- the present invention has no relationship with the distance, as long as different delays are controlled. The delay time of the unit can achieve the
- the liquid crystal panel device of the present invention includes a driving circuit of the liquid crystal panel 30.
- the liquid crystal panel 30 includes a plurality of data lines 31, a data driving module 20 coupled to the data lines 31, and a monitoring module 10 coupled to the data driving module 20;
- the data driving module 20 includes a data latch unit coupled to the leads 33. 21 and delay unit 24;
- monitoring module 10 outputs timing signal control data latch unit 21 outputs display signal to data line 31, timing signal is coupled to data latch unit 21 via delay unit 24; delay unit 24 reaches a predetermined delay trigger time
- the control data latch unit 21 outputs a display signal to the corresponding data line 31; the delay lead time of the delay unit 24 coupled by the longer lead 33 is less than the delay trigger time of the delay unit 24 coupled by the shorter lead 33.
- the data latch unit 21 includes a data buffer 22, and a digital-to-analog conversion module 23 coupled to the data register 22, and the digital-to-analog conversion module 23 converts the display signal into an analog signal and outputs it to the corresponding data line 31;
- the logic level is high (logic 1 )
- the display signal is transmitted from the data register 22 to the digital-to-analog conversion module 23;
- the timing signal is low, the digital-to-analog conversion mode outputs the converted display signal to the corresponding data line 31.
- the data line 31 of the liquid crystal panel 30 is coupled with the pixels 32.
- the delay unit 24 controls the display signals output by the data latch unit 21 to reach the same row of pixels 32 for the same time; this can completely solve the problem of display signal delay and achieve the best display effect. .
- the data of each channel of the general data driving module is simultaneously output, that is, the display signal of each data latch unit is simultaneously loaded into the data line, as shown in FIG. 2 .
- the data driving module has 2n output channels, n is the channel closest to the data column, so the impedance of the lead to the data column is the smallest, and the impedance of the left and right channels is symmetrically distributed, increasing sequentially, and the signal reaches the panel data line.
- the degree of delay is also gradually increased, and the charging time of the data column corresponding to the panel is gradually reduced.
- the present invention controls the data chip output channel separately.
- the data driving module generates the sub-timing signals TP1 to N corresponding to each output channel according to the timing signal TP transmitted from the monitoring module, and the falling edge of the timing signal TP is sequentially from the two sides of the liquid crystal panel to the middle.
- the delay that is, the delay trigger time of the delay unit is incremented.
- the output of the display signal of the corresponding area is also delayed accordingly ( Figure 7).
- the charging time of the pixels in each area of the liquid crystal panel can be made uniform by adjusting the delay of the falling edge of the corresponding sub-timing signal, thereby solving the problem of inconsistent signal delay caused by the impedance inconsistency.
- the delay unit includes a plurality of cascaded D flip-flops 25, the output of each D flip-flop 25 being coupled to a data latch unit and coupled to the output of the next stage D flip-flop 25; Delay The delay unit further includes a counter 26 corresponding to the D flip-flop 25; the trigger terminal of the D flip-flop 25 is coupled to the unified clock signal elk through the counter 26; when the timing signal is high, the D flip-flop will follow the clock pulse signal The frequency of elk generates timing signals step by step.
- the pulse signals CK1 ⁇ N of the trigger end of the D flip-flop can be generated by the clock pulse signal elk through the counters 1 ⁇ N.
- the D flip-flop can realize signal delay output, has good follow-up characteristics, and has low cost, which is beneficial to reduce cost; the delay output time of the D flip-flop can be flexibly set by the counter.
- the present invention also discloses a driving method of a liquid crystal panel driving circuit of the present invention, which comprises the steps of:
- the timing signal of the monitoring module is coupled to the data latch unit through the delay unit;
- the delay triggering time of the longer lead coupled delay unit is less than the delay triggering time of the shorter lead coupled delay unit; after the delay unit reaches a predetermined delay trigger time, the timing signal is converted to a low level The status is sent to the data latch unit, and the control data latch unit outputs a display signal to the corresponding data line.
- step B includes: controlling the delay trigger time of the delay unit, so that the display signals output by each data latch unit reach the pixels of the same row of liquid crystal panels for the same time.
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Abstract
液晶面板(30)包括多条数据线(31),和与数据线(31)连接的引线(33),液晶面板(30)的驱动电路包括监控模块(10)和数据驱动模块(20),数据驱动模块(20)包括与液晶面板(30)的引线(33)耦合的数据锁存单元(21);监控模块(10)输出时序信号控制数据锁存单元(21)输出显示信号到数据线(31),液晶面板(30)的驱动电路还包括与数据线(31)对应的延迟单元(24),时序信号通过延迟单元(24)耦合到数据锁存单元(21);延迟单元(24)到达预定的延迟触发时间后,控制数据锁存单元(21)输出显示信号到相应的数据线(31);较长的引线(33)耦合的延迟单元(24)的延迟触发时间小于较短的引线(33)耦合的延迟单元(24)的延迟触发时间。通过控制不同延迟单元(24)的延迟时间,达到改善显示信号延迟的效果。
Description
一种液晶面板的驱动电路、 液晶面板和一种驱动方法
【技术领域】
本发明涉及液晶面板领域, 更具体的说, 涉及一种液晶面板的驱动电路、 液晶面板和一种驱动方法。
【背景技术】
在液晶面板中, 从数据芯片输出的信号在到达数据线前有一段走线, 随着 数据芯片输出通道数的增加, 液晶面板两端的走线与中间走线的长度差异越来 越大, 进而阻抗差异也越来越大, 阻抗差异会影响着数据信号的失真程度。 通 常, 为了使得达到每一个像素时走线的阻抗基本一致, 会采用再用一段蛇形走 线来实现, 如图一, COF ( chip on Aim )封装的数据驱动模块的金手指会压合 到玻璃的引线上, 然后经过一段绕线再连接到液晶面板的像素。 但是目前液晶 面板正朝着窄边框方向发展, 故绕线空间逐渐缩小。 而且随着数据驱动模块的 芯片输出通道数越来越多, 这样的补偿是没法减少距离差异导致的阻抗差异, 这样就造成了数据芯片两端的输出通道的显示信号到达液晶面板的数据线时比 数据芯片中间的输出通道的显示信号到达液晶面板数据线时还是有延迟。 因此, 寻求别的方式来解决补偿问题已迫在眉睫。
【发明内容】
本发明所要解决的技术问题是提供一种新的可改善显示信号延迟, 特别适 用于多输出通道数据驱动模块的液晶面板的驱动电路、 液晶面板和一种驱动方 法。
本发明的目的是通过以下技术方案来实现的:
一种液晶面板的驱动电路, 所述液晶面板包括多条数据线、 与数据线连接 的引线, 所述驱动电路包括监控模块和数据驱动模块, 所述数据驱动模块包括 与液晶面板的引线耦合的数据锁存单元; 所述监控模块输出时序信号控制所述
数据锁存单元输出显示信号到数据线, 所述液晶面板的驱动电路还包括与数据 线对应的延迟单元, 所述时序信号通过所述延迟单元耦合到所述数据锁存单元; 所述延迟单元到达预定的延迟触发时间后, 控制数据锁存单元输出显示信 号到相应的数据线; 所述较长的引线耦合的延迟单元的延迟触发时间小于较短 的引线耦合的延迟单元的延迟触发时间。
进一步的, 所述液晶面板的数据线耦合有像素, 所述延迟单元控制每个数 据锁存单元输出的显示信号抵达同一行像素的时间相等。 这样可以彻底解决显 示信号延迟的问题, 达到最佳的显示效果。
进一步的, 所述延迟单元包括多个级联的 D触发器, 每个 D触发器的输出 端耦合到一个数据锁存单元, 并耦合到下一级 D触发器的输入端; 所述延迟单 元还包括与所述 D触发器——对应的计数器; 所述 D触发器的触发端通过所述 计数器耦合到统一的时钟脉沖信号。 当时序信号为高电平时, D 触发器会随着 时钟信号的频率逐级产生时序信号。 其中 D触发器触发端的脉沖信号可以用时 钟信号通过计数器产生, 因此, 通过改变计数器就可以产生不同的脉沖信号, 进而产生不同延迟的时序信号。 D 触发器能实现信号延迟输出, 并有 4艮好的跟 随特性, 且成本低廉, 有利于降成本; 通过计数器可以灵活设置 D触发器的延 迟输出时间。
进一步的, 所述数据锁存单元包括数据暂存器, 与数据暂存器耦合的数模 转换模块, 所述数模转换模块将所述显示信号转化成模拟信号后输出到相应的 数据线。 此为一种具体的数据锁存单元结构。
进一步的, 所述时序信号为高电平时, 所述显示信号从所述数据暂存器传 送到所述数模转换模块; 所述时序信号为低电平时, 所述数模转换模将转换后 的显示信号输出到相应的数据线。 此为一种采用低电平触发控制的技术方案。
进一步的, 所述液晶面板的数据线耦合有像素, 所述延迟单元控制数据锁 存单元输出的显示信号抵达同一行像素的时间相等; 所述延迟单元包括多个级 联的 D触发器, 每个 D触发器的输出端耦合到一个数据锁存单元, 并耦合到下
一级 D触发器的输出端;所述延迟单元还包括与所述 D触发器——对应的计数 器; 所述 D触发器的触发端通过所述计数器耦合到统一的时钟脉沖信号; 所述 数据锁存单元包括数据暂存器, 与数据暂存器耦合的数模转换模块, 所述数模 转换模块将所述显示信号转化成模拟信号后输出到相应的数据线; 所述时序信 号为高电平时, 所述显示信号从所述数据暂存器传送到所述数模转换模块; 所 述时序信号为低电平时, 所述数模转换模将转换后的显示信号输出到相应的数 据线。 此为一种具体的液晶面板驱动电路结构。
一种液晶面板装置, 包括本发明所述的液晶面板的驱动电路。
一种液晶面板驱动电路的驱动方法, 所述液晶面板包括多条数据线, 与数 据线耦合的数据驱动模块, 与数据驱动模块耦合的监控模块; 所述数据驱动模 块包括与数据线对应的数据锁存单元和延迟单元; 所述驱动方法包括步骤:
A: 监控模块的时序信号通过延迟单元耦合到数据锁存单元;
B: 所述较长的引线耦合的延迟单元的延迟触发时间小于较短的引线耦合的 延迟单元的延迟触发时间; 所述延迟单元到达预定的延迟触发时间后, 将时序 信号转换成低电平状态并发送到数据锁存单元, 控制数据锁存单元输出显示信 号到相应的数据线。
进一步的, 所述步骤 B 中包括: 控制延迟单元的延迟触发时间, 使得每个 数据锁存单元输出的显示信号抵达同一行液晶面板的像素的时间相等。 这样可 以彻底解决显示信号延迟的问题, 达到最佳的显示效果。
进一步的, 所述步骤 B中包括: 采用 D触发器控制延迟时间。 此为一种具 体延迟单元电路结构, D 触发器能实现信号延迟输出, 并有很好的跟随特性, 且成本低廉, 有利于降成本。
经研究, 一般的数据驱动模块各通道的数据是同时输出的, 即每个数据锁 存单元的显示信号是同时加载到数据线中。 随着引线长度的增长, 其信号到达 面板数据线时的延迟程度也逐渐增大, 面板对应的数据列的充电时间也逐渐减 少。 现有的数据驱动模块一般通过时序信号来控制, 其动作逻辑是: 时序信号
在其上升沿时会将显示信号锁存至数据锁存单元, 在其下降沿时再将显示信号 推入液晶面板。 考虑到时序信号的这种特性, 本发明采用延迟单元来控制时序 信号下降沿抵达每个数据锁存单元的时间, 当延迟单元到达预定的延迟触发时 间后, 将时序信号转换成低电平状态并发送到数据锁存单元, 控制数据锁存单 元输出显示信号到相应的引线, 进而抵达与该引线连接的数据线; 较长的引线 耦合的延迟单元的延迟触发时间小于较短的引线耦合的延迟单元的延迟触发时 间, 这样显示信号抵达同一行像素的时间差异就能减小, 达到改善显示信号延 迟, 提高显示品质; 另外, 本发明跟距离没有关系, 只要控制好不同延迟单元 的延迟时间, 都能达到改善显示信号延迟的问题, 适用于多输出通道数据驱动 模块。
【附图说明】
图 1是现有的一种液晶面板驱动电路示意图;
图 2是现有的数据驱动模块输出的波形示意图;
图 3是本发明液晶面板的驱动电路的原理示意图;
图 4是本发明实施例一的原理示意图;
图 5是本发明实施例一中时序信号延迟示意图;
图 6是本发明实施例一中时序信号和子时序信号的波形示意图;
图 7是本发明实施例一的数据驱动模块输出的波形示意图;
图 8是本发明实施例一的延迟单元电路示意图;
图 9是本发明实施例二的方法流程示意图。
【具体实施方式】
如图 3 所示, 本发明公开一种液晶面板的驱动电路, 液晶面板包括多条数 据线 31 , 与数据线连接的引线 33 , 驱动电路包括监控模块 10和数据驱动模块 20, 数据驱动模块 20包括与液晶面板 30的引线 33对应的数据锁存单元 21 ; 监
控模块 10输出时序信号控制数据锁存单元 21输出显示信号到数据线, 液晶面 板的驱动电路还包括与数据线对应的延迟单元 24,时序信号通过延迟单元 24耦 合到数据锁存单元 21 ; 延迟单元 24到达预定的延迟触发时间后, 控制数据锁存 单元 21输出显示信号到相应的数据线 31 ;
较长的引线 33耦合的延迟单元 24的延迟触发时间小于较短的引线 33耦合 的延迟单元 24的延迟触发时间。
经研究, 一般的数据驱动模块各通道的数据是同时输出的, 即每个数据锁 存单元的显示信号是同时加载到数据线中, 如图 2所示。 假设数据驱动模块有 2n个输出通道, n为离数据列最近的通道, 因此其到数据列的引线的阻抗最小, 左右通道的阻抗呈对称分布, 逐次增大, 其信号到达面板数据线时的延迟程度 也逐渐增大, 面板对应的数据列的充电时间也逐渐减少。 现有的数据驱动模块 一般通过时序信号来控制, 其动作逻辑是: 时序信号在其上升沿时会将显示信 号锁存至数据锁存单元, 在其下降沿时再将显示信号推入液晶面板。 考虑到时 序信号的这种特性, 本发明采用延迟单元来控制时序信号下降沿抵达每个数据 锁存单元的时间, 当延迟单元到达预定的延迟触发时间后, 将时序信号转换成 低电平( logic 0 )状态并发送到数据锁存单元, 控制数据锁存单元输出显示信号 到相应的引线, 进而抵达与该引线连接的数据线; 较长的引线耦合的延迟单元 的延迟触发时间小于较短的引线耦合的延迟单元的延迟触发时间, 这样显示信 号抵达同一行像素的时间差异就能减小, 达到改善显示信号延迟, 提高显示品 质; 另外, 本发明跟距离没有关系, 只要控制好不同延迟单元的延迟时间, 都 能达到改善显示信号延迟的问题, 适用于多输出通道数据驱动模块。
下面结合附图和较佳的实施例对本发明作进一步说明。
实施例一
如图 4所示, 本发明的液晶面板装置包括液晶面板 30的驱动电路。 液晶面 板 30包括多条数据线 31 , 与数据线 31耦合的数据驱动模块 20, 与数据驱动模 块 20耦合的监控模块 10;数据驱动模块 20包括与引线 33耦合的数据锁存单元
21和延迟单元 24; 监控模块 10输出时序信号控制数据锁存单元 21输出显示信 号到数据线 31 , 时序信号通过延迟单元 24耦合到数据锁存单元 21; 延迟单元 24到达预定的延迟触发时间后,控制数据锁存单元 21输出显示信号到相应的数 据线 31; 较长的引线 33耦合的延迟单元 24的延迟触发时间小于较短的引线 33 耦合的延迟单元 24的延迟触发时间。 数据锁存单元 21包括数据暂存器 22, 与 数据暂存器 22耦合的数模转换模块 23 , 数模转换模块 23将显示信号转化成模 拟信号后输出到相应的数据线 31; 时序信号为高电平 (logic 1 ) 时, 显示信号 从数据暂存器 22传送到数模转换模块 23; 时序信号为低电平时, 数模转换模将 转换后的显示信号输出到相应的数据线 31。
液晶面板 30的数据线 31耦合有像素 32, 延迟单元 24控制数据锁存单元 21输出的显示信号抵达同一行像素 32的时间相等;这样可以彻底解决显示信号 延迟的问题, 达到最佳的显示效果。
一般的数据驱动模块各通道的数据是同时输出的, 即每个数据锁存单元的 显示信号是同时加载到数据线中, 如图 2所示。 假设数据驱动模块有 2n个输出 通道, n为离数据列最近的通道, 因此其到数据列的引线的阻抗最小, 左右通道 的阻抗呈对称分布, 逐次增大, 其信号到达面板数据线时的延迟程度也逐渐增 大, 面板对应的数据列的充电时间也逐渐减少。 本发明将数据芯片输出通道单 独控制。
如图 5、 6所示, 数据驱动模块根据监控模块传输过来的时序信号 TP, 产 生跟每个输出通道对应的子时序信号 TP1 ~ N, 时序信号 TP的下降沿从液晶面 板的两边至中间依次延迟, 即延迟单元的延迟触发时间递增。 相应区域的显示 信号的输出也相应得到延迟(如图 7 )。 最后就可以通过调节相应子时序信号下 降沿的延迟来使液晶面板各区域的像素的充电时间趋于一致, 解决了因阻抗不 一致而引起的信号延迟不一致的问题。
如图 8所示, 延迟单元包括多个级联的 D触发器 25, 每个 D触发器 25的 输出端耦合到一个数据锁存单元, 并耦合到下一级 D触发器 25 的输出端; 延
迟单元还包括与 D触发器 25对应的计数器 26; D触发器 25的触发端通过计数 器 26耦合到统一的时钟脉沖信号 elk; 当时序信号为高电平时, D触发器会随 着时钟脉沖信号 elk的频率逐级产生时序信号。 其中 D触发器触发端的脉沖信 号 CK1 ~ N可以用时钟脉沖信号 elk通过计数器 1 ~ N产生, 因此, 通过改变计 数器 26就可以产生不同的脉沖信号 CKN,进而产生不同延迟的时序信号 TP1 ~ TPN。 D触发器能实现信号延迟输出, 并有很好的跟随特性, 且成本低廉, 有利 于降成本; 通过计数器可以灵活设置 D触发器的延迟输出时间。
实施例二
如图 9所示, 本发明还公开一种本发明液晶面板驱动电路的驱动方法, 包 括步骤:
A: 监控模块的时序信号通过延迟单元耦合到数据锁存单元;
B:所述较长的引线耦合的延迟单元的延迟触发时间小于较短的引线耦合的 延迟单元的延迟触发时间; 所述延迟单元到达预定的延迟触发时间后, 将时序 信号转换成低电平状态并发送到数据锁存单元, 控制数据锁存单元输出显示信 号到相应的数据线。
为了彻底解决显示信号延迟的问题, 达到最佳的显示效果, 步骤 B中包括: 控制延迟单元的延迟触发时间, 使得每个数据锁存单元输出的显示信号抵达同 一行液晶面板的像素的时间相等。
本实施例的延迟单元可以选用 D触发器, 具体控制电路和方法参见实施例 以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明, 不 能认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通 技术人员来说, 在不脱离本发明构思的前提下, 还可以做出若干筒单推演或替 换, 都应当视为属于本发明的保护范围。
Claims
1、 一种液晶面板的驱动电路, 所述液晶面板包括多条数据线、 与数据线连 接的引线, 所述驱动电路包括监控模块和数据驱动模块, 所述数据驱动模块包 括与液晶面板的引线耦合的数据锁存单元; 所述监控模块输出时序信号控制所 述数据锁存单元输出显示信号到数据线;
所述液晶面板的驱动电路还包括与数据线对应的延迟单元, 所述时序信号 通过所述延迟单元发送到所述数据锁存单元; 所述延迟单元到达预定的延迟触 发时间后, 控制数据锁存单元输出显示信号到相应的数据线; 所述较长的引线 耦合的延迟单元的延迟触发时间小于较短的引线耦合的延迟单元的延迟触发时 间。
2、 如权利要求 1所述的液晶面板的驱动电路, 其中, 所述液晶面板的数据 线耦合有像素, 所述延迟单元控制每个数据锁存单元输出的显示信号抵达同一 行像素的时间相等。
3、 如权利要求 1所述的液晶面板的驱动电路, 其中, 所述延迟单元包括多 个级联的 D触发器, 每个 D触发器的输出端耦合到一个数据锁存单元, 并耦合 到下一级 D触发器的输入端;所述延迟单元还包括与所述 D触发器对应的计数 器; 所述 D触发器的触发端通过所述计数器耦合到统一的时钟脉沖信号。
4、 如权利要求 1所述的液晶面板的驱动电路, 其中, 所述数据锁存单元包 括数据暂存器, 与数据暂存器耦合的数模转换模块, 所述数模转换模块将所述 显示信号转化成模拟信号后输出到相应的数据线。
5、 如权利要求 4所述的液晶面板的驱动电路, 其中, 所述时序信号为高电 平时, 所述显示信号从所述数据暂存器传送到所述数模转换模块; 所述时序信 号为低电平时, 所述数模转换模将转换后的显示信号输出到相应的数据线。
6、 如权利要求 1所述的液晶面板的驱动电路, 其中, 所述液晶面板的数据 线耦合有像素, 所述延迟单元控制数据锁存单元输出的显示信号抵达同一行像
素的时间相等; 所述延迟单元包括多个级联的 D触发器, 每个 D触发器的输出 端耦合到一个数据锁存单元, 并耦合到下一级 D触发器的输出端; 所述延迟单 元还包括与所述 D触发器对应的计数器; 所述 D触发器的触发端通过所述计数 器耦合到统一的时钟脉沖信号;
所述数据锁存单元包括数据暂存器, 与数据暂存器耦合的数模转换模块, 所述数模转换模块将所述显示信号转化成模拟信号后输出到相应的数据线; 所 述时序信号为高电平时, 所述显示信号从所述数据暂存器传送到所述数模转换 模块; 所述时序信号为低电平时, 所述数模转换模将转换后的显示信号输出到 相应的数据线。
7、 一种液晶面板装置, 包括液晶面板的驱动电路, 所述液晶面板包括多条 数据线, 与数据线连接的引线, 所述驱动电路包括监控模块和数据驱动模块, 所述数据驱动模块包括与液晶面板的引线耦合的数据锁存单元; 所述监控模块 输出时序信号控制所述数据锁存单元输出显示信号到数据线;
所述液晶面板的驱动电路还包括与数据线对应的延迟单元, 所述时序信号 通过所述延迟单元耦合到所述数据锁存单元; 所述延迟单元到达预定的延迟触 发时间后, 控制数据锁存单元输出显示信号到相应的数据线; 所述较长的引线 耦合的延迟单元的延迟触发时间小于较短的引线耦合的延迟单元的延迟触发时 间。
8、 如权利要求 7所述的液晶面板装置, 其中, 所述液晶面板的数据线耦合 有像素, 所述延迟单元控制每个数据锁存单元输出的显示信号抵达同一行像素 的时间相等。
9、 如权利要求 7所述的液晶面板装置, 其中, 所述延迟单元包括多个级联 的 D触发器, 每个 D触发器的输出端耦合到一个数据锁存单元, 并耦合到下一 级 D触发器的输入端; 所述延迟单元还包括与所述 D触发器对应的计数器; 所 述 D触发器的触发端通过所述计数器耦合到统一的时钟脉沖信号。
10、 如权利要求 7所述的液晶面板装置, 其中, 所述数据锁存单元包括数
据暂存器, 与数据暂存器耦合的数模转换模块, 所述数模转换模块将所述显示 信号转化成模拟信号后输出到相应的数据线。
11、如权利要求 10所述的液晶面板装置, 其中, 所述时序信号为高电平时, 所述显示信号从所述数据暂存器传送到所述数模转换模块; 所述时序信号为低 电平时, 所述数模转换模将转换后的显示信号输出到相应的数据线。
12、 如权利要求 7所述的液晶面板装置, 其中, 所述液晶面板的数据线耦 合有像素, 所述延迟单元控制数据锁存单元输出的显示信号抵达同一行像素的 时间相等; 所述延迟单元包括多个级联的 D触发器, 每个 D触发器的输出端耦 合到一个数据锁存单元, 并耦合到下一级 D触发器的输出端; 所述延迟单元还 包括与所述 D触发器对应的计数器; 所述 D触发器的触发端通过所述计数器耦 合到统一的时钟脉沖信号;
所述数据锁存单元包括数据暂存器, 与数据暂存器耦合的数模转换模块, 所述数模转换模块将所述显示信号转化成模拟信号后输出到相应的数据线; 所 述时序信号为高电平时, 所述显示信号从所述数据暂存器传送到所述数模转换 模块; 所述时序信号为低电平时, 所述数模转换模将转换后的显示信号输出到 相应的数据线。
13、 一种液晶面板驱动电路的驱动方法, 所述液晶面板包括多条数据线, 与数据线耦合的数据驱动模块, 与数据驱动模块耦合的监控模块; 所述数据驱 动模块包括与数据线对应的数据锁存单元和延迟单元; 所述驱动方法包括步骤:
A: 监控模块的时序信号通过延迟单元耦合到数据锁存单元;
B: 所述较长的引线耦合的延迟单元的延迟触发时间小于较短的引线耦合的 延迟单元的延迟触发时间; 所述延迟单元到达预定的延迟触发时间后, 将时序 信号转换成低电平状态并发送到数据锁存单元, 控制数据锁存单元输出显示信 号到相应的数据线。
14、 如权利要求 13所述的液晶面板驱动电路的驱动方法, 其中, 所述步骤 B中包括:控制延迟单元的延迟触发时间,使得每个数据锁存单元输出的显示信
号抵达同一行液晶面板的像素的时间相等。
15、 如权利要求 13所述的液晶面板驱动电路的驱动方法, 其中, 所述步骤 B中包括: 采用 D触发器控制延迟时间。
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CN104732944A (zh) * | 2015-04-09 | 2015-06-24 | 京东方科技集团股份有限公司 | 源极驱动电路、源极驱动方法及显示装置 |
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CN104064154B (zh) * | 2014-05-26 | 2016-07-06 | 深圳市华星光电技术有限公司 | 液晶面板的电路结构及液晶面板的驱动方法 |
CN104835471B (zh) * | 2015-05-28 | 2019-04-05 | 南京中电熊猫液晶显示科技有限公司 | 一种液晶面板的源极驱动器 |
US10410599B2 (en) * | 2015-08-13 | 2019-09-10 | Samsung Electronics Co., Ltd. | Source driver integrated circuit for ompensating for display fan-out and display system including the same |
CN105161062B (zh) * | 2015-08-28 | 2018-05-04 | 南京中电熊猫液晶显示科技有限公司 | 一种液晶显示面板 |
CN105118423A (zh) * | 2015-10-09 | 2015-12-02 | 京东方科技集团股份有限公司 | 用于驱动显示面板的数据驱动模组、方法及显示装置 |
WO2018143025A1 (ja) * | 2017-01-31 | 2018-08-09 | シャープ株式会社 | 表示装置およびその駆動方法 |
TWI673702B (zh) * | 2017-04-26 | 2019-10-01 | 矽創電子股份有限公司 | 顯示裝置及其驅動電路 |
CN108735172A (zh) * | 2018-05-24 | 2018-11-02 | 深圳市华星光电技术有限公司 | 液晶显示电路及液晶显示器 |
CN109686290B (zh) * | 2019-01-18 | 2022-04-15 | 合肥京东方显示技术有限公司 | 显示驱动装置及方法、显示装置 |
JP2020134890A (ja) * | 2019-02-26 | 2020-08-31 | セイコーエプソン株式会社 | タイミングコントローラーおよび表示装置 |
CN112382226B (zh) * | 2020-11-27 | 2022-04-26 | Tcl华星光电技术有限公司 | 数据驱动芯片以及显示装置 |
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