WO2014121545A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
WO2014121545A1
WO2014121545A1 PCT/CN2013/072857 CN2013072857W WO2014121545A1 WO 2014121545 A1 WO2014121545 A1 WO 2014121545A1 CN 2013072857 W CN2013072857 W CN 2013072857W WO 2014121545 A1 WO2014121545 A1 WO 2014121545A1
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WIPO (PCT)
Prior art keywords
semiconductor
layer
semiconductor device
gate conductor
forming
Prior art date
Application number
PCT/CN2013/072857
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French (fr)
Chinese (zh)
Inventor
朱慧珑
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中国科学院微电子研究所
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Publication of WO2014121545A1 publication Critical patent/WO2014121545A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

Definitions

  • the present invention relates to semiconductor technology and, more particularly, to a semiconductor device including a fin (Fm) formed using an SOI wafer and a method of fabricating the same.
  • Background technique
  • the FinFET includes a channel region formed in the middle of the fin of the semiconductor material, and source/drain regions formed at both ends of the fin.
  • the gate electrode surrounds the channel region (i.e., the double gate structure) at least on both sides of the channel region, thereby forming an inversion layer on each side of the channel. Since the entire channel region can be controlled by the gate, it is possible to suppress the short channel effect.
  • UTBB Ultra-thin buried oxide body
  • the UTBB type FET includes an ultra-thin buried oxide layer in a semiconductor substrate, a front gate and source/drain regions over the ultra-thin oxide buried layer, and a back gate under the ultra-thin buried oxide layer.
  • power consumption can be significantly reduced while maintaining the same speed.
  • An object of the present invention is to provide a semiconductor device which utilizes fins and a back gate to improve performance and a method of fabricating the same.
  • a semiconductor device comprising: a semiconductor substrate; a contact region in the semiconductor substrate; a sandwich structure on the contact region, the sandwich structure including a back gate conductor, located on both sides of the back gate conductor a semiconductor fin, and a respective back gate dielectric separating the back gate conductor from the semiconductor fin, wherein the contact region is part of a conductive path of the back gate conductor; a front gate stack intersecting the semiconductor fin, the front gate The stack includes a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductor from the semiconductor fin; an insulating cap over the back gate conductor and over the semiconductor fin, and the insulating cap covers the back gate conductor to the front
  • the gate conductors are spaced apart; and source and drain regions connected to the channel regions provided by the semiconductor fins.
  • a method of fabricating a semiconductor device including:
  • the back gate conductor Since the back gate conductor is not formed under the semiconductor fins, the contact area between the back gate conductor and the well region as a part of the conductive path can be independently determined as needed to avoid the self-heating effect generated by the back gate conductor. Also, since it is not necessary to perform ion implantation through the semiconductor fins when forming the back gate conductor, unintentional doping of the channel region can be avoided to cause fluctuation in device performance. Further Ground, the back gate conductor is connected to the well region via the highly doped region, so that the contact resistance between the back gate conductor and the well region can be reduced.
  • the semiconductor device combines the advantages of FinFET and UTBB type FETs.
  • the back gate conductor can be used to control or dynamically adjust the threshold voltage of the semiconductor device, and the power consumption can be significantly reduced while maintaining the speed.
  • Fin can be utilized. The short channel effect is suppressed, and the performance of the semiconductor device is maintained when the semiconductor device is shrunk. Therefore, the semiconductor device can reduce power consumption while reducing the size of the semiconductor device to improve integration. Further, and the method of manufacturing the semiconductor device is compatible with the conventional semiconductor process, the manufacturing cost is low.
  • FIGS. 1-13 are schematic views showing semiconductor structures at various stages of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.
  • FIG. 14-15 illustrate schematic views of a semiconductor structure at a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.
  • 16-18 are schematic views of semiconductor structures at a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.
  • semiconductor structure refers to a general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
  • semiconductor structure refers to a general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
  • the semiconductor material includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a Group IV semiconductor such as Si, Ge.
  • the gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaTbN, TaErN.
  • the gate dielectric may be composed of Si ⁇ 2 or a material having a dielectric constant greater than Si ⁇ 2 , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, Si.
  • the nitride includes, for example, Si 3 N 4
  • the silicate includes, for example, HfiiOx
  • the aluminate includes, for example, LaA10 3
  • a titanate for example Including SrTi0 3
  • the oxynitride includes, for example, SiON.
  • the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.
  • the present invention can be embodied in various forms, some of which are described below.
  • FIG. 13a An exemplary flow of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention is described with reference to Figures 1-13, wherein the top view and the cut-away position of the cross-sectional view of the semiconductor structure are shown in Figure 13a, in Figures 1-12 and 13b
  • a cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIG. 13c, which is shown in FIG. 13d.
  • FIG. 13d A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin.
  • the method begins with an SOI wafer.
  • the SOI wafer includes a stack of a semiconductor substrate 101, a buried insulating layer 103, and a semiconductor layer 104, wherein the buried insulating layer 103 separates the semiconductor substrate 101 from the semiconductor layer 104.
  • the semiconductor layer 104 and the buried insulating layer 103 Through ion implantation, through the semiconductor layer 104 and the buried insulating layer 103, in the semiconductor A dopant is implanted into the substrate 101 such that an upper region of the semiconductor substrate 101 forms a doped contact region
  • the contact region 102 will be part of the conductive path of the back gate.
  • a process of forming the contact region 102 in the semiconductor substrate 101 is known, for example, by ion implantation to form a doped region in the semiconductor layer and then annealed to activate the dopant in the doped region. Process parameters that control ion implantation and annealing can be controlled as needed to control the depth and extent of contact region 102.
  • the contact region 102 is adjacent to the buried insulating layer 103 (as shown in FIG. 1) or a certain depth within the semiconductor substrate 101 under the buried insulating layer 103.
  • An N-type contact region 102 may be formed for the P-type FET, and a P-type contact region 102 may be formed for the N-type FET.
  • the doping concentration of the contact region 102 is, for example, 1 ⁇ 10 18 cm" 3 -l X 10 21 cm" 0 further, by known deposition processes such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atom
  • EBM electron beam evaporation
  • CVD chemical vapor deposition
  • a first mask layer 105, a second mask layer 106, and a third mask layer 107 are sequentially formed on the semiconductor layer 104 by layer deposition (ALD), sputtering, or the like.
  • a photoresist layer PR is formed on the third mask layer 107, for example, by spin coating, and the photoresist layer PR is formed to define a pattern of the back gate by a photolithography process including exposure and development therein. (For example, an opening having a width of about 15 nm to 100 nm), as shown in FIG.
  • the semiconductor substrate 101 is composed of one selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, and InGaSb.
  • the semiconductor substrate 101 is, for example, a single crystal silicon substrate.
  • the semiconductor layer 104 will form semiconductor fins and determine the approximate height of the semiconductor fins.
  • the first mask layer 105, the second mask layer 106, and the third mask layer 107 may be composed of materials of desired chemical and physical properties to achieve desired etch selectivity in an etching step, and/or in chemistry Mechanical polishing (CMP) acts as a stop layer, and/or as an insulating layer in the final semiconductor device. Also, the first mask layer 105, the second mask layer 106, and the third mask layer 107 may be formed using the same or different deposition processes described above, depending on the materials used.
  • CMP chemistry Mechanical polishing
  • the first mask layer 105 is a silicon oxide layer having a thickness of about 5-15 nm formed by thermal oxidation
  • the second mask layer 106 is amorphous silicon having a thickness of about 50 nm to 200 nm formed by sputtering
  • the third mask layer 107 is a silicon nitride layer having a thickness of about 5-15 nm formed by sputtering.
  • etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution
  • dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution
  • etching step is stopped at the top of the first mask layer due to the selectivity of the etching, or by controlling the etching time. Different layers can be etched separately by etching in multiple steps.
  • the first step of etching includes using a reactive ion etch to remove a third, for example, silicon nitride, with respect to a second mask layer 106, such as comprised of amorphous silicon, using a suitable etchant.
  • the exposed portion of the mask layer 107, the second etching includes the use of reactive ion etching, using another suitable etchant, to remove the upper, for example, amorphous silicon, relative to, for example, the first mask layer 105 consisting of silicon oxide.
  • the exposed portion of the second mask layer 106 includes using a reactive ion etch to remove a third, for example, silicon nitride, with respect to a second mask layer 106, such as comprised of amorphous silicon, using a suitable etchant.
  • a conformal fourth mask layer 108 is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • the portion of the fourth mask layer 108 extending laterally over the third mask layer 107 and the bottom portion of the opening (ie, the first mask layer 105) are removed by an anisotropic etching process (eg, reactive ion etching).
  • an anisotropic etching process eg, reactive ion etching.
  • the portion of the fourth mask layer 108 on the inner wall of the opening is left to form a side wall, as shown in FIG.
  • the fourth mask layer 108 will be used to define the width of the semiconductor fins.
  • the thickness of the fourth mask layer 108 can be controlled according to the desired width of the semiconductor fins.
  • the fourth mask layer 108 is a silicon nitride layer having a thickness of about 3 nm to 28 nm formed by atomic layer deposition.
  • the exposed portion of the first mask layer 105 is removed through the opening by the above-described known etching process. And the exposed portions of the semiconductor layer 104 and the buried insulating layer 103 are further etched as shown in FIG. The etch stops at the top of the contact region 102 such that the opening reaches the top of the contact region 102.
  • a conformal dielectric layer is formed on the surface of the semiconductor structure by the above-described known deposition process. Removing the portion of the read dielectric layer that extends laterally over the third mask layer 107 and the bottom portion of the opening (ie, the exposed surface of the contact region 102 within the opening) by an anisotropic etch process (eg, reactive ion etching) In part, the portion of the dielectric layer on the inner wall of the opening remains such that a back gate dielectric 109 in the form of a sidewall is formed, as shown in FIG.
  • an anisotropic etch process eg, reactive ion etching
  • a back gate dielectric 109 in the form of an oxide spacer can be formed directly on the sidewall of the semiconductor layer 104 within the opening by thermal oxidation, thereby eliminating the need for subsequent anisotropic etching, which can be further Process.
  • the back gate dielectric 109 is a silicon oxide layer having a thickness of about 10 nm to 30 nm.
  • a conductor layer is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • the conductor layer fills at least the opening. Etching the conductor layer to remove a portion located outside the opening, and And further removing a portion of the conductor layer that is located within the opening to form a back gate conductor 110 within the opening, as shown in FIG.
  • the back gate conductor 110 and the semiconductor layer 104 are separated by a back gate dielectric 109.
  • the back gate conductor 110 is composed of polysilicon doped with N-type or P-type, and the doping concentration is, for example, 1 ⁇ 10 18 cm" -l X 10 19 cm" 3 0
  • the etch back used to form the back gate conductor 110 is such that the top of the back gate conductor 110 is below the back gate dielectric 109.
  • the back gate dielectric 109 can be selectively etched back relative to the back gate conductor 110 such that the tops of the back gate dielectric 109 and the back gate conductor 110 are flush, as shown in FIG.
  • the third mask layer 107 located above the second mask layer 106 is selectively completely removed with respect to the second mask layer 106 by the above-described known etching process, thereby The surface of the second mask layer 106 is exposed.
  • silicon oxide can be selectively removed using hydrofluoric acid as an etchant.
  • An insulating layer is formed on the surface of the semiconductor structure by the above-described known deposition process. The insulating layer fills at least the opening to cover the top surface of the back gate conductor 110. The insulating layer is etched back to remove a portion located outside the opening.
  • the insulating layer is a silicon nitride layer formed by sputtering.
  • the read insulating layer and the fourth mask layer 108 together form an insulating cap 108, as shown in FIG.
  • the etch may further remove a portion of the insulating layer that is within the opening. By controlling the time of the etch back, the portion of the insulating layer that is within the opening covers the top of the back gate conductor 110 and provides the desired electrical insulation properties.
  • the second mask layer 106 is selectively completely removed with respect to the insulating cap 108' and the first mask layer 105 by the above-described known etching process, thereby exposing the first
  • the surface of the mask layer 105 is as shown in FIG.
  • the first mask layer 105 is composed of silicon oxide
  • the second mask layer 106 is composed of amorphous silicon
  • the insulating cap 108' is composed of silicon nitride
  • Ammonium (TMAH) acts as an etchant to selectively remove amorphous silicon.
  • the exposed portion of the semiconductor layer 104 is completely removed by the above-described known etching process, as shown in FIG. This etching stops at the top of the buried insulating layer 103.
  • the etch engraves the semiconductor layer 104 into two semiconductor fins 104' on either side of the back gate conductor 110, and the back gate conductor 110 and the two semiconductor fins 104' are separated by respective back gate dielectrics 109, thereby forming Flip-back gate-Fin sandwich structure.
  • the semiconductor fin 104' may be selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, One of a group of MP, GaN, SiC, InGaAs, InSb, and InGaSb.
  • the semiconductor fin 104' is in the form of a strip having a length along a direction perpendicular to the plane of the paper, a width along a lateral direction in the plane of the paper, and a height along the plane of the paper. Vertical direction. The height of the semiconductor fin 104' is substantially determined by the thickness of the initial semiconductor layer 104.
  • the width of the semiconductor fin 104' is substantially determined by the thickness of the initial fourth mask layer 108, and the length of the semiconductor fin 104' can be designed according to the design. Need to be defined by an additional etching step. In the read etch step and subsequent process steps, the previously formed back gate conductor 110 provides mechanical support and protection for the semiconductor fins 104' to achieve high yield.
  • a front gate dielectric is formed on the surface of the semiconductor structure by the above-described known deposition process
  • the front gate dielectric 111 (silicon oxide or silicon nitride), as shown in Figure 11.
  • the front gate dielectric 111 is a silicon oxide layer that is about 0.8-1.5 nm thick. Front gate dielectric 111 covers each side of the two semiconductor fins 104'.
  • a front gate conductor is formed on the surface of the semiconductor structure by the above-described known deposition process
  • the front gate conductor 112 (for example, doped polysilicon), as shown in Figure 12. If necessary, the front gate conductor 112 can be chemical mechanically polished (CMP) to obtain a flat surface.
  • CMP chemical mechanically polished
  • the front gate conductor 112 is then patterned into a strip that intersects the semiconductor fins 104' using a photoresist mask.
  • the photoresist layer is then removed by dissolving or ashing in a solvent.
  • a nitride layer is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • the read nitride layer is a silicon nitride layer having a thickness of about 5-20 nm.
  • the laterally extending portion of the nitride layer is removed by an anisotropic etching process (eg, reactive ion etching) such that a vertical portion of the nitride layer on the side of the front gate conductor 112 remains, thereby forming a gate spacer 113, This is shown in Figures 13a, 13b, 13c and 13d.
  • anisotropic etching process eg, reactive ion etching
  • the semiconductor fins 104, the nitride layer on the sides The thickness is smaller than the thickness of the nitride layer on the side of the front gate conductor 112, so that the nitride layer on the side of the semiconductor fin 104' can be completely removed in this etching step. Otherwise, the nitride layer on the side of the semiconductor fin 104' will affect the formation of subsequent source/drain regions.
  • An additional mask can be used to further remove the nitride layer on the side of the semiconductor fin 104'.
  • the front gate conductor 112 and the front gate dielectric 111 together form a gate stack.
  • the front gate conductor 112 is in the form of a strip and extends in a direction perpendicular to the length of the semiconductor fin.
  • the source and drain regions associated with the channel regions provided by the semiconductor fins 104' may be formed in a conventional process with the previous gate conductor 112 and gate spacers 113 as hard masks.
  • the source and drain regions can be doped regions formed by ion implantation or in-situ doping at both ends of the semiconductor fin 104'.
  • the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fins 104.
  • FIGS. 14a and 15a An exemplary flow of a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention is described with reference to Figures 14-15, wherein the top and bottom views of the semiconductor structure are shown in Figures 14a and 15a, A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown in FIGS. 14b and 15b, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIGS. 14c and 15c. A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin is shown in FIGS. 14d and 15d.
  • the steps shown in Figs. 14 and 15 are further performed after the step shown in Fig. 13 to form a stress acting layer.
  • the stressor layer 114 is epitaxially grown on the exposed side of the semiconductor fin 104' by the known deposition process described above, as shown in Figures 14a, 14b, 14c and 14d. A stress acting layer 114 is also formed on the front gate conductor 112. The thickness of the stressor layer 114 should be sufficient to apply the desired stress on the semiconductor fins 104.
  • Different stress active layers 114 can be formed for different types of FinFETs.
  • the stressor layer 114 is formed using a semiconductor material different from the material of the semiconductor fin 104' to produce a desired stress.
  • the stress acting layer 114 is, for example, a Si:C layer having a C content of about 0.2 to 2% by atom formed on the Si substrate, and a tensile stress is applied to the channel region along the longitudinal direction of the channel region. .
  • the stress acting layer 114 is, for example, a SiGe layer having a Ge content of about 155% by atom on the Si substrate, and a compressive stress is applied to the channel region along the longitudinal direction of the channel region.
  • a second insulating layer 115 is formed on the surface of the semiconductor structure by the above-described known deposition process.
  • the second insulating layer 115 is, for example, a silicon oxide layer and is thick enough to be filled in
  • An opening formed in the etching step of the semiconductor fin 104' is formed on the side of the semiconductor fin 104' and also covers the top surface of the front gate conductor 112.
  • the second insulating layer 115 is chemically mechanically polished with the gate spacer 113 as a stop layer to obtain a flat surface as shown in Figs. 15a, 15b, 15c and 15d.
  • the chemical mechanical polishing removes a portion of the stressor layer 115 above the front gate conductor 112 and exposes the top surface of the front gate conductor 112.
  • the source of the channel region provided by the semiconductor fin 104' may be formed by using the conventional gate process 112 and the gate spacer 113 as a hard mask in a conventional process. Zone and drain zone.
  • the source and drain regions can be doped regions formed by ion implantation or in-situ doping across the semiconductor fins 104'.
  • the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fins 104'.
  • FIGS. 16b, 17b, and 18b A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown in FIGS. 16b, 17b, and 18b, and is shown in FIGS. 16c, 17c, and 18c along the line BB in the width direction of the semiconductor fin.
  • FIGS. 16d, 17d, and 18d A cross-sectional view of a semiconductor structure is shown in Figs. 16d, 17d, and 18d as a cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin.
  • the sacrificial gate conductor 11 is formed in the step of FIG. 11, the sacrificial gate dielectric 112' is formed in the step of FIG. 12, and the stress acting layer 114 is formed after the step shown in FIG. The regions and drain regions, and then further performing the steps illustrated in Figures 16-18, replace the sacrificial gate stack including the sacrificial gate conductor 11 and the sacrificial gate dielectric 112' with a replacement gate stack including a replacement gate conductor and a replacement gate dielectric.
  • the sacrificial gate conductor 11 ⁇ is removed by the above-described known etching process (for example, reactive ion etching), thereby forming a gate opening.
  • the portion of the sacrificial gate dielectric 112' located at the bottom of the gate opening can be further removed, as shown in Figures 16a, 16b, 16c and 16d.
  • a replacement gate dielectric 116 is formed in the gate opening, as shown in Figures 17a, 17b, 17c and 17d, and the gate opening is filled with a conductive material to form a replacement gate conductor 117.
  • the replacement gate conductor 117 and the replacement gate dielectric 116 together form a replacement gate stack.
  • the replacement gate dielectric 116 is a Hf ⁇ 2 layer having a thickness of about 0.3 nm to 1.2 nm
  • the replacement gate conductor 117 is, for example, a TiN layer.
  • an interlayer insulating layer after forming the source and drain regions, an interlayer insulating layer, a plug in the interlayer insulating layer, a wiring on the upper surface of the interlayer insulating layer, or The electrodes, thereby completing other parts of the semiconductor device.
  • Figure 19 shows an exploded perspective view of a semiconductor device 100 in accordance with a preferred embodiment of the present invention, wherein the second insulating layer 115 is not shown for clarity.
  • the semiconductor device 100 is formed using the steps illustrated in Figures 1-18 to include various preferred aspects of the present invention, but should not be construed as limiting the present invention to combinations of the various preferred aspects.
  • the materials already mentioned above will not be repeated for the sake of clarity.
  • the semiconductor device 100 includes a semiconductor substrate 101, a contact region 102 in the semiconductor substrate 101, and a sandwich structure on the contact region 102.
  • the read sandwich structure includes a back gate conductor 110, two semiconductor fins 104' on either side of the back gate conductor 110, and a respective back gate dielectric 109 separating the back gate conductor 110 from the two semiconductor fins 104', respectively.
  • Contact region 102 is part of the conductive path of back gate conductor 110.
  • the buried insulating layer 103 is located below the semiconductor fins 104'.
  • the front gate stack intersects the semiconductor fins 104', which include a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductor from the semiconductor fins 104'.
  • the front gate dielectric is a replacement gate dielectric 116 formed in accordance with a back gate process
  • the front gate conductor is a replacement gate conductor 117 formed in accordance with a back gate process.
  • the gate spacer 113 is on the side of the replacement gate conductor 117. During the back gate process, although the portion of the sacrificial gate electrode 113' located within the gate opening is removed, the portion under the gate spacer 113 remains.
  • the insulative cap 108' is positioned over the back gate conductor 110 and separates the back gate conductor 110 from the alternate gate conductor 117.
  • the buried insulating layer 103 is located between the replacement gate dielectric 118 and the contact region 102 and separates the replacement gate dielectric 118 from the contact region 102.
  • the semiconductor device 100 also includes a source region 118a and a drain region 118b connected to the channel region provided by the semiconductor fin 104'.
  • the source region 118a and the drain region 118b may be semiconductor fins 104, doped regions formed by ion implantation or in-situ doping at both ends.
  • An additional stress active layer 114 is in contact with the sides of the semiconductor fins 104'.
  • Four plungers 119 are connected through the interlayer insulating layers to the source and drain regions of the two semiconductor fins 104', respectively.
  • An additional plunger 119 is coupled to the replacement gate conductor 117, Another additional 119 is connected to the contact region 102 through the interlayer insulating layer and the buried insulating layer 103 to be connected to the back gate conductor 110 via the contact region 102.

Abstract

Provided are a semiconductor device and manufacturing method thereof, the semiconductor device comprising: a semiconductor substrate (101), a contact region (102) in the semiconductor substrate (101), a sandwich structure located on the contact region (102), a front-gate stack intersecting with semiconductor fins (104'), an insulation cap (108') located above a back-gate conductor (110) and the semiconductor fins (104'), and a source region and a drain region connected with a channel region provided by the semiconductor fins (104'). The sandwich structure comprises the back-gate conductor (110), the semiconductor fins (104') located on the two sides of the back-gate conductor (110), and respective back-gate dielectrics (109) each isolating the back-gate conductor (110) from the semiconductor fin (104'); the contact region (102) is part of the conductive path of the back-gate conductor (110); the front-gate stack comprises a front-gate dielectric (111) and a front-gate conductor (112), and the front-gate dielectric (111) isolates the front-gate conductor (112) from the semiconductor fins (104'); and the insulation cap (108') isolates the back-gate conductor (110) from the front-gate conductor (112). The semiconductor device realizes high integration and low power consumption.

Description

半导体器件及其制造方法 本申请要求了 2013年 2月 8日提交的、 申请号为 201310050056.3、 发明 名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通 过引用结合在本申请中。 技术领域  The present application claims priority to Chinese Patent Application No. 201310050056.3, entitled "Semiconductor Device and Its Manufacturing Method", filed on February 8, 2013, the entire contents of In this application. Technical field
本发明涉及半导体技术， 更具体地， 涉及采用 SOI 晶片形成的包含鳍片 ( Fm ) 的半导体器件及其制造方法。 背景技术  The present invention relates to semiconductor technology and, more particularly, to a semiconductor device including a fin (Fm) formed using an SOI wafer and a method of fabricating the same. Background technique
随着半导体技术的发展，希望在减小半导体器件的尺寸以提高集成度的同 时减小功耗。 为了抑制由于尺寸缩小而导致的短沟道效应， 提出了在 SOI 晶 片或块状半导体衬底上形成的 FinFET。 FinFET包括在半导体材料的鳍片的中 间形成的沟道区， 以及在鳍片两端形成的源 /漏区。 栅电极至少在沟道区的两 个侧面包围沟道区 （即双栅结构）， 从而在沟道各侧上形成反型层。 由于整个 沟道区都能受到栅极的控制， 因此能够起到抑制短沟道效应的作用。 为了减小 由于漏电导致的功耗， 提出了在半导体衬底中形成的 UTBB ( ultra-thin buried oxide body )型 FET。 UTBB型 FET包括位于半导体衬底中的超薄掩埋氧化物 层、 位于超薄氧化物埋层上方的前栅和源 /漏区、 以及位于超薄掩埋氧化物层 下方的背栅。 在工作中， 通过向背栅施加偏置电压， 可以在维持速度不变的情 形下显著减小功耗。  With the development of semiconductor technology, it is desirable to reduce the power consumption while reducing the size of a semiconductor device to improve integration. In order to suppress the short channel effect due to size reduction, a FinFET formed on an SOI wafer or a bulk semiconductor substrate has been proposed. The FinFET includes a channel region formed in the middle of the fin of the semiconductor material, and source/drain regions formed at both ends of the fin. The gate electrode surrounds the channel region (i.e., the double gate structure) at least on both sides of the channel region, thereby forming an inversion layer on each side of the channel. Since the entire channel region can be controlled by the gate, it is possible to suppress the short channel effect. In order to reduce power consumption due to leakage, a UTBB (Ultra-thin buried oxide body) type FET formed in a semiconductor substrate has been proposed. The UTBB type FET includes an ultra-thin buried oxide layer in a semiconductor substrate, a front gate and source/drain regions over the ultra-thin oxide buried layer, and a back gate under the ultra-thin buried oxide layer. In operation, by applying a bias voltage to the back gate, power consumption can be significantly reduced while maintaining the same speed.
尽管存在着各自的优点，但还没有提出一种将两种的优点结合在一起的半 导体器件， 这是因为在 FinFET中形成背栅存在着许多困难。 在基于块状半导 体衬底的 FinFET中， 由于半导体鳍片与半导体衬底的接触面积 4艮小， 所形成 的背栅将导致严重的自热效应。 在基于 SOI晶片的 FinFET中， 由于 SOI晶片 的价格昂贵而导致高成本的问题。 而且， 在 SOI 晶片形成背栅需要采用精确 控制的离子注入， 穿过顶部半导体层在掩埋绝缘层下方形成用于背栅的注入 区，从而导致工艺上的困难使得成品率低， 以及由于对沟道区的非有意掺杂而 导致器件性能波动。 发明内容 Despite their respective advantages, a semiconductor device that combines the advantages of both has not been proposed because of the many difficulties in forming a back gate in a FinFET. In a bulk semiconductor substrate-based FinFET, since the contact area of the semiconductor fin to the semiconductor substrate is small, the formed back gate will cause a severe self-heating effect. In a FinFET based on an SOI wafer, a high cost problem arises due to the high price of the SOI wafer. Moreover, the formation of the back gate on the SOI wafer requires precise controlled ion implantation through the top semiconductor layer to form an implant region for the back gate under the buried insulating layer, resulting in process difficulties resulting in low yield, and due to the trench Unintentional doping Causes device performance to fluctuate. Summary of the invention
本发明的目的是提供一种利用鳍片和背栅改善性能的半导体器件及其制 造方法。  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which utilizes fins and a back gate to improve performance and a method of fabricating the same.
根据本发明的一方面， 提供了一种半导体器件， 包括： 半导体衬底； 半导 体衬底中的接触区； 位于接触区上的夹层结构， 该夹层结构包括背栅导体、 位 于背栅导体两侧的半导体鳍片、以及将背栅导体与半导体鳍片分别隔开的各自 的背栅电介质，其中接触区作为背栅导体的导电路径的一部分； 与半导体鳍片 相交的前栅堆叠，该前栅堆叠包括前栅电介质和前栅导体，并且前栅电介质将 前栅导体和半导体鳍片隔开；位于背栅导体上方以及半导体鳍片上方的绝缘帽 盖， 并且绝缘帽盖将背栅导体与前栅导体隔开； 以及与半导体鳍片提供的沟道 区相连的源区和漏区。  According to an aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor substrate; a contact region in the semiconductor substrate; a sandwich structure on the contact region, the sandwich structure including a back gate conductor, located on both sides of the back gate conductor a semiconductor fin, and a respective back gate dielectric separating the back gate conductor from the semiconductor fin, wherein the contact region is part of a conductive path of the back gate conductor; a front gate stack intersecting the semiconductor fin, the front gate The stack includes a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductor from the semiconductor fin; an insulating cap over the back gate conductor and over the semiconductor fin, and the insulating cap covers the back gate conductor to the front The gate conductors are spaced apart; and source and drain regions connected to the channel regions provided by the semiconductor fins.
根据本发明的另一方面， 提供了一种制造半导体器件的方法， 包括： 在 According to another aspect of the present invention, a method of fabricating a semiconductor device is provided, including:
SOI晶片的半导体衬底中形成接触区， SOI晶片包括半导体衬底、 掩埋绝缘层 和半导体层的堆叠； 在半导体层上形成多个掩模层； 在所述多个掩模层中的最 顶部的一个中形成开口； 在开口内壁形成侧墙形式的另一个掩模层； 采用所述 另一个掩模层作为硬掩模，将开口穿过所述多个掩模层和所述半导体层延伸到 接触区； 在开口内壁形成背栅电介质； 在开口中形成背栅导体； 在开口中形成 绝缘帽盖， 该绝缘帽盖包括所述另一个掩模层并且覆盖背栅电介质和背栅导 体； 采用绝缘帽盖作为硬掩模， 将半导体层图案化为半导体鳍片； 形成与半导 体鳍片相交的前栅堆叠，该前栅堆叠包括前栅电介质和前栅导体， 并且前栅电 介质将前栅导体和半导体鳍片隔开；以及形成与半导体鳍片提供的沟道区相连 的源区和漏区。 导体。 由于背栅导体未形成在半导体鳍片下方， 因此可以根据需要独立地确定 该背栅导体与作为导电路径的一部分的阱区之间的接触面积，以避免背栅导体 产生的自热效应。 并且， 由于在形成背栅导体时不需要执行穿过半导体鳍片的 离子注入， 因此可以避免对沟道区的非有意掺杂而导致器件性能波动。进一步 地， 背栅导体经由高掺杂区与阱区相连，使得可以减小背栅导体与阱区之间的 接触电阻。 Forming a contact region in the semiconductor substrate of the SOI wafer, the SOI wafer including a stack of the semiconductor substrate, the buried insulating layer, and the semiconductor layer; forming a plurality of mask layers on the semiconductor layer; at the top of the plurality of mask layers Forming an opening in one of the openings; forming another mask layer in the form of a sidewall in the inner wall of the opening; using the other mask layer as a hard mask, extending the opening through the plurality of mask layers and the semiconductor layer a contact region; forming a back gate dielectric in the inner wall of the opening; forming a back gate conductor in the opening; forming an insulating cap in the opening, the insulating cap including the another mask layer and covering the back gate dielectric and the back gate conductor; Using a insulating cap as a hard mask, patterning the semiconductor layer into semiconductor fins; forming a front gate stack that intersects the semiconductor fins, the front gate stack including a front gate dielectric and a front gate conductor, and the front gate dielectric will front gate The conductor is separated from the semiconductor fin; and a source and drain regions are formed that are connected to the channel region provided by the semiconductor fin. conductor. Since the back gate conductor is not formed under the semiconductor fins, the contact area between the back gate conductor and the well region as a part of the conductive path can be independently determined as needed to avoid the self-heating effect generated by the back gate conductor. Also, since it is not necessary to perform ion implantation through the semiconductor fins when forming the back gate conductor, unintentional doping of the channel region can be avoided to cause fluctuation in device performance. Further Ground, the back gate conductor is connected to the well region via the highly doped region, so that the contact resistance between the back gate conductor and the well region can be reduced.
该半导体器件结合了 FinFET和 UTBB型 FET的优点，一方面可以利用背 栅导体控制或动态调整半导体器件的阈值电压，在维持速度不变的情形下显著 减小功耗， 另一方面可以利用 Fin抑制短沟道效应， 在缩小半导体器件时维持 半导体器件的性能。 因此，该半导体器件可以在减小半导体器件的尺寸以提高 集成度的同时减小功耗。 并且， 并且该半导体器件的制造方法与现有的半导体 工艺兼容， 因而制造成本低。 附图说明  The semiconductor device combines the advantages of FinFET and UTBB type FETs. On the one hand, the back gate conductor can be used to control or dynamically adjust the threshold voltage of the semiconductor device, and the power consumption can be significantly reduced while maintaining the speed. On the other hand, Fin can be utilized. The short channel effect is suppressed, and the performance of the semiconductor device is maintained when the semiconductor device is shrunk. Therefore, the semiconductor device can reduce power consumption while reducing the size of the semiconductor device to improve integration. Further, and the method of manufacturing the semiconductor device is compatible with the conventional semiconductor process, the manufacturing cost is low. DRAWINGS
通过以下参照附图对本发明实施例的描述， 本发明的上述以及其他目的、 特征和优点将更为清楚， 在附图中：  The above and other objects, features and advantages of the present invention will become more apparent from
图 1-13是示出了根据本发明的一个实施例的制造半导体器件的方法的各 个阶段的半导体结构的示意图。  1-13 are schematic views showing semiconductor structures at various stages of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.
图 14-15示出了根据本发明的进一步优选实施例的制造半导体器件的方法 的一部分阶段的半导体结构的示意图。  14-15 illustrate schematic views of a semiconductor structure at a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.
图 16-18示出了根据本发明的进一步优选实施例的制造半导体器件的方法 的一部分阶段的半导体结构的示意图。  16-18 are schematic views of semiconductor structures at a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention.
具体实施方式 detailed description
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类 似的附图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。  The invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by like reference numerals. For the sake of clarity, the various parts in the figures are not drawn to scale.
为了简明起见， 可以在一幅图中描述经过数个步骤后获得的半导体结构。 应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个区域"上面"或"上方"时， 可以指直接位于另一层、 另一个区域上面， 或 者在其与另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件 翻转， 该一层、 一个区域将位于另一层、 另一个区域"下面"或"下方"。  For the sake of brevity, the semiconductor structure obtained after several steps can be described in one figure. It should be understood that when describing a structure of a device, when a layer or a region is referred to as being "above" or "above" another layer, another region may be directly above another layer or another region, or Other layers or regions are also included between it and another layer. Also, if the device is flipped, the layer, one area will be located on the other layer, and the other area "below" or "below".
如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将采用"直 接在 ... ...上面"或"在 ... ...上面并与之邻接 "的表述方式。 If you want to describe the situation directly above another layer or another area, this article will use "straight Connected to the expression "above" or "adjacent to".
在本申请中，术语"半导体结构"指在制造半导体器件的各个步骤中形成的 整个半导体结构的统称， 包括已经形成的所有层或区域。在下文中描述了本发 明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理工艺和技术， 以便 更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照 这些特定的细节来实现本发明。  In the present application, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed. Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the invention, in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.
除非在下文中特别指出，半导体器件的各个部分可以由本领域的技术人员 公知的材料构成。 半导体材料例如包括 III-V族半导体， 如 GaAs、 InP、 GaN、 SiC, 以及 IV族半导体， 如 Si、 Ge。 栅导体可以由能够导电的各种材料形成， 例如金属层、掺杂多晶硅层、或包括金属层和掺杂多晶硅层的叠层栅导体或者 是其他导电材料， 例如为 TaC、 TiN、 TaTbN、 TaErN, TaYbN, TaSiN, HfSiN, MoSiN、 RuTax, NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 Ti肅、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 Hf u、 RuOx和所述各种导电材料的组合。 栅电介质 可以由 Si〇2或介电常数大于 Si〇2的材料构成， 例如包括氧化物、 氮化物、 氧 氮化物、 硅酸盐、 铝酸盐、 钛酸盐， 其中， 氧化物例如包括 Si〇2、 Hf02、 Zr02、 A1203、 Ti02、 La203, 氮化物例如包括 Si3N4, 硅酸盐例如包括 HffiiOx, 铝酸 盐例如包括 LaA103，钛酸盐例如包括 SrTi03,氧氮化物例如包括 SiON。并且， 栅电介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发 的用于栅电介质的材料。 Unless otherwise indicated below, various portions of the semiconductor device can be constructed from materials well known to those skilled in the art. The semiconductor material includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a Group IV semiconductor such as Si, Ge. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaTbN, TaErN. , TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, Ti, TaN, PtSix, Ni 3 Si, Pt, Ru, Ir, Mo, Hf u, RuOx and the various conductive materials Combination of materials. The gate dielectric may be composed of Si〇 2 or a material having a dielectric constant greater than Si〇 2 , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, Si. 〇 2 , Hf0 2 , Zr0 2 , A1 2 0 3 , Ti0 2 , La 2 0 3 , the nitride includes, for example, Si 3 N 4 , the silicate includes, for example, HfiiOx, the aluminate includes, for example, LaA10 3 , a titanate, for example Including SrTi0 3 , the oxynitride includes, for example, SiON. Also, the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.
本发明可以各种形式呈现， 以下将描述其中一些示例。  The present invention can be embodied in various forms, some of which are described below.
参照图 1-13描述根据本发明的一个实施例的制造半导体器件的方法的示 例流程， 其中， 在图 13a中示出了半导体结构的俯视图及截面图的截取位置， 在图 1-12和 13b中示出在半导体鳍片的宽度方向上沿线 A-A截取的半导体结 构的截面图， 在图 13c中示出在半导体鳍片的宽度方向上沿线 B-B截取的半 导体结构的截面图， 在图 13d中示出在半导体鳍片的长度方向上沿线 C-C截 取的半导体结构的截面图。  An exemplary flow of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention is described with reference to Figures 1-13, wherein the top view and the cut-away position of the cross-sectional view of the semiconductor structure are shown in Figure 13a, in Figures 1-12 and 13b A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIG. 13c, which is shown in FIG. 13d. A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin.
该方法开始于 SOI晶片。 该 SOI晶片包括半导体衬底 101、 掩埋绝缘层 103和半导体层 104的叠层， 其中掩埋绝缘层 103将半导体衬底 101和半导体 层 104隔开。 通过离子注入， 穿过半导体层 104和掩埋绝缘层 103， 在半导体 衬底 101 中注入掺杂剂， 使得半导体衬底 101 的上部区域形成掺杂的接触区The method begins with an SOI wafer. The SOI wafer includes a stack of a semiconductor substrate 101, a buried insulating layer 103, and a semiconductor layer 104, wherein the buried insulating layer 103 separates the semiconductor substrate 101 from the semiconductor layer 104. Through ion implantation, through the semiconductor layer 104 and the buried insulating layer 103, in the semiconductor A dopant is implanted into the substrate 101 such that an upper region of the semiconductor substrate 101 forms a doped contact region
102。 正如下文将描述的那样， 接触区 102将作为背栅的导电路径的一部分。 在半导体衬底 101中形成接触区 102的工艺是已知的，例如采用离子注入从而 在半导体层中形成掺杂区然后进行退火以激活掺杂区中的掺杂剂。可以根据需 要控制控制离子注入和退火的工艺参数， 以控制接触区 102 的深度及延伸范 围。 该接触区 102与掩埋绝缘层 103邻接（如图 1所示）， 或者位于掩埋绝缘 层 103下方的半导体衬底 101内的一定深度。 针对 P型 FET可以形成 N型接 触区 102，针对 N型 FET可以形成 P型接触区 102。接触区 102的掺杂浓度例 如为 1 X 1018 cm"3-l X 1021 cm" 0 进一步地， 通过已知的沉积工艺， 如电子束蒸 发（EBM )、 化学气相沉积（CVD )、 原子层沉积（ALD )、 溅射等， 在半导体 层 104上依次形成第一掩模层 105、 第二掩模层 106和第三掩模层 107。 然后， 例如通过旋涂在第三掩模层 107上形成光致抗蚀剂层 PR, 并通过其中包括曝 光和显影的光刻工艺将光致抗蚀剂层 PR形成用于限定背栅的图案（例如， 宽 度约为 15nm-100nm的开口）， 如图 1所示。 102. As will be described below, the contact region 102 will be part of the conductive path of the back gate. A process of forming the contact region 102 in the semiconductor substrate 101 is known, for example, by ion implantation to form a doped region in the semiconductor layer and then annealed to activate the dopant in the doped region. Process parameters that control ion implantation and annealing can be controlled as needed to control the depth and extent of contact region 102. The contact region 102 is adjacent to the buried insulating layer 103 (as shown in FIG. 1) or a certain depth within the semiconductor substrate 101 under the buried insulating layer 103. An N-type contact region 102 may be formed for the P-type FET, and a P-type contact region 102 may be formed for the N-type FET. The doping concentration of the contact region 102 is, for example, 1×10 18 cm" 3 -l X 10 21 cm" 0 further, by known deposition processes such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atom A first mask layer 105, a second mask layer 106, and a third mask layer 107 are sequentially formed on the semiconductor layer 104 by layer deposition (ALD), sputtering, or the like. Then, a photoresist layer PR is formed on the third mask layer 107, for example, by spin coating, and the photoresist layer PR is formed to define a pattern of the back gate by a photolithography process including exposure and development therein. (For example, an opening having a width of about 15 nm to 100 nm), as shown in FIG.
半导体衬底 101由选自 Si、 Ge、 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs, InSb和 InGaSb构成的组中的一种组成。 在一个示例中， 半导体衬底 101例如是单晶硅衬底。正如下文将要描述的，半导体层 104将形 成半导体鳍片， 并且决定了半导体鳍片的大致高度。  The semiconductor substrate 101 is composed of one selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, and InGaSb. In one example, the semiconductor substrate 101 is, for example, a single crystal silicon substrate. As will be described below, the semiconductor layer 104 will form semiconductor fins and determine the approximate height of the semiconductor fins.
第一掩模层 105、 第二掩模层 106和第三掩模层 107可以由所需化学和物 理性质的材料组成， 从而在蚀刻步骤中获得所需的蚀刻选择性， 和 /或在化学 机械抛光（CMP ) 中作为停止层， 和 /或在最终的半导体器件中进一步作为绝 缘层。 并且， 根据使用的材料， 第一掩模层 105、 第二掩模层 106和第三掩模 层 107可以采用相同或不同的上述沉积工艺形成。在一个示例中， 第一掩模层 105是通过热氧化形成的厚度约为 5-15nm的氧化硅层， 第二掩模层 106是通 过溅射形成的厚度约为 50nm-200nm的非晶硅层，第三掩模层 107是通过溅射 形成的厚度约为 5-15nm的氮化硅层。  The first mask layer 105, the second mask layer 106, and the third mask layer 107 may be composed of materials of desired chemical and physical properties to achieve desired etch selectivity in an etching step, and/or in chemistry Mechanical polishing (CMP) acts as a stop layer, and/or as an insulating layer in the final semiconductor device. Also, the first mask layer 105, the second mask layer 106, and the third mask layer 107 may be formed using the same or different deposition processes described above, depending on the materials used. In one example, the first mask layer 105 is a silicon oxide layer having a thickness of about 5-15 nm formed by thermal oxidation, and the second mask layer 106 is amorphous silicon having a thickness of about 50 nm to 200 nm formed by sputtering. The third mask layer 107 is a silicon nitride layer having a thickness of about 5-15 nm formed by sputtering.
然后， 采用光致抗蚀剂层 PR作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过使用蚀刻剂溶液的湿法蚀刻， 从上至下去除第三掩模层 107和第二掩模层 106的暴露部分而形成开口，如图 2所示。 由于蚀刻的选择性， 或者通过控制蚀刻时间， 使得该蚀刻步骤停止在 第一掩模层的顶部。 可以多个步骤的蚀刻分别蚀刻不同层。 在一个示例中， 第 一步蚀刻包括采用反应离子蚀刻，使用一种合适的蚀刻剂，相对于例如由非晶 硅组成的第二掩模层 106去除上面的例如由氮化硅组成的第三掩模层 107的暴 露部分， 第二步蚀刻包括采用反应离子蚀刻， 使用另一种合适的蚀刻剂， 相对 于例如由氧化硅组成的第一掩模层 105 去除上面的例如由非晶硅组成的第二 掩模层 106的暴露部分。 Then, using the photoresist layer PR as a mask, by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution, from top to bottom Removing the exposed portions of the third mask layer 107 and the second mask layer 106 to form an opening, as shown in FIG. 2 is shown. The etching step is stopped at the top of the first mask layer due to the selectivity of the etching, or by controlling the etching time. Different layers can be etched separately by etching in multiple steps. In one example, the first step of etching includes using a reactive ion etch to remove a third, for example, silicon nitride, with respect to a second mask layer 106, such as comprised of amorphous silicon, using a suitable etchant. The exposed portion of the mask layer 107, the second etching includes the use of reactive ion etching, using another suitable etchant, to remove the upper, for example, amorphous silicon, relative to, for example, the first mask layer 105 consisting of silicon oxide. The exposed portion of the second mask layer 106.
然后， 通过在溶剂中溶解或灰化去除光致抗蚀剂层 PR。 通过上述已知的 沉积工艺， 在半导体结构的表面上形成共形的第四掩模层 108。 通过各向异性 的蚀刻工艺 （例如， 反应离子蚀刻）， 去除第四掩模层 108在第三掩模层 107 上方横向延伸的部分以及位于开口的底部（即第一掩模层 105上）的部分， 使 得第四掩模层 108位于开口内壁上的部分保留而形成侧墙，如图 3所示。正如 下文将要描述的， 第四掩模层 108将用于限定半导体鳍片的宽度。可以根据所 需的半导体鳍片的宽度控制第四掩模层 108的厚度。在一个示例中， 第四掩模 层 108是通过原子层沉积形成的厚度约为 3nm-28nm的氮化硅层。  Then, the photoresist layer PR is removed by dissolving or ashing in a solvent. A conformal fourth mask layer 108 is formed on the surface of the semiconductor structure by the above-described known deposition process. The portion of the fourth mask layer 108 extending laterally over the third mask layer 107 and the bottom portion of the opening (ie, the first mask layer 105) are removed by an anisotropic etching process (eg, reactive ion etching). In part, the portion of the fourth mask layer 108 on the inner wall of the opening is left to form a side wall, as shown in FIG. As will be described below, the fourth mask layer 108 will be used to define the width of the semiconductor fins. The thickness of the fourth mask layer 108 can be controlled according to the desired width of the semiconductor fins. In one example, the fourth mask layer 108 is a silicon nitride layer having a thickness of about 3 nm to 28 nm formed by atomic layer deposition.
然后， 采用第三掩模层 107和第四掩模层 108作为硬掩模，通过上述已知 的蚀刻工艺经由开口去除第一掩模层 105的暴露部分。并且进一步蚀刻半导体 层 104和掩埋绝缘层 103的暴露部分，如图 4所示。该蚀刻在接触区 102的顶 部停止， 使得开口到达接触区 102的顶部。  Then, using the third mask layer 107 and the fourth mask layer 108 as a hard mask, the exposed portion of the first mask layer 105 is removed through the opening by the above-described known etching process. And the exposed portions of the semiconductor layer 104 and the buried insulating layer 103 are further etched as shown in FIG. The etch stops at the top of the contact region 102 such that the opening reaches the top of the contact region 102.
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成共形的电介 质层。 通过各向异性的蚀刻工艺 （例如， 反应离子蚀刻）， 去除读电介质层在 第三掩模层 107上方横向延伸的部分以及位于开口的底部（即接触区 102在开 口内的暴露表面上）的部分，使得该电介质层位于开口内壁上的部分保留而形 成侧墙形式的背栅电介质 109， 如图 5所示。 代替其中沉积电介质层的工艺， 可以通过热氧化直接在半导体层 104位于开口内的侧壁上形成氧化物侧墙形 式的背栅电介质 109, 从而不需要随后的各向异性蚀刻， 这可以进一步筒化工 艺。 在一个示例中， 背栅电介质 109是厚度约为 10nm-30nm的氧化硅层。  Then, a conformal dielectric layer is formed on the surface of the semiconductor structure by the above-described known deposition process. Removing the portion of the read dielectric layer that extends laterally over the third mask layer 107 and the bottom portion of the opening (ie, the exposed surface of the contact region 102 within the opening) by an anisotropic etch process (eg, reactive ion etching) In part, the portion of the dielectric layer on the inner wall of the opening remains such that a back gate dielectric 109 in the form of a sidewall is formed, as shown in FIG. Instead of a process in which a dielectric layer is deposited, a back gate dielectric 109 in the form of an oxide spacer can be formed directly on the sidewall of the semiconductor layer 104 within the opening by thermal oxidation, thereby eliminating the need for subsequent anisotropic etching, which can be further Process. In one example, the back gate dielectric 109 is a silicon oxide layer having a thickness of about 10 nm to 30 nm.
然后， 通过上述已知的沉积工艺， 在半导体结构的表面上形成导体层。 该 导体层至少填满开口。 对该导体层进行回蚀刻， 去除位于开口外部的部分， 并 且进一步去除该导体层位于开口内的一部分,从而在开口内形成背栅导体 110， 如图 6所示。 背栅导体 110与半导体层 104之间由背栅电介质 109隔开。在一 个示例中， 背栅导体 110由掺杂为 N型或 P型的多晶硅组成， 掺杂浓度例如 为 1 X 1018 cm" -l X 1019 cm"3 0 Then, a conductor layer is formed on the surface of the semiconductor structure by the above-described known deposition process. The conductor layer fills at least the opening. Etching the conductor layer to remove a portion located outside the opening, and And further removing a portion of the conductor layer that is located within the opening to form a back gate conductor 110 within the opening, as shown in FIG. The back gate conductor 110 and the semiconductor layer 104 are separated by a back gate dielectric 109. In one example, the back gate conductor 110 is composed of polysilicon doped with N-type or P-type, and the doping concentration is, for example, 1×10 18 cm" -l X 10 19 cm" 3 0
用于形成背栅导体 110的回蚀刻使得背栅导体 110的顶部位于背栅电介质 109的下方。 可选地， 可以进一步相对于背栅导体 110选择性地回蚀刻背栅电 介质 109, 使得背栅电介质 109和背栅导体 110的顶部齐平， 如图 Ί所示。  The etch back used to form the back gate conductor 110 is such that the top of the back gate conductor 110 is below the back gate dielectric 109. Alternatively, the back gate dielectric 109 can be selectively etched back relative to the back gate conductor 110 such that the tops of the back gate dielectric 109 and the back gate conductor 110 are flush, as shown in FIG.
然后， 在未使用掩模的情形下， 通过上述已知的蚀刻工艺，相对于第二掩 模层 106， 选择性地完全去除位于第二掩模层 106上方的第三掩模层 107， 从 而暴露第二掩模层 106的表面。在一个示例中，在第二掩模层 106由非晶硅组 成以及第三掩模层 107由氧化硅组成的情形下，可以使用氢氟酸作为蚀刻剂选 择性地去除氧化硅。通过上述已知的沉积工艺，在半导体结构的表面上形成绝 缘层。 该绝缘层至少填满开口， 从而覆盖背栅导体 110的顶部表面。 对该绝缘 层进行回蚀刻， 去除位于开口外部的部分。 在一个示例中， 该绝缘层是通过溅 射形成的氮化硅层。 读绝缘层与第四掩模层 108—起形成绝缘帽盖 108，， 如 图 8所示。该蚀刻可能进一步去除该绝缘层位于开口内的一部分。通过控制回 蚀刻的时间，使得该绝缘层位于开口内的部分覆盖背栅导体 110的顶部， 并且 提供所需的电绝缘特性。  Then, in the case where the mask is not used, the third mask layer 107 located above the second mask layer 106 is selectively completely removed with respect to the second mask layer 106 by the above-described known etching process, thereby The surface of the second mask layer 106 is exposed. In one example, in the case where the second mask layer 106 is composed of amorphous silicon and the third mask layer 107 is composed of silicon oxide, silicon oxide can be selectively removed using hydrofluoric acid as an etchant. An insulating layer is formed on the surface of the semiconductor structure by the above-described known deposition process. The insulating layer fills at least the opening to cover the top surface of the back gate conductor 110. The insulating layer is etched back to remove a portion located outside the opening. In one example, the insulating layer is a silicon nitride layer formed by sputtering. The read insulating layer and the fourth mask layer 108 together form an insulating cap 108, as shown in FIG. The etch may further remove a portion of the insulating layer that is within the opening. By controlling the time of the etch back, the portion of the insulating layer that is within the opening covers the top of the back gate conductor 110 and provides the desired electrical insulation properties.
然后， 在未使用掩模的情形下， 通过上述已知的蚀刻工艺，相对于绝缘帽 盖 108' 和第一掩模层 105, 选择性地完全去除第二掩模层 106, 从而暴露第 一掩模层 105的表面， 如图 9所示。 在一个示例中， 在第一掩模层 105由氧化 硅组成、 第二掩模层 106由非晶硅组成以及绝缘帽盖 108' 由氮化硅组成的情 形下， 可以使用四甲基氢氧化铵（TMAH )作为蚀刻剂选择性地去除非晶硅。  Then, in the case where the mask is not used, the second mask layer 106 is selectively completely removed with respect to the insulating cap 108' and the first mask layer 105 by the above-described known etching process, thereby exposing the first The surface of the mask layer 105 is as shown in FIG. In one example, in the case where the first mask layer 105 is composed of silicon oxide, the second mask layer 106 is composed of amorphous silicon, and the insulating cap 108' is composed of silicon nitride, tetramethyl hydroxide can be used. Ammonium (TMAH) acts as an etchant to selectively remove amorphous silicon.
然后， 采用绝缘帽盖 108' 作为硬掩模， 通过上述已知的蚀刻工艺完全去 除半导体层 104的暴露部分， 如图 10所示。 该蚀刻在掩埋绝缘层 103的顶部 停止。该蚀刻将半导体层 104图案化成位于背栅导体 110两侧的两个半导体鳍 片 104'， 背栅导体 110与两个半导体鳍片 104' 之间由各自的背栅电介质 109 隔开， 从而形成鳍片-背栅 -鳍片 （ Fin-Back Gate-Fin ) 的夹层结构。  Then, using the insulating cap 108' as a hard mask, the exposed portion of the semiconductor layer 104 is completely removed by the above-described known etching process, as shown in FIG. This etching stops at the top of the buried insulating layer 103. The etch engraves the semiconductor layer 104 into two semiconductor fins 104' on either side of the back gate conductor 110, and the back gate conductor 110 and the two semiconductor fins 104' are separated by respective back gate dielectrics 109, thereby forming Flip-back gate-Fin sandwich structure.
半导体鳍片 104' 可以由选自 Si、 Ge、 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 MP, GaN、 SiC、 InGaAs, InSb和 InGaSb构成的组中的一种组成。 在图 10 所示的示例中， 半导体鳍片 104' 的形状为条带， 其长度沿着垂直于纸面的方 向， 其宽度沿着纸面内的横向方向， 其高度沿着纸面内的垂直方向。 半导体鳍 片 104' 的高度大致由初始的半导体层 104的厚度决定， 半导体鳍片 104' 的 宽度大致由初始的第四掩模层 108的厚度决定， 半导体鳍片 104' 的长度则可 以根据设计需要通过附加的蚀刻步骤限定。在读蚀刻步骤以及随后的工艺步骤 中， 先前形成的背栅导体 110为半导体鳍片 104' 提供了机械支撑和保护， 从 而可以获得高成品率。 The semiconductor fin 104' may be selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, One of a group of MP, GaN, SiC, InGaAs, InSb, and InGaSb. In the example shown in FIG. 10, the semiconductor fin 104' is in the form of a strip having a length along a direction perpendicular to the plane of the paper, a width along a lateral direction in the plane of the paper, and a height along the plane of the paper. Vertical direction. The height of the semiconductor fin 104' is substantially determined by the thickness of the initial semiconductor layer 104. The width of the semiconductor fin 104' is substantially determined by the thickness of the initial fourth mask layer 108, and the length of the semiconductor fin 104' can be designed according to the design. Need to be defined by an additional etching step. In the read etch step and subsequent process steps, the previously formed back gate conductor 110 provides mechanical support and protection for the semiconductor fins 104' to achieve high yield.
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成前栅电介质 Then, a front gate dielectric is formed on the surface of the semiconductor structure by the above-described known deposition process
111 (氧化硅或氮化硅）， 如图 11所示。 在一个示例中， 该前栅电介质 111为 约 0.8-1.5nm厚的氧化硅层。 前栅电介质 111覆盖两个半导体鳍片 104' 的各 自的一个侧面。 111 (silicon oxide or silicon nitride), as shown in Figure 11. In one example, the front gate dielectric 111 is a silicon oxide layer that is about 0.8-1.5 nm thick. Front gate dielectric 111 covers each side of the two semiconductor fins 104'.
然后， 通过上述已知的沉积工艺， 在半导体结构的表面上形成前栅导体 Then, a front gate conductor is formed on the surface of the semiconductor structure by the above-described known deposition process
112 (例如， 掺杂多晶硅）， 如图 12所示。 如果需要， 可以对前栅导体 112进 行化学机械抛光（CMP ), 以获得平整的表面。 112 (for example, doped polysilicon), as shown in Figure 12. If necessary, the front gate conductor 112 can be chemical mechanically polished (CMP) to obtain a flat surface.
然后，采用光致抗蚀剂掩模，将前栅导体 112图案化为与半导体鳍片 104' 相交的条带。 然后， 通过在溶剂中溶解或灰化去除光致抗蚀剂层。 通过上述已 知的沉积工艺， 在半导体结构的表面上形成氮化物层。 在一个示例中， 读氮化 物层为厚度约 5-20nm的氮化硅层。 通过各向异性的蚀刻工艺 （例如， 反应离 子蚀刻）， 去除氮化物层的横向延伸的部分， 使得氮化物层位于前栅导体 112 的侧面上的垂直部分保留，从而形成栅极侧墙 113， 如图 13a、 13b、 13c和 13d 所示。  The front gate conductor 112 is then patterned into a strip that intersects the semiconductor fins 104' using a photoresist mask. The photoresist layer is then removed by dissolving or ashing in a solvent. A nitride layer is formed on the surface of the semiconductor structure by the above-described known deposition process. In one example, the read nitride layer is a silicon nitride layer having a thickness of about 5-20 nm. The laterally extending portion of the nitride layer is removed by an anisotropic etching process (eg, reactive ion etching) such that a vertical portion of the nitride layer on the side of the front gate conductor 112 remains, thereby forming a gate spacer 113, This is shown in Figures 13a, 13b, 13c and 13d.
通常， 由于形状因子（例如栅导体层（例如， 掺杂多晶硅）的厚度大于两 倍的鳍的高度， 或者采用上大下小的鳍片形状）， 半导体鳍片 104， 侧面上的 氮化物层厚度比前栅导体 112的侧面上的氮化物层厚度小，从而在该蚀刻步骤 中可以完全去除半导体鳍片 104' 侧面上的氮化物层。 否则， 半导体鳍片 104' 侧面上的氮化物层会影响后续源 /漏区的形成。 可以采用附加的掩模进一步去 除半导体鳍片 104' 侧面上的氮化物层。  Typically, due to the shape factor (eg, the thickness of the gate conductor layer (eg, doped polysilicon) is greater than twice the height of the fin, or the upper and lower fin shapes are used), the semiconductor fins 104, the nitride layer on the sides The thickness is smaller than the thickness of the nitride layer on the side of the front gate conductor 112, so that the nitride layer on the side of the semiconductor fin 104' can be completely removed in this etching step. Otherwise, the nitride layer on the side of the semiconductor fin 104' will affect the formation of subsequent source/drain regions. An additional mask can be used to further remove the nitride layer on the side of the semiconductor fin 104'.
前栅导体 112和前栅电介质 111一起形成栅堆叠。 在图 13a、 13b、 13c和 13d所示的示例中， 前栅导体 112的形状为条带， 并且沿着与半导体鳍片的长 度垂直的方向延伸。 The front gate conductor 112 and the front gate dielectric 111 together form a gate stack. In Figures 13a, 13b, 13c and In the example shown in Fig. 13d, the front gate conductor 112 is in the form of a strip and extends in a direction perpendicular to the length of the semiconductor fin.
在随后的步骤中， 可以按照常规的工艺， 以前栅导体 112和栅极侧墙 113 作为硬掩模， 形成与半导体鳍片 104' 提供的沟道区相连的源区和漏区。 在一 个示例中， 源区和漏区可以是半导体鳍片 104' 两端的通过离子注入或原位掺 杂形成的掺杂区。 在另一个示例中， 源区和漏区可以是与半导体鳍片 104， 的 两端或侧面接触的附加的半导体层中通过离子注入或原位掺杂形成的掺杂区。  In a subsequent step, the source and drain regions associated with the channel regions provided by the semiconductor fins 104' may be formed in a conventional process with the previous gate conductor 112 and gate spacers 113 as hard masks. In one example, the source and drain regions can be doped regions formed by ion implantation or in-situ doping at both ends of the semiconductor fin 104'. In another example, the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fins 104.
参照图 14-15描述根据本发明的进一步优选实施例的制造半导体器件的方 法的一部分阶段的示例流程， 其中， 在图 14a和 15a 中示出了半导体结构的 俯视图及截面图的截取位置，在图 14b和 15b中示出在半导体鳍片的宽度方向 上沿线 A-A截取的半导体结构的截面图， 在图 14c和 15c中示出在半导体鳍 片的宽度方向上沿线 B-B截取的半导体结构的截面图， 在图 14d和 15d中示 出在半导体鳍片的长度方向上沿线 C-C截取的半导体结构的截面图。  An exemplary flow of a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention is described with reference to Figures 14-15, wherein the top and bottom views of the semiconductor structure are shown in Figures 14a and 15a, A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown in FIGS. 14b and 15b, and a cross-sectional view of the semiconductor structure taken along line BB in the width direction of the semiconductor fin is shown in FIGS. 14c and 15c. A cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin is shown in FIGS. 14d and 15d.
根据该优选实施例， 在图 13所示的步骤之后进一步执行图 14和 15所示 的步骤以形成应力作用层。  According to the preferred embodiment, the steps shown in Figs. 14 and 15 are further performed after the step shown in Fig. 13 to form a stress acting layer.
通过上述已知的沉积工艺， 在半导体鳍片 104' 的暴露侧面上外延生长应 力作用层 114， 如图 14a、 14b、 14c和 14d所示。 应力作用层 114还形成在前 栅导体 112上。 该应力作用层 114的厚度应当足以在半导体鳍片 104， 上施加 期望的应力。  The stressor layer 114 is epitaxially grown on the exposed side of the semiconductor fin 104' by the known deposition process described above, as shown in Figures 14a, 14b, 14c and 14d. A stress acting layer 114 is also formed on the front gate conductor 112. The thickness of the stressor layer 114 should be sufficient to apply the desired stress on the semiconductor fins 104.
针对不同类型的 FinFET可以形成不同的应力作用层 114。 通过应力作用 层 114向 FinFET的沟道区施加合适的应力， 可以提高载流子的迁移率， 从而 减小导通电阻并提高器件的开关速度。 为此， 采用与半导体鳍片 104' 的材料 不同的半导体材料形成应力作用层 114, 可以产生期望的应力。 对于 N型 FinFET, 应力作用层 114例如是在 Si衬底上形成的 C的含量约为原子百分比 0.2-2%的 Si: C层， 沿着沟道区的纵向方向对沟道区施加拉应力。 对于 P型 FinFET,应力作用层 114例如是在 Si衬底上形成的 Ge的含量约为原子百分比 15-75%的 SiGe层， 沿着沟道区的纵向方向对沟道区施加压应力。  Different stress active layers 114 can be formed for different types of FinFETs. By applying a suitable stress to the channel region of the FinFET through the stress-applying layer 114, the carrier mobility can be increased, thereby reducing the on-resistance and increasing the switching speed of the device. To this end, the stressor layer 114 is formed using a semiconductor material different from the material of the semiconductor fin 104' to produce a desired stress. For the N-type FinFET, the stress acting layer 114 is, for example, a Si:C layer having a C content of about 0.2 to 2% by atom formed on the Si substrate, and a tensile stress is applied to the channel region along the longitudinal direction of the channel region. . For the P-type FinFET, the stress acting layer 114 is, for example, a SiGe layer having a Ge content of about 155% by atom on the Si substrate, and a compressive stress is applied to the channel region along the longitudinal direction of the channel region.
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成第二绝缘层 115。 在一个示例中， 第二绝缘层 115例如是氧化硅层， 并且厚度足以填充在 形成半导体鳍片 104' 的蚀刻步骤中形成的位于半导体鳍片 104' 侧面的开口， 并且还覆盖前栅导体 112的顶部表面。 以栅极侧墙 113作为停止层， 对第二绝 缘层 115进行化学机械抛光， 以获得平整的表面， 如图 15a、 15b、 15c和 15d 所示。 该化学机械抛光去除应力作用层 115的位于前栅导体 112上方的部分， 并且暴露前栅导体 112的顶部表面。 Then, a second insulating layer 115 is formed on the surface of the semiconductor structure by the above-described known deposition process. In one example, the second insulating layer 115 is, for example, a silicon oxide layer and is thick enough to be filled in An opening formed in the etching step of the semiconductor fin 104' is formed on the side of the semiconductor fin 104' and also covers the top surface of the front gate conductor 112. The second insulating layer 115 is chemically mechanically polished with the gate spacer 113 as a stop layer to obtain a flat surface as shown in Figs. 15a, 15b, 15c and 15d. The chemical mechanical polishing removes a portion of the stressor layer 115 above the front gate conductor 112 and exposes the top surface of the front gate conductor 112.
进一步地， 如前所述， 在随后的步骤中， 可以按照常规的工艺， 以前栅导 体 112和栅极侧墙 113作为硬掩模， 形成与半导体鳍片 104' 提供的沟道区相 连的源区和漏区。 在一个示例中， 源区和漏区可以是半导体鳍片 104' 两端的 通过离子注入或原位掺杂形成的掺杂区。在另一个示例中， 源区和漏区可以是 与半导体鳍片 104' 的两端或侧面接触的附加的半导体层中通过离子注入或原 位掺杂形成的掺杂区。  Further, as described above, in a subsequent step, the source of the channel region provided by the semiconductor fin 104' may be formed by using the conventional gate process 112 and the gate spacer 113 as a hard mask in a conventional process. Zone and drain zone. In one example, the source and drain regions can be doped regions formed by ion implantation or in-situ doping across the semiconductor fins 104'. In another example, the source and drain regions may be doped regions formed by ion implantation or in-situ doping in an additional semiconductor layer in contact with both ends or sides of the semiconductor fins 104'.
参照图 16-18描述根据本发明的进一步优选实施例的制造半导体器件的方 法的一部分阶段的示例流程， 其中， 在图 16a、 17a和 18a 中示出了半导体结 构的俯视图及截面图的截取位置， 在图 16b、 17b和 18b中示出在半导体鳍片 的宽度方向上沿线 A-A截取的半导体结构的截面图， 在图 16c、 17c和 18c中 示出在半导体鳍片的宽度方向上沿线 B-B截取的半导体结构的截面图， 在图 16d、 17d和 18d中示出在半导体鳍片的长度方向上沿线 C-C截取的半导体结 构的截面图。  An exemplary flow of a portion of a stage of a method of fabricating a semiconductor device in accordance with a further preferred embodiment of the present invention is described with reference to Figures 16-18, wherein a top view of the semiconductor structure and a cut-out position of the cross-sectional view are shown in Figures 16a, 17a and 18a A cross-sectional view of the semiconductor structure taken along line AA in the width direction of the semiconductor fin is shown in FIGS. 16b, 17b, and 18b, and is shown in FIGS. 16c, 17c, and 18c along the line BB in the width direction of the semiconductor fin. A cross-sectional view of a semiconductor structure is shown in Figs. 16d, 17d, and 18d as a cross-sectional view of the semiconductor structure taken along line CC in the length direction of the semiconductor fin.
根据该优选实施例， 在图 11的步骤中形成牺牲栅导体 11 , 在图 12的 步骤中形成牺牲栅电介质 112' , 并且在图 14所示的步骤之后形成应力作用层 114, 并且已经形成源区和漏区， 然后进一步执行图 16-18所示的步骤采用包 括替代栅导体和替代栅介质的替代栅堆叠代替包括牺牲栅导体 11 和牺牲栅 电介质 112' 的牺牲栅堆叠。  According to the preferred embodiment, the sacrificial gate conductor 11 is formed in the step of FIG. 11, the sacrificial gate dielectric 112' is formed in the step of FIG. 12, and the stress acting layer 114 is formed after the step shown in FIG. The regions and drain regions, and then further performing the steps illustrated in Figures 16-18, replace the sacrificial gate stack including the sacrificial gate conductor 11 and the sacrificial gate dielectric 112' with a replacement gate stack including a replacement gate conductor and a replacement gate dielectric.
采用第二绝缘层 115和栅极侧墙 113作为硬掩模，通过上述已知的蚀刻工 艺 （例如反应离子蚀刻）去除牺牲栅导体 11 Γ , 从而形成栅极开口。 可选地， 可以进一步去除牺牲栅电介质 112'位于栅极开口底部的部分，如图 16a、 16b、 16c和 16d所示。 按照后栅工艺， 在栅极开口中形成替代栅电介质 116, 如图 17a, 17b, 17c和 17d所示， 以及利用导电材料填充栅极开口以形成替代栅导 体 117。 替代栅导体 117和替代栅电介质 116一起形成替代栅堆叠。 在一个示 例中， 替代栅电介质 116介是厚度约为 0.3nm-1.2nm的 Hf〇2层， 替代栅导体 117例如是 TiN层。 Using the second insulating layer 115 and the gate spacer 113 as a hard mask, the sacrificial gate conductor 11 去除 is removed by the above-described known etching process (for example, reactive ion etching), thereby forming a gate opening. Alternatively, the portion of the sacrificial gate dielectric 112' located at the bottom of the gate opening can be further removed, as shown in Figures 16a, 16b, 16c and 16d. In accordance with the back gate process, a replacement gate dielectric 116 is formed in the gate opening, as shown in Figures 17a, 17b, 17c and 17d, and the gate opening is filled with a conductive material to form a replacement gate conductor 117. The replacement gate conductor 117 and the replacement gate dielectric 116 together form a replacement gate stack. In a show In the example, the replacement gate dielectric 116 is a Hf 〇 2 layer having a thickness of about 0.3 nm to 1.2 nm, and the replacement gate conductor 117 is, for example, a TiN layer.
根据上述的各个实施例，在形成源区和漏区之后，可以在所得到的半导体 结构上形成层间绝缘层、位于层间绝缘层中的柱塞、位于层间绝缘层上表面的 布线或电极， 从而完成半导体器件的其他部分。  According to various embodiments described above, after forming the source and drain regions, an interlayer insulating layer, a plug in the interlayer insulating layer, a wiring on the upper surface of the interlayer insulating layer, or The electrodes, thereby completing other parts of the semiconductor device.
图 19示出了根据本发明的优选实施例的半导体器件 100的分解透视图， 其中为了清楚而未示出第二绝缘层 115。该半导体器件 100是采用图 1-18所示 的步骤形成，从而包括本发明的多个优选方面， 然而不应理解为将本发明限制 为这多个优选方面的组合。此外， 为了筒明起见不再重复在上文中已经提及的 材料。  Figure 19 shows an exploded perspective view of a semiconductor device 100 in accordance with a preferred embodiment of the present invention, wherein the second insulating layer 115 is not shown for clarity. The semiconductor device 100 is formed using the steps illustrated in Figures 1-18 to include various preferred aspects of the present invention, but should not be construed as limiting the present invention to combinations of the various preferred aspects. In addition, the materials already mentioned above will not be repeated for the sake of clarity.
半导体器件 100包括半导体衬底 101、 半导体衬底 101中的接触区 102、 位于接触区 102上的夹层结构。 读夹层结构包括背栅导体 110、 位于背栅导体 110两侧的两个半导体鳍片 104'、以及将背栅导体 110与两个半导体鳍片 104' 分别隔开的各自的背栅电介质 109。 接触区 102作为背栅导体 110的导电路径 的一部分。 掩埋绝缘层 103位于半导体鳍片 104' 下方。 前栅堆叠与半导体鳍 片 104' 相交， 该前栅堆叠包括前栅电介质和前栅导体， 并且前栅电介质将前 栅导体和半导体鳍片 104' 隔开。  The semiconductor device 100 includes a semiconductor substrate 101, a contact region 102 in the semiconductor substrate 101, and a sandwich structure on the contact region 102. The read sandwich structure includes a back gate conductor 110, two semiconductor fins 104' on either side of the back gate conductor 110, and a respective back gate dielectric 109 separating the back gate conductor 110 from the two semiconductor fins 104', respectively. Contact region 102 is part of the conductive path of back gate conductor 110. The buried insulating layer 103 is located below the semiconductor fins 104'. The front gate stack intersects the semiconductor fins 104', which include a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductor from the semiconductor fins 104'.
在图 19所示的示例中， 前栅电介质是按照后栅工艺形成的替代栅电介质 116, 前栅导体是按照后栅工艺形成的替代栅导体 117。 栅极侧墙 113位于替 代栅导体 117的侧面上。在后栅工艺期间， 虽然去除了牺牲栅电 113 '位于栅极 开口内的部分， 但保留了位于栅极侧墙 113下方的部分。  In the example shown in FIG. 19, the front gate dielectric is a replacement gate dielectric 116 formed in accordance with a back gate process, and the front gate conductor is a replacement gate conductor 117 formed in accordance with a back gate process. The gate spacer 113 is on the side of the replacement gate conductor 117. During the back gate process, although the portion of the sacrificial gate electrode 113' located within the gate opening is removed, the portion under the gate spacer 113 remains.
此外， 绝缘帽盖 108' 位于背栅导体 110上方， 并且将背栅导体 110与替 代栅导体 117隔开。 掩埋绝缘层 103位于替代栅介质 118和接触区 102之间， 并且将替代栅介质 118和接触区 102隔开。  In addition, the insulative cap 108' is positioned over the back gate conductor 110 and separates the back gate conductor 110 from the alternate gate conductor 117. The buried insulating layer 103 is located between the replacement gate dielectric 118 and the contact region 102 and separates the replacement gate dielectric 118 from the contact region 102.
半导体器件 100还包括与半导体鳍片 104'提供的沟道区相连的源区 118a 和漏区 118b。 在图 19所示的示例中， 源区 118a和漏区 118b可以是半导体鳍 片 104，两端的通过离子注入或原位掺杂形成的掺杂区。附加的应力作用层 114 与半导体鳍片 104' 的侧面接触。 四个柱塞 119穿过层间绝缘层分别连接到两 个半导体鳍片 104'的源区和漏区。一个附加的柱塞 119连接到替代栅导体 117， 另一个附加的柱塞 119穿过层间绝缘层和掩埋绝缘层 103连接到接触区 102， 从而经由接触区 102与背栅导体 110相连。 The semiconductor device 100 also includes a source region 118a and a drain region 118b connected to the channel region provided by the semiconductor fin 104'. In the example shown in FIG. 19, the source region 118a and the drain region 118b may be semiconductor fins 104, doped regions formed by ion implantation or in-situ doping at both ends. An additional stress active layer 114 is in contact with the sides of the semiconductor fins 104'. Four plungers 119 are connected through the interlayer insulating layers to the source and drain regions of the two semiconductor fins 104', respectively. An additional plunger 119 is coupled to the replacement gate conductor 117, Another additional 119 is connected to the contact region 102 through the interlayer insulating layer and the buried insulating layer 103 to be connected to the back gate conductor 110 via the contact region 102.
在以上的描述中，对于各层的构图、蚀刻等技术细节并没有做出详细的说 明。 但是本领域技术人员应当理解， 可以通过各种技术手段， 来形成所需形状 的层、 区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以 上描述的方法并不完全相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例中的措施不能有利地结合使用。  In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it will be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination.
以上对本发明的实施例进行了描述。但是，这些实施例仅仅是为了说明的 目的， 而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价 物限定。 不脱离本发明的范围， 本领域技术人员可以做出多种替代和修改， 这 些替代和修改都应落在本发明的范围之内。  The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Numerous alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims

权利 要 求 书 claims
1、 一种半导体器件， 包括： 1. A semiconductor device, including:
半导体衬底； semiconductor substrate;
半导体衬底中的接触区； Contact areas in semiconductor substrates;
位于接触区上的夹层结构，该夹层结构包括背栅导体、位于背栅导体两侧 的半导体鳍片、 以及将背栅导体与半导体鳍片分别隔开的各自的背栅电介质， 其中接触区作为背栅导体的导电路径的一部分； A sandwich structure located on the contact area, the sandwich structure including a back gate conductor, semiconductor fins located on both sides of the back gate conductor, and respective back gate dielectrics respectively separating the back gate conductor and the semiconductor fins, wherein the contact area serves as part of the conductive path of the back gate conductor;
与半导体鳍片相交的前栅堆叠， 该前栅堆叠包括前栅电介质和前栅导体， 并且前栅电介质将前栅导体和半导体鳍片隔开； a front gate stack intersecting the semiconductor fins, the front gate stack including a front gate dielectric and a front gate conductor, and the front gate dielectric separating the front gate conductor and the semiconductor fin;
位于半导体鳍片下方和半导体衬底之间的掩埋绝缘层； a buried insulating layer located beneath the semiconductor fins and between the semiconductor substrate;
位于背栅导体上方以及半导体鳍片上方的绝缘帽盖，并且绝缘帽盖将背栅 导体与前栅导体隔开； 以及 an insulating cap located over the back gate conductor and over the semiconductor fins, and isolating the back gate conductor from the front gate conductor; and
与半导体鳍片提供的沟道区相连的源区和漏区。 Source and drain regions connected to the channel region provided by the semiconductor fin.
2、 根据权利要求 1所述的半导体器件， 其中所述半导体鳍片由选自 Si、 2. The semiconductor device according to claim 1, wherein the semiconductor fin is selected from the group consisting of Si,
Ge、 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs, InSb和 InGaSb 构成的组中的一种组成。 A component of the group consisting of Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb and InGaSb.
3、 根据权利要求 1所述的半导体器件， 其中所述半导体器件是 N型的， 所述接触区是 P型的掺杂区。 3. The semiconductor device according to claim 1, wherein the semiconductor device is N-type, and the contact region is a P-type doped region.
4、 根据权利要求 1所述的半导体器件， 其中所述半导体器件是 P型的， 所述接触区是 N型的掺杂区。 4. The semiconductor device according to claim 1, wherein the semiconductor device is P-type, and the contact region is an N-type doped region.
5、 根据权利要求 3或 4所述的半导体器件， 其中所述接触区的掺杂浓度 例如为 1 X 1018 cm" -l X 1021 cm 5. The semiconductor device according to claim 3 or 4, wherein the doping concentration of the contact region is, for example, 1 × 10 18 cm" - 1 × 10 21 cm
6、 根据权利要求 1所述的半导体器件， 其中所述背栅导体由掺杂的多晶 硅组成。 6. The semiconductor device of claim 1, wherein the back gate conductor is composed of doped polysilicon.
7、 根据权利要求 1所述的半导体器件， 还包括位于前栅电介质和接触区 之间的掩埋绝缘层。 7. The semiconductor device of claim 1, further comprising a buried insulating layer between the front gate dielectric and the contact region.
8、 根据权利要求 1所述的半导体器件， 其中源区和漏区是半导体鳍片两 端的部分。 8. The semiconductor device according to claim 1, wherein the source region and the drain region are parts at both ends of the semiconductor fin.
9、 根据权利要求 1所述的半导体器件， 其中源区和漏区是与半导体鳍片 的两端接触的附加的半导体层中的掺杂区。 9. The semiconductor device according to claim 1, wherein the source region and the drain region are doped regions in an additional semiconductor layer in contact with both ends of the semiconductor fin.
10、根据权利要求 1所述的半导体器件，其中源区和漏区是与半导体鳍片 的侧面接触的附加的半导体层中的掺杂区。 10. The semiconductor device of claim 1, wherein the source and drain regions are doped regions in an additional semiconductor layer in contact with the sides of the semiconductor fin.
11、 根据权利要求 10所述的半导体器件， 其中源区和漏区由与半导体鳍 片不同的材料组成。 11. The semiconductor device according to claim 10, wherein the source region and the drain region are composed of different materials from the semiconductor fin.
12、根据权利要求 1所述的半导体器件，还包括与半导体鳍片的侧面接触 的附加的应力作用层。 12. The semiconductor device of claim 1, further comprising an additional stressor layer in contact with the sides of the semiconductor fin.
13、根据权利要求 12所述的半导体器件，其中所述半导体器件是 N型的， 并且所述半导体鳍片由 Si组成， 所述应力作用层由 C的含量约为原子百分比 0.2-2%的 Si: C组成。 13. The semiconductor device according to claim 12, wherein the semiconductor device is N-type, and the semiconductor fin is composed of Si, and the stress application layer is composed of a C content of about 0.2-2 atomic percent. Si: Composed of C.
14、根据权利要求 12所述的半导体器件，其中所述半导体器件是 P型的， 并且所述半导体鳍片由 Si组成，所述应力作用层由 Ge的含量约为原子百分比 15-75%的 SiGe组成。 14. The semiconductor device according to claim 12, wherein the semiconductor device is P-type, and the semiconductor fin is composed of Si, and the stress application layer is composed of Ge with a content of about 15-75 atomic percent. Composed of SiGe.
15、 一种制造半导体器件的方法， 包括： 15. A method of manufacturing a semiconductor device, including:
在 SOI晶片的半导体衬底中形成接触区， SOI晶片包括半导体衬底、掩埋 绝缘层和半导体层的堆叠； Forming a contact region in a semiconductor substrate of an SOI wafer, the SOI wafer including a semiconductor substrate, a buried insulating layer and a stack of semiconductor layers;
在半导体层上形成多个掩模层； forming a plurality of mask layers on the semiconductor layer;
在所述多个掩模层中的最顶部的一个中形成开口； forming an opening in a topmost one of the plurality of mask layers;
在开口内壁形成侧墙形式的另一个掩模层； Another mask layer in the form of side walls is formed on the inner wall of the opening;
采用所述另一个掩模层作为硬掩模，将开口穿过所述多个掩模层和所述半 导体层延伸到接触区； Using the other mask layer as a hard mask, extend openings through the plurality of mask layers and the semiconductor layer to the contact area;
在开口内壁形成背栅电介质； Form a back gate dielectric on the inner wall of the opening;
在开口中形成背栅导体； forming a back gate conductor in the opening;
在开口中形成绝缘帽盖，读绝缘帽盖包括所述另一个掩模层并且覆盖背栅 电介质和背栅导体； forming an insulating cap in the opening, the insulating cap including the other mask layer and covering the back gate dielectric and the back gate conductor;
采用绝缘帽盖作为硬掩模， 将半导体层图案化为半导体鳍片； Using an insulating cap as a hard mask, the semiconductor layer is patterned into semiconductor fins;
形成与半导体鳍片相交的前栅堆叠，该前栅堆叠包括前栅电介质和前栅导 体， 并且前栅电介质将前栅导体和半导体鳍片隔开； 以及 Ψ forming a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor, and the front gate dielectric separating the front gate conductor and the semiconductor fin; and Ψ
16、 根据权利要求 15所述的方法， 其中所述半导体鳍片由选自 Si、 Ge、 SiGe、 GaAs、 GaSb、 AlAs、 InAs、 InP、 GaN、 SiC、 InGaAs, InSb和 InGaSb 构成的组中的一种组成。 16. The method of claim 15, wherein the semiconductor fin is selected from the group consisting of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb and InGaSb A composition.
17、 根据权利要求 15所述的方法， 其中形成接触区包括穿过 SOI晶片的 半导体层和掩埋绝缘层在半导体衬底中注入掺杂剂。 17. The method of claim 15, wherein forming the contact region includes injecting dopants into the semiconductor substrate through the semiconductor layer and the buried insulating layer of the SOI wafer.
18、 根据权利要求 17所述的方法， 其中所述半导体器件是 N型的， 并且 在形成接触区的步骤中使用 P型掺杂剂。 18. The method of claim 17, wherein the semiconductor device is N-type, and a P-type dopant is used in the step of forming the contact region.
19、 根据权利要求 17所述的方法， 其中所述半导体器件是 P型的， 并且 在形成接触区的步骤中使用 N型掺杂剂。 19. The method of claim 17, wherein the semiconductor device is P-type, and an N-type dopant is used in the step of forming the contact region.
20、 根据权利要求 1所述的方法， 其中形成背栅导体包括： 20. The method of claim 1, wherein forming the back gate conductor includes:
在开口内填充多晶硅； 以及 filling the openings with polysilicon; and
在多晶硅中注入掺杂剂。 Dopants are implanted into the polysilicon.
21、 根据权利要求 15所述的方法， 其中形成源区和漏区包括对半导体鳍 片的两端的离子注入。 21. The method of claim 15, wherein forming the source region and the drain region includes ion implantation to both ends of the semiconductor fin.
22、 根据权利要求 15所述的方法， 其中形成源区和漏区包括形成与半导 体鳍片的两端接触的附加的半导体层，以及对附加的半导体层进行离子注入或 原位掺杂。 22. The method of claim 15, wherein forming the source region and the drain region includes forming an additional semiconductor layer in contact with both ends of the semiconductor fin, and performing ion implantation or in-situ doping on the additional semiconductor layer.
23、 根据权利要求 15所述的方法， 其中形成源区和漏区包括形成与半导 体鳍片的侧面接触的附加的半导体层，以及对附加的半导体层进行离子注入或 原位掺杂。 23. The method of claim 15, wherein forming the source and drain regions includes forming additional semiconductor layers in contact with side surfaces of the semiconductor fins, and ion implanting or in-situ doping the additional semiconductor layers.
24、 根据权利要求 15所述的方法， 还包括形成与半导体鳍片的侧面上外 延生长应力作用层。 24. The method of claim 15, further comprising forming an epitaxially grown stress application layer on the side of the semiconductor fin.
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