WO2014115657A1 - Output-signal generation device, semiconductor device, and output-signal generation method - Google Patents

Output-signal generation device, semiconductor device, and output-signal generation method Download PDF

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Publication number
WO2014115657A1
WO2014115657A1 PCT/JP2014/050838 JP2014050838W WO2014115657A1 WO 2014115657 A1 WO2014115657 A1 WO 2014115657A1 JP 2014050838 W JP2014050838 W JP 2014050838W WO 2014115657 A1 WO2014115657 A1 WO 2014115657A1
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Prior art keywords
phase
signal
circuit
phase adjustment
output
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PCT/JP2014/050838
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French (fr)
Japanese (ja)
Inventor
宮野　和孝
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ピーエスフォー ルクスコ エスエイアールエル
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Publication of WO2014115657A1 publication Critical patent/WO2014115657A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Definitions

  • the present invention relates to an output signal generation device, a semiconductor device, and an output signal generation method, and more particularly to an output signal generation device, a semiconductor device, and an output signal generation method for generating an output signal based on an input signal.
  • a synchronous memory that operates in synchronization with a clock signal is widely used.
  • a DDR (Double Data Rate) type synchronous memory output data needs to be synchronized with an external clock signal, so that a DLL (Delay Locked Loop for generating an internal clock signal synchronized with the external clock signal is used. )
  • the circuit is installed.
  • the DLL circuit includes a counter circuit whose count value is updated based on the phase difference between the external clock signal and the internal clock signal, and a delay line that generates the internal clock signal by delaying the external clock signal based on the counter value of the counter circuit. And having.
  • the counter value that is, the delay amount in the delay line, can realize data synchronization at the timing when the counter value is determined.
  • the operating current of the output transistor changes due to power supply fluctuations as time elapses, the data output timing changes and data synchronization is lost. Therefore, it is known that the adjustment of the counter value is not completed once but intermittently.
  • phase adjustment operation the operation of updating the count value of the counter circuit and delaying the external clock signal based on the updated counter value.
  • Patent Document 1 describes a semiconductor device with a DLL circuit that reduces power consumption by suppressing execution of a phase adjustment operation with low necessity.
  • the semiconductor device described in Patent Document 1 performs a phase adjustment operation when the power supply voltage fluctuates at a predetermined acceleration or higher.
  • the output signal generator of the present invention is An output signal based on the input signal, and a phase adjustment unit capable of executing an adjustment operation for setting a phase difference between the input signal and the output signal to a predetermined value; A phase adjustment control unit that causes the phase adjustment unit to execute the adjustment operation when the phase difference is out of an allowable range including the predetermined value.
  • the output signal generation method of the present invention includes: An output signal generation method performed by an output signal generation apparatus including a phase adjustment unit capable of executing an adjustment operation for generating an output signal based on an input signal and setting a phase difference between the input signal and the output signal to a predetermined value. And When the phase difference is out of an allowable range including the predetermined value, the phase adjustment unit is caused to execute the adjustment operation.
  • the phase adjustment operation is executed when the phase difference between the input signal and the output signal is out of the allowable range. For this reason, when the phase difference between the input signal and the output signal is included in the allowable range, the phase adjustment operation is not performed. Therefore, it is possible to suppress the execution of the phase adjustment operation in a situation where the phase difference between the input signal and the output signal is within the allowable range, that is, the execution of the phase adjustment operation with low necessity.
  • FIG. 1 is a diagram illustrating a semiconductor device 100 according to a first embodiment of the present invention. It is the figure which showed the phase adjustment circuit 107a. It is the figure which showed the phase adjustment control circuit 107b. 6 is a diagram for explaining an operation example of a detection circuit 13; FIG. 4 is a timing chart for explaining operations of a phase adjustment circuit 107a and a phase adjustment control circuit 107b. It is the figure which showed the phase adjustment circuit 107a1 used in 2nd Embodiment. It is the figure which showed the phase adjustment control circuit 107b1 used in 2nd Embodiment. 6 is a timing chart for explaining operations of the phase adjustment circuit 107a1 and the phase adjustment control circuit 107b1.
  • FIG. 1 is a diagram showing a semiconductor device 100 according to the first embodiment of the present invention.
  • a RAM Random Access Memory
  • the semiconductor device 100 includes a clock terminal group 101, a command terminal group 102, an address terminal group 103, a data input / output terminal group 104, and a power supply terminal group 105 as external terminals.
  • the semiconductor device 100 includes a clock input circuit 106, an input / output clock generation unit 107, a command input circuit 108, a command decode circuit 109, a refresh control circuit 110, an address input circuit 111, and an address latch circuit 112.
  • FIFO first-in / first-out
  • the clock terminal group 101 receives external clock signals CK and / CK.
  • a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, external clock signal CK and external clock signal / CK are complementary signals.
  • the clock input circuit 106 receives the external clock signals CK and / CK from the clock terminal group 101, and generates the internal clock signal ICLK synchronized with the external clock signals CK and / CK using the external clock signals CK and / CK.
  • the clock input circuit 106 outputs the internal clock signal ICLK to the input / output clock generation unit 107.
  • the input / output clock generation unit 107 is an example of an output signal generation apparatus according to an embodiment of the present invention.
  • the input / output clock generation unit 107 generates the input / output clock signal LCLK by adjusting the phase of the internal clock signal ICLK.
  • the internal clock signal ICLK is an example of an input signal
  • the input / output clock signal LCLK is an example of an output signal.
  • the input / output clock generator 107 includes a phase adjustment circuit 107a and a phase adjustment control circuit 107b.
  • the phase adjustment circuit 107a is an example of a phase adjustment unit, for example, a DLL circuit.
  • the phase adjustment circuit 107a generates an input / output clock signal LCLK based on the internal clock signal ICLK. Further, the phase adjustment circuit 107a can execute a phase adjustment operation for setting the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK to a predetermined value.
  • the phase adjustment control circuit 107b is an example of a phase adjustment control unit, and determines the adjustment timing at which the phase adjustment circuit 107a executes the phase adjustment operation.
  • This embodiment is characterized by the operation of determining the adjustment timing in the phase adjustment control circuit 107b.
  • the operation of determining the adjustment timing in the phase adjustment control circuit 107b will be described later.
  • the phase adjustment control circuit 107b outputs an enable signal ENA to the phase adjustment circuit 107a at the adjustment timing.
  • the enable signal ENA is an example of an adjustment signal.
  • the phase adjustment circuit 107a performs a phase adjustment operation.
  • the input / output clock signal LCLK generated by the phase adjustment circuit 107a is supplied to the FIFO circuit 117 and the input / output circuit 118.
  • the FIFO circuit 117 and the input / output circuit 118 will be described later.
  • the command terminal group 102 receives a command signal.
  • the command signals are, for example, a row address strobe signal / RAS, a column address strobe signal / CAS, and a reset signal / RESET.
  • the command input circuit 108 receives a command signal from the command terminal group 102 and outputs the command signal to the command decode circuit 109.
  • the command input circuit 108 outputs a reset signal RESET to the phase adjustment circuit 107a and the phase adjustment control circuit 107b, and outputs an initial (initialization) signal INIT to the phase adjustment control circuit 107b.
  • the command decode circuit 109 receives a command signal.
  • the command decode circuit 109 generates an internal command signal by holding the command signal, decoding the command signal, counting the command signal, and the like.
  • the command decode circuit 109 generates, for example, a refresh command, a write command, and a read command as internal command signals.
  • the refresh control circuit 110 receives a refresh command from the command decode circuit 109. When the refresh control circuit 110 receives a refresh command, the refresh control circuit 110 supplies a refresh signal to the row decoder 115.
  • the address terminal group 103 receives an address signal.
  • the address input circuit 111 receives an address signal from the address terminal group 103 and outputs the address signal to the address latch circuit 112.
  • the address latch circuit 112 receives an address signal from the address input circuit 111.
  • the address latch circuit 112 outputs an address signal to the mode register 113 when setting the mode register 113.
  • the address latch circuit 112 outputs a row address of the address signal to the row decoder 115 and outputs a column address of the address signal to the column decoder 116.
  • the mode register 113 is a register in which operation parameters (for example, burst length or CAS latency) of the semiconductor device 100 are set.
  • the mode register 113 receives the internal command signal from the command decode circuit 109 and the address signal from the address latch circuit 112, and sets an operation parameter specified based on the internal command signal and the address signal.
  • the memory cell array 114 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC. Each memory cell MC is specified by a word line WL and a bit line BL.
  • the row decoder 115 receives a row address from the address latch circuit 112 and a write command or a read command from the command decode circuit 109. In addition, the row decoder 115 receives a refresh signal from the refresh control circuit 110.
  • the row decoder 115 When the row decoder 115 receives a write command or a read command, the row decoder 115 selects a word line WL corresponding to the row address from the plurality of word lines WL in the memory cell array 114.
  • a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections.
  • FIG. 1 only one word line WL, one bit line BL, and one memory cell MC are shown for simplicity of explanation.
  • Each bit line BL is connected to a sense amplifier (not shown) corresponding to its own bit line BL.
  • the row decoder 115 When the row decoder 115 receives the refresh signal, the row decoder 115 selects the word line WL corresponding to the row address from the plurality of word lines WL, and refreshes the memory cells MC corresponding to the selected word line WL. Perform a refresh.
  • the column decoder 116 receives the column address from the address latch circuit 112 and the write command or read command from the command decode circuit 109.
  • the column decoder 116 When the column decoder 116 receives the column address and the write command or the read command, the column decoder 116 selects a sense amplifier corresponding to the column address from the plurality of sense amplifiers.
  • Data (read data) in the MC (hereinafter referred to as “selected memory cell”) is amplified by the sense amplifier selected by the column decoder 116, supplied to the FIFO circuit 117, and then supplied to the input / output circuit 118. Is done.
  • the sense amplifier selected by the column decoder 116 writes the write data from the FIFO circuit 117 to the selected memory cell.
  • the FIFO circuit 117 receives the input / output clock signal LCLK from the phase adjustment circuit 107a, and exchanges read data and write data between the memory cell array 114 and the input / output circuit 118 in synchronization with the input / output clock signal LCLK. I do.
  • the data input / output terminal group 104 performs read data output and write data input.
  • the data input / output terminal group 104 is connected to the input / output circuit 118.
  • the input / output circuit 118 receives the input / output clock signal LCLK from the phase adjustment circuit 107a, and outputs read data to the data input / output terminal group 104 in synchronization with the input / output clock signal LCLK during the read operation.
  • the power supply terminal group 105 receives the voltage VDD on the high potential side of the power supply voltage and the voltage VSS on the low potential side of the power supply voltage.
  • the internal power supply generation circuit 119 receives the voltage VDD and the voltage VSS from the power supply terminal group 105 and generates internal power supply voltages such as the voltage VPP, the voltage VPERI, and the voltage VPERR. Note that the voltage VDD and the voltage VSS are also supplied to the phase adjustment control circuit 107b, the FIFO circuit 117, and the input / output circuit 118.
  • phase adjustment circuit 107a Next, the phase adjustment circuit 107a will be described.
  • FIG. 2 is a diagram showing the phase adjustment circuit 107a.
  • the phase adjustment circuit 107 a includes a signal adjustment circuit 1, a replica circuit 2, a phase comparison circuit 3, an update timing generation circuit 4, and a counter circuit 5.
  • the signal adjustment circuit 1 is, for example, a delay line, and generates the input / output clock signal LCLK by delaying the internal clock signal ICLK.
  • a voltage VPERD is supplied to the signal adjustment circuit 1.
  • the signal adjustment circuit 1 includes a coarse delay line that delays the internal clock signal ICLK with a relatively coarse adjustment pitch, and a fine delay that delays the internal clock signal ICLK with a relatively fine adjustment pitch. It is preferable to include a line.
  • the input / output clock signal LCLK is supplied to the FIFO circuit 117 and the input / output circuit 118 and the replica circuit 2 shown in FIG.
  • the replica circuit 2 is a circuit having a delay amount equivalent to a delay amount due to an actual signal route from the signal adjustment circuit 1 to the output terminal group 104 (hereinafter simply referred to as “signal route”).
  • An output buffer included in the input / output circuit 118 is mainly used.
  • the replica circuit 2 outputs a replica clock signal RCLK obtained by delaying the input / output clock signal LCLK by a delay amount by a signal route.
  • the phase of the replica clock signal RCLK substantially matches the phase of the signal output from the data input / output terminal group 104.
  • the phase comparison circuit 3 starts when the enable signal ENA is input, and stops operating when the lock signal LOCK is input.
  • the lock signal LOCK is output from the counter circuit 5 when the phase of the internal clock signal ICLK matches the phase of the replica clock signal RCLK.
  • phase comparison circuit 3 When the phase comparison circuit 3 is activated, it detects the phase difference between the internal clock signal ICLK and the replica clock signal RCLK.
  • the phase of the replica clock signal RCLK is adjusted by the signal adjustment circuit 1 so as to match the phase of the output signal from the data input / output terminal group 104.
  • the phase of both changes momentarily due to fluctuations in parameters such as voltage and temperature which affect the delay amount of the signal adjustment circuit 1 and fluctuations in the frequency of the internal clock signal ICLK itself.
  • the phase comparison circuit 3 detects such a change and determines whether the replica clock signal RCLK is advanced or delayed with respect to the internal clock signal ICLK. This determination is performed for each cycle of the internal clock signal ICLK while the phase comparison circuit 3 is operating.
  • the determination result is supplied to the counter circuit 5 as the phase determination signal UD.
  • the phase determination signal UD is “H”
  • the phase determination signal UD becomes “L”.
  • the update timing generation circuit 4 is activated in response to the input of the enable signal ENA and stops operating in response to the input of the lock signal LOCK, as in the phase comparison circuit 3.
  • the update timing generation circuit 4 divides the internal clock signal ICLK to generate a count timing signal Count_timing that is a one-shot pulse.
  • the count timing signal Count_timing is output to the counter circuit 5 and is used as a synchronization signal indicating the timing at which the count value of the counter circuit 5 is updated. Therefore, the activation cycle of the count timing signal Count_timing is defined as the sampling cycle of the phase adjustment circuit 107a.
  • the counter circuit 5 starts when the enable signal ENA is input and stops operating when the lock signal LOCK is output.
  • the counter circuit 5 sets the delay amount of the signal adjustment circuit 1 during operation.
  • the counter circuit 5 updates the count value in synchronization with the count timing signal Count_timing.
  • the increase / decrease of the count value is determined based on the phase determination signal UD supplied from the phase comparison circuit 3.
  • the counter circuit 5 when the phase determination signal UD is “H”, the counter circuit 5 up-counts the count value in synchronization with the count timing signal Count_timing, thereby increasing the delay amount of the signal adjustment circuit 1. . Conversely, when the phase determination signal UP is “L”, the counter circuit 5 counts down the count value in synchronization with the count timing signal Count_timing, thereby reducing the delay amount of the signal adjustment circuit 1.
  • the counter circuit 5 determines that the phase of the internal clock signal ICLK and the phase of the replica clock signal RCLK coincide with each other when the down count and the up count are alternately repeated a predetermined number of times (for example, twice), and holds the count value at that time However, the activated lock signal LOCK is output, and then the operation is stopped. Note that the counter circuit 5 holds the count value even when the operation is stopped.
  • the counter circuit 5 is supplied with a reset signal RESET. When the reset signal RESET is activated, the counter circuit 5 initializes the count value to a preset value.
  • phase adjustment control circuit 107b Next, the phase adjustment control circuit 107b will be described.
  • FIG. 3 is a diagram showing the phase adjustment control circuit 107b that controls the operation timing of the phase adjustment operation in the phase adjustment circuit 107a.
  • the phase adjustment control circuit 107 b includes an SR latch 11, a determination timing control circuit 12, a detection circuit 13, and an update control circuit 14.
  • Detection circuit 13 includes delay circuits 13a and 13b, phase detection units 13c and 13d, and an OR circuit 13e.
  • phase adjustment control circuit 107b First, an outline of the phase adjustment control circuit 107b will be described.
  • phase adjustment control circuit 107b when the detection circuit 13 detects that the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range including the specific value, the update control circuit 14 The activated enable signal ENA is output to the phase adjustment circuit 107a to cause the phase adjustment circuit 107a to execute the phase adjustment operation.
  • the specific value is a value of a phase difference between the internal clock signal ICLK and the input / output clock signal LCLK in a situation where the phase of the internal clock signal ICLK and the phase of the replica clock signal RCLK match.
  • phase adjustment control circuit 107b suppresses current consumption associated with the phase adjustment operation without executing the phase adjustment operation.
  • the SR latch 11 and the determination timing control circuit 12 cooperate to output an activated comparison timing signal SCLK that determines the detection timing of the detection circuit 13.
  • the SR latch 11 receives the lock signal LOCK at the set terminal S and receives the reset signal RESET at the reset terminal R. Therefore, the SR latch 11 activates (“H”) the output signal from the output terminal Q when the lock signal LOCK is activated (“H”), and activates (“H”) the reset signal RESET. The output signal from the output terminal Q is deactivated (“L”).
  • the determination timing control circuit 12 is activated while the output signal of the SR latch 11 is activated.
  • the determination timing control circuit 12 outputs the activated comparison timing signal SCLK every time the internal clock signal ICLK is counted a predetermined number of times during the active state.
  • the rising timing of the activated comparison timing signal SCLK occurs almost simultaneously with any of the rising timings of the internal clock signal ICLK.
  • the activated comparison timing signal SCLK is supplied to the detection circuit 13 (specifically, the phase detection unit 13c and the delay circuit 13b).
  • the detection circuit 13 detects whether or not the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range including the specific value.
  • the delay circuit 13a and the phase detection unit 13c cooperate to determine whether the phase of the replica clock signal RCLK is advanced (earlier) by the time ⁇ or more than the phase of the internal clock signal ICLK. Detect.
  • the delay circuit 13b and the phase detector 13d cooperate to detect whether or not the phase of the replica clock signal RCLK is delayed by a time ⁇ or more compared to the phase of the internal clock signal ICLK.
  • the delay circuit 13a delays the replica clock signal RCLK by the delay time ⁇ .
  • the delay circuit 13b delays the activated comparison timing signal SCLK by the delay time ⁇ .
  • OR circuit 13e receives the levels of points B and C, respectively, and outputs an OR logic operation result to update control circuit 14. That is, when the phase of the replica clock signal RCLK is earlier or later than the phase of the internal clock signal ICLK by the time ⁇ , the output signal of the OR circuit 13e is activated (H) and falls within the range of time ⁇ ⁇ . Is deactivated (L).
  • the update control circuit 14 shown in FIG. 3 is an OR circuit, for example, and outputs an activated enable signal ENA when receiving an initial signal INIT or an output signal (“H”) activated by the OR circuit 13e. .
  • FIG. 5 is a timing chart for explaining operations of the phase adjustment circuit 107a and the phase adjustment control circuit 107b.
  • a control circuit (not shown) connected to the semiconductor device 100 first applies an external reset signal to the command terminal group 102 in order to activate the phase adjustment circuit 107a during a so-called initial sequence after power-on.
  • an external initial signal indicating the initial sequence is output to the command terminal group 102.
  • the external reset signal and the external initial signal are supplied to the command input circuit 108 via the command terminal group 102, respectively.
  • the command input circuit 108 When the command input circuit 108 receives the reset signal from the command terminal group 102, the command input circuit 108 outputs the activated reset signal RESET (signal P1 in FIG. 5) to the phase adjustment circuit 107a and the phase adjustment control circuit 107b. Further, when receiving an initial signal from the command terminal group 102, the command input circuit 108 outputs the activated initial signal INIT (signal P2 in FIG. 5) to the phase adjustment control circuit 107b.
  • the counter circuit 5 receives the activated reset signal RESET, and initializes the count value to a preset value in accordance with the activated reset signal RESET.
  • the SR latch 11 receives the activated reset signal RESET and deactivates ("L") the output signal from the output terminal Q in accordance with the activated reset signal RESET. .
  • the determination timing control circuit 12 is deactivated and deactivates (“L”) the comparison timing signal SCLK.
  • phase adjustment control circuit 107b when the update control circuit 15a receives the activated initial signal INIT, the update control circuit 15a generates an activated enable signal ENA (signal P3 in FIG. 5) in accordance with the activated initial signal INIT. Outputs the phase adjustment circuit 107a.
  • ENA activated enable signal
  • phase adjustment circuit 107a the phase comparison circuit 3, the update timing generation circuit 4 and the counter circuit 5 each start the phase adjustment operation (phase P101 in FIG. 5) upon receiving the activated enable signal ENA.
  • the counter circuit 5 activates the activated lock signal LOCK (FIG. 5 signal P4) is output to the phase comparison circuit 3, the update timing generation circuit 4 and the SR latch 11, and then the operation is stopped.
  • the phase comparison circuit 3 and the update timing generation circuit 4 stop operating when receiving the activated lock signal LOCK.
  • the SR latch 11 activates the output signal from the output terminal Q when receiving the activated lock signal LOCK.
  • the determination timing control circuit 12 When the output signal from the output terminal Q of the SR latch 11 is activated, the determination timing control circuit 12 is activated, and the activation timing that determines the detection operation timing of the detection circuit 13 every time the internal clock signal ICLK is counted a predetermined number of times.
  • Phase detection of the compared comparison timing signal SCLK (signal P5 at time t2, signal P6 at time t3, signal P7 at time t4, signal P8 at time t5, signal P9 at time t6 in FIG. 5) To the unit 13c and the delay circuit 13b.
  • the delay circuit 13b delays the activated comparison timing signal SCLK by a delay time ⁇ , and outputs the delayed activated comparison timing signal SCLK to the phase detector 13d.
  • the phase detector 13c detects the level of the output signal of the delay circuit 13a at the rising timing of the activated comparison timing signal SCLK, and outputs an output signal having a level corresponding to the detection result.
  • the phase detector 13d detects the level of the replica clock signal RCLK at the rising timing of the delayed activated comparison timing signal SCLK, and outputs an output signal having a level corresponding to the detection result.
  • the phase of the rising edge of the replica clock signal RCLK is longer than the phase of the rising edge of the internal clock signal ICLK by time ⁇ when detected by the phase detectors 13c and 13d associated with the signals P5, P7 and P9. It is not delayed any more and has not advanced more than time ⁇ . For this reason, the levels of the output signal C of the phase detector 13c and the output signal B of the phase detector 13d are “L”, and the level of the output signal A of the OR circuit 13e is also “L”. Therefore, the phase adjustment circuit 107a does not execute the phase adjustment operation according to the signals P5, P7, and P9.
  • the phase adjustment operation with low necessity is not executed. Therefore, it is possible to suppress the current consumption associated with the phase adjustment operation which is not necessary.
  • the phase of the rising edge of the replica clock signal RCLK is delayed by a time ⁇ or more than the phase of the rising edge of the internal clock signal ICLK when detected by the phase detectors 13c and 13d associated with the signal P6. ing. For this reason, the level of the output signal B of the phase detector 13d becomes “H” (signal P10 in FIG. 5), and the level of the output signal A of the OR circuit 13e also becomes “H” (signal P11 in FIG. 5). Then, the enable signal ENA from the update control circuit 14 is activated (signal P12 in FIG. 5). Therefore, the phase adjustment circuit 107a performs a phase adjustment operation in response to the activated enable signal ENA (signal P12 in FIG. 4) (phase P102 in FIG. 4). Therefore, when the rising phase of replica clock signal RCLK is delayed by ⁇ or more than the rising phase of internal clock signal ICLK, the phase difference can be reduced by performing the phase adjustment operation.
  • the phase of the rising edge of the replica clock signal RCLK is earlier than the time of rising of the internal clock signal ICLK by a time ⁇ or more when detected by the phase detectors 13c and 13d associated with the signal P8. ing.
  • the level of the output signal C of the phase detector 13c becomes “H” (signal P13 in FIG. 5), and the level of the output signal A of the OR circuit 13e also becomes “H” (signal P14 in FIG. 5).
  • the enable signal ENA from the update control circuit 14 is activated (signal P15 in FIG. 5). Therefore, the phase adjustment circuit 107a performs a phase adjustment operation in response to the activated enable signal ENA (signal P15 in FIG. 4) (phase P103 in FIG. 4). Therefore, when the rising phase of the replica clock signal RCLK is earlier than the rising phase of the internal clock signal ICLK by a time ⁇ or more, the phase adjustment operation can be performed to reduce the phase difference.
  • the phase adjustment control circuit 107b causes the phase adjustment circuit 107a to perform a phase adjustment operation when the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range.
  • phase adjustment operation when the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is within the allowable range, the phase adjustment operation is not performed. Therefore, it is possible to suppress the execution of the phase adjustment operation in a situation where the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is within the allowable range, that is, the execution of the phase adjustment operation with low necessity. Become.
  • the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK varies with the variation in the power supply voltage, but the phase difference variation with the variation in the power supply voltage is included in the allowable range. There is little need to perform the adjustment operation. For this reason, in the present embodiment, it is possible to suppress the execution of the phase adjustment operation, which is less necessary, as compared with the case where the phase adjustment operation is always performed in accordance with the fluctuation of the power supply voltage, thereby suppressing current consumption. Is possible.
  • the phase adjustment control circuit 107b outputs the activated enable signal ENA to the phase adjustment circuit 107a when the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range. To do.
  • the phase adjustment circuit 107a performs the phase adjustment operation when receiving the activated enable signal ENA.
  • the second embodiment of the present invention causes the signal adjustment circuit 1 of the first embodiment to execute the rising phase adjustment operation, and further, for the falling phase adjustment (Duty adjustment: duty adjustment) with respect to the configuration of the first embodiment.
  • the circuit part is added.
  • the cycle of the falling phase adjustment operation is longer than the cycle for determining whether or not to execute the rising phase adjustment operation.
  • this is due to the fact that the present inventors have found that the fluctuation of the falling phase accompanying the fluctuation of the power supply voltage is smaller than the fluctuation of the rising phase accompanying the fluctuation of the power supply voltage.
  • phase adjustment circuit 107a1 shown in FIG. 6 is used instead of the phase adjustment circuit 107a shown in FIG. 1, and the phase adjustment control circuit 107b shown in FIG.
  • the phase adjustment control circuit 107b1 is used.
  • FIG. 6 is a diagram showing the phase adjustment circuit 107a1 used in the second embodiment.
  • the phase adjustment circuit 107a1 includes the phase adjustment circuit 107a shown in FIG. 2 in that the signal adjustment circuit 1 performs a rising phase adjustment operation and a signal adjustment circuit 6 and a DCC (Duty correction circuit) circuit 7 are added. And different.
  • the signal adjustment circuit 6 adjusts the phase of the falling edge of the output signal of the signal adjustment circuit 1 so that the phase of the falling edge of the internal clock signal ICLK and the phase of the falling edge of the input / output clock signal LCLK are shifted.
  • a falling phase adjustment operation for setting the phase difference to the predetermined value is executed.
  • the DCC circuit 7 is activated in response to the input of the enable signal ENA2, and compares the phase of the falling edge of the internal clock signal ICLK and the falling edge of the input / output clock signal LCLK by detecting the duty of the replica clock signal RCLK. To do.
  • the DCC circuit 7 does not directly compare the falling edges of the internal clock signal ICLK and the input / output clock signal LCLK, but indirectly compares the falling edges of both clocks based on the duty of the replica clock signal RCLK. Do it.
  • the DCC circuit 7 outputs the comparison result to the signal adjustment circuit 6 and then stops its operation.
  • the signal adjustment circuit 6 adjusts the falling phase of the output clock signal of the signal adjustment circuit 1 according to the comparison result from the DCC circuit 7, so that the falling phase of the internal clock signal ICLK The phase difference between the falling phase of the clock signal LCLK and the predetermined value is set.
  • FIG. 7 is a diagram showing the phase adjustment control circuit 107b1 used in the second embodiment.
  • the same components as those shown in FIG. 7 the same components as those shown in FIG. 7
  • the phase adjustment control circuit 107b1 uses the determination timing control circuit 12a in place of the determination timing control circuit 12 shown in FIG. 3, and the update control circuit 15 is added, so that the phase adjustment control shown in FIG. Different from the circuit 107b.
  • the determination timing control circuit 12a is in an active state while the output signal of the SR latch 11 is active, and is activated every time the internal clock signal ICLK is counted a predetermined number of times.
  • the signal SCLK is output.
  • the predetermined number of times is set so that the output period of the activated comparison timing signal SCLK matches the fluctuation period (for example, several to several hundreds of us) of the power supply voltage.
  • This setting is common to the first embodiment.
  • the time required to count the internal clock signal ICLK a predetermined number of times is an example of a first time.
  • the determination timing control circuit 12a outputs an activated operation instruction signal IS every time the internal clock signal ICLK is counted more than a predetermined number during the active state.
  • the time required to count the internal clock signal ICLK a specific number of times is an example of a second time.
  • the update control circuit 15 is an OR circuit, for example, and outputs an activated enable signal ENA2 upon receiving an activated initial signal INIT or an activated operation instruction signal IS.
  • FIG. 8 is a timing chart for explaining operations of the phase adjustment circuit 107a1 and the phase adjustment control circuit 107b1.
  • signals having the same functions as those shown in FIG. 8 signals having the same functions as those shown in FIG.
  • phase adjustment circuit 107a1 and the phase adjustment control circuit 107b1 will be described focusing on differences from the operation of the first embodiment.
  • the command input circuit 108 When the command input circuit 108 receives the initial signal from the command terminal group 102, the command input circuit 108 outputs the activated initial signal INIT (signal P2 in FIG. 8) to the update control circuits 14 and 15 in the phase adjustment control circuit 107b2.
  • the update control circuit 15 Upon receiving the activated initial signal INIT, the update control circuit 15 outputs the activated enable signal ENA2 (signal P16 in FIG. 8) to the DCC circuit 7.
  • the DCC circuit 7 is activated in response to the input of the activated enable signal ENA2 (signal P16 in FIG. 8), and detects the duty of the replica clock signal RCLK.
  • the DCC circuit 7 outputs the duty detection result (phase comparison result between the falling edge of the internal clock signal ICLK and the falling edge of the input / output clock signal LCLK) to the signal adjustment circuit 6, and then stops the operation. To do.
  • the signal adjustment circuit 6 executes the falling phase adjustment operation (phase P104 in FIG. 8) in accordance with the duty detection result from the DCC circuit 7.
  • the determination timing control circuit 12a when the determination timing control circuit 12a is activated, every time the internal clock signal ICLK is counted a predetermined number of times, the activated comparison timing signal SCLK (signal P5, signal P6, signal P7, signal P8, signal P8 in FIG. P9) is output to the phase detector 13c and the delay circuit 13b, and the activated operation instruction signal IS is output to the update control circuit 15 every time the internal clock signal ICLK is counted a specific number of times.
  • SCLK signal P5, signal P6, signal P7, signal P8, signal P8 in FIG. P9
  • the update control circuit 15 When receiving the activated operation instruction signal IS, the update control circuit 15 outputs the activated enable signal ENA2 (signal P17 in FIG. 8) to the DCC circuit 7.
  • the DCC circuit 7 is activated in response to the input of the activated enable signal ENA2 (signal P17 in FIG. 8), and detects the duty of the clock signal output from the signal adjustment control circuit 1.
  • the DCC circuit 7 outputs the duty detection result to the signal adjustment circuit 6, and then stops the operation.
  • the signal adjustment circuit 6 performs a falling phase adjustment operation (phase P105 in FIG. 8) in accordance with the duty detection result from the DCC circuit 7.
  • the rise timing of the external clock signal CK and the rise timing of the signal DQ output from the data input / output terminal group 104 determined by the rise timing of the input / output clock signal LCLK are likely to be shifted with respect to fluctuations in the power supply voltage. . For example, if the power supply voltage is lowered, the output timing of the signal DQ is delayed.
  • the duty of the input / output clock signal LCLK which fluctuates in accordance with the falling timing of the input / output clock signal LCLK, is the duration of the “H” level of the input / output clock signal LCLK and the “L” of the input / output clock LCLK. Since the “level duration” is similarly affected by fluctuations in the power supply voltage, it is unlikely to be biased to one side.
  • the falling phase adjustment operation for adjusting the duty of the input / output clock signal LCLK is more than the rising phase adjustment operation that affects the output timing of the signal DQ. It is found that it may be performed less frequently.
  • the phase adjustment control circuit 107b1 determines whether or not the rising phase difference is out of the allowable range at the first time interval, and rises up to the phase adjustment circuit 107a1 when the rising phase difference is out of the allowable range. A phase adjustment operation is executed, and the phase adjustment circuit 107a1 is caused to execute a falling phase adjustment operation at a second time interval longer than the first time interval.
  • the cycle of the falling phase adjustment operation is longer than the cycle for determining whether or not to execute the rising phase adjustment operation. Therefore, compared with the case where the falling phase adjustment operation is executed at the same frequency as the determination whether the rising phase adjustment operation is executed, the frequency of the falling phase adjustment operation can be lowered and the current consumption can be suppressed. Become.
  • the phase adjustment control circuit 107b1 outputs the activated enable signal ENA2 to the phase adjustment circuit 107a1 at the second time interval.
  • the phase adjustment circuit 107a1 executes the falling phase adjustment operation when the activated enable signal ENA2 is received.

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Abstract

This output-signal generation device contains the following: a phase adjustment unit that generates an output signal on the basis of an input signal and can perform an adjustment operation that sets the phase difference between the input signal and the output signal to a prescribed value; and a phase-adjustment control unit that makes the phase adjustment unit perform the aforementioned adjustment operation if the aforementioned phase difference falls outside an acceptable range that contains the aforementioned prescribed value.

Description

出力信号生成装置、半導体装置および出力信号生成方法Output signal generation device, semiconductor device, and output signal generation method
　本発明は、出力信号生成装置、半導体装置および出力信号生成方法に関し、特には、入力信号に基づいて出力信号を生成する出力信号生成装置、半導体装置および出力信号生成方法に関する。 The present invention relates to an output signal generation device, a semiconductor device, and an output signal generation method, and more particularly to an output signal generation device, a semiconductor device, and an output signal generation method for generating an output signal based on an input signal.
　パーソナルコンピュータ等のメモリとして、クロック信号に同期した動作を行うシンクロナスメモリが広く使用されている。そして、ＤＤＲ（Double Data Rate）型のシンクロナスメモリでは、出力データを外部クロック信号に対して同期させる必要があるので、外部クロック信号に同期した内部クロック信号を生成するためのＤＬＬ（Delay Locked Loop）回路が搭載されている。 As a memory for personal computers and the like, a synchronous memory that operates in synchronization with a clock signal is widely used. In a DDR (Double Data Rate) type synchronous memory, output data needs to be synchronized with an external clock signal, so that a DLL (Delay Locked Loop for generating an internal clock signal synchronized with the external clock signal is used. ) The circuit is installed.
　ＤＬＬ回路は、外部クロック信号と内部クロック信号の位相差に基づいてカウント値が更新されるカウンタ回路と、カウンタ回路のカウンタ値に基づいて外部クロック信号を遅延させて内部クロック信号を生成するディレイラインと、を有する。 The DLL circuit includes a counter circuit whose count value is updated based on the phase difference between the external clock signal and the internal clock signal, and a delay line that generates the internal clock signal by delaying the external clock signal based on the counter value of the counter circuit. And having.
　該カウンタ値、すなわちディレイラインにおける遅延量は、当該カウンタ値を決定したタイミングにおいてはデータの同期を実現出来る。しかしながら、時間の経過により、特に電源変動によって出力トランジスタの動作電流が変化すると、データ出力のタイミングが変化し、データの同期が崩れてしまう。従って、上記カウンタ値の調整は一度きりで完結ではなく、間欠的に行われることが知られている。 The counter value, that is, the delay amount in the delay line, can realize data synchronization at the timing when the counter value is determined. However, when the operating current of the output transistor changes due to power supply fluctuations as time elapses, the data output timing changes and data synchronization is lost. Therefore, it is known that the adjustment of the counter value is not completed once but intermittently.
　以下、カウンタ回路のカウント値を更新し更新されたカウンタ値に基づいて外部クロック信号を遅延させる動作を、「位相調整動作」と称する。 Hereinafter, the operation of updating the count value of the counter circuit and delaying the external clock signal based on the updated counter value is referred to as “phase adjustment operation”.
　特許文献１には、必要性の低い位相調整動作の実行を抑制することによって消費電力を低減するＤＬＬ回路付き半導体装置が記載されている。特許文献１に記載の半導体装置は、所定以上の加速度で電源電圧が変動したときに、位相調整動作を実行する。 Patent Document 1 describes a semiconductor device with a DLL circuit that reduces power consumption by suppressing execution of a phase adjustment operation with low necessity. The semiconductor device described in Patent Document 1 performs a phase adjustment operation when the power supply voltage fluctuates at a predetermined acceleration or higher.
特開２０１１－６１４５７号公報JP 2011-61457 A
　現在、必要性の低い位相調整動作の実行を抑制することによって位相調整動作に伴う消費電力を低減するための新たな手法が望まれている。 Currently, there is a demand for a new method for reducing the power consumption associated with the phase adjustment operation by suppressing the execution of the phase adjustment operation which is less necessary.
　本発明の出力信号生成装置は、
　入力信号に基づいて出力信号を生成し、また、前記入力信号と前記出力信号との位相差を所定値に設定する調整動作を実行可能な位相調整部と、
　前記位相差が、前記所定値を含む許容範囲から外れている場合に、前記位相調整部に前記調整動作を実行させる位相調整制御部と、を含む。 The output signal generator of the present invention is
An output signal based on the input signal, and a phase adjustment unit capable of executing an adjustment operation for setting a phase difference between the input signal and the output signal to a predetermined value;
A phase adjustment control unit that causes the phase adjustment unit to execute the adjustment operation when the phase difference is out of an allowable range including the predetermined value.
　また、本発明の出力信号生成方法は、
　入力信号に基づいて出力信号を生成し前記入力信号と前記出力信号との位相差を所定値に設定する調整動作を実行可能な位相調整部を含む出力信号生成装置が行う出力信号生成方法であって、
　前記位相差が、前記所定値を含む許容範囲から外れている場合に、前記位相調整部に前記調整動作を実行させる。 Further, the output signal generation method of the present invention includes:
An output signal generation method performed by an output signal generation apparatus including a phase adjustment unit capable of executing an adjustment operation for generating an output signal based on an input signal and setting a phase difference between the input signal and the output signal to a predetermined value. And
When the phase difference is out of an allowable range including the predetermined value, the phase adjustment unit is caused to execute the adjustment operation.
　本発明では、入力信号と出力信号との位相差が許容範囲から外れている場合に、位相調整動作が実行される。このため、入力信号と出力信号との位相差が許容範囲に含まれる場合には、位相調整動作は実施されない。したがって、入力信号と出力信号との位相差が許容範囲に含まれる状況での位相調整動作の実行、つまり、必要性の低い位相調整動作の実行を抑制することが可能になる。 In the present invention, the phase adjustment operation is executed when the phase difference between the input signal and the output signal is out of the allowable range. For this reason, when the phase difference between the input signal and the output signal is included in the allowable range, the phase adjustment operation is not performed. Therefore, it is possible to suppress the execution of the phase adjustment operation in a situation where the phase difference between the input signal and the output signal is within the allowable range, that is, the execution of the phase adjustment operation with low necessity.
本発明の第１実施形態の半導体装置１００を示した図である。1 is a diagram illustrating a semiconductor device 100 according to a first embodiment of the present invention. 位相調整回路１０７ａを示した図である。It is the figure which showed the phase adjustment circuit 107a. 位相調整制御回路１０７ｂを示した図である。It is the figure which showed the phase adjustment control circuit 107b. 検出回路１３の動作例を説明するための図である。6 is a diagram for explaining an operation example of a detection circuit 13; FIG. 位相調整回路１０７ａと位相調整制御回路１０７ｂとの動作を説明するためのタイミングチャートである。4 is a timing chart for explaining operations of a phase adjustment circuit 107a and a phase adjustment control circuit 107b. 第２実施形態で用いられる位相調整回路１０７ａ１を示した図である。It is the figure which showed the phase adjustment circuit 107a1 used in 2nd Embodiment. 第２実施形態で用いられる位相調整制御回路１０７ｂ１を示した図である。It is the figure which showed the phase adjustment control circuit 107b1 used in 2nd Embodiment. 位相調整回路１０７ａ１と位相調整制御回路１０７ｂ１との動作を説明するためのタイミングチャートである。6 is a timing chart for explaining operations of the phase adjustment circuit 107a1 and the phase adjustment control circuit 107b1.
　以下、本発明の実施形態について図面を参照して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（第１実施形態）
　図１は、本発明の第１実施形態の半導体装置１００を示した図である。本実施形態では、半導体装置１００として、ＲＡＭ（Random Access Memory）が用いられる。 (First embodiment)
FIG. 1 is a diagram showing a semiconductor device 100 according to the first embodiment of the present invention. In the present embodiment, a RAM (Random Access Memory) is used as the semiconductor device 100.
　半導体装置１００は、外部端子として、クロック端子群１０１と、コマンド端子群１０２と、アドレス端子群１０３と、データ入出力端子群１０４と、電源端子群１０５と、を含む。 The semiconductor device 100 includes a clock terminal group 101, a command terminal group 102, an address terminal group 103, a data input / output terminal group 104, and a power supply terminal group 105 as external terminals.
　また、半導体装置１００は、クロック入力回路１０６と、入出力用クロック生成部１０７と、コマンド入力回路１０８と、コマンドデコード回路１０９と、リフレッシュ制御回路１１０と、アドレス入力回路１１１と、アドレスラッチ回路１１２と、モードレジスタ１１３と、メモリセルアレイ１１４と、ロウデコーダ１１５と、カラムデコーダ１１６と、ＦＩＦＯ（First-In First-Out）回路１１７と、入出力回路１１８と、内部電源発生回路１１９と、を含む。 Further, the semiconductor device 100 includes a clock input circuit 106, an input / output clock generation unit 107, a command input circuit 108, a command decode circuit 109, a refresh control circuit 110, an address input circuit 111, and an address latch circuit 112. A mode register 113, a memory cell array 114, a row decoder 115, a column decoder 116, a first-in / first-out (FIFO) circuit 117, an input / output circuit 118, and an internal power generation circuit 119. .
　クロック端子群１０１は、外部クロック信号ＣＫおよび／ＣＫを受け付ける。 The clock terminal group 101 receives external clock signals CK and / CK.
　なお、本明細書において信号名の先頭に「／」が付されている信号は、対応する信号の反転信号またはローアクティブな信号であることを意味する。したがって、外部クロック信号ＣＫと外部クロック信号／ＣＫとは互いに相補の信号である。 In this specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, external clock signal CK and external clock signal / CK are complementary signals.
　クロック入力回路１０６は、クロック端子群１０１から外部クロック信号ＣＫおよび／ＣＫを受け付け、外部クロック信号ＣＫおよび／ＣＫを用いて、外部クロック信号ＣＫおよび／ＣＫに同期した内部クロック信号ＩＣＬＫを生成する。クロック入力回路１０６は、内部クロック信号ＩＣＬＫを、入出力用クロック生成部１０７に出力する。 The clock input circuit 106 receives the external clock signals CK and / CK from the clock terminal group 101, and generates the internal clock signal ICLK synchronized with the external clock signals CK and / CK using the external clock signals CK and / CK. The clock input circuit 106 outputs the internal clock signal ICLK to the input / output clock generation unit 107.
　入出力用クロック生成部１０７は、本発明の一実施形態の出力信号生成装置の一例である。 The input / output clock generation unit 107 is an example of an output signal generation apparatus according to an embodiment of the present invention.
　入出力用クロック生成部１０７は、内部クロック信号ＩＣＬＫの位相を調整することによって、入出力用クロック信号ＬＣＬＫを生成する。内部クロック信号ＩＣＬＫは、入力信号の一例であり、入出力用クロック信号ＬＣＬＫは、出力信号の一例である。 The input / output clock generation unit 107 generates the input / output clock signal LCLK by adjusting the phase of the internal clock signal ICLK. The internal clock signal ICLK is an example of an input signal, and the input / output clock signal LCLK is an example of an output signal.
　入出力用クロック生成部１０７は、位相調整回路１０７ａと、位相調整制御回路１０７ｂと、を含む。 The input / output clock generator 107 includes a phase adjustment circuit 107a and a phase adjustment control circuit 107b.
　位相調整回路１０７ａは、位相調整部の一例であり、例えばＤＬＬ回路である。位相調整回路１０７ａは、内部クロック信号ＩＣＬＫに基づいて入出力用クロック信号ＬＣＬＫを生成する。また、位相調整回路１０７ａは、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差を所定値に設定する位相調整動作を実行可能である。 The phase adjustment circuit 107a is an example of a phase adjustment unit, for example, a DLL circuit. The phase adjustment circuit 107a generates an input / output clock signal LCLK based on the internal clock signal ICLK. Further, the phase adjustment circuit 107a can execute a phase adjustment operation for setting the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK to a predetermined value.
　位相調整制御回路１０７ｂは、位相調整制御部の一例であり、位相調整回路１０７ａが位相調整動作を実行する調整タイミングを決定する。 The phase adjustment control circuit 107b is an example of a phase adjustment control unit, and determines the adjustment timing at which the phase adjustment circuit 107a executes the phase adjustment operation.
　本実施形態では、位相調整制御回路１０７ｂでの調整タイミングの決定動作に特徴がある。なお、位相調整制御回路１０７ｂでの調整タイミングの決定動作については後述する。 This embodiment is characterized by the operation of determining the adjustment timing in the phase adjustment control circuit 107b. The operation of determining the adjustment timing in the phase adjustment control circuit 107b will be described later.
　位相調整制御回路１０７ｂは、その調整タイミングで、イネーブル信号ＥＮＡを位相調整回路１０７ａに出力する。イネーブル信号ＥＮＡは、調整用信号の一例である。位相調整回路１０７ａは、イネーブル信号ＥＮＡを受け付けると、位相調整動作を実行する。 The phase adjustment control circuit 107b outputs an enable signal ENA to the phase adjustment circuit 107a at the adjustment timing. The enable signal ENA is an example of an adjustment signal. When receiving the enable signal ENA, the phase adjustment circuit 107a performs a phase adjustment operation.
　位相調整回路１０７ａにて生成された入出力用クロック信号ＬＣＬＫは、ＦＩＦＯ回路１１７および入出力回路１１８に供給される。ＦＩＦＯ回路１１７および入出力回路１１８については後述する。 The input / output clock signal LCLK generated by the phase adjustment circuit 107a is supplied to the FIFO circuit 117 and the input / output circuit 118. The FIFO circuit 117 and the input / output circuit 118 will be described later.
　コマンド端子群１０２は、コマンド信号を受け付ける。コマンド信号は、例えば、ロウアドレスストローブ信号／ＲＡＳ、カラムアドレスストローブ信号／ＣＡＳ、および、リセット信号／ＲＥＳＥＴなどである。 The command terminal group 102 receives a command signal. The command signals are, for example, a row address strobe signal / RAS, a column address strobe signal / CAS, and a reset signal / RESET.
　コマンド入力回路１０８は、コマンド端子群１０２からコマンド信号を受け付け、コマンド信号をコマンドデコード回路１０９に出力する。また、コマンド入力回路１０８は、リセット信号ＲＥＳＥＴを位相調整回路１０７ａと位相調整制御回路１０７ｂとに出力し、イニシャル（初期化）信号ＩＮＩＴを位相調整制御回路１０７ｂに出力する。 The command input circuit 108 receives a command signal from the command terminal group 102 and outputs the command signal to the command decode circuit 109. The command input circuit 108 outputs a reset signal RESET to the phase adjustment circuit 107a and the phase adjustment control circuit 107b, and outputs an initial (initialization) signal INIT to the phase adjustment control circuit 107b.
　コマンドデコード回路１０９は、コマンド信号を受け付ける。コマンドデコード回路１０９は、コマンド信号の保持、コマンド信号のデコード、および、コマンド信号のカウントなどを行うことによって、内部コマンド信号を生成する。コマンドデコード回路１０９は、内部コマンド信号として、例えば、リフレッシュコマンド、書込みコマンド、および、読出しコマンドを生成する。 The command decode circuit 109 receives a command signal. The command decode circuit 109 generates an internal command signal by holding the command signal, decoding the command signal, counting the command signal, and the like. The command decode circuit 109 generates, for example, a refresh command, a write command, and a read command as internal command signals.
　リフレッシュ制御回路１１０は、コマンドデコード回路１０９からリフレッシュコマンドを受け付ける。リフレッシュ制御回路１１０は、リフレッシュコマンドを受け付けると、ロウデコーダ１１５にリフレッシュ信号を供給する。 The refresh control circuit 110 receives a refresh command from the command decode circuit 109. When the refresh control circuit 110 receives a refresh command, the refresh control circuit 110 supplies a refresh signal to the row decoder 115.
　アドレス端子群１０３は、アドレス信号を受け付ける。 The address terminal group 103 receives an address signal.
　アドレス入力回路１１１は、アドレス端子群１０３からアドレス信号を受け付け、アドレス信号をアドレスラッチ回路１１２に出力する。 The address input circuit 111 receives an address signal from the address terminal group 103 and outputs the address signal to the address latch circuit 112.
　アドレスラッチ回路１１２は、アドレス入力回路１１１からアドレス信号を受け付ける。アドレスラッチ回路１１２は、モードレジスタ１１３をセットする場合には、アドレス信号を、モードレジスタ１１３に出力する。また、アドレスラッチ回路１１２は、アドレス信号のうちロウアドレスをロウデコーダ１１５に出力し、アドレス信号のうちカラムアドレスをカラムデコーダ１１６に出力する。 The address latch circuit 112 receives an address signal from the address input circuit 111. The address latch circuit 112 outputs an address signal to the mode register 113 when setting the mode register 113. The address latch circuit 112 outputs a row address of the address signal to the row decoder 115 and outputs a column address of the address signal to the column decoder 116.
　モードレジスタ１１３は、半導体装置１００の動作パラメータ（例えば、バースト長またはＣＡＳレイテンシ）が設定されるレジスタである。モードレジスタ１１３は、コマンドデコード回路１０９からの内部コマンド信号と、アドレスラッチ回路１１２からのアドレス信号と、を受け付け、内部コマンド信号とアドレス信号とに基づいて特定される動作パラメータを設定する。 The mode register 113 is a register in which operation parameters (for example, burst length or CAS latency) of the semiconductor device 100 are set. The mode register 113 receives the internal command signal from the command decode circuit 109 and the address signal from the address latch circuit 112, and sets an operation parameter specified based on the internal command signal and the address signal.
　メモリセルアレイ１１４は、複数のワード線ＷＬと、複数のビット線ＢＬと、複数のメモリセルＭＣと、を含む。各メモリセルＭＣは、ワード線ＷＬとビット線ＢＬにて特定される。 The memory cell array 114 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC. Each memory cell MC is specified by a word line WL and a bit line BL.
　ロウデコーダ１１５は、アドレスラッチ回路１１２からのロウアドレスと、コマンドデコード回路１０９からの書込みコマンドまたは読出しコマンドと、を受け付ける。また、ロウデコーダ１１５は、リフレッシュ制御回路１１０から、リフレッシュ信号を受け付ける。 The row decoder 115 receives a row address from the address latch circuit 112 and a write command or a read command from the command decode circuit 109. In addition, the row decoder 115 receives a refresh signal from the refresh control circuit 110.
　ロウデコーダ１１５は、書込みコマンドまたは読出しコマンドを受け付けると、メモリセルアレイ１１４内の複数のワード線ＷＬの中から、ロウアドレスに応じたワード線ＷＬを選択する。 When the row decoder 115 receives a write command or a read command, the row decoder 115 selects a word line WL corresponding to the row address from the plurality of word lines WL in the memory cell array 114.
　メモリセルアレイ１１４内では、複数のワード線ＷＬと複数のビット線ＢＬが交差しており、その交点には、メモリセルＭＣが配置されている。なお、図１では、説明の簡略化のため、１本のワード線ＷＬと１本のビット線ＢＬと１個のメモリセルＭＣのみが示されている。ビット線ＢＬは、それぞれ、自ビット線ＢＬに対応するセンスアンプ（不図示）に接続されている。 In the memory cell array 114, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections. In FIG. 1, only one word line WL, one bit line BL, and one memory cell MC are shown for simplicity of explanation. Each bit line BL is connected to a sense amplifier (not shown) corresponding to its own bit line BL.
　また、ロウデコーダ１１５は、リフレッシュ信号を受け付けると、複数のワード線ＷＬの中から、ロウアドレスに応じたワード線ＷＬを選択し、選択されたワード線ＷＬに対応するメモリセルＭＣをリフレッシュするセルフリフレッシュを実行する。 When the row decoder 115 receives the refresh signal, the row decoder 115 selects the word line WL corresponding to the row address from the plurality of word lines WL, and refreshes the memory cells MC corresponding to the selected word line WL. Perform a refresh.
　カラムデコーダ１１６は、アドレスラッチ回路１１２からのカラムアドレスと、コマンドデコード回路１０９からの書込みコマンドまたは読出しコマンドと、を受け付ける。 The column decoder 116 receives the column address from the address latch circuit 112 and the write command or read command from the command decode circuit 109.
　カラムデコーダ１１６は、カラムアドレスと、書込みコマンドまたは読出しコマンドと、を受け付けると、複数のセンスアンプの中から、カラムアドレスに応じたセンスアンプを選択する。 When the column decoder 116 receives the column address and the write command or the read command, the column decoder 116 selects a sense amplifier corresponding to the column address from the plurality of sense amplifiers.
　読出し動作時（読出しコマンド発生時）には、カラムデコーダ１１６にて選択されたセンスアンプと接続するビット線ＢＬと、ロウデコーダ１１５にて選択されたワード線ＷＬと、の交点に存在するメモリセルＭＣ（以下「選択メモリセル」と称する）内のデータ（リードデータ）は、カラムデコーダ１１６にて選択されたセンスアンプにて増幅され、ＦＩＦＯ回路１１７に供給され、その後、入出力回路１１８に供給される。一方、書込み動作時（書込みコマンド発生時）には、カラムデコーダ１１６にて選択されたセンスアンプは、ＦＩＦＯ回路１１７からのライトデータを選択メモリセルに書き込む。 During a read operation (when a read command is generated), a memory cell present at the intersection of the bit line BL connected to the sense amplifier selected by the column decoder 116 and the word line WL selected by the row decoder 115 Data (read data) in the MC (hereinafter referred to as “selected memory cell”) is amplified by the sense amplifier selected by the column decoder 116, supplied to the FIFO circuit 117, and then supplied to the input / output circuit 118. Is done. On the other hand, during a write operation (when a write command is generated), the sense amplifier selected by the column decoder 116 writes the write data from the FIFO circuit 117 to the selected memory cell.
　ＦＩＦＯ回路１１７は、位相調整回路１０７ａから入出力用クロック信号ＬＣＬＫを受け付け、入出力用クロック信号ＬＣＬＫに同期して、メモリセルアレイ１１４と入出力回路１１８との間で、リードデータとライトデータのやり取りを行う。 The FIFO circuit 117 receives the input / output clock signal LCLK from the phase adjustment circuit 107a, and exchanges read data and write data between the memory cell array 114 and the input / output circuit 118 in synchronization with the input / output clock signal LCLK. I do.
　データ入出力端子群１０４は、リードデータの出力と、ライトデータの入力と、を行う。データ入出力端子群１０４は、入出力回路１１８に接続されている。 The data input / output terminal group 104 performs read data output and write data input. The data input / output terminal group 104 is connected to the input / output circuit 118.
　入出力回路１１８は、位相調整回路１０７ａから入出力用クロック信号ＬＣＬＫを受け付け、リード動作時においては入出力用クロック信号ＬＣＬＫに同期してリードデータをデータ入出力端子群１０４に出力する。 The input / output circuit 118 receives the input / output clock signal LCLK from the phase adjustment circuit 107a, and outputs read data to the data input / output terminal group 104 in synchronization with the input / output clock signal LCLK during the read operation.
　電源端子群１０５は、電源電圧の高電位側の電圧ＶＤＤと、電源電圧の低電位側の電圧ＶＳＳと、を受け付ける。 The power supply terminal group 105 receives the voltage VDD on the high potential side of the power supply voltage and the voltage VSS on the low potential side of the power supply voltage.
　内部電源発生回路１１９は、電源端子群１０５から電圧ＶＤＤおよび電圧ＶＳＳを受け付け、電圧ＶＰＰ、電圧ＶＰＥＲＩ、電圧ＶＰＥＲＤ等の内部電源電圧を発生する。なお、電圧ＶＤＤおよび電圧ＶＳＳは、位相調整制御回路１０７ｂとＦＩＦＯ回路１１７と入出力回路１１８にも供給される。 The internal power supply generation circuit 119 receives the voltage VDD and the voltage VSS from the power supply terminal group 105 and generates internal power supply voltages such as the voltage VPP, the voltage VPERI, and the voltage VPERR. Note that the voltage VDD and the voltage VSS are also supplied to the phase adjustment control circuit 107b, the FIFO circuit 117, and the input / output circuit 118.
　次に、位相調整回路１０７ａについて説明する。 Next, the phase adjustment circuit 107a will be described.
　図２は、位相調整回路１０７ａを示した図である。図２において、位相調整回路１０７ａは、信号調整回路１と、レプリカ回路２と、位相比較回路３と、更新タイミング発生回路４と、カウンタ回路５と、を含む。 FIG. 2 is a diagram showing the phase adjustment circuit 107a. In FIG. 2, the phase adjustment circuit 107 a includes a signal adjustment circuit 1, a replica circuit 2, a phase comparison circuit 3, an update timing generation circuit 4, and a counter circuit 5.
　信号調整回路１は、例えば、ディレイラインであり、内部クロック信号ＩＣＬＫを遅延させることによって入出力用クロック信号ＬＣＬＫを生成する。信号調整回路１には、電圧ＶＰＥＲＤが供給される。 The signal adjustment circuit 1 is, for example, a delay line, and generates the input / output clock signal LCLK by delaying the internal clock signal ICLK. A voltage VPERD is supplied to the signal adjustment circuit 1.
　特に限定されるものではないが、信号調整回路１は、相対的に粗い調整ピッチで内部クロック信号ＩＣＬＫを遅延させるコースディレイラインと、相対的に細かい調整ピッチで内部クロック信号ＩＣＬＫを遅延させるファインディレイラインを含むことが好ましい。 Although not particularly limited, the signal adjustment circuit 1 includes a coarse delay line that delays the internal clock signal ICLK with a relatively coarse adjustment pitch, and a fine delay that delays the internal clock signal ICLK with a relatively fine adjustment pitch. It is preferable to include a line.
　入出力用クロック信号ＬＣＬＫは、図１に示したＦＩＦＯ回路１１７および入出力回路１１８と、レプリカ回路２に供給される。 The input / output clock signal LCLK is supplied to the FIFO circuit 117 and the input / output circuit 118 and the replica circuit 2 shown in FIG.
　レプリカ回路２は、信号調整回路１から出力端子群１０４までの実際の信号ルート（以下、単に「信号ルート」と称する）による遅延量と等価の遅延量を有する回路である。主には入出力回路１１８に含まれる出力バッファである。 The replica circuit 2 is a circuit having a delay amount equivalent to a delay amount due to an actual signal route from the signal adjustment circuit 1 to the output terminal group 104 (hereinafter simply referred to as “signal route”). An output buffer included in the input / output circuit 118 is mainly used.
　レプリカ回路２は、入出力用クロック信号ＬＣＬＫを信号ルートによる遅延量だけ遅延したレプリカクロック信号ＲＣＬＫを出力する。これにより、レプリカクロック信号ＲＣＬＫの位相は、データ入出力端子群１０４から出力される信号の位相と実質的に一致する。 The replica circuit 2 outputs a replica clock signal RCLK obtained by delaying the input / output clock signal LCLK by a delay amount by a signal route. As a result, the phase of the replica clock signal RCLK substantially matches the phase of the signal output from the data input / output terminal group 104.
　位相比較回路３は、イネーブル信号ＥＮＡの入力に伴い起動し、ロック信号ＬＯＣＫの入力に伴い動作を停止する。 The phase comparison circuit 3 starts when the enable signal ENA is input, and stops operating when the lock signal LOCK is input.
　ロック信号ＬＯＣＫは、内部クロック信号ＩＣＬＫの位相とレプリカクロック信号ＲＣＬＫの位相が一致した際に、カウンタ回路５から出力される。 The lock signal LOCK is output from the counter circuit 5 when the phase of the internal clock signal ICLK matches the phase of the replica clock signal RCLK.
　位相比較回路３は、起動すると、内部クロック信号ＩＣＬＫとレプリカクロック信号ＲＣＬＫとの位相差を検出する。 When the phase comparison circuit 3 is activated, it detects the phase difference between the internal clock signal ICLK and the replica clock signal RCLK.
　上述の通り、レプリカクロック信号ＲＣＬＫの位相は、データ入出力端子群１０４からの出力信号の位相と一致するよう、信号調整回路１によって調整される。しかしながら、電圧や温度など信号調整回路１の遅延量に影響を与えるパラメータの変動や、内部クロック信号ＩＣＬＫ自体の周波数変動などによって、両者の位相は刻々と変化する。 As described above, the phase of the replica clock signal RCLK is adjusted by the signal adjustment circuit 1 so as to match the phase of the output signal from the data input / output terminal group 104. However, the phase of both changes momentarily due to fluctuations in parameters such as voltage and temperature which affect the delay amount of the signal adjustment circuit 1 and fluctuations in the frequency of the internal clock signal ICLK itself.
　位相比較回路３はこのような変化を検出し、内部クロック信号ＩＣＬＫに対してレプリカクロック信号ＲＣＬＫが進んでいるかあるいは遅れているかを判定する。この判定は、位相比較回路３が動作している間、内部クロック信号ＩＣＬＫの周期ごとに行われる。 The phase comparison circuit 3 detects such a change and determines whether the replica clock signal RCLK is advanced or delayed with respect to the internal clock signal ICLK. This determination is performed for each cycle of the internal clock signal ICLK while the phase comparison circuit 3 is operating.
　この判定結果は、位相判定信号ＵＤとしてカウンタ回路５に供給される。例えば、内部クロック信号ＩＣＬＫに対してレプリカクロック信号ＲＣＬＫが進んでいる場合には、位相判定信号ＵＤが“Ｈ”となり、内部クロック信号ＩＣＬＫに対してレプリカクロック信号ＲＣＬＫが遅れている場合には、位相判定信号ＵＤが“Ｌ”となる。 The determination result is supplied to the counter circuit 5 as the phase determination signal UD. For example, when the replica clock signal RCLK is advanced with respect to the internal clock signal ICLK, the phase determination signal UD is “H”, and when the replica clock signal RCLK is delayed with respect to the internal clock signal ICLK, The phase determination signal UD becomes “L”.
　更新タイミング発生回路４は、位相比較回路３と同様に、イネーブル信号ＥＮＡの入力に伴い起動し、ロック信号ＬＯＣＫの入力に伴い動作を停止する。 The update timing generation circuit 4 is activated in response to the input of the enable signal ENA and stops operating in response to the input of the lock signal LOCK, as in the phase comparison circuit 3.
　更新タイミング発生回路４は、起動すると、内部クロック信号ＩＣＬＫを分周することにより、ワンショットパルスであるカウントタイミング信号Ｃｏｕｎｔ＿ｔｉｍｉｎｇを生成する。カウントタイミング信号Ｃｏｕｎｔ＿ｔｉｍｉｎｇは、カウンタ回路５に出力され、カウンタ回路５のカウント値を更新するタイミングを示す同期信号として用いられる。したがって、カウントタイミング信号Ｃｏｕｎｔ＿ｔｉｍｉｎｇの活性化周期は、位相調整回路１０７ａのサンプリング周期として定義される。 When activated, the update timing generation circuit 4 divides the internal clock signal ICLK to generate a count timing signal Count_timing that is a one-shot pulse. The count timing signal Count_timing is output to the counter circuit 5 and is used as a synchronization signal indicating the timing at which the count value of the counter circuit 5 is updated. Therefore, the activation cycle of the count timing signal Count_timing is defined as the sampling cycle of the phase adjustment circuit 107a.
　カウンタ回路５は、イネーブル信号ＥＮＡの入力に伴い起動し、ロック信号ＬＯＣＫの出力に伴い動作を停止する。 The counter circuit 5 starts when the enable signal ENA is input and stops operating when the lock signal LOCK is output.
　カウンタ回路５は、動作中、信号調整回路１の遅延量を設定する。 The counter circuit 5 sets the delay amount of the signal adjustment circuit 1 during operation.
　カウンタ回路５は、カウントタイミング信号Ｃｏｕｎｔ＿ｔｉｍｉｎｇに同期して、そのカウント値が更新される。カウント値の増減は、位相比較回路３から供給される位相判定信号ＵＤに基づいて定められる。 The counter circuit 5 updates the count value in synchronization with the count timing signal Count_timing. The increase / decrease of the count value is determined based on the phase determination signal UD supplied from the phase comparison circuit 3.
　本実施形態では、位相判定信号ＵＤが“Ｈ”である場合、カウンタ回路５はカウントタイミング信号Ｃｏｕｎｔ＿ｔｉｍｉｎｇに同期してそのカウント値をアップカウントし、これにより、信号調整回路１の遅延量を増大させる。逆に、位相判定信号ＵＰが“Ｌ”である場合、カウンタ回路５はカウントタイミング信号Ｃｏｕｎｔ＿ｔｉｍｉｎｇに同期してそのカウント値をダウンカウントし、これにより、信号調整回路１の遅延量を減少させる。 In the present embodiment, when the phase determination signal UD is “H”, the counter circuit 5 up-counts the count value in synchronization with the count timing signal Count_timing, thereby increasing the delay amount of the signal adjustment circuit 1. . Conversely, when the phase determination signal UP is “L”, the counter circuit 5 counts down the count value in synchronization with the count timing signal Count_timing, thereby reducing the delay amount of the signal adjustment circuit 1.
　カウンタ回路５は、ダウンカウントとアップカウントを交互に所定回数（例えば２回）繰り返すと、内部クロック信号ＩＣＬＫの位相とレプリカクロック信号ＲＣＬＫの位相とが一致したと判定し、その時のカウント値を保持しつつ、活性化したロック信号ＬＯＣＫを出力し、その後動作を停止する。なお、カウンタ回路５は動作停止中もカウント値を保持する。 The counter circuit 5 determines that the phase of the internal clock signal ICLK and the phase of the replica clock signal RCLK coincide with each other when the down count and the up count are alternately repeated a predetermined number of times (for example, twice), and holds the count value at that time However, the activated lock signal LOCK is output, and then the operation is stopped. Note that the counter circuit 5 holds the count value even when the operation is stopped.
　また、カウンタ回路５にはリセット信号ＲＥＳＥＴも供給される。リセット信号ＲＥＳＥＴが活性化すると、カウンタ回路５は、カウント値をプリセット値に初期化する。 Also, the counter circuit 5 is supplied with a reset signal RESET. When the reset signal RESET is activated, the counter circuit 5 initializes the count value to a preset value.
　次に、位相調整制御回路１０７ｂについて説明する。 Next, the phase adjustment control circuit 107b will be described.
　図３は、位相調整回路１０７ａでの位相調整動作の動作タイミングを制御する位相調整制御回路１０７ｂを示した図である。図３において、位相調整制御回路１０７ｂは、ＳＲラッチ１１と、判定タイミング制御回路１２と、検出回路１３と、更新制御回路１４と、を含む。検出回路１３は、遅延回路１３ａおよび１３ｂと、位相検知部１３ｃおよび１３ｄと、ＯＲ回路１３ｅと、を含む。 FIG. 3 is a diagram showing the phase adjustment control circuit 107b that controls the operation timing of the phase adjustment operation in the phase adjustment circuit 107a. In FIG. 3, the phase adjustment control circuit 107 b includes an SR latch 11, a determination timing control circuit 12, a detection circuit 13, and an update control circuit 14. Detection circuit 13 includes delay circuits 13a and 13b, phase detection units 13c and 13d, and an OR circuit 13e.
　まず、位相調整制御回路１０７ｂの概要を説明する。 First, an outline of the phase adjustment control circuit 107b will be described.
　位相調整制御回路１０７ｂでは、検出回路１３が、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が、特定値を含む許容範囲から外れていることを検出すると、更新制御回路１４は、活性化したイネーブル信号ＥＮＡを位相調整回路１０７ａに出力し、位相調整回路１０７ａに位相調整動作を実行させる。 In the phase adjustment control circuit 107b, when the detection circuit 13 detects that the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range including the specific value, the update control circuit 14 The activated enable signal ENA is output to the phase adjustment circuit 107a to cause the phase adjustment circuit 107a to execute the phase adjustment operation.
　なお、特定値は、内部クロック信号ＩＣＬＫの位相とレプリカクロック信号ＲＣＬＫの位相が一致した状況における、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差の値である。 The specific value is a value of a phase difference between the internal clock signal ICLK and the input / output clock signal LCLK in a situation where the phase of the internal clock signal ICLK and the phase of the replica clock signal RCLK match.
　このため、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が許容範囲から外れていない場合、つまり、その位相差が、位相調整動作を実行する必要がない程度の位相差である場合には、位相調整制御回路１０７ｂは、位相調整動作を実行させずに、位相調整動作に伴う電流消費を抑制する。 For this reason, when the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is not out of the allowable range, that is, when the phase difference is such that it is not necessary to perform the phase adjustment operation. In other words, the phase adjustment control circuit 107b suppresses current consumption associated with the phase adjustment operation without executing the phase adjustment operation.
　次に、位相調整制御回路１０７ｂ内の各構成について説明する。 Next, each component in the phase adjustment control circuit 107b will be described.
　ＳＲラッチ１１と判定タイミング制御回路１２とは、協同して、検出回路１３の検出タイミングを決定する活性化した比較タイミング信号ＳＣＬＫを出力する。 The SR latch 11 and the determination timing control circuit 12 cooperate to output an activated comparison timing signal SCLK that determines the detection timing of the detection circuit 13.
　具体的には、ＳＲラッチ１１は、ロック信号ＬＯＣＫをセット端子Ｓで受け付け、リセット信号ＲＥＳＥＴをリセット端子Ｒで受け付ける。このため、ＳＲラッチ１１は、ロック信号ＬＯＣＫが活性化（“Ｈ”）すると、出力端子Ｑからの出力信号が活性化（“Ｈ”）し、リセット信号ＲＥＳＥＴが活性化（“Ｈ”）すると、出力端子Ｑからの出力信号が非活性化（“Ｌ”）する。 Specifically, the SR latch 11 receives the lock signal LOCK at the set terminal S and receives the reset signal RESET at the reset terminal R. Therefore, the SR latch 11 activates (“H”) the output signal from the output terminal Q when the lock signal LOCK is activated (“H”), and activates (“H”) the reset signal RESET. The output signal from the output terminal Q is deactivated (“L”).
　判定タイミング制御回路１２は、ＳＲラッチ１１の出力信号が活性化している間、活性状態となる。判定タイミング制御回路１２は、活性状態の間、内部クロック信号ＩＣＬＫを所定回数カウントするごとに、活性化した比較タイミング信号ＳＣＬＫを出力する。 The determination timing control circuit 12 is activated while the output signal of the SR latch 11 is activated. The determination timing control circuit 12 outputs the activated comparison timing signal SCLK every time the internal clock signal ICLK is counted a predetermined number of times during the active state.
　このため、活性化した比較タイミング信号ＳＣＬＫの立ち上がりタイミングは、内部クロック信号ＩＣＬＫの立ち上がりタイミングのいずれかとほぼ同時に生じる。 Therefore, the rising timing of the activated comparison timing signal SCLK occurs almost simultaneously with any of the rising timings of the internal clock signal ICLK.
　活性化した比較タイミング信号ＳＣＬＫは、検出回路１３（具体的には、位相検知部１３ｃと遅延回路１３ｂ）に供給される。 The activated comparison timing signal SCLK is supplied to the detection circuit 13 (specifically, the phase detection unit 13c and the delay circuit 13b).
　検出回路１３は、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が、特定値を含む許容範囲から外れているか否かを検出する。 The detection circuit 13 detects whether or not the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range including the specific value.
　本実施形態では、許容範囲として、「特定値－α」よりも大きく「特定値＋α」よりも小さい範囲が用いられる。 In the present embodiment, as the allowable range, a range larger than “specific value−α” and smaller than “specific value + α” is used.
　まず、検出回路１３の概要を説明する。 First, the outline of the detection circuit 13 will be described.
　検出回路１３では、遅延回路１３ａと位相検知部１３ｃとは、協同して、レプリカクロック信号ＲＣＬＫの位相が、内部クロック信号ＩＣＬＫの位相と比べて時間α以上進んでいるか（早いか）否かを検知する。一方、遅延回路１３ｂと位相検知部１３ｄとは、協同して、レプリカクロック信号ＲＣＬＫの位相が、内部クロック信号ＩＣＬＫの位相と比べて時間α以上遅れているか否かを検知する。 In the detection circuit 13, the delay circuit 13a and the phase detection unit 13c cooperate to determine whether the phase of the replica clock signal RCLK is advanced (earlier) by the time α or more than the phase of the internal clock signal ICLK. Detect. On the other hand, the delay circuit 13b and the phase detector 13d cooperate to detect whether or not the phase of the replica clock signal RCLK is delayed by a time α or more compared to the phase of the internal clock signal ICLK.
　次に、検出回路１３の各構成について説明する。 Next, each configuration of the detection circuit 13 will be described.
　遅延回路１３ａは、レプリカクロック信号ＲＣＬＫを遅延時間αだけ遅らせる。 The delay circuit 13a delays the replica clock signal RCLK by the delay time α.
　遅延回路１３ｂは、活性化した比較タイミング信号ＳＣＬＫを遅延時間αだけ遅らせる。 The delay circuit 13b delays the activated comparison timing signal SCLK by the delay time α.
　位相検知部１３ｃは、活性化した比較タイミング信号ＳＣＬＫの立ち上がりタイミングで、遅延回路１３ａの出力信号（遅延時間αだけ遅延したレプリカクロック信号ＲＣＬＫ）のレベルを検出する。図４のＲＣＬＫ（Ｃ＝Ａ：Ｈ）に示すように、レプリカクロック信号ＲＣＬＫの位相が、内部クロック信号ＩＣＬＫの位相よりも時間α以上早い場合には、検出されるレベルは“Ｈ”となり、それ以外は“Ｌ”となる。その論理レベルがそのままＣ点のレベルとして出力される。 The phase detector 13c detects the level of the output signal of the delay circuit 13a (the replica clock signal RCLK delayed by the delay time α) at the rising timing of the activated comparison timing signal SCLK. As shown in RCLK (C = A: H) in FIG. 4, when the phase of the replica clock signal RCLK is earlier than the phase of the internal clock signal ICLK by a time α or more, the detected level is “H”. Otherwise, it is “L”. The logic level is output as it is as the C point level.
　位相検知部１３ｄは、遅延回路１３ｂにて遅延時間αだけ遅延された、活性化した比較タイミング信号ＳＣＬＫの立ち上がりタイミングで、レプリカクロック信号ＲＣＬＫのレベルを検出する。図４のＲＣＬＫ（Ｂ＝Ａ：Ｈ）に示すように、レプリカクロック信号ＲＣＬＫの位相が、内部クロック信号ＩＣＬＫの位相よりも時間α以上遅い場合には、検出されるレベルは“Ｌ”となり、それ以外に“Ｈ”となる。その論理レベルが反転されてＢ点のレベルとして出力される。 The phase detector 13d detects the level of the replica clock signal RCLK at the rising timing of the activated comparison timing signal SCLK delayed by the delay time α by the delay circuit 13b. As shown in RCLK (B = A: H) in FIG. 4, when the phase of the replica clock signal RCLK is later than the phase of the internal clock signal ICLK by a time α or more, the detected level becomes “L”. Otherwise, it is “H”. The logic level is inverted and output as the level of point B.
　ＯＲ回路１３ｅは、Ｂ点、Ｃ点のレベルをそれぞれ受けてＯＲ論理演算結果を、更新制御回路１４に出力する。即ち、レプリカクロック信号ＲＣＬＫの位相が、内部クロック信号ＩＣＬＫの位相よりも時間α以上早い場合又は遅い場合にＯＲ回路１３ｅの出力信号は活性化（Ｈ）され、時間±αの範囲内に収まっている場合に非活性化（Ｌ）される。 OR circuit 13e receives the levels of points B and C, respectively, and outputs an OR logic operation result to update control circuit 14. That is, when the phase of the replica clock signal RCLK is earlier or later than the phase of the internal clock signal ICLK by the time α, the output signal of the OR circuit 13e is activated (H) and falls within the range of time ± α. Is deactivated (L).
　図３に示した更新制御回路１４は、例えばＯＲ回路であり、イニシャル信号ＩＮＩＴ、または、ＯＲ回路１３ｅの活性化した出力信号（“Ｈ”）を受け付けると、活性化したイネーブル信号ＥＮＡを出力する。 The update control circuit 14 shown in FIG. 3 is an OR circuit, for example, and outputs an activated enable signal ENA when receiving an initial signal INIT or an output signal (“H”) activated by the OR circuit 13e. .
　次に、動作を説明する。 Next, the operation will be described.
　図５は、位相調整回路１０７ａと位相調整制御回路１０７ｂとの動作を説明するためのタイミングチャートである。 FIG. 5 is a timing chart for explaining operations of the phase adjustment circuit 107a and the phase adjustment control circuit 107b.
　時刻ｔ０では、半導体装置１００と接続された不図示の制御回路は、まず、電源投入後のいわゆるイニシャルシーケンス時に、位相調整回路１０７ａを活性化するために、外部リセット信号をコマンド端子群１０２の対応する一つに出力し、さらに、イニシャルシーケンスであることを示す外部イニシャル信号をコマンド端子群１０２に出力する。 At time t0, a control circuit (not shown) connected to the semiconductor device 100 first applies an external reset signal to the command terminal group 102 in order to activate the phase adjustment circuit 107a during a so-called initial sequence after power-on. In addition, an external initial signal indicating the initial sequence is output to the command terminal group 102.
　外部リセット信号と外部イニシャル信号は、それぞれ、コマンド端子群１０２を介してコマンド入力回路１０８に供給される。 The external reset signal and the external initial signal are supplied to the command input circuit 108 via the command terminal group 102, respectively.
　コマンド入力回路１０８は、コマンド端子群１０２からリセット信号を受け付けると、活性化したリセット信号ＲＥＳＥＴ（図５の信号Ｐ１）を、位相調整回路１０７ａと位相調整制御回路１０７ｂとに出力する。また、コマンド入力回路１０８は、コマンド端子群１０２からイニシャル信号を受け付けると、活性化したイニシャル信号ＩＮＩＴ（図５の信号Ｐ２）を、位相調整制御回路１０７ｂに出力する。 When the command input circuit 108 receives the reset signal from the command terminal group 102, the command input circuit 108 outputs the activated reset signal RESET (signal P1 in FIG. 5) to the phase adjustment circuit 107a and the phase adjustment control circuit 107b. Further, when receiving an initial signal from the command terminal group 102, the command input circuit 108 outputs the activated initial signal INIT (signal P2 in FIG. 5) to the phase adjustment control circuit 107b.
　位相調整回路１０７ａでは、カウンタ回路５が、活性化したリセット信号ＲＥＳＥＴを受け付け、活性化したリセット信号ＲＥＳＥＴに応じて、カウント値をプリセット値に初期化する。 In the phase adjustment circuit 107a, the counter circuit 5 receives the activated reset signal RESET, and initializes the count value to a preset value in accordance with the activated reset signal RESET.
　一方、位相調整制御回路１０７ｂでは、ＳＲラッチ１１が、活性化したリセット信号ＲＥＳＥＴを受け付け、活性化したリセット信号ＲＥＳＥＴに応じて、出力端子Ｑからの出力信号を非活性化（“Ｌ”）する。ＳＲラッチ１１の出力端子Ｑからの出力信号が非活性化（“Ｌ”）すると、判定タイミング制御回路１２は、非活性状態となり、比較タイミング信号ＳＣＬＫを非活性化（“Ｌ”）する。 On the other hand, in the phase adjustment control circuit 107b, the SR latch 11 receives the activated reset signal RESET and deactivates ("L") the output signal from the output terminal Q in accordance with the activated reset signal RESET. . When the output signal from the output terminal Q of the SR latch 11 is deactivated (“L”), the determination timing control circuit 12 is deactivated and deactivates (“L”) the comparison timing signal SCLK.
　その後、位相調整制御回路１０７ｂでは、更新制御回路１５ａは、活性化したイニシャル信号ＩＮＩＴを受け付けると、活性化したイニシャル信号ＩＮＩＴに応じて、活性化したイネーブル信号ＥＮＡ（図５の信号Ｐ３）を、位相調整回路１０７ａ出力する。 Thereafter, in the phase adjustment control circuit 107b, when the update control circuit 15a receives the activated initial signal INIT, the update control circuit 15a generates an activated enable signal ENA (signal P3 in FIG. 5) in accordance with the activated initial signal INIT. Outputs the phase adjustment circuit 107a.
　位相調整回路１０７ａでは、位相比較回路３と更新タイミング発生回路４とカウンタ回路５は、それぞれ、活性化したイネーブル信号ＥＮＡを受け付けると、位相調整動作（図５のフェーズＰ１０１）を開始する。 In the phase adjustment circuit 107a, the phase comparison circuit 3, the update timing generation circuit 4 and the counter circuit 5 each start the phase adjustment operation (phase P101 in FIG. 5) upon receiving the activated enable signal ENA.
　その後、位相調整回路１０７ａでの位相調整動作によって、内部クロック信号ＩＣＬＫの位相とレプリカクロック信号ＲＣＬＫの位相が一致した状況になると（時刻ｔ１）、カウンタ回路５は、活性化したロック信号ＬＯＣＫ（図５の信号Ｐ４）を、位相比較回路３と更新タイミング発生回路４とＳＲラッチ１１に出力し、その後動作を停止する。 Thereafter, when the phase of the internal clock signal ICLK and the phase of the replica clock signal RCLK coincide with each other by the phase adjustment operation in the phase adjustment circuit 107a (time t1), the counter circuit 5 activates the activated lock signal LOCK (FIG. 5 signal P4) is output to the phase comparison circuit 3, the update timing generation circuit 4 and the SR latch 11, and then the operation is stopped.
　位相比較回路３と更新タイミング発生回路４は、活性化したロック信号ＬＯＣＫを受け付けると、動作を停止する。 The phase comparison circuit 3 and the update timing generation circuit 4 stop operating when receiving the activated lock signal LOCK.
　また、ＳＲラッチ１１は、活性化したロック信号ＬＯＣＫを受け付けると、出力端子Ｑからの出力信号を活性化する。 Further, the SR latch 11 activates the output signal from the output terminal Q when receiving the activated lock signal LOCK.
　ＳＲラッチ１１の出力端子Ｑからの出力信号が活性化すると、判定タイミング制御回路１２は、活性状態となり、内部クロック信号ＩＣＬＫを所定回数カウントするごとに、検出回路１３の検出動作のタイミングを定める活性化した比較タイミング信号ＳＣＬＫ（図５における、時刻ｔ２での信号Ｐ５、時刻ｔ３での信号Ｐ６、時刻ｔ４での信号Ｐ７、時刻ｔ５での信号Ｐ８、時刻ｔ６での信号Ｐ９）を、位相検知部１３ｃと遅延回路１３ｂに出力する。 When the output signal from the output terminal Q of the SR latch 11 is activated, the determination timing control circuit 12 is activated, and the activation timing that determines the detection operation timing of the detection circuit 13 every time the internal clock signal ICLK is counted a predetermined number of times. Phase detection of the compared comparison timing signal SCLK (signal P5 at time t2, signal P6 at time t3, signal P7 at time t4, signal P8 at time t5, signal P9 at time t6 in FIG. 5) To the unit 13c and the delay circuit 13b.
　遅延回路１３ｂは、活性化した比較タイミング信号ＳＣＬＫを遅延時間αだけ遅延し、遅延された活性化した比較タイミング信号ＳＣＬＫを位相検知部１３ｄに出力する。 The delay circuit 13b delays the activated comparison timing signal SCLK by a delay time α, and outputs the delayed activated comparison timing signal SCLK to the phase detector 13d.
　位相検知部１３ｃは、活性化した比較タイミング信号ＳＣＬＫの立ち上がりタイミングで、遅延回路１３ａの出力信号のレベルを検出し、その検出結果に応じたレベルの出力信号を出力する。 The phase detector 13c detects the level of the output signal of the delay circuit 13a at the rising timing of the activated comparison timing signal SCLK, and outputs an output signal having a level corresponding to the detection result.
　また、位相検知部１３ｄは、遅延された活性化した比較タイミング信号ＳＣＬＫの立ち上がりタイミングで、レプリカクロック信号ＲＣＬＫのレベルを検出し、その検出結果に応じたレベルの出力信号を出力する。 The phase detector 13d detects the level of the replica clock signal RCLK at the rising timing of the delayed activated comparison timing signal SCLK, and outputs an output signal having a level corresponding to the detection result.
　図５に示した例では、信号Ｐ５、Ｐ７およびＰ９に伴う位相検知部１３ｃ、１３ｄでの検出時には、レプリカクロック信号ＲＣＬＫの立ち上がりの位相が、内部クロック信号ＩＣＬＫの立ち上がりの位相よりも、時間α以上遅れておらずかつ時間α以上進んでいない。このため、位相検知部１３ｃの出力信号Ｃおよび位相検知部１３ｄの出力信号Ｂのレベルは“Ｌ”となり、これにより、ＯＲ回路１３ｅの出力信号Ａのレベルも“Ｌ”となる。よって、位相調整回路１０７ａは、信号Ｐ５、Ｐ７およびＰ９に応じて位相調整動作を実行することはない。したがって、レプリカクロック信号ＲＣＬＫの立ち上がりの位相が、内部クロック信号ＩＣＬＫの立ち上がりの位相よりも、時間α以上遅れておらずかつ時間α以上進んでいない場合、必要性の低い位相調整動作は実行されず、必要性の低い位相調整動作に伴う電流消費を抑制できる。 In the example shown in FIG. 5, the phase of the rising edge of the replica clock signal RCLK is longer than the phase of the rising edge of the internal clock signal ICLK by time α when detected by the phase detectors 13c and 13d associated with the signals P5, P7 and P9. It is not delayed any more and has not advanced more than time α. For this reason, the levels of the output signal C of the phase detector 13c and the output signal B of the phase detector 13d are “L”, and the level of the output signal A of the OR circuit 13e is also “L”. Therefore, the phase adjustment circuit 107a does not execute the phase adjustment operation according to the signals P5, P7, and P9. Therefore, if the rising phase of the replica clock signal RCLK is not delayed by more than the time α and not more than the time α than the rising phase of the internal clock signal ICLK, the phase adjustment operation with low necessity is not executed. Therefore, it is possible to suppress the current consumption associated with the phase adjustment operation which is not necessary.
　また、図５に示した例では、信号Ｐ６に伴う位相検知部１３ｃ、１３ｄでの検出時には、レプリカクロック信号ＲＣＬＫの立ち上がりの位相が、内部クロック信号ＩＣＬＫの立ち上がりの位相よりも時間α以上遅くなっている。このため、位相検知部１３ｄの出力信号Ｂのレベルは“Ｈ”となり（図５の信号Ｐ１０）、これにより、ＯＲ回路１３ｅの出力信号Ａのレベルも“Ｈ”となり（図５の信号Ｐ１１）、更新制御回路１４からのイネーブル信号ＥＮＡが活性化する（図５の信号Ｐ１２）。よって、位相調整回路１０７ａは、活性化したイネーブル信号ＥＮＡ（図４の信号Ｐ１２）に応じて、位相調整動作を実行する（図４のフェーズＰ１０２）。したがって、レプリカクロック信号ＲＣＬＫの立ち上がりの位相が、内部クロック信号ＩＣＬＫの立ち上がりの位相よりも時間α以上遅くなっている場合、位相調整動作を行って位相差を小さくできる。 In the example shown in FIG. 5, the phase of the rising edge of the replica clock signal RCLK is delayed by a time α or more than the phase of the rising edge of the internal clock signal ICLK when detected by the phase detectors 13c and 13d associated with the signal P6. ing. For this reason, the level of the output signal B of the phase detector 13d becomes “H” (signal P10 in FIG. 5), and the level of the output signal A of the OR circuit 13e also becomes “H” (signal P11 in FIG. 5). Then, the enable signal ENA from the update control circuit 14 is activated (signal P12 in FIG. 5). Therefore, the phase adjustment circuit 107a performs a phase adjustment operation in response to the activated enable signal ENA (signal P12 in FIG. 4) (phase P102 in FIG. 4). Therefore, when the rising phase of replica clock signal RCLK is delayed by α or more than the rising phase of internal clock signal ICLK, the phase difference can be reduced by performing the phase adjustment operation.
　また、図５に示した例では、信号Ｐ８に伴う位相検知部１３ｃ、１３ｄでの検出時には、レプリカクロック信号ＲＣＬＫの立ち上がりの位相が、内部クロック信号ＩＣＬＫの立ち上がりの位相よりも時間α以上早くなっている。このため、位相検知部１３ｃの出力信号Ｃのレベルは“Ｈ”となり（図５の信号Ｐ１３）、これにより、ＯＲ回路１３ｅの出力信号Ａのレベルも“Ｈ”となり（図５の信号Ｐ１４）、更新制御回路１４からのイネーブル信号ＥＮＡが活性化する（図５の信号Ｐ１５）。よって、位相調整回路１０７ａは、活性化したイネーブル信号ＥＮＡ（図４の信号Ｐ１５）に応じて、位相調整動作を実行する（図４のフェーズＰ１０３）。したがって、レプリカクロック信号ＲＣＬＫの立ち上がりの位相が、内部クロック信号ＩＣＬＫの立ち上がりの位相よりも時間α以上早くなっている場合、位相調整動作を行って位相差を小さくできる。 In the example shown in FIG. 5, the phase of the rising edge of the replica clock signal RCLK is earlier than the time of rising of the internal clock signal ICLK by a time α or more when detected by the phase detectors 13c and 13d associated with the signal P8. ing. For this reason, the level of the output signal C of the phase detector 13c becomes “H” (signal P13 in FIG. 5), and the level of the output signal A of the OR circuit 13e also becomes “H” (signal P14 in FIG. 5). Then, the enable signal ENA from the update control circuit 14 is activated (signal P15 in FIG. 5). Therefore, the phase adjustment circuit 107a performs a phase adjustment operation in response to the activated enable signal ENA (signal P15 in FIG. 4) (phase P103 in FIG. 4). Therefore, when the rising phase of the replica clock signal RCLK is earlier than the rising phase of the internal clock signal ICLK by a time α or more, the phase adjustment operation can be performed to reduce the phase difference.
　次に、本実施形態の効果を説明する。 Next, the effect of this embodiment will be described.
　位相調整制御回路１０７ｂは、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が許容範囲から外れている場合に、位相調整回路１０７ａに位相調整動作を実行させる。 The phase adjustment control circuit 107b causes the phase adjustment circuit 107a to perform a phase adjustment operation when the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range.
　このため、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が許容範囲に含まれる場合には、位相調整動作は実施されない。したがって、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が許容範囲に含まれる状況での位相調整動作の実行、つまり、必要性の低い位相調整動作の実行を抑制することが可能になる。 Therefore, when the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is within the allowable range, the phase adjustment operation is not performed. Therefore, it is possible to suppress the execution of the phase adjustment operation in a situation where the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is within the allowable range, that is, the execution of the phase adjustment operation with low necessity. Become.
　例えば、電源電圧の変動に伴い、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が変動するが、電源電圧の変動に伴う位相差の変動が許容範囲に含まれる場合には、位相調整動作を実行する必要性は低い。このため、本実施形態は、電源電圧の変動に伴って位相調整動作を常に実行する場合に比べて、必要性の低い位相調整動作の実行を抑制することが可能になり、電流消費を抑えることが可能になる。 For example, the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK varies with the variation in the power supply voltage, but the phase difference variation with the variation in the power supply voltage is included in the allowable range. There is little need to perform the adjustment operation. For this reason, in the present embodiment, it is possible to suppress the execution of the phase adjustment operation, which is less necessary, as compared with the case where the phase adjustment operation is always performed in accordance with the fluctuation of the power supply voltage, thereby suppressing current consumption. Is possible.
　本実施形態では、位相調整制御回路１０７ｂは、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの位相差が許容範囲から外れている場合に、活性化したイネーブル信号ＥＮＡを位相調整回路１０７ａに出力する。位相調整回路１０７ａは、活性化したイネーブル信号ＥＮＡを受け付けた場合に、位相調整動作を実行する。 In the present embodiment, the phase adjustment control circuit 107b outputs the activated enable signal ENA to the phase adjustment circuit 107a when the phase difference between the internal clock signal ICLK and the input / output clock signal LCLK is out of the allowable range. To do. The phase adjustment circuit 107a performs the phase adjustment operation when receiving the activated enable signal ENA.
　このため、活性化したイネーブル信号ＥＮＡを用いて、位相調整動作の実行を制御することが可能になる。 Therefore, the execution of the phase adjustment operation can be controlled using the activated enable signal ENA.
　（第２実施形態）
　本発明の第２実施形態は、第１実施形態の信号調整回路１に立ち上がり位相調整動作を実行させ、さらに、第１実施形態の構成に対して立ち下がり位相調整（Ｄｕｔｙ調整：デューティ調整）用の回路部分を付加したものである。 (Second Embodiment)
The second embodiment of the present invention causes the signal adjustment circuit 1 of the first embodiment to execute the rising phase adjustment operation, and further, for the falling phase adjustment (Duty adjustment: duty adjustment) with respect to the configuration of the first embodiment. The circuit part is added.
　そして、第２実施形態では、立ち下がり位相調整動作の周期が、立ち上がり位相調整動作を実行するか否かを判定する周期よりも長くなっている。これは、後述するように、電源電圧の変動に伴う立ち下がり位相の変動が、電源電圧の変動に伴う立ち上がり位相の変動よりも小さいことを本発明者が見出したことに起因する。 In the second embodiment, the cycle of the falling phase adjustment operation is longer than the cycle for determining whether or not to execute the rising phase adjustment operation. As will be described later, this is due to the fact that the present inventors have found that the fluctuation of the falling phase accompanying the fluctuation of the power supply voltage is smaller than the fluctuation of the rising phase accompanying the fluctuation of the power supply voltage.
　以下、第２実施形態について、第１実施形態と異なる点を中心に説明する。 Hereinafter, the second embodiment will be described focusing on differences from the first embodiment.
　第２実施形態では、図１に示した位相調整回路１０７ａの代わりに、図６に示した位相調整回路１０７ａ１が用いられ、図１に示した位相調整制御回路１０７ｂの代わりに、図７に示した位相調整制御回路１０７ｂ１が用いられる。 In the second embodiment, the phase adjustment circuit 107a1 shown in FIG. 6 is used instead of the phase adjustment circuit 107a shown in FIG. 1, and the phase adjustment control circuit 107b shown in FIG. The phase adjustment control circuit 107b1 is used.
　図６は、第２実施形態で用いられる位相調整回路１０７ａ１を示した図である。図６において、図２に示したものと同一構成のものについては同一符号を付してある。 FIG. 6 is a diagram showing the phase adjustment circuit 107a1 used in the second embodiment. In FIG. 6, the same components as those shown in FIG.
　位相調整回路１０７ａ１は、信号調整回路１が立ち上がり位相調整動作を実行し、信号調整回路６とＤＣＣ（Duty correction circuit）回路７とが追加されている点において、図２に示した位相調整回路１０７ａと異なる。 The phase adjustment circuit 107a1 includes the phase adjustment circuit 107a shown in FIG. 2 in that the signal adjustment circuit 1 performs a rising phase adjustment operation and a signal adjustment circuit 6 and a DCC (Duty correction circuit) circuit 7 are added. And different.
　信号調整回路６は、信号調整回路１の出力信号の立ち下がりの位相を調整することによって、内部クロック信号ＩＣＬＫの立ち下がりの位相と、入出力用クロック信号ＬＣＬＫの立ち下がりの位相と、の位相差を前記所定値に設定する立ち下がり位相調整動作を実行する。 The signal adjustment circuit 6 adjusts the phase of the falling edge of the output signal of the signal adjustment circuit 1 so that the phase of the falling edge of the internal clock signal ICLK and the phase of the falling edge of the input / output clock signal LCLK are shifted. A falling phase adjustment operation for setting the phase difference to the predetermined value is executed.
　ＤＣＣ回路７は、イネーブル信号ＥＮＡ２の入力に伴い起動し、レプリカクロック信号ＲＣＬＫのデューティを検出することによって、内部クロック信号ＩＣＬＫの立ち下がりエッジと入出力用クロック信号ＬＣＬＫの立ち下がりエッジの位相を比較する。ＤＣＣ回路７は、内部クロック信号ＩＣＬＫと入出力用クロック信号ＬＣＬＫとの立ち下がりエッジを直接的に比較するのではなく、レプリカクロック信号ＲＣＬＫのデューティに基づいて両クロックの立ち下がりエッジの比較を間接的に行う。ＤＣＣ回路７は、比較結果を信号調整回路６に出力し、その後、動作を停止する。 The DCC circuit 7 is activated in response to the input of the enable signal ENA2, and compares the phase of the falling edge of the internal clock signal ICLK and the falling edge of the input / output clock signal LCLK by detecting the duty of the replica clock signal RCLK. To do. The DCC circuit 7 does not directly compare the falling edges of the internal clock signal ICLK and the input / output clock signal LCLK, but indirectly compares the falling edges of both clocks based on the duty of the replica clock signal RCLK. Do it. The DCC circuit 7 outputs the comparison result to the signal adjustment circuit 6 and then stops its operation.
　信号調整回路６は、ＤＣＣ回路７からの比較結果に応じて、信号調整回路１の出力クロック信号の立ち下がりの位相を調整することによって、内部クロック信号ＩＣＬＫの立ち下がりの位相と、入出力用クロック信号ＬＣＬＫの立ち下がりの位相と、の位相差を該所定値に設定する。 The signal adjustment circuit 6 adjusts the falling phase of the output clock signal of the signal adjustment circuit 1 according to the comparison result from the DCC circuit 7, so that the falling phase of the internal clock signal ICLK The phase difference between the falling phase of the clock signal LCLK and the predetermined value is set.
　図７は、第２実施形態で用いられる位相調整制御回路１０７ｂ１を示した図である。図７において、図３に示したものと同一構成のものについては同一符号を付してある。 FIG. 7 is a diagram showing the phase adjustment control circuit 107b1 used in the second embodiment. In FIG. 7, the same components as those shown in FIG.
　位相調整制御回路１０７ｂ１は、図３に示した判定タイミング制御回路１２の代わりに、判定タイミング制御回路１２ａが用いられ、更新制御回路１５が追加されている点において、図１に示した位相調整制御回路１０７ｂと異なる。 The phase adjustment control circuit 107b1 uses the determination timing control circuit 12a in place of the determination timing control circuit 12 shown in FIG. 3, and the update control circuit 15 is added, so that the phase adjustment control shown in FIG. Different from the circuit 107b.
　判定タイミング制御回路１２ａは、判定タイミング制御回路１２と同様に、ＳＲラッチ１１の出力信号が活性化している間、活性状態となり、内部クロック信号ＩＣＬＫを所定回数カウントするごとに、活性化した比較タイミング信号ＳＣＬＫを出力する。 Similar to the determination timing control circuit 12, the determination timing control circuit 12a is in an active state while the output signal of the SR latch 11 is active, and is activated every time the internal clock signal ICLK is counted a predetermined number of times. The signal SCLK is output.
　なお、活性化した比較タイミング信号ＳＣＬＫの出力周期が、電源電圧の変動周期（例えば、数～数百ｕｓ）に合うように、所定回数は設定される。この設定は、第１実施形態にも共通する。内部クロック信号ＩＣＬＫを所定回数カウントするのに要する時間は、第１時間の一例である。 Note that the predetermined number of times is set so that the output period of the activated comparison timing signal SCLK matches the fluctuation period (for example, several to several hundreds of us) of the power supply voltage. This setting is common to the first embodiment. The time required to count the internal clock signal ICLK a predetermined number of times is an example of a first time.
　判定タイミング制御回路１２ａは、さらに、活性状態の間、内部クロック信号ＩＣＬＫを所定回数よりも多い特定回数カウントするごとに、活性化した動作指示信号ＩＳを出力する。内部クロック信号ＩＣＬＫを特定回数カウントするのに要する時間は、第２時間の一例である。 Further, the determination timing control circuit 12a outputs an activated operation instruction signal IS every time the internal clock signal ICLK is counted more than a predetermined number during the active state. The time required to count the internal clock signal ICLK a specific number of times is an example of a second time.
　更新制御回路１５は、例えばＯＲ回路であり、活性化したイニシャル信号ＩＮＩＴ、または、活性化した動作指示信号ＩＳを受け付けると、活性化したイネーブル信号ＥＮＡ２を出力する。 The update control circuit 15 is an OR circuit, for example, and outputs an activated enable signal ENA2 upon receiving an activated initial signal INIT or an activated operation instruction signal IS.
　次に、動作を説明する。 Next, the operation will be described.
　図８は、位相調整回路１０７ａ１と位相調整制御回路１０７ｂ１との動作を説明するためのタイミングチャートである。なお、図８において、図５に示したものと同一機能の信号には同一符号を付してある。 FIG. 8 is a timing chart for explaining operations of the phase adjustment circuit 107a1 and the phase adjustment control circuit 107b1. In FIG. 8, signals having the same functions as those shown in FIG.
　以下、位相調整回路１０７ａ１と位相調整制御回路１０７ｂ１との動作について、第１実施形態の動作と異なる点を中心に説明する。 Hereinafter, operations of the phase adjustment circuit 107a1 and the phase adjustment control circuit 107b1 will be described focusing on differences from the operation of the first embodiment.
　コマンド入力回路１０８は、コマンド端子群１０２からイニシャル信号を受け付けると、活性化したイニシャル信号ＩＮＩＴ（図８の信号Ｐ２）を、位相調整制御回路１０７ｂ２内の更新制御回路１４および１５に出力する。 When the command input circuit 108 receives the initial signal from the command terminal group 102, the command input circuit 108 outputs the activated initial signal INIT (signal P2 in FIG. 8) to the update control circuits 14 and 15 in the phase adjustment control circuit 107b2.
　更新制御回路１５は、活性化したイニシャル信号ＩＮＩＴを受け付けると、活性化したイネーブル信号ＥＮＡ２（図８の信号Ｐ１６）を、ＤＣＣ回路７に出力する。 Upon receiving the activated initial signal INIT, the update control circuit 15 outputs the activated enable signal ENA2 (signal P16 in FIG. 8) to the DCC circuit 7.
　ＤＣＣ回路７は、活性化したイネーブル信号ＥＮＡ２（図８の信号Ｐ１６）の入力に伴い起動し、レプリカクロック信号ＲＣＬＫのデューティを検出する。ＤＣＣ回路７は、デューティの検出結果（内部クロック信号ＩＣＬＫの立ち下がりエッジと入出力用クロック信号ＬＣＬＫの立ち下がりエッジとの位相の比較結果）を信号調整回路６に出力し、その後、動作を停止する。 The DCC circuit 7 is activated in response to the input of the activated enable signal ENA2 (signal P16 in FIG. 8), and detects the duty of the replica clock signal RCLK. The DCC circuit 7 outputs the duty detection result (phase comparison result between the falling edge of the internal clock signal ICLK and the falling edge of the input / output clock signal LCLK) to the signal adjustment circuit 6, and then stops the operation. To do.
　信号調整回路６は、ＤＣＣ回路７からのデューティの検出結果に応じて、立ち下がり位相調整動作（図８のフェーズＰ１０４）を実行する。 The signal adjustment circuit 6 executes the falling phase adjustment operation (phase P104 in FIG. 8) in accordance with the duty detection result from the DCC circuit 7.
　また、判定タイミング制御回路１２ａは、活性状態になると、内部クロック信号ＩＣＬＫを所定回数カウントするごとに、活性化した比較タイミング信号ＳＣＬＫ（図８における信号Ｐ５、信号Ｐ６、信号Ｐ７、信号Ｐ８、信号Ｐ９）を、位相検知部１３ｃと遅延回路１３ｂに出力し、さらに、内部クロック信号ＩＣＬＫを特定回数カウントするごとに、活性化した動作指示信号ＩＳを、更新制御回路１５に出力する。 Further, when the determination timing control circuit 12a is activated, every time the internal clock signal ICLK is counted a predetermined number of times, the activated comparison timing signal SCLK (signal P5, signal P6, signal P7, signal P8, signal P8 in FIG. P9) is output to the phase detector 13c and the delay circuit 13b, and the activated operation instruction signal IS is output to the update control circuit 15 every time the internal clock signal ICLK is counted a specific number of times.
　更新制御回路１５は、活性化した動作指示信号ＩＳを受け付けると、活性化したイネーブル信号ＥＮＡ２（図８の信号Ｐ１７）を、ＤＣＣ回路７に出力する。 When receiving the activated operation instruction signal IS, the update control circuit 15 outputs the activated enable signal ENA2 (signal P17 in FIG. 8) to the DCC circuit 7.
　ＤＣＣ回路７は、活性化したイネーブル信号ＥＮＡ２（図８の信号Ｐ１７）の入力に伴い起動し、信号調整制御回路１が出力したクロック信号のデューティを検出する。ＤＣＣ回路７は、デューティの検出結果を信号調整回路６に出力し、その後、動作を停止する。 The DCC circuit 7 is activated in response to the input of the activated enable signal ENA2 (signal P17 in FIG. 8), and detects the duty of the clock signal output from the signal adjustment control circuit 1. The DCC circuit 7 outputs the duty detection result to the signal adjustment circuit 6, and then stops the operation.
　信号調整回路６は、ＤＣＣ回路７からのデューティの検出結果に応じて、立ち下がり位相調整動作（図８のフェーズＰ１０５）を実行する。 The signal adjustment circuit 6 performs a falling phase adjustment operation (phase P105 in FIG. 8) in accordance with the duty detection result from the DCC circuit 7.
　次に、本実施形態の効果を説明する。 Next, the effect of this embodiment will be described.
　電源電圧の変動に対して、外部クロック信号ＣＫの立ち上がりタイミングと、入出力用クロック信号ＬＣＬＫの立ち上がりタイミングにより定まるデータ入出力端子群１０４から出力される信号ＤＱの立ち上がりタイミングとは、ズレを生じやすい。例えば、電源電圧が低くなれば、信号ＤＱの出力タイミングが遅れる。 The rise timing of the external clock signal CK and the rise timing of the signal DQ output from the data input / output terminal group 104 determined by the rise timing of the input / output clock signal LCLK are likely to be shifted with respect to fluctuations in the power supply voltage. . For example, if the power supply voltage is lowered, the output timing of the signal DQ is delayed.
　一方、入出力用クロック信号ＬＣＬＫの立ち下がりタイミングに応じて変動する入出力用クロック信号ＬＣＬＫのデューティは、入出力用クロック信号ＬＣＬＫの“Ｈ”レベルの継続期間と入出力用クロックＬＣＬＫの“Ｌ”レベルの継続期間とが、同じように電源電圧の変動の影響を受けるため、一方に偏るということは起きにくい。 On the other hand, the duty of the input / output clock signal LCLK, which fluctuates in accordance with the falling timing of the input / output clock signal LCLK, is the duration of the “H” level of the input / output clock signal LCLK and the “L” of the input / output clock LCLK. Since the “level duration” is similarly affected by fluctuations in the power supply voltage, it is unlikely to be biased to one side.
　このため、電源電圧の変動の影響について考慮した場合、入出力用クロック信号ＬＣＬＫのデューティを調整するための立ち下がり位相調整動作は、信号ＤＱの出力タイミングに影響を与える立ち上がり位相調整動作よりも、低い頻度で実行されてもよいことが見出される。 Therefore, when considering the influence of fluctuations in the power supply voltage, the falling phase adjustment operation for adjusting the duty of the input / output clock signal LCLK is more than the rising phase adjustment operation that affects the output timing of the signal DQ. It is found that it may be performed less frequently.
　本実施形態では、位相調整制御回路１０７ｂ１は、第１時間間隔で、立ち上がり位相差が許容範囲から外れたか否かを判定し立ち上がり位相差が許容範囲から外れている場合に位相調整回路１０７ａ１に立ち上がり位相調整動作を実行させ、第１時間間隔よりも長い第２時間間隔で、位相調整回路１０７ａ１に立ち下がり位相調整動作を実行させる。 In the present embodiment, the phase adjustment control circuit 107b1 determines whether or not the rising phase difference is out of the allowable range at the first time interval, and rises up to the phase adjustment circuit 107a1 when the rising phase difference is out of the allowable range. A phase adjustment operation is executed, and the phase adjustment circuit 107a1 is caused to execute a falling phase adjustment operation at a second time interval longer than the first time interval.
　このため、立ち下がり位相調整動作の周期が、立ち上がり位相調整動作を実行するか否かを判定する周期よりも長くなっている。したがって、立ち下がり位相調整動作を立ち上がり位相調整動作を実行するか否かを判定と同じ頻度で実行する場合に比べて、立ち下がり位相調整動作の頻度を低くでき、電流消費を抑えることが可能になる。 Therefore, the cycle of the falling phase adjustment operation is longer than the cycle for determining whether or not to execute the rising phase adjustment operation. Therefore, compared with the case where the falling phase adjustment operation is executed at the same frequency as the determination whether the rising phase adjustment operation is executed, the frequency of the falling phase adjustment operation can be lowered and the current consumption can be suppressed. Become.
　また、本実施形態では、位相調整制御回路１０７ｂ１は、第２時間間隔で、活性化したイネーブル信号ＥＮＡ２を位相調整回路１０７ａ１に出力する。位相調整回路１０７ａ１は、活性化したイネーブル信号ＥＮＡ２を受け付けた場合に、立ち下がり位相調整動作を実行する。 In this embodiment, the phase adjustment control circuit 107b1 outputs the activated enable signal ENA2 to the phase adjustment circuit 107a1 at the second time interval. The phase adjustment circuit 107a1 executes the falling phase adjustment operation when the activated enable signal ENA2 is received.
　このため、活性化したイネーブル信号ＥＮＡ２を用いて、立ち下がり位相調整動作の実行を制御することが可能になる。 Therefore, it is possible to control the execution of the falling phase adjustment operation using the activated enable signal ENA2.
　実施形態を参照して本願発明を説明したが、本願発明は上記実施形態に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。この出願は、２０１３年１月２２日に出願された日本出願特願２０１３－９２５１を基礎とする優先権を主張し、その開示の全てをここに取り込む。 Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2013-9251 for which it applied on January 22, 2013, and takes in those the indications of all here.
　　　１００　　　半導体装置
　　　１０１　　　クロック端子群
　　　１０２　　　コマンド端子群
　　　１０３　　　アドレス端子群
　　　１０４　　　データ入出力端子群
　　　１０５　　　電源端子群
　　　１０６　　　クロック入力回路
　　　１０７　　　入出力用クロック生成部
　　　１０７ａ、１０７ａ１　位相調整回路
　　　１０７ｂ、１０７ｂ１　位相調整制御回路
　　　１０８　　　コマンド入力回路
　　　１０９　　　コマンドデコード回路
　　　１１０　　　リフレッシュ制御回路
　　　１１１　　　アドレス入力回路
　　　１１２　　　アドレスラッチ回路
　　　１１３　　　モードレジスタ
　　　１１４　　　メモリセルアレイ
　　　１１５　　　ロウデコーダ
　　　１１６　　　カラムデコーダ
　　　１１７　　　ＦＩＦＯ回路
　　　１１８　　　入出力回路
　　　１１９　　　内部電源発生回路
　　　　ＢＬ　　　ビット線
　　　　ＷＬ　　　ワード線
　　　　ＭＣ　　　メモリセル
　　　　　１　　　信号調整回路
　　　　　２　　　レプリカ回路
　　　　　３　　　位相比較回路
　　　　　４　　　更新タイミング発生回路
　　　　　５　　　カウンタ回路
　　　　　６　　　信号調整回路
　　　　　７　　　ＤＣＣ回路
　　　　１１　　　ＳＲラッチ
　　　　１２、１２ａ　判定タイミング制御回路
　　　　１３　　　検出回路
　　　　１３ａ、１３ｂ　遅延回路
　　　　１３ｃ、１３ｄ　位相検知部
　　　　１３ｅ　ＯＲ回路
　　　　１４、１５　更新制御回路 DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Clock terminal group 102 Command terminal group 103 Address terminal group 104 Data input / output terminal group 105 Power supply terminal group 106 Clock input circuit 107 Input / output clock generation part 107a, 107a1 Phase adjustment circuit 107b, 107b1 Phase adjustment control circuit 108 Command input circuit 109 Command decode circuit 110 Refresh control circuit 111 Address input circuit 112 Address latch circuit 113 Mode register 114 Memory cell array 115 Row decoder 116 Column decoder 117 FIFO circuit 118 Input / output circuit 119 Internal power generation circuit BL Bit line WL Word line MC Memory cell 1 Signal conditioning circuit 2 Replica circuit 3 Phase comparison circuit 4 Update timing generation circuit 5 Counter circuit 6 Signal adjustment circuit 7 DCC circuit 11 SR latch 12, 12a Determination timing control circuit 13 Detection circuit 13a, 13b Delay circuit 13c, 13d Phase detection unit 13e OR circuit 14, 15 Update Control circuit

Claims (8)

  1. 　入力信号に基づいて出力信号を生成し、また、前記入力信号と前記出力信号との位相差を所定値に設定する調整動作を実行可能な位相調整部と、
    　前記位相差が、前記所定値を含む許容範囲から外れている場合に、前記位相調整部に前記調整動作を実行させる位相調整制御部と、を含む出力信号生成装置。     An output signal based on the input signal, and a phase adjustment unit capable of executing an adjustment operation for setting a phase difference between the input signal and the output signal to a predetermined value;
    An output signal generation device including: a phase adjustment control unit that causes the phase adjustment unit to execute the adjustment operation when the phase difference is out of an allowable range including the predetermined value.
  2. 　前記位相調整制御部は、前記位相差が前記許容範囲から外れている場合に、調整用信号を前記位相調整部に出力し、
    　前記位相調整部は、前記調整用信号を受け付けた場合に、前記調整動作を実行する、請求項１に記載の出力信号生成装置。     The phase adjustment control unit outputs an adjustment signal to the phase adjustment unit when the phase difference is out of the allowable range,
    The output signal generation device according to claim 1, wherein the phase adjustment unit performs the adjustment operation when the adjustment signal is received.
  3. 　前記位相調整制御部は、間欠的に、前記位相差が前記許容範囲から外れたか否かを判定し、前記位相差が前記許容範囲から外れている場合に前記位相調整部に前記位相調整動作を実行させる、請求項１または２に記載の出力信号生成装置。 The phase adjustment control unit intermittently determines whether the phase difference is out of the allowable range, and performs the phase adjustment operation on the phase adjustment unit when the phase difference is out of the allowable range. The output signal generation device according to claim 1, wherein the output signal generation device is executed.
  4. 　前記位相差は、前記入力信号の立ち上がりと前記出力信号の立ち上がりとの位相差である立ち上がり位相差であり、
    　前記調整動作は、前記立ち上がり位相差を前記所定値に設定する立ち上がり位相調整動作である、請求項１から３のいずれか１項に記載の出力信号生成装置。     The phase difference is a rising phase difference that is a phase difference between the rising edge of the input signal and the rising edge of the output signal.
    4. The output signal generation device according to claim 1, wherein the adjustment operation is a rising phase adjustment operation for setting the rising phase difference to the predetermined value. 5.
  5. 　前記位相調整部は、さらに、前記入力信号の立ち下がりと前記出力信号の立ち下がりとの位相差である立ち下がり位相差を前記所定値に設定する立ち下がり位相調整動作を実行可能であり、
    　前記位相調整制御部は、第１時間間隔で、前記立ち上がり位相差が前記許容範囲から外れたか否かを判定し前記立ち上がり位相差が前記許容範囲から外れている場合に前記位相調整部に前記立ち上がり位相調整動作を実行させ、前記第１時間間隔よりも長い第２時間間隔で、前記位相調整部に前記立ち下がり位相調整動作を実行させる、請求項４に記載の出力信号生成装置。     The phase adjustment unit is further capable of executing a fall phase adjustment operation for setting a fall phase difference, which is a phase difference between a fall of the input signal and a fall of the output signal, to the predetermined value,
    The phase adjustment control unit determines whether or not the rising phase difference is out of the allowable range at a first time interval. When the rising phase difference is out of the allowable range, the phase adjustment control unit 5. The output signal generation device according to claim 4, wherein a phase adjustment operation is executed, and the falling phase adjustment operation is executed by the phase adjustment unit at a second time interval longer than the first time interval.
  6. 　前記位相調整制御部は、前記第２時間間隔で、立ち下がり位相調整用信号を前記位相調整部に出力し、
    　前記位相調整部は、前記立ち下がり位相調整用信号を受け付けた場合に、前記立ち下がり位相調整動作を実行する、請求項５に記載の出力信号生成装置。     The phase adjustment control unit outputs a falling phase adjustment signal to the phase adjustment unit at the second time interval,
    The output signal generation device according to claim 5, wherein the phase adjustment unit performs the falling phase adjustment operation when the falling phase adjustment signal is received.
  7. 　請求項１から６のいずれか１項に記載の出力信号生成装置と、
    　メモリセルと、
    　前記出力信号生成装置にて生成された出力信号に応じて、前記メモリセルへのデータの書き込み、または、前記メモリセルからのデータの読み出しを実行する入出力部と、を含む半導体装置。     The output signal generation device according to any one of claims 1 to 6,
    A memory cell;
    A semiconductor device comprising: an input / output unit that executes data writing to the memory cell or data reading from the memory cell in accordance with an output signal generated by the output signal generating device.
  8. 　入力信号に基づいて出力信号を生成し前記入力信号と前記出力信号との位相差を所定値に設定する調整動作を実行可能な位相調整部を含む出力信号生成装置が行う出力信号生成方法であって、
    　前記位相差が、前記所定値を含む許容範囲から外れている場合に、前記位相調整部に前記調整動作を実行させる出力信号生成方法。     An output signal generation method performed by an output signal generation apparatus including a phase adjustment unit capable of executing an adjustment operation for generating an output signal based on an input signal and setting a phase difference between the input signal and the output signal to a predetermined value. And
    An output signal generation method for causing the phase adjustment unit to perform the adjustment operation when the phase difference is out of an allowable range including the predetermined value.
PCT/JP2014/050838 2013-01-22 2014-01-17 Output-signal generation device, semiconductor device, and output-signal generation method WO2014115657A1 (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286697A (en) * 1999-03-31 2000-10-13 Nec Ic Microcomput Syst Ltd Digital pll circuit and method for controlling it
JP2002124873A (en) * 2000-10-18 2002-04-26 Mitsubishi Electric Corp Semiconductor device
JP2009283058A (en) * 2008-05-21 2009-12-03 Elpida Memory Inc Semiconductor device
US20100033218A1 (en) * 2008-08-11 2010-02-11 Hynix Semiconductor Inc. Semiconductor integrated circuit and method of controlling the same
JP2010187229A (en) * 2009-02-12 2010-08-26 Elpida Memory Inc Clock control circuit and semiconductor device including the same
JP2010226173A (en) * 2009-03-19 2010-10-07 Elpida Memory Inc Duty detection circuit, clock generation circuit including the duty detection circuit, and semiconductor device
JP2013031128A (en) * 2011-07-29 2013-02-07 Elpida Memory Inc Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286697A (en) * 1999-03-31 2000-10-13 Nec Ic Microcomput Syst Ltd Digital pll circuit and method for controlling it
JP2002124873A (en) * 2000-10-18 2002-04-26 Mitsubishi Electric Corp Semiconductor device
JP2009283058A (en) * 2008-05-21 2009-12-03 Elpida Memory Inc Semiconductor device
US20100033218A1 (en) * 2008-08-11 2010-02-11 Hynix Semiconductor Inc. Semiconductor integrated circuit and method of controlling the same
JP2010187229A (en) * 2009-02-12 2010-08-26 Elpida Memory Inc Clock control circuit and semiconductor device including the same
JP2010226173A (en) * 2009-03-19 2010-10-07 Elpida Memory Inc Duty detection circuit, clock generation circuit including the duty detection circuit, and semiconductor device
JP2013031128A (en) * 2011-07-29 2013-02-07 Elpida Memory Inc Semiconductor device

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