WO2014108037A1 - 深沟槽刻蚀工艺中圆片的刻蚀方法 - Google Patents

深沟槽刻蚀工艺中圆片的刻蚀方法 Download PDF

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Publication number
WO2014108037A1
WO2014108037A1 PCT/CN2013/091182 CN2013091182W WO2014108037A1 WO 2014108037 A1 WO2014108037 A1 WO 2014108037A1 CN 2013091182 W CN2013091182 W CN 2013091182W WO 2014108037 A1 WO2014108037 A1 WO 2014108037A1
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wafer
etching
main process
sub
steps
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PCT/CN2013/091182
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English (en)
French (fr)
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章安娜
李晓明
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无锡华润上华半导体有限公司
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Priority to US14/435,955 priority Critical patent/US9728472B2/en
Publication of WO2014108037A1 publication Critical patent/WO2014108037A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks

Definitions

  • the invention relates to the field of semiconductor manufacturing processes, and in particular to a method for etching a wafer in a deep trench etching process.
  • Deep trench etch deep The silicon trench etching (DSIE) process is an etching method used to etch deep trenches. The process mainly uses a sheet as a substrate sheet, with a photoresist (photoresist, PR) As a masking layer, the transfer of the pattern is realized on the sheet by the etching process to realize some special functions.
  • DSIE deep The silicon trench etching
  • a method for etching a wafer in a deep trench etching process comprising the following steps:
  • step d Determining whether the accumulated time of the main process sub-step reaches a predetermined threshold, if yes, proceeding to step e; if not, performing the operations of steps a to c again;
  • the wafer is manufactured.
  • the method before performing step e, the method further includes:
  • the predetermined threshold value in step d is the time required for the main process of the wafer.
  • the operations of steps a through c are cycled at least twice.
  • the time of the main process sub-step is less than or equal to 30 minutes.
  • the electrostatic discharge is for a period of from 1 to 2 minutes.
  • the wafer is cooled by a helium gas stream during the main process sub-step.
  • the helium gas stream is to cool the back of the wafer.
  • the helium gas stream has a gas flow intensity of 1.5 mbar.
  • the main process is etching.
  • the etching is to etch a wafer having a mask prepared by using an etching gas in a plasma state.
  • the step of transmitting the wafer is further included.
  • the etching method of the wafer in the above deep trench etching process adopts the principle of step etching and increases the electrostatic discharge step. Avoid the continuous contact of the wafer with the electrostatic chuck, and receive the plasma bombardment for a long time to make the surface temperature of the wafer become higher, resulting in the phenomenon of paste on the surface of the wafer.
  • FIG. 1 is a flow chart showing a method of etching a wafer in the deep trench etching process of Embodiment 1;
  • FIG. 2 is a flow chart showing a method of etching a wafer in the deep trench etching process of Embodiment 2.
  • Embodiment 1 is a flow chart showing a method of etching a wafer in the deep trench etching process of Embodiment 1.
  • the conventional single wafer main process etching step is divided into a plurality of main process etching sub-steps.
  • the main process step of the wafer is the step of etching the wafer.
  • the time required for the main process of the wafer is the time required to complete the wafer etching.
  • the main process step of the wafer is to divide the step of etching the wafer into several sub-steps, that is, to perform wafer etching in multiple times, and one etching in multiple etching is referred to as a wafer main process sub-step.
  • the substep time is less than a single main process etch step.
  • the sub-step time is much smaller than a single main process etching step.
  • the wafer is subjected to a static dechucking step, and then the electrostatic chuck is used again. Adsorbing the wafer and re-stabilizing the process atmosphere for the next main etching sub-step. After the next etching sub-step, the wafer is again electrostatically discharged, and the cycle is continued until all the main process etchers are performed before. The cumulative time of the steps reaches a predetermined threshold.
  • Embodiment 1 includes the following steps: first, preparation work before the wafer etching process, that is, step S110, in which electrostatic adsorption is performed on the wafer by an electrostatic chuck (E-CHUCK), and the process is stabilized. The atmosphere needed. Then, in step S120, the wafer main process etching sub-step is performed, and in step S120, the wafer in which the mask has been prepared is mainly etched by using the plasma etching gas. The duration of S120 is less than a single main process etch step. It is preferably much smaller than the original single main process etch step.
  • step S110 preparation work before the wafer etching process
  • E-CHUCK electrostatic chuck
  • step S130 is performed in which the electrostatic adsorption of the electrostatic chuck to the wafer is released and electrostatic discharge is performed.
  • step S140 determining whether the accumulated time of all the main process etching sub-steps performed before reaches a predetermined threshold, specifically, whether the cumulative time required for the main process etching is reached, and if the result of the determination is "Yes" Then, the process proceeds to step S150 to complete the wafer etching.
  • step S110 If the result of the determination is "NO", it means that the accumulation time of the main process etching substep does not meet the requirements of the main process etching, and the step returns to step S110, the wafer is again adsorbed by the electrostatic chuck (RECHUCK), and the main body is stabilized.
  • step S130 After the main process sub-step S120 ends, the process proceeds to step S130 to release the electrostatic adsorption of the electrostatic chuck to the wafer.
  • step S140 it is determined once again whether the accumulated time of all the main process etching sub-steps performed before reaches the accumulation time required for the main process etching, and cycles until the accumulation time of all the main process etching sub-steps After the time required for the main process etching is reached, the process proceeds to step S150 to complete the wafer etching, and then the wafer is subjected to the next operation, such as transferring the main process cavity.
  • Embodiment 1 it can be seen from Embodiment 1 that the whole process adopts the step etching principle, and the single etching is changed into the etching sub-step of several steps, and the electrostatic discharge step is added after the end of each small etching process to avoid the circle.
  • the film continues to contact with the electrostatic chuck (E-CHUCK), and the plasma is bombarded for a long time to make the surface temperature of the wafer become higher, the loss rate of the photoresist (PR) increases, and the surface paste of the wafer is generated, and even the PR is The phenomenon of etching is clean.
  • E-CHUCK electrostatic chuck
  • the method can reduce the amount of surface static accumulation generated by the wafer for a long time process to ensure that the electrostatic discharge is not clean after the wafer process ends and deviates from the electrostatic chuck position.
  • Embodiment 2 is a flow chart showing a method of etching a wafer in the deep trench etching process of Embodiment 2.
  • Embodiment 2 is substantially the same as Embodiment 1, and the conventional single wafer main process etching step is divided into a plurality of main process etching sub-steps, and the sub-step time is much smaller than the original single main process etching step.
  • the wafer After each main process etching sub-step, the wafer is subjected to a static discharge (DECHUCK) step, and then the electrostatic chuck is used to adsorb the wafer again, and the process atmosphere is re-stabilized for the next main etching step, the next step After the etchant step is completed, the wafer is again electrostatically discharged, and the cycle is continued until the cumulative time of all the main process etch sub-steps previously performed reaches a predetermined threshold.
  • DECHUCK static discharge
  • Embodiment 2 when it is judged that the accumulation time of all the main process etching substeps reaches a predetermined threshold, the method further comprises contacting the wafer with the ground, so that the static electricity in the wafer is completely released. Then, the wafer is subjected to the next step, such as transferring the main process chamber.
  • Embodiment 2 includes the following steps: starting the process and performing preparatory work before the wafer etching process, that is, step S210, in which the disk is electrostatically adsorbed by the electrostatic chuck and the atmosphere required for the process is stabilized. Then, proceeding to step S220, the wafer main process etching sub-step, in step S220, the wafer having prepared the mask is mainly etched by using the plasma etching gas. Unlike the prior art, the duration of step S220 is less than the original single main process etch step, preferably much smaller than the original single main process etch step.
  • step S230 in which the electrostatic chucking of the disk by the electrostatic chuck is released.
  • step S240 determining the cumulative time predetermined threshold value of all the main process etching sub-steps performed before, specifically, whether the time required for the main process etching is reached, and if the result of the determination is "Yes", then Proceeding to step S250, the wafer is brought into contact with the ground to perform complete release of static electricity; if the result of the determination is "NO", it means that the accumulation time of the main process etching substep does not meet the requirements of the main process etching, and the steps are re
  • step S210 the wafer is again adsorbed by the electrostatic chuck (RECHUCK), and the atmosphere required for the main process is stabilized; then the wafer main process etching sub-step is performed, and the cycle is continued until the accumulation time of all the main process etching sub-steps When the accumulation time required for the main process etching
  • the entire process adopts a step-by-step etching principle, and a single etching is changed into an etching sub-step of several steps, and an electrostatic discharge step is added after each small etching process to avoid the wafer.
  • Continuous contact with the electrostatic chuck long-term plasma bombardment to make the surface temperature of the wafer become higher, the loss rate of the photoresist increases, the surface paste of the wafer is generated, and even the PR is etched clean.
  • the method can also reduce the amount of surface static accumulation generated by the wafer for a long time process.
  • the embodiment increases the contact between the wafer and the ground after the final etching process. Compared to Example 1, the electrostatic discharge was more completely complete, resulting in fewer positional debris after the wafer process.
  • Embodiment 3 is basically the same as Embodiment 1. The difference between the two is that in the present embodiment, the time of each main process etching sub-step is less than or equal to 30 minutes.
  • Embodiment 1 changing the main process etching step into a plurality of main art etching sub-steps can improve the problem of paste position and debris of the chuck position caused by electrostatic accumulation.
  • the duration of the etching sub-step may also be relatively long, and there may be a slight problem of paste and debris at the chuck position.
  • the time of each main process etching sub-step is less than or equal to 30 minutes to solve the above problem.
  • Embodiment 4 is basically the same as Embodiment 2. The difference between the two is that in the present embodiment, the time of each main process etching sub-step is less than or equal to 30 minutes to achieve a superior effect.
  • the time of each main process etching sub-step is less than or equal to 30 minutes, and the surface paste of the wafer can be completely prevented.
  • the electrostatic discharge step one avoids the long-term contact between the wafer and the electrostatic chuck, and the temperature of the wafer surface is increased due to plasma bombardment, thereby causing the problem of the wafer paste.
  • the second is to release the static electricity accumulated on the wafer during the long-term process to avoid debris from the electrostatic chuck.
  • the time of electrostatic discharge will be related to the decrease of the surface temperature of the wafer and the degree of electrostatic discharge. Too short electrostatic discharge time is not conducive to the surface temperature of the wafer is reduced; too long electrostatic discharge time makes the surface temperature of the wafer effectively reduce, after the effective release of static electricity, the process time is wasted, resulting in too long process time. , reducing production efficiency. Therefore, the time for electrostatic discharge can be 1 to 2 minutes.
  • This embodiment is a further improvement of the above embodiment.
  • the above embodiment employs a cyclic etching sub-step method to reduce the temperature of the wafer, in the course of the main etching process, the problem of excessive temperature of the wafer may still occur. If only relying on the addition of the etching sub-step and the electrostatic discharge to reduce the wafer temperature, for example, the entire process time is increased, or even too long, the overall production efficiency is lowered.
  • helium gas flow is used throughout the main process (He Flow) Cools the wafer to maintain a good cooling effect on the wafer. That is, the wafer is cooled by a helium gas flow in each process etching sub-step.
  • the back side of the wafer is cooled by a helium gas flow, so that the entire main process etching process is not affected, so that the etching is not affected at all.
  • the gas pressure of the helium gas stream can be 1.5 mbar (mbar).

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Abstract

一种深沟槽刻蚀工艺中圆片的刻蚀方法，包括如下步骤：a.利用静电吸盘对圆片进行静电吸附，并稳定工艺所需要的气氛（S110）；b.进行圆片主工艺子步骤，所述主工艺子步骤的时间小于圆片主工艺要求的时间（S120）；c.解除所述静电吸盘对所述圆片的静电吸附（S130）；d.判断之前进行的所有的所述主工艺子步骤的累积时间是否达到要求，如果判断结果为"是"，则进行步骤e（S150），如果判断结果为"否"，则再次进行步骤a至步骤c的操作（S140）；e.圆片制造结束（S150）。该刻蚀方法避免圆片持续与静电吸盘接触，减少了圆片表面静电积聚，从而解决了DSIE工艺中圆片表面糊胶的问题。

Description

深沟槽刻蚀工艺中圆片的刻蚀方法
【技术领域】
本发明涉及一种半导体制造工艺领域，尤其涉及一种深沟槽刻蚀工艺中圆片的刻蚀方法。
【背景技术】
在半导体制造工艺中，通常在圆片上刻蚀形成沟槽。在一些特殊的应用领域中，例如集成电路所使用的半导体器件，需要刻蚀较深的沟槽。深沟槽刻蚀（deep silicon trench etching, DSIE）工艺是一种用来蚀刻深沟槽的刻蚀方法。该工艺主要使用薄片作为衬底片，以光刻胶（photoresist, PR）作为掩蔽层，通过该刻蚀工艺在薄片上实现图形的转移，实现某些特殊的功能。
对于现有的DSIE工艺，由于DSIE工艺时间长、刻蚀深度深（深度可达几百μm），并且存在着PR厚度限制，在深沟槽刻蚀后，在圆片表面常常出现糊胶的现象，甚至在圆片上出现局部光刻胶被刻蚀干净的现象。上述的两个现象导致工艺后圆片图形不完整，尺寸出现很大的偏差和不规则、工艺后圆片表面光刻胶难以去除的问题。同时由于光刻胶保护不足，严重限制了DSIE刻蚀深度继续满足更多工艺需求的目的。因此，DSIE工艺后圆片表面糊胶的问题成为某些产品研发的工艺瓶颈。
为了解决在DSIE中使用光刻胶而导致的圆片表面糊胶，工艺后圆片图形不完整、圆片表面光刻胶难以去除的问题。现有技术中提出了改用SiO2或者SiN作为刻蚀掩蔽层取代光刻胶，以试图规避由于使用光刻胶作为掩膜层而导致的各种问题。但使用SiO2或者SiN作为刻蚀掩蔽层实际上并没有真正意义上的解决用光刻胶作为掩蔽层导致的工艺中圆片表面糊胶的问题，并且还带来了新的问题。采用SiO2或者SiN作为掩蔽层，在DSIE工艺后SiO2和SiN无法去除干净，同时在圆片表面会出现碎片的情况，这也进一步限制了更加广泛的应用DSIE工艺的需求。
【发明内容】
基于此，有必要提供一种能在DSIE工艺中防止圆片表面糊胶的深沟槽刻蚀工艺中圆片的刻蚀方法。
一种深沟槽刻蚀工艺中圆片的刻蚀方法，包括如下步骤：
a. 利用静电吸盘对圆片进行静电吸附；
b. 进行圆片主工艺子步骤，所述进行主工艺子步骤的时间小于圆片主工艺要求的时间；
c. 解除所述静电吸盘对所述圆片的静电吸附；
d. 判断所述主工艺子步骤的累积时间是否达到预定阀值，如果是，则进行步骤e；如果否，则再次进行步骤a至步骤c的操作；
e. 圆片制造结束。
在其中一个实施例中，在进行步骤e之前，还包括:
f. 将所述圆片与地极接触，进行静电释放。
在其中一个实施例中，在步骤d中的所述预定阀值为所述圆片主工艺要求的时间。
在其中一个实施例中，所述步骤a至所述步骤c的操作至少循环2次。
在其中一个实施例中，所述主工艺子步骤的时间小于等于30分钟。
在其中一个实施例中，所述静电释放的时间为1~2分钟。
在其中一个实施例中，在所述主工艺子步骤的过程中，利用氦气流对所述圆片进行冷却。
在其中一个实施例中，所述氦气流是对所述圆片的背部进行冷却。
在其中一个实施例中，所述氦气流的气流强度为1.5mbar。
在其中一个实施例中，所述主工艺为刻蚀。
在其中一个实施例中，所述刻蚀为利用等离子态的刻蚀气体对已经制备好掩膜的圆片进行刻蚀。
在其中一个实施例中，在所述步骤e后，还包括对所述圆片进行传输的步骤。
上述深沟槽刻蚀工艺中圆片的刻蚀方法采用了分步刻蚀的原则，并增加了静电释放步骤。避免圆片持续与静电吸盘接触，长时间接受等离子体轰击而使圆片表面温度变高，产生圆片表面糊胶的现象。
【附图说明】
图1为实施例1的深沟槽刻蚀工艺中圆片的刻蚀方法的流程图；
图2是实施例2的深沟槽刻蚀工艺中圆片的刻蚀方法的流程图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施的限制。
实施例1
图1示出了实施例1的深沟槽刻蚀工艺中圆片的刻蚀方法的流程图。实施例1中，将常规的单一的圆片主工艺刻蚀步骤分成若干个主工艺刻蚀子步骤。圆片主工艺步骤即为对圆片进行刻蚀的步骤。圆片主工艺要求的时间为完成圆片刻蚀所需要的时间。圆片主工艺子步骤为将圆片进行刻蚀的步骤分成若干个子步骤，即分多次进行圆片刻蚀，多次刻蚀中的一次刻蚀称为一个圆片主工艺子步骤。子步骤的时间小于单一的主工艺刻蚀步骤。在本实施例中，子步骤的时间为远远小于单一的主工艺刻蚀步骤，在每一个主工艺刻蚀子步骤结束后，对圆片进行静电释放（dechuck）步骤，然后再次利用静电吸盘吸附圆片，并重新稳定工艺气氛，以便进行下一步主刻蚀子步骤，下一步刻蚀子步骤结束后，再次对圆片进行静电释放，如此循环，直到之前进行的所有主工艺刻蚀子步骤的累积时间达到预定阀值。
具体而言，实施例1包括如下步骤：首先进行圆片刻蚀工艺前的准备工作，即步骤S110，在该步骤中，利用静电吸盘（E-CHUCK）对圆片进行静电吸附，并稳定工艺所需要的气氛。然后进行步骤S120，圆片主工艺刻蚀子步骤，在步骤S120中主要利用等离子态的刻蚀气体对已经制备好掩膜的圆片进行刻蚀。S120的持续时间小于单一的主工艺刻蚀步骤。优选为远远小于原先的单一的主工艺刻蚀步骤。即在深沟槽刻蚀工艺中圆片的刻蚀方法中，所述圆片主工艺刻蚀子步骤至少重复一次。在主工艺子步骤S120结束后，进行步骤S130，在该步骤中，解除静电吸盘对圆片的静电吸附，并进行静电释放。接下来进行步骤S140，判断之前进行的所有主工艺刻蚀子步骤的累积时间是否达到预定阀值，具体来说，是否达到主工艺刻蚀所要求的累积时间，如果判断的结果为“是”，则进入步骤S150，完成圆片刻蚀。如果判断的结果为“否”，则说明主工艺刻蚀子步骤的累积时间没有达到主工艺刻蚀的要求，步骤重新回到步骤S110，圆片重新被静电吸盘吸附（RECHUCK），并稳定主工艺所需要的气氛；然后进行圆片主工艺刻蚀子步骤，在步骤S120中主要利用等离子态的刻蚀气体对已经制备好掩膜的圆片进行刻蚀。在主工艺子步骤S120结束后，进行到步骤S130，解除静电吸盘对圆片的静电吸附。接下来进行到步骤S140，再一次判断之前进行的所有主工艺刻蚀子步骤的累积时间是否达到主工艺刻蚀所要求的累积时间，以此循环，直到所有主工艺刻蚀子步骤的累积时间达到主工艺刻蚀所要求的时间，则进行到步骤S150，完成圆片刻蚀，再将圆片进行下一步操作，如传输传出主工艺腔体。
从实施例1中可见，整个工艺过程采用分步刻蚀原则，将单一的刻蚀改成若干步循环的刻蚀子步骤，在每一小步刻蚀工艺结束后增加静电释放步骤，避免圆片持续与静电吸盘（E-CHUCK）接触，长时间接受等离子（plasma）轰击而使圆片表面温度变高，光刻胶（PR）损失速率增大，产生圆片表面糊胶，甚至PR被刻蚀干净的现象。
此外，该方法可以减少圆片长时间工艺产生的表面静电积聚的数量保证圆片工艺结束后静电释放不净而偏离静电吸盘位置碎片。
实施例2
图2示出了实施例2的深沟槽刻蚀工艺中圆片的刻蚀方法的流程图。实施例2与实施例1基本相同，将常规的单一的圆片主工艺刻蚀步骤分成若干个主工艺刻蚀子步骤，子步骤的时间远远小于原先的单一的主工艺刻蚀步骤，在每一个主工艺刻蚀子步骤结束后，对圆片进行静电释放（DECHUCK）步骤，然后再次利用静电吸盘吸附圆片，并重新稳定工艺气氛，以便进行下一步主刻蚀子步骤，下一步刻蚀子步骤结束后，再次对圆片进行静电释放，如此循环，直到之前进行的所有主工艺刻蚀子步骤的累积时间达到预定阀值。实施例2与实施例1的不同之处在于：当判断所有主工艺刻蚀子步骤的累积时间达到预定阀值后，还包括将圆片与地极接触，使得圆片中的静电完全的释放，再将圆片进行下一步操作，如传输传出主工艺腔体。
具体地，实施例2包括如下步骤：开始流程，进行圆片刻蚀工艺前的准备工作，即步骤S210，在该步骤中，利用静电吸盘对圆片进行静电吸附，并稳定工艺所需要的气氛。然后进入步骤S220，圆片主工艺刻蚀子步骤，在步骤S220中主要利用等离子态的刻蚀气体对已经制备好掩膜的圆片进行刻蚀。与现有技术不同的是，步骤S220的持续时间小于原先的单一的主工艺刻蚀步骤，优选为远远小于原先的单一的主工艺刻蚀步骤。在主工艺子步骤S220结束后，进行到步骤S230，在该步骤中，解除静电吸盘对圆片的静电吸附。接下来进行到步骤S240，判断之前进行的所有主工艺刻蚀子步骤的累积时间预定阀值，具体来说，是否达到主工艺刻蚀所要求的时间，如果判断的结果为“是”，则进行到步骤S250，使得圆片与地极接触，进行静电的完全释放；如果判断的结果为“否”，则说明主工艺刻蚀子步骤的累积时间没有达到主工艺刻蚀的要求，步骤重新回到步骤S210，圆片重新被静电吸盘吸附（RECHUCK），并稳定主工艺所需要的气氛；然后进行圆片主工艺刻蚀子步骤，如此循环，直到所有主工艺刻蚀子步骤的累积时间达到主工艺刻蚀所要求的累积时间，则进行到步骤S250，使得圆片与地极接触，进行静电的完全释放。最后进入步骤S260，完成圆片刻蚀。后续可以进行圆片的传输。
在该实施例中，整个工艺过程采用分步刻蚀原则，将单一的刻蚀改成若干步循环的刻蚀子步骤，在每一小步刻蚀工艺结束后增加静电释放步骤，避免圆片持续与静电吸盘接触，长时间接受等离子轰击而使圆片表面温度变高，光刻胶损失速率增大，产生圆片表面糊胶，甚至PR被刻蚀干净的现象。
同时，该方法还可以减少圆片长时间工艺产生的表面静电积聚的数量，此外该实施例在最后的刻蚀工艺结束后除了常规的静电释放外，还增加了圆片与地极的接触，相比与实施例1，静电释放更加完全彻底，使得圆片工艺结束后位置碎片更少。
实施例3
实施例3与实施例1基本相同。两者的不同之处在于：在本实施例中，每一个主工艺刻蚀子步骤的时间小于等于30分钟。
在实施例1中，将主工艺刻蚀步骤改成若干个主艺刻蚀子步骤能够改进糊胶问题和静电聚积造成的吸盘位置碎片的问题。但由于沟槽的深度较深，刻蚀子步骤的持续时间也可能比较长，还可能存在轻微的糊胶问题和吸盘位置碎片的问题。在本实施例中，每一个主工艺刻蚀子步骤的时间小于等于30分钟，以解决上述问题。
实施例4
实施例4与实施例2基本相同。两者的不同之处在于：在本实施例中，每一个主工艺刻蚀子步骤的时间小于等于30分钟，以实现较优的效果。
在本实施例中，每一个主工艺刻蚀子步骤的时间小于等于30分钟，可以完全防止圆片表面糊胶。同时，通过静电释放步骤，一是避免了圆片与静电吸盘的长时间接触，接受等离子轰击而导致的圆片表面温度升高，进而产生的圆片糊胶的问题。二是对圆片长时间工艺中累积的表面静电进行释放，以避免静电吸盘产生碎片。
其中，静电释放的时间将与圆片表面温度的降低以及静电释放的程度有关。过短的静电释放时间不利于圆片表面温度降低；过长的静电释放时间使得在圆片表面温度有效降低后，静电有效释放后，工艺流程时间无谓的浪费，从而导致整个工艺流程时间过长，降低了生产效率。因此，静电释放的时间可以为1~2分钟。
实施例5
本实施例是对上述实施例的进一步改进。上述实施例虽然采用了循环的刻蚀子步骤的方法来降低圆片的温度，但在主刻蚀工艺的过程中，仍然可能出现圆片温度过高的问题。如果仅仅依靠增加刻蚀子步骤，以及静电释放来降低圆片温度，比如导致整个工艺时间增加，甚至过长，降低整体生产效率。
因此，在本实施例中，在整个主工艺过程中采用氦气流（He Flow）对圆片进行冷却，保持圆片整体良好的冷却效果。即，在每个工工艺刻蚀子步骤中采用氦气流对圆片进行冷却。
其中，采用氦气流对圆片背面进行冷却，这样不至于影响整个主工艺刻蚀过程，可使得刻蚀不受任何的影响。
其中，氦气流的气压强度过低将起不到冷却的效果，氦气流气压强度过高将可能冲击圆片，影响刻蚀工艺中的圆片的稳定性。因此，氦气流的气压强度为可以为1.5mbar（毫巴）。
应当知道，上述的各个实施例之间并不是相互排斥的，本领域技术人员完全可以结合不同的实施例以获得最优的效果。还应当知道，虽然在本发明的实施例中，采用了刻蚀说明了主工艺步骤，但这只是一种例举而非限定，该主工艺步骤可以是相同的工艺步骤，也可以是不同工艺步骤的组合，只要是在深沟槽刻蚀工艺任何长时间工作而导致晶片制造效果不佳的工艺，均可以是主工艺步骤。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种深沟槽刻蚀工艺中圆片的刻蚀方法，其特征在于，包括如下步骤：
    a. 利用静电吸盘对圆片进行静电吸附；
    b. 进行圆片主工艺子步骤，所述进行主工艺子步骤的时间小于圆片主工艺要求的时间；
    c. 解除所述静电吸盘对所述圆片的静电吸附；
    d. 判断所述主工艺子步骤的累积时间是否达到预定阀值，如果是，则进行步骤e；如果否，则再次进行步骤a至步骤c的操作；
    e. 圆片制造结束。
  2. 根据权利要求1所述的刻蚀方法，其特征在于，在进行步骤e之前，还包括:
    f. 将所述圆片与地极接触，进行静电释放。
  3. 根据权利要求1所述的刻蚀方法，其特征在于，在步骤d中的所述预定阀值为所述圆片主工艺要求的时间。
  4. 根据权利要求1所述的刻蚀方法，其特征在于，所述步骤a至所述步骤c的操作至少循环2次。
  5. 根据权利要求1所述的刻蚀方法，其特征在于，所述主工艺子步骤的时间小于等于30分钟。
  6. 根据权利要求1所述的刻蚀方法，其特征在于，所述静电释放的时间为1~2分钟。
  7. 根据权利要求1所述的刻蚀方法，其特征在于，在所述主工艺子步骤的过程中，利用氦气流对所述圆片进行冷却。
  8. 根据权利要求7所述的刻蚀方法，其特征在于，所述氦气流是对所述圆片的背部进行冷却。
  9. 根据权利要求7所述的刻蚀方法，其特征在于，所述氦气流的气流强度为1.5mbar。
  10. 根据权利要求1所述的刻蚀方法，其特征在于，所述主工艺为刻蚀。
  11. 根据权利要求10所述的刻蚀方法，其特征在于，所述刻蚀为利用等离子态的刻蚀气体对已经制备好掩膜的圆片进行刻蚀。
  12. 根据权利要求1所述的刻蚀方法，其特征在于，在所述步骤e后，还包括对所述圆片进行传输的步骤。
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