WO2014097857A1 - 撮像素子、撮像装置、電子機器、閾値算出装置および撮像方法 - Google Patents
撮像素子、撮像装置、電子機器、閾値算出装置および撮像方法 Download PDFInfo
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Definitions
- This technology relates to an image sensor. More specifically, the present invention relates to an imaging device, an imaging device, an electronic device, and a threshold value calculation device and an imaging method for an imaging device that detect weak light.
- CMOS Complementary Metal Oxide Semiconductor
- This technology was created in view of such a situation, and aims to improve the accuracy of determination of photons incident on a pixel.
- the present technology has been made to solve the above-described problems.
- the first aspect of the present technology is based on the signal output from the pixel, and the charge accumulated by the photons incident on the pixel during the exposure period.
- an image pickup device, an image pickup apparatus, an electronic apparatus, and an image pickup method including a determination unit that compares the generated digital value with the generated digital value to determine the incidence of a photon on a pixel that outputs the signal.
- the threshold value set for each pixel having similar conversion efficiency when converting into a digital value is compared with the digital value, and the photon incidence determination is performed.
- the signal processing apparatus may further include an amplifying unit that amplifies the signal at a magnification larger than 1, and the generation unit may perform the generation based on the amplified signal.
- the generation unit may perform the generation based on the amplified signal.
- the amplification unit is provided for each pixel, and the determination unit sets the magnification at the time of amplifying the signal as the conversion efficiency, and sets a threshold value set for each pixel.
- the above determination may be performed using the above.
- a digital value is generated based on the signal amplified by the amplifying unit provided for each pixel, and the generated digital value is compared with a threshold value to determine the incidence of photons.
- the amplifying unit may be configured by a common source amplifier transistor provided for each pixel.
- a digital value is generated based on the signal amplified by the common-source amplifier transistor provided for each pixel, and the generated digital value is compared with a threshold value to determine the incidence of photons. Bring.
- the amplifying unit is provided in units of columns with respect to the pixels arranged in a matrix, and the determining unit uses a magnification when the signal is amplified as the conversion efficiency.
- the determination may be performed using a threshold value set for each column unit.
- a digital value is generated based on the signal amplified by the amplifying unit provided for each column, and the generated digital value is compared with a threshold set for each column to determine the incidence of photons. It brings about the effect that is performed.
- the amplifying unit may be composed of an operational amplifier or a CMOS (Complementary Metal Oxide Semiconductor) inverter.
- CMOS Complementary Metal Oxide Semiconductor
- the amplifying unit includes a feedback circuit for feeding back the potential in the signal to the potential in the floating diffusion of the pixel that has output the signal. This brings about the effect
- pixels having similar conversion efficiencies are threshold designation values for designating the threshold with fewer bits than the number of bits necessary to indicate the digital value generated by the generation unit.
- a holding unit that holds each of the pixels, and the determination unit obtains the threshold specification value of the pixel that outputs the signal converted into the digital value to be determined, and the digital value and the threshold specification value
- the threshold value may be set by converting the acquired specified threshold value into a gradation value of the digital value on the basis of a table indicating the association. This brings about the effect that the threshold value is set by converting the threshold value specified by the holding unit into a digital gradation value.
- the threshold value is acquired by acquiring a digital value obtained by converting a reset signal, which is a signal in a state where there is no charge accumulation due to photons, for each pixel having a similar conversion efficiency.
- a reset signal which is a signal in a state where there is no charge accumulation due to photons
- it may be calculated based on a standard deviation and an average value calculated from a plurality of digital values.
- the threshold value is calculated based on the standard deviation and the average value of the digital values obtained by converting the reset signal.
- a generation unit that generates a digital value indicating the amount of charge accumulated by photons incident on the pixel during an exposure period based on a signal output from the pixel, and the pixel
- the threshold value set for each pixel having a similar conversion efficiency when converting the amount of charge accumulated in the generation unit into a digital value generated by the generation unit is compared with the generated digital value
- a determination unit that determines the incidence of a photon on a pixel that outputs a signal.
- a digital value obtained by converting a reset signal that is a signal in a state where there is no charge accumulation due to photons is obtained a plurality of times for each pixel having similar conversion efficiency, and the obtained plurality of digital You may make it further comprise the calculation part which calculates the said threshold value based on the standard deviation and average value of a value.
- the threshold value is calculated based on the standard deviation and average value of the digital values obtained by converting the reset signal.
- a generation unit that generates a digital value indicating the amount of charge accumulated by photons incident on the pixel during an exposure period based on a signal output from the pixel; and the pixel And comparing the generated digital value with a threshold value set for each pixel having similar conversion efficiency when converting the amount of charge accumulated in the digital value generated by the generating unit.
- An acquisition unit that acquires the digital value generated by the imaging device including a determination unit that determines the incidence of photons on the output pixel for each pixel with similar conversion efficiency; and the acquired digital value And a calculation unit that calculates the threshold based on a standard deviation and an average value. Thereby, the threshold value is calculated based on the standard deviation and the average value of the digital values.
- the signal may be a reset signal in a state where there is no charge accumulation due to photons. This brings about the effect that the threshold value is calculated based on the standard deviation and average value of the digital value generated from the reset signal in a state where there is no charge accumulation due to photons.
- the signal is a signal in a state where electric charges are accumulated by photons
- the acquisition unit acquires the digital value generated by the exposed image sensor a plurality of times. May be executed a plurality of times with different exposure amounts, and the calculation unit may calculate the threshold value from the standard deviation and the average value obtained for each exposure amount. This brings about the effect that the threshold value is calculated from the standard deviation and the average value obtained for each exposure amount.
- FIG. 3 is a schematic diagram illustrating an example of a circuit configuration of a pixel 310 according to the first embodiment of the present technology.
- FIG. FIG. 3 is a diagram schematically illustrating an example of a layout of a pixel 310 according to the first embodiment of the present technology.
- 3 is a conceptual diagram illustrating an example of a functional configuration example of a digital value generation circuit 400 and an operation example of the digital value generation circuit 400 according to the first embodiment of the present technology.
- FIG. 5 is a graph showing the relationship between the average number of photons incident on each pixel during a unit exposure period and the count probability in the first embodiment of the present technology. It is a figure which shows typically the effect of performing binary determination using the adjustment value for every pixel currently hold
- FIG. 3 is a functional configuration diagram for describing an example of a method for calculating an adjustment value when the adjustment value holding unit 210 of the image sensor 100 holds the adjustment value in the first embodiment of the present technology.
- Fig. 18 is a flowchart illustrating an example of a processing procedure of adjustment value calculation by an adjustment value calculation unit 551 of the adjustment device 550 according to the first embodiment of the present technology. It is a figure which shows typically an example of the circuit structural example of the amplifier part 440 of the operational amplifier shown as the 1st modification of 1st Embodiment of this technique. 12 is a timing chart illustrating an example of operations of an amplifier circuit 460 and a digital value generation circuit 400 illustrated as a first modification of the first embodiment of the present technology.
- FIG. 12 is a table for comparing the ramp waveform of the REF signal in the first modification of the first embodiment of the present technology with the ramp waveform of the REF signal in another imaging device. It is a figure which shows typically an example of the circuit structural example of the amplifier circuit (amplifier circuit 710) of the inverter shown as a 2nd modification of 1st Embodiment of this technique.
- a mimetic diagram showing an example of circuit composition of a pixel (pixel 830) in an example which feeds back an output of a pixel to a floating diffusion shown as a 3rd modification of a 1st embodiment of this art. It is a mimetic diagram showing an example of circuit composition of a pixel (pixel 840) in an example which feeds back an output of a pixel to a drain terminal of an amplifier transistor shown as a 4th modification of a 1st embodiment of this art.
- FIG. 820 It is a schematic diagram which shows.
- First Embodiment (Imaging Control: Example of Performing Binary Determination of Photon Incidence Using Threshold for Each Pixel) 2. Second Embodiment (Imaging Control: Example of Obtaining a Threshold for Each Pixel from a Digital Value of Exposed Pixel)
- FIG. 1 is a conceptual diagram illustrating an example of a basic configuration example of the image sensor 100 according to the first embodiment of the present technology.
- the image sensor 100 is a light detector provided in a system for detecting faint light (for example, an imaging plate fluorescent scanner, a radiation scintillation counter, etc.).
- the image sensor 100 is realized by, for example, a CMOS (Complementary Metal Metal Oxide Semiconductor) sensor.
- the image sensor 100 is used in place of a conventional photomultiplier tube, avalanche photodiode, or photodiode.
- the image sensor 100 includes a pixel array unit 300, a vertical drive circuit 110, an amplifier unit 440, a digital value generation circuit 400, a register 130, an adjustment value holding unit 210, a binary determination unit 220, and an output circuit 150. Is provided.
- the pixel array unit 300 includes a plurality of pixels (pixels 310) arranged in a two-dimensional matrix (n ⁇ m). In the first embodiment of the present technology, it is assumed that the pixels 310 of 128 rows ⁇ 128 columns are arranged in the pixel array unit 300. In the pixel array unit 300 shown in FIG. 1, a part of the pixels 310 of 128 rows ⁇ 128 columns is shown. Control lines (control lines 330) are wired from the vertical drive circuit 110 to the pixels 310 arranged in the pixel array unit 300 in units of rows.
- the pixel 310 is provided with a vertical signal line (vertical signal line 341) in a column unit (column unit). Note that the circuit configuration of the pixel 310 will be described with reference to FIG.
- the vertical drive circuit 110 supplies a signal to the pixel 310 via the control line 330, and sequentially scans the pixel 310 in units of rows in the vertical direction (column direction). By performing selective scanning in units of rows by the vertical drive circuit 110, signals are output from the pixels 310 in units of rows.
- the control line 330 includes a pixel reset line 331 and a charge transfer line 332. Since the pixel reset line 331 and the charge transfer line 332 will be described with reference to FIG. 2, description thereof is omitted here.
- the amplifier unit 440 amplifies the signal output from the pixel 310 by N times (magnification greater than 1 (N> 1)).
- the amplifier unit 440 is realized by an operational amplifier connected between the pixel 310 and the digital value generation circuit 400, for example. Further, when the amplification factor of the amplifier transistor of the pixel 310 is large, an operational amplifier is not connected between the pixel 310 and the ACDS unit 410, and the amplifier unit 440 is realized by the amplifier transistor of the pixel 310.
- various examples of the amplifier unit 440 will be described with reference to FIGS. 10 to 20 as modifications of the first embodiment of the present technology, and thus detailed description thereof will be omitted.
- description will be made assuming an operational amplifier (for example, see FIG. 12) connected between the pixel 310 and the ACDS unit 410.
- the amplifier unit 440 is realized by an operational amplifier, a difference between a reference voltage arbitrarily set using resistance division or capacitance division and a signal (reset signal or accumulation signal) output from the pixel 310 is an amplifier. Amplified by the unit 440. Note that since the amplifier unit 440 is provided between the pixel 310 and the ACDS unit 410 or is an amplifier transistor of the pixel, an offset generated in the pixel 310 such as kTC noise is also amplified and output. Further, the random noise generated in the pixel is also amplified and output by the amplifier unit 440. The output of the amplifier unit 440 includes the offset of the amplifier unit 440 itself. The amplifier unit 440 supplies the amplified signal to the digital value generation circuit 400.
- the amplifier unit 440 is an example of an amplification unit described in the claims.
- the digital value generation circuit 400 generates a digital value indicating the amount of light incident on the pixel 310 (the amount of charge accumulated in the pixel by photons) based on the output signal amplified by the amplifier unit 440.
- the digital value generation circuit 400 is provided for each vertical signal line 341. That is, the image sensor 100 includes 128 digital value generation circuits 400 connected to 128 vertical signal lines 341 respectively wired to pixels (32 rows ⁇ 128 columns) driven by the vertical drive circuit 110. .
- the digital value generation circuit 400 generates a digital value by substantially removing the offset component generated in the pixel 310 and the amplifier unit 440, but generates a digital value without removing the random noise generated in the pixel.
- the digital value generation circuit 400 supplies the generated digital value to the register 130 connected to each digital value generation circuit 400.
- the digital value generation circuit 400 is an example of a generation unit described in the claims.
- the register 130 is provided for each digital value generation circuit 400, and temporarily holds the digital value supplied from the digital value generation circuit 400.
- the register 130 sequentially outputs the digital values to be held to the binary determination unit 220 during the period (readout period) in which the signal of the next row of pixels is read out.
- the adjustment value holding unit 210 holds a value (adjustment value) indicating a threshold necessary for binary determination of digital values sequentially supplied from the register 130.
- the threshold value indicated by the adjustment value is a value set between a digital value when no photon is incident on the pixel and a digital value when one photon is incident on the pixel.
- the difference between the digital value when no photon is incident and the digital value when one photon is incident is the conversion efficiency of the accumulated charge into a digital value (how much is converted into a digital value) Depending on the value).
- the adjustment value holding unit 210 holds an adjustment value for designating such a threshold value for each pixel.
- the adjustment value is set so that the threshold value can be specified with a small number of gradation values with respect to a multi-value (multi-gradation) digital value. That is, the adjustment value is set so that the threshold digital value can be specified with a smaller number of bits than the number of bits necessary to indicate the digital value. Since the adjustment value will be described with reference to FIG. 5, the description thereof is omitted here.
- the adjustment value holding unit 210 is configured by a semiconductor recording device. For example, when the adjustment value is held in the manufacturing process of the image sensor 100 and is not changed during use, the adjustment value holding unit 210 is realized by a nonvolatile memory. Further, when the threshold value is detected and held during use of the image sensor 100 or before the start of use, it is realized by a rewritable volatile memory such as SRAM (Static Random Access Memory). For example, when a 4-bit adjustment value is set for each of the pixels 310 of 128 rows ⁇ 128 columns, an adjustment value holding unit 210 having a capacity of 64 Kbits is provided in the image sensor 100.
- SRAM Static Random Access Memory
- the adjustment value holding unit 210 For the adjustment value holding unit 210, an example in which the adjustment value holding unit 210 holds an adjustment value for each pixel will be described in the first embodiment of the present technology. If the same threshold value can be set because the conversion efficiency is the same in a predetermined group unit (for example, column unit), the adjustment value may be set in a group unit (for example, column unit). Is possible.
- the adjustment value holding unit 210 is an example of a holding unit described in the claims.
- the binary determination unit 220 binary-determines whether or not a photon is incident on a pixel that outputs a signal converted to the digital value, based on the digital value sequentially supplied from the register 130.
- the binary determination unit 220 acquires an adjustment value for a pixel that has output a signal that is a binary determination target digital value from the adjustment value holding unit 210.
- the binary determination unit 220 converts the acquired adjustment value into a digital gradation value using a look-up table indicating the relationship between the adjustment value and the digital gradation value.
- the binary determination unit 220 determines a binary determination target digital value using the converted gradation value of the digital value as a threshold value.
- the binary determination unit 220 supplies the determination result (binary value) to the output circuit 150.
- the binary determination unit 220 is an example of a determination unit described in the claims.
- the output circuit 150 outputs a signal generated by the image sensor 100 to an external circuit.
- FIG. 2 is a schematic diagram illustrating an example of a circuit configuration of the pixel 310 according to the first embodiment of the present technology.
- the pixel 310 converts an optical signal that is incident light into an electrical signal by performing photoelectric conversion.
- the pixel 310 amplifies the converted electric signal and outputs it as a pixel signal.
- the pixel 310 amplifies an electric signal by an FD amplifier having a floating diffusion layer (floating diffusion: FD).
- the pixel 310 includes a photodiode 311, a transfer transistor 312, a reset transistor 313, and an amplifier transistor 314.
- the photodiode 311 has its anode terminal grounded and its cathode terminal connected to the source terminal of the transfer transistor 312.
- the transfer transistor 312 has a gate terminal connected to the charge transfer line 332 and a drain terminal connected to the source terminal of the reset transistor 313 and the gate terminal of the amplifier transistor 314 via the floating diffusion (FD 322).
- the reset transistor 313 has its gate terminal connected to the pixel reset line 331 and its drain terminal connected to the power supply line 323 and the drain terminal of the amplifier transistor 314.
- the source terminal of the amplifier transistor 314 is connected to the vertical signal line 341.
- the photodiode 311 is a photoelectric conversion element that generates an electric charge according to the intensity of light.
- a pair of electrons and holes is generated by photons incident on the photodiode 311, and the generated electrons are stored here.
- the transfer transistor 312 transfers electrons generated in the photodiode 311 to the FD 322 according to a signal (transfer pulse) from the vertical drive circuit 110. For example, when a signal (pulse) is supplied from the charge transfer line 332 supplied to the gate terminal of the transfer transistor 312, the transfer transistor 312 becomes conductive and transfers electrons generated in the photodiode 311 to the FD 322.
- the reset transistor 313 is for resetting the potential of the FD 322 in accordance with a signal (reset pulse) supplied from the vertical drive circuit 110.
- the reset transistor 313 becomes conductive when a reset pulse is supplied to the gate terminal via the pixel reset line 331, and a current flows from the FD 322 to the power supply line 323.
- this potential is referred to as a reset potential. Note that when the photodiode 311 is reset, the transfer transistor 312 and the reset transistor 313 are simultaneously turned on.
- a potential (power supply) flowing through the power supply line 323 is a power supply used for resetting and a source follower, and for example, 3 V is supplied.
- the amplifier transistor 314 is for amplifying the potential of the floating diffusion (FD 322) and outputting a signal (output signal) corresponding to the amplified potential to the vertical signal line 341.
- the amplifier transistor 314 shown in FIG. 2 is a source follower type amplifier transistor, and the amplification factor is close to 1.
- the amplifier transistor 314 When the potential of the floating diffusion (FD 322) is reset (in the case of the reset potential), the amplifier transistor 314 outputs an output signal (hereinafter referred to as a reset signal) corresponding to the reset potential vertically. Output to the signal line 341.
- the amplifier transistor 314 outputs an output signal (hereinafter referred to as an accumulated signal) corresponding to the amount of transferred electrons to the vertical signal. Output to line 341.
- an output signal hereinafter referred to as an accumulated signal
- a selection transistor may be inserted for each pixel between the amplifier transistor 314 and the vertical signal line 341.
- the basic circuit and operation mechanism of the pixel as shown in FIG. 2 are the same as those of a normal pixel, and various other variations are possible.
- the pixel assumed in the present technology is designed so that the conversion efficiency is significantly higher than that of the conventional pixel.
- the pixel is designed so that the parasitic capacitance (parasitic capacitance of the FD 322) of the gate terminal of the amplifier (amplifier transistor 314) constituting the source follower is effectively reduced to the limit.
- This design can be performed by, for example, a method of devising the layout or a method of feeding back the output of the source follower to a circuit in the pixel (see, for example, JP-A-5-63468 and JP-A-2011-119441).
- FIG. 3 is a diagram schematically illustrating an example of the layout of the pixel 310 according to the first embodiment of the present technology.
- a photodiode 311, an FD 322, and a vertical signal line 341 are shown in the layout of the pixel 310 shown in FIG. 3.
- the gate terminal wiring (gate wiring 362) of the transfer transistor 312, the reset transistor 313 gate terminal wiring (gate wiring 363), and the amplifier transistor 314 gate terminal wiring (gate wiring 364) are shown in FIG. 3.
- the FD 322 is indicated by a thick broken line
- the vertical signal line 341 is indicated by a thin broken line
- the gate wirings 362 to 364 are indicated by hatched rectangles.
- FIG. 3 shows an impurity diffusion layer (diffusion layer 371) corresponding to the drain terminal of the transfer transistor 312, the source terminal of the reset transistor 313, and the wiring between the two terminals.
- FIG. 3 also shows an impurity diffusion layer (diffusion layer 372) corresponding to the drain terminal of the reset transistor 313, the drain terminal of the amplifier transistor 314, and the wiring between the two terminals.
- FIG. 3 shows an impurity diffusion layer (diffusion layer 373) corresponding to the source terminal of the amplifier transistor 314.
- the diffusion layers 371 to 373 are indicated by rectangles with fine dots.
- a contact (contact 382) for connecting the gate wiring 362 to the charge transfer line 332 and a contact (contact 383) for connecting the gate wiring 363 to the pixel reset line 331 are shown. Yes.
- This layout also shows a contact (contact 384) for connecting the gate wiring 364 to the FD 322 and a contact (contact 385) for connecting the diffusion layer 371 to the FD 322.
- a contact (contact 386) for connecting the diffusion layer 372 to the power supply line 323 and a contact (contact 387) for connecting the diffusion layer 373 to the vertical signal line 341 are shown. .
- the layout of the pixel 310 will be described by focusing on the size of the FD 322.
- the layout of the pixel 310 is designed so that the parasitic capacitance in the FD 322 is minimized. Therefore, in the pixel 310, the layout is designed so that the FD 322, which is a wiring portion that connects the diffusion layer 371 to the gate wiring 364, the diffusion layer 371, and the gate wiring 364 have the smallest possible area. In the pixel 310, the width at the drain terminal of the amplifier transistor 314 (near the gate wiring 364 of the diffusion layer 373) is reduced.
- the output signal is sufficiently larger than the random noise, so in principle one photon Can be detected.
- the pixel 310 as shown in FIG. 3 can store a charge of about 1000 e ⁇ in the photodiode 311 when a power supply voltage of about 3 V is supplied, for example.
- the accumulated signal (output signal) is an analog output having an operation range of about 0.6V.
- the magnitude of the signal per electron is about 10 times larger than the conventional one. For this reason, the influence of random noise on the amplifier transistor 314 and the digital value generation circuit 400 is about 1/10. That is, the pixel 310 is suitable for low-illuminance imaging.
- the output signal of the pixel including the photodiode and the amplifier transistor can be handled as binary data or analog data having a gradation when the conversion efficiency is sufficiently high.
- a pixel has a problem that the upper limit (dynamic range) of the detected light amount in one imaging is small.
- it is effective to increase the frame rate by increasing the reading speed of the signal output from the pixel and accumulate the results of reading multiple times. For example, in the case of binary determination of the incidence of photons, if 1023 exposures and readouts are performed and the results are integrated, the dynamic range per pixel becomes 10-bit gradation data.
- the maximum number of accumulated electrons is 1000e ⁇ and the number of photons is determined after analog output, if the results are accumulated by performing 16 exposures and readings, the maximum number of accumulated electrons is 16, Equivalent to the output of a pixel that is 000e-.
- FIG. 3 illustrates an example of a pixel in which one pixel can be detected by designing the pixel so that the parasitic capacitance is effectively reduced to the minimum
- the detection of one photon can be similarly performed by a pixel that amplifies electrons obtained by photoelectric conversion in the pixel.
- a pixel in which a plurality of stages of CCD multiplication transfer elements are embedded between the photodiode in the pixel and the gate terminal of the amplifier transistor is conceivable (see, for example, JP 2008-35015 A).
- the photoelectrically converted electrons are multiplied by about 10 times in the pixel.
- one-photon detection can be performed also by multiplying an image of electrons in a pixel, and an image sensor in which such a pixel is arranged can be used as the image sensor 100.
- FIG. 4 is a conceptual diagram illustrating an example of a functional configuration example of the digital value generation circuit 400 and an operation example of the digital value generation circuit 400 according to the first embodiment of the present technology.
- FIG. 4a as a functional configuration of the digital value generation circuit 400, an amplifier unit 440, an ACDS (AnalogACorrelated Double Sampling) unit 410, a DCDS (Digital CDS) unit 420, It is shown.
- ACDS AnalogACorrelated Double Sampling
- DCDS Digital CDS
- the vertical signal line 341 connected to the digital value generation circuit 400, a part of the pixel 310 connected to the vertical signal line 341, the pixel array unit 300, and the amplifier unit 440 are digital values.
- the functional configuration of the generation circuit 400 is shown.
- the ACDS unit 410 performs offset removal by analog CDS, and includes a switch 412, a capacitor 413, and a comparator 411.
- the switch 412 is a switch for connecting the vertical signal line 341 to either an input terminal for inputting a reference voltage to the comparator 411 or an input terminal for inputting a signal to be compared to the comparator 411.
- the switch 412 connects the vertical signal line 341 to an input terminal (a left terminal to which the capacitor 413 is connected) for inputting a reference voltage.
- the comparator 411 outputs the result of analog CDS
- the switch 412 connects the vertical signal line 341 to an input terminal (right terminal without a capacitor) for inputting a signal to be compared.
- the capacitor 413 is a storage capacitor for sample-holding the reset signal of the pixel 310.
- the comparator 411 outputs the difference between the sampled and held signal and the signal to be compared. That is, the comparator 411 outputs the difference between the reset signal sampled and held and the signal (accumulated signal or reset signal) supplied from the vertical signal line 341. That is, the comparator 411 removes an offset generated in the pixel 310 such as kTC noise or an offset of the amplifier unit 440 from the accumulated signal or the reset signal.
- the comparator 411 is realized by an operational amplifier with a gain of 1, for example.
- the comparator 411 supplies the difference signal to the DCDS unit 420.
- the difference signal between the reset signal and the reset signal is referred to as no signal
- the difference signal between the reset signal and the accumulation signal is referred to as a net accumulation signal.
- the DCDS unit 420 performs offset removal by digital CDS, and includes an AD (Analog Digital) conversion unit 421, a register 422, a switch 423, and a subtractor 424.
- AD Analog Digital
- the AD conversion unit 421 performs AD conversion on the signal supplied from the comparator 411.
- the switch 423 is a switch for switching the supply destination of the signal after AD conversion generated by the AD conversion unit 421.
- the switch 423 supplies the signal to the register 422 and causes the register 422 to latch (hold) it.
- the offset values of the comparator 411 and the AD conversion unit 421 are held in the register 422.
- the switch 423 supplies this signal to the subtractor 424 when the AD conversion unit 421 outputs the result of AD conversion of the net accumulated signal (digital net accumulated signal).
- the register 422 holds the result of no signal AD conversion.
- the register 422 supplies the non-signal A / D conversion result (digital non-signal) held to the subtractor 424.
- the subtractor 424 subtracts the digital no-signal value from the digital net accumulated signal value.
- the subtractor 424 outputs the subtraction result (net digital value).
- the advantage of providing the amplifier unit 440 will be described from the point of operation of each component of the digital value generation circuit 400.
- the resolution required when the AD conversion unit 421 performs AD conversion can be reduced to 1 / N.
- the signal of the pixel 310 is amplified N times before entering the ACDS unit 410, while the offset generated in the pixel 310 and the amplifier unit
- the ACDS unit 410 can remove the offset of 440. That is, the AD conversion unit 421 performs AD conversion on the signal from which the offset of the pixel 310 and the amplifier unit 440 have been removed, thereby minimizing the offset component when performing AD conversion.
- the AD conversion resolution may be 1 / N, and the amount of the offset component at the time of AD conversion is the same. Time can be shortened. In particular, when AD conversion is performed on a non-signal, the required time is greatly shortened because the non-signal with the offset component suppressed to the minimum is AD-converted with a resolution of 1 / N.
- the offset components constituting the no signal are an offset component generated in the ACDS unit 410 and an offset component generated in the DCDS unit 420.
- the digital value generation circuit 400 shown in FIG. 4 may integrate the comparator 411 and the AD conversion unit 421 and perform CDS by auto-zero operation. Note that an example of a circuit configuration of such a digital value generation circuit 400 will be described with reference to FIG.
- FIG. 4b shows a flowchart showing an example of the operation of the digital value generation circuit 400.
- the frame of each procedure in the flowchart shown in FIG. 4B corresponds to the frame surrounding each component shown in FIG. 4A. That is, the procedure indicated by the double frame indicates the procedure of the pixel 310, the procedure indicated by the long dashed line frame indicates the procedure of the ACDS unit 410, and the procedure indicated by the short dashed line frame indicates the procedure of the DCDS unit 420.
- the procedure indicated by a bold frame indicates the procedure of the amplifier unit 440.
- the ACDS processing by the ACDS unit 410 is not illustrated, and will be described together in a procedure when the DCDS unit 420 performs AD conversion.
- the potential of the gate terminal of the amplifier transistor 314 (the potential of the FD 322) is reset, and a reset signal is output to the vertical signal line 341 (step 511).
- the reset signal output from the pixel 310 is amplified N times (N> 1) by the amplifier unit 440 (step 512).
- the amplified reset signal includes kTC noise that is an offset component of the pixel and an offset component of the amplifier unit 440, and these noises are also multiplied and output.
- the amplified reset signal also includes random noise generated in the pixel, and this random noise is also multiplied and output.
- the reset signal amplified by the amplifier unit 440 is sampled and held by the capacitor 413 of the ACDS unit 410 (step 513).
- a difference signal (no signal) between the reset signal amplified by the amplifier unit 440 and the sampled and held reset signal is AD-converted by the AD conversion unit 421 of the DCDS unit 420 (step 514).
- the AD-converted no signal includes noise generated by the comparator 411 and the AD converter 421, and a value for canceling (offset) these noises is digitally detected. .
- the result of this AD conversion without signal is held in the register 422 as an offset value (step 515).
- the electrons accumulated in the photodiode 311 are transferred to the FD 322, and an accumulation signal is output from the pixel 310 (step 516).
- the accumulated signal output from the pixel 310 is amplified N times (N> 1) by the amplifier unit 440 (step 517).
- a difference signal (net accumulated signal) between the accumulated signal amplified by the amplifier unit 440 and the sampled and held reset signal is AD-converted by the AD converting unit 421 of the DCDS unit 420 (step 518).
- the offset component of the pixel and the offset component of the amplifier unit 440 are canceled by using a difference signal from the reset signal sampled and held.
- the AD conversion result of the difference signal includes noise generated by the comparator 411 and the AD conversion unit 421. Further, the result of the AD conversion of the difference signal includes pixel random noise.
- the subtracter 424 outputs a value obtained by subtracting the result of the non-signal AD conversion (first time) held in the register 422 from the value of the AD conversion result (second time) of the net accumulated signal. (Step 519). As a result, noise (offset component) caused by the comparator 411 and the AD conversion unit 421 is canceled, and a digital value (a net digital value) indicating the magnitude of the accumulated signal output from the pixel 310 and the magnitude of the random noise of the pixel. ) Is output.
- random noise generated in the pixel is not canceled by ACDS and DCDS, and is included in the net digital value.
- amplification is performed by the amplifier unit 440, variation in the digital value due to random noise increases.
- random noise included in the digital value
- the amplifier unit 440, ACDS unit 410, and DCDS unit 420 also generate random noise. These random noises are also included in the net digital value.
- the random noise of the amplifier unit 440 is amplified N times. Note that random noise of the amplifier unit 440 can be reduced by configuring the amplifier unit 440 with a sufficiently large-area transistor. Note that these random noises can be reduced to some extent by multiple sampling or band limitation, but cannot be completely removed like offset components.
- the net digital value generated by the digital value generation circuit 400 is supplied to the binary determination unit 220. Then, the binary determination unit 220 sets a binary determination threshold value for the pixel that outputs the accumulated signal that is the supplied net digital value from the adjustment value for each pixel held by the adjustment value holding unit 210. Thereafter, the set threshold value and the net digital value are compared, and the binary determination unit 220 determines whether or not one photon is incident.
- FIG. 5 is a diagram for describing the adjustment value held by the adjustment value holding unit 210 according to the first embodiment of the present technology.
- FIG. 5 a shows a table schematically showing the adjustment values for each pixel held by the adjustment value holding unit 210.
- FIG. 5b shows a table schematically showing the relationship between the binary determination determination threshold (digital gradation value) and the adjustment value in the binary determination unit 220.
- the 128 rows ⁇ 128 columns of pixels in the pixel array unit 300 are specified by the row number and the column number.
- the adjustment value is a 4-bit value (0 to 15).
- the adjustment value for each pixel is held in the adjustment value holding unit 210.
- the adjustment value is set for each pixel in the manufacturing process of the image sensor 100 and held in the adjustment value holding unit 210, for example. Since the setting of the adjustment value will be described with reference to FIGS. 9 to 11, the description thereof is omitted here.
- the binary determination unit 220 when the binary determination unit 220 performs binary determination, the adjustment value of the binary determination target pixel is acquired. Then, the binary determination unit 220 converts the adjustment value into a determination threshold value (tone value) associated with each value (0 to 15).
- the binary determination unit 220 holds information (lookup table) indicating the association between the adjustment value and the determination threshold value (tone value), and the adjustment is performed based on this information.
- the value is converted into a determination threshold. That is, a determination threshold of 16 gradations can be set with a 4-bit adjustment value.
- the binary determination unit 220 When the adjustment value is converted into the determination threshold value, the binary determination unit 220 performs binary determination based on the converted threshold value.
- binary determination can be performed by setting an appropriate threshold value for each pixel with respect to variations in output values of the pixels. For example, when the gain is different for each amplifier unit 440 shown in FIG. 1 and the gain is also different for each amplifier transistor 314 of the pixel shown in FIG. 2, the gain applied to the signal output from the pixel is greatly different for each pixel. It is assumed that Even in such a case, binary determination can be performed accurately by setting an appropriate threshold value for each pixel.
- FIG. 5 illustrates an example in which the adjustment value is set for each pixel
- the adjustment value for each unit of variation.
- the amplifier unit 440 is provided for each column (for each vertical signal line 341), if the gain of the amplifier unit 440 varies but the gain of the amplifier transistor 314 of the pixel does not vary, an adjustment value is provided for each column. You can also.
- FIG. 6 is a graph showing the relationship between the average number of photons incident on each pixel during a unit exposure period and the count probability in the first embodiment of the present technology.
- the average number of photons incident on each pixel within the unit exposure period (average photon number) and the probability that the incident photons are counted (determined as “1” by the binary determination unit 220) (count probability) )
- count probability the probability that the incident photons are counted
- P (k) is a probability that photon incidence occurs k times (k photons are incident) in the unit pixel within the unit exposure period.
- ⁇ is the average number of photons incident on the unit pixel (average photon number) within the unit exposure period.
- E is the base of the natural logarithm ( ⁇ 2.718).
- the probability P (k) of the above-described formula 1 indicates the probability that the number of incident photons is the number k of photons when the number of photons incident on each pixel during the unit exposure period is the average number of photons ⁇ . .
- the probability that the photons incident on the unit pixel overlap is smaller as the number of overlapping photons increases.
- the probability that the digital value is “0” is “0.8105”, which is the probability of the case where the number of photons incident on the unit pixel is zero.
- the probability that the digital value is “1” (count probability) is “0.1894”, which is the sum of the probabilities of one or more photons incident on the unit pixel.
- the count probability “0.1894” indicates that about 10% of the incident photons are not counted (count loss). This count loss is caused by counting “1” when two or more photons are incident on a unit pixel within the unit exposure period. Therefore, the count loss increases as the average photon number ⁇ increases.
- the average photon number ⁇ is “0.21”.
- the relationship between the average photon number ⁇ and the count probability is such that the photons are spatially and temporally uniform. It is unique when incident randomly. That is, when the vertical axis is the axis indicating the count probability and the horizontal axis is the average number of photons incident on each pixel during the unit exposure period, the relationship between the count probability and the average photon number is represented by the solid line ( The relationship is shown by a line 521).
- the position of the average photon number shown with a chain line shows the position (10% detection loss position) where about 10% of the incident photons are lost.
- linearity can be guaranteed when the average number of photons is “0.21” or less. If this is viewed from the side of the digital output value generated by the image sensor, that is, if the count probability in the digital value generated by the image sensor is “0.1894” or less, the image is captured with the illuminance and exposure conditions that can guarantee linearity. It is judged that On the other hand, when the count probability exceeds “0.1894” (the range indicated by the compression area 523 in FIG. 6), it is determined that the count loss is large and the linearity cannot be guaranteed.
- the count value can be corrected.
- a count probability (a ratio of pixels having a value of “1” in all pixels) is calculated based on a digital value generated by the image sensor, and the relationship shown in the table of FIG. 6 is shown.
- the average photon number is calculated from the data.
- the number of photons incident on the image sensor is calculated from the calculated average number of photons.
- an apparatus including the image sensor 100 can accurately count photons, and linearity Judgment and correction of the count value can be performed accurately.
- FIG. 7 is a diagram schematically illustrating an effect of performing the binary determination using the adjustment value for each pixel held in the adjustment value holding unit 210 according to the first embodiment of the present technology.
- FIG. 7a shows an example (an example in which a single threshold value is set for all pixels) assuming that binary determination of all pixels is performed using one threshold value in an image sensor in which the gain varies from pixel to pixel. Has been.
- FIG. 7a shows two graphs showing frequency distributions of output signals of two pixels (pixel A and pixel B) having different gains.
- the vertical axis is an axis indicating frequency
- the horizontal axis is an axis indicating a signal amount (a gradation value of a digital value).
- a frequency distribution with a signal (one-photon signal) generated in a state where one photon is incident is shown. Note that the frequency distribution is shown assuming that the pixel A has a smaller gain value (lower amplification factor) than the pixel B.
- the peak position of the non-accumulated signal of the pixel A is indicated by the position G1
- the peak position of the one-photon signal of the pixel A is indicated by the position G2.
- the peak position of the non-accumulated signal of the pixel B is indicated by a position G3
- the peak position of the one-photon signal of the pixel B is indicated by a position G4.
- the peak position (position G1) of the non-accumulated signal of the pixel A and the peak position (position G3) of the non-accumulated signal of the pixel B are the same signal amount (for example, It is assumed that the gradation value is “0”.
- the gain value of the pixel A is smaller than that of the pixel B, the distance between the peak position of the non-accumulated signal and the peak position of the one-photon signal is larger in the pixel A than in the pixel B. small.
- the variation in value due to random noise is smaller in the pixel A with a smaller gain than in the pixel B. Even in the case of a non-accumulated signal, the value varies due to random noise, as shown in FIG. 7a. Therefore, if a threshold value is not provided for a value higher than the varied value, an erroneous determination occurs.
- the range of the signal amount in which a threshold value that does not make a misjudgment of binary determination can be set is that the range of the pixel A (range P1) is narrower than the range of the pixel B (range P2). Note that the range between the distance between the peak positions of the non-accumulated signal and the one-photon signal, the variation in the value due to random noise, and the threshold value that does not make a misjudgment can be set to N times when the gain is N times. Become.
- the threshold value is set from the range (range P3) of the signal amount (gradation value) overlapping between the range P1 and the range P2. .
- range P3 the range of the signal amount (gradation value) overlapping between the range P1 and the range P2.
- FIG. 7a an example of a common threshold is shown as threshold H1.
- FIG. 7B illustrates an example of the image sensor 100 according to the first embodiment of the present technology that performs binary determination using the adjustment value for each pixel held in the adjustment value holding unit 210 (for each pixel using the adjustment value.
- An example of setting a threshold value (image pickup device 100) is shown in FIG.
- the frequency distribution of the output signals of the two pixels (pixel A and pixel B) having different gains shown in FIG. 7b is the same as that shown in FIG. To do.
- the value of the adjustment value in addition to the frequency distribution of the pixel A and the pixel B, the value of the adjustment value, the threshold value of the signal amount corresponding to the adjustment value of the value “5” set in the pixel A (threshold value H11), A signal amount threshold value (threshold value H12) corresponding to the adjustment value of “7” set in B is shown.
- the threshold value can be set for each pixel by causing the adjustment value holding unit 210 to hold the adjustment value for each pixel. Thereby, binary determination can be performed accurately.
- FIG. 8 is a flowchart illustrating an example of a processing procedure of binary determination by the binary determination unit 220 according to the first embodiment of the present technology.
- FIG. 8 the process procedure performed with respect to one digital value supplied to the binary determination part 220 is demonstrated. That is, for example, when signals are read from 128 pixels, the processing procedure shown in FIG. 8 is performed 128 times.
- the digital value of the net accumulated signal read from the pixel 310 and digitized by the digital value generation circuit 400 is acquired by the binary determination unit 220 (step S911).
- the procedure in which the digital value generation circuit 400 generates the digital value of the net accumulated signal acquired in step S911 is an example of the generation procedure described in the claims, and corresponds to steps 511 to 519 in FIG. To do.
- the adjustment value of the pixel that has output the accumulation signal converted to the digital value is acquired from the adjustment value holding unit 210 by the binary determination unit 220 (step S912).
- Step S913 is an example of a determination procedure described in the claims.
- FIG. 9 is a functional configuration diagram for describing an example of a method for calculating an adjustment value when the adjustment value holding unit 210 of the image sensor 100 holds the adjustment value in the first embodiment of the present technology.
- FIG. 9A schematically shows a functional configuration at the time of calibration (at the time of adjustment value setting) in which an adjustment value for each pixel is calculated and the adjustment value holding unit 210 holds the adjustment value.
- a functional configuration when the image sensor 100 is used for photon counting after the adjustment value is held (after completion of the adjustment value setting) is schematically shown.
- 9A illustrates an example in which the adjustment value is calculated in the manufacturing process of the image sensor 100 (or the manufacturing process of the apparatus on which the image sensor 100 is mounted) and written to the adjustment value holding unit 210 configured with a nonvolatile memory. To do.
- FIG. 9a shows the image sensor 100 for which the adjustment value is to be calculated, and a device (adjustment device 550) for calculating the adjustment value.
- a device adjustment device 550
- FIG. 9a shows the image sensor 100 for which the adjustment value is to be calculated, and a device (adjustment device 550) for calculating the adjustment value.
- the image pick-up element 100 only the structure used in description is attached
- the adjustment device 550 calculates an adjustment value for each pixel and checks various performances of the image sensor 100.
- an adjustment value calculation unit 551 is shown inside the adjustment device 550 as a functional configuration for calculating the adjustment value of the adjustment device 550.
- the adjustment device 550 is an example of the threshold value calculation device in the claims.
- the adjustment device 550 causes the image sensor 100 to generate a non-accumulation signal a predetermined number of times, and causes the adjustment value calculation unit 551 to output a digital value of the generated no-accumulation signal.
- the function of the binary determination unit 220 (see FIGS. 1 and 9b) is turned off in order to output the digital value of the non-accumulated signal to the outside of the image sensor 100. That is, the image sensor 100 outputs the digital value of the non-accumulated signal from the output circuit 150.
- FIG. 9A each configuration is illustrated without illustrating the binary determination unit 220 whose function is turned off.
- the adjustment value calculation unit 551 of the adjustment device 550 calculates an adjustment value for each pixel based on the supplied digital value of the non-accumulation signal. Since this calculation method will be described with reference to FIG. 10, a detailed description thereof will be omitted here.
- the adjustment value calculation unit 551 is an example of an acquisition unit and a calculation unit of the threshold value calculation device described in the claims.
- FIG. 9b shows the image sensor 100 in a state where the adjustment value is held in the adjustment value holding unit 210 and can be used for photon counting. Note that.
- the image pickup device 100 in this state is the same as the image pickup device 100 shown in FIG. 1, and thus detailed description thereof is omitted here.
- the function of the binary determination unit 220 is turned on.
- binary determination is performed using the adjustment value for each pixel held in the adjustment value holding unit 210.
- an adjustment value calculation unit 551 may be provided in an image pickup apparatus including an image pickup device, and the adjustment may be performed when the image pickup apparatus is turned on, or calibration may be performed every time immediately before image pickup.
- calibration is performed at the time of power-on or immediately before imaging, for example, dark current measurement is also performed, and an adjustment value for a determination threshold is written to the memory, and at the same time, a defective pixel is detected and detected. You may make it perform the operation
- FIG. 10 is a diagram schematically illustrating the calculation of the adjustment value by the adjustment value calculation unit 551 in the first embodiment of the present technology.
- FIG. 10 is described assuming an example in which adjustment values for the pixels A and B shown in FIG. 7 are calculated.
- FIG. 10 a shows a diagram for explaining the calculation of the adjustment value of the pixel A
- FIG. 10 b shows a diagram for explaining the calculation of the adjustment value of the pixel B.
- FIGS. 10a and 10b the position of each average value (position G21, position G22) calculated from the frequency of non-accumulated signals of pixel A and pixel B and the frequency of each non-accumulated signal are calculated.
- a double arrow indicating the magnitude of the value of each standard deviation ( ⁇ ) is shown.
- 10a and 10b a double arrow indicating a value (K1 ⁇ ⁇ ) obtained by multiplying the standard deviation of the pixel A and the pixel B by a constant (K1), and a chain line indicating the calculated threshold (threshold T21, threshold T22). ) And is shown.
- FIGS. 10a double arrow indicating the magnitude of the value of each standard deviation ( ⁇ ) is shown.
- the axis indicating the adjustment value is shown, and the adjustment value converted into the gradation value closest to the calculated threshold value (gradation value) is a broken line with a dot inside.
- the value covered by the rectangle pixel A is “5”, pixel B is “7”).
- the image sensor 100 When calculating the adjustment value, the image sensor 100 generates a non-accumulation signal a plurality of times (for example, 64 times for each pixel), and supplies the generated non-accumulation signal to the adjustment value calculation unit 551. Thereby, the adjustment value calculation part 551 can detect the frequency distribution of the non-accumulation signal as shown in the frequency distribution curve 561 in FIG. 10a and the frequency distribution curve 565 in FIG. 10b for each pixel.
- the frequency distribution curves (frequency distribution curve 561 and frequency distribution curve 565) of the non-accumulated signal generated when calculating the adjustment value are indicated by thick solid lines. Note that the frequency distribution curves (frequency distribution curve 562 and frequency distribution curve 566) of the one-photon signal shown for explanation of what is not generated when calculating the adjustment value are shown by thin broken lines.
- the non-accumulation signal is generated, for example, in a state in which the reset transistor 313 (see FIG. 2) is turned on and the potential of the FD 322 is fixed to the reset potential, and imaging in a state where there is no charge accumulation is realized in a pseudo manner.
- the It can also be generated by performing an imaging operation in a state where there is no light (dark state) with a short exposure time that does not generate a dark current for one electron (noise generated in the photodiode).
- the adjustment value calculation unit 551 generates a frequency distribution for each pixel based on the non-accumulated signal generated a plurality of times, and from this frequency distribution, an average value (Av) of signal amount (gradation) and a standard deviation ( ⁇ ) is calculated. Subsequently, the adjustment value calculation unit 551 calculates a threshold value (Vth) from the average value Av and the standard deviation ⁇ using, for example, the following Expression 2.
- Vth Av + K1 ⁇ ⁇ Equation 2
- K1 is a constant.
- the threshold value Vth calculated by Equation 2 is about the middle between the average (peak) position (position G21, position G22) of the non-accumulated signal and the average (peak) position of the one-photon signal. (Position of signal (gradation)).
- the above formula 2 will be described.
- the distance (peak-to-peak distance) between the peak position of the non-accumulated signal and the peak position of the one-photon signal is different for each pixel according to the gain.
- the degree of variation in the value of the non-accumulation signal varies from pixel to pixel depending on the gain. Note that the distance between peaks and the degree of variation also increase N times when the gain increases N times.
- the adjustment value calculation unit 551 calculates the standard deviation ⁇ of the value of the non-accumulated signal as a value indicating the degree of variation in the value of the non-accumulated signal. Thereafter, the adjustment value calculation unit 551 calculates a threshold value by regarding the standard deviation ⁇ that increases or decreases according to the gain as a gain. The adjustment value calculation unit 551 calculates the threshold position from the peak position (average value Av) of the non-accumulated signal by multiplying the standard deviation ⁇ by the constant K1. Note that when the value obtained by multiplying the standard deviation ⁇ by the constant K1 is doubled, a value close to the distance between the peak position of the non-accumulated signal and the peak position of the one-photon signal is obtained.
- the constant K1 is a common value determined in advance for each product type (each circuit type of the image sensor). For example, the frequency distribution when one photon is incident is actually detected using a single photon generator, and a constant K1 for calculating an appropriate threshold value for any gain (any pixel) is calculated. Then, the calculated constant K1 is held in the adjustment value calculation unit 551, and when the adjustment value is calculated, the threshold value is calculated using the constant K1 corresponding to the imaging element to be calculated.
- the average value Av is substantially zero when various offsets are sufficiently canceled in the digital value generation circuit 400. In this case, the addition of the average value Av may be omitted.
- the average value Av is a gradation value of approximately “0”
- the count of the accumulated signal is reduced due to random noise in the signal amount (gradation value) count in the digital value generation circuit 400 and becomes negative. It may be a digital value.
- the adjustment value calculation unit 551 In order for the adjustment value calculation unit 551 to correctly detect the average and the standard deviation, it is necessary to keep the negative value, so the digital value generation circuit 400 does not round up the gradation value to “0”. The negative value is supplied to the adjustment value calculation unit 551 as it is.
- the adjustment value calculation unit 551 uses the lookup table to calculate an adjustment value corresponding to the signal amount (gradation value) closest to the signal amount of the calculated threshold value Vth after calculating the threshold value Vth using the above-described Expression 2. To detect. Then, the adjustment value calculation unit 551 supplies the detected adjustment value to the adjustment value holding unit 210 and holds it as the adjustment value of the pixel that has output the non-accumulation signal.
- the example in which the adjustment value is held for each pixel has been described.
- This example has the best binary determination accuracy.
- the main cause of the variation is the amplifier section for each column, and there is almost no variation in the amplifier transistors of the pixels, it may be possible to set the adjustment value for each column.
- a determination threshold may be provided for each image sensor.
- FIG. 11 is a flowchart illustrating an example of a processing procedure of adjustment value calculation by the adjustment value calculation unit 551 of the adjustment device 550 according to the first embodiment of the present technology.
- a signal with no charge accumulation (non-accumulation signal) generated by the image sensor 100 for which an adjustment value is set is acquired by the adjustment value calculation unit 551 as many times (predetermined number) as necessary to generate a frequency distribution. (Step S921). Based on the frequency distribution of the non-accumulated signal for each pixel, the average value (Av) and standard deviation ( ⁇ ) of the non-accumulated signal are calculated for each pixel (step S922).
- a threshold value (tone value) is calculated for each pixel using the calculated average value (Av), the calculated standard deviation ( ⁇ ), and the constant K1 (step S923). Thereafter, the calculated threshold value for each pixel is converted into an adjustment value for each pixel, and the converted adjustment value is recorded in the adjustment value holding unit (step S924), and the adjustment value calculation processing procedure ends.
- the adjustment value is held in the adjustment value holding unit 210, whereby the thresholds are separately set according to the gain variation (conversion efficiency variation). Binary judgment can be performed.
- the precision of the determination of the photon which injected into the pixel can be improved.
- the present invention is not limited to this.
- the amplifier unit 440 when the amplification factor is the same as that of a pixel including a normal source follower type amplifier transistor and is 1 or less), it is assumed that the variation in conversion efficiency of the amplifier transistor is large. .
- the adjustment value for each pixel by performing binary determination using the adjustment value for each pixel, it is possible to improve the accuracy of determination of photons incident on the pixel.
- FIG. 12 to FIG. 20 a plurality of amplification methods will be described as modified examples for the amplifier unit 440 in which various examples are considered.
- FIG. 12 is a diagram schematically illustrating an example of a circuit configuration example of an amplifier unit 440 of an operational amplifier illustrated as a first modification example of the first embodiment of the present technology.
- FIG. 12 also shows an example of a circuit configuration example of the digital value generation circuit 400 for convenience of explanation.
- an amplifier circuit 460 is shown as a circuit configuration of the amplifier unit 440 configured by an operational amplifier, and a comparator 470, capacitors 471 and 472, and a counter 480 are included as the circuit configuration of the digital value generation circuit 400. It is shown.
- a vertical signal line 341 connected to the amplifier circuit 460 and a part of the pixel 310 connected to the vertical signal line 341 are shown together.
- the amplifier circuit 460 includes an amplifier 461, capacitors 462 and 463, and a switch 464.
- the amplifier 461 has a positive input terminal (+ end) connected to the vertical signal line 341, and a negative input terminal ( ⁇ end) connected to one electrode of the capacitor 462, one electrode of the capacitor 463, and the switch 464.
- the amplifier 461 has an output terminal connected to one electrode of the capacitor 471, the other electrode of the capacitor 463, and the switch 464.
- the other electrode of the capacitor 471 is connected to the positive input terminal (+ end) of the comparator 470.
- the capacitor 472 has one electrode connected to the REF signal line 473 and the other electrode connected to the negative input terminal ( ⁇ end) of the comparator 470.
- the output terminal of the comparator 470 is connected to the counter 480.
- the amplifier circuit 460 amplifies a signal (indicated as “PXOUT” in FIG. 5) supplied from the pixel 310 via the vertical signal line 341 by N times (N> 1). That is, the amplifier circuit 460 corresponds to the amplifier unit 440 in the functional configuration example illustrated in FIG.
- the amplifier circuit 460 first performs the auto-zero operation by setting the switch 464 in a conductive state after setting the potential at the + end to a predetermined intermediate potential. As a result, the potential at the ⁇ end becomes the same as the potential at the + end. Then, after the switch 464 is turned off, the signal supplied to the + terminal is amplified. In this amplification, the difference between the potential at the ⁇ end (intermediate potential) and the potential at the + end is amplified N times (N> 1) using capacitive division, and output in the normal direction (non-inverted).
- the auto-zero operation of the amplifier circuit 460 performs the auto-zero operation simultaneously with the amplification of the reset signal, for example, at the timing when the pixel 310 outputs the reset signal with the potential of the reset signal of the pixel 310 as an intermediate potential.
- the offset component generated in the pixel 310 (the offset component of the pixel 310) is canceled by the auto-zero operation.
- the signal output from the output terminal of the amplifier circuit 460 (shown as “PXAOUT” in FIG. 5) includes an offset component unique to the amplifier circuit 460.
- This offset component is, for example, switching noise generated on the negative side due to the feedthrough of the switch 464 when the auto-zero operation is completed, kTC noise of the amplifier circuit 460, or the like.
- These offsets are amplified N times as in the signal when the signal (PXOUT) of the pixel 310 is amplified. That is, the signal (PXAOUT) output from the output terminal of the amplifier circuit 460 includes a considerably large offset component.
- Capacitors 471 and 472 are capacitors of equal capacitance provided at the + end and ⁇ end of the comparator 470.
- the capacitors 471 and 472 have an ACDS charge for the + end side capacitor 471 electrode (the other electrode) of the comparator 470 and the ⁇ end side capacitor 471 electrode (the other end) of the comparator 470. Electrode).
- the comparator 470 compares the potentials of PXAOUT and REF.
- a signal (no signal) in which the charge of the reset signal is canceled is output from the comparator 470. + Supplied to the end.
- the offset component generated in the pixel 310 is canceled when the auto-zero operation of the amplifier circuit 460 is performed with the potential of the reset signal as an intermediate potential, so only the offset component of the amplifier circuit 460 is canceled.
- the comparator 470 compares the potential at the + end (the potential of PXAOUT) with the potential at the ⁇ end (the potential of the REF signal), and outputs a signal corresponding to the terminal side having a higher potential. For example, the comparator 470 outputs a signal having the highest potential (referred to as H level) when the potential at the positive end is higher than the potential of the REF signal (referred to as “REF”), and the potential of PXAOUT is When the potential is lower than the REF potential, a signal having the lowest potential (referred to as L level) is output. Comparator 470 performs two comparisons, when the potential at the + end is the potential of the reset signal and when the potential at the + end is the potential of the accumulated signal. When the potential at the + terminal is the potential of the reset signal, the comparator 470 supplies the comparison result signal (shown as “CMOUT”) to the counter 480.
- CMOUT comparison result signal
- the counter 480 performs a count for generating a digital value based on the comparison result signal (CMOUT) of the comparator 470 and the clock signal (CTIN) supplied from the clock signal line 481.
- the counter 480 counts down from an initial value (for example, “0”) when counting the reset signal. Then, in the case of counting the accumulated signal, the counter 480 performs up-counting from the count value resulting from the down-counting.
- the up-counting from the count value resulting from the down-counting corresponds to the subtraction of the subtractor 424 shown in FIG.
- the counter 480 outputs a signal (DOUT) indicating the digital value of the up-count result.
- the counter 480 and the comparator 470 correspond to the DCDS unit 420 in the functional configuration example shown in FIG.
- Capacitors 471 and 472 correspond to ACDS unit 410 in the functional configuration example shown in FIG.
- the comparison by the comparator 470 is for digitizing the reset signal and the accumulated signal. Therefore, when comparing, the potential of the REF signal supplied via the REF signal line 473 is a ramp waveform.
- the clock signal is supplied with a pulse corresponding to each stage of the ramp waveform on a one-to-one basis. Supply of this pulse is started in synchronization with the start timing of the ramp waveform, and the counter 480 is a pulse from the start of the ramp waveform until the signal of the comparison result of the comparator 470 is inverted (transition from L level to H level). Count numbers and generate digital values.
- step potential difference the amount of potential that falls in each step of the ramp waveform is set according to the gradation when the accumulated signal is converted to a digital value. That is, the potential difference of the step is N times as with the amplification magnification, compared to an image sensor (another image sensor) that does not include the amplifier circuit 460.
- the reset signal is digitally determined (the reset signal count period (see FIG. 13)
- the offset components in the pixel 310 and the amplifier 461 are already canceled by ACDS.
- the image sensor another image sensor that does not include the amplifier circuit 460. Therefore, the potential difference from the start (scan start) to the end (scan end) of the ramp waveform in the reset signal count period in the imaging device including the amplifier circuit 460 (scan target potential difference (see potential difference D1 in FIG. 13)).
- Imaging without the amplifier circuit 460 Is the same as the child (other imaging device).
- FIG. 13 is a timing chart illustrating an example of operations of the amplifier circuit 460 and the digital value generation circuit 400 shown as the first modification example of the first embodiment of the present technology.
- the horizontal axis is a common time axis, and the potential change of the pixel reset line 331, the charge transfer line 332, the vertical signal line 341, the amplification signal line 469, the REF signal line 473, and the clock signal line 481 is shown by a solid line. Yes.
- the potential change in the amplified signal line 469 and the potential change in the REF signal line 473 the potential change in the amplified signal line 469 after the timing T2 is applied to the REF signal line 473. This is indicated by the superimposed broken lines.
- the length of the time axis is schematic and does not indicate the ratio of the time length between the timings.
- FIG. 13 for convenience of explanation, a description is given by illustrating the middle of a period for performing digital determination of an accumulated signal (accumulated signal count period).
- a predetermined timing timing T1 to T8 of the operation transition from when the reset signal is output from the pixel 310 until the digital value (net digital value) of the accumulated signal is determined.
- T1 to T8 timing T1 to T8 of the operation transition from when the reset signal is output from the pixel 310 until the digital value (net digital value) of the accumulated signal is determined.
- FIG. 13 description will be made assuming that the amplifier circuit 460 amplifies the signal four times and outputs the amplified signal.
- a reset pulse is supplied to the gate terminal of the reset transistor 313 of the pixel 310 via the pixel reset line 331. Accordingly, a reset level signal (reset signal) is supplied to the vertical signal line 341, and the potential of the vertical signal line 341 changes to the potential of the reset signal.
- the potential transition in the vertical signal line 341 is amplified four times by the amplifier circuit 460 and output to the amplified signal line 469. That is, the potential transition amount (potential difference) of the amplification signal line 469 at the timing T1 is four times the potential difference of the vertical signal line 341. Note that at the timing T1, the auto-zero operation of the amplifier circuit 460 is performed with the potential of the reset signal of the pixel 310 as an intermediate potential.
- the potential of the vertical signal line 341 slightly drops due to the influence of coupling.
- the potential of the amplified signal line 469 also drops by about four times the potential transition amount (potential difference) of the vertical signal line 341. Note that the potential of the amplified signal line 469 when lowered and stabilized by the influence of the coupling is used in the digital value generation circuit 400 as the potential of the reset signal amplified four times.
- the charge for performing analog CDS is held in the capacitor 471 connected to the + end of the comparator 470 and the capacitor 472 connected to the ⁇ end of the comparator 470.
- this charge holding is performed by balancing the voltages applied to the + end and the ⁇ end of the comparator 470 by turning on and off the transistors inside the comparator 470. This is performed by holding the balanced voltages (see, for example, Japanese Patent Application Laid-Open No. 2008-193373).
- the potential of the reset signal supplied to the + terminal of the comparator 470 becomes the relative potential of the reference signal (frame F1 in FIG. 13) and can be regarded as no signal.
- the charge retention at the timing T2 corresponds to the reset signal sample hold described with reference to FIG.
- the potential of the REF signal line 473 is changed to the potential (V1) at the start of the ramp waveform.
- the potential difference to be transitioned at the timing T3 is common to the plurality of comparators 470. Therefore, the potential difference of the REF signal line 473 is set such that the potential of the REF signal coincides with the potential of the reset signal in the middle of the ramp waveform in all the comparators 470. In other words, the potential difference of the REF signal line 473 is included so that it can correspond to the offset in which the potential of the signal input from the + end of the comparator 470 rises the most among offsets that vary for each comparator 470. As set).
- the supply of the stepped pulse to the REF signal line 473 is started, and the period for counting the reset signal output from the pixel 310 (reset signal count period) is started. That is, at the timing T4, the first step-like pulse is supplied to the REF signal line 473.
- supply of a pulse synchronized with the stepped pulse is started on the clock signal line 481.
- the counter 480 starts down-counting according to the number of pulses on the clock signal line 481. The down-count is counted from an initial value (for example, “0”) of a value (count value) counted by the counter 480. This down-counting is performed until the signal (CMOUT) output from the comparator 470 is inverted.
- the output signal (CMOUT) of the comparator 470 is inverted and the downcounting of the counter 480 stops. That is, the count is stopped at the timing (the frame F2 in FIG. 13) at which the potential relationship between the + end and the ⁇ end in the comparator 470 is reversed. The count value counted by the down-counting is held until the accumulated signal is counted. Note that the count value generated by the down-count corresponds to the result of no-signal AD conversion (digital no-signal) described in FIG. That is, the count value generated by the downcount corresponds to a value obtained by digitizing the offset component of the comparator 470.
- the reset signal counting period is finished.
- the scan target potential difference (potential difference D1 in FIG. 13) from the start to the end of the ramp waveform in the reset signal count period is the offset with the highest potential and the potential with the lowest potential among the offsets that vary for each comparator 470. It is set so as to correspond to the offset.
- the potential difference D1 is set so that the number of extra stages is as small as possible in order to shorten the time length of the reset signal count period.
- the potential of the REF signal transits to the ramp waveform start potential (V1). That is, the state returns to the same state as the timing T3, and the output signal (CMOUT) of the comparator 470 also returns to the potential counted by the counter 480. Further, at timing T 7, a transfer pulse is supplied to the gate terminal of the transfer transistor 312 of the pixel 310 via the charge transfer line 332. As a result, a signal (accumulated signal) corresponding to the accumulated charge is supplied to the vertical signal line 341. Then, the potential of the vertical signal line 341 changes to a potential corresponding to the accumulated signal.
- the potential transition in the vertical signal line 341 is amplified four times by the amplifier circuit 460.
- the potentials of the amplified signal line 469 and the vertical signal line 341 slightly drop due to the influence of coupling.
- the potential at the time of being lowered and stabilized by the influence of the coupling is used in the digital value generation circuit 400 as the potential of the accumulated signal amplified four times.
- timing T8 supply of a stepped pulse to the REF signal line 473 is started, and a period for counting the accumulation signal output from the pixel 310 (accumulation signal count period) is started.
- a pulse synchronized with the stepped pulse is supplied to the clock signal line 481. Note that in the accumulation signal count period, the counter 480 counts up until the output signal (CMOUT) of the comparator 470 is inverted. This up-count is counted up from the count value resulting from the down-count in the reset signal count period.
- the held count value corresponds to the subtraction result (net digital value) of the subtractor 424 described in FIG. That is, the count value that is up-counted and held from the down-count result is a net pixel value in which the offset component of the pixel 310, the offset component of the amplifier circuit 460, and the offset component of the comparator 470 are offset.
- each offset component (an offset component caused by the pixel 310, an offset component caused by the amplifier circuit 460, and an offset component caused by the comparator 470) will be described.
- the auto-zero operation of the amplifier circuit 460 is performed using the reset signal potential of the pixel 310 as an intermediate potential at the timing T ⁇ b> 1, the offset component due to the pixel 310 is canceled by the auto-zero operation of the amplifier circuit 460.
- the signal on the amplified signal line 469 includes an offset component due to the amplifier circuit 460.
- the offset component caused by the amplifier circuit 460 is canceled by the analog CDS operation at the timing T2.
- offset components caused by the comparator 470 offset inherent in the comparator 470, kTC noise generated due to the auto-zero operation of the comparator 470, feedthrough, etc. are canceled out. Absent. However, the offset component caused by the comparator 470 is canceled by the digital CDS due to the down count of the reset signal and the up count of the accumulated signal.
- the potential difference between the steps of the ramp waveform becomes four times because the signal from the pixel 310 is amplified four times in the amplifier circuit 460.
- the resolution of AD conversion is improved with an accuracy of 1 ⁇ 4 compared to an image sensor (other image sensor) that does not include the amplifier circuit 460.
- the slope of the ramp waveform is 4 times.
- the potential difference from the start to the end of the ramp waveform in the reset signal count period (potential difference D1 in FIG. 13) is the same as that of the other imaging elements. Since the same potential difference is scanned with a slope of 4 times, the length of the reset signal count period in the imaging device (imaging device 100) including the amplifier circuit 460 is 1/4 times that of the other imaging devices.
- the potential difference from the start to the end of the ramp waveform in the accumulation signal count period (scan target potential difference in the accumulation signal count period) will be described.
- This potential difference is set so that the transition of the potential obtained by adding the offset component caused by the comparator 470 and the accumulated signal can be detected. That is, the scan target potential difference during the accumulation signal count period is a potential difference obtained by adding the potential difference D1 during the reset signal count period and the potential difference for detection of the accumulation signal.
- the potential difference for detecting the accumulated signal is N times the potential difference of an image sensor (other image sensor) that does not include the amplifier circuit 460 because the output signal of the pixel 310 is N times.
- the potential difference D1 during the reset signal count period is the same as that of other imaging elements. In other words, the time length of the accumulated signal count period is increased by a factor of 1 ⁇ 4 as the detection time of the offset component of the comparator 470 is longer in the accumulated signal count period, and is shorter than other image sensors. .
- the image sensor 100 is an image sensor for detecting weak light
- the accumulated signal is very small. That is, the ratio of the detection time of the offset component of the comparator 470 is very large in the time length of the accumulated signal count period.
- the detection time of the offset component of the comparator 470 that occupies most of the time required for AD conversion when detecting weak light can be significantly shortened.
- FIG. 14 shows a reset signal count period of the image sensor 100 including the amplifier circuit 460 and the digital value generation circuit 400 shown as a first modification of the first embodiment of the present technology, and reset signal counts of other image sensors. It is a figure which shows a period typically.
- FIG. 14a shows a potential change in a reset signal count period of a line (REF signal line 599) for supplying a REF signal of another imaging element
- FIG. 14b shows a first change in the first embodiment of the present technology.
- the potential change of the REF signal line 473 of the image sensor (image sensor 100) of the modification is shown. Note that the potential change shown in FIG. 14B is the same as that described with reference to FIG.
- the scan target potential difference (potential difference D1) is the same between the other image sensor and the image sensor 100.
- the potential difference of the step of the ramp waveform is N times the potential difference of the image sensor 100 with respect to the potential difference of other image sensors. Therefore, the time length of the reset signal count period of the image sensor 100 (reset signal count period (image sensor 100)) is 1 / N of the time length of other image sensors (reset signal count period (other image sensors)). Double time.
- FIG. 15 is a table for comparing the ramp waveform of the REF signal in the first modification of the first embodiment of the present technology with the ramp waveform of the REF signal in another imaging device.
- 15a shows a table for comparing the ramp waveforms in the reset signal count period.
- the potential difference of the step of the ramp waveform of the REF signal is set in the image sensor 100 as a potential difference of N times ( ⁇ N) with respect to the potential difference ( ⁇ 1) in the other image sensor.
- the scan target potential difference in the reset signal count period (the difference between the start potential and the end potential of the ramp waveform in the reset signal count period) is the same potential difference ( ⁇ 1) as the scan target potential difference ( ⁇ 1) of other image sensors. ) Is set in the image sensor 100.
- the number of stages in the reset signal count period is set in the image sensor 100 as 1 / N times ( ⁇ 1 / N) the number of stages ( ⁇ 1) of other image sensors.
- the time length of the reset signal count period in the image sensor 100 is 1 / N times ( ⁇ 1 / N) the time length ( ⁇ 1) of other image sensors.
- the table of FIG. 15b shows a table for comparing the ramp waveforms in the accumulation signal count period.
- the potential difference of the step of the ramp waveform of the REF signal during the accumulation signal count period is the same as that during the reset signal count period.
- the scan target potential difference during the accumulation signal count period is the same ( ⁇ 1) as other image sensors for the amount corresponding to the potential difference for detecting the offset component of the comparator 470.
- the amount corresponding to the potential difference for detecting the accumulated signal is N times ( ⁇ N) this potential difference in the other image sensor. That is, the larger the proportion of the potential difference for detecting the offset component of the comparator in the scan target potential difference in the accumulation signal count period, the closer the scan target potential difference in the accumulation signal count period is to the potential difference of the other image sensor.
- the number of stages in the accumulated signal count period is 1 / N times that of other image sensors for the part corresponding to the number of stages for detecting the offset component of the comparator 470.
- the amount corresponding to the number of stages for detecting the accumulated signal is the same ( ⁇ 1) as the number of stages in the other image sensors.
- the time length of the accumulation signal count period is 1 / N times that of the other image sensors for the time length for detecting the offset component of the comparator 470.
- the amount corresponding to the time length for detecting the accumulated signal is the same as ( ⁇ 1) the amount corresponding to this time length of the other image sensor.
- the time required for AD conversion of the offset component of the comparator 470 can be shortened.
- the determination threshold for binary determination of the presence or absence of one-photon incidence is about 300 ⁇ V, which is an intermediate value from 0 to 600 ⁇ V, if the offset of the comparator 470 is not taken into consideration. Therefore, if the offset of the comparator 470 is not taken into consideration, if the ramp waveform of the REF signal covers up to about 300 ⁇ V, binary determination of the presence or absence of one-photon incidence becomes possible.
- the offset of the comparator 470 is several mV to several tens mV, and considering the output signal range (0 ⁇ V to 600 ⁇ V) of the pixel 310, the offset range (several mV to several tens mV) of the comparator 470 is one. More than an order of magnitude larger. As shown in FIG. 13, the offset cancellation of the comparator 470 is performed by subtracting the amount corresponding to the offset component (down count value during the reset signal count period) from the count value during the accumulated signal count period.
- the step of the ramp waveform (detection accuracy) for detecting the output signal of the pixel 310 and the step of the ramp waveform (detection accuracy) for detecting the offset component of the comparator 470 need to be performed with the same accuracy.
- the signal amount of one photon is S ( ⁇ V)
- the output signal of the pixel 310 is included in the quantization error of the offset component of the comparator 470. It will be buried. That is, if AD conversion is not performed at a step of a ramp waveform that is 1 ⁇ 2 or less of the signal amount generated by one photon, the resolution of AD conversion is insufficient.
- the reset signal count period and the accumulation signal count period in the determination of one-photon incidence are Most of the time becomes the offset detection time of the comparator 470.
- the output signal range (0 ⁇ V to 600 ⁇ V) of the pixel 310 is four times (0 ⁇ V to 2400 ⁇ V).
- the detection accuracy of 300 ⁇ V (S / 2 ⁇ V) is sufficient with a detection accuracy of 1 ⁇ 4 times (1200 ⁇ V).
- the offset range (several mV to several tens of mV) of the comparator 470 does not change.
- the amplifier circuit 460 by providing the amplifier circuit 460, it is possible to increase the step of the ramp waveform (decrease the detection accuracy). That is, it is possible to reduce only the resolution with respect to the offset component of the comparator 470 without reducing the resolution with respect to the output signal of the pixel 310 (detection accuracy capable of detecting the presence or absence of one-photon incidence).
- FIG. 16 is a diagram schematically illustrating an example of a circuit configuration example of an amplifier circuit (amplifier circuit 710) of the inverter illustrated as the second modification example of the first embodiment of the present technology.
- the amplifier circuit 710 is provided in place of the amplifier circuit 460 shown in FIG. 12, and includes an inverter 711, capacitors 712 and 713, and a switch 714.
- the inverter 711 has an input terminal connected to one electrode of the capacitor 712, one electrode of the capacitor 713, and one end of the switch 714.
- the output terminal of the inverter 711 is connected to the other electrode of the capacitor 713, the other end of the switch 714, and one electrode of the capacitor 471 through the amplification signal line 469.
- the other electrode of the capacitor 712 is connected to the pixel 310 via the vertical signal line 341.
- the amplifier circuit 710 amplifies an input signal (PXOUT) using a CMOS inverter (inverter 711), and performs signal amplification according to the ratio of two capacitors (capacitors 712 and 713). Since the amplifier uses an inverter, the output signal (PXAOUT) has a phase opposite to that of the input signal (PXOUT).
- the amplifier circuit 710 has a large 1 / f noise generated as random noise, and thus generates a large amount of noise.
- This 1 / f noise can be reduced by providing a transistor having a sufficiently larger area than the amplifier transistor (amplifier transistor 314 in FIG. 2) provided in each pixel as a transistor constituting the inverter 711.
- the area allocated to each amplifier circuit 710 can be increased by sharing the amplifier circuit 710 among a plurality of columns.
- the output of the pixel can be amplified also by an amplifier (amplifier circuit 710) using an inverter.
- FIG. 17 is a schematic diagram illustrating an example of a circuit configuration of a pixel (pixel 830) in an example in which the output of the pixel is fed back to the floating diffusion illustrated as the third modification example of the first embodiment of the present technology.
- the pixel 830 includes a capacitor (capacitor 832) having one end connected to the FD 322 in addition to the components of the pixel 310 in FIG.
- the amplifier transistor 314 is a source follower type as in FIG. 2, and a feedback circuit (feedback amplifier 831) is provided for each column (for each vertical signal line 341) together with the pixel 830.
- the feedback amplifier 831 is a feedback circuit that feeds back the output signal of the pixel supplied to the vertical signal line 341 to the FD 322 of the pixel that has output the output signal.
- the feedback amplifier 831 is realized by a source follower of a PMOS transistor, for example.
- each configuration (PMOS transistor and constant current source (constant current load transistor)) constituting the feedback amplifier 831 is not shown, and the feedback amplifier 831 is shown as a triangular symbol indicating the amplifier.
- the signal lines on the input side and the output side of the feedback amplifier 831 are indicated by broken lines, and are distinguished from the pixel configuration. .
- the feedback amplifier 831 has an input terminal (PMOS transistor gate terminal) connected to the vertical signal line 341.
- the output terminal of the feedback amplifier 831 (the source terminal of the PMOS transistor) is connected to one end of a capacitor 832 provided in each pixel connected to the vertical signal line 341. That is, the feedback amplifier 831 varies the potential of one end of the capacitor 832 of the pixel that outputs the output signal in accordance with the output signal supplied to the vertical signal line 341.
- the feedback amplifier 831 is composed of a PMOS transistor, and the relationship between the input and the output is in a positive phase, so that a positive feedback is applied to the potential of the FD 322.
- the capacitor 832 has a capacitance for coupling the output of the feedback amplifier 831 and the FD 322 of the pixel. That is, the potential of the FD 322 varies according to the output of the feedback amplifier 831 due to capacitive coupling by the capacitor 832.
- FIG. 18 is a schematic diagram illustrating an example of a circuit configuration of a pixel (pixel 840) in an example in which the output of the pixel is fed back to the drain terminal of the amplifier transistor illustrated as the fourth modification example of the first embodiment of the present technology. is there.
- the drain terminal of the amplifier transistor 314 of the pixel 310 in FIG. 2 is not connected to the power supply line 323 but is connected to a line (signal line 849) for supplying a potential for the drain terminal of the amplifier transistor 314.
- the rest is the same as the pixel 310 in FIG.
- a feedback circuit (feedback amplifier 841) is provided for each column (for each vertical signal line 341).
- the feedback amplifier 841 is the same as the feedback amplifier 831 shown in FIG. 17 except that the output is supplied to the signal line 849. Therefore, only the influence of the output on the potential of the signal line 849 will be described here.
- the output of the feedback amplifier 831 is directly connected to the drain of the amplifier transistor 314, and the output of the feedback amplifier 831 replaces the conventional power supply connection. Accordingly, in the pixel 840, the potential of the drain terminal of the amplifier transistor 314 varies according to the output of the feedback amplifier 831. Note that the drain diffusion layer of the amplifier transistor 314 has a strong parasitic capacitance with a gate electrode (floating diffusion). Therefore, when the potential on the drain side fluctuates, the potential of the gate of the amplifier transistor 314 (the potential of the FD 322) also fluctuates due to the parasitic capacitance between the gate and the drain. That is, the decrease in the potential of the signal line 849 due to the output of the feedback amplifier 841 becomes positive feedback to the FD 322 through the parasitic capacitance, and the output signal of the pixel is amplified.
- the output of the pixel can be amplified also by feeding back the output of the pixel to the drain terminal of the amplifier transistor 314.
- FIG. 19 illustrates a pixel (pixel 810) in an example in which a common-source NMOS transistor shown as a fifth modification of the first embodiment of the present technology is provided as an amplifier transistor to amplify an output from the pixel. It is a schematic diagram which shows an example of a circuit structure.
- the pixel 810 includes a common-source amplifier transistor 811 instead of the source-follower amplifier transistor 314 provided in the pixel 310 of FIG. Since the configuration of the pixels other than the amplifier transistor 811 is the same as that in FIG. 2, the same reference numerals as those in FIG. 2 are used and description thereof is omitted here.
- the amplifier transistor 811 is an amplifier transistor composed of a grounded source NMOS transistor whose source terminal side is grounded.
- the drain terminal of the amplifier transistor 811 is connected to the constant current source 819 and the digital value generation circuit via the vertical signal line 341. Since the amplifier transistor 811 is a common source amplifier transistor, the input (the potential of the FD 322) can be amplified and output to the vertical signal line 341.
- ⁇ Id gm ⁇ ⁇ Vg + ⁇ Vd / Rd Equation 3
- ⁇ Id is a change amount of the drain current from the drain current before amplification.
- Gm is a mutual conductance.
- ⁇ Vg is a change amount of the gate voltage from the gate voltage before amplification
- Rd is a drain resistance
- ⁇ Vd is a change amount of the drain voltage from the drain voltage before amplification.
- the output of the amplifier transistor 811 is out of phase. Further, since the amplification factor is generally larger than 1 (much larger), the output signal of the pixel is amplified by the amplifier transistor 811.
- the amplifier circuit 460 of the digital value generation circuit 400 illustrated in FIG. 5 is omitted, and the output of the pixel 810 amplified by the amplifier transistor 811 is directly supplied to the capacitor 471.
- the mutual conductance gm and the drain resistance r are values that slightly vary with changes in the operating point. For this reason, the output from the amplifier transistor 811 has poor linearity.
- the output from the amplifier transistor 811 has poor linearity.
- binary determination is performed in one-photon detection, only a small amount of electrons are accumulated, so that the fluctuation of the potential of the FD 322 is small and the operating point is almost constant.
- this deterioration in linearity does not become a problem. That is, the example in which the common-source amplifier transistor is provided in the pixel is particularly suitable for one-photon detection. Further, in this example, random noise does not increase due to the addition of extra transistors and circuits (for example, addition of the amplifier circuit 460 shown in FIG. 12).
- FIG. 19 shows an example in which the constant current source 819 and the power source of the pixel (power source (power source voltage) supplied to the pixel via the power source line 323) are separated.
- a PMOS transistor is used in the saturation region as the constant current source 819.
- an operating point suitable for amplification can be ensured by making the power supply potential of the constant current source 819 higher than the power supply potential of the pixel supplied to the pixel through the power supply line 323.
- FIG. 19 illustrates an example in which the common-source amplifier transistor 811 is configured with a general NMOS transistor
- a common-source amplifier transistor can be provided in a pixel even if a PMOS transistor is used. In this case, it is not necessary to set the power supply potential of the constant current source higher than the power supply potential of the pixel, and the setting of the power supply potential of the constant current source is facilitated.
- the common source amplifier transistor 811 is configured with a PMOS transistor will be described with reference to FIG.
- FIG. 20 shows a pixel (pixel 820) in an example in which a common-source PMOS transistor shown as a sixth modification of the first embodiment of the present technology is provided as an amplifier transistor in the pixel to amplify the output from the pixel. It is a schematic diagram which shows an example of a circuit structure.
- the pixel 820 includes an amplifier transistor 821 configured with a source grounded PMOS transistor instead of the amplifier transistor 314 configured with a source grounded NMOS transistor of FIG. Since the configuration of the pixels other than the amplifier transistor 821 is the same as that in FIGS. 2 and 19, the same reference numerals as those in FIG.
- the amplifier transistor 821 is an amplifier transistor composed of a common source PMOS transistor.
- the amplifier transistor 821 has a gate terminal connected to the FD 322 and a source terminal connected to the power supply line 323 and the drain terminal of the reset transistor 313.
- the amplifier transistor 821 has a drain terminal connected to the constant current source 829 and the digital value generation circuit via the vertical signal line 341.
- the amplifier transistor 821 has a positive phase output, similar to the amplifier transistor 314 of FIG.
- an NMOS transistor common to a CMOS image sensor can be used as a constant current load (a load of a constant current source 829).
- the operating point can be secured without setting the power supply potential of the constant current source higher than the power supply potential of the pixel, and the setting of the operating point becomes easy.
- the output of the pixel can be amplified also by providing the pixel with the common-source amplifier transistor.
- the output of the pixel can be amplified by various methods. 19 and FIG. 20 can easily amplify the output of the pixel signal with a simple structure, but gain variation greatly increases in order to obtain large amplification in an open loop.
- the determination threshold for binary determination can be set for each pixel in the imaging device with variable gain, and thus adverse effects caused by gain variations in photon counting are reduced. be able to.
- by providing a binary determination unit that can set a determination threshold for each pixel in an imaging device that includes an amplifier unit that amplifies a weak signal erroneous determination due to gain variation by the amplifier unit is prevented.
- a weak signal can be detected with high accuracy.
- the adjustment device 550 obtains the threshold value from the non-accumulation signal of the pixels that are not exposed. However, the adjustment device 550 can also obtain the threshold value from the signal of the exposed pixel.
- the adjustment device 550 of the second embodiment is different from the first embodiment in that a threshold value is obtained from a signal of an exposed pixel.
- FIG. 21 is a graph illustrating an example of the relationship between the standard deviation of digital values and the average value according to the second embodiment of the present technology.
- the signal amount (gradation value) of the accumulated signal of the pixel on which the photon is incident varies according to the conversion efficiency of the accumulated charge into a digital value.
- the relationship between the signal amount of the accumulated signal and the number of accumulated charges is expressed by the following Equation 5.
- Av ⁇ ⁇ N Equation 5
- Av is the average value of the signal amount
- N is the number of accumulated charges.
- ⁇ is the conversion efficiency of accumulated charges into a digital value.
- Equation 6 ⁇ is the standard deviation of the signal amount, N is the number of charges, and ⁇ is the conversion efficiency.
- Equation 7 The average value Av and the standard deviation ⁇ are different values depending on the exposure amount. Therefore, if the exposure amount is changed to obtain a set of the average value Av and the standard deviation ⁇ at each exposure amount, and at least two sets of values are obtained, the conversion efficiency ⁇ can be obtained by the substitution method or the like based on Equation 7.
- the adjustment device 550 may use a least square method or the like when obtaining the conversion efficiency ⁇ . Specifically, the adjustment device 550 uses the standard deviation value obtained by substituting the measured value of the average value Av in Equation 7 as the theoretical value, and the sum of squares of the difference between the measured value of the standard deviation ⁇ and the theoretical value. The value of the conversion efficiency ⁇ that minimizes is calculated.
- FIG. 21 is a graph showing an example of the relationship between the average value Av and the standard deviation ⁇ shown in Equation 7.
- the horizontal axis represents the average value Av
- the vertical axis represents the square of the standard deviation ⁇ .
- White circles on the graph are points obtained by measurement. Based on Equation 7, a proportional line is obtained from these points. The slope of this straight line corresponds to the conversion efficiency ⁇ .
- FIG. 22 is a flowchart illustrating an example of a processing procedure of adjustment value calculation by the adjustment value calculation unit 551 of the adjustment device 550 according to the second embodiment of the present technology.
- Adjusting device 550 first, exposure of one M at a constant exposure, the digital value converted from the stored signal of the exposed pixel to obtain M 1 times.
- M 1 is an integer of 2 or more (step S931).
- the adjustment device 550 calculates the average value Av and the standard deviation ⁇ of the digital values for the exposure amount for each pixel (step S932).
- the adjusting device 550 determines, for each pixel, whether or not the set of the average value Av and the standard deviation ⁇ has been calculated M 2 times.
- M 2 is an integer of 2 or more (step S933).
- step S933 If not calculated M 2 times (step S933: No), the adjustment device 550 changes the amount of exposure (step S934), the flow returns to step S931. If the calculated M 2 times (step S933: Yes), the adjustment device 550, a set of average values Av and standard deviation ⁇ for each exposure, calculates the conversion efficiency ⁇ based on the equation 7 (step S935) .
- Adjustment device 550 calculates a value obtained by multiplying ⁇ by K2 for each pixel (step S936).
- K2 is a real number, for example, a value of approximately 1 ⁇ 2 is set.
- the value of K2 is set in consideration of which priority between missing count and erroneous determination is increased.
- the adjustment device 550 converts the calculated threshold values into adjustment values, respectively, and records them in the adjustment value holding unit 210 (step S937).
- the adjustment device 550 calculates an average value and a standard deviation of digital values for each exposure amount, and calculates a threshold value from these values. An accurate threshold according to efficiency can be obtained. By using this threshold value, it is possible to improve the accuracy of determination of photons that have entered the pixel.
- the image pickup element shown in the embodiment of the present technology can be widely applied as a light detection unit in a conventional electronic device provided with a photomultiplier tube, an avalanche photodiode, or a photodiode.
- a fluorescence scanner of an imaging plate and a scintillation counter of radiation can be applied to DNA chip detectors, X-ray imaging devices called DR (Digital Radiography), CT (Computed Tomography) devices, SPECT (Single Photon Emission Tomography) devices, and the like.
- DR Digital Radiography
- CT Computed Tomography
- SPECT Single Photon Emission Tomography
- CMOS image sensor since it is a CMOS image sensor and can be mass-produced at a low price, a large number of light detection units are provided in an electronic device in which only a small number of light detection units are provided due to the high price of photomultiplier tubes. As a result, the detection speed can be improved.
- the imaging device shown in the embodiment of the present technology is introduced into a detector of a CT apparatus, it is possible to detect scintillation light with a much higher sensitivity than a detector using a conventional photodiode or the like, and high accuracy of detection. This can contribute to the reduction in exposure due to the reduction of the X-ray dose and the X-ray dose.
- detection of gamma rays such as SPECT and PET, which conventionally used a photomultiplier tube.
- the effect is not limited only to an electronic device provided with a large number of detection heads, but the same effect can be obtained in an electronic device using a single detection head.
- a pocket dosimeter having a small size and a light weight and an ultra-high sensitivity can be realized using an inexpensive semiconductor imaging device.
- the binary determination unit is provided in the image sensor.
- the present invention is not limited to this.
- a digital value provided for each vertical signal line 341 (for each column). It may be provided for each generation circuit 400.
- the amplifier unit that amplifies the signal output from the pixel is only one stage.
- the present invention is not limited to this, and a plurality of amplifiers are provided to amplify the signal. You may make it do. For example, when an amplifier (fifth and sixth modifications) provided in a pixel and an amplifier (first to fourth modifications) provided for each column are combined, or the amplifier provided for each column is multistage. The case where it connects to is considered.
- the binary determination (binary determination) of “with photon incidence” and “without photon incidence” has been described, but a plurality of reference signals (REF) are used.
- REF reference signals
- two systems of reference signals (REF) are prepared, and one system is set to an intermediate value between a digital value when the number of photons is “0” and a digital value when the number of photons is “1”.
- the other system (second system) is set to an intermediate value between the digital value when the number of photons is “1” and the digital value when the number of photons is “2”.
- the adjustment value holding unit 210 holds information regarding the threshold value of the second system, and can be implemented in the same manner as in the embodiment of the present technology.
- the threshold value of the second system can be calculated, for example, by setting the constant K in Expression 2 shown in FIG. 10 to a constant K ′ having a value larger than the constant K.
- the constant K It is good also considering the value which multiplied 3 as constant K '.
- the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it.
- this recording medium for example, a hard disk, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray (registered trademark) disc, or the like can be used.
- this technique can also take the following structures.
- a generation unit that generates a digital value indicating the amount of charge accumulated by photons incident on the pixel during an exposure period based on a signal output from the pixel;
- a threshold value set for each pixel having a similar conversion efficiency when converting the amount of charge accumulated in the pixel into a digital value generated by the generation unit is compared with the generated digital value.
- An image sensor comprising: a determination unit that determines the incidence of a photon on a pixel that outputs the signal.
- the amplification unit is provided for each pixel, The image sensor according to (2), wherein the determination unit performs the determination using a threshold value set for each pixel, using the magnification at the time of amplifying the signal as the conversion efficiency.
- the amplifying unit includes a common-source amplifier transistor provided for each pixel.
- the amplification unit is provided in units of columns with respect to the pixels arranged in a matrix, The image sensor according to (2), wherein the determination unit performs the determination using a threshold value set for each column unit, using the magnification at the time of amplifying the signal as the conversion efficiency.
- the amplifying unit includes an operational amplifier or a CMOS (Complementary Metal Oxide Semiconductor) inverter.
- the amplifying unit includes a feedback circuit that feeds back a potential in the signal to a potential in a floating diffusion of a pixel that outputs the signal.
- a holding unit that holds a threshold designation value for designating the threshold with a smaller number of bits than the number of bits necessary to indicate the digital value generated by the generation unit for each pixel having similar conversion efficiency.
- the determination unit acquires the threshold value specification value of a pixel that outputs a signal converted into the digital value to be determined, and acquires the threshold value based on a table indicating an association between the digital value and the threshold value specification value.
- the imaging device according to any one of (1) to (7), wherein a threshold value is converted into a gradation value of the digital value and the threshold value is set. (9) The threshold value is obtained by obtaining a digital value obtained by converting a reset signal, which is a signal in a state where there is no charge accumulation due to photons, for each pixel having similar conversion efficiency, and from the obtained digital values.
- the imaging device according to any one of (1) to (8), which is calculated based on the calculated standard deviation and average value.
- a generation unit that generates a digital value indicating the amount of charge accumulated by photons incident on the pixel during an exposure period based on a signal output from the pixel;
- a threshold value set for each pixel having a similar conversion efficiency when converting the amount of charge accumulated in the pixel into a digital value generated by the generation unit is compared with the generated digital value.
- An imaging device comprising: a determination unit that determines the incidence of a photon on a pixel that outputs the signal.
- a generation unit that generates a digital value indicating the amount of charge accumulated by photons incident on the pixel during an exposure period based on a signal output from the pixel; A threshold value set for each pixel having a similar conversion efficiency when converting the amount of charge accumulated in the pixel into a digital value generated by the generation unit is compared with the generated digital value.
- An electronic apparatus comprising: a determination unit that determines the incidence of a photon on a pixel that outputs the signal. (13) Based on the signal output from the pixel, a generation unit that generates a digital value indicating the amount of charge accumulated by photons incident on the pixel during the exposure period; and the amount of charge accumulated in the pixel Incident of a photon to a pixel that outputs the signal by comparing the generated digital value with a threshold value set for each pixel having similar conversion efficiency when converted into a digital value generated by the generation unit
- An acquisition unit that acquires the digital value generated by the imaging device including a determination unit that performs the determination of multiple times for each pixel with similar conversion efficiency;
- a threshold value calculation apparatus comprising: a calculation unit that calculates the threshold value based on a standard deviation and an average value of the acquired digital values.
- the threshold value calculation device wherein the signal is a reset signal in a state where there is no charge accumulation due to photons.
- the signal is a signal in a state where charges are accumulated by photons.
- a generation procedure for generating a digital value indicating the amount of charge accumulated by photons incident on the pixel during an exposure period based on a signal output by the pixel;
- the threshold value set for each pixel having similar conversion efficiency when converting the amount of charge accumulated in the pixel into a digital value generated by the generation procedure is compared with the generated digital value.
- a determination procedure for determining the incidence of photons on the pixel that has output the signal.
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Abstract
Description
1.第1の実施の形態(撮像制御:画素ごとの閾値を用いて光子の入射のバイナリ判定を行う例)
2.第2の実施の形態(撮像制御:露光させた画素のデジタル値から画素ごとの閾値を求める例)
[撮像素子の構成例]
図1は、本技術の第1の実施の形態の撮像素子100の基本構成例の一例を示す概念図である。
図2は、本技術の第1の実施の形態の画素310の回路構成の一例を示す模式図である。
図3は、本技術の第1の実施の形態の画素310のレイアウトの一例を模式的に示す図である。
図4は、本技術の第1の実施の形態のデジタル値生成回路400の機能構成例の一例およびデジタル値生成回路400の動作例の一例を示す概念図である。
図5は、本技術の第1の実施の形態の調整値保持部210が保持する調整値を説明するための図である。
図6は、本技術の第1の実施の形態において、単位露光期間に各画素に入射する光子の平均数とカウント確率との関係を示すグラフである。
単位画素に入射する光子が0個(k=0)の確率:0.8105
単位画素に入射する光子が1個(k=1)の確率:0.1702
単位画素に入射する光子が2個(k=2)の確率:0.0179
単位画素に入射する光子が3個(k=3)の確率:0.0013
・・・(これ以下は、値が非常に小さい(0.00007以下)ので省略)
図7は、本技術の第1の実施の形態の調整値保持部210に保持されている画素ごとの調整値を用いてバイナリ判定を行うことの効果を模式的に示す図である。
次に、本技術の第1の実施の形態における撮像素子100のバイナリ判定部220の動作について図面を参照して説明する。
図9は、本技術の第1の実施の形態において、撮像素子100の調整値保持部210に調整値を保持させる際の調整値の算出方法の一例を説明するための機能構成図である。
図10は、本技術の第1の実施の形態における調整値算出部551による調整値の算出を模式的に示す図である。
Vth=Av+K1・σ ・・・式2
ここで、K1は、定数である。この定数K1は、式2により算出される閾値Vthが、無蓄積信号の平均(ピーク)の位置(位置G21、位置G22)と、1光子信号の平均(ピーク)の位置との間の中間ぐらいの位置(信号量(階調))になるように設定される。
次に、本技術の第1の実施の形態における調整装置550の調整値算出部551による調整値算出動作について図面を参照して説明する。
ここまでの図1乃至図11を参照して示した本技術の第1の実施の形態では、調整値を用いたバイナリ判定に着目し、種々な例が考えられるアンプ部440については説明を省略した。
図12は、本技術の第1の実施の形態の第1の変形例として示すオペアンプのアンプ部440の回路構成例の一例を模式的に示す図である。
図13は、本技術の第1の実施の形態の第1の変形例として示すアンプ回路460およびデジタル値生成回路400の動作の一例を示すタイミングチャートである。
図14は、本技術の第1の実施の形態の第1の変形例として示すアンプ回路460およびデジタル値生成回路400を備える撮像素子100のリセット信号カウント期間と、他の撮像素子のリセット信号カウント期間とを模式的に示す図である。
図15は、本技術の第1の実施の形態の第1の変形例におけるREF信号のランプ波形と、他の撮像素子におけるREF信号のランプ波形とを比較するための表である。
図16は、本技術の第1の実施の形態の第2の変形例として示すインバータのアンプ回路(アンプ回路710)の回路構成例の一例を模式的に示す図である。
図17は、本技術の第1の実施の形態の第3の変形例として示すフローティングディフュージョンに画素の出力をフィードバックさせる例における画素(画素830)の回路構成の一例を示す模式図である。
このように、画素の出力をFD322にフィードバックすることによっても、画素の出力を増幅することができる。
図19は、本技術の第1の実施の形態の第5の変形例として示すソース接地型のNMOSトランジスタをアンプトランジスタとして画素に設けて画素からの出力を増幅する例における画素(画素810)の回路構成の一例を示す模式図である。
ΔId=gm・ΔVg+ΔVd/Rd ・・・式3
ここで、ΔIdは、増幅前のドレイン電流からのドレイン電流の変化量である。また、gmは、相互コンダクタンスである。ΔVgは、増幅前のゲート電圧からのゲート電圧の変化量であり、Rdは、ドレイン抵抗であり、ΔVdは、増幅前のドレイン電圧からのドレイン電圧の変化量である。
第1の実施の形態では、調整装置550は、露光させていない画素の無蓄積信号から、閾値を求めていた。しかし、調整装置550は、露光させた画素の信号から閾値を求めることもできる。第2の実施の形態の調整装置550は、露光させた画素の信号から閾値を求める点において第1の実施の形態と異なる。
Av=η×N ・・・式5
式5において、Avは、信号量の平均値であり、Nは蓄積された電荷の個数である。また、ηは、蓄積された電荷のデジタル値への変換効率である。
σ=η×N1/2 ・・・式6
式6において、σは、信号量の標準偏差であり、Nは電荷の個数、ηは変換効率である。
σ2=η×Av ・・・式7
平均値Avおよび標準偏差σは、露光量に応じて異なる値となる。したがって、露光量を変えて、それぞれの露光量における平均値Avおよび標準偏差σの組を求め、少なくとも2組の値を求めれば、式7に基づいて代入法などにより変換効率ηが得られる。
(1) 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、
前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定部と
を具備する撮像素子。
(2) 前記信号を1より大きい倍率で増幅する増幅部をさらに具備し、
前記生成部は、前記増幅された信号に基づいて前記生成を行う
前記(1)に記載の撮像素子。
(3) 前記増幅部は、前記画素ごとに設けられ、
前記判定部は、前記信号を増幅する際の倍率を前記変換効率とし、前記画素ごとに設定されている閾値を用いて前記判定を行う
前記(2)に記載の撮像素子。
(4) 前記増幅部は、前記画素ごとに設けられるソース接地型のアンプトランジスタにより構成される前記(3)に記載の撮像素子。
(5) 前記増幅部は、行列状に配置されている前記画素に対して列単位で設けられ、
前記判定部は、前記信号を増幅する際の倍率を前記変換効率とし、前記列単位ごとに設定されている閾値を用いて前記判定を行う
前記(2)に記載の撮像素子。
(6) 前記増幅部は、オペアンプまたはCMOS(Complementary Metal Oxide Semiconductor)インバータにより構成される前記(5)に記載の撮像素子。
(7) 前記増幅部は、前記信号における電位を、前記信号を出力した画素のフローティングディフュージョンにおける電位にフィードバックさせるためのフィードバック回路により構成される前記(5)に記載の撮像素子。
(8) 前記生成部により生成されるデジタル値を示すのに必要なビット数よりも少ないビット数で前記閾値を指定するための閾値指定値を前記変換効率が類似する画素ごとに保持する保持部をさらに具備し、
前記判定部は、前記判定対象となるデジタル値に変換された信号を出力した画素の前記閾値指定値を取得し、前記デジタル値と前記閾値指定値との関連付けを示すテーブルに基づいて前記取得した閾値指定値を前記デジタル値の階調値に変換して前記閾値を設定する
前記(1)から(7)のいずれかに記載の撮像素子。
(9) 前記閾値は、光子による電荷の蓄積が無い状態における信号であるリセット信号を変換したデジタル値を前記変換効率が類似する画素ごとに複数回取得し、当該取得された複数のデジタル値から算出された標準偏差および平均値に基づいて算出される前記(1)から(8)のいずれかに記載の撮像素子。
(10) 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、
前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定部と
を具備する撮像装置。
(11) 光子による電荷の蓄積が無い状態における信号であるリセット信号を変換したデジタル値を前記変換効率が類似する画素ごとに複数回取得して、当該取得した複数のデジタル値の標準偏差および平均値に基づいて前記閾値を算出する算出部をさらに具備する
前記(10)に記載の撮像装置。
(12) 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、
前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定部と
を具備する電子機器。
(13) 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と前記生成されたデジタル値とを比較して前記信号を出力した画素への光子の入射の判定を行う判定部とを備える撮像素子が生成した前記デジタル値を前記変換効率が類似する画素ごとに複数回取得する取得部と、
前記取得されたデジタル値の標準偏差および平均値に基づいて前記閾値を算出する算出部と
を具備する閾値算出装置。
(14) 前記信号は、光子による電荷の蓄積が無い状態におけるリセット信号である前記(13)記載の閾値算出装置。
(15) 前記信号は、光子により電荷が蓄積された状態における信号であり、
前記取得部は、露光させた前記撮像素子により生成された前記デジタル値を複数回取得する処理を異なる露光量により複数回実行し、
前記算出部は、前記露光量ごとに求めた前記標準偏差および前記平均値から前記閾値を算出する前記(13)記載の閾値算出装置。
(16) 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成手順と、
前記画素において蓄積される電荷の量を前記生成手順により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定手順と
を具備する撮像方法。
110 垂直駆動回路
130 レジスタ
150 出力回路
210 調整値保持部
220 バイナリ判定部
300 画素アレイ部
310 画素
311 フォトダイオード
312 転送トランジスタ
313 リセットトランジスタ
314 アンプトランジスタ
400 デジタル値生成回路
440 アンプ部
550 調整装置
551 調整値算出部
Claims (16)
- 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、
前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定部と
を具備する撮像素子。 - 前記信号を1より大きい倍率で増幅する増幅部をさらに具備し、
前記生成部は、前記増幅された信号に基づいて前記生成を行う
請求項1記載の撮像素子。 - 前記増幅部は、前記画素ごとに設けられ、
前記判定部は、前記信号を増幅する際の倍率を前記変換効率とし、前記画素ごとに設定されている閾値を用いて前記判定を行う
請求項2記載の撮像素子。 - 前記増幅部は、前記画素ごとに設けられるソース接地型のアンプトランジスタにより構成される請求項3記載の撮像素子。
- 前記増幅部は、行列状に配置されている前記画素に対して列単位で設けられ、
前記判定部は、前記信号を増幅する際の倍率を前記変換効率とし、前記列単位ごとに設定されている閾値を用いて前記判定を行う
請求項2記載の撮像素子。 - 前記増幅部は、オペアンプまたはCMOS(Complementary Metal Oxide Semiconductor)インバータにより構成される請求項5記載の撮像素子。
- 前記増幅部は、前記信号における電位を、前記信号を出力した画素のフローティングディフュージョンにおける電位にフィードバックさせるためのフィードバック回路により構成される請求項5記載の撮像素子。
- 前記生成部により生成されるデジタル値を示すのに必要なビット数よりも少ないビット数で前記閾値を指定するための閾値指定値を前記変換効率が類似する画素ごとに保持する保持部をさらに具備し、
前記判定部は、前記判定対象となるデジタル値に変換された信号を出力した画素の前記閾値指定値を取得し、前記デジタル値と前記閾値指定値との関連付けを示すテーブルに基づいて前記取得した閾値指定値を前記デジタル値の階調値に変換して前記閾値を設定する
請求項1記載の撮像素子。 - 前記閾値は、光子による電荷の蓄積が無い状態における信号であるリセット信号を変換したデジタル値を前記変換効率が類似する画素ごとに複数回取得し、当該取得された複数のデジタル値から算出された標準偏差および平均値に基づいて算出される請求項1記載の撮像素子。
- 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、
前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定部と
を具備する撮像装置。 - 光子による電荷の蓄積が無い状態における信号であるリセット信号を変換したデジタル値を前記変換効率が類似する画素ごとに複数回取得して、当該取得した複数のデジタル値の標準偏差および平均値に基づいて前記閾値を算出する算出部をさらに具備する請求項10記載の撮像装置。
- 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、
前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定部と
を具備する電子機器。 - 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成部と、前記画素において蓄積される電荷の量を前記生成部により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と前記生成されたデジタル値とを比較して前記信号を出力した画素への光子の入射の判定を行う判定部とを備える撮像素子が生成した前記デジタル値を前記変換効率が類似する画素ごとに複数回取得する取得部と、
前記取得されたデジタル値の標準偏差および平均値に基づいて前記閾値を算出する算出部と
を具備する閾値算出装置。 - 前記信号は、光子による電荷の蓄積が無い状態におけるリセット信号である請求項13記載の閾値算出装置。
- 前記信号は、光子により電荷が蓄積された状態における信号であり、
前記取得部は、露光させた前記撮像素子により生成された前記デジタル値を複数回取得する処理を異なる露光量により複数回実行し、
前記算出部は、前記露光量ごとに求めた前記標準偏差および前記平均値から前記閾値を算出する請求項13記載の閾値算出装置。 - 画素が出力した信号に基づいて、露光期間中に前記画素に入射した光子により蓄積された電荷の量を示すデジタル値を生成する生成手順と、
前記画素において蓄積される電荷の量を前記生成手順により生成されるデジタル値に変換する際の変換効率が類似する画素ごとに設定されている閾値と、前記生成されたデジタル値とを比較して、前記信号を出力した画素への光子の入射の判定を行う判定手順と
を具備する撮像方法。
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JP2021153346A (ja) * | 2017-05-18 | 2021-09-30 | キヤノン株式会社 | 固体撮像素子及び撮像装置 |
JP7223070B2 (ja) | 2017-05-18 | 2023-02-15 | キヤノン株式会社 | 固体撮像素子及び撮像装置 |
JP2021192518A (ja) * | 2017-08-07 | 2021-12-16 | ウェイモ エルエルシー | フルデジタルのモノリシックなフレーム平均化レシーバに関する非結像spadアーキテクチャの集約 |
JP7150112B2 (ja) | 2017-08-07 | 2022-10-07 | ウェイモ エルエルシー | フルデジタルのモノリシックなフレーム平均化レシーバに関する非結像spadアーキテクチャの集約 |
WO2020129150A1 (ja) * | 2018-12-18 | 2020-06-25 | 株式会社日立ハイテク | 測定装置、及び信号処理方法 |
JPWO2020129150A1 (ja) * | 2018-12-18 | 2021-10-28 | 株式会社日立ハイテク | 測定装置、及び信号処理方法 |
JP7121140B2 (ja) | 2018-12-18 | 2022-08-17 | 株式会社日立ハイテク | 測定装置、及び信号処理方法 |
US11842881B2 (en) | 2018-12-18 | 2023-12-12 | Hitachi High-Tech Corporation | Measurement device and signal processing method |
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KR20150099727A (ko) | 2015-09-01 |
CN104838645A (zh) | 2015-08-12 |
US9602745B2 (en) | 2017-03-21 |
TW201433164A (zh) | 2014-08-16 |
EP2938066A4 (en) | 2016-10-19 |
US20160219234A1 (en) | 2016-07-28 |
EP2938066A1 (en) | 2015-10-28 |
TWI623230B (zh) | 2018-05-01 |
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