WO2014080639A1 - Solar cell - Google Patents

Solar cell Download PDF

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Publication number
WO2014080639A1
WO2014080639A1 PCT/JP2013/006909 JP2013006909W WO2014080639A1 WO 2014080639 A1 WO2014080639 A1 WO 2014080639A1 JP 2013006909 W JP2013006909 W JP 2013006909W WO 2014080639 A1 WO2014080639 A1 WO 2014080639A1
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type semiconductor
semiconductor layer
layer
ratio
electrode layer
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PCT/JP2013/006909
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French (fr)
Japanese (ja)
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橋本　泰宏
根上　卓之
樋口　洋
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
    • H01L31/0322—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312 comprising only AIBIIICVI chalcopyrite compounds, e.g. Cu In Se2, Cu Ga Se2, Cu In Ga Se2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03926—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate comprising a flexible substrate
    • H01L31/03928—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate comprising a flexible substrate including AIBIIICVI compound, e.g. CIS, CIGS deposited on metal or polymer foils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02485—Other chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02557—Sulfides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02568—Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/541—CuInSe2 material PV cells

Definitions

  • the present invention relates to a solar cell, and more specifically to a solar cell using a compound semiconductor layer as a light absorption layer.
  • a thin film solar cell using a compound semiconductor having a chalcopyrite structure such as Cu (In, Ga) Se 2 as a light absorption layer has been conventionally known.
  • Cu (In, Ga) Se 2 and at least a part of Se thereof are replaced by S (sulfur) may be collectively referred to as “CIGS”.
  • the band gap of the CIGS layer which is a light absorption layer can be changed by changing the ratio of In and Ga.
  • the band gap of CuInSe 2 is 1.02 eV
  • the band gap of CuGaSe 2 is 1.69 eV. Therefore, the band gap of Cu (In, Ga) Se 2 can be changed within the range of 1.02 to 1.69 eV by changing the ratio of In to Ga.
  • Patent Documents 1 and 2 In a CIGS solar cell using CIGS as a light absorption layer, a method of providing a gradient in the Ga concentration in the light absorption layer has been conventionally proposed (see Patent Documents 1 and 2). It is described in paragraph [0010] of Patent Document 2 that the conversion efficiency can be improved by providing a gradient in the Ga concentration.
  • one of the objects of the present invention is to provide a solar cell capable of reducing the cost without greatly reducing the conversion efficiency.
  • one embodiment of the present invention includes a first electrode layer, a second electrode layer, and a p disposed between the first electrode layer and the second electrode layer.
  • a solar cell including a p-type semiconductor layer and an n-type semiconductor layer disposed between the p-type semiconductor layer and the second electrode layer, wherein the p-type semiconductor layer comprises a group 11 element, a group 13 And a p-type semiconductor layer containing In and Ga as the group 13 element, and the thickness of the p-type semiconductor layer is 0.5.
  • the value of ((the number of Ga atoms) / (the number of Ga atoms + the number of In atoms)) in the p-type semiconductor layer is in the range of .about.0.7 ⁇ m from the n-type semiconductor layer side to the first electrode.
  • the p-type half of the main surface on the n-type semiconductor layer side increases toward the layer side.
  • the value of ((number of Ga atoms) / (number of Ga atoms + In atoms)) of the body layer is in the range of 0.225 to 0.325, and the p on the main surface on the first electrode layer side
  • the value of ((the number of Ga atoms) / (the number of Ga atoms + the number of In atoms)) of the large semiconductor layer is in the range of 0.375 to 0.542.
  • a solar cell capable of reducing the cost without greatly reducing the conversion efficiency can be obtained.
  • FIG. 6 is a diagram showing a profile of a Ga / (Ga + In) ratio in a p-type semiconductor layer assumed in the simulation of Example 1.
  • FIG. 10 is a diagram illustrating an example of a profile of a Ga / (Ga + In) ratio in a p-type semiconductor layer assumed in a simulation of Example 2.
  • FIG. 6 is a diagram showing measured values of a Ga / (Ga + In) ratio in a p-type semiconductor layer produced in Example 3.
  • FIG. 10 is a diagram illustrating an example of a profile of a Ga / (Ga + In) ratio in a p-type semiconductor layer assumed in the simulation of Example 4.
  • FIG. It is a figure which shows the relationship between Ga / (Ga + In) ratio of the p-type semiconductor layer in two main surfaces, and conversion efficiency. It is a figure which shows the relationship between the Ga / (Ga + In) ratio of the p-type semiconductor layer in two main surfaces, and conversion efficiency when a p-type semiconductor layer is thickened.
  • the solar cell of the present embodiment includes a first electrode layer, a second electrode layer, a p-type semiconductor layer disposed between the first electrode layer and the second electrode layer, and a p-type semiconductor layer. And an n-type semiconductor layer disposed between the first electrode layer and the second electrode layer.
  • the p-type semiconductor layer is made of a compound semiconductor containing a group 11 element, a group 13 element, and a group 16 element and having a chalcopyrite structure.
  • the p-type semiconductor layer contains In and Ga as group 13 elements.
  • the thickness of the p-type semiconductor layer is in the range of 0.5 to 0.7 ⁇ m.
  • the p-type semiconductor layer is a layer that functions as a light absorption layer.
  • the value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) in the p-type semiconductor layer changes in the film thickness direction.
  • the value of ((Ga atom number) / (Ga atom number + In atom number)) in the p-type semiconductor layer may be hereinafter referred to as “Ga / (Ga + In) ratio”.
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer (light absorption layer) satisfies the following three requirements.
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer increases from the n-type semiconductor layer side toward the first electrode layer side.
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the n-type semiconductor layer side is in the range of 0.225 to 0.325. This Ga / (Ga + In) ratio may be greater than 0.225 and less than 0.325.
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the first electrode layer side is in the range of 0.375 to 0.542. This Ga / (Ga + In) ratio may be greater than 0.375 and less than 0.542.
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer continuously increases from the n-type semiconductor layer side toward the first electrode layer side.
  • this ratio preferably increases substantially linearly from the n-type semiconductor layer side toward the first electrode layer side.
  • the solar cell of this embodiment can achieve relatively high conversion efficiency even if the p-type semiconductor layer is thin. Therefore, according to the solar cell of this embodiment, it is possible to achieve both high conversion efficiency and low cost.
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer (light absorption layer) may further satisfy the following two requirements.
  • the following ranges (4) and (5) are obtained by narrowing the above ranges (2) and (3).
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the n-type semiconductor layer side is in the range of 0.250 to 0.300.
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the first electrode layer side is in the range of 0.417 to 0.500.
  • the group 11 element constituting the p-type semiconductor layer may contain Cu, for example, Cu.
  • the group 16 element constituting the p-type semiconductor layer may be at least one element selected from Se and S. Examples of the p-type semiconductor layer in this case include a CIGS layer represented by Cu (In, Ga) Se 2 or Cu (In, Ga) (Se, S) 2 .
  • the value of ((number of Ga atoms) / (number of group 13 element atoms)) in the p-type semiconductor layer may increase from the n-type semiconductor layer side toward the first electrode layer side. In a preferred example, the value increases continuously or linearly from the n-type semiconductor layer side toward the first electrode layer side.
  • group 13 elements other than In and Ga include Al.
  • FIG. 1 A cross-sectional view of an example of the solar cell of the present embodiment is shown in FIG.
  • a solar cell that generates power using light incident from the second electrode layer side will be described, but the solar cell of the present embodiment is not limited to this.
  • a solar cell 10 shown in FIG. 1 includes a substrate 11, a first electrode layer 12, a second electrode layer 15, and a p-type semiconductor layer disposed between the first electrode layer 12 and the second electrode layer 15. 13, an n-type semiconductor layer 14 disposed between the second electrode layer 15 and the p-type semiconductor layer 13, and extraction electrodes 16 and 17.
  • the first electrode layer 12, the p-type semiconductor layer 13, the n-type semiconductor layer 14, and the second electrode layer 15 are stacked on the substrate 11 in this order.
  • the n-type semiconductor layer 14 is a semiconductor layer that can form a pn junction with the p-type semiconductor layer 13 that is a light absorption layer.
  • the n-type semiconductor layer 14 usually functions as a window layer.
  • the p-type semiconductor layer 13 functions as a light absorption layer.
  • photovoltaic power is generated by light incident from the second electrode layer 15 side.
  • the generated photovoltaic power is transmitted to the outside through the extraction electrode 16 electrically connected to the first electrode layer 12 and the extraction electrode 17 electrically connected to the second electrode layer 15. Can do.
  • the p-type semiconductor layer 13 is disposed above the first electrode layer 12 (on the light incident side).
  • the p-type semiconductor layer 13 includes a group 11 element, a group 13 element, In and Ga, and a group 16 element, and is made of a compound semiconductor having a crystal structure (chalcopyrite structure) similar to chalcopyrite. .
  • the element group designation in this specification is based on the provisions of IUPAC (1989). Based on the provisions of IUPAC (1970), the Group 11 element corresponds to Group Ib, the Group 13 element corresponds to Group IIIb, and the Group 16 element corresponds to Group VIb.
  • Cu copper
  • the group 11 element can be used as the group 11 element.
  • the group 16 element for example, at least one element selected from Se (selenium) and S (sulfur) can be used.
  • the group 11 element is Cu
  • the group 13 element is In and Ga
  • the group 16 element is at least one element selected from Se and S.
  • the p-type semiconductor layer 13 can be formed using Cu (In, Ga) Se 2 , Cu (In, Ga) (Se, S) 2, or the like.
  • the thickness of the p-type semiconductor layer 13 is in the range of 0.5 ⁇ m to 0.7 ⁇ m.
  • the value of ((number of Ga atoms) / (number of Ga atoms + In number of atoms)) (that is, Ga / (Ga + In) ratio) is the first value from the n-type semiconductor layer 14 side. It increases toward the electrode layer 12 side.
  • the band gap of the p-type semiconductor layer 13 increases from the n-type semiconductor layer 14 side toward the first electrode layer 12 side.
  • the Ga / (Ga + In) ratio in another aspect, the band gap) increases linearly from the n-type semiconductor layer 14 side toward the first electrode layer 12 side.
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side is in the range of 0.225 to 0.325.
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the first electrode layer 12 side is in the range of 0.375 to 0.542.
  • the main surface on the n-type semiconductor layer 14 side means the main surface on the n-type semiconductor layer 14 side of the two main surfaces of the p-type semiconductor layer 13.
  • the main surface on the first electrode layer 12 side means the main surface on the first electrode layer 12 side among the two main surfaces of the p-type semiconductor layer 13.
  • the solar cell 10 having the above configuration, high conversion efficiency can be achieved even when the light absorption layer is as thin as 0.5 ⁇ m to 0.7 ⁇ m.
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side is in the range of 0.250 to 0.300, and the main surface on the first electrode layer 12 side is.
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 in the plane is in the range of 0.417 to 0.500.
  • the first electrode layer 12, the p-type semiconductor layer 13, and the n-type semiconductor layer 14 are disposed adjacent to each other.
  • the portion of the p-type semiconductor layer 13 adjacent to the n-type semiconductor layer 14 has a Ga / (Ga + In) ratio in the range of 0.225 to 0.325, and the p-type semiconductor layer
  • the Ga / (Ga + In) ratio of the portion adjacent to the first electrode layer 12 in 13 is in the range of 0.375 to 0.542.
  • the Ga / (Ga + In) ratio of the portion adjacent to the n-type semiconductor layer 14 in the p-type semiconductor layer 13 is in the range of 0.250 to 0.300, and p It can also be said that the Ga / (Ga + In) ratio of the portion adjacent to the first electrode layer 12 in the large semiconductor layer 13 is in the range of 0.417 to 0.500.
  • the Ga / (Ga + In) ratio described above can be realized by changing the composition of the p-type semiconductor layer 13 in the film thickness direction. More specifically, it can be realized by changing the Ga and In concentrations in the p-type semiconductor layer 13 in the film thickness direction.
  • the value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) of the p-type semiconductor layer 13 is a value of ((number of Ga atoms) / (number of atoms of group 13 element)).
  • the band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.225 to 0.325 is 1.15 to 1.21 eV.
  • the band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.375 to 0.542 is in the range of 1.25 to 1.36 eV.
  • the band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.250 to 0.300 is , 1.17 to 1.20 eV.
  • the band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.417 to 0.500 is in the range of 1.27 to 1.33 eV.
  • the material used for the substrate 11 is not particularly limited as long as it is a material generally used for solar cells.
  • a substrate made of a non-metallic material such as a glass substrate or a polyimide substrate, an aluminum alloy substrate such as duralumin, or a substrate made of a metal material such as a stainless steel substrate may be used.
  • the solar cell of this embodiment is an integrated solar cell which forms the several unit cell connected in series on the board
  • substrate 11 needs to be insulating. For this reason, when a conductive substrate (for example, a stainless steel substrate) is used, it is necessary to form an insulating layer on the surface of the substrate or to insulate the surface of the substrate.
  • the material used for the first electrode layer 12 is not particularly limited as long as it has conductivity.
  • a metal or semiconductor having a volume resistivity of 6 ⁇ 10 6 ⁇ ⁇ cm or less may be used.
  • Mo (molybdenum) can be used.
  • the shape of the 1st electrode layer 12 is not specifically limited, The shape calculated
  • the thickness of the first electrode layer 12 may be, for example, in the range of about 0.1 ⁇ m to 1 ⁇ m.
  • the material used for the n-type semiconductor layer 14 is not particularly limited as long as it can form a pn junction with the p-type semiconductor layer 13.
  • CdS or a compound containing Zn may be used.
  • the n-type semiconductor layer 14 may be composed of a plurality of n-type semiconductor layers.
  • FIG. 2 shows a cross-sectional view of an example solar cell 10a when the n-type semiconductor layer 14 is composed of n-type semiconductor layers 14a and 14b.
  • the n-type semiconductor layer 14a may be formed of CdS, Zn (O, S), ZnMgO, or the like.
  • the n-type semiconductor layer 14b can be formed using a material different from that of the n-type semiconductor layer 14a.
  • the n-type semiconductor layer 14b may be formed using ZnO or a material containing ZnO.
  • the thickness of the n-type semiconductor layer 14a may be in the range of 5 nm to 200 nm, for example, and the thickness of the n-type semiconductor layer 14b may be in the range of 50 nm to 200 nm, for example.
  • the n-type semiconductor layer 14b can be omitted.
  • the second electrode layer 15 on the light incident side can be formed of, for example, a light-transmitting conductive material.
  • the “translucency” may be any translucency with respect to light that contributes to power generation of the solar cell 10.
  • a layer made of indium tin oxide (ITO), a layer made of ZnO doped with ZnO or a group 13 element (Al, Ga, etc.), or a laminated film thereof is used as the electrode layer 15, a layer made of indium tin oxide (ITO), a layer made of ZnO doped with ZnO or a group 13 element (Al, Ga, etc.), or a laminated film thereof is used. Can be used.
  • the thickness of the second electrode layer 15 may be in the range of about 0.1 to 0.6 ⁇ m, for example.
  • the material used for the extraction electrodes 16 and 17 is not particularly limited as long as it is a material generally used for the extraction electrode of the solar cell.
  • NiCr, Ag, Au, Al, etc. may be used.
  • the first electrode layer 12, the p-type semiconductor layer 13, the n-type semiconductor layer 14, and the second electrode layer 15 are disposed on the substrate 11.
  • the substrate 11 is not necessarily required and can be omitted as necessary.
  • the extraction electrodes 16 and 17 can be omitted as necessary.
  • the layers other than the p-type semiconductor layer 13 can be manufactured by a technique generally used for manufacturing solar cells.
  • a sputtering method or a vapor deposition method can be used.
  • a sputtering method may be used in order to form the n-type semiconductor layer 14 (for example, the n-type semiconductor layers 14a and 14b) on the p-type semiconductor layer 13, for example.
  • a sputtering method may be used to form the second electrode layer 15.
  • the method of forming the extraction electrodes 16 and 17 is not particularly limited as long as each extraction electrode can be electrically connected to each electrode layer, and a general method may be used.
  • an evaporation method for the formation of the p-type semiconductor layer 13 on the first electrode layer 12, for example, an evaporation method, more specifically, a multi-source evaporation method may be used.
  • the multi-source evaporation method is an evaporation method using a plurality of evaporation sources.
  • a Cu vapor deposition source for example, in an example of forming the p-type semiconductor layer 13 made of Cu (In, Ga) Se 2 , four types of vapor deposition sources of a Cu vapor deposition source, an In vapor deposition source, a Ga vapor deposition source, and a Se vapor deposition source are used. May be used.
  • the p-type semiconductor layer in which the atomic ratio of Ga is changed in the film thickness direction by controlling the energy applied to the Ga vapor deposition source and controlling the thermal diffusion speed of Ga atoms with respect to other atoms. 13 can be formed. Further, a Ga layer is formed in advance on the first electrode layer 12 by a sputtering method, a vapor deposition method, or the like, and a Cu (In, Ga) Se 2 layer is further formed on the Ga layer.
  • the p-type semiconductor layer 13 in which the Ga atom number ratio is changed in the film thickness direction can also be formed by the method of diffusing.
  • the p-type semiconductor layer 13 in which the atomic ratio of Al or In is changed in the film thickness direction is formed, a similar method (a method in which a part of Ga in the above method is replaced with Al or In) may be used.
  • the method for forming the p-type semiconductor layer 13 is not limited to the above example, and any method that can realize the configuration of the p-type semiconductor layer 13 described above may be used.
  • Example 1 In Example 1, a simulation was performed on the relationship between the Ga concentration in the film thickness direction of the p-type semiconductor layer 13 made of Cu (In, Ga) Se 2 and the conversion efficiency.
  • a solar cell 10a shown in FIG. 2 was used as a model of the solar cell. More specifically, simulation was performed under the conditions shown in Table 1.
  • the band profile of the p-type semiconductor layer 13 was controlled by changing the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 made of Cu (In, Ga) Se 2 .
  • the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side is referred to as “G1”
  • the Ga / (Ga + In) ratio on the main surface on the first electrode layer 12 side is referred to as “G1”. It may be referred to as “G2”.
  • FIG. 3 shows a Ga concentration profile for which the simulation used in Example 1 was performed.
  • the Ga / (Ga + In) ratio at the midpoint of the p-type semiconductor layer 13 was fixed at 0.36, and G2 was fixed at 0.45. Further, G1 was changed in the range of 0.17 to 0.41. Then, the conversion efficiency was calculated under the condition that the Ga / (Ga + In) ratio varies linearly between the n-type semiconductor layer 14 and the intermediate point and between the intermediate point and the first electrode layer 12.
  • G1 is 0.27
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 changes linearly between the n-type semiconductor layer 14 and the first electrode layer 12.
  • Ga / (Ga + In) ratio is constant (0.36) from the midpoint to the n-type semiconductor layer 14.
  • Ga / (Ga + In) ratio changes linearly means a change rate of Ga / (Ga + In) ratio in the film thickness direction (straight line representing Ga / (Ga + In) ratio). Means constant.
  • the simulation results are shown in FIG.
  • the conversion efficiency was highest when the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increased linearly from the n-type semiconductor layer 14 side toward the first electrode layer 12 side.
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increases linearly and monotonically from the main surface on the n-type semiconductor layer 14 side to the main surface on the first electrode layer 12 side, the conversion efficiency was the highest.
  • the Ga / (Ga + In) ratio increases almost linearly from the n-type semiconductor layer 14 side to the first electrode layer 12 side, high conversion efficiency is achieved even if it is not linear. .
  • Example 2 In Example 2, a simulation was performed for a case where the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 linearly changed in the film thickness direction.
  • G2 which is the Ga / (Ga + In) ratio in the main surface on the first electrode layer 12 side was fixed to 0.45.
  • G1 which is the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side was changed in the range of 0 to 0.45.
  • FIG. 5 shows a Ga / (Ga + In) ratio profile when G1 is 0, 0.27, and 0.45.
  • Table 1 the physical properties shown in Table 1 were assumed for the p-type semiconductor layer 13, the n-type semiconductor layer 14a, the n-type semiconductor layer 14b, and the second electrode layer 15 as in Example 1.
  • Example 3 In order to verify the simulation result of Example 1, two solar cells having different Ga / (Ga + In) ratio profiles in the p-type semiconductor layer 13 were produced and evaluated.
  • a 1.1 mm thick soda lime glass substrate was prepared as a substrate.
  • the soda lime glass substrate was cleaned with a detergent and then rinsed with pure water to clean the substrate.
  • an Mo film (first electrode layer 12) having a thickness of 800 nm was formed on the soda-lime glass substrate.
  • the Mo film was formed by a direct current sputtering method (DC sputtering method) using Mo as a target in Ar gas. The pressure during sputtering was 0.3 Pa.
  • a Cu (In, Ga) Se 2 layer (p-type semiconductor layer 13) was formed on the Mo film.
  • the Cu (In, Ga) Se 2 layer was formed by a vapor deposition apparatus provided with four Knudsen cells each containing one kind of Cu, In, Ga, and Se.
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 can be changed in the film thickness direction by changing the temperature of the Ga cells in the first and third stages. For example, by lowering the temperature of the third-stage Ga cell than the temperature of the first-stage Ga cell, the Ga / (Ga + In) ratio in the main surface on the first electrode layer 12 side is increased, and the n-type semiconductor layer 14 An inclined structure having a small Ga / (Ga + In) ratio in the main surface on the side can be formed.
  • Example 3 the temperature of the first stage Ga cell is fixed at 928 ° C., and the temperature of the third stage Ga cell is changed in the range of 848 to 928 ° C., so that the Ga / (Ga + In) ratio is changed to the film thickness.
  • the direction was changed. Specifically, the temperature of the Ga cell at the third stage was set to the temperature shown in Table 2 described later.
  • a CdS film (n-type semiconductor layer 14a) was formed by chemical deposition. Specifically, first, a solution containing cadmium acetate (Cd (CH 3 COO) 2 ), thiourea (NH 2 CSNH 2 ), ammonium acetate (CH 3 COONH 4 ) and ammonia was prepared. The concentration of cadmium acetate in the solution was 0.001 mol / L, the concentration of thiourea was 0.005 mol / L, the concentration of ammonium acetate was 0.01 mol / L, and the concentration of ammonia was 0.4 mol / L. The container in which this solution was put was left still in the warm water tank kept at 85 degreeC.
  • Cu (In, Ga) to form a CdS film on the Se 2 layer was placed Cu (In, Ga) a substrate Se 2 layer was formed in the solution.
  • a CdS film having a film thickness of about 100 nm was formed by the treatment for 15 minutes.
  • a ZnO film (n-type semiconductor layer 14b: film thickness 100 nm) was formed on the CdS film by a sputtering method using a ZnO target. Sputtering was performed under the conditions of an argon gas pressure of 2.66 Pa (2 ⁇ 10 ⁇ 2 Torr) and a high frequency power applied to the ZnO target of 50 W.
  • a transparent conductive film ZnO: Al (second electrode layer 15: film thickness 100 nm) was formed by a sputtering method using a ZnO: Al target. Specifically, it was formed under the conditions of an argon gas pressure of 1.064 Pa (8 ⁇ 10 ⁇ 3 Torr) and a high frequency power of 50 W. Thereafter, an extraction electrode made of an Al film was formed by thermal evaporation. In this manner, a plurality of solar cells were produced by changing the temperature of the third stage Ga cell.
  • the p-type semiconductor layer 13 thus produced was subjected to SIMS analysis (Secondary / Ion / Mass / Spectrometry, secondary ion mass spectrometry).
  • SIMS analysis Secondary / Ion / Mass / Spectrometry, secondary ion mass spectrometry.
  • the measurement result of the Ga / (Ga + In) ratio when the temperature of the third-stage Ga cell is 908 ° C. is shown by the dotted line (a) in FIG.
  • the measurement result of the Ga / (Ga + In) ratio when the temperature of the third stage Ga cell is 888 ° C. is shown in FIG.
  • the inclined structure see FIG. 3) simulated in Example 1 was formed.
  • the Ga / (Ga + In) ratio increases almost linearly from the n-type semiconductor layer 14 side to the first electrode layer 12 side. .
  • Table 2 shows the relationship between the temperature of the Ga cell at the third stage and the measured value of the Ga / (Ga + In) ratio (that is, the value of G1) on the main surface on the n-type semiconductor layer 14 side.
  • the conversion efficiency was measured by irradiating the solar cell manufactured by the above-described method with artificial sunlight of AM (Air Mass) 1.5 and 100 mW / cm 2 .
  • the measurement results are shown in FIG.
  • the measurement results in FIG. 8 correspond to the experimental results of the Ga / (Ga + In) ratio profile (see FIG. 3) assumed in the simulation of Example 1.
  • the conversion efficiency peaked when the value of G1 was 0.27. This result coincided with the simulation result of Example 1 (see FIG. 4).
  • These results show that a high conversion efficiency is achieved by increasing the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 linearly from the n-type semiconductor layer 14 side toward the first electrode layer 12 side. It is shown that.
  • Example 4 In Example 4, a simulation is performed by changing the Ga / (Ga + In) ratio on the main surface on the n-type semiconductor layer 14 side and the Ga / (Ga + In) ratio on the main surface on the first electrode layer 12 side, thereby converting the conversion efficiency. was calculated.
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 was changed linearly in the film thickness direction.
  • the physical properties shown in Table 3 below were assumed for the p-type semiconductor layer 13, the n-type semiconductor layer 14a, the n-type semiconductor layer 14b, and the second electrode layer 15.
  • Example 4 the Ga / (Ga + In) ratio (that is, the value of G1) on the main surface on the n-type semiconductor layer 14 side is changed in the range of 0.150 to 0.400, and the main electrode on the first electrode layer 12 side is changed.
  • the Ga / (Ga + In) ratio (that is, the value of G2) on the surface was changed in the range of 0.250 to 0.667.
  • the film thickness of the p-type semiconductor layer 13 was changed in the range of 0.5 to 0.7 ⁇ m.
  • Table 4 shows the set values of G1 and G2 and the slope of the Ga / (Ga + In) ratio at that time.
  • the conversion efficiency was maximized when the value of G1 was 0.275 and the value of G2 was 0.458. Further, as shown in Table 10, it was found that when the thickness of the p-type semiconductor layer 13 is in the range of 0.5 to 0.7 ⁇ m, high conversion efficiency is achieved by satisfying the following conditions. (1)
  • the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increases from the n-type semiconductor layer 14 side toward the first electrode layer 12 side. Specifically, the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increases monotonously and linearly from the main surface on the n-type semiconductor layer 14 side to the main surface on the first electrode layer 12 side.
  • the value of G1 is in the range of 0.225 to 0.325 (for example, a range greater than 0.225 and less than 0.325).
  • the value of G2 is in the range of 0.375 to 0.542 (for example, a range of greater than 0.375 and less than 0.542).
  • the conversion efficiency was particularly high when the following requirement was satisfied.
  • the value of G1 is in the range of 0.250 to 0.300.
  • the value of G2 is in the range of 0.417 to 0.500.
  • the slope of the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 is in the range of 0.214 to 0.434 ⁇ m ⁇ 1 .
  • the slope of the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 is in the range of 0.239 to 0.400 ⁇ m ⁇ 1 .
  • the conversion efficiency was simulated by setting the thickness of the p-type semiconductor layer 13 to 1.8 ⁇ m, which is a typical thickness of the light absorption layer of the CIGS solar cell.
  • the simulation was performed under the same conditions as the simulation of Example 4 except for the film thickness of the p-type semiconductor layer 13.
  • the calculation results are shown in FIG. Unlike the case where the thickness of the p-type semiconductor layer 13 is 0.5 to 0.7 ⁇ m, the conversion efficiency is maximized when the value of G1 is 0.325 and the value of G2 is 0.542.
  • FIGS. 10 and 11 show that when a compound semiconductor layer containing a group 11 element, a group 13 element, and a group 16 element is used as the light absorption layer, the thickness is made thinner than a general thickness, and thus the light absorption layer. It shows that the optimum value of the distribution of the Ga / (Ga + In) ratio changes. Based on this new knowledge, the present embodiment determines the Ga / (Ga + In) ratio profile of the light absorption layer so that high conversion efficiency can be obtained when the light absorption layer is thin.
  • the present invention can be used for solar cells. According to the present invention, a relatively high conversion efficiency can be achieved even with a thin light absorption layer, and as a result, cost reduction of the solar cell can be achieved.
  • the solar cell of the present invention is useful as an energy source for general households, factories, solar power generation facilities, automobiles, bicycles, portable terminals, portable computers and the like.

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Abstract

This solar cell (10) includes a first electrode layer (12), a second electrode layer (15), a p-type semiconductor layer (13) disposed between the electrode layers, and an n-type semiconductor layer (14) disposed between the p-type semiconductor layer (13) and the second electrode layer (15). The p-type semiconductor layer (13) includes a group 11 element, a group 13 element, and a group 16 element, and comprises a compound semiconductor having a chalcopyrite structure. The p-type semiconductor layer (13) includes In and Ga as group 13 elements. The thickness of the p-type semiconductor layer (13) is in the range of 0.5-0.7 µm. The Ga/(Ga+In) ratio in the p-type semiconductor layer (13) increases toward the electrode layer (12) from the n-type semiconductor layer (14). The Ga/(Ga+In) ratio in the principal surface of the n-type semiconductor layer (14) is in the range of 0.225-0.325. The Ga/(Ga+In) ratio in the principal surface of the electrode layer (12) is in the range of 0.375-0.542.

Description

太陽電池Solar cell
　本発明は、太陽電池に関し、より具体的には、光吸収層に化合物半導体層を用いた太陽電池に関する。 The present invention relates to a solar cell, and more specifically to a solar cell using a compound semiconductor layer as a light absorption layer.
　Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2などのカルコパイライト構造を有する化合物半導体を光吸収層に用いた薄膜太陽電池が従来から知られている。以下では、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2およびそのＳｅの少なくとも一部をＳ（硫黄）で置き換えたものを総称して「ＣＩＧＳ」という場合がある。 A thin film solar cell using a compound semiconductor having a chalcopyrite structure such as Cu (In, Ga) Se 2 as a light absorption layer has been conventionally known. Hereinafter, Cu (In, Ga) Se 2 and at least a part of Se thereof are replaced by S (sulfur) may be collectively referred to as “CIGS”.
　光吸収層であるＣＩＧＳ層のバンドギャップは、ＩｎとＧａとの比を変えることによって変化させることができる。ＣｕＩｎＳｅ2のバンドギャップは１．０２ｅＶであり、ＣｕＧａＳｅ2のバンドギャップは１．６９ｅＶである。そのため、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2のバンドギャップは、ＩｎとＧａとの比を変えることによって、１．０２～１．６９ｅＶの範囲内で変化させることができる。 The band gap of the CIGS layer which is a light absorption layer can be changed by changing the ratio of In and Ga. The band gap of CuInSe 2 is 1.02 eV, and the band gap of CuGaSe 2 is 1.69 eV. Therefore, the band gap of Cu (In, Ga) Se 2 can be changed within the range of 1.02 to 1.69 eV by changing the ratio of In to Ga.
　ＣＩＧＳを光吸収層に用いたＣＩＧＳ太陽電池において、従来から、光吸収層におけるＧａ濃度に勾配をもたせる方法が提案されている（特許文献１および２参照）。Ｇａ濃度に勾配をもたせることによって変換効率を向上できることが、特許文献２の段落［００１０］に記載されている。 In a CIGS solar cell using CIGS as a light absorption layer, a method of providing a gradient in the Ga concentration in the light absorption layer has been conventionally proposed (see Patent Documents 1 and 2). It is described in paragraph [0010] of Patent Document 2 that the conversion efficiency can be improved by providing a gradient in the Ga concentration.
特開平１０－１３５４９５号公報JP-A-10-135495 特開２０１０－２２５８２９号公報JP 2010-225829 A
　現在、太陽電池では、低コスト化が重要な課題となっている。しかし、ＣＩＧＳ太陽電池にはＩｎやＧａといった希少金属が用いられており、低コスト化を妨げている。コストを下げるためには、ＩｎおよびＧａの使用量を少なくする必要があるが、光吸収層であるＣＩＧＳ層を薄くすると変換効率が大きく低下する。 Currently, cost reduction is an important issue for solar cells. However, rare metals such as In and Ga are used for CIGS solar cells, which hinders cost reduction. In order to reduce the cost, it is necessary to reduce the amount of In and Ga used. However, if the CIGS layer as the light absorption layer is thinned, the conversion efficiency is greatly reduced.
　このような状況において、本発明の目的の１つは、変換効率を大きく低下させることなく低コスト化が可能な太陽電池を提供することである。 In such a situation, one of the objects of the present invention is to provide a solar cell capable of reducing the cost without greatly reducing the conversion efficiency.
　上記目的を達成するために、本発明の一態様は、第１の電極層と、第２の電極層と、前記第１の電極層と前記第２の電極層との間に配置されたｐ形半導体層と、前記ｐ形半導体層と前記第２の電極層との間に配置されたｎ形半導体層とを含む太陽電池であって、前記ｐ形半導体層は、１１族元素、１３族元素および１６族元素を含み、且つ、カルコパイライト構造を有する化合物半導体からなり、前記ｐ形半導体層は、前記１３族元素としてＩｎおよびＧａを含み、前記ｐ形半導体層の厚さが０．５～０．７μｍの範囲にあり、前記ｐ形半導体層における（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が、前記ｎ形半導体層側から前記第１の電極層側に向かって増加しており、前記ｎ形半導体層側の主面における前記ｐ形半導体層の（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が０．２２５～０．３２５の範囲にあり、前記第１の電極層側の主面における前記ｐ形半導体層の（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が０．３７５～０．５４２の範囲にある。 In order to achieve the above object, one embodiment of the present invention includes a first electrode layer, a second electrode layer, and a p disposed between the first electrode layer and the second electrode layer. A solar cell including a p-type semiconductor layer and an n-type semiconductor layer disposed between the p-type semiconductor layer and the second electrode layer, wherein the p-type semiconductor layer comprises a group 11 element, a group 13 And a p-type semiconductor layer containing In and Ga as the group 13 element, and the thickness of the p-type semiconductor layer is 0.5. The value of ((the number of Ga atoms) / (the number of Ga atoms + the number of In atoms)) in the p-type semiconductor layer is in the range of .about.0.7 μm from the n-type semiconductor layer side to the first electrode. The p-type half of the main surface on the n-type semiconductor layer side increases toward the layer side. The value of ((number of Ga atoms) / (number of Ga atoms + In atoms)) of the body layer is in the range of 0.225 to 0.325, and the p on the main surface on the first electrode layer side The value of ((the number of Ga atoms) / (the number of Ga atoms + the number of In atoms)) of the large semiconductor layer is in the range of 0.375 to 0.542.
　本発明によれば、変換効率を大きく低下させることなく低コスト化が可能な太陽電池が得られる。 According to the present invention, a solar cell capable of reducing the cost without greatly reducing the conversion efficiency can be obtained.
本実施形態の太陽電池の一例を模式的に示す断面図である。It is sectional drawing which shows typically an example of the solar cell of this embodiment. 本実施形態の太陽電池の他の一例を模式的に示す断面図である。It is sectional drawing which shows typically another example of the solar cell of this embodiment. 実施例１のシミュレーションで仮定した、ｐ形半導体層におけるＧａ／（Ｇａ＋Ｉｎ）比のプロファイルを示す図である。6 is a diagram showing a profile of a Ga / (Ga + In) ratio in a p-type semiconductor layer assumed in the simulation of Example 1. FIG. 実施例１のシミュレーション結果を示す図である。It is a figure which shows the simulation result of Example 1. FIG. 実施例２のシミュレーションで仮定した、ｐ形半導体層におけるＧａ／（Ｇａ＋Ｉｎ）比のプロファイルの例を示す図である。10 is a diagram illustrating an example of a profile of a Ga / (Ga + In) ratio in a p-type semiconductor layer assumed in a simulation of Example 2. FIG. 実施例２のシミュレーション結果を示す図である。It is a figure which shows the simulation result of Example 2. FIG. 実施例３で作製したｐ形半導体層におけるＧａ／（Ｇａ＋Ｉｎ）比の測定値を示す図である。6 is a diagram showing measured values of a Ga / (Ga + In) ratio in a p-type semiconductor layer produced in Example 3. FIG. 実施例３で作製した太陽電池について、ｎ形半導体層側の主面におけるｐ形半導体層のＧａ／（Ｇａ＋Ｉｎ）比と変換効率との関係を示す図である。It is a figure which shows the relationship between Ga / (Ga + In) ratio of the p-type semiconductor layer in the main surface by the side of an n-type semiconductor layer, and conversion efficiency about the solar cell produced in Example 3. FIG. 実施例４のシミュレーションで仮定した、ｐ形半導体層におけるＧａ／（Ｇａ＋Ｉｎ）比のプロファイルの例を示す図である。10 is a diagram illustrating an example of a profile of a Ga / (Ga + In) ratio in a p-type semiconductor layer assumed in the simulation of Example 4. FIG. ２つの主面におけるｐ形半導体層のＧａ／（Ｇａ＋Ｉｎ）比と、変換効率との関係を示す図である。It is a figure which shows the relationship between Ga / (Ga + In) ratio of the p-type semiconductor layer in two main surfaces, and conversion efficiency. ｐ形半導体層を厚くしたときの、２つの主面におけるｐ形半導体層のＧａ／（Ｇａ＋Ｉｎ）比と、変換効率との関係を示す図である。It is a figure which shows the relationship between the Ga / (Ga + In) ratio of the p-type semiconductor layer in two main surfaces, and conversion efficiency when a p-type semiconductor layer is thickened.
　以下では、本発明の実施形態について例を挙げて説明するが、本発明は以下で説明する例に限定されない。 Hereinafter, embodiments of the present invention will be described by way of examples, but the present invention is not limited to the examples described below.
　本実施形態の太陽電池は、第１の電極層と、第２の電極層と、第１の電極層と第２の電極層との間に配置されたｐ形半導体層と、ｐ形半導体層と第２の電極層との間に配置されたｎ形半導体層とを含む。ｐ形半導体層は、１１族元素、１３族元素および１６族元素を含み、且つ、カルコパイライト構造を有する化合物半導体からなる。ｐ形半導体層は、１３族元素としてＩｎおよびＧａを含む。また、ｐ形半導体層の厚さは０．５～０．７μｍの範囲にある。 The solar cell of the present embodiment includes a first electrode layer, a second electrode layer, a p-type semiconductor layer disposed between the first electrode layer and the second electrode layer, and a p-type semiconductor layer. And an n-type semiconductor layer disposed between the first electrode layer and the second electrode layer. The p-type semiconductor layer is made of a compound semiconductor containing a group 11 element, a group 13 element, and a group 16 element and having a chalcopyrite structure. The p-type semiconductor layer contains In and Ga as group 13 elements. The thickness of the p-type semiconductor layer is in the range of 0.5 to 0.7 μm.
　ｐ形半導体層は、光吸収層として機能する層である。本実施形態の太陽電池では、ｐ形半導体層における（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が、膜厚方向に変化している。ｐ形半導体層における（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値を、以下では、「Ｇａ／（Ｇａ＋Ｉｎ）比」という場合がある。 The p-type semiconductor layer is a layer that functions as a light absorption layer. In the solar cell of the present embodiment, the value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) in the p-type semiconductor layer changes in the film thickness direction. The value of ((Ga atom number) / (Ga atom number + In atom number)) in the p-type semiconductor layer may be hereinafter referred to as “Ga / (Ga + In) ratio”.
　ｐ形半導体層（光吸収層）におけるＧａ／（Ｇａ＋Ｉｎ）比は、以下の３つの要件を満たす。
（１）ｐ形半導体層におけるＧａ／（Ｇａ＋Ｉｎ）比が、ｎ形半導体層側から第１の電極層側に向かって増加している。
（２）ｎ形半導体層側の主面におけるｐ形半導体層のＧａ／（Ｇａ＋Ｉｎ）比が、０．２２５～０．３２５の範囲にある。このＧａ／（Ｇａ＋Ｉｎ）比は、０．２２５より大きく、０．３２５未満であってもよい。
（３）第１の電極層側の主面におけるｐ形半導体層のＧａ／（Ｇａ＋Ｉｎ）比が、０．３７５～０．５４２の範囲にある。このＧａ／（Ｇａ＋Ｉｎ）比は、０．３７５より大きく、０．５４２未満であってもよい。 The Ga / (Ga + In) ratio in the p-type semiconductor layer (light absorption layer) satisfies the following three requirements.
(1) The Ga / (Ga + In) ratio in the p-type semiconductor layer increases from the n-type semiconductor layer side toward the first electrode layer side.
(2) The Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the n-type semiconductor layer side is in the range of 0.225 to 0.325. This Ga / (Ga + In) ratio may be greater than 0.225 and less than 0.325.
(3) The Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the first electrode layer side is in the range of 0.375 to 0.542. This Ga / (Ga + In) ratio may be greater than 0.375 and less than 0.542.
　ｐ形半導体層におけるＧａ／（Ｇａ＋Ｉｎ）比は、ｎ形半導体層側から第１の電極層側に向かって連続的に増加していることが好ましい。たとえば、この比は、ｎ形半導体層側から第１の電極層側に向かって、実質的に直線的に増加していることが好ましい。 It is preferable that the Ga / (Ga + In) ratio in the p-type semiconductor layer continuously increases from the n-type semiconductor layer side toward the first electrode layer side. For example, this ratio preferably increases substantially linearly from the n-type semiconductor layer side toward the first electrode layer side.
　上記要件を満たすことによって、本実施形態の太陽電池では、ｐ形半導体層が薄くても比較的高い変換効率を達成できる。そのため、本実施形態の太陽電池によれば、高い変換効率と低いコストとを両立させることができる。 By satisfying the above requirements, the solar cell of this embodiment can achieve relatively high conversion efficiency even if the p-type semiconductor layer is thin. Therefore, according to the solar cell of this embodiment, it is possible to achieve both high conversion efficiency and low cost.
　なお、ｐ形半導体層以外の部分の構成に特に限定はなく、ＣＩＧＳ太陽電池で用いられる公知の構成を適用してもよい。 In addition, there is no limitation in particular in the structure of parts other than a p-type semiconductor layer, You may apply the well-known structure used with a CIGS solar cell.
　ｐ形半導体層（光吸収層）におけるＧａ／（Ｇａ＋Ｉｎ）比は、さらに以下の２つの要件を満たしてもよい。以下の（４）および（５）の範囲は、上記（２）および（３）の範囲をより狭くしたものである。
（４）ｎ形半導体層側の主面におけるｐ形半導体層のＧａ／（Ｇａ＋Ｉｎ）比が、０．２５０～０．３００の範囲にある。
（５）第１の電極層側の主面におけるｐ形半導体層のＧａ／（Ｇａ＋Ｉｎ）比が、０．４１７～０．５００の範囲にある。 The Ga / (Ga + In) ratio in the p-type semiconductor layer (light absorption layer) may further satisfy the following two requirements. The following ranges (4) and (5) are obtained by narrowing the above ranges (2) and (3).
(4) The Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the n-type semiconductor layer side is in the range of 0.250 to 0.300.
(5) The Ga / (Ga + In) ratio of the p-type semiconductor layer on the main surface on the first electrode layer side is in the range of 0.417 to 0.500.
　ｐ形半導体層（光吸収層）を構成する１１族元素はＣｕを含んでもよく、たとえばＣｕであってもよい。また、ｐ形半導体層を構成する１６族元素はＳｅおよびＳから選ばれる少なくとも１つの元素であってもよい。この場合のｐ形半導体層の例には、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2やＣｕ（Ｉｎ，Ｇａ）（Ｓｅ，Ｓ）2で表されるＣＩＧＳ層が含まれる。 The group 11 element constituting the p-type semiconductor layer (light absorption layer) may contain Cu, for example, Cu. The group 16 element constituting the p-type semiconductor layer may be at least one element selected from Se and S. Examples of the p-type semiconductor layer in this case include a CIGS layer represented by Cu (In, Ga) Se 2 or Cu (In, Ga) (Se, S) 2 .
　ｐ形半導体層における（（Ｇａの原子数）／（１３族元素の原子数））の値は、ｎ形半導体層側から第１の電極層側に向かって増加していてもよい。好ましい例では、当該値が、ｎ形半導体層側から第１の電極層側に向かって連続的または直線的に増加している。ＩｎおよびＧａ以外の１３族元素の例には、Ａｌが含まれる。 The value of ((number of Ga atoms) / (number of group 13 element atoms)) in the p-type semiconductor layer may increase from the n-type semiconductor layer side toward the first electrode layer side. In a preferred example, the value increases continuously or linearly from the n-type semiconductor layer side toward the first electrode layer side. Examples of group 13 elements other than In and Ga include Al.
　以下、図面を参照しながら本実施形態の例について説明する。なお、図面を用いた説明において、同様の部材には同一の符号を付して重複する説明を省略する場合がある。 Hereinafter, an example of this embodiment will be described with reference to the drawings. In the description with reference to the drawings, the same members may be denoted by the same reference numerals, and redundant descriptions may be omitted.
　（本実施形態の太陽電池の一例）
　本実施形態の太陽電池の一例の断面図を図１に示す。なお、以下では、第２の電極層側から入射する光によって発電する太陽電池について説明するが、本実施形態の太陽電池はこれに限定されない。 (Example of solar cell of this embodiment)
A cross-sectional view of an example of the solar cell of the present embodiment is shown in FIG. In the following, a solar cell that generates power using light incident from the second electrode layer side will be described, but the solar cell of the present embodiment is not limited to this.
　図１に示す太陽電池１０は、基板１１、第１の電極層１２、第２の電極層１５、第１の電極層１２と第２の電極層１５との間に配置されたｐ形半導体層１３、第２の電極層１５とｐ形半導体層１３との間に配置されたｎ形半導体層１４、ならびに、取り出し電極１６および１７を含む。第１の電極層１２、ｐ形半導体層１３、ｎ形半導体層１４、および第２の電極層１５は、基板１１上にこの順に積層されている。 A solar cell 10 shown in FIG. 1 includes a substrate 11, a first electrode layer 12, a second electrode layer 15, and a p-type semiconductor layer disposed between the first electrode layer 12 and the second electrode layer 15. 13, an n-type semiconductor layer 14 disposed between the second electrode layer 15 and the p-type semiconductor layer 13, and extraction electrodes 16 and 17. The first electrode layer 12, the p-type semiconductor layer 13, the n-type semiconductor layer 14, and the second electrode layer 15 are stacked on the substrate 11 in this order.
　ｎ形半導体層１４は、光吸収層であるｐ形半導体層１３とｐ－ｎ接合を形成できる半導体層である。ｎ形半導体層１４は、通常、窓層として機能する。 The n-type semiconductor layer 14 is a semiconductor layer that can form a pn junction with the p-type semiconductor layer 13 that is a light absorption layer. The n-type semiconductor layer 14 usually functions as a window layer.
　ｐ形半導体層１３は光吸収層として機能する。太陽電池１０では、第２の電極層１５側から入射する光によって光起電力が発生する。発生した光起電力は、第１の電極層１２に電気的に接続された取り出し電極１６と、第２の電極層１５に電気的に接続された取り出し電極１７とを介して外部に伝達することができる。 The p-type semiconductor layer 13 functions as a light absorption layer. In the solar cell 10, photovoltaic power is generated by light incident from the second electrode layer 15 side. The generated photovoltaic power is transmitted to the outside through the extraction electrode 16 electrically connected to the first electrode layer 12 and the extraction electrode 17 electrically connected to the second electrode layer 15. Can do.
　ｐ形半導体層１３は、第１の電極層１２の上方（光入射側）に配置されている。ｐ形半導体層１３は、１１族元素、１３族元素であるＩｎおよびＧａ、ならびに１６族元素を含み、且つ、カルコパイライト（ｃｈａｌｃｏｐｙｒｉｔｅ）と同様の結晶構造（カルコパイライト構造）を有する化合物半導体からなる。なお、本明細書における元素の族表示は、ＩＵＰＡＣ（１９８９）の規定に基づいている。ＩＵＰＡＣ（１９７０）の規定に基づけば、上記１１族元素はIb族に、上記１３族元素はIIIb族に、上記１６族元素はVIb族に該当する。 The p-type semiconductor layer 13 is disposed above the first electrode layer 12 (on the light incident side). The p-type semiconductor layer 13 includes a group 11 element, a group 13 element, In and Ga, and a group 16 element, and is made of a compound semiconductor having a crystal structure (chalcopyrite structure) similar to chalcopyrite. . The element group designation in this specification is based on the provisions of IUPAC (1989). Based on the provisions of IUPAC (1970), the Group 11 element corresponds to Group Ib, the Group 13 element corresponds to Group IIIb, and the Group 16 element corresponds to Group VIb.
　１１族元素には、たとえばＣｕ（銅）を用いることができる。１６族元素には、たとえば、Ｓｅ（セレン）およびＳ（硫黄）から選ばれる少なくとも１つの元素を用いることができる。好ましい一例では、１１族元素がＣｕであり、１３族元素がＩｎおよびＧａであり、１６族元素がＳｅおよびＳから選ばれる少なくとも１つの元素である。具体的には、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2やＣｕ（Ｉｎ，Ｇａ）（Ｓｅ，Ｓ）2などを用いてｐ形半導体層１３を形成できる。ｐ形半導体層１３の厚さは、０．５μｍ～０．７μｍの範囲にある。 For example, Cu (copper) can be used as the group 11 element. As the group 16 element, for example, at least one element selected from Se (selenium) and S (sulfur) can be used. In a preferred example, the group 11 element is Cu, the group 13 element is In and Ga, and the group 16 element is at least one element selected from Se and S. Specifically, the p-type semiconductor layer 13 can be formed using Cu (In, Ga) Se 2 , Cu (In, Ga) (Se, S) 2, or the like. The thickness of the p-type semiconductor layer 13 is in the range of 0.5 μm to 0.7 μm.
　ｐ形半導体層１３において、（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値（すなわち、Ｇａ／（Ｇａ＋Ｉｎ）比）が、ｎ形半導体層１４側から第１の電極層１２側に向かって増加している。換言すれば、ｐ形半導体層１３のバンドギャップは、ｎ形半導体層１４側から第１の電極層１２側に向かって増加している。好ましい一例では、Ｇａ／（Ｇａ＋Ｉｎ）比（別の観点では、バンドギャップ）は、ｎ形半導体層１４側から第１の電極層１２側に向かって直線的に増加している。 In the p-type semiconductor layer 13, the value of ((number of Ga atoms) / (number of Ga atoms + In number of atoms)) (that is, Ga / (Ga + In) ratio) is the first value from the n-type semiconductor layer 14 side. It increases toward the electrode layer 12 side. In other words, the band gap of the p-type semiconductor layer 13 increases from the n-type semiconductor layer 14 side toward the first electrode layer 12 side. In a preferred example, the Ga / (Ga + In) ratio (in another aspect, the band gap) increases linearly from the n-type semiconductor layer 14 side toward the first electrode layer 12 side.
　また、ｎ形半導体層１４側の主面におけるｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比は、０．２２５～０．３２５の範囲にある。また、第１の電極層１２側の主面におけｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比は、０．３７５～０．５４２の範囲にある。なお、ｎ形半導体層１４側の主面とは、ｐ形半導体層１３の２つの主面のうちｎ形半導体層１４側の主面を意味する。また、第１の電極層１２側の主面とは、ｐ形半導体層１３の２つの主面のうち第１の電極層１２側の主面を意味する。 The Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side is in the range of 0.225 to 0.325. The Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the first electrode layer 12 side is in the range of 0.375 to 0.542. The main surface on the n-type semiconductor layer 14 side means the main surface on the n-type semiconductor layer 14 side of the two main surfaces of the p-type semiconductor layer 13. The main surface on the first electrode layer 12 side means the main surface on the first electrode layer 12 side among the two main surfaces of the p-type semiconductor layer 13.
　上記構成を有する太陽電池１０によれば、光吸収層の厚さが０．５μｍ～０．７μｍと薄い場合でも、高い変換効率を達成できる。 According to the solar cell 10 having the above configuration, high conversion efficiency can be achieved even when the light absorption layer is as thin as 0.5 μm to 0.7 μm.
　好ましい一例では、ｎ形半導体層１４側の主面におけるｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比が０．２５０～０．３００の範囲にあり、且つ、第１の電極層１２側の主面におけるｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比が０．４１７～０．５００の範囲にある。 In a preferred example, the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side is in the range of 0.250 to 0.300, and the main surface on the first electrode layer 12 side is. The Ga / (Ga + In) ratio of the p-type semiconductor layer 13 in the plane is in the range of 0.417 to 0.500.
　図１に示す太陽電池１０では、第１の電極層１２、ｐ形半導体層１３およびｎ形半導体層１４が隣接して配置されている。このような太陽電池１０では、ｐ形半導体層１３のうちｎ形半導体層１４に隣接している部分のＧａ／（Ｇａ＋Ｉｎ）比が０．２２５～０．３２５の範囲にあり、ｐ形半導体層１３のうち第１の電極層１２に隣接している部分のＧａ／（Ｇａ＋Ｉｎ）比が０．３７５～０．５４２の範囲にある、ということも可能である。　 In the solar cell 10 shown in FIG. 1, the first electrode layer 12, the p-type semiconductor layer 13, and the n-type semiconductor layer 14 are disposed adjacent to each other. In such a solar cell 10, the portion of the p-type semiconductor layer 13 adjacent to the n-type semiconductor layer 14 has a Ga / (Ga + In) ratio in the range of 0.225 to 0.325, and the p-type semiconductor layer The Ga / (Ga + In) ratio of the portion adjacent to the first electrode layer 12 in 13 is in the range of 0.375 to 0.542. *
　同様に、太陽電池１０における好ましい一例では、ｐ形半導体層１３のうちｎ形半導体層１４に隣接している部分のＧａ／（Ｇａ＋Ｉｎ）比が０．２５０～０．３００の範囲にあり、ｐ形半導体層１３のうち第１の電極層１２に隣接している部分のＧａ／（Ｇａ＋Ｉｎ）比が０．４１７～０．５００の範囲にある、ということも可能である。 Similarly, in a preferred example of the solar cell 10, the Ga / (Ga + In) ratio of the portion adjacent to the n-type semiconductor layer 14 in the p-type semiconductor layer 13 is in the range of 0.250 to 0.300, and p It can also be said that the Ga / (Ga + In) ratio of the portion adjacent to the first electrode layer 12 in the large semiconductor layer 13 is in the range of 0.417 to 0.500.
　上述したＧａ／（Ｇａ＋Ｉｎ）比は、ｐ形半導体層１３の組成を、その膜厚方向に変化させることによって実現できる。より具体的には、ｐ形半導体層１３中のＧａおよびＩｎの濃度を、その膜厚方向に変化させることによって実現できる。 The Ga / (Ga + In) ratio described above can be realized by changing the composition of the p-type semiconductor layer 13 in the film thickness direction. More specifically, it can be realized by changing the Ga and In concentrations in the p-type semiconductor layer 13 in the film thickness direction.
　なお、ｐ形半導体層１３の（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値は、（（Ｇａの原子数）／（１３族元素の原子数））の値として読み替えることが可能である。Ｇａ／（Ｇａ＋Ｉｎ）比について説明したように（Ｇａの原子数）／（１３族元素の原子数）の値を変化させることによって、光吸収層の厚さが０．５μｍ～０．７μｍと薄い場合でも、高い変換効率を達成できる。 The value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) of the p-type semiconductor layer 13 is a value of ((number of Ga atoms) / (number of atoms of group 13 element)). Can be read as As described for the Ga / (Ga + In) ratio, by changing the value of (number of Ga atoms) / (number of group 13 element atoms), the thickness of the light absorption layer is as thin as 0.5 μm to 0.7 μm. Even in this case, high conversion efficiency can be achieved.
　ＩｎおよびＧａを含むｐ形半導体層１３（たとえばＣｕ（Ｉｎ，Ｇａ）Ｓｅ2）において、Ｇａ／（Ｇａ＋Ｉｎ）比が０．２２５～０．３２５の範囲にあるｐ形半導体層１３のバンドギャップは、１．１５～１．２１ｅＶの範囲にある。また、Ｇａ／（Ｇａ＋Ｉｎ）比が０．３７５～０．５４２の範囲にあるｐ形半導体層１３のバンドギャップは、１．２５～１．３６ｅＶの範囲にある。 In a p-type semiconductor layer 13 containing In and Ga (for example, Cu (In, Ga) Se 2 ), the band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.225 to 0.325 is 1.15 to 1.21 eV. The band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.375 to 0.542 is in the range of 1.25 to 1.36 eV.
　ＩｎおよびＧａを含むｐ形半導体層１３（たとえばＣｕ（Ｉｎ，Ｇａ）Ｓｅ2）において、Ｇａ／（Ｇａ＋Ｉｎ）比が０．２５０～０．３００の範囲にあるｐ形半導体層１３のバンドギャップは、１．１７～１．２０ｅＶの範囲にある。また、Ｇａ／（Ｇａ＋Ｉｎ）比が０．４１７～０．５００の範囲にあるｐ形半導体層１３のバンドギャップは、１．２７～１．３３ｅＶの範囲にある。 In a p-type semiconductor layer 13 containing In and Ga (for example, Cu (In, Ga) Se 2 ), the band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.250 to 0.300 is , 1.17 to 1.20 eV. The band gap of the p-type semiconductor layer 13 having a Ga / (Ga + In) ratio in the range of 0.417 to 0.500 is in the range of 1.27 to 1.33 eV.
　本実施形態の太陽電池におけるその他の層について以下に説明する。 Other layers in the solar cell of this embodiment will be described below.
　基板１１に用いる材料は特に限定されず、太陽電池に一般的に用いられる材料であればよい。たとえば、ガラス基板、ポリイミド基板などの非金属材料からなる基板の他、デュラルミンなどのアルミニウム合金基板、ステンレス基板などの金属材料からなる基板などを用いればよい。なお、本実施形態の太陽電池が、直列接続された複数のユニットセルを基板１１上に形成する集積形太陽電池である場合には、少なくとも基板１１の表面が絶縁性である必要がある。このため、導電性の基板（たとえば、ステンレス基板）を用いる場合には、基板の表面に絶縁層を形成するか、基板の表面を絶縁化する処理を行う必要がある。 The material used for the substrate 11 is not particularly limited as long as it is a material generally used for solar cells. For example, a substrate made of a non-metallic material such as a glass substrate or a polyimide substrate, an aluminum alloy substrate such as duralumin, or a substrate made of a metal material such as a stainless steel substrate may be used. In addition, when the solar cell of this embodiment is an integrated solar cell which forms the several unit cell connected in series on the board | substrate 11, at least the surface of the board | substrate 11 needs to be insulating. For this reason, when a conductive substrate (for example, a stainless steel substrate) is used, it is necessary to form an insulating layer on the surface of the substrate or to insulate the surface of the substrate.
　第１の電極層１２に用いる材料は、導電性を有する限り特に限定されない。たとえば、体積抵抗率が６×１０6Ω・ｃｍ以下の金属や半導体などを用いてもよい。具体的には、たとえばＭｏ（モリブデン）を用いることができる。第１の電極層１２の形状は特に限定されず、太陽電池１０の電極層に求められる形状を採用できる。その他の層の形状についても同様である。第１の電極層１２の厚さは、たとえば０．１μｍ～１μｍ程度の範囲としてもよい。 The material used for the first electrode layer 12 is not particularly limited as long as it has conductivity. For example, a metal or semiconductor having a volume resistivity of 6 × 10 6 Ω · cm or less may be used. Specifically, for example, Mo (molybdenum) can be used. The shape of the 1st electrode layer 12 is not specifically limited, The shape calculated | required by the electrode layer of the solar cell 10 is employable. The same applies to the shapes of the other layers. The thickness of the first electrode layer 12 may be, for example, in the range of about 0.1 μm to 1 μm.
　ｎ形半導体層１４に用いる材料は、ｐ形半導体層１３とｐ－ｎ接合を形成できる材料である限り特に限定されず、たとえば、ＣｄＳや、Ｚｎを含む化合物を用いてもよい。本実施形態の太陽電池では、ｎ形半導体層１４が複数のｎ形半導体層からなるものであってもよい。ｎ形半導体層１４が、ｎ形半導体層１４ａおよび１４ｂからなる場合の一例の太陽電池１０ａの断面図を、図２に示す。 The material used for the n-type semiconductor layer 14 is not particularly limited as long as it can form a pn junction with the p-type semiconductor layer 13. For example, CdS or a compound containing Zn may be used. In the solar cell of this embodiment, the n-type semiconductor layer 14 may be composed of a plurality of n-type semiconductor layers. FIG. 2 shows a cross-sectional view of an example solar cell 10a when the n-type semiconductor layer 14 is composed of n- type semiconductor layers 14a and 14b.
　ｎ形半導体層１４ａは、ＣｄＳ、Ｚｎ（Ｏ，Ｓ）、ＺｎＭｇＯなどで形成してもよい。ｎ形半導体層１４ｂは、ｎ形半導体層１４ａとは異なる材料で形成でき、たとえば、ＺｎＯまたはＺｎＯを含む材料を用いて形成してもよい。ｎ形半導体層１４ａの厚さは、たとえば、５ｎｍ～２００ｎｍの範囲としてもよく、ｎ形半導体層１４ｂの厚さは、たとえば、５０ｎｍ～２００ｎｍの範囲としてもよい。なお、ｎ形半導体層１４ｂは省略が可能である。 The n-type semiconductor layer 14a may be formed of CdS, Zn (O, S), ZnMgO, or the like. The n-type semiconductor layer 14b can be formed using a material different from that of the n-type semiconductor layer 14a. For example, the n-type semiconductor layer 14b may be formed using ZnO or a material containing ZnO. The thickness of the n-type semiconductor layer 14a may be in the range of 5 nm to 200 nm, for example, and the thickness of the n-type semiconductor layer 14b may be in the range of 50 nm to 200 nm, for example. The n-type semiconductor layer 14b can be omitted.
　光入射側にある第２の電極層１５は、たとえば、透光性を有する導電性材料で形成できる。ここでいう「透光性」とは、太陽電池１０の発電に寄与する光に対する透光性であればよい。たとえば、電極層１５として、インジウム・スズ酸化物（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ：ＩＴＯ）からなる層や、ＺｎＯや、１３族元素（ＡｌやＧａなど）をドープしたＺｎＯからなる層や、それらの積層膜を用いることができる。第２の電極層１５の厚さは、たとえば、０．１～０．６μｍ程度の範囲としてもよい。 The second electrode layer 15 on the light incident side can be formed of, for example, a light-transmitting conductive material. Here, the “translucency” may be any translucency with respect to light that contributes to power generation of the solar cell 10. For example, as the electrode layer 15, a layer made of indium tin oxide (ITO), a layer made of ZnO doped with ZnO or a group 13 element (Al, Ga, etc.), or a laminated film thereof is used. Can be used. The thickness of the second electrode layer 15 may be in the range of about 0.1 to 0.6 μm, for example.
　取り出し電極１６および１７に用いる材料は特に限定されず、太陽電池の取り出し電極に一般的に用いられる材料であればよい。たとえば、ＮｉＣｒ、Ａｇ、Ａｕ、Ａｌなどを用いてもよい。 The material used for the extraction electrodes 16 and 17 is not particularly limited as long as it is a material generally used for the extraction electrode of the solar cell. For example, NiCr, Ag, Au, Al, etc. may be used.
　図１に示す太陽電池１０では、第１の電極層１２、ｐ形半導体層１３、ｎ形半導体層１４および第２の電極層１５が基板１１の上に配置されている。しかし、本実施形態の太陽電池では基板１１は必ずしも必要ではなく、必要に応じて省略できる。取り出し電極１６および１７も、基板１１と同様に、必要に応じて省略できる。また、本実施形態の太陽電池では、上述した各層の間に、必要に応じて任意の層を配置してもよい。 In the solar cell 10 shown in FIG. 1, the first electrode layer 12, the p-type semiconductor layer 13, the n-type semiconductor layer 14, and the second electrode layer 15 are disposed on the substrate 11. However, in the solar cell of the present embodiment, the substrate 11 is not necessarily required and can be omitted as necessary. Similarly to the substrate 11, the extraction electrodes 16 and 17 can be omitted as necessary. Moreover, in the solar cell of this embodiment, you may arrange | position arbitrary layers between each layer mentioned above as needed.
　（本実施形態の太陽電池の製造方法の一例）
　本実施形態の太陽電池の製造方法の一例について以下に説明する。ｐ形半導体層１３以外の層は、太陽電池の製造に一般的に用いられている手法によって製造できる。基板１１上に第１の電極層１２を形成するためには、たとえば、スパッタリング法や蒸着法などを用いることができる。ｐ形半導体層１３上へｎ形半導体層１４（たとえばｎ形半導体層１４ａおよび１４ｂ）を形成するためには、たとえば、スパッタリング法を用いてもよい。第２の電極層１５の形成には、たとえば、スパッタリング法を用いてもよい。取り出し電極１６および１７を形成する方法は、各取り出し電極が各電極層と電気的に接続できる限り特に限定されず、一般的な方法を用いてもよい。 (An example of the manufacturing method of the solar cell of this embodiment)
An example of the manufacturing method of the solar cell of this embodiment is demonstrated below. The layers other than the p-type semiconductor layer 13 can be manufactured by a technique generally used for manufacturing solar cells. In order to form the first electrode layer 12 on the substrate 11, for example, a sputtering method or a vapor deposition method can be used. In order to form the n-type semiconductor layer 14 (for example, the n- type semiconductor layers 14a and 14b) on the p-type semiconductor layer 13, for example, a sputtering method may be used. For example, a sputtering method may be used to form the second electrode layer 15. The method of forming the extraction electrodes 16 and 17 is not particularly limited as long as each extraction electrode can be electrically connected to each electrode layer, and a general method may be used.
　第１の電極層１２上へのｐ形半導体層１３の形成には、たとえば、蒸着法、より具体的には多元蒸着法などを用いればよい。多元蒸着法とは、複数の蒸着源を用いた蒸着法である。たとえば、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2からなるｐ形半導体層１３を形成する場合の一例では、Ｃｕ蒸着源と、Ｉｎ蒸着源と、Ｇａ蒸着源と、Ｓｅ蒸着源との４種類の蒸着源を用いてもよい。この場合の一例では、Ｇａ蒸着源へ印加するエネルギーを制御し、他の原子に対するＧａ原子の熱拡散のスピードを制御することによって、Ｇａの原子数比が膜厚方向に変化したｐ形半導体層１３を形成できる。また、スパッタリング法や蒸着法などによって第１の電極層１２上に予めＧａ層を形成し、そのＧａ層上にさらにＣｕ（Ｉｎ，Ｇａ）Ｓｅ2層を形成し、その後に熱処理してＧａ原子を拡散させる方法でも、Ｇａの原子数比が膜厚方向に変化したｐ形半導体層１３を形成できる。ＡｌやＩｎの原子数比が膜厚方向に変化したｐ形半導体層１３を形成する場合でも、同様の方法（上記方法におけるＧａの一部をＡｌやＩｎに置き換えた方法）を用いればよい。なお、ｐ形半導体層１３の形成方法は、上記の例に限定されず、上述したｐ形半導体層１３の構成を実現できる方法であればよい。 For the formation of the p-type semiconductor layer 13 on the first electrode layer 12, for example, an evaporation method, more specifically, a multi-source evaporation method may be used. The multi-source evaporation method is an evaporation method using a plurality of evaporation sources. For example, in an example of forming the p-type semiconductor layer 13 made of Cu (In, Ga) Se 2 , four types of vapor deposition sources of a Cu vapor deposition source, an In vapor deposition source, a Ga vapor deposition source, and a Se vapor deposition source are used. May be used. In an example of this case, the p-type semiconductor layer in which the atomic ratio of Ga is changed in the film thickness direction by controlling the energy applied to the Ga vapor deposition source and controlling the thermal diffusion speed of Ga atoms with respect to other atoms. 13 can be formed. Further, a Ga layer is formed in advance on the first electrode layer 12 by a sputtering method, a vapor deposition method, or the like, and a Cu (In, Ga) Se 2 layer is further formed on the Ga layer. The p-type semiconductor layer 13 in which the Ga atom number ratio is changed in the film thickness direction can also be formed by the method of diffusing. Even when the p-type semiconductor layer 13 in which the atomic ratio of Al or In is changed in the film thickness direction is formed, a similar method (a method in which a part of Ga in the above method is replaced with Al or In) may be used. The method for forming the p-type semiconductor layer 13 is not limited to the above example, and any method that can realize the configuration of the p-type semiconductor layer 13 described above may be used.
　以下では、実施例によって本実施形態をさらに詳細に説明するが、本実施形態は以下の実施例に限定されない。 Hereinafter, the present embodiment will be described in more detail by way of examples, but the present embodiment is not limited to the following examples.
　（実施例１）
　実施例１では、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2からなるｐ形半導体層１３の膜厚方向におけるＧａの濃度と、変換効率との関係についてシミュレーションを行った。 (Example 1)
In Example 1, a simulation was performed on the relationship between the Ga concentration in the film thickness direction of the p-type semiconductor layer 13 made of Cu (In, Ga) Se 2 and the conversion efficiency.
　まず、シミュレーションに用いた太陽電池のモデルについて説明する。太陽電池のモデルとして、図２に示す太陽電池１０ａを用いた。より具体的には、表１に示す条件でシミュレーションを行った。 First, the solar cell model used for the simulation will be described. A solar cell 10a shown in FIG. 2 was used as a model of the solar cell. More specifically, simulation was performed under the conditions shown in Table 1.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　ｐ形半導体層１３のバンドプロファイルは、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2からなるｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比を変化させることによって制御した。以下では、ｎ形半導体層１４側の主面におけるｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比を「Ｇ１」といい、第１の電極層１２側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比を「Ｇ２」という場合がある。 The band profile of the p-type semiconductor layer 13 was controlled by changing the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 made of Cu (In, Ga) Se 2 . Hereinafter, the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side is referred to as “G1”, and the Ga / (Ga + In) ratio on the main surface on the first electrode layer 12 side is referred to as “G1”. It may be referred to as “G2”.
　実施例１で用いたシミュレーションを行ったＧａ濃度のプロファイルを、図３に示す。このシミュレーションでは、ｐ形半導体層１３の中間点におけるＧａ／（Ｇａ＋Ｉｎ）比を０．３６に固定し、Ｇ２を０．４５に固定した。また、Ｇ１を０．１７～０．４１の範囲で変化させた。そして、ｎ形半導体層１４と中間点との間、および中間点と第１の電極層１２との間においてＧａ／（Ｇａ＋Ｉｎ）比が直線的に変化するという条件で変換効率を算出した。なお、Ｇ１が０．２７の場合、ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比は、ｎ形半導体層１４と第１の電極層１２との間で直線的に変化する。また、Ｇ２が０．３６の場合、中間点からｎ形半導体層１４までＧａ／（Ｇａ＋Ｉｎ）比は一定（０．３６）となる。なお、本明細書において、「Ｇａ／（Ｇａ＋Ｉｎ）比が直線的に変化する」とは、膜厚方向におけるＧａ／（Ｇａ＋Ｉｎ）比の変化率（Ｇａ／（Ｇａ＋Ｉｎ）比を表す直線の傾き）が一定であることを意味する。 FIG. 3 shows a Ga concentration profile for which the simulation used in Example 1 was performed. In this simulation, the Ga / (Ga + In) ratio at the midpoint of the p-type semiconductor layer 13 was fixed at 0.36, and G2 was fixed at 0.45. Further, G1 was changed in the range of 0.17 to 0.41. Then, the conversion efficiency was calculated under the condition that the Ga / (Ga + In) ratio varies linearly between the n-type semiconductor layer 14 and the intermediate point and between the intermediate point and the first electrode layer 12. When G1 is 0.27, the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 changes linearly between the n-type semiconductor layer 14 and the first electrode layer 12. When G2 is 0.36, the Ga / (Ga + In) ratio is constant (0.36) from the midpoint to the n-type semiconductor layer 14. In this specification, “Ga / (Ga + In) ratio changes linearly” means a change rate of Ga / (Ga + In) ratio in the film thickness direction (straight line representing Ga / (Ga + In) ratio). Means constant.
　シミュレーション結果を図４に示す。ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比が、ｎ形半導体層１４側から第１の電極層１２側に向かって直線的に増加するときに、変換効率が最も高かった。言い換えれば、ｎ形半導体層１４側の主面から第１の電極層１２側の主面まで、ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比が直線的かつ単調に増加するときに、変換効率が最も高かった。また、直線的でなくても、ｎ形半導体層１４側から第１の電極層１２側に向かってＧａ／（Ｇａ＋Ｉｎ）比がほぼ直線的に増加する場合には、高い変換効率が達成された。 The simulation results are shown in FIG. The conversion efficiency was highest when the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increased linearly from the n-type semiconductor layer 14 side toward the first electrode layer 12 side. In other words, when the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increases linearly and monotonically from the main surface on the n-type semiconductor layer 14 side to the main surface on the first electrode layer 12 side, the conversion efficiency Was the highest. Further, even if the Ga / (Ga + In) ratio increases almost linearly from the n-type semiconductor layer 14 side to the first electrode layer 12 side, high conversion efficiency is achieved even if it is not linear. .
　（実施例２）
　実施例２では、ｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比が膜厚方向に直線的に変化する場合についてシミュレーションを行った。このシミュレーションでは、第１の電極層１２側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比であるＧ２を、０．４５に固定した。一方、ｎ形半導体層１４側の主面におけるｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比であるＧ１を０～０．４５の範囲で変化させた。シミュレーションされたＧａ／（Ｇａ＋Ｉｎ）比のプロファイルの例として、Ｇ１が０、０．２７および０．４５の場合におけるＧａ／（Ｇａ＋Ｉｎ）比のプロファイルを図５に示す。なお、このシミュレーションにおいて、ｐ形半導体層１３、ｎ形半導体層１４ａ、ｎ形半導体層１４ｂ、および第２の電極層１５には、実施例１と同様に、表１に示す物性を仮定した。 (Example 2)
In Example 2, a simulation was performed for a case where the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 linearly changed in the film thickness direction. In this simulation, G2 which is the Ga / (Ga + In) ratio in the main surface on the first electrode layer 12 side was fixed to 0.45. On the other hand, G1 which is the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 on the main surface on the n-type semiconductor layer 14 side was changed in the range of 0 to 0.45. As an example of a simulated Ga / (Ga + In) ratio profile, FIG. 5 shows a Ga / (Ga + In) ratio profile when G1 is 0, 0.27, and 0.45. In this simulation, the physical properties shown in Table 1 were assumed for the p-type semiconductor layer 13, the n-type semiconductor layer 14a, the n-type semiconductor layer 14b, and the second electrode layer 15 as in Example 1.
　シミュレーション結果を図６に示す。シミュレーション結果から、Ｇ１が０．２７のとき太陽電池特性が最大となることが分かった。すなわち、Ｇ１とＧ２との比には最適値があり、その値は、Ｇ１／Ｇ２＝０．２７／０．４５＝０．６であった。また、実施例２のシミュレーションにおいて、Ｇａ／（Ｇａ＋Ｉｎ）比の傾きの最適値は、（０．４５－０．２７）／０．６＝０．３μｍ-1であった。 The simulation result is shown in FIG. From the simulation results, it was found that the solar cell characteristics are maximized when G1 is 0.27. That is, the ratio between G1 and G2 has an optimum value, and the value is G1 / G2 = 0.27 / 0.45 = 0.6. In the simulation of Example 2, the optimum value of the slope of the Ga / (Ga + In) ratio was (0.45−0.27) /0.6=0.3 μm −1 .
　（実施例３）
　実施例１のシミュレーション結果を検証するために、ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比のプロファイルが異なる２つの太陽電池を作製して評価した。 (Example 3)
In order to verify the simulation result of Example 1, two solar cells having different Ga / (Ga + In) ratio profiles in the p-type semiconductor layer 13 were produced and evaluated.
　初めに、基板として厚さ１．１ｍｍのソーダライムガラス基板を用意した。このソーダライムガラス基板を洗剤で洗浄したのち純水ですすぐことによって、基板を洗浄した。次に、このソーダライムガラス基板上に、８００ｎｍの厚さのＭｏ膜（第１の電極層１２）を形成した。Ｍｏ膜は、Ａｒガス中においてＭｏをターゲットとした直流スパッタ法（ＤＣスパッタ法）によって形成した。スパッタ時の圧力は０．３Ｐａとした。 First, a 1.1 mm thick soda lime glass substrate was prepared as a substrate. The soda lime glass substrate was cleaned with a detergent and then rinsed with pure water to clean the substrate. Next, an Mo film (first electrode layer 12) having a thickness of 800 nm was formed on the soda-lime glass substrate. The Mo film was formed by a direct current sputtering method (DC sputtering method) using Mo as a target in Ar gas. The pressure during sputtering was 0.3 Pa.
　次に、Ｍｏ膜上にＣｕ（Ｉｎ，Ｇａ）Ｓｅ2層（ｐ形半導体層１３）を形成した。Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2層は、Ｃｕ、Ｉｎ、Ｇａ、およびＳｅを１種類ずつ入れた４つのクヌーセンセルを備えた蒸着装置で形成した。Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2膜は、３段階法で形成した。具体的には、１段階目として、基板温度４００℃でＩｎとＧａとＳｅとを蒸着した。次に、２段階目として、（Ｃｕの原子数）／（Ｇａの原子数＋Ｉｎの原子数）＝１．３となるまでＣｕとＳｅとを蒸着した。次に、３段階目として、（Ｃｕの原子数）／（Ｇａの原子数＋Ｉｎの原子数）＝０．９となるまで、ＩｎとＧａとＳｅとを蒸着した。Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2層の膜厚は蒸着時間によって変えることができ、膜厚が０．６μｍになるように蒸着時間を調節した。 Next, a Cu (In, Ga) Se 2 layer (p-type semiconductor layer 13) was formed on the Mo film. The Cu (In, Ga) Se 2 layer was formed by a vapor deposition apparatus provided with four Knudsen cells each containing one kind of Cu, In, Ga, and Se. The Cu (In, Ga) Se 2 film was formed by a three-step method. Specifically, as the first stage, In, Ga, and Se were deposited at a substrate temperature of 400 ° C. Next, as the second stage, Cu and Se were vapor-deposited until (Cu atom number) / (Ga atom number + In atom number) = 1.3. Next, as the third stage, In, Ga, and Se were vapor-deposited until (Cu atom number) / (Ga atom number + In atom number) = 0.9. The film thickness of the Cu (In, Ga) Se 2 layer can be changed depending on the vapor deposition time, and the vapor deposition time is adjusted so that the film thickness becomes 0.6 μm.
　３段階法では、１段階目と３段階目のＧａセルの温度を変えることによって、ｐ形半導体層１３中のＧａ／（Ｇａ＋Ｉｎ）比を膜厚方向に変えることができる。たとえば、１段階目のＧａセルの温度よりも３段階目のＧａセルの温度を下げることによって、第１の電極層１２側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比が大きく、ｎ形半導体層１４側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比が小さい傾斜構造を形成できる。実施例３では、１段階目のＧａセルの温度を９２８℃に固定し、３段階目のＧａセルの温度を８４８～９２８℃の範囲で変化させることによって、Ｇａ／（Ｇａ＋Ｉｎ）比を膜厚方向に変化させた。具体的には、３段階目のＧａセルの温度を、後述する表２の温度とした。 In the three-stage method, the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 can be changed in the film thickness direction by changing the temperature of the Ga cells in the first and third stages. For example, by lowering the temperature of the third-stage Ga cell than the temperature of the first-stage Ga cell, the Ga / (Ga + In) ratio in the main surface on the first electrode layer 12 side is increased, and the n-type semiconductor layer 14 An inclined structure having a small Ga / (Ga + In) ratio in the main surface on the side can be formed. In Example 3, the temperature of the first stage Ga cell is fixed at 928 ° C., and the temperature of the third stage Ga cell is changed in the range of 848 to 928 ° C., so that the Ga / (Ga + In) ratio is changed to the film thickness. The direction was changed. Specifically, the temperature of the Ga cell at the third stage was set to the temperature shown in Table 2 described later.
　次に、化学析出法によってＣｄＳ膜（ｎ形半導体層１４ａ）を形成した。具体的には、まず、酢酸カドミウム（Ｃｄ（ＣＨ3ＣＯＯ）2）、チオ尿素（ＮＨ2ＣＳＮＨ2）、酢酸アンモニウム（ＣＨ3ＣＯＯＮＨ4）およびアンモニアを含有する溶液を用意した。溶液中の酢酸カドミウムの濃度は０．００１ｍｏｌ／Ｌ、チオ尿素の濃度は０．００５ｍｏｌ／Ｌ、酢酸アンモニウムの濃度は０．０１ｍｏｌ／Ｌ、アンモニアの濃度は０．４ｍｏｌ／Ｌとした。この溶液を入れた容器を８５℃に保った温水槽に静置した。Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2層上にＣｄＳ膜を形成するために、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ2層が形成された基板をこの溶液の中に入れた。１５分間の処理によって、約１００ｎｍの膜厚を有するＣｄＳ膜が形成された。 Next, a CdS film (n-type semiconductor layer 14a) was formed by chemical deposition. Specifically, first, a solution containing cadmium acetate (Cd (CH 3 COO) 2 ), thiourea (NH 2 CSNH 2 ), ammonium acetate (CH 3 COONH 4 ) and ammonia was prepared. The concentration of cadmium acetate in the solution was 0.001 mol / L, the concentration of thiourea was 0.005 mol / L, the concentration of ammonium acetate was 0.01 mol / L, and the concentration of ammonia was 0.4 mol / L. The container in which this solution was put was left still in the warm water tank kept at 85 degreeC. Cu (In, Ga) to form a CdS film on the Se 2 layer was placed Cu (In, Ga) a substrate Se 2 layer was formed in the solution. A CdS film having a film thickness of about 100 nm was formed by the treatment for 15 minutes.
　さらに、ＺｎＯターゲットを用いたスパッタリング法によって、ＺｎＯ膜（ｎ形半導体層１４ｂ：膜厚１００ｎｍ）をＣｄＳ膜上に形成した。スパッタリングは、アルゴンガス圧が２．６６Ｐａ（２×１０-2Ｔｏｒｒ）、ＺｎＯターゲットに加えた高周波パワーが５０Ｗの条件で行った。 Further, a ZnO film (n-type semiconductor layer 14b: film thickness 100 nm) was formed on the CdS film by a sputtering method using a ZnO target. Sputtering was performed under the conditions of an argon gas pressure of 2.66 Pa (2 × 10 −2 Torr) and a high frequency power applied to the ZnO target of 50 W.
　さらに、透明導電膜であるＺｎＯ：Ａｌ（第２の電極層１５：膜厚１００ｎｍ）をＺｎＯ：Ａｌターゲットを用いたスパッタリング法によって形成した。具体的には、アルゴンガス圧１．０６４Ｐａ（８×１０-3Ｔｏｒｒ）、高周波パワー５０Ｗの条件によって形成した。その後、熱蒸着法によってＡｌ膜からなる取り出し電極を形成した。このようにして、３段階目のＧａセルの温度を変えて複数の太陽電池を作製した。 Furthermore, a transparent conductive film ZnO: Al (second electrode layer 15: film thickness 100 nm) was formed by a sputtering method using a ZnO: Al target. Specifically, it was formed under the conditions of an argon gas pressure of 1.064 Pa (8 × 10 −3 Torr) and a high frequency power of 50 W. Thereafter, an extraction electrode made of an Al film was formed by thermal evaporation. In this manner, a plurality of solar cells were produced by changing the temperature of the third stage Ga cell.
　作製したｐ形半導体層１３について、ＳＩＭＳ分析（Secondary Ion Mass Spectrometry、二次イオン質量分析法）を行った。３段階目のＧａセルの温度を９０８℃としたときのＧａ／（Ｇａ＋Ｉｎ）比の測定結果を図７の点線（ａ）に示す。また、第３段階目のＧａセルの温度を８８８℃としたときのＧａ／（Ｇａ＋Ｉｎ）比の測定結果を図７の線（ｂ）に示す。図７に示すように、実施例１でシミュレーションした傾斜構造（図３参照）が形成された。図７の線（ｂ）で示されるｐ形半導体層１３では、ｎ形半導体層１４側から第１の電極層１２側に向かって、Ｇａ／（Ｇａ＋Ｉｎ）比がほぼ直線的に増加している。 The p-type semiconductor layer 13 thus produced was subjected to SIMS analysis (Secondary / Ion / Mass / Spectrometry, secondary ion mass spectrometry). The measurement result of the Ga / (Ga + In) ratio when the temperature of the third-stage Ga cell is 908 ° C. is shown by the dotted line (a) in FIG. The measurement result of the Ga / (Ga + In) ratio when the temperature of the third stage Ga cell is 888 ° C. is shown in FIG. As shown in FIG. 7, the inclined structure (see FIG. 3) simulated in Example 1 was formed. In the p-type semiconductor layer 13 indicated by the line (b) in FIG. 7, the Ga / (Ga + In) ratio increases almost linearly from the n-type semiconductor layer 14 side to the first electrode layer 12 side. .
　表２に、３段階目のＧａセルの温度と、ｎ形半導体層１４側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比（すなわちＧ１の値）の実測値との関係を示す。 Table 2 shows the relationship between the temperature of the Ga cell at the third stage and the measured value of the Ga / (Ga + In) ratio (that is, the value of G1) on the main surface on the n-type semiconductor layer 14 side.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　上述した方法で作製された太陽電池に、ＡＭ（Air Mass）１．５、１００ｍＷ／ｃｍ2の疑似太陽光を照射して変換効率を測定した。測定結果を図８に示す。図８の測定結果は、実施例１のシミュレーションで仮定したＧａ／（Ｇａ＋Ｉｎ）比のプロファイル（図３参照）の実験結果に対応する。実測値では、Ｇ１の値が０．２７のときに変換効率がピークとなった。この結果は、実施例１のシミュレーションの結果（図４参照）と一致した。これらの結果は、ｐ形半導体層１３のＧａ／（Ｇａ＋Ｉｎ）比が、ｎ形半導体層１４側から第１の電極層１２側に向かって直線状に増加することによって高い変換効率が達成されることを示している。 The conversion efficiency was measured by irradiating the solar cell manufactured by the above-described method with artificial sunlight of AM (Air Mass) 1.5 and 100 mW / cm 2 . The measurement results are shown in FIG. The measurement results in FIG. 8 correspond to the experimental results of the Ga / (Ga + In) ratio profile (see FIG. 3) assumed in the simulation of Example 1. In actual measurement, the conversion efficiency peaked when the value of G1 was 0.27. This result coincided with the simulation result of Example 1 (see FIG. 4). These results show that a high conversion efficiency is achieved by increasing the Ga / (Ga + In) ratio of the p-type semiconductor layer 13 linearly from the n-type semiconductor layer 14 side toward the first electrode layer 12 side. It is shown that.
　（実施例４）
　実施例４では、ｎ形半導体層１４側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比、および第１の電極層１２側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比を変化させてシミュレーションを行い、変換効率を算出した。上記実施例の結果を考慮して、実施例４では、ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比を、膜厚方向に直線状に変化させた。なお、このシミュレーションにおいて、ｐ形半導体層１３、ｎ形半導体層１４ａ、ｎ形半導体層１４ｂ、および第２の電極層１５には、以下の表３に示す物性を仮定した。 Example 4
In Example 4, a simulation is performed by changing the Ga / (Ga + In) ratio on the main surface on the n-type semiconductor layer 14 side and the Ga / (Ga + In) ratio on the main surface on the first electrode layer 12 side, thereby converting the conversion efficiency. Was calculated. In consideration of the results of the above examples, in Example 4, the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 was changed linearly in the film thickness direction. In this simulation, the physical properties shown in Table 3 below were assumed for the p-type semiconductor layer 13, the n-type semiconductor layer 14a, the n-type semiconductor layer 14b, and the second electrode layer 15.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　実施例４では、ｎ形半導体層１４側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比（すなわちＧ１の値）を０．１５０～０．４００の範囲で変化させ、第１の電極層１２側の主面におけるＧａ／（Ｇａ＋Ｉｎ）比（すなわちＧ２の値）を０．２５０～０．６６７の範囲で変化させた。また、ｐ形半導体層１３の膜厚は、０．５～０．７μｍの範囲で変化させた。設定したＧ１およびＧ２の値、およびそのときのＧａ／（Ｇａ＋Ｉｎ）比の傾きを表４に示す。 In Example 4, the Ga / (Ga + In) ratio (that is, the value of G1) on the main surface on the n-type semiconductor layer 14 side is changed in the range of 0.150 to 0.400, and the main electrode on the first electrode layer 12 side is changed. The Ga / (Ga + In) ratio (that is, the value of G2) on the surface was changed in the range of 0.250 to 0.667. The film thickness of the p-type semiconductor layer 13 was changed in the range of 0.5 to 0.7 μm. Table 4 shows the set values of G1 and G2 and the slope of the Ga / (Ga + In) ratio at that time.
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
　シミュレーションしたプロファイルの２つの例（表４の番号１および１１）を、図９に示す。また、変換効率の計算結果を図１０に示す。 Two examples of simulated profiles ( numbers 1 and 11 in Table 4) are shown in FIG. Moreover, the calculation result of conversion efficiency is shown in FIG.
　図１０に示すように、ｐ形半導体層１３の膜厚によらず、Ｇ１の値が０．２７５でＧ２の値が０．４５８の場合に変換効率が最大となった。また、表１０に示すように、ｐ形半導体層１３の厚さが０．５～０．７μｍの範囲にある場合、以下の条件を満たすことによって高い変換効率が達成されることが分かった。
（１）ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比が、ｎ形半導体層１４側から第１の電極層１２側に向かって増加している。詳細には、ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比が、ｎ形半導体層１４側の主面から第１の電極層１２側の主面まで単調かつ直線的に増加している。
（２）Ｇ１の値が０．２２５～０．３２５の範囲（たとえば０．２２５より大きく０．３２５未満の範囲）にある。
（３）Ｇ２の値が０．３７５～０．５４２の範囲（たとえば０．３７５より大きく０．５４２未満の範囲）にある。 As shown in FIG. 10, regardless of the thickness of the p-type semiconductor layer 13, the conversion efficiency was maximized when the value of G1 was 0.275 and the value of G2 was 0.458. Further, as shown in Table 10, it was found that when the thickness of the p-type semiconductor layer 13 is in the range of 0.5 to 0.7 μm, high conversion efficiency is achieved by satisfying the following conditions.
(1) The Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increases from the n-type semiconductor layer 14 side toward the first electrode layer 12 side. Specifically, the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 increases monotonously and linearly from the main surface on the n-type semiconductor layer 14 side to the main surface on the first electrode layer 12 side.
(2) The value of G1 is in the range of 0.225 to 0.325 (for example, a range greater than 0.225 and less than 0.325).
(3) The value of G2 is in the range of 0.375 to 0.542 (for example, a range of greater than 0.375 and less than 0.542).
　また、上記（１）の要件に加えて、以下の要件を満たす場合に変換効率が特に高くなった。
（４）Ｇ１の値が０．２５０～０．３００の範囲にある。
（５）Ｇ２の値が０．４１７～０．５００の範囲にある。 In addition to the requirement (1), the conversion efficiency was particularly high when the following requirement was satisfied.
(4) The value of G1 is in the range of 0.250 to 0.300.
(5) The value of G2 is in the range of 0.417 to 0.500.
　別の観点では、図１０および表４に示すように、上記（１）および（２）の要件に加えて、以下の要件を満たす場合に変換効率が高くなった。
（６）ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比の傾きが０．２１４～０．４３４μｍ-1の範囲にある。 From another viewpoint, as shown in FIG. 10 and Table 4, in addition to the requirements (1) and (2) above, the conversion efficiency was increased when the following requirements were satisfied.
(6) The slope of the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 is in the range of 0.214 to 0.434 μm −1 .
　また、別の観点では、図１０および表４に示すように、上記（１）および（４）の要件に加えて、以下の要件を満たす場合に変換効率が特に高くなった。
（７）ｐ形半導体層１３におけるＧａ／（Ｇａ＋Ｉｎ）比の傾きが０．２３９～０．４００μｍ-1の範囲にある。 From another viewpoint, as shown in FIG. 10 and Table 4, in addition to the requirements (1) and (4) above, the conversion efficiency was particularly high when the following requirements were satisfied.
(7) The slope of the Ga / (Ga + In) ratio in the p-type semiconductor layer 13 is in the range of 0.239 to 0.400 μm −1 .
　比較例として、ｐ形半導体層１３の膜厚を、ＣＩＧＳ太陽電池の光吸収層の一般的な厚さである１．８μｍとして変換効率のシミュレーションを行った。シミュレーションは、ｐ形半導体層１３の膜厚を除いて上記実施例４のシミュレーションと同じ条件で行った。計算結果を図１１に示す。ｐ形半導体層１３の膜厚が０．５～０．７μｍの場合とは異なり、Ｇ１の値が０．３２５でＧ２の値が０．５４２の時に変換効率が最大となった。 As a comparative example, the conversion efficiency was simulated by setting the thickness of the p-type semiconductor layer 13 to 1.8 μm, which is a typical thickness of the light absorption layer of the CIGS solar cell. The simulation was performed under the same conditions as the simulation of Example 4 except for the film thickness of the p-type semiconductor layer 13. The calculation results are shown in FIG. Unlike the case where the thickness of the p-type semiconductor layer 13 is 0.5 to 0.7 μm, the conversion efficiency is maximized when the value of G1 is 0.325 and the value of G2 is 0.542.
　図１０および図１１の結果は、１１族元素と１３族元素と１６族元素とを含む化合物半導体層を光吸収層として用いる場合、その厚さを一般的な厚さよりも薄くすると、光吸収層のＧａ／（Ｇａ＋Ｉｎ）比の分布の最適値が変化することを示している。この新たな知見に基づき、本実施形態は、光吸収層が薄い場合に高い変換効率が得られるように光吸収層のＧａ／（Ｇａ＋Ｉｎ）比のプロファイルを決定している。 The results of FIGS. 10 and 11 show that when a compound semiconductor layer containing a group 11 element, a group 13 element, and a group 16 element is used as the light absorption layer, the thickness is made thinner than a general thickness, and thus the light absorption layer. It shows that the optimum value of the distribution of the Ga / (Ga + In) ratio changes. Based on this new knowledge, the present embodiment determines the Ga / (Ga + In) ratio profile of the light absorption layer so that high conversion efficiency can be obtained when the light absorption layer is thin.
　本発明は、太陽電池に利用できる。本発明によれば、薄い光吸収層でも比較的高い変換効率を達成できるため、結果として、太陽電池の低コスト化を達成できる。本発明の太陽電池は、一般家庭、工場、太陽光発電施設、自動車、自転車、携帯型端末、携帯型コンピューターなどのエネルギー源として有用である。 The present invention can be used for solar cells. According to the present invention, a relatively high conversion efficiency can be achieved even with a thin light absorption layer, and as a result, cost reduction of the solar cell can be achieved. The solar cell of the present invention is useful as an energy source for general households, factories, solar power generation facilities, automobiles, bicycles, portable terminals, portable computers and the like.

Claims (3)

  1. 　第１の電極層と、第２の電極層と、前記第１の電極層と前記第２の電極層との間に配置されたｐ形半導体層と、前記ｐ形半導体層と前記第２の電極層との間に配置されたｎ形半導体層とを含む太陽電池であって、
    　前記ｐ形半導体層は、１１族元素、１３族元素および１６族元素を含み、且つ、カルコパイライト構造を有する化合物半導体からなり、
    　前記ｐ形半導体層は、前記１３族元素としてＩｎおよびＧａを含み、
    　前記ｐ形半導体層の厚さが０．５～０．７μｍの範囲にあり、
    　前記ｐ形半導体層における（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が、前記ｎ形半導体層側から前記第１の電極層側に向かって増加しており、
    　前記ｎ形半導体層側の主面における前記ｐ形半導体層の（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が０．２２５～０．３２５の範囲にあり、
    　前記第１の電極層側の主面における前記ｐ形半導体層の（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が０．３７５～０．５４２の範囲にある太陽電池。     A first electrode layer; a second electrode layer; a p-type semiconductor layer disposed between the first electrode layer and the second electrode layer; the p-type semiconductor layer; and the second electrode layer. A solar cell comprising an n-type semiconductor layer disposed between the electrode layers,
    The p-type semiconductor layer includes a compound semiconductor including a group 11 element, a group 13 element, and a group 16 element, and having a chalcopyrite structure,
    The p-type semiconductor layer contains In and Ga as the group 13 element,
    The p-type semiconductor layer has a thickness in the range of 0.5 to 0.7 μm;
    The value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) in the p-type semiconductor layer increases from the n-type semiconductor layer side toward the first electrode layer side. ,
    A value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) of the p-type semiconductor layer on the main surface on the n-type semiconductor layer side is in a range of 0.225 to 0.325;
    The value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) of the p-type semiconductor layer on the main surface on the first electrode layer side is in the range of 0.375 to 0.542. Solar cell.
  2. 　前記ｎ形半導体層側の主面における前記ｐ形半導体層の（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が０．２５０～０．３００の範囲にあり、
    　前記第１の電極層側の主面における前記ｐ形半導体層の（（Ｇａの原子数）／（Ｇａの原子数＋Ｉｎの原子数））の値が、０．４１７～０．５００の範囲にある、請求項１に記載の太陽電池。     The value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) of the p-type semiconductor layer on the main surface on the n-type semiconductor layer side is in the range of 0.250 to 0.300;
    The value of ((number of Ga atoms) / (number of Ga atoms + number of In atoms)) of the p-type semiconductor layer on the main surface on the first electrode layer side is in the range of 0.417 to 0.500. The solar cell according to claim 1, wherein
  3. 　前記１１族元素がＣｕであり、
    　前記１６族元素がＳｅおよびＳから選ばれる少なくとも１つの元素である、請求項１に記載の太陽電池。     The Group 11 element is Cu;
    The solar cell according to claim 1, wherein the group 16 element is at least one element selected from Se and S.
PCT/JP2013/006909 2012-11-26 2013-11-25 Solar cell WO2014080639A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10135498A (en) * 1996-10-25 1998-05-22 Showa Shell Sekiyu Kk Solar cell composed of chalcopyrite multi-component compound semiconductor thin-film light-absorbing layer
JPH10135495A (en) * 1996-10-25 1998-05-22 Showa Shell Sekiyu Kk Method and apparatus for manufacturing thin-film solar cell

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10135498A (en) * 1996-10-25 1998-05-22 Showa Shell Sekiyu Kk Solar cell composed of chalcopyrite multi-component compound semiconductor thin-film light-absorbing layer
JPH10135495A (en) * 1996-10-25 1998-05-22 Showa Shell Sekiyu Kk Method and apparatus for manufacturing thin-film solar cell

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