WO2014061971A1 - High-brightness semiconductor light-emitting element having light-emitting region separation trench and excellent current dispersion effect - Google Patents

High-brightness semiconductor light-emitting element having light-emitting region separation trench and excellent current dispersion effect Download PDF

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WO2014061971A1
WO2014061971A1 PCT/KR2013/009208 KR2013009208W WO2014061971A1 WO 2014061971 A1 WO2014061971 A1 WO 2014061971A1 KR 2013009208 W KR2013009208 W KR 2013009208W WO 2014061971 A1 WO2014061971 A1 WO 2014061971A1
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layer
extension electrode
semiconductor layer
trench
light emitting
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French (fr)
Korean (ko)
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황성주
김동우
송정섭
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일진엘이디(주)
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the present invention relates to a semiconductor light emitting device having improved luminance characteristics, including a light emitting region isolation trench and a contact hole structure.
  • a conventional semiconductor light emitting device is, for example, a GaN nitride semiconductor light emitting device, which is a high-speed switching device such as a blue or green LED light emitting device, MESFET and HEMT in the application field And high output devices.
  • FIG. 1 schematically shows a general nitride-based semiconductor light emitting device.
  • a nitride semiconductor light emitting device is formed from a growth substrate 11. More specifically, the nitride based light emitting device includes an n-type nitride semiconductor layer 12, an active layer 13, and a p-type nitride semiconductor layer 14.
  • an n-side electrode pad 15 electrically connected to the n-type nitride semiconductor layer 12 is formed.
  • a p-side electrode pad 16 electrically connected to the p-type nitride semiconductor layer 14 is formed.
  • the p-type nitride semiconductor layer has a high specific resistance. Therefore, the current is not evenly distributed in the p-type nitride semiconductor layer, and the current is concentrated in the portion where the p-side electrode pad is formed.
  • planar structure light emitting device in which two electrodes are arranged almost horizontally on the upper surface of the light emitting structure has a uniform current flow in the entire light emitting area as compared to the vertical structure light emitting device.
  • the effective area to join is not large.
  • the light emitting device is gradually increasing in size to about 1 mm 2 or more.
  • the problem of current dispersion due to the large area has been recognized as an important technical problem in semiconductor light emitting devices.
  • n-side electrode and p-side electrode include a plurality of electrode fingers that extend and engage with each other at regular intervals. Through this electrode structure, it was intended to provide an additional current path, secure a large effective emission area, and form a uniform current flow.
  • the present inventors have conducted research and efforts to develop a semiconductor light emitting device having a structure capable of exhibiting an excellent current dispersion effect, and as a result, the first semiconductor layer exposed inside the contact hole and the upper portion of the second semiconductor layer formed to expose the first semiconductor layer.
  • a first extension electrode that electrically connects the second electrode, a trench that can separate a plurality of light emitting regions, a gap between the second semiconductor layer and the first extension electrode, between the sidewall of the contact hole and the first extension electrode;
  • the present invention has been completed by discovering that an insulating layer is formed between the surface of the trench and the first extension electrode to form a semiconductor light emitting device having a plurality of light emitting regions, thereby maximizing current dispersion to improve luminance.
  • an object of the present invention is to provide a semiconductor light emitting device having an electrode structure and a trench for separating a light emitting region, which exhibit excellent current dispersion effects.
  • the semiconductor light emitting device of the present invention is characterized in that a plurality of light emitting regions are separated by the trench.
  • the semiconductor light emitting device of the present invention is formed such that the current diffusion contact hole exposes the first semiconductor layer, and a first extension electrically connecting the first semiconductor layer exposed by the current diffusion contact hole. And an second extension electrode electrically connected to the electrode and the second semiconductor layer.
  • the semiconductor light emitting device of the present invention includes an insulating layer electrically insulating the first extension electrode and the active layer, the second semiconductor layer or the trench region, and electrically insulating the second extension electrode and the trench region.
  • the insulating layer may be formed between the second semiconductor layer and the first extension electrode, between the sidewall of the current diffusion contact hole and the first extension electrode, and between the surface of the trench and the first extension electrode.
  • the semiconductor light emitting device of the present invention can spread the current flowing through the semiconductor layer evenly to increase the effective light emitting area.
  • the respective light emitting regions are separated by the light emitting region isolation trenches, the same effects as those of individual elements connected in parallel can be obtained, and the light efficiency can be improved.
  • FIG. 1 is a cross-sectional view showing a cross section of a conventional semiconductor light emitting device.
  • FIG. 2 is a plan view of a semiconductor light emitting device according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view taken along the line A-A of FIG. 2.
  • FIG. 4 is a cross-sectional view taken along the line B-B of FIG. 2.
  • FIG. 5 is a plan view of a semiconductor light emitting device according to a comparative example of the present invention.
  • the first semiconductor layer is an n-type nitride layer
  • the second semiconductor layer is a p-type nitride layer
  • the first extension electrode is an n-side extension electrode
  • the second extension electrode is a p-side extension electrode
  • the first electrode pad is n
  • the side electrode pads and the second electrode pads are referred to as p-side electrode pads.
  • FIG. 2 is a plan view of a horizontal semiconductor light emitting device according to a first embodiment of the present invention.
  • the light emitting device includes a light emitting region isolation trench 120 that penetrates the p-type nitride layer and the active layer to separate the light emitting region into a plurality of regions.
  • the trench 120 may further include a contact hole 110 formed to expose the n-type nitride layer through the p-type nitride layer and the active layer.
  • an n-side extension electrode 111 electrically connecting the n-type nitride layer exposed by the contact hole 110 to the inside of the contact hole, the p-type nitride layer and the light emitting region isolation trench 120 is included. do.
  • the emission region isolation trench 120 may be formed in a vertical direction of the n-side extension electrode 111.
  • the n-side extension electrode 111 may be electrically connected to the n-side electrode pad 112, and two or more contact holes 110 may be included in one n-side extension electrode 111.
  • the two or more contact holes 110 may be regularly spaced apart from each other, but the position at which the two or more contact holes 110 are formed is not particularly limited and may be arranged in various forms rather than in a straight line.
  • the p-side extension electrode 121 is electrically connected to the p-side electrode pad 122 positioned on a part of the upper portion of the p-type nitride layer to form the p-side electrode part.
  • the n-side extension electrode 111 is formed to be electrically insulated from the p-side extension electrode 121.
  • 3 and 4 illustrate cross-sectional views taken along the cutting lines A-A and B-B of FIG. 2 to explain more specific configurations.
  • a buffer layer 140, an n-type nitride layer 150, an active layer 160, and a p-type nitride layer 170 are stacked in an upper direction of the substrate 130. It is formed.
  • the substrate 130 may be made of a compound such as sapphire, SiC, Si, GaN, ZnO, GaAs, GaP, LiAl 2 O 3 , BN or AlN.
  • the buffer layer 140 may be selectively formed to solve the lattice mismatch between the substrate 130 and the n-type nitride layer 150, for example, may be formed of AlN or GaN.
  • the n-type nitride layer 150 is formed on the upper surface of the substrate 130 or the buffer layer 140, and is formed of nitride to which the n-type dopant is doped.
  • the n-type dopant silicon (Si), germanium (Ge), tin (Sn), or the like may be used.
  • the n-type nitride layer 150 is a laminated structure in which a first layer made of n-type AlGaN or undoped AlGaN doped with Si and a second layer made of n-type GaN doped with undoped or Si are formed. Can be.
  • n-type nitride layer 150 may be grown as a single n-type nitride layer, but may be formed as a laminated structure of the first layer and the second layer to act as a carrier limiting layer having good crystallinity without cracking. .
  • the active layer 160 may be formed of a single quantum well structure or a multi-quantum well structure between the n-type nitride layer 150 and the p-type nitride layer 170, and electrons flowing through the n-type nitride layer 150, p As holes flowing through the type nitride layer 170 are re-combined, light is generated.
  • the active layer 160 having a structure in which the quantum barrier layer and the quantum well layer are formed repeatedly may suppress spontaneous polarization due to stress and deformation generated.
  • the p-type nitride layer 170 is formed of a nitride doped with a p-type dopant.
  • a p-type dopant magnesium (Mg), zinc (Zn) or cadmium (Cd) may be used.
  • the p-type nitride layer may be formed by alternately stacking a first layer made of p-type AlGaN or undoped AlGaN doped with Mg, and a second layer made of p-type GaN doped with undoped or Mg. have.
  • the p-type nitride layer 170 may be grown as a single-layer p-type nitride layer similarly to the n-type nitride layer 150, but may be formed as a laminated structure to act as a carrier-limiting layer having good crystallinity without cracks. have.
  • the contact hole 110 is formed through the p-type nitride layer 170 and the active layer 160 to expose the n-type nitride layer 150.
  • the p-type nitride layer 170 and the active layer 160 are etched to form a light emitting region isolation trench 120.
  • the contact hole 110 and the trench 120 may be formed through a photoresist or the like.
  • a photoresist as a pattern mask
  • photo-lithography, e-beam lithography, and ion beam lithography Ion-beam Lithography, Extreme Ultraviolet Lithography, Proximity X-ray Lithography, or Nano imprint lithography, etc.
  • the dry or wet etching may be used.
  • n-contact layer 151 may be further included on the n-type nitride layer 150 exposed by the contact hole 110.
  • the n-contact layer 151 is ohmic contacted to the n-type nitride 150 to lower the contact resistance.
  • the n-contact layer 151 may be made of a transparent conductive oxide, and the material may include elements such as In, Sn, Al, Zn, Ga, and the like, for example, of ITO, CIO, ZnO, NiO, and In 2 O 3 . It can be formed of either.
  • an insulating layer 180 is formed on the sidewalls of the contact holes 110 to separate the sidewalls of the contact holes 110 from the n-side extension electrode 111 and are exposed by the contact holes 110. Part of the form nitride layer is exposed.
  • the insulating layer 180 extends over the p-type nitride 170 to separate the p-type nitride layer 170 from the n-side extension electrode 111, and extends over the trench 120 to form a trench.
  • the area 120 is spaced apart from the n-side extension electrode 111.
  • the insulating layer 180 may be formed of silicon oxide or silicon nitride, and may be formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, a MOCVD method, or an e-beam evaporation method.
  • PECVD plasma enhanced chemical vapor deposition
  • the n-side extension electrode 111 is formed in the contact hole 110, on the p-type nitride layer 170, and on the trench 120 to electrically n-type nitride layer exposed by the contact hole 110. It serves to connect, it may be made of a material capable of electrical connection, such as metal, alloy or metal oxide.
  • n-side extension electrode 111 is electrically connected to the n-side electrode pad 112 present on the insulating layer 180.
  • a p-contact layer 171 may be formed below the p-side extension electrode 121 formed to be spaced apart from the n-side extension electrode 111, and the p-contact layer 171 may be a p-type nitride 170. Ohmic contact reduces contact resistance.
  • the p-contact layer 171 may be made of a transparent conductive oxide, and the material may include elements such as In, Sn, Al, Zn, Ga, and the like, for example, of ITO, CIO, ZnO, NiO, and In 2 O 3 . It can be formed of either.
  • the buffer layer 140, the n-type nitride layer 150, the active layer 160, and the p-type nitride layer 170 are disposed below the p-side extension electrode 121 in the upper direction of the substrate 130.
  • p-contact layer 171 are sequentially formed, and a trench 120 region where the active layer 160 and the p-type nitride layer 170 are etched is also formed, and the p-side extension electrode 121 is a p-side electrode. It is electrically connected to the pad 122.
  • the trench 120 is electrically insulated from the p-side extension electrode 121 by the insulating layer 180. As shown in FIG.
  • the insulating layer 180 which separates the p-contact layer 171 from the sidewalls and the bottom surface of the trench 120 includes the sidewalls of the n-side extension electrode 111 and the contact hole 110 and p.
  • the nitride layer 170 may be formed to be connected to or separated from the insulating layer 180 spaced apart from each other.
  • the cross section of the contact hole 110 may be formed as a circle, but is not limited to this, it may be formed in the form of a triangle, a square or other polygons.
  • the diameter of the cross section of the contact hole 110 may be formed in the range of 1 to 200 ⁇ m, preferably 5 to 150 ⁇ m, and when two or more contact holes are formed, the size of the cross sections may be all the same or different. have.
  • the distance between the neighboring contact holes 110 in the one n-side extension electrode 111 may vary depending on the cross-sectional area of the entire light emitting device, but preferably between the neighboring contact holes 110 in the one n-side extension electrode. The distance is adjusted to be within the range of 10 to 500 ⁇ m, more preferably 50 to 400 ⁇ m.
  • the width of the light emitting region separation trench 120 is preferably formed in the range of 0.5 to 20 ⁇ m, preferably 3 to 10 ⁇ m.
  • the width of the n-side extension electrode 111 may be adjusted within the range of 1 to 100 ⁇ m, preferably 5 to 50 ⁇ m, but is not limited thereto.
  • the width of the n-side extension electrode 111 may be maintained while being constant, but as the distance from the n-side electrode pad 112 increases, the width of the n-side extension electrode 111 connecting the contact holes is increased.
  • the width of the n-side extension electrode 111 connecting the contact hole may increase as the distance from the n-side electrode pad 112 increases in the one n-side extension electrode.
  • One or two or more n-side extension electrodes 111 may be electrically connected to the n-side electrode pad 112, and at least one contact hole may be formed in each of the n-side extension electrodes.
  • the n-side extension electrode 111 may be formed to have one or more bending points as well as a straight shape having no bending points.
  • One or more p-side extension electrodes 121 may also be electrically connected to the p-side electrode pad 122.
  • opposite ends that are not connected to the p-side electrode pad 122 are generally formed to be spaced apart from each other, but the ends may be connected to each other to form a closed figure. .
  • the n-side extension electrode 111 may be spaced apart by an insulating layer.
  • the light emitting regions of the semiconductor light emitting device of the present invention may be divided into a plurality of by the trench 120. As shown in FIG. 2, when two trenches 120 are formed, the light emitting regions are divided into three regions. do. As the trench 120 regions are formed between the plurality of contact holes 110, each light emitting region may include one or more contact holes 110.
  • the number of light emitting regions separated by the trench in one device is not particularly limited, but is preferably separated into 3 to 5 regions, and the light emitting regions are formed at equal intervals so that the areas of the light emitting regions are uniform. desirable.
  • the respective light emitting regions may have the same effect as if the individual elements are connected in parallel by the n-side extension electrode 111 and the p-side extension electrode 121, and the plurality of contact holes Current dispersion effect can be expected and brightness can be increased by improving current density.
  • GaN was applied as a nitride layer of a nitride light emitting device to a sapphire substrate, and a general Au-based electrode was applied as an extension electrode to obtain a light emitting device.
  • a light emitting device was manufactured by stacking the same nitride-based component as in Example on a sapphire substrate, but having a plan view as illustrated in FIG. 5.
  • the light emitting device of the embodiment was improved by about 3.1% or more light output compared to the comparative example, it was confirmed that the light emitting device of the embodiment can exhibit excellent light output characteristics.

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Abstract

The present invention relates to a semiconductor light-emitting element comprising a light-emitting region separation trench and a contact hole structure. A semiconductor light-emitting element, according to the present invention, can widen an effective light-emitting area by evenly dispersing a current flowing through a semiconductor layer. In addition, according to the separation of each light-emitting region by a light-emitting region separation trench, an effect can be obtained such that individual elements are connected in parallel, and the improvement of optical efficiency can also be expected.

Description

발광 영역 분리 트렌치를 갖는 전류 분산 효과가 우수한 고휘도 반도체 발광소자High brightness semiconductor light emitting device with excellent current dispersion effect with light emitting region isolation trench
본 발명은 발광 영역 분리 트렌치 및 컨택홀 구조를 포함하여 우수한 전류 분산 효과를 나타내면서, 휘도 특성을 향상시킨 반도체 발광소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device having improved luminance characteristics, including a light emitting region isolation trench and a contact hole structure.
종래의 반도체 발광소자에는 예를 들어, GaN계 질화물 반도체 발광소자를 들 수 있고, 이 GaN계 질화물 반도체 발광소자는 그 응용 분야에 있어서 청색 또는 녹색 LED의 발광소자, MESFET과 HEMT 등의 고속 스위칭 소자, 고출력 소자 등에 응용되고 있다.A conventional semiconductor light emitting device is, for example, a GaN nitride semiconductor light emitting device, which is a high-speed switching device such as a blue or green LED light emitting device, MESFET and HEMT in the application field And high output devices.
도 1은 일반적인 질화물계 반도체 발광소자를 개략적으로 나타낸 것이다.1 schematically shows a general nitride-based semiconductor light emitting device.
도 1을 참조하면, 질화물계 반도체 발광소자는 성장 기판(11)로부터 형성된다. 보다 구체적으로, 질화물계 발광소자는, n형 질화물 반도체층(12), 활성층(13) 및 p형 질화물 반도체층(14)을 포함한다.Referring to FIG. 1, a nitride semiconductor light emitting device is formed from a growth substrate 11. More specifically, the nitride based light emitting device includes an n-type nitride semiconductor layer 12, an active layer 13, and a p-type nitride semiconductor layer 14.
그리고, n형 질화물 반도체층(12)에 전자를 주입하기 위하여, n형 질화물 반도체층(12)에 전기적으로 연결되는 n측 전극 패드(15)가 형성된다. 또한, p형 질화물 반도체층(14)에 정공을 주입하기 위하여, p형 질화물 반도체층(14)에 전기적으로 연결되는 p측 전극 패드(16)가 형성된다.In order to inject electrons into the n-type nitride semiconductor layer 12, an n-side electrode pad 15 electrically connected to the n-type nitride semiconductor layer 12 is formed. In addition, in order to inject holes into the p-type nitride semiconductor layer 14, a p-side electrode pad 16 electrically connected to the p-type nitride semiconductor layer 14 is formed.
한편, p형 질화물 반도체층은 높은 비저항을 갖는다. 따라서, p형 질화물 반도체층 내에서 전류가 고르게 분산되지 못하고, p측 전극 패드가 형성된 부분에 전류가 집중된다. On the other hand, the p-type nitride semiconductor layer has a high specific resistance. Therefore, the current is not evenly distributed in the p-type nitride semiconductor layer, and the current is concentrated in the portion where the p-side electrode pad is formed.
또한, 전류는 반도체층들을 통해 흘러서 n측 전극 패드로 빠져나간다. 이에 따라, n형 질화물 반도체층에서 n측 전극 패드가 형성된 부분에 전류가 집중되며, 반도체 발광소자의 모서리를 통해 전류가 집중적으로 흐르는 문제점이 발생된다. 상기와 같은 전류의 집중은 발광영역의 감소로 이어지고, 결과적으로 발광 효율을 저하시킨다. In addition, current flows through the semiconductor layers and exits to the n-side electrode pad. As a result, current is concentrated in a portion where the n-side electrode pad is formed in the n-type nitride semiconductor layer, and current flows intensively through the edge of the semiconductor light emitting device. Such concentration of current leads to a reduction of the light emitting area, and consequently lowers the light emitting efficiency.
특히, 2개의 전극이 발광구조의 상면에 거의 수평으로 배열되는 플래너(planar) 구조 발광소자는, 수직(vertical) 구조 발광소자에 비해 전류흐름이 전체 발광영역에 균일하게 분포하지 못하므로, 발광에 가담하는 유효면적이 크지 못하다는 문제가 있다.In particular, the planar structure light emitting device in which two electrodes are arranged almost horizontally on the upper surface of the light emitting structure has a uniform current flow in the entire light emitting area as compared to the vertical structure light emitting device. There is a problem that the effective area to join is not large.
한편, 조명용 발광소자와 같이 고출력을 위해서, 발광소자는 점차 약 1㎟ 이상으로 대면적화 되는 추세에 있다. 하지만, 발광소자가 대면적화 될수록, 전체 면적에서 균일한 전류 분포를 실현하는 것은 보다 어려운 문제이다. 이와 같이, 대면적화에 따른 전류분산 문제는 반도체 발광소자에서 중요한 기술적 과제로 인식되고 있다.On the other hand, for high output, such as a light emitting device for lighting, the light emitting device is gradually increasing in size to about 1 mm 2 or more. However, as the light emitting device becomes larger in area, it is more difficult to realize a uniform current distribution in the entire area. As such, the problem of current dispersion due to the large area has been recognized as an important technical problem in semiconductor light emitting devices.
종래 전류밀도를 향상시키고 면적효율성을 향상시키기 위하여, 다양한 p측 전극과 n측 전극의 형태과 배열을 개선하는 방향으로 연구되어 왔다. 그 예로, 미국특허 제6,486,499호에서는 n측 전극과 p측 전극이 서로 일정한 간격을 갖도록 연장되어 맞물린 다수의 전극지(finger)를 포함하는 것을 개시하고 있다. 이러한 전극 구조를 통하여 추가적인 전류 경로를 제공하고, 넓은 유효발광면적을 확보하며 균일한 전류 흐름을 형성하고자 하였다. In order to improve current density and area efficiency in the related art, research has been conducted to improve the shape and arrangement of various p-side electrodes and n-side electrodes. For example, US Pat. No. 6,486,499 discloses that the n-side electrode and the p-side electrode include a plurality of electrode fingers that extend and engage with each other at regular intervals. Through this electrode structure, it was intended to provide an additional current path, secure a large effective emission area, and form a uniform current flow.
그러나 이러한 전극 구조에서도 p측 전극 부근의 p형 질화물 반도체층에서 전류밀도가 증가함에 따라 출력효율이 저하되고, 전류 분산 효율에 한계가 있었다. However, even in such an electrode structure, as the current density increases in the p-type nitride semiconductor layer near the p-side electrode, the output efficiency decreases, and there is a limit in the current dispersion efficiency.
따라서 반도체층들을 통하여 흐르는 전류를 고르게 분산시킬 수 있는 반도체 발광소자의 개발이 지속적으로 요구되는 실정이다. Therefore, the development of a semiconductor light emitting device capable of evenly distributing the current flowing through the semiconductor layers is constantly required.
이에 본 발명자들은 우수한 전류 분산 효과를 나타낼 수 있는 구조의 반도체 발광소자를 개발하고자 연구, 노력한 결과, 제1 반도체층을 노출시키도록 형성된 컨택홀 내부 및 제2 반도체층 상부에 노출된 제1 반도체층을 전기적으로 연결하는 제1 연장 전극을 형성하고, 발광 영역을 복수로 분리할 수 있는 트렌치를 형성하며, 상기 제2 반도체층과 제1 연장 전극 사이, 상기 컨택홀의 측벽과 제1 연장 전극 사이 및 상기 트렌치의 표면과 제1 연장 전극 사이에 절연층을 형성하여 복수의 발광 영역을 갖는 반도체 발광 소자를 구성하면 전류 분산을 극대화하여 휘도를 향상시킬 수 있음을 발견함으로써 본 발명을 완성하게 되었다. Accordingly, the present inventors have conducted research and efforts to develop a semiconductor light emitting device having a structure capable of exhibiting an excellent current dispersion effect, and as a result, the first semiconductor layer exposed inside the contact hole and the upper portion of the second semiconductor layer formed to expose the first semiconductor layer. A first extension electrode that electrically connects the second electrode, a trench that can separate a plurality of light emitting regions, a gap between the second semiconductor layer and the first extension electrode, between the sidewall of the contact hole and the first extension electrode; The present invention has been completed by discovering that an insulating layer is formed between the surface of the trench and the first extension electrode to form a semiconductor light emitting device having a plurality of light emitting regions, thereby maximizing current dispersion to improve luminance.
따라서 본 발명의 목적은 우수한 전류 분산 효과를 나타내는 전극 구조 및 발광 영역 분리용 트렌치를 가지는 반도체 발광소자를 제공하는데 있다. Accordingly, an object of the present invention is to provide a semiconductor light emitting device having an electrode structure and a trench for separating a light emitting region, which exhibit excellent current dispersion effects.
이와 같은 목적을 달성하기 위한 본 발명의 반도체 발광소자는 제1 반도체층, 활성층 및 제2 반도체층을 포함하고, 전류 확산용 컨택홀 및 트렌치를 포함하는 것을 특징으로 한다. The semiconductor light emitting device of the present invention for achieving the above object comprises a first semiconductor layer, an active layer and a second semiconductor layer, it characterized in that it comprises a contact hole and trench for current diffusion.
또한, 본 발명의 반도체 발광소자는 상기 트렌치에 의하여 발광 영역이 복수로 분리되는 것을 특징으로 한다. In addition, the semiconductor light emitting device of the present invention is characterized in that a plurality of light emitting regions are separated by the trench.
또한, 본 발명의 반도체 발광소자는 상기 전류 확산용 컨택홀이 상기 제1 반도체층을 노출시키도록 형성되고, 상기 전류 확산용 컨택홀에 의하여 노출된 제1 반도체층을 전기적으로 연결하는 제1 연장 전극 및 상기 제2 반도체층과 전기적으로 연결된 제2 연장 전극을 포함하는 것을 특징으로 한다. In addition, the semiconductor light emitting device of the present invention is formed such that the current diffusion contact hole exposes the first semiconductor layer, and a first extension electrically connecting the first semiconductor layer exposed by the current diffusion contact hole. And an second extension electrode electrically connected to the electrode and the second semiconductor layer.
또한, 본 발명의 반도체 발광소자는 상기 제1 연장 전극과, 상기 활성층, 제2 반도체층 또는 트렌치 영역간을 전기적으로 절연하고, 제2 연장전극과 트렌치 영역간을 전기적으로 절연하는 절연층을 포함하며, 상기 절연층은 상기 제2 반도체층과 제1 연장 전극 사이, 상기 전류 확산용 컨택홀의 측벽과 제1 연장 전극 사이 및 상기 트렌치의 표면과 제1 연장 전극 사이에 형성되는 것을 특징으로 한다. In addition, the semiconductor light emitting device of the present invention includes an insulating layer electrically insulating the first extension electrode and the active layer, the second semiconductor layer or the trench region, and electrically insulating the second extension electrode and the trench region. The insulating layer may be formed between the second semiconductor layer and the first extension electrode, between the sidewall of the current diffusion contact hole and the first extension electrode, and between the surface of the trench and the first extension electrode.
본 발명의 반도체 발광소자는 반도체층을 통하여 흐르는 전류를 고르게 분산하여 유효 발광 면적을 넓힐 수 있다. The semiconductor light emitting device of the present invention can spread the current flowing through the semiconductor layer evenly to increase the effective light emitting area.
또한 발광 영역 분리용 트렌치에 의하여 각 발광 영역이 분리됨에 따라 개별 소자가 병렬 연결된 것과 같은 효과를 얻을 수 있으며, 광효율의 향상도 기대할 수 있다. In addition, as the respective light emitting regions are separated by the light emitting region isolation trenches, the same effects as those of individual elements connected in parallel can be obtained, and the light efficiency can be improved.
도 1은 종래의 반도체 발광소자의 단면을 도시한 단면도이다. 1 is a cross-sectional view showing a cross section of a conventional semiconductor light emitting device.
도 2는 본 발명의 일 실시예에 따른 반도체 발광소자의 평면도이다. 2 is a plan view of a semiconductor light emitting device according to an embodiment of the present invention.
도 3은 도 2의 절취선 A-A에서 얻어진 단면도이다. 3 is a cross-sectional view taken along the line A-A of FIG. 2.
도 4는 도 2의 절취선 B-B에서 얻어진 단면도이다. 4 is a cross-sectional view taken along the line B-B of FIG. 2.
도 5는 본 발명의 비교예에 따른 반도체 발광소자의 평면도이다. 5 is a plan view of a semiconductor light emitting device according to a comparative example of the present invention.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 따른 반도체 발광소자에 관하여 상세히 설명하면 다음과 같다. Hereinafter, a semiconductor light emitting device according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
하기 실시예에서 제1 반도체층은 n형 질화물층, 제2 반도체층은 p형 질화물층, 제1 연장 전극은 n측 연장 전극, 제2 연장 전극은 p측 연장 전극, 제1 전극 패드는 n측 전극 패드, 제2 전극 패드는 p측 전극 패드로 나타난다. In the following example, the first semiconductor layer is an n-type nitride layer, the second semiconductor layer is a p-type nitride layer, the first extension electrode is an n-side extension electrode, the second extension electrode is a p-side extension electrode, and the first electrode pad is n The side electrode pads and the second electrode pads are referred to as p-side electrode pads.
도 2는 본 발명의 제1 실시예에 따른 수평형 반도체 발광소자의 평면도이다. 2 is a plan view of a horizontal semiconductor light emitting device according to a first embodiment of the present invention.
도 2에서 도시된 바와 같이, 본 발명에 따른 발광소자는 p형 질화물층 및 활성층을 관통하여 발광 영역을 복수의 영역으로 분리시키는 발광 영역 분리용 트렌치(120)를 포함한다. As shown in FIG. 2, the light emitting device according to the present invention includes a light emitting region isolation trench 120 that penetrates the p-type nitride layer and the active layer to separate the light emitting region into a plurality of regions.
또한, 상기의 발광 영역 분리용 트렌치(120)와 함께, p형 질화물층 및 활성층을 관통하여 상기 n형 질화물층을 노출시키도록 형성된 컨택홀(110)을 더 포함할 수 있다. In addition, the trench 120 may further include a contact hole 110 formed to expose the n-type nitride layer through the p-type nitride layer and the active layer.
또한, 상기 컨택홀 내부, p형 질화물층 및 발광 영역 분리용 트렌치(120) 상부에, 컨택홀(110)에 의하여 노출된 n형 질화물층을 전기적으로 연결하는 n측 연장 전극(111)을 포함한다. 상기 발광 영역 분리용 트렌치(120)는 상기 n측 연장 전극(111)의 수직 방향으로 형성될 수 있다. 상기 n측 연장 전극(111)은 n측 전극 패드(112)에 전기적으로 연결되며, 컨택홀(110)은 하나의 n측 연장 전극(111) 내 2개 이상 포함될 수 있다. 상기 2개 이상의 컨택홀(110)은 서로 떨어져 규칙적으로 형성될 수 있으나, 형성되는 위치가 특별히 한정되지 아니하고, 일직선 상이 아닌 다양한 형태로 배열될 수 있다. In addition, an n-side extension electrode 111 electrically connecting the n-type nitride layer exposed by the contact hole 110 to the inside of the contact hole, the p-type nitride layer and the light emitting region isolation trench 120 is included. do. The emission region isolation trench 120 may be formed in a vertical direction of the n-side extension electrode 111. The n-side extension electrode 111 may be electrically connected to the n-side electrode pad 112, and two or more contact holes 110 may be included in one n-side extension electrode 111. The two or more contact holes 110 may be regularly spaced apart from each other, but the position at which the two or more contact holes 110 are formed is not particularly limited and may be arranged in various forms rather than in a straight line.
그리고 p측 연장 전극(121)이 p형 질화물층 상부 중 일부에 위치한 p측 전극 패드(122)와 전기적으로 연결되어 p측 전극부를 형성한다. 상기 n측 연장 전극(111)은 상기 p측 연장 전극(121)과 전기적으로 절연되도록 형성된다. The p-side extension electrode 121 is electrically connected to the p-side electrode pad 122 positioned on a part of the upper portion of the p-type nitride layer to form the p-side electrode part. The n-side extension electrode 111 is formed to be electrically insulated from the p-side extension electrode 121.
보다 구체적인 구성을 설명하기 위하여 도 3 및 4에서 도 2의 절취선 A-A, B-B를 따라 보여지는 단면도를 나타내었다. 3 and 4 illustrate cross-sectional views taken along the cutting lines A-A and B-B of FIG. 2 to explain more specific configurations.
도 3에서 도시된 바와 같이, 본 발명의 반도체 발광소자는 기판(130)의 상부 방향으로 버퍼층(140), n형 질화물층(150), 활성층(160), p형 질화물층(170)이 적층되어 형성된다. As shown in FIG. 3, in the semiconductor light emitting device of the present invention, a buffer layer 140, an n-type nitride layer 150, an active layer 160, and a p-type nitride layer 170 are stacked in an upper direction of the substrate 130. It is formed.
상기 기판(130)은 사파이어를 비롯하여, SiC, Si, GaN, ZnO, GaAs, GaP, LiAl2O3, BN 또는 AlN 등의 화합물로 이루어질 수 있다. 또한, 상기 버퍼층(140)은 기판(130)과 n형 질화물층(150) 사이의 격자 부정합을 해소하기 위해 선택적으로 형성될 수 있고, 예컨대 AlN 또는 GaN으로 형성할 수 있다.The substrate 130 may be made of a compound such as sapphire, SiC, Si, GaN, ZnO, GaAs, GaP, LiAl 2 O 3 , BN or AlN. In addition, the buffer layer 140 may be selectively formed to solve the lattice mismatch between the substrate 130 and the n-type nitride layer 150, for example, may be formed of AlN or GaN.
n형 질화물층(150)은 기판(130) 또는 버퍼층(140)의 상부면에 형성되고, n형 도판트가 도핑되어 있는 질화물로 형성된다. 상기 n형 도판트로는 실리콘(Si), 게르마늄(Ge), 주석(Sn) 등이 사용될 수 있다. 여기서, n형 질화물층(150)은 Si을 도핑한 n형 AlGaN 또는 언도우프 AlGaN으로 이루어진 제 1 층, 및 언도우프 또는 Si을 도핑한 n형 GaN로 이루어진 제 2 층이 번갈아가며 형성된 적층 구조일 수 있다. 물론, n형 질화물층(150)은 단층의 n형 질화물층으로 성장시키는 것도 가능하나, 제 1 층과 제 2 층의 적층 구조로 형성하여 크랙이 없는 결정성이 좋은 캐리어 제한층으로 작용할 수 있다.The n-type nitride layer 150 is formed on the upper surface of the substrate 130 or the buffer layer 140, and is formed of nitride to which the n-type dopant is doped. As the n-type dopant, silicon (Si), germanium (Ge), tin (Sn), or the like may be used. Here, the n-type nitride layer 150 is a laminated structure in which a first layer made of n-type AlGaN or undoped AlGaN doped with Si and a second layer made of n-type GaN doped with undoped or Si are formed. Can be. Of course, the n-type nitride layer 150 may be grown as a single n-type nitride layer, but may be formed as a laminated structure of the first layer and the second layer to act as a carrier limiting layer having good crystallinity without cracking. .
활성층(160)은 n형 질화물층(150)과 p형 질화물층(170) 사이에서 단일양자우물구조 또는 다중양자우물구조로　이루어질 수 있으며, n형 질화물층(150)을 통하여 흐르는 전자와, p형 질화물층(170)을 통하여 흐르는 정공이 재결합(re-combination)되면서, 광이 발생된다. 여기서, 활성층(160)은 다중양자우물구조로서, 양자장벽층과 양자우물층은 각각 AlxGayInzN(이 때, x+y+z=1, 0≤x≤1, 0≤y≤1, 0≤z≤1)으로 이루어질 수 있다. 이러한 양자장벽층과 양자우물층이 반복되어 형성된 구조의 활성층(160)은 발생하는 응력과 변형에 의한 자발적인 분극을 억제할 수 있다.The active layer 160 may be formed of a single quantum well structure or a multi-quantum well structure between the n-type nitride layer 150 and the p-type nitride layer 170, and electrons flowing through the n-type nitride layer 150, p As holes flowing through the type nitride layer 170 are re-combined, light is generated. Here, the active layer 160 has a multi-quantum well structure, and the quantum barrier layer and the quantum well layer are each Al x Ga y In z N (where x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≤ 1, 0 ≤ z ≤ 1). The active layer 160 having a structure in which the quantum barrier layer and the quantum well layer are formed repeatedly may suppress spontaneous polarization due to stress and deformation generated.
p형 질화물층(170)은 p형 도판트가 도핑되어 있는 질화물로 형성된다. 상기 p형 도판트로는 마그네슘(Mg), 아연(Zn) 또는 카드뮴(Cd) 등이 사용될 수 있다. 여기서, p형 질화물층은 Mg을 도핑한 p형 AlGaN 또는 언도우프 AlGaN으로 이루어진 제 1 층, 및 언도우프 또는 Mg을 도핑한 p형 GaN로 이루어진 제 2 층을 번갈아가며 적층한 구조로 형성될 수 있다. 또한, p형 질화물층(170)은 n형 질화물층(150)과 마찬가지로 단층의 p형 질화물층으로 성장시키는 것도 가능하나, 적층 구조로 형성하여 크랙이 없는 결정성이 좋은 캐리어 제한층으로 작용할 수 있다.The p-type nitride layer 170 is formed of a nitride doped with a p-type dopant. As the p-type dopant, magnesium (Mg), zinc (Zn) or cadmium (Cd) may be used. Herein, the p-type nitride layer may be formed by alternately stacking a first layer made of p-type AlGaN or undoped AlGaN doped with Mg, and a second layer made of p-type GaN doped with undoped or Mg. have. In addition, the p-type nitride layer 170 may be grown as a single-layer p-type nitride layer similarly to the n-type nitride layer 150, but may be formed as a laminated structure to act as a carrier-limiting layer having good crystallinity without cracks. have.
상기 p형 질화물층(170) 및 활성층(160)을 관통하여 상기 n형 질화물층(150)을 노출시키도록 컨택홀(110)이 형성된다. 또한 상기 p형 질화물층(170) 및 활성층(160)을 식각하여 발광 영역 분리용 트렌치(120)가 형성된다. The contact hole 110 is formed through the p-type nitride layer 170 and the active layer 160 to expose the n-type nitride layer 150. In addition, the p-type nitride layer 170 and the active layer 160 are etched to form a light emitting region isolation trench 120.
상기 컨택홀(110) 및 트렌치(120)는 포토레지스트 등을 통하여 형성될 수 있는데, 패턴 마스크로 포토 레지스트를 이용하는 경우 포토 리소그래피(photo-lithography), 전자빔 리소그래피(e-beam lithography), 이온빔 리소그래피(Ion-beam Lithography), 극자외선 리소그래피(Extreme Ultraviolet Lithography), 근접 X선 리소그라피(Proximity X-ray Lithography) 또는 나노 임프린트 리소그래피(nano imprint lithography) 등의 방법을 이용하여 형성할 수 있고, 또한 이와 같은 방법은 건식(Dry) 또는 습식(Wet) 식각(Etching)을 이용할 수 있다.The contact hole 110 and the trench 120 may be formed through a photoresist or the like. When using a photoresist as a pattern mask, photo-lithography, e-beam lithography, and ion beam lithography Ion-beam Lithography, Extreme Ultraviolet Lithography, Proximity X-ray Lithography, or Nano imprint lithography, etc. The dry or wet etching may be used.
상기 컨택홀(110)에 의하여 노출된 n형 질화물층(150) 상에는 n-컨택층(151)이 더 포함될 수 있다. 상기 n-컨택층(151)은 n형 질화물(150)에 오믹 컨택되어 접촉 저항을 낮춘다. 상기 n-컨택층(151)은 투명 전도성 산화물로 이루어질 수 있으며, 그 재질은 In, Sn, Al, Zn, Ga 등의 원소를 포함하며, 예컨대 ITO, CIO, ZnO, NiO, In2O3 중 어느 하나로 형성될 수 있다. An n-contact layer 151 may be further included on the n-type nitride layer 150 exposed by the contact hole 110. The n-contact layer 151 is ohmic contacted to the n-type nitride 150 to lower the contact resistance. The n-contact layer 151 may be made of a transparent conductive oxide, and the material may include elements such as In, Sn, Al, Zn, Ga, and the like, for example, of ITO, CIO, ZnO, NiO, and In 2 O 3 . It can be formed of either.
또한, 상기 컨택홀(110)의 측벽에는 절연층(180)이 형성되어, 컨택홀(110)의 측벽과 n측 연장 전극(111)을 이격시키며, 상기 컨택홀(110)에 의하여 노출되는 n형 질화물층의 일부는 노출되도록 한다. 그리고, 상기 절연층(180)은 p형 질화물(170)의 상부로 연장되어 p형 질화물층(170)과 n측 연장 전극(111)을 이격시키며, 트렌치(120) 영역의 상부로 연장되어 트렌치(120) 영역과 n측 연장 전극(111)을 이격시킨다. 상기 절연층(180)은 실리콘 산화물 또는 실리콘 질화물로 형성될 수 있으며, PECVD(Plasma Enhanced Chemical Vapor Deposition) 방법, 스퍼터링 방법, MOCVD 방법 또는 전자빔 증착(e-beam evaporation) 방법으로 형성될 수 있다.In addition, an insulating layer 180 is formed on the sidewalls of the contact holes 110 to separate the sidewalls of the contact holes 110 from the n-side extension electrode 111 and are exposed by the contact holes 110. Part of the form nitride layer is exposed. The insulating layer 180 extends over the p-type nitride 170 to separate the p-type nitride layer 170 from the n-side extension electrode 111, and extends over the trench 120 to form a trench. The area 120 is spaced apart from the n-side extension electrode 111. The insulating layer 180 may be formed of silicon oxide or silicon nitride, and may be formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, a MOCVD method, or an e-beam evaporation method.
상기 n측 연장 전극(111)은 컨택홀(110) 내부, p형 질화물층(170) 상부 및 트렌치(120) 상부에 형성되어, 컨택홀(110)에 의하여 노출된 n형 질화물층을 전기적으로 연결하는 역할을 하며, 금속, 합금 도는 금속 산화물 등 전기적 연결이 가능한 물질로 이루어질 수 있다. The n-side extension electrode 111 is formed in the contact hole 110, on the p-type nitride layer 170, and on the trench 120 to electrically n-type nitride layer exposed by the contact hole 110. It serves to connect, it may be made of a material capable of electrical connection, such as metal, alloy or metal oxide.
또한 상기 n측 연장 전극(111)은 절연층(180) 상에 존재하는 n측 전극 패드(112)와 전기적으로 연결된다. In addition, the n-side extension electrode 111 is electrically connected to the n-side electrode pad 112 present on the insulating layer 180.
상기 n측 연장 전극(111)과 이격되어 형성된 p측 연장 전극(121)의 하부에는 p-컨택층(171)이 형성될 수 있으며, 상기 p-컨택층(171)은 p형 질화물(170)에 오믹 컨택되어 접촉 저항을 낮춘다. 상기 p-컨택층(171)은 투명 전도성 산화물로 이루어질 수 있으며, 그 재질은 In, Sn, Al, Zn, Ga 등의 원소를 포함하며, 예컨대 ITO, CIO, ZnO, NiO, In2O3 중 어느 하나로 형성될 수 있다. A p-contact layer 171 may be formed below the p-side extension electrode 121 formed to be spaced apart from the n-side extension electrode 111, and the p-contact layer 171 may be a p-type nitride 170. Ohmic contact reduces contact resistance. The p-contact layer 171 may be made of a transparent conductive oxide, and the material may include elements such as In, Sn, Al, Zn, Ga, and the like, for example, of ITO, CIO, ZnO, NiO, and In 2 O 3 . It can be formed of either.
도 4에서 도시된 바와 같이, p측 연장 전극(121)의 하부에는 기판(130)의 상부 방향으로 버퍼층(140), n형 질화물층(150), 활성층(160), p형 질화물층(170) 및 p-컨택층(171)이 차례로 형성되고, 활성층(160) 및 p형 질화물층(170)이 식각된 트렌치(120) 영역도 형성되며, 상기 p측 연장 전극(121)은 p측 전극 패드(122)와 전기적으로 연결된다. 또한, 상기 트렌치(120)는 절연층(180)에 의하여 상기 p측 연장 전극(121)과 전기적으로 절연된다. 상기 p-컨택층(171)을 트렌치(120)의 측벽 및 저면과 이격시키는 절연층(180)은 상기 도 3에서 나타난 바와 같이 n측 연장 전극(111)과 컨택홀(110)의 측벽 및 p형 질화물층(170)을 이격시키는 절연층(180)과 연결되어 형성되거나 또는 분리되어 형성될 수 있다. As shown in FIG. 4, the buffer layer 140, the n-type nitride layer 150, the active layer 160, and the p-type nitride layer 170 are disposed below the p-side extension electrode 121 in the upper direction of the substrate 130. ) And p-contact layer 171 are sequentially formed, and a trench 120 region where the active layer 160 and the p-type nitride layer 170 are etched is also formed, and the p-side extension electrode 121 is a p-side electrode. It is electrically connected to the pad 122. In addition, the trench 120 is electrically insulated from the p-side extension electrode 121 by the insulating layer 180. As shown in FIG. 3, the insulating layer 180 which separates the p-contact layer 171 from the sidewalls and the bottom surface of the trench 120 includes the sidewalls of the n-side extension electrode 111 and the contact hole 110 and p. The nitride layer 170 may be formed to be connected to or separated from the insulating layer 180 spaced apart from each other.
한편 상기 도 2의 평면도에서 보는 바와 같이, 상기 컨택홀(110)의 단면은 원으로 형성될 수 있으나, 이에 한정되지 아니하고, 삼각형, 사각형 기타 다각형의 형태로 형성될 수 있다. On the other hand, as shown in the plan view of Figure 2, the cross section of the contact hole 110 may be formed as a circle, but is not limited to this, it may be formed in the form of a triangle, a square or other polygons.
또한 상기 컨택홀(110)의 단면의 직경은 1 ~ 200 ㎛, 바람직하게는 5 ~ 150 ㎛ 의 범위로 형성될 수 있으며, 2 이상의 컨택홀이 형성되는 경우 그 단면의 크기는 모두 같거나 다를 수 있다. In addition, the diameter of the cross section of the contact hole 110 may be formed in the range of 1 to 200 μm, preferably 5 to 150 μm, and when two or more contact holes are formed, the size of the cross sections may be all the same or different. have.
상기 하나의 n측 연장 전극(111) 내 이웃하는 컨택홀(110) 간의 거리는 전체 발광 소자의 단면적에 따라 달라질 수 있으나, 바람직하게는 상기 하나의 n측 연장 전극 내 이웃하는 컨택홀(110) 간의 거리가 10 ~ 500 ㎛, 더욱 바람직하게는 50 ~ 400 ㎛ 범위 내에 있도록 조절한다. The distance between the neighboring contact holes 110 in the one n-side extension electrode 111 may vary depending on the cross-sectional area of the entire light emitting device, but preferably between the neighboring contact holes 110 in the one n-side extension electrode. The distance is adjusted to be within the range of 10 to 500 μm, more preferably 50 to 400 μm.
한편, 상기 발광 영역 분리용 트렌치(120)의 폭은 0.5 ~ 20 ㎛, 바람직하게는 3 ~ 10 ㎛ 범위로 형성되는 것이 바람직하다. On the other hand, the width of the light emitting region separation trench 120 is preferably formed in the range of 0.5 to 20 ㎛, preferably 3 to 10 ㎛.
또한 상기 n측 연장 전극(111)의 폭은 1 ~ 100 ㎛, 바람직하게는 5 ~ 50 ㎛ 범위 내로 조절할 수 있으나, 이에 제한되지 아니한다. 특히, 상기 n측 연장 전극(111)의 폭이 일정하게 유지되면서 형성될 수 있으나, 상기 n측 전극 패드(112)로부터 거리가 멀어질수록 컨택홀을 연결하는 n측 연장 전극(111)의 폭이 감소할 수 있으며, 또한 그 반대로 상기 하나의 n측 연장 전극 내에서 n측 전극 패드(112)로부터 거리가 멀어질수록 컨택홀을 연결하는 n측 연장 전극(111)의 폭이 커질 수 있다. In addition, the width of the n-side extension electrode 111 may be adjusted within the range of 1 to 100 μm, preferably 5 to 50 μm, but is not limited thereto. In particular, the width of the n-side extension electrode 111 may be maintained while being constant, but as the distance from the n-side electrode pad 112 increases, the width of the n-side extension electrode 111 connecting the contact holes is increased. The width of the n-side extension electrode 111 connecting the contact hole may increase as the distance from the n-side electrode pad 112 increases in the one n-side extension electrode.
상기 n측 전극 패드(112)에는 하나 또는 2 이상의 n측 연장 전극(111)이 전기적으로 연결될 수 있으며, 이 때 각각의 n측 연장 전극에 하나 이상의 컨택홀이 형성될 수 있다. 특히 상기 n측 연장 전극(111)은 절곡점이 없는 직선 형태뿐 만 아니라 하나 이상의 절곡점을 갖도록 형성될 수 있다. One or two or more n-side extension electrodes 111 may be electrically connected to the n-side electrode pad 112, and at least one contact hole may be formed in each of the n-side extension electrodes. In particular, the n-side extension electrode 111 may be formed to have one or more bending points as well as a straight shape having no bending points.
그리고 상기 p측 전극 패드(122)에도 역시 하나 또는 2 이상의 p측 연장 전극(121)이 전기적으로 연결될 수 있다. 상기 2 이상의 p측 연장 전극(121)이 형성되는 경우 p측 전극 패드(122)에 연결되지 않는 반대편의 끝단은 각각 이격되어 형성되는 것이 일반적이나, 끝단이 서로 연결되어 폐도형을 형성할 수 있다. 상기와 같이 p측 연장 전극(121)의 끝단이 서로 연결되더라도 n측 연장 전극(111)과는 절연층에 의하여 이격될 수 있음은 당업자에게 자명한 사실이다. One or more p-side extension electrodes 121 may also be electrically connected to the p-side electrode pad 122. When the two or more p-side extension electrodes 121 are formed, opposite ends that are not connected to the p-side electrode pad 122 are generally formed to be spaced apart from each other, but the ends may be connected to each other to form a closed figure. . As described above, even if the ends of the p-side extension electrode 121 are connected to each other, the n-side extension electrode 111 may be spaced apart by an insulating layer.
상기 본 발명의 반도체 발광소자의 발광 영역은 상기 트렌치(120)에 의하여 복수로 나누어질 수 있으며, 도 2에서 보는 바와 같이, 트렌치(120)가 2개 형성되는 경우 발광 영역은 3개의 영역으로 분리된다. 상기 복수의 컨택홀(110) 사이에 트렌치(120) 영역이 형성됨에 따라, 각 발광 영역은 하나 이상의 컨택홀(110)을 구비하게 된다. 하나의 소자 내에서 상기 트렌치에 의하여 분리 형성되는 발광 영역의 수는 크게 한정되지 않으나, 3 ~ 5개의 영역으로 분리되는 것이 바람직하며, 발광 영역 각각의 면적이 균일해 지도록 등간격으로 형성되는 것이 보다 바람직하다. The light emitting regions of the semiconductor light emitting device of the present invention may be divided into a plurality of by the trench 120. As shown in FIG. 2, when two trenches 120 are formed, the light emitting regions are divided into three regions. do. As the trench 120 regions are formed between the plurality of contact holes 110, each light emitting region may include one or more contact holes 110. The number of light emitting regions separated by the trench in one device is not particularly limited, but is preferably separated into 3 to 5 regions, and the light emitting regions are formed at equal intervals so that the areas of the light emitting regions are uniform. desirable.
상기 발광 영역이 분리됨에 따라, 각각의 발광 영역이 n측 연장 전극(111)과 p측 연장 전극(121)에 의하여 마치 개별 소자가 병렬 연결된 것과 같은 효과를 얻을 수 있고, 복수개의 컨택홀에 의한 전류 분산 효과를 기대할 수 있으며, 전류 밀도를 향상시켜 휘도를 높일 수 있다. As the light emitting regions are separated, the respective light emitting regions may have the same effect as if the individual elements are connected in parallel by the n-side extension electrode 111 and the p-side extension electrode 121, and the plurality of contact holes Current dispersion effect can be expected and brightness can be increased by improving current density.
이하, 본 발명의 하기 실시예를 통하여 본 발명의 반도체 발광소자에 대하여 보다 구체적으로 설명하기로 한다.Hereinafter, the semiconductor light emitting device of the present invention will be described in more detail with reference to the following examples.
실시예Example
도 2 내지 4와 같은 반도체 발광소자를 구성하기 위하여 사파이어 기판에 질화물 발광소자의 질화물층으로 GaN을 적용하였고, 연장 전극으로 일반적인 Au 기반 전극을 적용하여 발광소자를 얻었다. 2 to 4, GaN was applied as a nitride layer of a nitride light emitting device to a sapphire substrate, and a general Au-based electrode was applied as an extension electrode to obtain a light emitting device.
비교예Comparative example
사파이어 기판에 실시예와 동일한 질화물계 성분으로 적층하되, 도 5와 같은 평면도를 가지는 발광소자를 제조하였다. A light emitting device was manufactured by stacking the same nitride-based component as in Example on a sapphire substrate, but having a plan view as illustrated in FIG. 5.
상기 실시예 및 비교예의 발광소자에서의 발광 출력을 패키지 상태에서 120 mA의 동일 전류를 인가하여 측정하였으며, 그 결과를 하기 표 1 에 나타내었다. The light emission output of the light emitting devices of Examples and Comparative Examples was measured by applying the same current of 120 mA in a package state, and the results are shown in Table 1 below.
[표 1]TABLE 1
Figure PCTKR2013009208-appb-I000001
Figure PCTKR2013009208-appb-I000001
상기 표 1에서 보는 바와 같이, 실시예의 발광소자는 비교예에 비하여 약 3.1% 이상 광출력 특성이 개선된 바, 실시예의 발광소자는 우수한 광출력 특성을 나타낼 수 있음을 확인할 수 있었다. As shown in Table 1, the light emitting device of the embodiment was improved by about 3.1% or more light output compared to the comparative example, it was confirmed that the light emitting device of the embodiment can exhibit excellent light output characteristics.
이상에서는 본 발명의 실시예를 중심으로 설명하였으나, 이는 예시적인 것에 불과하며, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 기술자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호범위는 이하에 기재되는 특허청구범위에 의해서 판단되어야 할 것이다.Although the above description has been made with reference to the embodiments of the present invention, this is only an example, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention should be judged by the claims described below.

Claims (16)

  1. 제1 반도체층;A first semiconductor layer;
    상기 제1 반도체층 상에 형성되는 활성층;An active layer formed on the first semiconductor layer;
    상기 활성층 상에 형성되는 제2 반도체층; 및A second semiconductor layer formed on the active layer; And
    상기 제2 반도체층 및 활성층을 복수의 영역으로 분리하는 트렌치;를 포함하는 것을 특징으로 하는 반도체 발광소자.And a trench separating the second semiconductor layer and the active layer into a plurality of regions.
  2. 제1항에 있어서,The method of claim 1,
    상기 트렌치는 The trench
    상기 트렌치에 의하여 분리되는 복수의 영역 각각의 면적이 균일하도록 형성되는 것을 특징으로 하는 반도체 발광소자.And the area of each of the plurality of regions separated by the trench is formed to be uniform.
  3. 제1항에 있어서,The method of claim 1,
    상기 트렌치에 의하여 분리된 복수의 영역에, 상기 제1 반도체층을 노출시키도록 형성되는 전류 확산용 컨택홀;을 더 포함하는 것을 특징으로 하는 반도체 발광소자. And a current diffusion contact hole formed to expose the first semiconductor layer in the plurality of regions separated by the trench.
  4. 제3항에 있어서,The method of claim 3,
    상기 전류 확산용 컨택홀에 의하여 노출된 제1 반도체층을 전기적으로 연결하는 제1 연장 전극 및 A first extension electrode electrically connecting the first semiconductor layer exposed by the current diffusion contact hole;
    상기 제2 반도체층과 전기적으로 연결된 제2 연장 전극을 포함하는 것을 특징으로 하는 반도체 발광소자.And a second extension electrode electrically connected to the second semiconductor layer.
  5. 제4항에 있어서,The method of claim 4, wherein
    상기 제1 연장 전극과, 상기 활성층, 제2 반도체층 또는 트렌치 영역간을 전기적으로 절연하고, 제2 연장전극과 트렌치 영역간을 전기적으로 절연하는 절연층을 더 포함하는 것을 특징으로 하는 반도체 발광소자.And an insulating layer electrically insulating between the first extension electrode and the active layer, the second semiconductor layer or the trench region, and electrically insulating the second extension electrode and the trench region.
  6. 제5항에 있어서,The method of claim 5,
    상기 절연층은 상기 제2 반도체층과 제1 연장 전극 사이, 상기 전류 확산용 컨택홀의 측벽과 제1 연장 전극 사이 및 상기 트렌치의 표면과 제1 연장 전극 사이에 형성되는 것을 특징으로 하는 반도체 발광소자.And the insulating layer is formed between the second semiconductor layer and the first extension electrode, between the sidewall of the current spreading contact hole and the first extension electrode, and between the surface of the trench and the first extension electrode. .
  7. 제4항에 있어서,The method of claim 4, wherein
    상기 제1 연장 전극은 전류 확산용 컨택홀 내부, 제2 반도체층 및 트렌치 상부에 형성되는 것을 특징으로 하는 반도체 발광소자.And the first extension electrode is formed in the current diffusion contact hole, the second semiconductor layer, and the trench.
  8. 제4항에 있어서,The method of claim 4, wherein
    상기 전류 확산용 컨택홀은 제1 연장 전극 내 2개 이상 포함되는 것을 특징으로 하는 반도체 발광소자.And at least two contact diffusion holes for current spreading in the first extension electrode.
  9. 제4항에 있어서,The method of claim 4, wherein
    상기 제1 연장 전극과 전기적으로 연결된 제1 전극 패드 및 상기 제2 연장 전극과 전기적으로 연결된 제2 전극 패드를 더 포함하는 것을 특징으로 하는 반도체 발광소자.And a first electrode pad electrically connected to the first extension electrode, and a second electrode pad electrically connected to the second extension electrode.
  10. 제3항에 있어서,The method of claim 3,
    상기 전류 확산용 컨택홀의 단면의 직경은 1 ~ 200 ㎛ 범위에 있는 것을 특징으로 하는 반도체 발광소자.The diameter of the cross section of the current diffusion contact hole is in the range of 1 ~ 200 ㎛ semiconductor light emitting device.
  11. 제3항에 있어서,The method of claim 3,
    상기 전류 확산용 컨택홀의 단면은 원, 삼각형 또는 사각형 형태인 것을 특징으로 하는 반도체 발광소자.The cross section of the current diffusion contact hole is a semiconductor light emitting device, characterized in that the shape of a circle, triangle or square.
  12. 제1항에 있어서,The method of claim 1,
    상기 트렌치의 폭은 0.5 ~ 20 ㎛ 범위에 있는 것을 특징으로 하는 반도체 발광소자.The width of the trench is a semiconductor light emitting device, characterized in that in the range of 0.5 ~ 20 ㎛.
  13. 제1 반도체층;A first semiconductor layer;
    상기 제1 반도체층 상에 형성되는 활성층;An active layer formed on the first semiconductor layer;
    상기 활성층 상에 형성되는 제2 반도체층; A second semiconductor layer formed on the active layer;
    상기 제2 반도체층 및 활성층을 복수의 영역으로 분리하는 트렌치;A trench separating the second semiconductor layer and the active layer into a plurality of regions;
    상기 트렌치에 의하여 분리된 복수의 영역에, 상기 제1 반도체층을 노출시키도록 형성되는 전류 확산용 컨택홀; A current diffusion contact hole formed to expose the first semiconductor layer in the plurality of regions separated by the trench;
    상기 전류 확산용 컨택홀에 의하여 노출된 제1 반도체층을 전기적으로 연결하는 제1 연장 전극; 및A first extension electrode electrically connecting the first semiconductor layer exposed by the current spreading contact hole; And
    상기 제1 연장 전극과, 상기 활성층, 제2 반도체층 또는 트렌치 영역간을 전기적으로 절연하는 절연층;을 포함하는 것을 특징으로 하는 반도체 발광소자.And an insulating layer electrically insulating between the first extension electrode and the active layer, the second semiconductor layer, or the trench region.
  14. 제13항에 있어서,The method of claim 13,
    상기 절연층은 상기 제2 반도체층과 제1 연장 전극 사이, 상기 전류 확산용 컨택홀의 측벽과 제1 연장 전극 사이, 및 상기 트렌치의 표면과 제1 연장 전극 사이에 형성되는 것을 특징으로 하는 반도체 발광소자.Wherein the insulating layer is formed between the second semiconductor layer and the first extension electrode, between the sidewall of the current diffusion contact hole and the first extension electrode, and between the surface of the trench and the first extension electrode. device.
  15. 제13항에 있어서,The method of claim 13,
    상기 제1 연장 전극은 전류 확산용 컨택홀 내부, 제2 반도체층 및 트렌치 상부에 형성되는 것을 특징으로 하는 반도체 발광소자.And the first extension electrode is formed in the current diffusion contact hole, the second semiconductor layer, and the trench.
  16. 제13항에 있어서,The method of claim 13,
    상기 제2 반도체층과 전기적으로 연결된 제2 연장 전극;을 더 포함하고,And a second extension electrode electrically connected to the second semiconductor layer.
    상기 절연층은 상기 제2 연장전극과 트렌치 영역간을 전기적으로 절연하도록 형성되는 것을 특징으로 하는 반도체 발광소자. And the insulating layer is formed to electrically insulate the second extension electrode from the trench region.
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