WO2014054567A1 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
WO2014054567A1
WO2014054567A1 PCT/JP2013/076505 JP2013076505W WO2014054567A1 WO 2014054567 A1 WO2014054567 A1 WO 2014054567A1 JP 2013076505 W JP2013076505 W JP 2013076505W WO 2014054567 A1 WO2014054567 A1 WO 2014054567A1
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WO
WIPO (PCT)
Prior art keywords
element isolation
insulating film
forming
semiconductor device
etching
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PCT/JP2013/076505
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French (fr)
Japanese (ja)
Inventor
寛生 西
弘充 大嶋
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
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Publication of WO2014054567A1 publication Critical patent/WO2014054567A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • LSI large-scale integrated circuit
  • STI Shallow Trench Isolation
  • This STI means that, for example, a shallow trench called a shallow trench is formed on a silicon substrate, and this is filled with an element isolation insulating film made of an insulating material such as an oxide film, whereby an active region provided on the silicon substrate is formed.
  • This is a structure in which element isolation regions to be partitioned are provided.
  • Such STI has an advantage that it can be miniaturized without expanding in the horizontal direction, compared to LOCOS (Local Oxidation of Silicon), which is simple in process.
  • the word line and the dummy word line are formed in the STI structure, an etch rate difference is generated between the inner wall oxide film and the buried film, and the cross section of the groove opening on the silicon substrate is rectangular.
  • the STI inner wall oxide film located on the side surface becomes difficult to be etched, and the problem that the inner wall oxide film tends to remain on the side surface of the fin arises. This becomes more conspicuous as the inner wall oxide film is thicker.
  • the channel region is located above the top of the inner wall oxide film remaining on the side wall of the fin because the effect as the channel region is less likely to be exhibited in the portion where the inner wall oxide film remains on the side wall of the fin. Depends on the height of the silicon substrate formed.
  • FIGS. 9A to 9C and FIGS. 10A to 10D a method for forming a buried substrate type word line using a fin structure for forming a channel region of a transistor, which the present inventors have experimented Will be explained.
  • 9A and 10A are plan views showing a conventional semiconductor device.
  • FIGS. 9B and 10B are cross-sectional views taken along the line AA in FIGS. 9A and 10A, respectively.
  • FIGS. 9C, 10C, and 10D are FIGS.
  • FIG. 10B is a sectional view taken along line BB shown in FIGS. 9A and 10A, respectively.
  • an embedded word is formed on a silicon substrate 101 in which an element isolation region 102e having an STI line and space pattern is formed by embedding an element isolation insulating film 102e in a surface layer.
  • Line grooving As shown in FIG. 9A, the STI line and space pattern extends in the X ′ direction, and the trench of the buried word line extends in the Y direction intersecting the X ′ direction.
  • a silicon nitride film 103a is formed on the STI, and then a resist mask R having a line and space pattern along the word line planned line is formed thereon using a lithography technique.
  • the element isolation insulating film 102e in the element isolation region 102 is selectively etched, and Si (silicon substrate) in the active region 101a is hardly etched as much as possible. Etching is performed so as not to cut. As a result, the etching shape of the word groove 103b becomes almost rectangular as shown in the illustrated example.
  • the inner wall oxide film 102d in the element isolation region 2 tends to be left on the side wall of the Si substrate 112a. Then, as shown in FIG. 10A to FIG.
  • the word groove 103b is further etched to a predetermined depth, and as shown in FIG.
  • a saddle type fin portion 112 is formed so that the upper surface of the silicon substrate 101a protrudes to a position higher than the upper surface of the element isolation insulating film 102e.
  • etching is performed under the condition that the etching rate of the element isolation insulating film 102e is higher than the etching rate of the silicon substrate 1.
  • an etch rate difference occurs between the inner wall oxide film 102d of the STI and the element isolation insulating film 102e, and since Si is rectangular, the inner wall oxide film 102d is difficult to be etched.
  • the inner wall oxide film 102d on the side surface of Si cannot be completely removed during etching, and the remaining portion 102f of the inner wall oxide film is generated on the side surface of the saddle type fin portion 112.
  • the amount of the remaining portion 102f of the inner wall oxide film remaining is proportional to the film thickness of the inner wall oxide film 102d, and the remaining amount increases as the film thickness increases.
  • the remaining portion 102f of the inner wall oxide film is formed on the side surface of Si, the effect as a channel region in this portion is hardly exhibited, and there is a problem that the channel does not function as a transistor. Therefore, as shown in FIG. 10D, for the purpose of securing the channel region, it is necessary to dig deeper into the word groove 103b in the element isolation region 102 to increase the height of the fin.
  • the remaining film of the element isolation insulating film 102e remaining at the bottom of the element isolation region 102 becomes thin, and a leakage current is generated on the surface of the silicon substrate 101 located therebelow due to the parasitic MOS effect. There was a problem that it was easy to do.
  • the portion serves as a channel region, so that there is a problem that the possibility of occurrence of a leakage current is increased.
  • the present inventors have conducted intensive research, and in the process of manufacturing a semiconductor device having a three-dimensional structure, a saddle type fin portion and a buried word line are formed on a silicon substrate on which an STI structure is formed.
  • the knowledge that the inner wall oxide film formed on the side surface of the active region can be surely removed by side-etching the side surface of the active region exposed during the formation of the word groove portion when forming the word groove for forming. did.
  • the height of each fin portion can be ensured and the thickness of the element isolation insulating film remaining at the bottom of the element isolation groove can be secured without digging a large STI structure (element isolation insulating film).
  • the present inventors have found that leakage current can be prevented from occurring on the surface of the silicon substrate immediately below the bottom surface of the substrate.
  • the method for manufacturing a semiconductor device includes a plurality of element isolation grooves extending in a first direction on a surface layer of a silicon substrate and repeatedly arranged in a second direction intersecting the first direction, and the element Forming an active region partitioned by the isolation trench; forming an inner wall oxide film on a side surface of the active region; and forming an element isolation region by forming an element isolation insulating film filling the element isolation trench
  • a plurality of mask film patterns extending in the second direction across the active region and the element isolation region, and an upper surface of the active region and the element isolation are formed in an opening of the mask film pattern Exposing the upper surface of the region, etching back the element isolation insulating film whose upper surface is exposed in the element isolation region in the vertical direction, and side-etching both side surfaces of the active region to thereby form the active region of
  • the inner wall oxide film on the side surface of the saddle type fin portion can be surely removed, so that the height of each fin portion can be ensured without digging a large STI structure. Further, by avoiding excessive digging of the element isolation insulating film, it is possible to secure the thickness of the element isolation insulating film remaining at the bottom of the element isolation groove, so that the surface of the silicon substrate located immediately below the bottom surface of the element isolation groove is formed. Generation of flowing leakage current can be prevented.
  • FIG. 2 is a schematic cross-sectional view showing the semiconductor device manufacturing method and the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ shown in FIG.
  • FIG. 3B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 3A.
  • FIG. 3B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a BB ′ cross-sectional view illustrated in FIG. 3A. It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface.
  • FIG. 4B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a sectional view taken along the line AA ′ in FIG. 4A.
  • FIG. 4B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention, and is a BB ′ sectional view shown in FIG. 4A. It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface.
  • FIG. 5B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 5A.
  • FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention, and is a BB ′ sectional view shown in FIG.
  • FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 6A.
  • FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention, and is a BB ′ sectional view shown in FIG. 6A.
  • FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 6A.
  • FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention, and is a BB ′ sectional view shown in FIG. 6A.
  • FIG. 7B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a sectional view taken along the line AA ′ in FIG. 7A. It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface.
  • FIG. 8B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 8A.
  • FIG. 1 is a plan view schematically showing a semiconductor device A according to an embodiment to which the present invention is applied.
  • the X direction shown in the drawing is a bit line extending direction (third direction), and X is inclined in the X direction.
  • the 'direction is the active region and element isolation region extending direction (first direction)
  • the Y direction is the word line extending direction (second direction)
  • the Z direction is the semiconductor lamination direction.
  • 2 is a cross-sectional view taken along line AA in the plan view of FIG. 3 to 8 are process diagrams schematically showing main processes of the semiconductor device manufacturing method of the present embodiment.
  • a DRAM Dynamic Random Access Memory
  • an inner wall oxide film 24 is formed on the inner surface of the element isolation groove 23 and an element isolation insulating film 25 is formed in the element isolation groove 23.
  • a shallow trench isolation (STI) structure including an element isolation region 2 that partitions the active region 1a extending in the X ′ direction (first direction) in the Y direction (second direction) is included.
  • a silicon substrate 1 is provided.
  • the active region 1a has a plurality of silicon pillars 12 and a height lower than that of the silicon pillars 12, and the width in the Y direction is narrower than the width in the Y direction of the active region 1a pattern.
  • a plurality of saddle type fin portions 11 from which the inner wall oxide film 24 has been removed are provided. That is, in the semiconductor device A, the silicon pillar portions 12 and the saddle-type fin portions 11 are connected by being repeatedly arranged in the X ′ direction in the active region 1a.
  • the semiconductor device A is provided between each of the plurality of pillar-type fin portions 12 and is provided on the upper surface of the first embedded word line 31 constituting the dummy electrode and the plurality of saddle-type fin portions 11, and the gate electrode Are provided on the first interlayer insulating film 4 formed so as to cover at least the STI structure on the silicon substrate 1, and the active region 1 a and the bit contact plug (bit contact layer) 54. And a bit line 55 connected to each other through the bit line gate 5.
  • the semiconductor device A is provided on the second interlayer insulating film 6 formed so as to cover the bit line gate (bit line) 5 and the first interlayer insulating film 4, and the active region 1a and the capacitive contact layer 7 are interposed therebetween.
  • the capacitor 8 is generally connected.
  • the semiconductor device A according to the present embodiment is configured such that a transistor having a buried gate type structure is formed on the STI structure included in the silicon substrate 1 by the above configuration.
  • an element isolation region 2 having a slope in the X direction (bit line direction) and extending in a straight line in the X ′ direction, and an X adjacent to the element isolation region 2
  • the active regions 1a extending linearly in the 'direction are repeatedly arranged in the Y direction (word line direction) at equal pitch intervals.
  • the active region 1a is electrically isolated in the Y direction by the element isolation region 2.
  • the upper surface width in the Y direction of the element isolation region 2 and the active region 1a may be the same, or the upper surface width of the element isolation region 2 may be smaller than the upper surface width of the active region 1a. good.
  • a second embedded word line 32 that extends in a straight line in the Y direction across the plurality of element isolation regions 2 and the plurality of active regions 1a and forms a gate electrode (hereinafter sometimes simply referred to as a word line). Further, a first buried word line (hereinafter also referred to as a dummy word line) 31 forming a dummy electrode is disposed. In FIG. 1, a part of the configuration is omitted, but two word lines 32 are arranged at equal intervals between two adjacent dummy word lines 31. That is, the dummy word lines 31 and the word lines 32 are arranged with the same width and interval.
  • the semiconductor device A according to the present embodiment has a configuration in which a saddle-type fin portion 11 is formed on the surface of the silicon substrate 1 located immediately below each word line, and a silicon pillar portion 12 is disposed between each word line. Has been.
  • the dummy word line 31 is made of the same material as the word line 32, but each word line 32 functions as a gate electrode of a corresponding transistor, whereas the dummy word line 31 has both sides of the dummy word line 31.
  • the active region 1a is insulated and isolated by the element isolation region 2 in the Y direction (word line direction) and by the dummy word line 31 in the extending X ′ direction (substantially bit line direction). It constitutes an independent island-like active region.
  • the adjacent dummy word lines 31 are directed in the X direction (bit line direction) 31A, 31B, 31C, and the word line 32 is directed in the X direction 32A. They are called 32B and 32C.
  • One island-like active region extending in the X ′ direction is sandwiched between the dummy word line 31A and the dummy word line 31B. Furthermore, the capacitor contact connection region 1d adjacent to the dummy word line 31A and the word line 32A, the bit contact connection region 1e adjacent to the word line 32A and the word line 32B, and the other adjacent to the word line 32B and the dummy word line 31B. And a capacitor contact connection region 1d.
  • one capacitor contact region 1d adjacent to the dummy word line 31A, one word line 32A, and the bit contact connection region 1e constitute one transistor Tr1.
  • the bit contact connection region 1e, the other word line 32B, and the other capacitor contact connection region 1d adjacent to the dummy word line 31B constitute another transistor Tr1. Accordingly, the bit contact connection region 1e is configured to be shared by the two transistors Tr1.
  • the capacitor contact connection region 1d and the bit contact connection region 1e are configured by the silicon pillar portion 12.
  • bit contact plug 53 is provided on each bit contact connection region 1e, and a bit line 55 extending in the X direction by connecting to each bit contact plug (bit contact layer) 54 is disposed.
  • bit line gate 5 is configured.
  • a capacitor contact 7 is provided on each capacitor contact connection region 1d, and a capacitor (not shown in FIG. 1) is provided on each capacitor contact 7.
  • word lines that also serve as gate electrodes are formed on the surface of the silicon substrate 1 through a gate insulating film in a plurality of word grooves 3 formed with the same width and interval. Each is buried. More specifically, a word line 3d made of metal is inserted into each of the first word groove 3A and the second word groove 3B formed with the same width and interval through a gate insulating film 3c made of a silicon oxide film. Each is buried. A cap insulating film 3e is buried so as to cover the upper surface of the word line 3d. A dummy word line 31 is disposed in the first word groove 3A, and a word line 32 is disposed in the second word groove 3B.
  • a refractory metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, or a tungsten film can be used.
  • the laminated film can be selected as appropriate.
  • a first interlayer insulating film 4 is provided so as to cover the cap insulating film 3e.
  • a bit contact plug (bit contact layer) 54 penetrating the first interlayer insulating film 4 is disposed on the upper surface of the bit contact connection region 1e formed of the active region 1a located between two adjacent word lines 32A and 32B.
  • bit lines 55 connected to the upper surface and extending in the X direction are arranged in a stacked manner to constitute a wiring.
  • a side wall insulating film 56 made of a silicon nitride film is provided on the upper surface and side wall of the bit line 55, and the bit contact plug 54, the bit line 55, and the side wall insulating film 56 constitute the bit line gate 5 in the memory cell region. ing.
  • each member constituting the bit line 55 for example, a refractory metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, a tungsten silicide film, or a tungsten film can be used.
  • a layer or a laminated film can be appropriately selected.
  • a second interlayer insulating film 6 made of a silicon oxide film is provided on the entire surface of the silicon substrate 1 so as to cover the bit line gate 5.
  • a capacitor contact plug (capacitor contact layer) 7 is connected to the upper surface of the active region 1 a serving as the capacitor contact connection region 1 d through the second interlayer insulating film 6 and the first interlayer insulating film 4.
  • a stopper film 9 made of a silicon nitride film and a third interlayer insulating film 13 made of a silicon oxide film are provided on the entire surface including the upper surface of the capacitor contact plug 7.
  • a cylinder hole 8a penetrating the third interlayer insulating film 13 and the stopper film 9 is opened so as to reach the upper surface of the capacitor contact plug 7, and the lower electrode 8b is covered so as to cover the inner wall and the bottom of the cylinder hole 8a. Is provided.
  • the lower electrode 8 b is connected to the upper surface of the capacitor contact plug 7.
  • a capacitor insulating film 8c and an upper electrode 8d are provided so as to cover the lower electrode surface 8b, and the capacitor 8 is configured by the lower electrode 8b, the capacitor insulating film 8c, and the upper electrode 8d.
  • the semiconductor device A is provided with a fourth interlayer insulating film 14 so as to cover the capacitor 8, and further, a wiring contact 15 is provided through the fourth interlayer insulating film 14.
  • the wiring layer 16 is connected.
  • a protective insulating film 17 is provided on the entire surface so as to cover the wiring layer 16 and the fourth interlayer insulating film 14.
  • the inner wall oxide film 24 is formed in the element isolation groove 23 and the element isolation insulating film 25 is formed in the element isolation groove 23, so that the element isolation region 2 is formed.
  • a plurality of pillar-type fin portions 12 and a height lower than that of the pillar-type fin portions 12 and a narrow width in the Y direction are formed to oxidize the inner wall.
  • the structure includes a plurality of saddle-type fin portions 11 from which the film 24 has been removed.
  • FIG. 3A shows a cross-sectional view along AA ′ in FIG. 6A).
  • the AA ′ cross-sectional views in FIGS. 3 to 6 are different in direction from the AA ′ cross-sectional view in FIG. 2, so care should be taken.
  • the silicon substrate 1 used in this embodiment is a p-type single crystal substrate.
  • the manufacturing method of the semiconductor device A of the present embodiment is repeatedly arranged in the Y direction (second direction) extending in the X ′ direction (first direction) on the surface layer of the silicon substrate 1 and intersecting the X ′ direction.
  • the manufacturing method of the present embodiment can be a method that sequentially includes the following steps (1) to (5).
  • a mask insulating film and a first resist mask (not shown) are sequentially formed on the silicon substrate 1, and the silicon substrate 1 and the mask insulating film are etched using the first resist mask, so that the X ′ direction (first After element isolation trenches 23 are formed in a line-and-space pattern along a region to be formed of element isolation regions 2 extending in one direction), an inner wall oxide film 24 is formed on the inner surface of the element isolation trenches 23.
  • An isolation region 2 for partitioning the active region 1a is formed by filling the isolation trench 23 with an insulating material to form an isolation isolation film 25, and an STI for forming a shallow trench isolation (STI) structure.
  • an element isolation insulating film whose upper surface is exposed in the element isolation region 2 when simultaneously forming a plurality of word grooves 3 that intersect the X ′ direction (first direction) and extend in the Y direction (second direction).
  • the inner wall oxide film 24 formed on the side wall of the active region 1a is removed by side-etching both side surfaces of the active region 1a to reduce the width in the Y direction (second direction).
  • the manufacturing method of the present embodiment is a method including a step of forming a bit line, a step of forming a capacitor, a step of forming a wiring layer, etc. in addition to the steps (1) to (5). be able to.
  • the saddle type fin portion 11 can be formed without leaving the inner wall oxide film 24.
  • STI process of this embodiment will be described with reference to FIGS. 3A to 3C.
  • a pad silicon oxide film having a thickness of 2 nm and a silicon nitride film having a thickness of 50 nm are stacked on the silicon substrate 1.
  • a plurality of photoresist patterns extending in the X ′ direction (first direction) are formed on the silicon nitride film by using a lithography technique.
  • This photoresist pattern is formed, for example, as a line pattern having a width in the Y direction of 40 nm and an interval of 40 nm.
  • the photoresist pattern as a mask, the underlying silicon nitride film and pad silicon oxide film are anisotropically dry etched to transfer the pattern. Thereby, the upper surface of the silicon substrate 1 is exposed.
  • the photoresist pattern is removed, and using the silicon nitride film as a mask, the portion of the silicon substrate 1 where the upper surface is exposed is subjected to anisotropic dry etching to form an element isolation groove 23.
  • the depth of the element isolation groove 23 from the upper surface of the silicon substrate 1 is, for example, 250 nm.
  • a mixed gas plasma of hydrogen bromide (HBr), chlorine (Cl 2 ), and oxygen (O 2 ) is used for the anisotropic dry etching.
  • the active region 1a is partitioned in the Y direction (second direction) by the formation of the element isolation groove 23, and the side surface of the element isolation groove 23, that is, the first side surface constituting the active region 1a.
  • the first side surface 1b and the second side surface 1c are formed.
  • the first side surface 1b and the second side surface 1c are formed to face the second direction and extend in the first direction with the active region 1a interposed therebetween.
  • the first side surface 1b and the second side surface 1c are formed so as to be slightly inclined toward the active region 1a made of the silicon substrate 1 so as not to deteriorate the characteristics of the transistor formed in the active region 1a in a later step. Is done. That is, the upper width of the opposing first side surface 1b and second side surface 1c is formed narrower than the lower width.
  • the inclination angle is in a range of 85 ° or more and less than 90 °.
  • the inner surface of the element isolation groove 23 including the first side surface 1b and the second side surface 1c is left thermally oxidized by a conventionally known method with the silicon nitride film used as a mask remaining, for example, a thickness of 2 nm.
  • An inner wall oxide film 24 made of a silicon oxide film is formed.
  • a buried insulating material film made of a silicon nitride film is formed by CVD on the entire surface of the silicon substrate 1 so as to fill the element isolation trench 23.
  • the buried insulating material is not limited to a silicon nitride film, and a silicon oxide film formed by a CVD method or a spin coating method can be used. Further, it may be formed of a laminated film of a silicon nitride film and the silicon oxide film.
  • the silicon nitride film used as the buried insulating material and the silicon nitride film used as the mask are simultaneously etched back and removed. At this time, even when a silicon oxide film is used as the buried insulating material, it can be removed by the same method.
  • the element isolation trench 23 is filled with the element isolation insulating film 25 having an upper surface that is flush with the upper surface of the silicon substrate 1. By filling such an element isolation insulating film 25, a plurality of element isolation regions 2 extending in the first direction are formed.
  • the width (upper surface width) W1 in the Y direction on the upper surface of the active region 1a is, for example, about 40 nm.
  • the element isolation region 2 has an STI structure, and the upper surface width in the Y direction is 40 nm, which is equal to the upper surface width of the active region 1a.
  • the width and interval in the Y direction of the photoresist pattern are both set to 40 nm, but the present invention is not limited to this, and the interval may be made smaller than 40 nm. That is, the upper surface width in the Y direction of the element isolation region 2 may be formed to be smaller than the upper surface width in the Y direction of the active region 1a. This has the advantage that the planar area of the memory cell can be reduced.
  • the element isolation region 2 in the present embodiment is formed of a silicon oxide film formed on the boundary with the active region 1a formed of the silicon substrate 1, that is, the first side surface 1b and the second side surface 1c by the thermal oxidation method.
  • the structure includes an inner wall oxide film 24 and an element isolation insulating film 25 that covers the inner wall oxide film 24.
  • a mask film 3a is formed on the silicon substrate 1, and then a second photoresist mask R is formed thereon using a lithography technique.
  • the mask film 3a can be made of a material such as an amorphous carbon film and a silicon oxide film.
  • the second photoresist mask R extends in a second direction (Y direction) intersecting the first direction (X ′ direction) and has a plurality of line patterns extending over the plurality of active regions 1 a and the plurality of element isolation regions 2. It is formed.
  • the width and interval of the second photoresist mask R in the X direction (third direction) perpendicular to the Y direction are each 40 nm, for example.
  • the lower mask film 3a is etched by an anisotropic dry etching method using the second photoresist mask R as a mask to transfer the mask pattern.
  • the upper surface of the active region 1a and the upper surface of the element isolation region 2 are exposed.
  • the second photoresist mask R is removed.
  • the active region 1a and the element isolation region 2 whose upper surfaces are exposed are subjected to anisotropic dry etching to simultaneously form the first word groove 3A and the second word groove 3B.
  • a method is used in which the element isolation region 2 is first subjected to anisotropic dry etching, and then the active region 1a is subjected to anisotropic dry etching.
  • a method of etching the element isolation region 2 after etching the active region 1a is not preferable. The reason is that, as described above, the first side surface 1b and the second side surface 1c constituting the active region 1a are formed so as to be slightly inclined toward the active region 1a side.
  • the element isolation insulating film 25 formed along the Z direction of the first side face 1b and the second side face 1c serves as an etching mask, and as a result, the first extension extending in the first direction. This is because the etching residue of the silicon substrate 1 occurs along the side surface 1b and the second side surface 1c. In order to avoid this, in this embodiment, it is necessary to anisotropically dry the element isolation region 2 first.
  • the element isolation region 2 whose upper surface is exposed is selectively subjected to anisotropic dry etching.
  • the upper surface of the element isolation region 2 includes the upper surface of the inner wall oxide film 24 formed on the first side surface 1b and the second side surface 1c and the element isolation insulating film 25 embedded in the element isolation trench 23. And an upper surface.
  • the inner wall oxide film 24 is made of a silicon oxide film formed by a thermal oxidation method
  • the element isolation insulating film 25 is made of a silicon nitride film formed by a CVD method.
  • the first side surface The inner wall oxide film 24 formed on 1b and the second side surface 1c is not sufficiently etched and tends to remain. Such remaining of the inner wall oxide film 24 causes various inconveniences as described above (see the section of the problem to be solved by the invention).
  • the element isolation insulating film is formed of a silicon oxide film formed by CVD or spin coating.
  • the silicon nitride film (element isolation insulating film 25) is etched by anisotropic dry etching, and at the same time, the first side surface 1b and the second side surface 1c are side etched to perform the Y-direction of the active region 1a. Reduce the width.
  • the degenerate width W2 on one side surface is, for example, 5 nm.
  • the entire active region 1a is degenerated by 10 nm.
  • an etching condition is used in which isotropic etching for simultaneously etching the inner wall oxide film 24 exposed on the first side surface 1b and the second side surface 1c in the lateral direction can be performed.
  • the inner wall oxide film 24 exposed on the first side face 1b and the second side face 1c is replaced with an isotropic silicon oxide film.
  • a method of performing dry etching step by step using etching conditions may be used.
  • a first saddle fin portion (saddle fin portion) 11a is formed in which the upper surface of the active region 1a is higher than the upper surface of the element isolation region 2 adjacent in the Y direction.
  • the position of the upper surface of the element isolation region 2 after being dug down is, for example, a position 150 nm below the upper surface of the silicon substrate 1.
  • the width W3 in the Y direction on the upper end side of the plurality of first saddle type fin portions 11a becomes 30 nm, and the upper surface width in the Y direction of the active region 1a It is 10 nm narrower than W1 (40 nm).
  • the inner wall oxide film 24 formed on the side surfaces 1b and 1c of the active region 1a can be reliably removed at a position corresponding to the side surface of the first saddle type fin portion 11a.
  • the side surface of the first saddle type fin portion 11a is newly formed.
  • the first side surface 1b of the active region 1a becomes a new first side surface 1bb in the first saddle type fin portion 11a
  • the second side surface 1c similarly becomes a new second side surface 1cc.
  • the new first side surface 1bb is connected to the original first side surface 1b via a step D1 having a degenerated width W2
  • the new second side surface 1cc is connected to the original second side via a step D2 having a degenerate width W2. It is formed so as to be connected to the side surface 1c.
  • a mask film 3a made of an amorphous carbon film and a silicon oxide film is formed on the entire surface of the silicon substrate 1 including the STI structure, for example, by a CVD method.
  • a BARC film is applied on the mask film 3a, and a photoresist is laminated and applied.
  • a second photoresist mask R having a repetitive pattern of the word grooves 3 is formed by lithography and BARC etching.
  • a mask film 3a is formed in a repeated pattern of the word grooves 3 by etching using the second resist mask R. Thereafter, the photoresist and the BARC film are removed.
  • the element isolation region 2 whose upper surface is exposed is selectively anisotropically dry etched using the mask film 3a as a mask.
  • the element isolation insulating film 25 in the element isolation region 2 is selectively etched, Si in the active region 1a is hardly etched from above, and the inner wall oxide film 24 is etched in the lateral direction and silicon.
  • Etching is performed under the condition of applying pressure and 700 to 1200 W of RF power.
  • the side etch amount increases when the chamber pressure becomes high, and the side etch amount decreases when the chamber pressure becomes low.
  • an appropriate side etch amount can be obtained and the inner wall oxidation can be achieved.
  • the saddle type fin portion 11 can be formed while the film 24 is reliably removed.
  • the change in the thickness of the inner wall oxide film 24 in the element isolation region 2 is not dependent on the thickness of the inner wall oxide film 24 by performing adjustment by changing the flow rate of O 2 . It is possible to form the saddle type fin portion 11 while reliably removing the inner wall oxide film 24.
  • the side etching is made appropriate and etching is performed so that the inner wall oxide film 24 in the element isolation region 2 does not remain in the saddle type fin portion 11.
  • the saddle type is formed while removing the inner wall oxide film 24 by changing the chamber pressure at the time of silicon etching in the next digging step to a high pressure side so that side etching can be performed. It is also possible to make the fin portion 11 thin.
  • the upper surface of the first saddle type fin portion 11a formed in the fin portion forming step is etched to a desired depth. This etching is preferably performed continuously by changing the conditions in the apparatus used in the fin portion forming step.
  • the desired depth at this time is 40 to 45 nm higher than the upper surface of the deeply isolated element isolation region 2, and in this case, 105 to 110 nm lower than the upper surface of the silicon substrate 1.
  • etching is performed on the element isolation region 2 under a condition with a high selection ratio, that is, anisotropic dry etching is performed on the condition that the ER of silicon is faster than the ER of the silicon nitride film or silicon oxide film.
  • anisotropic dry etching is performed on the condition that the ER of silicon is faster than the ER of the silicon nitride film or silicon oxide film.
  • the narrower the width the ER of the first saddle type fin portion 11a may be faster than expected.
  • the saddle type fin portion 11a may disappear. Therefore, a condition for lowering the ER of silicon is adopted for the etching of the first saddle type fin portion 11a.
  • a mixed gas plasma atmosphere of chlorine (Cl 2 ), tetrafluorocarbon (CF 4 ), SF 6 and He has a chamber pressure of 3 to 10 Pa and an RF power of 100 to 300 W.
  • Etching is performed by applying.
  • ER of Si silicon can be controlled at a flow rate of SF 6, for example, by reducing the flow rate of SF 6, it is possible to suppress the silicon etch rate.
  • the second saddle fin portion (saddle fin portion) 11 can be formed by narrowing the width in the Y direction while controlling the height of the first saddle fin portion 11a.
  • the inner wall oxide film 24 in the element isolation region 2 is not left on the first side surface 1b and the second side surface 1c, it is not necessary to etch the element isolation region 2 deeper. Therefore, it is possible to sufficiently secure the thickness of the element isolation insulating film 25 after being dug down, and to avoid the problem that current leaks on the surface of the silicon substrate immediately below due to the parasitic MOS effect.
  • the element isolation regions 2 and the saddle type fin parts 11 that are dug down are alternately arranged in the second direction.
  • the first word groove 3A and the second word groove 3B are formed simultaneously. That is, as shown in FIG. 6A, between the two first word grooves 3A extending in the second direction, two second word grooves 3B extending in the Y direction are arranged. ing.
  • the memory cell region is configured by repeatedly arranging the first word line 3A and the two second word lines 3B in the X direction as a basic configuration.
  • the active region 1a extending in the first direction is divided into island-shaped small active regions 1aa by two first word grooves 3A serving as element isolation regions in the first direction.
  • ⁇ (4) Embedded Word Line Formation Step> In the buried word line forming step, after a conductive material is deposited on the bottom surfaces of the plurality of word grooves 3 (first word groove 3A and second word groove 3B), a part of the conductive material is removed by etching. The conductive material is left on the bottom surfaces of the first word groove 3A and the second word groove 3B. Thereby, a dummy word line (first embedded word line) 31 constituting a dummy electrode is formed, and a word line (second embedded word line) 32 constituting a gate electrode is formed.
  • FIG. 7B is a cross-sectional view in the X ′ direction (first direction) as in FIG. 2.
  • silicon oxide films are formed on the side and bottom surfaces of the word groove 3 (first word groove 3A, second word groove 3B) by ISSG (In-Situ Steam Generation) oxidation.
  • a gate insulating film 3c is formed. The thickness of the gate insulating film 3c is preferably about 5 nm.
  • a TiN film and a W film are formed on the entire surface of the wafer so as to fill the first word groove 3A and the second word groove 3B by using the CVD method, and then the position of each upper surface is the upper surface of the silicon substrate 1.
  • the word line 3d is formed by etching back to a position below 70 to 80 nm from the back. Through the above process, the dummy word line 31 and the word line 32 which are embedded word lines are formed.
  • cap formation step After the dummy word line 31 and the word line 32 are formed in the above step, the first word groove 3A and the second word groove 3B are further filled with an insulating material, and the first buried word line 31 and the first word line 31 are then filled. 2 A cap forming step of forming the embedded cap insulating film 3e by embedding the embedded word line 32 is provided.
  • a cap insulating film 3e which is a silicon nitride film, is formed on the entire surface of the wafer by CVD, and is planarized by using CMP as a stop film using CMP. At this time, the mask film 3a may be removed at the time of planarization.
  • a bit line forming step is further provided following the cap forming step (5).
  • an insulating material is deposited so as to cover the STI structure and the embedded cap insulating film 3e on the silicon substrate 1, thereby forming the first interlayer insulating film 4.
  • a part of the first interlayer insulating film 4 is removed by etching to form a bit contact hole (contact hole) 53, and then the bit contact hole 53 is filled with a conductive material, whereby the first interlayer insulating film 4 is formed.
  • bit contact plug (bit contact layer) 54 that penetrates and is connected to the active region 1a is formed.
  • bit line forming step of forming a bit line gate upper layer film (bit line) 55 connected to the bit contact plug 54 by patterning a conductive material on the first interlayer insulating film 4 is provided.
  • a capacitor forming process as described below can be used.
  • this capacitor forming step as shown in FIGS. 7 to 8, first, an insulating material is deposited so as to cover the bit line gate 5 and the first interlayer insulating film 4 to form the second interlayer insulating film 6, and then Then, a part of the second interlayer insulating film 6 is removed by etching to form a contact hole. Next, the contact hole is filled with a conductive material, thereby forming a capacitor contact (capacitor contact layer) 7 penetrating the second interlayer insulating film 6 and connected to the active region 1a.
  • a stopper film 9 and a third interlayer insulating film 13 are sequentially laminated so as to cover the second interlayer insulating film 6 and the capacitor contact 7, and then the capacitor contact 7 in the stopper film 9 and the third interlayer insulating film 13 is stacked.
  • the cylinder hole 8a is formed by etching away the position corresponding to. Specifically, first, a stopper film 9 made of a silicon nitride film and a third interlayer insulating film 13 made of a silicon oxide film are formed on the entire surface of the wafer by using a CVD method, and a lithography method and dry etching are performed. The cylinder hole 8a is opened.
  • a thin TiN film is formed so as to cover the entire surface of the wafer, that is, the bottom surface and side walls of the cylinder hole 8a and the top surface of the third interlayer insulating film 13, and then the bottom surface and side walls of the cylinder hole 8a by etching.
  • the lower electrode (lower electrode layer) 8b is formed by leaving the TiN film only on the surface.
  • a capacitive insulating film 8c and an upper electrode (upper electrode layer) 8d are laminated in this order on the entire surface of the wafer including the inside of the lower electrode 8b. Then, etching is performed by lithography and dry etching so that only the capacitor insulating film 8c and the upper electrode 8d on the memory cell region MCA remain, and other portions are removed. Thereby, the capacitor 8 composed of the lower electrode 8b, the capacitor insulating film 8c, and the upper electrode 8d is formed.
  • a wiring layer forming step as described below can be provided.
  • the fourth interlayer insulating film 14 is formed so as to fill the cylinder hole 8a and cover the upper electrode 8d.
  • a part of the fourth interlayer insulating film 14 is removed by etching to form a contact hole, and then the contact hole is filled with a conductive material so as to penetrate the fourth interlayer insulating film 14 and connect to the upper electrode 8d.
  • a wiring contact 15 is formed.
  • a wiring layer 16 connected to the wiring contact 15 is formed by patterning a conductive material on the fourth interlayer insulating film 14.
  • a protective insulating film 17 is formed so as to cover the wiring layer 16 and the fourth interlayer insulating film 14.
  • the semiconductor device A configured as a vertical transistor as shown in FIGS. 1 and 2 is obtained by the above steps.
  • the inner wall oxide film 24 formed on the side surface of the active region 1a can be surely removed. It is possible to secure the height of each fin portion without the need to dig deeply. Further, by avoiding excessive digging into the element isolation region 2, the thickness of the element isolation insulating film 25 remaining at the bottom of the element isolation groove 23 can be secured. It is possible to prevent the occurrence of leakage current flowing on the surface of the silicon substrate 1.
  • the inner wall oxide film 24 in the element isolation trench 23 having the STI structure can be reliably removed only by adjusting the etching rate by changing the flow rate of the etching gas. Therefore, a process with excellent productivity can be realized without depending on the thickness of the inner wall oxide film 24.
  • a ... Semiconductor device 1 ... silicon substrate, 11 ... saddle type fin part, 11a ... 1st saddle type fin part, 11b ... 2nd saddle type fin part, 12 ... pillar type fin part 1a ... active region, 1aa ... small active region, 1b, 1bb ... first side surface, 1c, 1cc ... second side surface, 1d: capacitive contact connection region, 1e: Bit contact connection region, 2 ... element isolation region (STI), 23: Element isolation groove, 24 ... inner wall oxide film, 25 ... element isolation insulating film, 3 ... Word groove, 3A ... 1st word groove, 3B ... Second word groove, 31, 31A, 31B, 31C ...
  • STI element isolation region
  • lower electrode lower electrode
  • 8c capacitive insulating film
  • 8d upper electrode (upper electrode layer)
  • 13 Third interlayer insulating film
  • 14 Fourth interlayer insulating film
  • 15 ... wiring contact
  • 16 ... wiring layer
  • 17 Protective insulating film
  • R resist mask (second resist mask)
  • Tr1 ... cell transistor

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Abstract

Provided is a semiconductor device manufacturing method that is provided with: a step for forming, on a silicon substrate (1), a plurality of element isolation grooves (23) and active regions (1a), said element isolation grooves and active regions extending in the first direction and being repeatedly disposed in the second direction; a step for forming inner wall oxide films (24) on the side surfaces of the active regions (1a), respectively; a step for forming element isolation regions (2) by forming element isolating insulation films (25) with which the element isolation grooves (23) are filled; a step for forming a plurality of mask film patterns extending in the second direction, and exposing the active regions (1a) and the element isolation regions (2) from openings in the mask film patterns; a step for etching back the element isolating insulation films (25) exposed from the element isolation regions (2), and removing the inner wall oxide films (24) by side-etching both the side surfaces of respective active regions (1a); and a step for forming a saddle-shaped fin section (11) by etching back the silicon substrate (1) exposed from the active regions (1a). In the method, the inner wall oxide films (24) are reliably removed, the thickness of the element isolating insulation films (25) is ensured by eliminating excessive etching, and generation of a leak current can be eliminated.

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本発明は、半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
　一般に、コンピュータや電気機器の主要部分には、多数のＭＯＳトランジスタや抵抗等を一つのチップ上に集積化する大規模集積回路（ＬＳＩ）が採用されている。特に、ＬＳＩの中でも、ＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）又はＰＲＡＭ（Ｐａｒａｍｅｔｅｒ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）等の半導体装置の分野においては、使用される機器の高機能化等により、さらなる急速な微細化、高集積化が進められている。 Generally, a large-scale integrated circuit (LSI) that integrates a large number of MOS transistors, resistors, and the like on a single chip is adopted as a main part of a computer or an electric device. Especially in the field of semiconductor devices such as DRAM (Dynamic Random Access Memory) or PRAM (Parameter Random Access Memory) among LSIs, further rapid miniaturization and higher integration are achieved by increasing the functionality of the equipment used. Is underway.
　また、上述のような半導体装置における素子分離構造として、ＳＴＩ（Ｓｈａｌｌｏｗ　Ｔｒｅｎｃｈ　Ｉｓｏｌａｔｉｏｎ：シャロー・トレンチ・アイソレーション）と呼ばれる方法・構造が知られている。このＳＴＩとは、例えば、シリコン基板上にシャロートレンチと呼ばれる浅い溝を形成し、これを酸化膜等の絶縁材料からなる素子分離絶縁膜で充填することにより、シリコン基板上に設けられる活性領域を区画する素子分離領域が設けられてなる構造である。このようなこのＳＴＩは、プロセスが簡便なＬＯＣＯＳ（Ｌｏｃａｌ　Ｏｘｉｄａｔｉｏｎ　ｏｆ　Ｓｉｌｉｃｏｎ）に比べ、横方向への広がりが無く、微細化が可能となるというメリットがある。 Further, as an element isolation structure in the semiconductor device as described above, a method / structure called STI (Shallow Trench Isolation) is known. This STI means that, for example, a shallow trench called a shallow trench is formed on a silicon substrate, and this is filled with an element isolation insulating film made of an insulating material such as an oxide film, whereby an active region provided on the silicon substrate is formed. This is a structure in which element isolation regions to be partitioned are provided. Such STI has an advantage that it can be miniaturized without expanding in the horizontal direction, compared to LOCOS (Local Oxidation of Silicon), which is simple in process.
　上述したＳＴＩによるラインアンドスペースタイプのフィールドパターンを用いたトランジスタ構造においては、ゲート電極を構成するワード線に加え、さらに、素子を分離するためのダミーワード線を設けることが必要となる。このように、シリコン基板上のＳＴＩ構造に対して基板埋め込み型のワード線を設けるにあたり、トランジスタのチャネル部の形成にサドル型フィン構造を用いた場合、ＳＴＩ上にワードラインに沿った溝を形成する必要がある（例えば、特許文献１、２を参照）。 In the transistor structure using the line-and-space type field pattern by STI described above, it is necessary to provide a dummy word line for isolating elements in addition to the word line constituting the gate electrode. Thus, when a saddle type fin structure is used for forming a channel portion of a transistor in providing a substrate buried type word line for an STI structure on a silicon substrate, a groove along the word line is formed on the STI. (For example, refer to Patent Documents 1 and 2).
　ここで、ＳＴＩ構造にワード線及びダミーワード線を形成した場合、内壁酸化膜と埋設膜との間にエッチレート差が生じるとともに、シリコン基板上の溝開口部の断面が矩形であること等から、その側面に位置するＳＴＩの内壁酸化膜がエッチングされ難くなり、フィンの側面に内壁酸化膜が残存しやすいという問題が生じ、これは、内壁酸化膜が厚い場合ほど顕著となる。このように、フィンの側壁に内壁酸化膜が残存している箇所においては、チャネル領域としての効果が発現し難くなることから、チャネル領域は、フィンの側壁に残存した内壁酸化膜の頂部より上方に形成されるシリコン基板の高さに依存する。このため、フィンの高さを所定以上としてチャネル領域を確保するためには、その分だけ、シリコン基板上のＳＴＩ構造を深く掘り込んでワード溝を形成する必要がある。しかしながら、この場合にはＳＴＩの残膜、即ち、隣接活性領域を素子分離する埋設膜の膜厚が薄くなることから、寄生ＭＯＳ効果によって、その下に位置するシリコン基板の表面を通って電流がリークしやすくなるという問題がある。また、ダミーワードラインにおいて、フィンの側壁に残存している内壁酸化膜が薄い場合、その部分もチャネル領域となることから、このフィンを介して電流がリークしやすくなるという問題がある。 Here, when the word line and the dummy word line are formed in the STI structure, an etch rate difference is generated between the inner wall oxide film and the buried film, and the cross section of the groove opening on the silicon substrate is rectangular. The STI inner wall oxide film located on the side surface becomes difficult to be etched, and the problem that the inner wall oxide film tends to remain on the side surface of the fin arises. This becomes more conspicuous as the inner wall oxide film is thicker. As described above, the channel region is located above the top of the inner wall oxide film remaining on the side wall of the fin because the effect as the channel region is less likely to be exhibited in the portion where the inner wall oxide film remains on the side wall of the fin. Depends on the height of the silicon substrate formed. For this reason, in order to secure the channel region by setting the fin height to a predetermined value or more, it is necessary to dig deeply into the STI structure on the silicon substrate to form the word groove. However, in this case, since the film thickness of the remaining STI film, that is, the buried film for isolating the adjacent active region is thinned, current is passed through the surface of the underlying silicon substrate by the parasitic MOS effect. There is a problem that it is easy to leak. Further, in the dummy word line, when the inner wall oxide film remaining on the side wall of the fin is thin, the portion also becomes a channel region, and there is a problem that current is likely to leak through the fin.
特開２００８－０１６８４２号公報JP 2008-016842 A 特表２００８－０９１８７１号公報JP 2008-018771 A
　以下に、図９Ａ～図９Ｃ及び図１０Ａ～図１０Ｄを参照して、本発明者等が実験を行った、トランジスタのチャネル領域の形成にフィン構造を用いた基板埋め込み型のワード線の形成方法を説明する。図９Ａ及び図１０Ａは、従来の半導体装置を示す平面図であり、図９Ｂ及び図１０Ｂは、それぞれ、図９Ａ及び図１０Ａ中に示すＡ－Ａ断面図、図９Ｃ及び図１０Ｃ、図１０Ｄは、それぞれ、図９Ａ及び図１０Ａ中に示すＢ－Ｂ断面図である。 Hereinafter, referring to FIGS. 9A to 9C and FIGS. 10A to 10D, a method for forming a buried substrate type word line using a fin structure for forming a channel region of a transistor, which the present inventors have experimented Will be explained. 9A and 10A are plan views showing a conventional semiconductor device. FIGS. 9B and 10B are cross-sectional views taken along the line AA in FIGS. 9A and 10A, respectively. FIGS. 9C, 10C, and 10D are FIGS. FIG. 10B is a sectional view taken along line BB shown in FIGS. 9A and 10A, respectively.
　図９Ａ～図１０Ｃに示すように、まず、素子分離絶縁膜１０２ｅが表層に埋め込まれることでＳＴＩのラインアンドスペースパターンとされた素子分離領域１０２が形成されたシリコン基板１０１に対し、埋め込み型ワード線の溝加工を行う。図９Ａに示すように、ＳＴＩのラインアンドスペースパターンはＸ'方向に延在し、埋め込み型ワード線の溝はＸ'方向に交差するＹ方向に延在する。この際、まず、ＳＴＩ上に窒化シリコン膜１０３ａを成膜した後、その上に、リソグラフィ技術を用いて、ワード線予定ラインに沿ったラインアンドスペースパターンのレジストマスクＲを形成する。次いで、レジストマスクＲをマスクとしてドライエッチングを行い、窒化シリコン膜１０３ａをワード溝１０３ｂのパターンにエッチングする。これにより、ワード溝１０３ｂ内には、素子分離領域１０２の上面と、シリコン基板１０１からなる活性領域１０１ａの上面とが、Ｙ方向に交互に露出する。そして、窒化シリコン膜１０３ａをマスクとして、上面が露出している素子分離領域１０２と活性領域１０１ａとをエッチングすることにより、シリコン基板１０１に所定の深さのワード溝１０３ｂを形成する。この際、図９Ｂに示すように、まず、素子分離領域１０２における素子分離絶縁膜１０２ｅが選択的にエッチングされ、活性領域１０１ａのＳｉ（シリコン基板）がエッチングされにくい条件として、可能な限りＳｉを削らないようにエッチングを行う。これにより、図示例のように、ワード溝１０３ｂのエッチング形状が、ほぼ矩形状になる。この時、図９Ｃに示すＢ－Ｂ断面の位置においては、素子分離領域２における内壁酸化膜１０２ｄが、Ｓｉ基板１１２ａの側壁に取り残されがちになる。そして、図１０Ａ～図１０Ｃに示すように、活性領域１０１ａのＳｉが選択的にエッチングされる条件で、ワード溝１０３ｂをさらに所定の深さまでエッチングすることにより、図１０Ｃに示すように、活性領域１０１ａのシリコン基板の上面が素子分離絶縁膜１０２ｅの上面よりも高い位置まで突出して構成されるサドル型フィン部１１２を形成する。 As shown in FIGS. 9A to 10C, first, an embedded word is formed on a silicon substrate 101 in which an element isolation region 102e having an STI line and space pattern is formed by embedding an element isolation insulating film 102e in a surface layer. Line grooving. As shown in FIG. 9A, the STI line and space pattern extends in the X ′ direction, and the trench of the buried word line extends in the Y direction intersecting the X ′ direction. At this time, first, a silicon nitride film 103a is formed on the STI, and then a resist mask R having a line and space pattern along the word line planned line is formed thereon using a lithography technique. Next, dry etching is performed using the resist mask R as a mask, and the silicon nitride film 103a is etched into the pattern of the word groove 103b. As a result, the upper surface of the element isolation region 102 and the upper surface of the active region 101a made of the silicon substrate 101 are alternately exposed in the Y direction in the word groove 103b. Then, using the silicon nitride film 103a as a mask, the element isolation region 102 and the active region 101a whose upper surfaces are exposed are etched to form a word groove 103b having a predetermined depth in the silicon substrate 101. At this time, as shown in FIG. 9B, first, the element isolation insulating film 102e in the element isolation region 102 is selectively etched, and Si (silicon substrate) in the active region 101a is hardly etched as much as possible. Etching is performed so as not to cut. As a result, the etching shape of the word groove 103b becomes almost rectangular as shown in the illustrated example. At this time, at the position of the BB cross section shown in FIG. 9C, the inner wall oxide film 102d in the element isolation region 2 tends to be left on the side wall of the Si substrate 112a. Then, as shown in FIG. 10A to FIG. 10C, under the condition that Si in the active region 101a is selectively etched, the word groove 103b is further etched to a predetermined depth, and as shown in FIG. A saddle type fin portion 112 is formed so that the upper surface of the silicon substrate 101a protrudes to a position higher than the upper surface of the element isolation insulating film 102e.
　上記ワード溝１０３ｂを形成する工程においては、素子分離絶縁膜１０２ｅのエッチング速度がシリコン基板１のエッチング速度よりも速くなる条件としてエッチングを行う。このとき、ＳＴＩの内壁酸化膜１０２ｄと素子分離絶縁膜１０２ｅとの間にエッチレート差が生じるとともに、Ｓｉが矩形状となっていることから、内壁酸化膜１０２ｄがエッチングされ難くなる。このため、図１０Ｃに示すように、エッチングの際にＳｉの側面の内壁酸化膜１０２ｄを除去しきれず、サドル型フィン部１１２の側面に内壁酸化膜の残部１０２ｆが生じた状態となる。このような内壁酸化膜の残部１０２ｆが残存する量は、内壁酸化膜１０２ｄの膜厚に比例し、膜厚が厚いほど残存量も多くなる。 In the step of forming the word groove 103b, etching is performed under the condition that the etching rate of the element isolation insulating film 102e is higher than the etching rate of the silicon substrate 1. At this time, an etch rate difference occurs between the inner wall oxide film 102d of the STI and the element isolation insulating film 102e, and since Si is rectangular, the inner wall oxide film 102d is difficult to be etched. For this reason, as shown in FIG. 10C, the inner wall oxide film 102d on the side surface of Si cannot be completely removed during etching, and the remaining portion 102f of the inner wall oxide film is generated on the side surface of the saddle type fin portion 112. The amount of the remaining portion 102f of the inner wall oxide film remaining is proportional to the film thickness of the inner wall oxide film 102d, and the remaining amount increases as the film thickness increases.
　上述のように、Ｓｉの側面に内壁酸化膜の残部１０２ｆが生じた状態になると、この箇所におけるチャネル領域としての効果が発現し難くなり、トランジスタのチャネルとして機能しないという問題があった。このため、図１０Ｄに示すように、チャネル領域の確保を目的として、素子分離領域１０２におけるワード溝１０３ｂをさらに深く掘り込み、フィンの高さを高くする必要が生じる。しかしながら、このような場合には、素子分離領域１０２の底部に残存する素子分離絶縁膜１０２ｅの残膜が薄くなり、寄生ＭＯＳ効果により、その下に位置するシリコン基板１０１の表面においてリーク電流が発生しやすくなるという問題があった。また、ダミーワード線近傍で残存した内壁酸化膜１０２ｄが薄い場合には、その部分がチャネル領域として働くことから、リーク電流が発生する可能性が高くなるという問題があった。 As described above, when the remaining portion 102f of the inner wall oxide film is formed on the side surface of Si, the effect as a channel region in this portion is hardly exhibited, and there is a problem that the channel does not function as a transistor. Therefore, as shown in FIG. 10D, for the purpose of securing the channel region, it is necessary to dig deeper into the word groove 103b in the element isolation region 102 to increase the height of the fin. However, in such a case, the remaining film of the element isolation insulating film 102e remaining at the bottom of the element isolation region 102 becomes thin, and a leakage current is generated on the surface of the silicon substrate 101 located therebelow due to the parasitic MOS effect. There was a problem that it was easy to do. Further, when the inner wall oxide film 102d remaining in the vicinity of the dummy word line is thin, the portion serves as a channel region, so that there is a problem that the possibility of occurrence of a leakage current is increased.
　本発明者等は上記問題を解決するために鋭意研究を行い、３次元構造を有する半導体装置を製造する工程において、ＳＴＩ構造が形成されたシリコン基板に対し、サドル型フィン部や埋め込みワード線を形成するためのワード溝を形成するにあたり、このワード溝部
の形成途中に露出する活性領域の側面をサイドエッチングすることにより、活性領域の側面に形成されている内壁酸化膜を確実に除去できることを知見した。これにより、ＳＴＩ構造（素子分離絶縁膜）を大きく掘り込まなくても、各フィン部の高さが確保でき、素子分離溝底部に残存する素子分離絶縁膜の厚さも確保できることから、素子分離溝の底面直下のシリコン基板表面におけるリーク電流の発生を防止できることを見出し、本発明を完成させた。 In order to solve the above problems, the present inventors have conducted intensive research, and in the process of manufacturing a semiconductor device having a three-dimensional structure, a saddle type fin portion and a buried word line are formed on a silicon substrate on which an STI structure is formed. The knowledge that the inner wall oxide film formed on the side surface of the active region can be surely removed by side-etching the side surface of the active region exposed during the formation of the word groove portion when forming the word groove for forming. did. As a result, the height of each fin portion can be ensured and the thickness of the element isolation insulating film remaining at the bottom of the element isolation groove can be secured without digging a large STI structure (element isolation insulating film). The present inventors have found that leakage current can be prevented from occurring on the surface of the silicon substrate immediately below the bottom surface of the substrate.
　即ち、本発明の半導体装置の製造方法は、シリコン基板の表層に、第１方向に延在し、該第１方向に交差する第２方向に繰り返し配置される複数の素子分離溝と、該素子分離溝で区画される活性領域を形成する工程と、前記活性領域の側面に内壁酸化膜を形成する工程と、前記素子分離溝を埋め込む素子分離絶縁膜を形成して素子分離領域を形成する工程と、前記活性領域と前記素子分離領域とに跨がって前記第２方向に延在する複数のマスク膜パターンを形成し、該マスク膜パターンの開口部に前記活性領域の上面と前記素子分離領域の上面とを露出させる工程と、前記素子分離領域に上面が露出している前記素子分離絶縁膜を鉛直方向にエッチバックするとともに、前記活性領域の両側面をサイドエッチングすることで前記活性領域の両側面に形成されている前記内壁酸化膜を除去する工程と、前記活性領域に上面が露出している前記シリコン基板をエッチバックすることで、前記素子分離絶縁膜の上面より上方に突出したサドル型フィン部を形成する工程と、を順次備えることを特徴とする。 That is, the method for manufacturing a semiconductor device according to the present invention includes a plurality of element isolation grooves extending in a first direction on a surface layer of a silicon substrate and repeatedly arranged in a second direction intersecting the first direction, and the element Forming an active region partitioned by the isolation trench; forming an inner wall oxide film on a side surface of the active region; and forming an element isolation region by forming an element isolation insulating film filling the element isolation trench A plurality of mask film patterns extending in the second direction across the active region and the element isolation region, and an upper surface of the active region and the element isolation are formed in an opening of the mask film pattern Exposing the upper surface of the region, etching back the element isolation insulating film whose upper surface is exposed in the element isolation region in the vertical direction, and side-etching both side surfaces of the active region to thereby form the active region of A saddle type projecting upward from the upper surface of the element isolation insulating film by removing the inner wall oxide film formed on the side surface and etching back the silicon substrate with the upper surface exposed in the active region And a step of forming fin portions sequentially.
　係る構成の半導体装置の製造方法によれば、サドル型フィン部側面の内壁酸化膜を確実に除去できるので、ＳＴＩ構造を大きく掘り込むことなく各フィン部の高さが確保できる。また、素子分離絶縁膜の過剰な掘り込みを回避することで、素子分離溝の底部に残存する素子分離絶縁膜の厚さを確保できるので、素子分離溝の底面直下に位置するシリコン基板表面を流れるリーク電流の発生を防止することができる。 According to the manufacturing method of the semiconductor device having such a configuration, the inner wall oxide film on the side surface of the saddle type fin portion can be surely removed, so that the height of each fin portion can be ensured without digging a large STI structure. Further, by avoiding excessive digging of the element isolation insulating film, it is possible to secure the thickness of the element isolation insulating film remaining at the bottom of the element isolation groove, so that the surface of the silicon substrate located immediately below the bottom surface of the element isolation groove is formed. Generation of flowing leakage current can be prevented.
本発明の実施形態である半導体装置の製造方法及び半導体装置を示す断面模式図であり、本発明に係る製造方法で得られる半導体装置を上面側から見た平面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a cross-sectional schematic diagram which shows the manufacturing method and semiconductor device of the semiconductor device which are embodiment of this invention, and is the top view which looked at the semiconductor device obtained by the manufacturing method which concerns on this invention from the upper surface side. 本発明の実施形態である半導体装置の製造方法及び半導体装置を示す断面模式図であり、図１中に示すＡ－Ａ'断面図である。FIG. 2 is a schematic cross-sectional view showing the semiconductor device manufacturing method and the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ shown in FIG. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、ウェーハを上面から見た平面図である。It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図３Ａ中に示すＡ－Ａ'断面図である。FIG. 3B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 3A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図３Ａ中に示すＢ－Ｂ'断面図である。FIG. 3B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a BB ′ cross-sectional view illustrated in FIG. 3A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、ウェーハを上面から見た平面図である。It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図４Ａ中に示すＡ－Ａ'断面図である。FIG. 4B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a sectional view taken along the line AA ′ in FIG. 4A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図４Ａ中に示すＢ－Ｂ'断面図である。FIG. 4B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention, and is a BB ′ sectional view shown in FIG. 4A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、ウェーハを上面から見た平面図である。It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図５Ａ中に示すＡ－Ａ'断面図である。FIG. 5B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 5A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図５Ａ中に示すＢ－Ｂ'断面図である。FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention, and is a BB ′ sectional view shown in FIG. 5A; 本発明の実施形態である半導体装置の製造方法を示す工程図であり、ウェーハを上面から見た平面図である。It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図６Ａ中に示すＡ－Ａ'断面図である。FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 6A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図６Ａ中に示すＢ－Ｂ'断面図である。FIG. 6B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the invention, and is a BB ′ sectional view shown in FIG. 6A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、ウェーハを上面から見た平面図である。It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図７Ａ中に示すＡ－Ａ'断面図である。FIG. 7B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a sectional view taken along the line AA ′ in FIG. 7A. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、ウェーハを上面から見た平面図である。It is process drawing which shows the manufacturing method of the semiconductor device which is embodiment of this invention, and is the top view which looked at the wafer from the upper surface. 本発明の実施形態である半導体装置の製造方法を示す工程図であり、図８Ａ中に示すＡ－Ａ'断面図である。FIG. 8B is a process diagram illustrating the manufacturing method of the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view along AA ′ in FIG. 8A. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device.
　以下に、本発明の実施形態である半導体装置の製造方法について、図面を適宜参照しながら説明する。なお、以下の説明において参照する図面は、本実施形態の半導体装置の製造方法を説明する図面であって、図示される各部の大きさや厚さや寸法等は、実際の半導体装置の寸法関係とは異なっている。 Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings as appropriate. The drawings referred to in the following description are drawings for explaining the method of manufacturing the semiconductor device of the present embodiment, and the size, thickness, dimension, etc. of each part shown in the figure are the dimensional relationship of the actual semiconductor device. Is different.
　図１は、本発明を適用した実施形態である半導体装置Ａを模式的に示す平面図であり、図中に示すＸ方向はビット線延在方向（第３方向）、Ｘ方向に傾斜するＸ'方向は活性領域および素子分離領域延在方向（第１方向）、Ｙ方向はワード線延在方向（第２方向）、Ｚ方向は半導体積層方向である。また、図２は、図１の平面図におけるＡ－Ａ線の断面図である。また、図３～図８は、本実施形態の半導体装置の製造方法の主要な工程を模式的に示す工程図である。 FIG. 1 is a plan view schematically showing a semiconductor device A according to an embodiment to which the present invention is applied. The X direction shown in the drawing is a bit line extending direction (third direction), and X is inclined in the X direction. The 'direction is the active region and element isolation region extending direction (first direction), the Y direction is the word line extending direction (second direction), and the Z direction is the semiconductor lamination direction. 2 is a cross-sectional view taken along line AA in the plan view of FIG. 3 to 8 are process diagrams schematically showing main processes of the semiconductor device manufacturing method of the present embodiment.
「半導体装置の構成」
　まず、本実施形態の半導体装置の構成について、ＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）のメモリセルを例に挙げて、以下に説明する。
　図１及び図２に示すように、本実施形態の半導体装置Ａは、素子分離溝２３の内面に内壁酸化膜２４が形成されるとともに、素子分離溝２３内に素子分離絶縁膜２５が形成されることで、Ｘ'方向（第１方向）に延在する活性領域１ａをＹ方向（第２方向）に区画する素子分離領域２が設けられたシャロー・トレンチ・アイソレーション（ＳＴＩ）構造を含むシリコン基板１を備えている。また、活性領域１ａは、複数のシリコンピラー部１２、及び、該シリコンピラー部１２よりも低い高さとされるとともに、Ｙ方向の幅が活性領域１ａパターンのＹ方向の幅よりも狭く形成されることで内壁酸化膜２４が除去された複数のサドル型フィン部１１を備えている。即ち、半導体装置Ａにおいては、シリコンピラー部１２とサドル型フィン部１１とが、活性領域１ａ内において、Ｘ'方向に交互に繰り返し配置されることによって接続されている。また、半導体装置Ａは、複数のピラー型フィン部１２の各々の間に設けられ、ダミー電極を構成する第１埋め込みワード線３１と、複数のサドル型フィン部１１の上面に設けられ、ゲート電極を構成する第２埋め込みワード線３２と、少なくともシリコン基板１上のＳＴＩ構造を覆うように形成される第１層間絶縁膜４上に設けられ、活性領域１ａとビットコンタクトプラグ（ビットコンタクト層）５４を介して接続されるビット線５５とを備え、ビットラインゲート５が構成されている。そして、半導体装置Ａは、ビットラインゲート（ビット線）５及び第１層間絶縁膜４を覆うように形成された第２層間絶縁膜６上に設けられ、活性領域１ａと容量コンタクト層７を介して接続されるキャパシタ８を備え、概略構成されている。本実施形態の半導体装置Ａは、上記構成により、シリコン基板１に含まれるＳＴＩ構造上において、埋め込みゲート型構造のトランジスタが構成されるものである。 "Configuration of semiconductor devices"
First, the configuration of the semiconductor device of this embodiment will be described below by taking a DRAM (Dynamic Random Access Memory) memory cell as an example.
As shown in FIGS. 1 and 2, in the semiconductor device A of the present embodiment, an inner wall oxide film 24 is formed on the inner surface of the element isolation groove 23 and an element isolation insulating film 25 is formed in the element isolation groove 23. Thus, a shallow trench isolation (STI) structure including an element isolation region 2 that partitions the active region 1a extending in the X ′ direction (first direction) in the Y direction (second direction) is included. A silicon substrate 1 is provided. The active region 1a has a plurality of silicon pillars 12 and a height lower than that of the silicon pillars 12, and the width in the Y direction is narrower than the width in the Y direction of the active region 1a pattern. Thus, a plurality of saddle type fin portions 11 from which the inner wall oxide film 24 has been removed are provided. That is, in the semiconductor device A, the silicon pillar portions 12 and the saddle-type fin portions 11 are connected by being repeatedly arranged in the X ′ direction in the active region 1a. The semiconductor device A is provided between each of the plurality of pillar-type fin portions 12 and is provided on the upper surface of the first embedded word line 31 constituting the dummy electrode and the plurality of saddle-type fin portions 11, and the gate electrode Are provided on the first interlayer insulating film 4 formed so as to cover at least the STI structure on the silicon substrate 1, and the active region 1 a and the bit contact plug (bit contact layer) 54. And a bit line 55 connected to each other through the bit line gate 5. The semiconductor device A is provided on the second interlayer insulating film 6 formed so as to cover the bit line gate (bit line) 5 and the first interlayer insulating film 4, and the active region 1a and the capacitive contact layer 7 are interposed therebetween. The capacitor 8 is generally connected. The semiconductor device A according to the present embodiment is configured such that a transistor having a buried gate type structure is formed on the STI structure included in the silicon substrate 1 by the above configuration.
　図１に示す例においては、メモリセル領域において、Ｘ方向（ビット線方向）に傾きを有してＸ'方向に直線で延在する素子分離領域２と、素子分離領域２に隣接してＸ'方向に直線で延在する活性領域１ａとが、等ピッチ間隔でＹ方向（ワード線方向）に繰り返し配置されている。活性領域１ａは、素子分離領域２によってＹ方向で電気的に分離されている。ここで、素子分離領域２と活性領域１ａのＹ方向の上面幅は同じであっても良いし、あるいは、素子分離領域２の上面幅が活性領域１ａの上面幅よりも小さく構成されていても良い。 In the example shown in FIG. 1, in the memory cell region, an element isolation region 2 having a slope in the X direction (bit line direction) and extending in a straight line in the X ′ direction, and an X adjacent to the element isolation region 2 The active regions 1a extending linearly in the 'direction are repeatedly arranged in the Y direction (word line direction) at equal pitch intervals. The active region 1a is electrically isolated in the Y direction by the element isolation region 2. Here, the upper surface width in the Y direction of the element isolation region 2 and the active region 1a may be the same, or the upper surface width of the element isolation region 2 may be smaller than the upper surface width of the active region 1a. good.
　また、複数の素子分離領域２および複数の活性領域１ａに跨って、Ｙ方向に直線で延在し、ゲート電極をなす第２埋め込みワード線３２（以下、単にワード線と略称することがある）が設けられ、さらに、ダミー電極をなす第１埋め込みワード線（以下、ダミーワード線と称することがある）３１が配置されている。図１中においては、一部の構成が省略されているが、隣接する二つのダミーワード線３１の間に２本のワード線３２が均等間隔で配置されている。即ち、各々のダミーワード線３１及びワード線３２は、同一の幅及び間隔で配置されている。 A second embedded word line 32 that extends in a straight line in the Y direction across the plurality of element isolation regions 2 and the plurality of active regions 1a and forms a gate electrode (hereinafter sometimes simply referred to as a word line). Further, a first buried word line (hereinafter also referred to as a dummy word line) 31 forming a dummy electrode is disposed. In FIG. 1, a part of the configuration is omitted, but two word lines 32 are arranged at equal intervals between two adjacent dummy word lines 31. That is, the dummy word lines 31 and the word lines 32 are arranged with the same width and interval.
　本実施形態の半導体装置Ａは、各々のワード線の直下に位置するシリコン基板１の表面にサドル型フィン部１１が形成され、各々のワード線の間にシリコンピラー部１２が配置される構成とされている。 The semiconductor device A according to the present embodiment has a configuration in which a saddle-type fin portion 11 is formed on the surface of the silicon substrate 1 located immediately below each word line, and a silicon pillar portion 12 is disposed between each word line. Has been.
　ダミーワード線３１は、ワード線３２と同じ材料で構成されるが、各々のワード線３２は対応するトランジスタのゲート電極として機能するのに対し、ダミーワード線３１は、該ダミーワード線３１の両側に隣接するトランジスタを電気的に分離する素子分離機能を有する。これにより、活性領域１ａは、Ｙ方向（ワード線方向）に素子分離領域２で絶縁分離され、延在するＸ'方向（略ビット線方向）にダミーワード線３１で絶縁分離されることで、独立した島状活性領域を構成する。ここで、本実施形態においては、説明を容易にするため、隣接するダミーワード線３１をＸ方向（ビット線方向）に向かって３１Ａ、３１Ｂ、３１Ｃ、 ワード線３２をＸ方向に向かって３２Ａ、３２Ｂ、３２Ｃと称する。 The dummy word line 31 is made of the same material as the word line 32, but each word line 32 functions as a gate electrode of a corresponding transistor, whereas the dummy word line 31 has both sides of the dummy word line 31. Has an element isolation function for electrically isolating adjacent transistors. As a result, the active region 1a is insulated and isolated by the element isolation region 2 in the Y direction (word line direction) and by the dummy word line 31 in the extending X ′ direction (substantially bit line direction). It constitutes an independent island-like active region. Here, in this embodiment, for ease of explanation, the adjacent dummy word lines 31 are directed in the X direction (bit line direction) 31A, 31B, 31C, and the word line 32 is directed in the X direction 32A. They are called 32B and 32C.
　Ｘ'方向に延在する一つの島状活性領域は、ダミーワード線３１Ａとダミーワード線３１Ｂで挟まれる構成とされる。さらに、ダミーワード線３１Ａとワード線３２Ａに隣接する容量コンタクト接続領域１ｄと、ワード線３２Ａとワード線３２Ｂに隣接するビットコンタクト接続領域１ｅと、ワード線３２Ｂとダミーワード線３１Ｂに隣接する他方の容量コンタクト接続領域１ｄとで構成されている。これにより、ダミーワード線３１Ａに隣接する一方の容量コンタクト接続領域１ｄと、一方のワード線３２Ａと、ビットコンタクト接続領域１ｅとで一つのトランジスタＴｒ１が構成される。また、ビットコンタクト接続領域１ｅと、他方のワード線３２Ｂと、ダミーワード線３１Ｂに隣接する他方の容量コンタクト接続領域１ｄとで他の一つのトランジスタＴｒ１が構成される。従って、ビットコンタクト接続領域１ｅは、二つのトランジスタＴｒ１で共有される構成とされている。また、上記の容量コンタクト接続領域１ｄ及びビットコンタクト接続領域１ｅは、シリコンピラー部１２で構成される。 One island-like active region extending in the X ′ direction is sandwiched between the dummy word line 31A and the dummy word line 31B. Furthermore, the capacitor contact connection region 1d adjacent to the dummy word line 31A and the word line 32A, the bit contact connection region 1e adjacent to the word line 32A and the word line 32B, and the other adjacent to the word line 32B and the dummy word line 31B. And a capacitor contact connection region 1d. Thus, one capacitor contact region 1d adjacent to the dummy word line 31A, one word line 32A, and the bit contact connection region 1e constitute one transistor Tr1. The bit contact connection region 1e, the other word line 32B, and the other capacitor contact connection region 1d adjacent to the dummy word line 31B constitute another transistor Tr1. Accordingly, the bit contact connection region 1e is configured to be shared by the two transistors Tr1. The capacitor contact connection region 1d and the bit contact connection region 1e are configured by the silicon pillar portion 12.
　また、各々のビットコンタクト接続領域１ｅ上にはビットコンタクトプラグ５３が設けられ、各々のビットコンタクトプラグ（ビットコンタクト層）５４に接続してＸ方向に延在するビット線５５が配置されることで、ビットラインゲート５が構成されている。また、各々の容量コンタクト接続領域１ｄ上には容量コンタクト７が設けられ、各々の容量コンタクト７上にはキャパシタ（図１中では図示せず）が設けられている。 Further, a bit contact plug 53 is provided on each bit contact connection region 1e, and a bit line 55 extending in the X direction by connecting to each bit contact plug (bit contact layer) 54 is disposed. A bit line gate 5 is configured. Further, a capacitor contact 7 is provided on each capacitor contact connection region 1d, and a capacitor (not shown in FIG. 1) is provided on each capacitor contact 7.
　次に、図２の断面図に示すように、シリコン基板１の表面には、同じ幅及び間隔で形成された複数のワード溝３内に、ゲート絶縁膜を介してゲート電極を兼ねるワード線が各々埋設されている。より具体的には、同じ幅及び間隔で形成された第１ワード溝３Ａ及び第２ワード溝３Ｂの各々の内部に、シリコン酸化膜からなるゲート絶縁膜３ｃを介してメタルからなるワード線３ｄが各々埋設されている。そして、ワード線３ｄの上面を覆うようにキャップ絶縁膜３ｅが埋設されている。また、第１ワード溝３Ａ内にはダミーワード線３１が配置され、第２ワード溝３Ｂ内にワード線３２が配置される。 Next, as shown in the cross-sectional view of FIG. 2, word lines that also serve as gate electrodes are formed on the surface of the silicon substrate 1 through a gate insulating film in a plurality of word grooves 3 formed with the same width and interval. Each is buried. More specifically, a word line 3d made of metal is inserted into each of the first word groove 3A and the second word groove 3B formed with the same width and interval through a gate insulating film 3c made of a silicon oxide film. Each is buried. A cap insulating film 3e is buried so as to cover the upper surface of the word line 3d. A dummy word line 31 is disposed in the first word groove 3A, and a word line 32 is disposed in the second word groove 3B.
　上記のダミーワード線３１及びワード線３２の材料としては、例えば、窒化チタン膜、チタン膜、窒化タングステン膜、タングステン膜等の高融点金属膜等を用いることができ、これらの材料を単層あるいは積層膜として、適宜選択することが可能である。 As the material of the dummy word line 31 and the word line 32, for example, a refractory metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, or a tungsten film can be used. The laminated film can be selected as appropriate.
　また、図２に示す例では、キャップ絶縁膜３ｅを覆うように、第１層間絶縁膜４が設けられている。隣接する二つのワード線３２Ａ、３２Ｂ間に位置する活性領域１ａからなるビットコンタクト接続領域１ｅの上面には、第１層間絶縁膜４を貫通するビットコンタクトプラグ（ビットコンタクト層）５４が配置される。さらに、その上面に接続され、Ｘ方向に延在するビット線５５が積層配置され、配線を構成している。ビット線５５の上面及び側壁には、シリコン窒化膜からなるサイドウォール絶縁膜５６が設けられ、ビットコンタクトプラグ５４とビット線５５及びサイドウォール絶縁膜５６でメモリセル領域のビットラインゲート５を構成している。 In the example shown in FIG. 2, a first interlayer insulating film 4 is provided so as to cover the cap insulating film 3e. A bit contact plug (bit contact layer) 54 penetrating the first interlayer insulating film 4 is disposed on the upper surface of the bit contact connection region 1e formed of the active region 1a located between two adjacent word lines 32A and 32B. . Further, bit lines 55 connected to the upper surface and extending in the X direction are arranged in a stacked manner to constitute a wiring. A side wall insulating film 56 made of a silicon nitride film is provided on the upper surface and side wall of the bit line 55, and the bit contact plug 54, the bit line 55, and the side wall insulating film 56 constitute the bit line gate 5 in the memory cell region. ing.
　ビット線５５を構成する各部材の材料としては、例えば、窒化チタン膜、チタン膜、窒化タングステン膜、タングステンシリサイド膜、タングステン膜等の高融点金属膜等を用いることができ、これらの材料を単層あるいは積層膜として、適宜選択することが可能である。 As a material of each member constituting the bit line 55, for example, a refractory metal film such as a titanium nitride film, a titanium film, a tungsten nitride film, a tungsten silicide film, or a tungsten film can be used. A layer or a laminated film can be appropriately selected.
　また、半導体装置Ａは、ビットラインゲート５を覆うように、シリコン基板１上の全面にシリコン酸化膜からなる第２層間絶縁膜６が設けられている。また、容量コンタクト接続領域１ｄとなる活性領域１ａの上面には、第２層間絶縁膜６及び第１層間絶縁膜４を貫通して容量コンタクトプラグ（容量コンタクト層）７が接続されている。また、容量コンタクトプラグ７の上面を含む全面には、シリコン窒化膜からなるストッパー膜９とシリコン酸化膜からなる第３層間絶縁膜１３が設けられている。 Further, in the semiconductor device A, a second interlayer insulating film 6 made of a silicon oxide film is provided on the entire surface of the silicon substrate 1 so as to cover the bit line gate 5. Further, a capacitor contact plug (capacitor contact layer) 7 is connected to the upper surface of the active region 1 a serving as the capacitor contact connection region 1 d through the second interlayer insulating film 6 and the first interlayer insulating film 4. A stopper film 9 made of a silicon nitride film and a third interlayer insulating film 13 made of a silicon oxide film are provided on the entire surface including the upper surface of the capacitor contact plug 7.
　さらに、容量コンタクトプラグ７の上面に到達するように、第３層間絶縁膜１３とストッパー膜９を貫通するシリンダーホール８ａが開口しており、シリンダーホール８ａの内壁と底部を覆うように下部電極８ｂが設けられている。これにより、下部電極８ｂが、容量コンタクトプラグ７の上面に接続している。また、下部電極表面８ｂを覆うように、容量絶縁膜８ｃ及び上部電極８ｄが設けられ、下部電極８ｂ、容量絶縁膜８ｃ及び上部電極８ｄにより、キャパシタ８を構成している。 Further, a cylinder hole 8a penetrating the third interlayer insulating film 13 and the stopper film 9 is opened so as to reach the upper surface of the capacitor contact plug 7, and the lower electrode 8b is covered so as to cover the inner wall and the bottom of the cylinder hole 8a. Is provided. As a result, the lower electrode 8 b is connected to the upper surface of the capacitor contact plug 7. A capacitor insulating film 8c and an upper electrode 8d are provided so as to cover the lower electrode surface 8b, and the capacitor 8 is configured by the lower electrode 8b, the capacitor insulating film 8c, and the upper electrode 8d.
　また、半導体装置Ａは、キャパシタ８を覆うように第４層間絶縁膜１４が設けられており、さらに、第４層間絶縁膜１４を貫通して配線コンタクト１５が設けられ、配線コンタクト１５上面には配線層１６が接続されている。
　そして、配線層１６及び第４層間絶縁膜１４を覆うように、保護絶縁膜１７が全面に設けられている。 In addition, the semiconductor device A is provided with a fourth interlayer insulating film 14 so as to cover the capacitor 8, and further, a wiring contact 15 is provided through the fourth interlayer insulating film 14. The wiring layer 16 is connected.
A protective insulating film 17 is provided on the entire surface so as to cover the wiring layer 16 and the fourth interlayer insulating film 14.
　上述したように、本実施形態の半導体装置Ａは、素子分離溝２３に内壁酸化膜２４が形成され、且つ、素子分離溝２３に素子分離絶縁膜２５が形成されることで素子分離領域２が設けられたＳＴＩ構造を有するシリコン基板１上に、複数のピラー型フィン部１２、及び、該ピラー型フィン部１２よりも低い高さとされるとともに、Ｙ方向の幅を狭く形成することで内壁酸化膜２４が除去された複数のサドル型フィン部１１を有する構成とされている。半導体装置Ａによれば、上記構成により、素子分離溝２３の底面直下に位置するシリコン基板１の表面を流れるリーク電流の発生が防止され、優れた素子特性が得られる。 As described above, in the semiconductor device A of this embodiment, the inner wall oxide film 24 is formed in the element isolation groove 23 and the element isolation insulating film 25 is formed in the element isolation groove 23, so that the element isolation region 2 is formed. On the provided silicon substrate 1 having an STI structure, a plurality of pillar-type fin portions 12 and a height lower than that of the pillar-type fin portions 12 and a narrow width in the Y direction are formed to oxidize the inner wall. The structure includes a plurality of saddle-type fin portions 11 from which the film 24 has been removed. According to the semiconductor device A, with the above configuration, generation of a leakage current flowing on the surface of the silicon substrate 1 located immediately below the bottom surface of the element isolation groove 23 is prevented, and excellent element characteristics can be obtained.
「半導体装置の製造方法」
　次に、本実施形態の半導体装置Ａの製造方法について、図３～図８（必要に応じて図１、２も参照）を用いて以下に説明する。なお、図３～図６の各々におけるＢ図（図３Ｂ、図４Ｂ、図５Ｂ、図６Ｂ）は、説明を容易にするため、各々の平面図を示すＡ図（図３Ａ、図４Ａ、図５Ａ、図６Ａ）におけるＡ－Ａ'断面図を示している。ここで、これら図３～図６におけるＡ－Ａ'断面図は、図２のＡ－Ａ'断面図とは方向が異なっているので、注意が必要である。
　また、本実施形態で用いるシリコン基板１は、ｐ型の単結晶基板とする。 "Manufacturing method of semiconductor device"
Next, a method for manufacturing the semiconductor device A of this embodiment will be described below with reference to FIGS. 3 to 8 (see also FIGS. 1 and 2 as necessary). 3 to 6 are shown in FIG. 3A, FIG. 4B, FIG. 6B, and FIG. 3A, FIG. 4A, FIG. FIG. 5A shows a cross-sectional view along AA ′ in FIG. 6A). Here, the AA ′ cross-sectional views in FIGS. 3 to 6 are different in direction from the AA ′ cross-sectional view in FIG. 2, so care should be taken.
The silicon substrate 1 used in this embodiment is a p-type single crystal substrate.
　本実施形態の半導体装置Ａの製造方法は、シリコン基板１の表層に、Ｘ'方向（第１方向）に延在し、このＸ'方向に交差するＹ方向（第２方向）に繰り返し配置される複数の素子分離溝２３と、この素子分離溝２３で区画される活性領域１ａを形成する工程と、この活性領域１ａの側面に内壁酸化膜２４を形成する工程と、素子分離溝２３を埋め込む素子分離絶縁膜２５を形成して素子分離領域２を形成する工程と、活性領域１ａと素子分離領域２とに跨がってＹ方向（第２方向）に延在する複数のマスク膜パターンを形成し、このマスク膜パターンの開口部に活性領域１ａの上面と素子分離領域２の上面とを露出させる工程と、素子分離領域２に上面が露出している素子分離絶縁膜２５を鉛直方向にエッチバックするとともに、活性領域１ａの両側面をサイドエッチングすることで活性領域１ａの両側面に形成されている内壁酸化膜２４を除去する工程と、活性領域１ａに上面が露出しているシリコン基板１をエッチバックすることで、素子分離絶縁膜２５の上面より上方に突出したサドル型フィン部１１を形成する工程と、を順次備える方法とされている。 The manufacturing method of the semiconductor device A of the present embodiment is repeatedly arranged in the Y direction (second direction) extending in the X ′ direction (first direction) on the surface layer of the silicon substrate 1 and intersecting the X ′ direction. A plurality of element isolation trenches 23, a step of forming an active region 1a partitioned by the element isolation trenches 23, a step of forming an inner wall oxide film 24 on the side surface of the active region 1a, and embedding the element isolation trenches 23. A step of forming the element isolation insulating film 25 to form the element isolation region 2, and a plurality of mask film patterns extending in the Y direction (second direction) across the active region 1a and the element isolation region 2 Forming and exposing the upper surface of the active region 1a and the upper surface of the element isolation region 2 in the opening of the mask film pattern, and the element isolation insulating film 25 having the upper surface exposed in the element isolation region 2 in the vertical direction Etch back and active area a step of removing the inner wall oxide film 24 formed on both side surfaces of the active region 1a by side-etching both side surfaces of a, and etching back the silicon substrate 1 whose upper surface is exposed in the active region 1a. And a step of forming the saddle-type fin portion 11 protruding upward from the upper surface of the element isolation insulating film 25.
　また、本実施形態の製造方法は、より具体的には、以下に示す各工程（１）～（５）を順次備えた方法とすることができる。
（１）シリコン基板１上に図示略のマスク絶縁膜及び第１レジストマスクを順次形成し、この第１レジストマスクを用いてシリコン基板１及びマスク絶縁膜をエッチングすることで、Ｘ'方向（第１方向）に延在する素子分離領域２の形成予定領域に沿ったラインアンドスペースパターンで素子分離溝２３を形成した後、この素子分離溝２３の内面に内壁酸化膜２４を形成するとともに、素子分離溝２３に絶縁材料を充填して素子分離絶縁膜２５を形成することによって活性領域１ａを区画するための素子分離領域２を形成し、シャロー・トレンチ・アイソレーション（ＳＴＩ）構造を形成するＳＴＩ工程。
（２）シリコン基板１上にマスク窒化膜３ａ及び第２レジストマスクＲを順次形成した後、この第２レジストマスクＲを用いてシリコン基板１上における素子分離領域２及び活性領域１ａをエッチング除去することにより、Ｘ'方向（第１方向）と交差してＹ方向（第２方向）に延在する複数のワード溝３を同時に形成する際、素子分離領域２に上面が露出する素子分離絶縁膜２５を鉛直下方に掘り下げるとともに、活性領域１ａの両側面をサイドエッチしてＹ方向（第２方向）の幅を縮退させることで、活性領域１ａの側壁に形成された内壁酸化膜２４を除去し、掘り下げられた素子分離絶縁膜２５の上面よりも上方にシリコン基板１を突出させてサドル型フィン部１１を形成するフィン部形成工程。
（３）さらに、ワード溝３内に露出するサドル型フィン部１１の上面を選択的にエッチングして掘り下げることにより、サドル型フィン部１１の高さを制御する掘り込み工程。
（４）複数のワード溝３の底面上に導電材料を堆積させた後、この導電材料の一部をエッチング除去し、複数のワード溝３の底面に前記導電材料を残存させることにより、第１埋め込みワード線３１及び第２埋め込みワード線３２を形成する埋め込みワード線形成工程。
（５）第１ワード溝３Ａ及び第２ワード溝３Ｂに絶縁材料を充填して、第１埋め込みワード線３１及び第２埋め込みワード線３２を埋め込むことにより、埋め込みキャップ絶縁膜３ｅを形成するキャップ形成工程。 In addition, more specifically, the manufacturing method of the present embodiment can be a method that sequentially includes the following steps (1) to (5).
(1) A mask insulating film and a first resist mask (not shown) are sequentially formed on the silicon substrate 1, and the silicon substrate 1 and the mask insulating film are etched using the first resist mask, so that the X ′ direction (first After element isolation trenches 23 are formed in a line-and-space pattern along a region to be formed of element isolation regions 2 extending in one direction), an inner wall oxide film 24 is formed on the inner surface of the element isolation trenches 23. An isolation region 2 for partitioning the active region 1a is formed by filling the isolation trench 23 with an insulating material to form an isolation isolation film 25, and an STI for forming a shallow trench isolation (STI) structure. Process.
(2) After the mask nitride film 3a and the second resist mask R are sequentially formed on the silicon substrate 1, the element isolation region 2 and the active region 1a on the silicon substrate 1 are removed by etching using the second resist mask R. Thus, an element isolation insulating film whose upper surface is exposed in the element isolation region 2 when simultaneously forming a plurality of word grooves 3 that intersect the X ′ direction (first direction) and extend in the Y direction (second direction). 25, the inner wall oxide film 24 formed on the side wall of the active region 1a is removed by side-etching both side surfaces of the active region 1a to reduce the width in the Y direction (second direction). A fin part forming step of forming the saddle type fin part 11 by projecting the silicon substrate 1 above the upper surface of the deeply-isolated element isolation insulating film 25.
(3) Further, a digging step for controlling the height of the saddle type fin portion 11 by selectively etching and digging up the upper surface of the saddle type fin portion 11 exposed in the word groove 3.
(4) After depositing a conductive material on the bottom surfaces of the plurality of word grooves 3, a part of the conductive material is removed by etching, and the conductive material is left on the bottom surfaces of the plurality of word grooves 3. A buried word line forming step for forming the buried word line 31 and the second buried word line 32;
(5) Cap formation for forming a buried cap insulating film 3e by filling the first word groove 3A and the second word groove 3B with an insulating material and embedding the first buried word line 31 and the second buried word line 32. Process.
　さらに、本実施形態の製造方法では、上記（１）～（５）の工程に加え、ビット線を形成する工程や、キャパシタを形成する工程、配線層を形成する工程等を備えた方法とすることができる。 Furthermore, the manufacturing method of the present embodiment is a method including a step of forming a bit line, a step of forming a capacitor, a step of forming a wiring layer, etc. in addition to the steps (1) to (5). be able to.
　本実施形態では、特に、上記のフィン部形成工程において、素子分離絶縁膜２５を鉛直下方に掘り下げるとともに、活性領域１ａの側面をサイドエッチングすることによって内壁酸化膜２４を除去する方法を採用することで、内壁酸化膜２４を残存させることなく、サドル型フィン部１１を形成することが可能になる。 In the present embodiment, in particular, in the above-described fin portion forming step, a method is employed in which the element isolation insulating film 25 is dug down vertically and the inner wall oxide film 24 is removed by side etching the side surface of the active region 1a. Thus, the saddle type fin portion 11 can be formed without leaving the inner wall oxide film 24.
　以下、本実施形態の製造方法に備えられる上記（１）～（５）の各工程、及び、これに引き続いて行われる各工程について具体的に説明する。 Hereinafter, the steps (1) to (5) provided in the manufacturing method of the present embodiment and the steps performed subsequently will be specifically described.
＜（１）ＳＴＩ工程＞
　本実施形態のＳＴＩ工程について、図３Ａ～図３Ｃを参照しながら説明する。
　ＳＴＩ工程では、まず、シリコン基板１上に厚さ２ｎｍのパッドシリコン酸化膜と厚さ５０ｎｍのシリコン窒化膜を積層形成する。
　次に、リソグラフィ技術を用いて、シリコン窒化膜上に、Ｘ'方向（第１方向）に延在する複数のホトレジストパターンを形成する。このホトレジストパターンは、例えば、Ｙ方向の幅が４０ｎｍ、間隔が４０ｎｍとなるラインパターンで形成する。
　次に、ホトレジストパターンをマスクとして、下層のシリコン窒化膜及びパッドシリコン酸化膜を異方性ドライエッチングし、パターンを転写する。これにより、シリコン基板１の上面が露出する。 <(1) STI process>
The STI process of this embodiment will be described with reference to FIGS. 3A to 3C.
In the STI process, first, a pad silicon oxide film having a thickness of 2 nm and a silicon nitride film having a thickness of 50 nm are stacked on the silicon substrate 1.
Next, a plurality of photoresist patterns extending in the X ′ direction (first direction) are formed on the silicon nitride film by using a lithography technique. This photoresist pattern is formed, for example, as a line pattern having a width in the Y direction of 40 nm and an interval of 40 nm.
Next, using the photoresist pattern as a mask, the underlying silicon nitride film and pad silicon oxide film are anisotropically dry etched to transfer the pattern. Thereby, the upper surface of the silicon substrate 1 is exposed.
　次に、ホトレジストパターンを除去し、シリコン窒化膜をマスクとして、上面が露出している部分のシリコン基板１を異方性ドライエッチングし、素子分離溝２３を形成する。この素子分離溝２３のシリコン基板１の上面からの深さは、例えば２５０ｎｍとする。また、この際の異方性ドライエッチングには、例えば、臭化水素（ＨＢｒ）と塩素（Ｃｌ２）と酸素（Ｏ２）との混合ガスプラズマを用いる。
　上記工程により、図３Ｃに示すように、素子分離溝２３の形成によって活性領域１ａがＹ方向（第２方向）に区画され、素子分離溝２３の側面、すなわち活性領域１ａを構成する第１側面１ｂ及び第２側面１ｃが形成される。この第１側面１ｂ及び第２側面１ｃは、第２の方向に対向し、活性領域１ａを挟んで第１方向に延在するように形成される。
　なお、第１側面１ｂ及び第２側面１ｃは、後の工程で活性領域１ａに形成されるトランジスタの特性を悪化させないために、シリコン基板１からなる活性領域１ａ側にわずかに傾斜するように形成される。即ち、対向する第１側面１ｂ及び第２側面１ｃの上方の幅は下方の幅よりも狭く形成されている。この傾斜角は、８５°以上で９０°より小さい範囲とする。 Next, the photoresist pattern is removed, and using the silicon nitride film as a mask, the portion of the silicon substrate 1 where the upper surface is exposed is subjected to anisotropic dry etching to form an element isolation groove 23. The depth of the element isolation groove 23 from the upper surface of the silicon substrate 1 is, for example, 250 nm. In this case, for example, a mixed gas plasma of hydrogen bromide (HBr), chlorine (Cl 2 ), and oxygen (O 2 ) is used for the anisotropic dry etching.
3C, the active region 1a is partitioned in the Y direction (second direction) by the formation of the element isolation groove 23, and the side surface of the element isolation groove 23, that is, the first side surface constituting the active region 1a. 1b and the second side surface 1c are formed. The first side surface 1b and the second side surface 1c are formed to face the second direction and extend in the first direction with the active region 1a interposed therebetween.
The first side surface 1b and the second side surface 1c are formed so as to be slightly inclined toward the active region 1a made of the silicon substrate 1 so as not to deteriorate the characteristics of the transistor formed in the active region 1a in a later step. Is done. That is, the upper width of the opposing first side surface 1b and second side surface 1c is formed narrower than the lower width. The inclination angle is in a range of 85 ° or more and less than 90 °.
　次いで、マスクとして用いたシリコン窒化膜を残した状態で第１側面１ｂ及び第２側面１ｃを含む素子分離溝２３の内面を、従来公知の方法で熱酸化することにより、例えば、厚さが２ｎｍのシリコン酸化膜からなる内壁酸化膜２４を形成する。そして、素子分離溝２３内を埋め込むように、シリコン基板１上の全面に、ＣＶＤ法によってシリコン窒化膜からなる埋設絶縁材料の膜を形成する。この埋設絶縁材料としては、シリコン窒化膜に限らず、ＣＶＤ法や回転塗布法で形成するシリコン酸化膜を用いることができる。また、シリコン窒化膜と上記シリコン酸化膜の積層膜で形成しても良い。 Next, the inner surface of the element isolation groove 23 including the first side surface 1b and the second side surface 1c is left thermally oxidized by a conventionally known method with the silicon nitride film used as a mask remaining, for example, a thickness of 2 nm. An inner wall oxide film 24 made of a silicon oxide film is formed. Then, a buried insulating material film made of a silicon nitride film is formed by CVD on the entire surface of the silicon substrate 1 so as to fill the element isolation trench 23. The buried insulating material is not limited to a silicon nitride film, and a silicon oxide film formed by a CVD method or a spin coating method can be used. Further, it may be formed of a laminated film of a silicon nitride film and the silicon oxide film.
　次に、上記の埋設絶縁材料として用いたシリコン窒化膜と、マスクとして用いたシリコン窒化膜を同時にエッチバックして除去する。この際、埋設絶縁材料にシリコン酸化膜を用いた場合でも同じ手法で除去することができる。これにより、素子分離溝２３内には、シリコン基板１の上面と面一となる上面を有する素子分離絶縁膜２５が充填される。このような素子分離絶縁膜２５を充填することにより、第１方向に延在する複数の素子分離領域２が形成される。また、素子分離領域２によってＹ方向に区画されるとともに、Ｙ方向に対向する第１側面１ｂ及び第２側面１ｃを有して第１方向に延在する複数の活性領域１ａが形成される。これにより、活性領域１ａの上面におけるＹ方向の幅（上面幅）Ｗ１は、例えば、４０ｎｍ程度となる。また、素子分離領域２は、ＳＴＩ構造で構成され、Ｙ方向の上面幅は４０ｎｍとなり、活性領域１ａの上面幅と等しくなる。なお、ここでは、ホトレジストパターンのＹ方向の幅及び間隔を、何れも４０ｎｍとして形成しているが、これに限るものではなく、間隔を４０ｎｍよりも小さくしても良い。即ち、素子分離領域２のＹ方向の上面幅が活性領域１ａのＹ方向の上面幅より小さくなるように形成しても良い。これにより、メモリセルの平面面積を縮小化できる利点がある。 Next, the silicon nitride film used as the buried insulating material and the silicon nitride film used as the mask are simultaneously etched back and removed. At this time, even when a silicon oxide film is used as the buried insulating material, it can be removed by the same method. As a result, the element isolation trench 23 is filled with the element isolation insulating film 25 having an upper surface that is flush with the upper surface of the silicon substrate 1. By filling such an element isolation insulating film 25, a plurality of element isolation regions 2 extending in the first direction are formed. In addition, a plurality of active regions 1 a that are partitioned in the Y direction by the element isolation region 2 and that have the first side surface 1 b and the second side surface 1 c facing in the Y direction and extend in the first direction are formed. Thereby, the width (upper surface width) W1 in the Y direction on the upper surface of the active region 1a is, for example, about 40 nm. The element isolation region 2 has an STI structure, and the upper surface width in the Y direction is 40 nm, which is equal to the upper surface width of the active region 1a. Here, the width and interval in the Y direction of the photoresist pattern are both set to 40 nm, but the present invention is not limited to this, and the interval may be made smaller than 40 nm. That is, the upper surface width in the Y direction of the element isolation region 2 may be formed to be smaller than the upper surface width in the Y direction of the active region 1a. This has the advantage that the planar area of the memory cell can be reduced.
　上述したように、本実施形態における素子分離領域２は、シリコン基板１からなる活性領域１ａとの境界、すなわち第１側面１ｂ及び第２側面１ｃに熱酸化法で形成されるシリコン酸化膜からなる内壁酸化膜２４を備え、さらに、内壁酸化膜２４を覆う素子分離絶縁膜２５を備える構造を有する。 As described above, the element isolation region 2 in the present embodiment is formed of a silicon oxide film formed on the boundary with the active region 1a formed of the silicon substrate 1, that is, the first side surface 1b and the second side surface 1c by the thermal oxidation method. The structure includes an inner wall oxide film 24 and an element isolation insulating film 25 that covers the inner wall oxide film 24.
＜（２）フィン部形成工程＞
　次に、図４Ａ～図４Ｃを参照してフィン部形成工程について説明する。
　フィン部形成工程では、まず、シリコン基板１上に、マスク膜３ａを形成した後、この上に、リソグラフィ技術を用いて第２ホトレジストマスクＲを形成する。なお、マスク膜３ａは、非晶質カーボン膜とシリコン酸化膜等の材料で構成することができる。第２ホトレジストマスクＲは、第１方向（Ｘ'方向）に交差する第２の方向（Ｙ方向）に延在し、複数の活性領域１ａと複数の素子分離領域２に跨る複数のラインパターンで形成される。第２ホトレジストマスクＲの、Ｙ方向に垂直なＸ方向（第３方向）の幅および間隔は、例えば、各々４０ｎｍとする。 <(2) Fin part formation process>
Next, the fin part forming step will be described with reference to FIGS. 4A to 4C.
In the fin portion forming step, first, a mask film 3a is formed on the silicon substrate 1, and then a second photoresist mask R is formed thereon using a lithography technique. The mask film 3a can be made of a material such as an amorphous carbon film and a silicon oxide film. The second photoresist mask R extends in a second direction (Y direction) intersecting the first direction (X ′ direction) and has a plurality of line patterns extending over the plurality of active regions 1 a and the plurality of element isolation regions 2. It is formed. The width and interval of the second photoresist mask R in the X direction (third direction) perpendicular to the Y direction are each 40 nm, for example.
　次に、第２ホトレジストマスクＲをマスクとした異方性ドライエッチング法により、下層のマスク膜３ａをエッチングしてマスクパターンを転写する。これにより、第２の方向（Ｙ方向）に延在する複数のマスク膜３ａの間（開口部３ｂ）には、Ｙ方向に繰り返し配置された活性領域１ａの上面と素子分離領域２の上面（内壁酸化膜２４の上面と素子分離絶縁膜２５の上面）が露出する。
　その後、第２ホトレジストマスクＲを除去する。 Next, the lower mask film 3a is etched by an anisotropic dry etching method using the second photoresist mask R as a mask to transfer the mask pattern. Thus, between the plurality of mask films 3a extending in the second direction (Y direction) (opening 3b), the upper surface of the active region 1a and the upper surface of the element isolation region 2 (repeatedly arranged in the Y direction) The upper surface of the inner wall oxide film 24 and the upper surface of the element isolation insulating film 25 are exposed.
Thereafter, the second photoresist mask R is removed.
　次いで、マスク膜３ａをマスクとして、上面が露出している活性領域１ａ及び素子分離領域２を異方性ドライエッチングし、第１ワード溝３Ａと第２ワード溝３Ｂを同時に形成する。ここでは、最初に素子分離領域２を異方性ドライエッチングし、その後、活性領域１ａを異方性ドライエッチングする方法を用いる。一方、活性領域１ａをエッチングした後、素子分離領域２をエッチングする方法は好ましくない。その理由としては、上述のように、活性領域１ａを構成する第１側面１ｂ及び第２側面１ｃが、活性領域１ａ側にわずかに傾斜するように形成されているため、活性領域１ａを先に異方性ドライエッチングすると、第１側面１ｂ及び第２側面１ｃのＺ方向に沿って形成されている素子分離絶縁膜２５がエッチングのマスクとなり、結果的に、第１方向に延在する第１側面１ｂ及び第２側面１ｃに沿ってシリコン基板１のエッチング残りが発生してしまうからである。これを回避するために、本実施形態においては、素子分離領域２を先に異方性ドライエッチングする必要がある。 Next, using the mask film 3a as a mask, the active region 1a and the element isolation region 2 whose upper surfaces are exposed are subjected to anisotropic dry etching to simultaneously form the first word groove 3A and the second word groove 3B. Here, a method is used in which the element isolation region 2 is first subjected to anisotropic dry etching, and then the active region 1a is subjected to anisotropic dry etching. On the other hand, a method of etching the element isolation region 2 after etching the active region 1a is not preferable. The reason is that, as described above, the first side surface 1b and the second side surface 1c constituting the active region 1a are formed so as to be slightly inclined toward the active region 1a side. When anisotropic dry etching is performed, the element isolation insulating film 25 formed along the Z direction of the first side face 1b and the second side face 1c serves as an etching mask, and as a result, the first extension extending in the first direction. This is because the etching residue of the silicon substrate 1 occurs along the side surface 1b and the second side surface 1c. In order to avoid this, in this embodiment, it is necessary to anisotropically dry the element isolation region 2 first.
　まず、図５Ａ～図５Ｃに示すように、マスク膜３ａをマスクとして、上面が露出している素子分離領域２を選択的に異方性ドライエッチングする。上述のように、素子分離領域２の上面は、第１側面１ｂ及び第２側面１ｃに形成されている内壁酸化膜２４の上面と、素子分離溝２３に埋設されている素子分離絶縁膜２５の上面とから構成されている。内壁酸化膜２４は、熱酸化法で形成されたシリコン酸化膜からなり、素子分離絶縁膜２５は、ＣＶＤ法で形成されたシリコン窒化膜で構成されている。一般に、この状態で、素子分離絶縁膜２５を構成するシリコン窒化膜のエッチング速度（ＥＲ）が活性領域１ａ（シリコン基板１）のＥＲよりも速くなる条件で異方性ドライエッチングすると、第１側面１ｂ及び第２側面１ｃに形成されている内壁酸化膜２４が十分にエッチングされず、残存しやすくなってしまう。このような内壁酸化膜２４の残存は、上述した如く（発明が解決しようとする課題の欄を参照）、種々の不都合を生じる。なお、素子分離絶縁膜を、ＣＶＤ法や回転塗布法で形成したシリコン酸化膜で構成した場合にも、同様の問題が生じる。 First, as shown in FIGS. 5A to 5C, using the mask film 3a as a mask, the element isolation region 2 whose upper surface is exposed is selectively subjected to anisotropic dry etching. As described above, the upper surface of the element isolation region 2 includes the upper surface of the inner wall oxide film 24 formed on the first side surface 1b and the second side surface 1c and the element isolation insulating film 25 embedded in the element isolation trench 23. And an upper surface. The inner wall oxide film 24 is made of a silicon oxide film formed by a thermal oxidation method, and the element isolation insulating film 25 is made of a silicon nitride film formed by a CVD method. Generally, in this state, when anisotropic dry etching is performed under the condition that the etching rate (ER) of the silicon nitride film constituting the element isolation insulating film 25 is faster than the ER of the active region 1a (silicon substrate 1), the first side surface The inner wall oxide film 24 formed on 1b and the second side surface 1c is not sufficiently etched and tends to remain. Such remaining of the inner wall oxide film 24 causes various inconveniences as described above (see the section of the problem to be solved by the invention). The same problem occurs when the element isolation insulating film is formed of a silicon oxide film formed by CVD or spin coating.
　従って、本実施形態では、シリコン窒化膜（素子分離絶縁膜２５）を異方性ドライエッチングして掘り下げると同時に、第１側面１ｂ及び第２側面１ｃをサイドエッチングして活性領域１ａのＹ方向の幅を縮退させる。ここでは、片側の側面における縮退幅Ｗ２は、例えば、５ｎｍとする。この場合、活性領域１ａ全体では１０ｎｍ縮退することとなる。この縮退には、第１側面１ｂ及び第２側面１ｃに露出する内壁酸化膜２４を横方向にエッチングする等方性エッチングを同時に行うことができるエッチング条件を用いる。もしくは、素子分離絶縁膜２５を異方性ドライエッチングして所定の位置まで掘り下げた後、第１側面１ｂ及び第２側面１ｃに露出している内壁酸化膜２４を、シリコン酸化膜の等方性エッチング条件を用いて段階的にドライエッチングする方法を用いても良い。これにより、図５Ｃに示すように、活性領域１ａの上面が、Ｙ方向に隣接する素子分離領域２の上面より高くなっている第１サドル型フィン部（サドル型フィン部）１１ａが形成される。なお、ここでは、掘り下げた後の素子分離領域２の上面の位置は、例えば、シリコン基板１の上面から１５０ｎｍ下方の位置とする。 Therefore, in the present embodiment, the silicon nitride film (element isolation insulating film 25) is etched by anisotropic dry etching, and at the same time, the first side surface 1b and the second side surface 1c are side etched to perform the Y-direction of the active region 1a. Reduce the width. Here, the degenerate width W2 on one side surface is, for example, 5 nm. In this case, the entire active region 1a is degenerated by 10 nm. For this degeneration, an etching condition is used in which isotropic etching for simultaneously etching the inner wall oxide film 24 exposed on the first side surface 1b and the second side surface 1c in the lateral direction can be performed. Alternatively, after the element isolation insulating film 25 is anisotropically etched and dug down to a predetermined position, the inner wall oxide film 24 exposed on the first side face 1b and the second side face 1c is replaced with an isotropic silicon oxide film. A method of performing dry etching step by step using etching conditions may be used. As a result, as shown in FIG. 5C, a first saddle fin portion (saddle fin portion) 11a is formed in which the upper surface of the active region 1a is higher than the upper surface of the element isolation region 2 adjacent in the Y direction. . Here, the position of the upper surface of the element isolation region 2 after being dug down is, for example, a position 150 nm below the upper surface of the silicon substrate 1.
　上記のようなエッチング条件で素子分離領域２をエッチングすることにより、複数の第１サドル型フィン部１１ａの、上端部側のＹ方向の幅Ｗ３は３０ｎｍとなり、活性領域１ａのＹ方向の上面幅Ｗ１（４０ｎｍ）よりも１０ｎｍ狭くなっている。これにより、第１サドル型フィン部１１ａの側面に相当する位置において、活性領域１ａの側面１ｂ、１ｃに形成されていた内壁酸化膜２４を確実に除去することができる。また、内壁酸化膜２４を横方向にエッチングするとともに、活性領域１ａの側面１ｂ、１ｃをサイドエッチングすることにより、第１サドル型フィン部１１ａの側面も新たに形成されることとなる。即ち、活性領域１ａの第１側面１ｂは第１サドル型フィン部１１ａにおいて新たな第１側面１ｂｂとなり、同じく第２側面１ｃは新たな第２側面１ｃｃとなる。新たな第１の側面１ｂｂは、縮退幅Ｗ２の段差Ｄ１を介して元の第１側面１ｂと接続され、新たな第２の側面１ｃｃは、縮退幅Ｗ２の段差Ｄ２を介して元の第２側面１ｃと接続されるように形成される。 By etching the element isolation region 2 under the etching conditions as described above, the width W3 in the Y direction on the upper end side of the plurality of first saddle type fin portions 11a becomes 30 nm, and the upper surface width in the Y direction of the active region 1a It is 10 nm narrower than W1 (40 nm). Thereby, the inner wall oxide film 24 formed on the side surfaces 1b and 1c of the active region 1a can be reliably removed at a position corresponding to the side surface of the first saddle type fin portion 11a. Further, by etching the inner wall oxide film 24 in the lateral direction and side-etching the side surfaces 1b and 1c of the active region 1a, the side surface of the first saddle type fin portion 11a is newly formed. That is, the first side surface 1b of the active region 1a becomes a new first side surface 1bb in the first saddle type fin portion 11a, and the second side surface 1c similarly becomes a new second side surface 1cc. The new first side surface 1bb is connected to the original first side surface 1b via a step D1 having a degenerated width W2, and the new second side surface 1cc is connected to the original second side via a step D2 having a degenerate width W2. It is formed so as to be connected to the side surface 1c.
　以下に、本実施形態のフィン部形成工程（２）について、図４及び図５を参照しながら、より具体的な例を説明する。
　まず、ＳＴＩ構造を含むシリコン基板1の全面に、例えば、ＣＶＤ法によって非晶質カーボン膜及びシリコン酸化膜からなるマスク膜３ａを成膜する。次いで、マスク膜３ａ上にＢＡＲＣ膜を塗布し、さらにホトレジストを積層塗布する。その後、リソグラフィ法及びＢＡＲＣエッチングを用いて、ワード溝３（第１ワード溝３Ａ、第２ワード溝３Ｂ）の繰り返しパターンを持つ第２ホトレジストマスクＲを形成する。そして、図４Ａ～図４Ｃに示すように、第２レジストマスクＲを用いたエッチングにより、マスク膜３ａをワード溝３の繰り返しパターンに形成する。
　その後、ホトレジストおよびＢＡＲＣ膜を除去する。 Below, a more specific example is demonstrated about the fin part formation process (2) of this embodiment, referring FIG.4 and FIG.5.
First, a mask film 3a made of an amorphous carbon film and a silicon oxide film is formed on the entire surface of the silicon substrate 1 including the STI structure, for example, by a CVD method. Next, a BARC film is applied on the mask film 3a, and a photoresist is laminated and applied. Thereafter, a second photoresist mask R having a repetitive pattern of the word grooves 3 (first word groove 3A, second word groove 3B) is formed by lithography and BARC etching. Then, as shown in FIGS. 4A to 4C, a mask film 3a is formed in a repeated pattern of the word grooves 3 by etching using the second resist mask R.
Thereafter, the photoresist and the BARC film are removed.
　次に、図５Ａ～図５Ｃに示すように、マスク膜３ａをマスクとして、上面が露出している素子分離領域２を選択的に異方性ドライエッチングする。この際、まず、素子分離領域２の素子分離絶縁膜２５が選択的にエッチングされ、活性領域１ａのＳｉが上方からはエッチングされ難く、且つ、内壁酸化膜２４が横方向にエッチングされるとともにシリコン基板１がサイドエッチされる条件、例えば、トリフロロメタン(ＣＨＦ３)と、オクタフロロシクロブタン（Ｃ４Ｆ８）と、酸素（Ｏ２）とＡｒの混合ガスプラズマ雰囲気で、１０～２０Ｐａのチャンバー圧力とし、７００～１２００ＷのＲＦパワーを印加する条件でエッチングを行う。ここで、チャンバー圧力が高圧側になるとサイドエッチ量が多くなり、低圧側になるとサイドエッチ量が少なくなるが、チャンバー圧力を上記範囲とすることで、適正なサイドエッチ量が得られ、内壁酸化膜２４を確実に除去しながらサドル型フィン部１１を形成することが可能となる。また、上述したように、素子分離領域２の内壁酸化膜２４の厚さの変化に対しては、Ｏ２の流量変更による調整を行うことで、内壁酸化膜２４の厚さに依存せず、内壁酸化膜２４を確実に除去しながらサドル型フィン部１１を形成することが可能となる。
　このように、各エッチング条件を調整することで、図５Ｃに示すように、サイドエッチを適正とし、素子分離領域２の内壁酸化膜２４がサドル型フィン部１１に残らないようにエッチングする。 Next, as shown in FIGS. 5A to 5C, the element isolation region 2 whose upper surface is exposed is selectively anisotropically dry etched using the mask film 3a as a mask. At this time, first, the element isolation insulating film 25 in the element isolation region 2 is selectively etched, Si in the active region 1a is hardly etched from above, and the inner wall oxide film 24 is etched in the lateral direction and silicon. A chamber of 10 to 20 Pa in a condition in which the substrate 1 is side-etched, for example, in a mixed gas plasma atmosphere of trifluoromethane (CHF 3 ), octafluorocyclobutane (C 4 F 8 ), oxygen (O 2 ), and Ar. Etching is performed under the condition of applying pressure and 700 to 1200 W of RF power. Here, the side etch amount increases when the chamber pressure becomes high, and the side etch amount decreases when the chamber pressure becomes low. However, by setting the chamber pressure within the above range, an appropriate side etch amount can be obtained and the inner wall oxidation can be achieved. The saddle type fin portion 11 can be formed while the film 24 is reliably removed. Further, as described above, the change in the thickness of the inner wall oxide film 24 in the element isolation region 2 is not dependent on the thickness of the inner wall oxide film 24 by performing adjustment by changing the flow rate of O 2 . It is possible to form the saddle type fin portion 11 while reliably removing the inner wall oxide film 24.
Thus, by adjusting each etching condition, as shown in FIG. 5C, the side etching is made appropriate and etching is performed so that the inner wall oxide film 24 in the element isolation region 2 does not remain in the saddle type fin portion 11.
　なお、本実施形態においては、次の掘り込み工程におけるシリコンエッチング時のチャンバー圧力を高圧側に変更することでサイドエッチを入れられる条件とすることにより、内壁酸化膜２４を除去しながら、サドル型フィン部１１を薄く形成することも可能である。 In the present embodiment, the saddle type is formed while removing the inner wall oxide film 24 by changing the chamber pressure at the time of silicon etching in the next digging step to a high pressure side so that side etching can be performed. It is also possible to make the fin portion 11 thin.
＜（３）掘り込み工程＞
　掘り込み工程では、上記手順及び条件のフィン部形成工程において素子分離領域２の上面をシリコン基板１の上面から１５０ｎｍ掘り下げた後、さらに、活性領域１ａに露出している第１サドル型フィン部１１ａの上面を選択的にエッチングして掘り下げることにより、第２サドル型フィン部（サドル型フィン部）１１を形成する。 <(3) Digging process>
In the digging step, after the upper surface of the element isolation region 2 is dug 150 nm from the upper surface of the silicon substrate 1 in the fin portion forming step of the above procedure and conditions, the first saddle type fin portion 11a exposed to the active region 1a is further removed. A second saddle-type fin portion (saddle-type fin portion) 11 is formed by selectively etching and digging up the upper surface.
　以下に、本実施形態の掘り込み工程（３）について、図６を参照しながら、より具体的な例を説明する。
　掘り込み工程では、図６Ａ～図６Ｃに示すように、上記フィン部形成工程で形成された第１サドル型フィン部１１ａの上面を所望の深さまでエッチングする。このエッチングは、フィン部形成工程で使用した装置内で条件を変えて連続的に実施することが好ましい。この際の所望の深さは、掘り下げられた素子分離領域２の上面よりも４０～４５ｎｍ高い位置とし、この場合、シリコン基板１の上面から１０５～１１０ｎｍ低い位置となる。この際、素子分離領域２に対して選択比の高い条件でエッチングを行う、即ち、シリコンのＥＲがシリコン窒化膜やシリコン酸化膜のＥＲよりも早くなる条件で異方性ドライエッチングを実施する。しかしながら、第１サドル型フィン部１１ａのエッチングでは、幅が狭いほど、予想した以上に第１サドル型フィン部１１ａのＥＲが早くなる可能性もあり、通常のシリコンエッチング条件を用いると、第１サドル型フィン部１１ａが消滅してしまう場合がある。従って、第１サドル型フィン部１１ａのエッチングには、シリコンのＥＲが低くなる条件を採用する。このような条件としては、塩素（Ｃｌ２）と、テトラフロロカーボン（ＣＦ４）と、ＳＦ６と、Ｈｅとの混合ガスプラズマ雰囲気で、３～１０Ｐａのチャンバー圧力とし、１００～３００ＷのＲＦパワーを印加してエッチングを行う。この際、ＳｉシリコンのＥＲはＳＦ６の流量で制御することができ、例えば、ＳＦ６の流量を減らすことで、シリコンのエッチレートを低く抑えることができる。これにより、第１サドル型フィン部１１ａの高さを制御しつつ、Ｙ方向の幅を狭くして第２サドル型フィン部（サドル型フィン部）１１を形成することができる。 Below, a more specific example is demonstrated about the digging process (3) of this embodiment, referring FIG.
In the digging step, as shown in FIGS. 6A to 6C, the upper surface of the first saddle type fin portion 11a formed in the fin portion forming step is etched to a desired depth. This etching is preferably performed continuously by changing the conditions in the apparatus used in the fin portion forming step. The desired depth at this time is 40 to 45 nm higher than the upper surface of the deeply isolated element isolation region 2, and in this case, 105 to 110 nm lower than the upper surface of the silicon substrate 1. At this time, etching is performed on the element isolation region 2 under a condition with a high selection ratio, that is, anisotropic dry etching is performed on the condition that the ER of silicon is faster than the ER of the silicon nitride film or silicon oxide film. However, in the etching of the first saddle type fin portion 11a, the narrower the width, the ER of the first saddle type fin portion 11a may be faster than expected. The saddle type fin portion 11a may disappear. Therefore, a condition for lowering the ER of silicon is adopted for the etching of the first saddle type fin portion 11a. As such conditions, a mixed gas plasma atmosphere of chlorine (Cl 2 ), tetrafluorocarbon (CF 4 ), SF 6 and He has a chamber pressure of 3 to 10 Pa and an RF power of 100 to 300 W. Etching is performed by applying. At this time, ER of Si silicon can be controlled at a flow rate of SF 6, for example, by reducing the flow rate of SF 6, it is possible to suppress the silicon etch rate. Thus, the second saddle fin portion (saddle fin portion) 11 can be formed by narrowing the width in the Y direction while controlling the height of the first saddle fin portion 11a.
　このように、本実施形態では、素子分離領域２の内壁酸化膜２４が第１側面１ｂ及び第２側面１ｃに取り残されることが無いため、素子分離領域２をより深くエッチングする必要が無い。従って、掘り下げた後の素子分離絶縁膜２５の厚みを十分に確保でき、寄生ＭＯＳ効果によって直下のシリコン基板表面を流れる電流リークが生じる問題を回避することが可能となる。 Thus, in this embodiment, since the inner wall oxide film 24 in the element isolation region 2 is not left on the first side surface 1b and the second side surface 1c, it is not necessary to etch the element isolation region 2 deeper. Therefore, it is possible to sufficiently secure the thickness of the element isolation insulating film 25 after being dug down, and to avoid the problem that current leaks on the surface of the silicon substrate immediately below due to the parasitic MOS effect.
　上述のように、フィン部形成工程及び掘り込み工程を経る工程を採用することにより、掘り下げられた素子分離領域２とサドル型フィン部１１とが第２方向に交互に繰り返して配置される、第１ワード溝３Ａと第２ワード溝３Ｂが同時に形成される。即ち、図６Ａに示すように、第２方向に延在する２本の第１ワード溝３Ａの間に、同じくＹ方向に延在する２本の第２ワード溝３Ｂが配置される構成とされている。このように、１本の第１ワード線３Ａと２本の第２ワード線３Ｂとを基本構成として、これらがＸ方向に繰り返し配置されることにより、メモリセル領域が構成される。また、第１方向に延在する活性領域１ａは、第１方向の素子分離領域となる２本の第１ワード溝３Ａによって島状の小活性領域１ａａに分断されている。 As described above, by adopting the process through the fin part forming process and the digging process, the element isolation regions 2 and the saddle type fin parts 11 that are dug down are alternately arranged in the second direction. The first word groove 3A and the second word groove 3B are formed simultaneously. That is, as shown in FIG. 6A, between the two first word grooves 3A extending in the second direction, two second word grooves 3B extending in the Y direction are arranged. ing. As described above, the memory cell region is configured by repeatedly arranging the first word line 3A and the two second word lines 3B in the X direction as a basic configuration. The active region 1a extending in the first direction is divided into island-shaped small active regions 1aa by two first word grooves 3A serving as element isolation regions in the first direction.
＜（４）埋め込みワード線形成工程＞
　埋め込みワード線形成工程では、複数のワード溝３（第１ワード溝３Ａ及び第２ワード溝３Ｂ）の底面上に導電材料を堆積させた後、この導電材料の一部をエッチング除去し、複数の第１ワード溝３Ａ及び第２ワード溝３Ｂの底面に導電材料を残存させる。これにより、ダミー電極を構成するダミーワード線（第１埋め込みワード線）３１を形成するとともに、ゲート電極を構成するワード線（第２埋め込みワード線）３２を形成する。 <(4) Embedded Word Line Formation Step>
In the buried word line forming step, after a conductive material is deposited on the bottom surfaces of the plurality of word grooves 3 (first word groove 3A and second word groove 3B), a part of the conductive material is removed by etching. The conductive material is left on the bottom surfaces of the first word groove 3A and the second word groove 3B. Thereby, a dummy word line (first embedded word line) 31 constituting a dummy electrode is formed, and a word line (second embedded word line) 32 constituting a gate electrode is formed.
　以下に、本実施形態の埋め込みワード線形成工程（４）について、図７を参照しながら、より具体的な例を説明する。なお、図７Ｂ（図８Ｂ）の断面図は、図２と同様、Ｘ'方向（第１方向）の断面図となっている。
　まず、図７Ａ、図７Ｂに示すように、ＩＳＳＧ（Ｉｎ－Ｓｉｔｕ　Ｓｔｅａｍ　Ｇｅｎｅｒａｔｉｏｎ）酸化法により、ワード溝３（第１ワード溝３Ａ、第２ワード溝３Ｂ）内の側面と底面にシリコン酸化膜からなるゲート絶縁膜３ｃを形成する。このゲート絶縁膜３ｃの厚さは、５ｎｍ程度とすることが好ましい。 Hereinafter, a more specific example of the buried word line forming step (4) of the present embodiment will be described with reference to FIG. 7B (FIG. 8B) is a cross-sectional view in the X ′ direction (first direction) as in FIG. 2.
First, as shown in FIGS. 7A and 7B, silicon oxide films are formed on the side and bottom surfaces of the word groove 3 (first word groove 3A, second word groove 3B) by ISSG (In-Situ Steam Generation) oxidation. A gate insulating film 3c is formed. The thickness of the gate insulating film 3c is preferably about 5 nm.
　次いで、ＣＶＤ法を用いて、第１ワード溝３Ａ及び第２ワード溝３Ｂを埋め込むように、ウェーハの全面にＴｉＮ膜及びＷ膜を成膜した後、各々の上面の位置がシリコン基板１の上面から７０～８０ｎｍ下方の位置となるようにエッチバックすることで、ワード線３ｄを形成する。
　上記工程により、埋め込みワード線であるダミーワード線３１、及び、ワード線３２を形成する。 Next, a TiN film and a W film are formed on the entire surface of the wafer so as to fill the first word groove 3A and the second word groove 3B by using the CVD method, and then the position of each upper surface is the upper surface of the silicon substrate 1. The word line 3d is formed by etching back to a position below 70 to 80 nm from the back.
Through the above process, the dummy word line 31 and the word line 32 which are embedded word lines are formed.
＜（５）キャップ形成工程＞
　キャップ形成工程では、上記工程でダミーワード線３１及びワード線３２を形成した後、さらに、第１ワード溝３Ａ及び第２ワード溝３Ｂに絶縁材料を充填して、第１埋め込みワード線３１及び第２埋め込みワード線３２を埋め込むことにより、埋め込みキャップ絶縁膜３ｅを形成するキャップ形成工程を備えている。 <(5) Cap formation process>
In the cap formation step, after the dummy word line 31 and the word line 32 are formed in the above step, the first word groove 3A and the second word groove 3B are further filled with an insulating material, and the first buried word line 31 and the first word line 31 are then filled. 2 A cap forming step of forming the embedded cap insulating film 3e by embedding the embedded word line 32 is provided.
　具体的には、ウェーハ上の全面に、ＣＶＤ法を用いてシリコン窒化膜であるキャップ絶縁膜３ｅを成膜し、ＣＭＰ法を用いて、マスク膜３ａをストップ膜として平坦化する。この際、平坦化の時点でマスク膜３ａを除去しても良い。 Specifically, a cap insulating film 3e, which is a silicon nitride film, is formed on the entire surface of the wafer by CVD, and is planarized by using CMP as a stop film using CMP. At this time, the mask film 3a may be removed at the time of planarization.
＜ビット線形成工程＞
　本実施形態の製造方法では、さらに、上記のキャップ形成工程（５）に引き続き、ビット線形成工程が備えられている。図７Ａ、図７Ｂに示すように、ビット線形成工程においては、まず、シリコン基板１上のＳＴＩ構造及び埋め込みキャップ絶縁膜３ｅを覆うように絶縁材料を堆積させて第１層間絶縁膜４を形成する。次いで、第１層間絶縁膜４の一部をエッチング除去してビットコンタクトホール（コンタクトホール）５３を形成した後、このビットコンタクトホール５３に導電材料を充填することで、第１層間絶縁膜４を貫通して活性領域１ａに接続されるビットコンタクトプラグ（ビットコンタクト層）５４を形成する。次いで、第１層間絶縁膜４上に導電材料をパターニングすることで、ビットコンタクトプラグ５４に接続されるビットラインゲート上層膜（ビット線）５５を形成するビット線形成工程が備えられている。 <Bit line formation process>
In the manufacturing method of the present embodiment, a bit line forming step is further provided following the cap forming step (5). As shown in FIGS. 7A and 7B, in the bit line formation step, first, an insulating material is deposited so as to cover the STI structure and the embedded cap insulating film 3e on the silicon substrate 1, thereby forming the first interlayer insulating film 4. To do. Next, a part of the first interlayer insulating film 4 is removed by etching to form a bit contact hole (contact hole) 53, and then the bit contact hole 53 is filled with a conductive material, whereby the first interlayer insulating film 4 is formed. A bit contact plug (bit contact layer) 54 that penetrates and is connected to the active region 1a is formed. Next, a bit line forming step of forming a bit line gate upper layer film (bit line) 55 connected to the bit contact plug 54 by patterning a conductive material on the first interlayer insulating film 4 is provided.
＜キャパシタ形成工程＞
　本実施形態の製造方法では、さらに、上記のビット線形成工程の後、以下に説明するようなキャパシタ形成工程を備えた方法とすることができる。このキャパシタ形成工程は、図７～図８に示すように、まず、ビットラインゲート５及び第１層間絶縁膜４を覆うように絶縁材料を堆積させて第２層間絶縁膜６を形成し、次いで、この第２層間絶縁膜６の一部をエッチング除去してコンタクトホールを形成する。次いで、このコンタクトホールに導電材料を充填することで、第２層間絶縁膜６を貫通して活性領域１ａに接続される容量コンタクト（容量コンタクト層）７を形成する。 <Capacitor formation process>
In the manufacturing method of the present embodiment, after the bit line forming process, a capacitor forming process as described below can be used. In this capacitor forming step, as shown in FIGS. 7 to 8, first, an insulating material is deposited so as to cover the bit line gate 5 and the first interlayer insulating film 4 to form the second interlayer insulating film 6, and then Then, a part of the second interlayer insulating film 6 is removed by etching to form a contact hole. Next, the contact hole is filled with a conductive material, thereby forming a capacitor contact (capacitor contact layer) 7 penetrating the second interlayer insulating film 6 and connected to the active region 1a.
　次いで、第２層間絶縁膜６及び容量コンタクト７を覆うようにストッパー膜９及び第３層間絶縁膜１３をこの順次で積層し、次いで、これらストッパー膜９及び第３層間絶縁膜１３における容量コンタクト７に対応する位置をエッチング除去することでシリンダーホール８ａを形成する。具体的には、まず、ＣＶＤ法を用いて、ウェーハ上の全面にシリコン窒化膜からなるストッパー膜９と、シリコン酸化膜からなる第３層間絶縁膜１３を成膜し、リソグラフィ法及びドライエッチングによってシリンダーホール８ａを開口させる。 Next, a stopper film 9 and a third interlayer insulating film 13 are sequentially laminated so as to cover the second interlayer insulating film 6 and the capacitor contact 7, and then the capacitor contact 7 in the stopper film 9 and the third interlayer insulating film 13 is stacked. The cylinder hole 8a is formed by etching away the position corresponding to. Specifically, first, a stopper film 9 made of a silicon nitride film and a third interlayer insulating film 13 made of a silicon oxide film are formed on the entire surface of the wafer by using a CVD method, and a lithography method and dry etching are performed. The cylinder hole 8a is opened.
　次いで、ウェーハ上の全面、即ち、シリンダーホール８ａの底面及び側壁を覆うとともに、第３層間絶縁膜１３の上面を覆うように、薄くＴｉＮ膜を形成した後、エッチングによってシリンダーホール８ａの底面及び側壁のみにＴｉＮ膜を残存させることにより、下部電極（下部電極層）８ｂを形成する。 Next, a thin TiN film is formed so as to cover the entire surface of the wafer, that is, the bottom surface and side walls of the cylinder hole 8a and the top surface of the third interlayer insulating film 13, and then the bottom surface and side walls of the cylinder hole 8a by etching. The lower electrode (lower electrode layer) 8b is formed by leaving the TiN film only on the surface.
　次いで、下部電極８ｂの内側を含むウェーハ上の全面に、容量絶縁膜８ｃ及び上部電極（上部電極層）８ｄをこの順で積層する。そして、リソグラフィ法及びドライエッチングにより、メモリセル領域ＭＣＡ上の容量絶縁膜８ｃ及び上部電極８ｄのみを残存させ、その他の部分が除去されるようにエッチングを行う。これにより、下部電極８ｂ、容量絶縁膜８ｃ及び上部電極８ｄから構成されるキャパシタ８が形成される。 Next, a capacitive insulating film 8c and an upper electrode (upper electrode layer) 8d are laminated in this order on the entire surface of the wafer including the inside of the lower electrode 8b. Then, etching is performed by lithography and dry etching so that only the capacitor insulating film 8c and the upper electrode 8d on the memory cell region MCA remain, and other portions are removed. Thereby, the capacitor 8 composed of the lower electrode 8b, the capacitor insulating film 8c, and the upper electrode 8d is formed.
＜配線層形成工程＞
　本実施形態の製造方法では、さらに、上記のキャパシタ形成工程の後、以下に説明するような配線層形成工程を備えた方法とすることができる。
　この配線層形成工程においては、図８Ａ、図８Ｂに示すように、まず、シリンダーホール８ａを埋め込むとともに、上部電極８ｄ上を覆うように第４層間絶縁膜１４を形成する。次いで、第４層間絶縁膜１４の一部をエッチング除去してコンタクトホールを形成した後、このコンタクトホールに導電材料を充填することで、第４層間絶縁膜１４を貫通して上部電極８ｄに接続される配線コンタクト１５を形成する。次いで、第４層間絶縁膜１４上に導電材料をパターニングすることで、配線コンタクト１５に接続する配線層１６を形成する。その後、配線層形成工程においては、配線層１６及び第４層間絶縁膜１４を覆うように保護絶縁膜１７を形成する。 <Wiring layer formation process>
In the manufacturing method of this embodiment, after the capacitor forming step, a wiring layer forming step as described below can be provided.
In this wiring layer formation step, as shown in FIGS. 8A and 8B, first, the fourth interlayer insulating film 14 is formed so as to fill the cylinder hole 8a and cover the upper electrode 8d. Next, a part of the fourth interlayer insulating film 14 is removed by etching to form a contact hole, and then the contact hole is filled with a conductive material so as to penetrate the fourth interlayer insulating film 14 and connect to the upper electrode 8d. A wiring contact 15 is formed. Next, a wiring layer 16 connected to the wiring contact 15 is formed by patterning a conductive material on the fourth interlayer insulating film 14. Thereafter, in the wiring layer forming step, a protective insulating film 17 is formed so as to cover the wiring layer 16 and the fourth interlayer insulating film 14.
　本実施形態においては、上記各工程により、図１及び図２に示すような、縦型構造のトランジスタとして構成される半導体装置Ａが得られる。 In the present embodiment, the semiconductor device A configured as a vertical transistor as shown in FIGS. 1 and 2 is obtained by the above steps.
　以上説明したような、本発明の半導体装置の製造方法によれば、上記方法を採用することにより、活性領域１ａの側面に形成された内壁酸化膜２４を確実に除去できるので、素子分離領域２を大きく掘り込むことを必要とせずに、各フィン部の高さが確保できる。また、素子分離領域２に対する過剰な掘り込みを回避することで、素子分離溝２３の底部に残存する素子分離絶縁膜２５の厚さを確保できるので、寄生ＭＯＳ効果によって素子分離溝２３の底面直下のシリコン基板１の表面を流れるリーク電流の発生を防止することが可能となる。 According to the method for manufacturing a semiconductor device of the present invention as described above, by adopting the above method, the inner wall oxide film 24 formed on the side surface of the active region 1a can be surely removed. It is possible to secure the height of each fin portion without the need to dig deeply. Further, by avoiding excessive digging into the element isolation region 2, the thickness of the element isolation insulating film 25 remaining at the bottom of the element isolation groove 23 can be secured. It is possible to prevent the occurrence of leakage current flowing on the surface of the silicon substrate 1.
　また、ＳＴＩ構造の素子分離溝２３内の内壁酸化膜２４の厚さを変更した場合であっても、エッチングガスの流量変更によるエッチレートの調整のみで、確実に内壁酸化膜２４を除去することができるので、内壁酸化膜２４の厚さに依存せず、生産性に優れた工程を実現することができる。 Even when the thickness of the inner wall oxide film 24 in the element isolation trench 23 having the STI structure is changed, the inner wall oxide film 24 can be reliably removed only by adjusting the etching rate by changing the flow rate of the etching gas. Therefore, a process with excellent productivity can be realized without depending on the thickness of the inner wall oxide film 24.
　Ａ…半導体装置、
　１…シリコン基板、
　１１…サドル型フィン部、
　　１１ａ…第１サドル型フィン部、
　１１ｂ…第２サドル型フィン部、
　１２…ピラー型フィン部
　１ａ…活性領域、
　１ａａ…小活性領域、
　　１ｂ、１ｂｂ…第１側面、
　１ｃ、１ｃｃ…第２側面、
　　　１ｄ…容量コンタクト接続領域、
　　　１ｅ…ビットコンタクト接続領域、
　２…素子分離領域（ＳＴＩ）、
　　２３…素子分離溝、
　　２４…内壁酸化膜、
　　２５…素子分離絶縁膜、
　３…ワード溝、
　　３Ａ…第１ワード溝、
　　３Ｂ…第２ワード溝、
　　３１、３１Ａ、３１Ｂ、３１Ｃ…ダミーワード線（第１埋め込みワード線）、
　　３２、３２Ａ、３２Ｂ、３２Ｃ…ワード線（第２埋め込みワード線）、
　　３ａ…マスク膜、
　　３ｂ…開口部、
　３ｃ…ゲート絶縁膜、
　３ｄ…ワード線、
　３ｅ…キャップ絶縁膜、
　４…第１層間絶縁膜、
　　５…ビットラインゲート（ＢＬＧ：ビット線）、
　５３…ビットコンタクトホール、
　５４…ビットコンタクトプラグ（ビットコンタクト層）、
　５５…ビット線、
　５６…サイドウォール絶縁膜、
　　６…第２層間絶縁膜、
　　７…容量コンタクト（容量コンタクト層）、
　　８…キャパシタ、
　　　８ａ…シリンダーホール、
　　　８ｂ…下部電極（下部電極層）、
　８ｃ…容量絶縁膜、
　８ｄ…上部電極（上部電極層）、
　９…ストッパー膜、
　１３…第３層間絶縁膜、
　　１４…第４層間絶縁膜、
　　１５…配線コンタクト、
　　１６…配線層、
　　１７…保護絶縁膜、
　　Ｒ…レジストマスク（第２レジストマスク）、
　Ｔｒ１…セルトランジスタ、
　 A ... Semiconductor device,
1 ... silicon substrate,
11 ... saddle type fin part,
11a ... 1st saddle type fin part,
11b ... 2nd saddle type fin part,
12 ... pillar type fin part 1a ... active region,
1aa ... small active region,
1b, 1bb ... first side surface,
1c, 1cc ... second side surface,
1d: capacitive contact connection region,
1e: Bit contact connection region,
2 ... element isolation region (STI),
23: Element isolation groove,
24 ... inner wall oxide film,
25 ... element isolation insulating film,
3 ... Word groove,
3A ... 1st word groove,
3B ... Second word groove,
31, 31A, 31B, 31C ... dummy word lines (first embedded word lines),
32, 32A, 32B, 32C ... word lines (second embedded word lines),
3a ... Mask film,
3b ... opening,
3c ... gate insulating film,
3d ... word line,
3e: Cap insulating film,
4 ... 1st interlayer insulation film,
5. Bit line gate (BLG: bit line),
53 ... Bit contact hole,
54 ... Bit contact plug (bit contact layer),
55 ... bit line,
56 ... sidewall insulating film,
6 ... 2nd interlayer insulation film,
7: Capacitance contact (capacity contact layer),
8: Capacitor,
8a ... Cylinder hole,
8b ... lower electrode (lower electrode layer),
8c: capacitive insulating film,
8d: upper electrode (upper electrode layer),
9 ... stopper film,
13: Third interlayer insulating film,
14 ... Fourth interlayer insulating film,
15 ... wiring contact,
16 ... wiring layer,
17 ... Protective insulating film,
R: resist mask (second resist mask),
Tr1 ... cell transistor,

Claims (17)

  1. 　シリコン基板の表層に、第１方向に延在し、該第１方向に交差する第２方向に繰り返し配置される複数の素子分離溝と、該素子分離溝で区画される活性領域を形成する工程と、
    　前記活性領域の側面に内壁酸化膜を形成する工程と、
    　前記素子分離溝を埋め込む素子分離絶縁膜を形成して素子分離領域を形成する工程と、
    　前記活性領域と前記素子分離領域とに跨がって前記第２方向に延在する複数のマスク膜パターンを形成し、該マスク膜パターンの開口部に前記活性領域の上面と前記素子分離領域の上面とを露出させる工程と、
    　前記素子分離領域に上面が露出している前記素子分離絶縁膜を鉛直方向にエッチバックするとともに、前記活性領域の両側面をサイドエッチングすることで前記活性領域の両側面に形成されている前記内壁酸化膜を除去する工程と、
    　前記活性領域に上面が露出している前記シリコン基板をエッチバックすることで、前記素子分離絶縁膜の上面より上方に突出したサドル型フィン部を形成する工程と、
    を順次備えることを特徴とする半導体装置の製造方法。     Forming a plurality of element isolation grooves extending in a first direction and repeatedly disposed in a second direction intersecting the first direction and an active region partitioned by the element isolation grooves on a surface layer of the silicon substrate; When,
    Forming an inner wall oxide film on a side surface of the active region;
    Forming an element isolation region to fill the element isolation trench to form an element isolation region;
    A plurality of mask film patterns extending in the second direction across the active region and the element isolation region are formed, and an upper surface of the active region and the element isolation region are formed in the opening of the mask film pattern. Exposing the upper surface;
    The inner wall formed on both side surfaces of the active region by etching back the element isolation insulating film whose upper surface is exposed in the element isolation region in the vertical direction and side-etching both side surfaces of the active region Removing the oxide film;
    Etching back the silicon substrate whose upper surface is exposed in the active region, thereby forming a saddle type fin portion protruding upward from the upper surface of the element isolation insulating film;
    A method for manufacturing a semiconductor device, comprising:
  2. 　前記内壁酸化膜を除去する工程は、前記素子分離絶縁膜を異方性ドライエッチングによって選択的に除去すると同時に、前記内壁酸化膜を等方性ドライエッチングによって除去することで、前記サドル型フィン部を形成することを特徴とする請求項１に記載の半導体装置の製造方法。 The step of removing the inner wall oxide film selectively removes the element isolation insulating film by anisotropic dry etching, and simultaneously removes the inner wall oxide film by isotropic dry etching, so that the saddle type fin portion The method of manufacturing a semiconductor device according to claim 1, wherein:
  3. 　前記内壁酸化膜を除去する工程は、前記素子分離絶縁膜を異方性ドライエッチングによって選択的に除去した後、前記内壁酸化膜を等方性ドライエッチングによって除去する段階的なエッチングにより、前記サドル型フィン部を形成することを特徴とする請求項１に記載の半導体装置の製造方法。 The step of removing the inner wall oxide film includes the step of selectively removing the element isolation insulating film by anisotropic dry etching, and then performing stepwise etching to remove the inner wall oxide film by isotropic dry etching. The method for manufacturing a semiconductor device according to claim 1, wherein a mold fin portion is formed.
  4. 　前記サドル型フィン部を形成する工程は、前記内壁酸化膜を除去する工程で形成された前記サドル型フィン部の上面を異方性ドライエッチングによって選択的に除去することで、前記サドル型フィン部の高さを制御することを特徴とする請求項１に記載の半導体装置の製造方法。 The step of forming the saddle type fin portion selectively removes the upper surface of the saddle type fin portion formed in the step of removing the inner wall oxide film by anisotropic dry etching, so that the saddle type fin portion is formed. The method of manufacturing a semiconductor device according to claim 1, wherein the height of the semiconductor device is controlled.
  5. 　前記サドル型フィン部を形成する工程は、前記内壁酸化膜を除去する工程に引き続き、エッチング条件を変化させて前記サドル型フィン部の上面を異方性ドライエッチングすることで、前記サドル型フィン部の高さを制御することを特徴とする請求項１に記載の半導体装置の製造方法。 In the step of forming the saddle type fin portion, following the step of removing the inner wall oxide film, the saddle type fin portion is subjected to anisotropic dry etching on the upper surface of the saddle type fin portion by changing etching conditions. The method of manufacturing a semiconductor device according to claim 1, wherein the height of the semiconductor device is controlled.
  6. 　前記活性領域の側面は、対向する二つの側面を有しており、前記内壁酸化膜を除去する工程は、前記二つの側面を、該二つの側面の上方の幅が下方の幅よりも狭くなるように傾斜させながら形成することを特徴とする請求項１に記載の半導体装置の製造方法。 The side surface of the active region has two side surfaces that face each other, and the step of removing the inner wall oxide film reduces the width of the two side surfaces by making the upper width of the two side surfaces smaller than the lower width. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed while being inclined.
  7. 　前記素子分離領域の第２方向の上面幅と、前記素子分離領域に隣接する前記活性領域の第２方向の上面幅とを同じ寸法で形成することを特徴とする請求項１に記載の半導体装置の製造方法。 2. The semiconductor device according to claim 1, wherein the upper surface width in the second direction of the element isolation region and the upper surface width in the second direction of the active region adjacent to the element isolation region are formed to have the same dimension. Manufacturing method.
  8. 　前記素子分離領域の第２方向の上面幅を、前記素子分離領域に隣接する前記活性領域の第２方向の上面幅よりも小さい寸法で形成することを特徴とする請求項１に記載の半導体装置の製造方法。 2. The semiconductor device according to claim 1, wherein a top surface width in the second direction of the element isolation region is smaller than a top surface width in the second direction of the active region adjacent to the element isolation region. Manufacturing method.
  9. 　シリコン基板上にマスク絶縁膜及び第１レジストマスクを順次形成し、該第１レジストマスクを用いて前記シリコン基板及び前記マスク絶縁膜をエッチングすることで、前記第１方向に延在する素子分離領域の形成予定領域に沿ったラインアンドスペースパターンで素子分離溝を形成した後、該素子分離溝の内面に内壁酸化膜を形成するとともに、前記素子分離溝に絶縁材料を充填して素子分離絶縁膜を形成することによって活性領域を区画するための素子分離領域を形成し、シャロー・トレンチ・アイソレーション（ＳＴＩ）構造を形成するＳＴＩ工程と、
    　前記シリコン基板上にマスク窒化膜及び第２レジストマスクを順次形成した後、該第２レジストマスクを用いて前記シリコン基板上における前記素子分離領域及び前記活性領域をエッチング除去することにより、第１方向と交差して第２方向に延在する複数のワード溝を同時に形成する際、前記素子分離領域に上面が露出する前記素子分離絶縁膜を鉛直下方に掘り下げるとともに、前記活性領域の両側面をサイドエッチして前記第２方向の幅を縮退させることで、前記活性領域の側壁に形成された前記内壁酸化膜を除去し、掘り下げられた前記素子分離絶縁膜の上面よりも上方に前記シリコン基板を突出させてサドル型フィン部を形成するフィン部形成工程と、
    　さらに、前記ワード溝内に露出する前記サドル型フィン部の上面を選択的にエッチングして掘り下げることにより、前記サドル型フィン部の高さを制御する掘り込み工程と、
    　前記複数のワード溝の底面上に導電材料を堆積させた後、該導電材料の一部をエッチング除去し、前記複数のワード溝の底面に前記導電材料を残存させることにより、第１埋め込みワード線及び第２埋め込みワード線を形成する埋め込みワード線形成工程と、
    　前記第１ワード溝及び第２ワード溝に絶縁材料を充填して、前記第１埋め込みワード線及び第２埋め込みワード線を埋め込むことにより、埋め込みキャップ絶縁膜を形成するキャップ形成工程と、
    を順次備えることを特徴とする半導体装置の製造方法。     An element isolation region extending in the first direction by sequentially forming a mask insulating film and a first resist mask on the silicon substrate and etching the silicon substrate and the mask insulating film using the first resist mask. After forming an element isolation groove with a line-and-space pattern along the planned formation region, an inner wall oxide film is formed on the inner surface of the element isolation groove, and the element isolation groove is filled with an insulating material to form an element isolation insulating film Forming an element isolation region for partitioning an active region by forming a shallow trench isolation (STI) structure;
    A mask nitride film and a second resist mask are sequentially formed on the silicon substrate, and then the element isolation region and the active region on the silicon substrate are removed by etching using the second resist mask. When simultaneously forming a plurality of word grooves extending in the second direction intersecting with each other, the element isolation insulating film whose upper surface is exposed in the element isolation region is dug down vertically, and both side surfaces of the active region are Etching to reduce the width in the second direction removes the inner wall oxide film formed on the side wall of the active region, and the silicon substrate is placed above the upper surface of the element isolation insulating film dug down. A fin part forming step of forming a saddle type fin part by projecting; and
    Further, a digging step for controlling the height of the saddle type fin portion by selectively etching and digging up the upper surface of the saddle type fin portion exposed in the word groove;
    After depositing a conductive material on the bottom surfaces of the plurality of word grooves, a part of the conductive material is removed by etching, and the conductive material is left on the bottom surfaces of the plurality of word grooves, whereby a first buried word line And a buried word line forming step for forming a second buried word line;
    A cap forming step of forming a buried cap insulating film by filling the first word groove and the second word groove with an insulating material and embedding the first buried word line and the second buried word line;
    A method for manufacturing a semiconductor device, comprising:
  10. 　前記フィン部形成工程は、前記素子分離絶縁膜を異方性ドライエッチングによって選択的に除去すると同時に、前記内壁酸化膜を等方性ドライエッチングによって除去することで前記サドル型フィン部を形成することを特徴とする請求項９に記載の半導体装置の製造方法。 The fin part forming step forms the saddle type fin part by selectively removing the element isolation insulating film by anisotropic dry etching and simultaneously removing the inner wall oxide film by isotropic dry etching. A method for manufacturing a semiconductor device according to claim 9.
  11. 　前記フィン部形成工程は、前記素子分離絶縁膜を異方性ドライエッチングによって選択的に除去した後、前記内壁酸化膜を等方性ドライエッチングによって除去する段階的なエッチングにより、前記サドル型フィン部を形成することを特徴とする請求項９に記載の半導体装置の製造方法。 In the fin portion forming step, the saddle fin portion is selectively removed by anisotropic dry etching and then the inner wall oxide film is removed by isotropic dry etching. The method of manufacturing a semiconductor device according to claim 9, wherein:
  12. 　前記掘り込み工程は、前記サドル型フィン部の上面を異方性ドライエッチングによって選択的に除去することで、前記サドル型フィン部の高さを制御することを特徴とする請求項９に記載の半導体装置の製造方法。 The said digging process controls the height of the said saddle type fin part by selectively removing the upper surface of the said saddle type fin part by anisotropic dry etching. A method for manufacturing a semiconductor device.
  13. 　前記掘り込み工程は、前記フィン部形成工程に引き続き、エッチング条件を変化させて前記サドル型フィン部の上面を異方性ドライエッチングすることで、前記サドル型フィン部の高さを制御することを特徴とする請求項９に記載の半導体装置の製造方法。 The digging step controls the height of the saddle type fin portion by anisotropically etching the upper surface of the saddle type fin portion while changing the etching conditions following the fin portion forming step. The method for manufacturing a semiconductor device according to claim 9, wherein:
  14. 　さらに、前記キャップ形成工程の後、前記シリコン基板上のＳＴＩ構造及び前記キャップ絶縁膜を覆うように絶縁材料を堆積させて第１層間絶縁膜を形成し、次いで、該第１層間絶縁膜の一部をエッチング除去してコンタクトホールを形成した後、該コンタクトホールに導電材料を充填することで、前記第１層間絶縁膜を貫通して前記活性領域に接続されるビットコンタクト層を形成し、次いで、前記第１層間絶縁膜上に導電材料をパターニングすることで、前記ビットコンタクト層に接続されるビット線を形成するビット線形成工程が備えられていることを特徴とする請求項９に記載の半導体装置の製造方法。 Further, after the cap forming step, an insulating material is deposited so as to cover the STI structure on the silicon substrate and the cap insulating film to form a first interlayer insulating film, and then one of the first interlayer insulating films is formed. Forming a contact hole by etching away the portion, and then filling the contact hole with a conductive material to form a bit contact layer that penetrates the first interlayer insulating film and is connected to the active region, The bit line forming step of forming a bit line connected to the bit contact layer by patterning a conductive material on the first interlayer insulating film is provided. A method for manufacturing a semiconductor device.
  15. 　さらに、前記ビット線形成工程の後、前記ビット線及び前記第１層間絶縁膜を覆うように絶縁材料を堆積させて第２層間絶縁膜を形成し、次いで、該第２層間絶縁膜の一部をエッチング除去してコンタクトホールを形成した後、該コンタクトホールに導電材料を充填することで、前記第２層間絶縁膜を貫通して前記活性領域に接続される容量コンタクト層を形成し、次いで、該容量コンタクト層上にキャパシタを形成するキャパシタ形成工程が備えられていることを特徴とする請求項１４に記載の半導体装置の製造方法。 Further, after the bit line forming step, an insulating material is deposited so as to cover the bit line and the first interlayer insulating film to form a second interlayer insulating film, and then a part of the second interlayer insulating film Then, the contact hole is filled with a conductive material to form a capacitive contact layer that penetrates the second interlayer insulating film and is connected to the active region. 15. The method of manufacturing a semiconductor device according to claim 14, further comprising a capacitor forming step of forming a capacitor on the capacitor contact layer.
  16. 　前記キャパシタ形成工程は、前記容量コンタクト層を形成した後、前記第２層間絶縁膜及び前記容量コンタクト層を覆うようにストッパー膜及び第３層間絶縁膜をこの順次で積層し、次いで、該ストッパー膜及び第３層間絶縁膜における前記容量コンタクト層に対応する位置をエッチング除去することでシリンダーホールを形成した後、該シリンダーホールの底面及び側壁を覆うとともに、前記第３層間絶縁膜の上面を覆うように、下部電極層、容量絶縁膜及び上部電極層をこの順で積層することを特徴とする請求項１５に記載の半導体装置の製造方法。 In the capacitor forming step, after the capacitor contact layer is formed, a stopper film and a third interlayer insulating film are sequentially laminated so as to cover the second interlayer insulating film and the capacitor contact layer, and then the stopper film And forming a cylinder hole by etching and removing a position corresponding to the capacitive contact layer in the third interlayer insulating film, and then covering the bottom surface and side wall of the cylinder hole and covering the upper surface of the third interlayer insulating film. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the lower electrode layer, the capacitor insulating film, and the upper electrode layer are laminated in this order.
  17. 　さらに、前記キャパシタ形成工程の後、前記シリンダーホールを埋め込むとともに、前記上部電極層上を覆うように第４層間絶縁膜を形成し、次いで、該第４層間絶縁膜の一部をエッチング除去してコンタクトホールを形成した後、該コンタクトホールに導電材料を充填することで、前記第４層間絶縁膜を貫通して前記上部電極層に接続される配線コンタクトを形成し、次いで、前記第４層間絶縁膜上に導電材料をパターニングすることで、前記配線コンタクトに接続する配線層を形成した後、該配線層及び前記第４層間絶縁膜を覆うように保護絶縁膜を形成する配線層形成工程が備えられていることを特徴とする請求項１６に記載の半導体装置の製造方法。 Further, after the capacitor forming step, the cylinder hole is buried and a fourth interlayer insulating film is formed so as to cover the upper electrode layer, and then a part of the fourth interlayer insulating film is removed by etching. After the contact hole is formed, the contact hole is filled with a conductive material to form a wiring contact that penetrates the fourth interlayer insulating film and is connected to the upper electrode layer. A wiring layer forming step of forming a protective insulating film so as to cover the wiring layer and the fourth interlayer insulating film after forming a wiring layer connected to the wiring contact by patterning a conductive material on the film The method of manufacturing a semiconductor device according to claim 16, wherein the semiconductor device is manufactured.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105938832A (en) * 2015-03-03 2016-09-14 三星电子株式会社 Integrated circuit devices including fin shapes
CN111276480A (en) * 2018-12-04 2020-06-12 南亚科技股份有限公司 Memory device and forming method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180014550A (en) * 2016-08-01 2018-02-09 (주)피델릭스 Dram cell for reducing layout area and fabricating method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212369A (en) * 2008-03-05 2009-09-17 Elpida Memory Inc Semiconductor device, manufacturing method of semiconductor device and data processing system
JP2011159760A (en) * 2010-01-29 2011-08-18 Elpida Memory Inc Method of manufacturing semiconductor device, and the semiconductor device
JP2012084619A (en) * 2010-10-07 2012-04-26 Elpida Memory Inc Semiconductor device and method of manufacturing semiconductor device
JP2013183154A (en) * 2012-03-05 2013-09-12 Elpida Memory Inc Semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212369A (en) * 2008-03-05 2009-09-17 Elpida Memory Inc Semiconductor device, manufacturing method of semiconductor device and data processing system
JP2011159760A (en) * 2010-01-29 2011-08-18 Elpida Memory Inc Method of manufacturing semiconductor device, and the semiconductor device
JP2012084619A (en) * 2010-10-07 2012-04-26 Elpida Memory Inc Semiconductor device and method of manufacturing semiconductor device
JP2013183154A (en) * 2012-03-05 2013-09-12 Elpida Memory Inc Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105938832A (en) * 2015-03-03 2016-09-14 三星电子株式会社 Integrated circuit devices including fin shapes
CN111276480A (en) * 2018-12-04 2020-06-12 南亚科技股份有限公司 Memory device and forming method thereof

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