WO2014051233A2 - Carte de circuit imprimé - Google Patents

Carte de circuit imprimé Download PDF

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Publication number
WO2014051233A2
WO2014051233A2 PCT/KR2013/004110 KR2013004110W WO2014051233A2 WO 2014051233 A2 WO2014051233 A2 WO 2014051233A2 KR 2013004110 W KR2013004110 W KR 2013004110W WO 2014051233 A2 WO2014051233 A2 WO 2014051233A2
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WO
WIPO (PCT)
Prior art keywords
insulating layer
circuit board
printed circuit
core substrate
electronic device
Prior art date
Application number
PCT/KR2013/004110
Other languages
English (en)
Inventor
Won Suk Jung
Kyu Won Lee
Yun Ho An
Sang Myung Lee
Woo Young Lee
Original Assignee
Lg Innotek Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Publication of WO2014051233A2 publication Critical patent/WO2014051233A2/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components

Definitions

  • the present invention relates to a printed circuit board, and more specifically, to a printed circuit board which can improve quality by minimizing a bulge or a dell on a surface of the printed circuit board.
  • the electronic device-embedded board is useful. The reason is because it provides a means capable of improving a reliability problem which may be generated during the electrical connection of an electronic device using wire bonding or a solder ball used in a flip chip or a ball grid array.
  • a structure in which the electronic device is embedded in only one side of a core substrate or one side of a build-up layer is adopted.
  • the structure is an asymmetrical structure which is vulnerable to a warpage phenomenon under a thermal stress environment.
  • This has a limitation to embedding an electronic device having a thickness less than a predetermined thickness because the warpage phenomenon is generated from the board in a direction, in which the electronic device is located, under the thermal stress environment.
  • laminating materials used in the printed circuit board have a limitation that they cannot be manufactured to be less than a predetermined thickness due to an electrical insulating property. In this case, a critical thickness for preventing the warpage phenomenon is essentially limited due to material characteristics.
  • a printed circuit board and a manufacturing method thereof which can reduce the generation of a warpage phenomenon by geometrically forming an electronic device-equipped printed circuit board in an asymmetrical structure even through a thin device is embedded in the thin printed circuit board.
  • FIG. 1 is a view showing an electronic device-embedded printed circuit board according to a conventional art.
  • an electronic device-embedded printed circuit board includes: a core substrate 10; a via hole 12; an electronic device 20; a first insulating layer 30; a second insulating layer 32; and a circuit pattern 34.
  • the printed circuit board illustrated in FIG. 1 is designed and produced around the electronic device 20 in a symmetrical structure in which the extent of warpage of the board can be minimized.
  • the symmetrical structure functions to reduce dangerousness such as an increase in a warpage phenomenon as the thicknesses of a printed circuit board and a device 20 equipped therein become thin.
  • the printed circuit board according to the conventional art is configured such that an inner layer circuit pattern is formed on an upper surface and a lower surface of the core substrate 10, respectively, and thus the first insulating layer 30 and the second insulating layer 31 are formed in an upper part and a lower part of the core substrate 10 on which the inner layer circuit pattern is formed.
  • FIG. 2 is a view showing a bulge and a dell phenomenon generated from the printed circuit board according to the conventional art.
  • a main cause why the warpage phenomenon is entirely generated from the substrate is due to a difference in coefficient of thermal expansion (CTE) between the core and the insulating layer (Prepreg) material.
  • CTE coefficient of thermal expansion
  • a core, an insulating layer (Prepreg), and an active element material and a cavity for mounting the active element are present in the electronic device-embedded printed circuit board (PCB), a difference in coefficient of thermal expansion and other differences with respect to young's modulus, contraction, and expansion are additionally largely generated, thereby causing the non-uniform generation of a bulge or a dell.
  • An aspect of the present invention provides a printed circuit board and a method of manufacturing the same, which can improve quality of the printed circuit board by solving bulge and dell problems caused by a difference in thickness of an insulating material and a difference in coefficient of thermal expansion (CTE) of an electronic device.
  • CTE coefficient of thermal expansion
  • an another aspect of the present invention provides a printed circuit board and a method of manufacturing the same, which can improve a mass production yield at the same time as minimizing a warpage phenomenon generated from the printed circuit board, in which an electronic device is arranged, by managing a thickness of a second insulating material corresponding to a thickness of a first insulating material.
  • a printed circuit board including: a core substrate in which a cavity is formed; an electronic device mounted to the cavity; a first insulating layer which covers one surface of the core substrate and one surface of the electronic device; and a second insulating layer which covers another surface of the core substrate and another surface of the electronic device, wherein the first insulating layer has a same thickness at the core substrate and the electronic device.
  • the problem such as the lack of uniformity in flow of the resin caused by a space formed between a via hole of the core substrate and the electronic device can be solved, thereby enabling a deviation in thickness to be minimized.
  • the bulge and dell problems generated from the printed circuit board in which the electronic device is arranged can be solved by minimizing the lack of uniformity in flow of the resin and a deviation in thickness, thereby enabling quality of the printed circuit board to be improved.
  • an insulating material having a 10% or more larger thickness compared to a thickness of a first insulating material is used, so that the warpage phenomenon generated from the printed circuit board in which the electronic device is arranged can be minimized by managing a thickness of the second insulating material corresponding to the first insulating material, thereby enabling a mass production yield to increase.
  • FIG. 1 is a view showing a electronic device-embedded printed circuit board according to a conventional art
  • FIG. 2 is a view showing a bulge and a dell phenomenon generated from the printed circuit board according to the conventional art
  • FIG. 3 is a view showing a printed circuit board and a method of manufacturing the same according to an exemplary embodiment of the present invention
  • FIG. 4 through FIG. 22 are views for explaining, in the order of processes, the method of manufacturing the printed circuit board according to exemplary embodiments;
  • FIG. 23 is a view for explain a thickness of the printed circuit board of the conventional art.
  • FIG. 24 is a view for explain a thickness of the printed circuit board of the present invention.
  • FIG. 3 is a view showing a printed circuit board and a method of manufacturing the same according to an exemplary embodiment of the present invention.
  • a printed circuit board includes: a core substrate 110; an electronic device 120 which is inserted into a via hole formed in the core substrate 110; a first insulating layer 130 which is formed on the core substrate 110 to cover an upper part of the electronic device 120; a second insulating layer 140 which is formed below the core substrate 110 to cover a lower part of the electronic device 120; a first circuit pattern 136 formed on a surface of the first insulating layer 130; a second circuit pattern 144 formed on a surface of the second insulating layer 140; a third insulating layer 160 which is formed on the first insulating layer 130 to cover the surface of the first insulating layer 130; a fourth insulating layer 170 which is formed below the second insulating layer 140 to cover the surface of the second insulating layer 140; a third circuit pattern 164 formed on a surface of the third insulating layer 160; a fourth circuit pattern 174 formed on a surface of the fourth insulating layer 170; and a protective layer 190 which covers the surface
  • an upper part of the core substrate 110 is defined as an upper direction of the electronic device 120 on the drawings, and a lower part of the core substrate 110 is defined as a lower direction of the electronic device 120.
  • the core substrate 110 may be a thermosetting polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or a glass fiber-impregnated substrate.
  • the core substrate includes a polymer resin
  • an epoxy-based insulating resin may be included therein.
  • a polyimide-based resin may be included therein.
  • the core substrate 110 may be formed of an epoxy-based insulating resin in which glass fabric is impregnated.
  • a cavity 112 which passes through an upper surface and a lower surface is formed in the core substrate 110.
  • the core substrate 110 is composed of a dummy core substrate in which a circuit pattern is not formed on an upper surface thereof. Like this, when the core substrate 110 is formed of the dummy core substrate, a thickness of the first insulating layer formed in an upper part of the core substrate 110 may be more uniformly formed.
  • the cavity 112 may be formed by any one processing method of machining, laser and chemical processes.
  • the cavity 112 is formed by the machining process, methods such as a milling process, a drill process, routing process and the like may be used.
  • a milling process a drill process, routing process and the like
  • an UV or CO 2 laser method may be used.
  • the core substrate may be opened using chemicals including aminosilane, ketones and the like.
  • the laser process is a cutting method of partially melting and evaporating a material by concentrating optical energy on a surface of the material to obtain a desired shape.
  • the laser process is used, even complex formation using a computer program may be easily processed, a composite material which is difficult to cut it using other methods, may be also processed
  • a cut diameter may be at least 0.005 mm, and it is advantageous that the range in processable thickness is large.
  • An YAG (Yttrium Aluminum Garnet) laser, a CO 2 laser or an UV laser may be used as the laser process drill.
  • the YAG laser is a laser which may process both the copper foil layer and the insulating layer
  • the CO 2 laser is a laser which may process only the insulating layer.
  • the electronic device 120 is inserted into the cavity 112.
  • the electronic device 120 may be composed of a passive element or an active element.
  • the electronic device 120 may be a resistor, an inductor or a capacitor.
  • a terminal 122 for receiving currents or voltages supplied from the outside is formed at both ends of the electronic device 120.
  • the first insulating layer 130 is formed on the core substrate 110, and the second insulating layer 140 is formed below the core substrate 110.
  • the first insulating layer 130 and the second insulating layer 140 may be a thermosetting or thermo plastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or glass-fiber impregnated substrate.
  • a polymer resin such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build up Film) and the like may be included.
  • a polymide-based resin may be included therein.
  • the present invention is not specifically limited to this.
  • the first insulating layer 130 and the second insulating layer 140 may be formed in the same thickness.
  • the substantially same thickness includes the case in which a difference in thickness between the first insulating layer 130 and the second insulating layer 140 is more than 0 ⁇ m but is less than 10 ⁇ m, as well as the case in which the first insulating layer 130 and the second insulating layer 140 have the same thickness. More specifically, even though the thickness of the second insulating layer 140 is larger than that the first insulating layer 130, when a different in thickness is less than 10 ⁇ m, the thicknesses of the first insulating layer 130 and the second insulating layer 140 are deemed to be substantially identical to each other.
  • the inner layer-circuit pattern is not formed on the surface of the core substrate 110. If the circuit pattern is directly formed on the core substrate 110, this causes various problems during a laminating process of the first insulating layer or the second insulating layer, so a surface of the printed circuit board becomes non-uniform.
  • the dummy core substrate in which the circuit pattern is not formed, is used as the core substrate 110,and the first insulating layer 130 and the second insulating layer 140 are formed on and below the core substrate 110, respectively.
  • the first insulating layer 130 is in contact with the entire upper surface of the core substrate 110, and the second insulating layer 140 is in contact with the entire lower surface of the core substrate 110.
  • a thickness of the first insulating layer 130 formed in an area of the core substrate 110 in which the electronic device is mounted and a thickness of the first insulating layer 130 formed on the core substrate 110 are equal to each other.
  • the core substrate 110 is composed of the dummy core substrate so that the thicknesses of the first insulating layer 130 are more uniformly formed.
  • a difference between a maximum thickness and a minimum thickness of the first insulating layer 130 ranges from 0 ⁇ m to 10 ⁇ m.
  • a difference in thickness was more than 10 ⁇ m depending on areas of the insulating layer formed in an upper part of the core substrate.
  • a difference between a maximum thickness and a minimum thickness of the insulating layer ranges from 0 ⁇ m to 10 ⁇ m.
  • the first circuit pattern 136 is formed on the first insulating layer 130, and the second circuit pattern 144 is formed below the second insulating layer 140.
  • the first circuit pattern 136 may have a plurality of layered structures and may be formed on the first insulating layer 130 using a metal layer which forms the first circuit pattern 136.
  • the first circuit pattern 136 may be formed of an alloy including at least one of Al, Cu, Ag, Pt, Ni and Pd.
  • the first circuit pattern 136 may is formed by an additive process, a subtractive process, an MSAP (Modified Semi Additive Process) and a SAP (Semi Additive Process) which are general manufacturing processes of the printed circuit board. The detailed explanation thereon is omitted.
  • the second circuit pattern 144 may have a plurality of layered structures and may be formed on the second insulating layer 140 using a metal layer which forms the second circuit pattern 144.
  • the first circuit pattern 136 or the second circuit pattern 144 may be composed of a CCL (Copper Clad Laminate) circuit pattern.
  • the third insulating layer 160 is formed on the first insulating layer 130, and the fourth insulating layer 170 is formed below the second insulating layer 140.
  • the third insulating layer 160 and the fourth insulating layer 170 may be a thermosetting polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or a glass fiber-impregnated substrate.
  • a polymer resin such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build up Film) may be included.
  • a polyimide-based resin may be included.
  • the present invention is not limited to this
  • the third circuit pattern 164 is formed on the third insulating layer 160, and the fourth circuit pattern 174 is formed below the fourth insulating layer 170.
  • the third circuit pattern 164 and the fourth circuit pattern 174 may be formed using an additive process, a subtractive process, an MSAP (Modified Semi Additive Process) and a SAP (Semi Additive Process) which are general manufacturing processes of the printed circuit board. The detailed explanation thereon is omitted.
  • At least one conductive via 156, 158, 186, 188 is formed on the core substrate 100, the first insulating layer 130, the second insulating layer 140, the third insulating layer 160 and the fourth insulating layer 170.
  • the conductive via 156, 158, 186, 188 may be formed in such a manner that a via hole, which opens at least one of the core substrate 100, the first insulating layer 130, the second insulating layer 140, the third insulating layer 160 and the fourth insulating layer 170, is formed using the laser process, and an inner part of the via hole formed thereby is filled with a metal paste.
  • the conductive via 156, 158, 186, 188 is formed to conduct electricity in at least one or more areas of the first and second circuit patterns have conductive.
  • a metal material which forms the conductive via 156, 158, 186, 188 may be one material selected from the group consisting of Cu, Ag, Sn, Au, Ni and Pd.
  • the filling of the metal material may be performed using any one of a non-electrolyte or electrolyte plating process, a screen printing process, a sputtering process, an evaporation process, an ink jetting process and a dispensing process, or a combination thereof.
  • the terminal of the electronic device 120 is disposed to a side of the second insulating layer 140, and the conductive via 156 passes through the second insulating layer 140 so as to be connected to the terminal of the electronic device 120.
  • the protective layer 190 is formed on surfaces of the third insulating layer 160 and the fourth insulating layer 170.
  • the protective layer 190 may be a solder resist.
  • the inner layer-circuit pattern is not formed on the surface of the core substrate 110, lamination quality of the first insulating layer 130 to be laminated can be improved.
  • the bulge and dell problems generated from the printed circuit board in which the electronic device is arranged can be solved, thereby enabling quality of the printed circuit board to be improved
  • an insulating material having a larger thickness up to more than 10% compared to a thickness of a first insulating material is applied thereto.
  • a warpage phenomenon generated from the printed circuit board in which the electronic device is arranged can be minimized by managing the thickness of the second insulating layer corresponding to that of the first insulating layer, thereby increasing a mass production yield.
  • FIG. 4 through FIG. 22 are views for explaining, in the order of processes, the method of manufacturing the printed circuit board according to the exemplary embodiment.
  • the core substrate 110 is prepared.
  • the core substrate 110 may be a thermosetting polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or a glass fiber-impregnated substrate.
  • the core substrate includes a polymer resin
  • an epoxy-based insulating resin may be included.
  • a polyimide-based resin may be included.
  • the upper surface and the lower surface of the core substrate 110 are exposed to the outside. That is, in general, the metal layer is formed on at least one surface of the core substrate 110, and the inner layer-circuit pattern will be formed later using the metal layer.
  • the core substrate 110 which has a thickness same as or thinner than that of the electronic device 120 to be inserted later, and in which the inner layer-circuit pattern (or a metal layer) is not formed on both surfaces thereof, is prepared.
  • the cavity 112 is formed in at least one area of the core substrate 110.
  • the cavity 112 may be formed by any one processing method of a machining process, a laser process and a chemical process.
  • the cavity 112 is formed by the machining process, methods such as a milling process, a drill process, routing process and the like may be used.
  • a milling process a drill process, routing process and the like
  • an UV or CO 2 laser method may be used.
  • the core substrate may be opened using chemicals including aminosilane, ketones and the like.
  • the laser process is a cutting method of partially melting and evaporating a material by concentrating optical energy on a surface of the material to obtain a desired shape.
  • the laser process is used, even complex formation using a computer program may be easily processed, a composite material which is difficult to cut it using other methods, may be also processed
  • a cut diameter may be at least 0.005 mm, and it is advantageous that the range in processable thickness is large.
  • An YAG (Yttrium Aluminum Garnet) laser, a CO 2 laser or an UV laser may be used as the laser process drill.
  • the YAG laser is a laser which may process both the copper foil layer and the insulating layer
  • the CO 2 laser is a laser which may process only the insulating layer.
  • the cavity 112 is processed to have a larger size as much as about 100 ⁇ m to 200 ⁇ m than that of the electronic device to be inserted later.
  • an adhesive film 114 is adhered to the bottom of the core substrate 110 in which the cavity 112 is formed.
  • the adhesive film 114 may be formed of a same material as a general tape. Also, a carrier, which is usually used in a manufacturing process of the printed circuit board, may be used.
  • the electronic device 120 is inserted into the cavity 112.
  • the electronic device 120 may be fixed into the cavity 112 while being supported by an adhesive film 114 adhered to the bottom of the core substrate 110.
  • the electronic device 120 may include any one of a passive element and an active element.
  • the electronic device 120 may be a resistor, an inductor or a capacitor.
  • the terminal 122 for receiving currents or voltages supplied from the outside is formed on at least one surface of the electronic device 120.
  • a thickness of the first insulating material is calculated depending on a capacity of the electronic device 120 inserted into the cavity 112, thereby performing lay-up.
  • the first insulating material forms the first insulating layer 130, and a first metal layer 132 is formed on one surface of the first insulating layer 130.
  • the first insulating material may be a thermosetting or thermo plastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or glass-fiber impregnated substrate.
  • a polymer resin such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build up Film) and the like may be included.
  • a polyimide-based resin may be included.
  • the present invention is not specifically limited to this.
  • the cushion pad 134 is adhered onto the first metal layer 132, the first insulating 130 and the first metal layer 132 are formed on the core substrate 110 using the cushion pad 132 so that the upper part of the electronic device 120 inserted into the cavity 112 of the core substrate is embedded.
  • the cushion pad 134 is formed on the first metal layer 132, and the first insulating layer 130 is formed on the core substrate 110 by uniformly controlling pressure using the cushion pad 34 and controlling flow of the resin.
  • the flow of the resin was controlled using only the first insulating layer 130 and the first metal layer 132.
  • the first metal layer 132 has low elastic coefficient, each pressure of a flat portion and a via hole portion of the substrate having a step pulley such as the cavity 112 may be generated to be different from each other.
  • the first insulating layer 130 is formed by adhering the cushion pad 134 having high elastic coefficient onto the first metal layer, so the pressure of the flat portion in which the cavity 112 is not formed and the pressure of the part in which the cavity is formed may be uniformly maintained, thereby enabling a deviation in thickness to be reduced.
  • the cushion pad 134 may use a product having a thickness of 350 ⁇ m.
  • the thicknesses of the first insulating layer 130 are more uniformly formed, so a difference between a maximum thickness and a minimum thickness of the first insulating layer 130 ranges from 0 ⁇ m to 10 ⁇ m.
  • the thicknesses of the first insulating layer 130 are uniformly formed so that the difference between a maximum thickness and a minimum thickness of the first insulating layer 130 may range from 0 ⁇ m to 10 ⁇ m.
  • the cushion pad 132 formed on the first metal layer 132 and the adhesive film 114 adhered to the bottom of the core substrate 110 are removed by performing plasma treatment.
  • the second insulating layer 140 and the second metal layer are laid-up in a lower part of the core substrate 110.
  • the second metal layer 142 is formed on one surface of the second insulating layer 140.
  • the second insulating layer 140 is formed to be more than 10% thicker than the first insulating layer 130.
  • the thickness of the first insulating layer 130 is formed to be thick so that the resin can be prevented from flowing out to the outside of the printed circuit board.
  • the thickness of the second insulating layer 140 is thin compared to that of the first insulating layer because a large amount of resin flows out to the outside.
  • the process should be performed in a state of forming the second insulating layer 140 to be more than 10% thicker than the first insulating layer 130.
  • the second insulating layer 140 is laminated below the core substrate 110 by applying pressure to the second metal layer 142, so the thicknesses of the second insulating layer and the first insulating layer 130 become equal to each other.
  • the second insulating material may be a thermosetting or thermo plastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or glass-fiber impregnated substrate.
  • a polymer resin such as FR-4, BT (Bismaleimide Triazine), ABF (Ajinomoto Build up Film) and the like may be included.
  • a polyimide-based resin may be included.
  • the present invention is not specifically limited to this.
  • a first via hole 152 to which the terminal 122 of the electronic device 120 embedded in the core substrate 110 is exposed, is formed by opening the second insulating layer 140 and the second metal layer 142.
  • a second via hole 154 which opens the core substrate 110, the first insulating layer 130, the first metal layer 132, and the second insulating layer 140 and the second metal layer 142, is formed.
  • the first via hole 152 and the second via hole 154 may be formed by any one processing method of a machining process, a laser process and a chemical process.
  • first via hole 152 and the second via hole 154 are formed by the machining process
  • methods such as a milling process, a drilling process and a routing process and the like may be used.
  • a milling process such as a drilling process and a routing process and the like
  • an UV or CO 2 laser method may be used.
  • chemicals including aminosilane, ketones and the like may be used.
  • the first conductive via 156 and the second conductive via 158 are formed by filling the first via hole 152 and the second via hole 154 with a metal material.
  • the first conductive via 156 may be formed to be filled with the entire of the via first hole 152.
  • the second conductive via 158 may be selectively formed in only an inner wall of the second via hole 154.
  • the metal material may be one material selected from the group consisting of Cu, Ag, Sn, Au, Ni and Pd.
  • the filling of the metal material may be performed using any one of a non-electrolyte or electrolyte plating process, a screen printing process, a sputtering process, an evaporation process, an ink jetting process and a dispensing process, or a combination thereof.
  • the first circuit pattern 136 is formed by patterning the first metal layer
  • the second circuit pattern 144 is formed by patterning the second metal layer.
  • the first circuit pattern 136 and the second circuit pattern 144 may be formed using an additive process, a subtractive process, a modified semi additive process (MSAP) or a semi additive process (SAP).
  • MSAP modified semi additive process
  • SAP semi additive process
  • the third insulating layer 160 and the third metal layer 162 are laid-up in an upper part of the first insulating layer 130, and the fourth insulating layer 170 and the fourth metal layer 172 are laid up in a lower part of the second insulating layer 140.
  • the third insulating layer 160 in which the first circuit pattern 136 is embedded and the third metal layer 162 are formed on the first insulating layer 130, and the fourth insulating layer 170 in which the second circuit pattern 144 is embedded and the fourth metal layer 172 are formed below the second insulating layer 140.
  • the third via hole 182, in which the first circuit pattern is exposed is formed by processing the third insulating layer 160 and the third metal layer 162.
  • a fourth via hole 184 to which the second circuit pattern 144 is exposed is formed by processing the fourth insulating layer 170 and the fourth metal layer 172.
  • the third and fourth via holes 182, 184 may be formed using an excimer laser which emits a laser beam having the wavelength of an ultraviolet region.
  • an excimer laser i.e. a KrF excimer laser (i.e. a krypton fluoride laser having a center wavelength of 248nm), or an ArF excimer laser (i.e. an argon fluoride laser having a center wavelength of 193nm) may be applied.
  • the third conductive via 186 and a fourth conductive via 188 are formed by filling the third via hole 182 and the fourth via hole 184 with a metal material.
  • the metal material may be any one material selected from the group consisting of Cu, Ag, Sn, Au, Ni and Pd.
  • the filling of the metal material may be performed using any one process of a non-electrolytic or electrolytic plating process, a screen printing process, a sputtering process, an evaporation process, an ink jetting process and a dispensing process, or a combination thereof.
  • the third circuit pattern 164 and the fourth circuit pattern 174 are formed by patterning the third metal layer 162 and the fourth metal layer.
  • the third circuit pattern 164 and the fourth circuit pattern 174 may be formed using an additive process, a subtractive process, a modified semi additive process (MSAP) or a semi additive process (SAP).
  • MSAP modified semi additive process
  • SAP semi additive process
  • the protect layer 190 is formed on the third insulating layer 160 and the fourth insulating layer 170 so as to cover a surface of the third insulating layer 160, the third circuit pattern 164, a surface of the fourth insulating layer 170 and the fourth circuit pattern 174.
  • the protective layer 190 may be formed of a solder resist.
  • the surfaces of the third circuit pattern 164 and the fourth circuit pattern 174, which should be exposed, are exposed by opening the protective layer 190.
  • the problem such as the lack of uniformity in flow of the resin caused by a space formed between the via hole of the core substrate and the electronic device can be solved, thereby enabling a deviation in thickness to be minimized.
  • the bulge and dell problems generated from the printed circuit board in which the electronic device is arranged can be solved by minimizing the lack of uniformity in flow of the resin and a deviation in thickness, thereby enabling quality of the printed circuit board to be improved.
  • FIG. 23 is a view for explain a thickness of the printed circuit board of the conventional art.
  • FIG. 24 is a view for explain a thickness of the printed circuit board of the present invention.
  • a thickness (C) of a first area and a thickness (C') of a second area of the first insulating layer formed on the first electronic device 210 are designed as 55 ⁇ m to be identical to each other, a really measured thickness of the first area of the first insulating material formed on the first electronic device 210 was 45 ⁇ m, and a measured thickness of the second area of the first insulating material formed on the first electronic device 210 was 65 ⁇ m.
  • a difference in thickness reaches 20 ⁇ m.
  • a deviation in really measured thickness of the first insulating layer ranges from 45 ⁇ m to 65 ⁇ m. Consequently, the phenomenon of a bulge or dell of 3 mm is generated from a region of the printed circuit board in which the electronic devices 210, 220 are mounted, around the region.
  • the thickness (C) of the first area and the thickness (C') of the second area of the first insulating layer formed on the first electronic device 210 are designed as 55 ⁇ m to be identical to each other as shown in Table 2,because the core substrate is the dummy core substrate in which the circuit pattern is not formed on the upper surface thereof, as shown in Table 2, a really measured thickness of the first area of the first insulating material formed on the first electronic device 210 was 55 ⁇ m, and a measured thickness of the second area of the first insulating material formed on the first electronic device 210 was 65 ⁇ m. Thus, depending on the position of the first insulating layer, a difference in thickness is only 10 ⁇ m.
  • the difference in really measured thickness is only about 10 ⁇ m, a surface difference caused by a bulge or dell generated from the region of the printed circuit board in which the electronic devices 210, 220 are mounted, and around the region is only 1 mm.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/KR2013/004110 2012-09-28 2013-05-09 Carte de circuit imprimé WO2014051233A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020120109568A KR20140042604A (ko) 2012-09-28 2012-09-28 인쇄회로기판 및 이의 제조 방법
KR10-2012-0109568 2012-09-28

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WO2014051233A2 true WO2014051233A2 (fr) 2014-04-03

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KR (1) KR20140042604A (fr)
TW (1) TWI562697B (fr)
WO (1) WO2014051233A2 (fr)

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US9761518B2 (en) 2015-02-23 2017-09-12 Kyocera Corporation Cavity substrate and method of manufacturing the same
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US10448512B2 (en) 2015-01-22 2019-10-15 Samsung Electro-Mechanics Co., Ltd. Printed circuit board
TWI729026B (zh) * 2015-12-21 2021-06-01 美商英特爾公司 印刷電路板(pcb)總成及形成其之方法
CN113015327A (zh) * 2019-12-20 2021-06-22 奥特斯奥地利科技与***技术有限公司 部件承载件及制造部件承载件的方法

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IT201900006736A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
TWI725750B (zh) * 2020-02-21 2021-04-21 達方電子股份有限公司 薄膜電路板
WO2023101442A1 (fr) * 2021-11-30 2023-06-08 엘지이노텍 주식회사 Boîtier semi-conducteur

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TWI325745B (en) * 2006-11-13 2010-06-01 Unimicron Technology Corp Circuit board structure and fabrication method thereof
TWI418272B (zh) * 2009-08-25 2013-12-01 Samsung Electro Mech 處理核心基板之空腔的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10448512B2 (en) 2015-01-22 2019-10-15 Samsung Electro-Mechanics Co., Ltd. Printed circuit board
US9761518B2 (en) 2015-02-23 2017-09-12 Kyocera Corporation Cavity substrate and method of manufacturing the same
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
TWI611525B (zh) * 2015-07-31 2018-01-11 台灣積體電路製造股份有限公司 半導體構裝及其方法
TWI729026B (zh) * 2015-12-21 2021-06-01 美商英特爾公司 印刷電路板(pcb)總成及形成其之方法
CN113015327A (zh) * 2019-12-20 2021-06-22 奥特斯奥地利科技与***技术有限公司 部件承载件及制造部件承载件的方法
EP3840548A1 (fr) * 2019-12-20 2021-06-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Support de composant et son procédé de fabrication
US11551989B2 (en) 2019-12-20 2023-01-10 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method of manufacturing the same

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Publication number Publication date
TWI562697B (en) 2016-12-11
TW201414389A (zh) 2014-04-01
KR20140042604A (ko) 2014-04-07

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