WO2014045989A1 - Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor device Download PDF

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Publication number
WO2014045989A1
WO2014045989A1 PCT/JP2013/074642 JP2013074642W WO2014045989A1 WO 2014045989 A1 WO2014045989 A1 WO 2014045989A1 JP 2013074642 W JP2013074642 W JP 2013074642W WO 2014045989 A1 WO2014045989 A1 WO 2014045989A1
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region
circuit
semiconductor substrate
semiconductor wafer
semiconductor
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PCT/JP2013/074642
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French (fr)
Japanese (ja)
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元雄 鷲谷
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ピーエスフォー ルクスコ エスエイアールエル
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Publication of WO2014045989A1 publication Critical patent/WO2014045989A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor wafer and a semiconductor device.
  • a semiconductor chip is separated from a semiconductor wafer by forming a plurality of similar circuit regions made of a desired integrated circuit on a semiconductor wafer via a cutting region (scribe region) and cutting the scribe region. It is formed. Therefore, the semiconductor chip is provided with a protective layer called a guard ring on the outer periphery.
  • the guard ring is a member that is formed to surround the periphery of the circuit area using a wiring layer that extends from the diffusion layer formed on the semiconductor wafer to the upper layer of the wafer. Protect. Further, by providing the guard ring, the mechanical strength of the semiconductor chip after separation is enhanced.
  • test wiring tends to become complicated as the semiconductor chip is miniaturized, and if it is formed inside the semiconductor chip, the chip area may be increased. In particular, an increase in the number of pads may greatly affect an increase in chip area.
  • Patent Document 1 a structure is known in which an increase in the chip area is suppressed by drawing a wiring to the scribe region and providing a pad in the scribe region.
  • a semiconductor substrate including a circuit region having an internal circuit region in which an integrated circuit is disposed, a scribe region disposed around the circuit region, a semiconductor substrate covering the semiconductor substrate, and a plurality of wirings.
  • a multilayer wiring layer provided, a guard ring formed in the multilayer wiring layer between the internal circuit region and the scribe region in the circuit region, an inspection pad formed in the multilayer wiring layer in the scribe region, A conductive portion for electrically connecting the test pad and the integrated circuit in the internal circuit region, and a conductive portion formed of a diffusion layer formed on the semiconductor substrate at a portion intersecting the guard ring; It is a semiconductor wafer.
  • a semiconductor substrate a circuit region formed on the semiconductor substrate and provided with an integrated circuit, a multilayer wiring layer that covers the semiconductor substrate and includes a plurality of wirings, and surrounds the circuit region And a diffusion layer formed on the semiconductor substrate at a portion that intersects the guard ring in a planar manner, and a conduction portion electrically connected to the integrated circuit in the circuit region.
  • a semiconductor device having a conductive portion and a diffusion layer of the conductive portion reaching an end portion of the semiconductor substrate.
  • a semiconductor substrate including a circuit region having an integrated circuit and a scribe region, a test pad disposed in the scribe region, and electrical connection for electrically connecting the test pad and the integrated circuit.
  • a step of bringing the probe into contact with an inspection pad of a semiconductor wafer having a portion and a diffusion layer formed on a semiconductor substrate that constitutes a part of the conductive portion, and performing an operation test of the integrated circuit by applying a signal to the probe A method for manufacturing a semiconductor device comprising: a step of performing, and a step of separating a semiconductor substrate by cutting a scribe region after performing an operation test.
  • the present invention it is possible to improve the manufacturing yield in the semiconductor device technology in which wiring is drawn from the circuit region to the scribe region, probing the scribe region, and conducting to the circuit region.
  • FIG. 3 is an enlarged view of a circuit region 100 constituting a semiconductor wafer 200.
  • FIG. 3 is a cross-sectional view showing the vicinity of a guard ring 206 in FIG. 2.
  • FIG. 3 is a cross-sectional view showing the vicinity of a boundary between regions 102 and 203 in FIG. 2.
  • FIG. 3 is an enlarged view near a conductive portion 204 in FIG. 2.
  • FIG. 6 is a cross-sectional view taken along the line A-A ′ of FIG. 5. It is sectional drawing of a diffusion area
  • region. 3 is a cross-sectional view of a conductive part 204.
  • FIG. 6 is a circuit diagram showing wiring of a conductive portion 204.
  • FIG. It is a circuit diagram of the semiconductor chip 100a which comprises the semiconductor wafer 200a which concerns on 2nd Embodiment. It is a figure which shows the shape of the automatic connection pad 251.
  • FIG. It is a top view of the semiconductor chip 100 which comprises the semiconductor wafer 200b which concerns on 3rd Embodiment, Comprising: Only two adjacent semiconductor chips 100 are shown in figure.
  • It is a top view of the semiconductor chip 100 which comprises the semiconductor wafer 200c which concerns on 4th Embodiment, Comprising: Only two adjacent semiconductor chips 100 are shown in figure.
  • It is sectional drawing of NMOS transistor 300d which comprises the semiconductor wafer 200d which concerns on 5th Embodiment.
  • FIGS. 1 is an overall plan view of the semiconductor wafer 200
  • FIG. 2 is a plan view of the periphery of the circuit region 100 included in the semiconductor wafer 200
  • FIG. 1 is an overall plan view of the semiconductor wafer 200
  • FIG. 2 is a plan view of the periphery of the circuit region 100 included in the semiconductor wafer 200
  • FIG. 1 is an overall plan view of the semiconductor wafer 200
  • FIG. 2 is a plan view of the periphery of the circuit region 100 included in the semiconductor wafer 200
  • the semiconductor wafer 200 has a disk-shaped semiconductor substrate 201. On the semiconductor substrate 201, a plurality of similar circuit regions 100 in which a desired integrated circuit is formed are arranged in a matrix. In FIG. 1, each of rectangles formed by lines formed in a lattice shape corresponds to the circuit region 100.
  • the integrated circuit provided in the circuit area 100 is not limited to a predetermined one, but may be a DRAM (Dynamic Random Access Memory) or a logic circuit, for example.
  • the lines formed in a lattice shape in FIG. 1 are regions that separate circuit regions 100 arranged adjacent to each other, and are scribe regions 203 that are cut when the circuit regions 100 are separated and separated into individual pieces. is there.
  • Each of the separated circuit regions 100 is a semiconductor chip.
  • the semiconductor wafer 200 has a conductive portion 204 drawn out from the internal circuit region 102 having the internal circuit to be protected in the circuit region 100 to the scribe region 203. Further, a guard ring 206 is provided on the outer periphery of the internal circuit region 102 in the circuit region 100 to protect the internal circuit region 102. The configurations of the conductive portion 204 and the guard ring 206 will be described in detail later.
  • the scribe region 203 is a portion that is cut and disappears when the semiconductor region is separated from the semiconductor wafer 200 to obtain a semiconductor chip.
  • the scribe region 203 is a portion through which a blade for separating the circuit region 100 from the semiconductor wafer 200 passes, and is thereby crushed and disappears.
  • the arrows in FIG. 1 indicate the path of the blade for separating the chips into pieces, but the blade traveling direction is not limited to that reversed for each row as in FIG.
  • the scribe region 203 has a width of several tens to several hundreds of ⁇ m.
  • a probe inspection element for measuring element characteristics of a completed wafer and a needle pad for the element Probing pads
  • a test pad 205 that is a needle pad is provided in the scribe region 203 and is connected to the in-chip pad 207 in the circuit region 100 via the conduction portion 204.
  • the in-chip pad 207 is a bonding-dedicated pad that is not needle-contacted.
  • the inspection pad 205 and the in-chip pad 207 need to be disposed on the uppermost layer in order to be subjected to external probing or bonding, and a part of the protective film on the upper surface of each pad 205, 207 is removed and exposed. It has become a state.
  • the guard ring 206 uses a multilayer wiring formed on the main surface of the semiconductor substrate 201 (for example, the surface of a diffusion region formed in the semiconductor substrate 201).
  • the contact plug 103, the first wiring 104, the first via plug 105, the first metal wiring 106, the second via plug 107, and the first are sequentially arranged from the side close to the substrate surface.
  • An example constituted by two metal wirings 108, a third via plug 109, and a third metal wiring 110 is shown. These multilayer wirings are insulated from each other and protected by the interlayer insulating film 111.
  • the contact plug 103 and the first wiring 104 for example, tungsten, conductive polysilicon (polycrystalline silicon), or the like can be used.
  • materials for the first to third via plugs 105, 107, 109 and the first to third metal wirings 106, 108, 110 for example, aluminum or copper can be applied.
  • silicon oxide, silicon nitride, or the like can be used as the material of the interlayer insulating film 111. Note that the above-described inspection pads 205 and in-chip pads 206 may be formed of the same material in the same layer as the third metal wiring 110.
  • the above-described multilayer wiring is arranged so as to surround the inner circuit region 102 to constitute the guard ring 206 of the present embodiment.
  • the internal circuit region 102 can be protected from external contamination factors when cutting to obtain a semiconductor chip by dividing the circuit region 100 into individual pieces.
  • the mechanical strength after singulation can be strengthened.
  • the guard ring 206 is double, but it may be single or triple. If it is a single layer, the area occupied by the circuit region 100 can be reduced.
  • the conductive portion 204 is a conductive portion for connecting the internal circuit region 102 in the circuit region 100 and the inspection pad 205 in the scribe region 203.
  • the conductive portion 204 of the present embodiment is a diffusion layer formed in the semiconductor substrate 201 as a portion that reaches the internal circuit region 102 from the scribe region 203 through the region where the guard ring 206 is disposed. 211.
  • a diffusion layer also referred to as a diffusion region or an active region
  • STI groove type isolation portion
  • Trench (Isolation) etc. is a region partitioned on the main surface of the substrate.
  • the diffusion pad 211 as described above can electrically connect the inspection pad 205 in the guard ring region 203 and the internal circuit region 102 without using the upper layer wiring.
  • the inspection pad 205 and the diffusion layer 211 are connected in the guard ring region 203 via the scribe region side multilayer wiring 215.
  • the device under test belonging to the internal circuit region 102 and the diffusion layer 211 are connected in the internal circuit region 102 via the internal circuit side multilayer wiring 213.
  • the diffusion layer 211 shows an example in which silicon is an N-type conductivity type including a donor impurity, but silicon may be a P-type conductivity type including an acceptor impurity. Then, the conductivity of the conductive portion 204 can be adjusted by adjusting the amount of impurities.
  • the diffusion layer 211 formed on the semiconductor substrate 201 is applied as the conductive portion 204 that is drawn from the internal circuit region 102 to the scribe region 203, whereby the circuit region 100 is separated into individual pieces.
  • the metal wiring is not exposed to the end. Therefore, the concern of moisture and contamination factors entering from the interface between the wiring material and the interlayer insulating film material is reduced.
  • the concern about short-circuit defects that occur between the wiring and other conductive parts is reduced. As a result, the manufacturing yield of the semiconductor device is improved.
  • FIG. 5 is a plan view of the surface level of the semiconductor substrate 201 and shows the periphery of the diffusion layer 211 in the conductive portion 204.
  • FIG. 6 is a cross-sectional view taken along line A-A ′ of FIG.
  • the conduction part 204 of the present embodiment has a diffusion layer 211 formed on the surface of the semiconductor substrate 201 from the guard ring region 203 to the internal circuit region 102.
  • the diffusion layer 211 is connected to the internal circuit side multilayer wiring 213 made of multilayer wiring in the internal circuit region 102 at both ends thereof, and is connected to the scribe region side multilayer wiring 215 made of multilayer wiring in the scribe region 203.
  • the layer using the contact plug 103 which is the lowermost layer of the guard ring 206 is omitted.
  • the guard ring 206 is prevented from contacting.
  • a MOS transistor (planar field effect transistor) 300 having a gate electrode 217 disposed so as to cross the diffusion layer 211 may be disposed.
  • a cross-sectional view of the MOS transistor is shown in FIG.
  • the diffusion layer 211 may have a crack stopper 231 formed of an STI-shaped separation part inside.
  • the diffusion layer 211 is not divided by the crack stopper 231 and is formed around the crack stopper 231.
  • the diffusion layer 211 has a crack stopper 231 composed of a separation portion inside, but by detouring to surround the diffusion stopper 211, the internal circuit side multilayer wiring 213, the MOS transistor 300, (the crack stopper 231), Electrical connection paths are formed from the diffusion layers 211 to (scribe region 203) to the scribe region-side multilayer wiring 215.
  • the diffusion layer 211 constitutes the drain and source regions of the MOS transistor 300 formed on the semiconductor substrate 201 (here, P-type conductivity type), and the gate electrode 217 is provided therebetween. Yes.
  • the gate electrode 217 is connected to an evaluation pad 219 provided in the scribe region 203 via an evaluation diffusion layer 221.
  • the wiring for the gate electrode 217 is commonly connected to the plurality of diffusion layers 211 (and the inspection pad 205).
  • a current is supplied to the MOS transistor 300 by flowing a current to the gate electrode 217 via the evaluation pad 219 only during monitoring such as a needle contact test before the circuit region 100 is separated from the semiconductor wafer 200. It flows (that is, the conducting part 204 becomes conductive).
  • the wiring for the gate electrode 217 disappears, so that no current flows through the MOS transistor 300 (that is, the conducting portion 204 is turned off).
  • the diffusion layer 211 has a built-in switch circuit, it is possible to prevent current leakage through the conduction portion 204 (diffusion layer 211).
  • the semiconductor wafer 200 is configured with the circuit region 100 and the scribe region 203 connected to each other.
  • the semiconductor chip 100 there is an in-chip pad 207 which is a bonding dedicated pad which is not touched by a needle, and a scribe area 203 is provided with an inspection pad 205 which is a probe dedicated pad.
  • the VSS terminal in the chip that shares the power supply during the test is used for both bonding and needle contact.
  • MOS transistor 300 When performing a probe test, it is necessary to turn on the switch (MOS transistor 300), and a voltage for turning on the MOS transistor 300 as a switch circuit is applied between the VSS terminal and the monitor EN terminal.
  • the MOS transistor 300 is turned on, the inspection pad 205 and the in-chip pad 207 are brought into conduction, and the inspection using the inspection pad 205 can be performed.
  • the inspection pad 205 disappears by scribing. Since the node of the monitor EN terminal is pulled down to VSS in the chip, the node is not connected and the MOS transistor 300 is turned off. In this state, since the potential of the cross section of the diffusion layer 211 is the same as that of the substrate, no current flows through the diffusion layer 211 even if the substrate is short-circuited externally. Since the other terminal cross sections are turned off by the MOS transistor 300, similarly, no leakage current flows between the substrate and other diffusion cross sections.
  • an evaluation buffer is provided in the scribe area 203 in the first embodiment.
  • the conductive portion 204 has the diffusion layer 211, but the diffusion layer 211 has a higher electrical resistance than a metal wiring or the like of a multilayer wiring. Therefore, when the output signal via the diffusion layer 211 is monitored, there is a possibility that the output signal cannot be measured correctly in the structure as shown in FIG. 10A due to the resistance value of the diffusion layer 211.
  • an evaluation buffer 241 is provided in the scribe area 203 as shown in FIG.
  • the external buffer may be directly connected, but it is connected to the input / output pad 245 used for both input and output. If the external buffer is connected to the evaluation pad, an input signal from this terminal to the chip cannot be applied. This is because the output buffer and the input signal cannot be switched accurately and operated unless the output operation and the input operation are clearly understood from the outside.
  • the diffusion layer 211 is connected to the input / output pad 245, it is desirable to have a configuration as shown in FIGS. 10 (c) and 10 (d).
  • the OUTPUT signal in the output buffer in the circuit area 100 a is assigned to the input / output buffer control in the scribe area 203.
  • a switching circuit 247 for switching input / output is provided in the scribe area 203.
  • the automatic connection pad 251 is used.
  • the automatic connection pad 251 has a structure in which input / output pads in the chip are separated into an input pad 251a and an output pad 251b before wire bonding, and each of them is an input conduction portion. 221a and an output conducting portion 221b having a buffer circuit 241.
  • the input pad 251a and the output pad 251b are provided adjacent to each other (having a structure in which the pads are separated by providing slits), and wire bonding 252 is performed so as to connect the input pad 251a and the output pad 251b.
  • the input pad 251a and the output pad 251b are connected.
  • the output buffer (buffer circuit 241) disposed in the scribe area 203 may be connected to the OUT terminal in the chip, and the input terminal may be independently disposed in the scribe area 203.
  • the planar shape of the automatic connection pad 251 is not particularly limited as long as the input pad 251a and the output pad 251b are electrically separated from each other before wire bonding and are connected to each other after wire bonding. Absent.
  • the automatic connection pad 251 a rectangle illustrated in FIG. 11B, a concavo-convex shape illustrated in FIG. 11C, and an oblique shape illustrated in FIG. 11D are illustrated, but other shapes may be used. .
  • the semiconductor wafer 200a is formed on the outer periphery of the conductive portion 204 drawn from the internal circuit region 102 of the circuit region 100a to the scribe region 203 and the internal circuit region 102 of the circuit region 100a.
  • the conductive portion 204 is formed on the main surface of the semiconductor substrate as a portion extending from the internal circuit region 102 to the scribe region 203 through the region where the guard ring 206 is disposed.
  • a diffusion layer 211 is provided. Therefore, the same effects as those of the first embodiment are obtained.
  • the semiconductor wafer 200 a is provided with an evaluation buffer in the scribe region 203. Therefore, the output signal can be monitored regardless of the influence of the resistance value of the diffusion layer 211.
  • test pads 205 are shared among a plurality of circuit regions 100, and each is connected to the center pad 271 via the diffusion layer 211. Note that in the third embodiment, elements that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.
  • the semiconductor wafer 200b according to the third embodiment has a center pad 271 that is electrically connected between different circuit regions 100 in the wafer state, and can share signals in the wafer state. For example, paratests are possible. And the diffusion layer 211 similar to the said 1st Embodiment is applied to the conduction
  • the length of the diffusion layer 211 it is more preferable to set the length of the diffusion layer 211 so that the metal wiring portion 208 of the conducting portion 204 is accommodated inside the width through which the scribing blade passes when viewed in the scribe region 203. Thereby, the metal wiring part 208 is not exposed to the outside after scribing.
  • the semiconductor wafer 200 b is formed on the outer periphery of the internal circuit region 102 in the circuit region 100 and the conductive portion 204 drawn from the internal circuit region 102 in the circuit region 100 to the scribe region 203.
  • the conductive portion 204 is formed on the main surface of the semiconductor substrate as a portion extending from the internal circuit region 102 to the scribe region 203 through the region where the guard ring 206 is disposed.
  • a diffusion layer 211 is provided. Accordingly, the same effects as those of the first embodiment are obtained.
  • the semiconductor wafer 200 b shares the inspection pad 205 among the plurality of circuit regions 100, and each is connected to the center pad 271 via the diffusion layer 211. Therefore, signals can be shared by different circuit regions 100, and paratests are possible.
  • the inspection pad of the scribe area 203 in the third embodiment is not provided, and the scribe area 203 is connected by a metal wiring portion 208.
  • elements that perform the same functions as those in the third embodiment are denoted by the same reference numerals, and different portions from the third embodiment will be mainly described.
  • the semiconductor wafer 200c according to the fourth embodiment has no pad provided in the scribe region 203, and the scribe region 203 has a structure in which the metal wiring part 208 is directly connected.
  • the same effects as those of the third embodiment can be obtained, and the number of needle pad pads arranged in the scribe region 203 can be reduced. As a result, it is possible to increase the number of the plurality of circuit regions 100 that can perform the paratest.
  • the fifth embodiment uses a P-type diffusion layer instead of an N-type diffusion layer as the diffusion layer 211 in the first embodiment. Note that in the fifth embodiment, elements that perform the same functions as in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.
  • the NMOS transistor 300d of the semiconductor wafer 200d (circuit region 100d) uses a P-type diffusion layer as the diffusion layer 211a, not an N-type diffusion layer.
  • the diffusion layer 211a is not necessarily limited to the N-type diffusion layer, and a P-type diffusion layer may be used. By adopting such a structure, unlike the case where an N-type diffusion layer is used, conduction of a negative voltage is possible.
  • an NWell layer 261 is provided around the diffusion layer 211a and separated from the semiconductor substrate 201 as shown in FIG.
  • the semiconductor wafer 200d is formed on the outer periphery of the conductive portion 204 drawn from the internal circuit region 102 of the circuit region 100d to the scribe region 203 and the internal circuit region 102 of the circuit region 100d.
  • the conductive portion 204 is a diffusion formed on the main surface of the semiconductor substrate 201 as a portion extending from the internal circuit region 102 to the scribe region 203 through the region where the guard ring 206 is disposed.
  • a layer 211a is provided. Accordingly, the same effects as those of the first embodiment are obtained.
  • the diffusion layer 211a of the NMOS transistor 300d is configured by a P-type diffusion layer. Therefore, it is possible to conduct a negative voltage.
  • the structure in which the evaluation buffer 241 is provided in the scribe region 203 is illustrated.
  • the diffusion layer 211 has resistance. If a signal can be evaluated, the evaluation buffer 241 is not necessarily provided.
  • Circuit area 102 Internal circuit area 200: Semiconductor wafer 200b: Semiconductor wafer 200c: Semiconductor wafer 200d: Semiconductor wafer 201: Substrate 203: Scribe area 204: Conductive portion 205: Inspection pad 206: Guard ring 207: In-chip pad 211: diffusion layer 211a: diffusion layer 213: internal circuit side multilayer wiring 215: scribe region side multilayer wiring 217: gate electrode 219: evaluation pad 221: evaluation diffusion layer 231: crack stopper 241: buffer 245: input / output pad 247 : Switching circuit 251: automatic connection pad 251a: input pad 251b: output pad 252: wire bonding 261: NWell layer 271: center pad 300: MOS transistor (planar type field effect) Transistor)

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Abstract

The present invention addresses the problem of increasing the manufacturing yield of semiconductor devices in a technique involving the use of a semiconductor wafer in which wiring is drawn into a scribing region. A semiconductor wafer (200) has a semiconductor substrate that includes a circuit region (100) and a scribing region (203) arranged around the circuit region (100); a multi-layered wiring layer for covering the semiconductor substrate; a guard ring (206); an inspection pad (205) arranged in the scribing region (203); and a conducting part (204) for connecting an integrated circuit in an internal circuit region (102) inside the circuit region (100) with the inspection pad (205), a portion of the conducting part (204) intersecting the guard ring (206) being configured from a diffusion layer in the semiconductor substrate.

Description

半導体ウェハ、半導体装置および半導体装置の製造方法Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device
　本発明は、半導体ウェハおよび半導体装置に関する。 The present invention relates to a semiconductor wafer and a semiconductor device.
　半導体チップは、半導体ウェハ上に、所望の集積回路からなる同様の複数の回路領域を、切断領域（スクライブ領域）を介して形成し、スクライブ領域を切断することにより半導体ウェハから個片化されて形成される。そのため、半導体チップは、外周にガードリングと呼ばれる保護層を設けている。ガードリングは、半導体ウェハに形成された拡散層からウェハ上層まで達する配線層を用い、回路領域の周囲を囲むように形成される部材であり、外部からの水分や汚染要因の侵入から回路領域を保護する。また、ガードリングを備えることで、個片化後の半導体チップの機械強度が強化される。 A semiconductor chip is separated from a semiconductor wafer by forming a plurality of similar circuit regions made of a desired integrated circuit on a semiconductor wafer via a cutting region (scribe region) and cutting the scribe region. It is formed. Therefore, the semiconductor chip is provided with a protective layer called a guard ring on the outer periphery. The guard ring is a member that is formed to surround the periphery of the circuit area using a wiring layer that extends from the diffusion layer formed on the semiconductor wafer to the upper layer of the wafer. Protect. Further, by providing the guard ring, the mechanical strength of the semiconductor chip after separation is enhanced.
　一方、半導体チップは、信頼性確保のための導通テストを行うため、テスト用の回路およびテスト時にプローブを接触させるためのパッド等の配線を形成する必要がある。 On the other hand, since a semiconductor chip performs a continuity test for ensuring reliability, it is necessary to form a test circuit and wiring such as a pad for contacting the probe during the test.
　このテスト用の配線は、半導体チップの微細化に伴い、複雑化する傾向にあり、半導体チップ内部にこれを形成すると、チップ面積の増大を招く恐れがある。特にパッドの数の増大はチップ面積の増大に大きく作用する恐れがある。 The test wiring tends to become complicated as the semiconductor chip is miniaturized, and if it is formed inside the semiconductor chip, the chip area may be increased. In particular, an increase in the number of pads may greatly affect an increase in chip area.
　そこで、配線をスクライブ領域に引き出してスクライブ領域にパッドを設けることにより、チップ面積の増大を抑えた構造が知られている（特許文献１）。 Therefore, a structure is known in which an increase in the chip area is suppressed by drawing a wiring to the scribe region and providing a pad in the scribe region (Patent Document 1).
特開２００５－３５３７６５号公報JP 2005-353765 A
　しかしながら、特許文献１のように、回路領域からスクライブ領域に配線を引き出す構造を本発明者が検討したところ、以下の課題を有することが分かった。このようにして回路領域からスクライブ領域に配線を引き出すと、半導体チップを個片化した際に、引き出した配線の端部が露出する。この露出部分において、配線材料と層間絶縁膜材料の界面などから水分や汚染要因が浸入し易くなる。また、切断の際に生じる配線の切削屑等の付着により、配線と他導通部（例えば拡散層など）との間でショート不良を生じる可能性がある。これらの現象により、半導体装置の製造歩留まりが低減し得ることが分かった。 However, when the inventor examined a structure in which wiring is drawn from the circuit region to the scribe region as in Patent Document 1, it was found that the following problems were encountered. When the wiring is drawn out from the circuit area to the scribe area in this way, the end portion of the drawn wiring is exposed when the semiconductor chip is separated. In this exposed portion, moisture and contamination factors easily enter from the interface between the wiring material and the interlayer insulating film material. Moreover, there is a possibility that a short-circuit failure may occur between the wiring and another conductive portion (for example, a diffusion layer) due to adhesion of cutting chips or the like of the wiring generated at the time of cutting. It has been found that the manufacturing yield of semiconductor devices can be reduced by these phenomena.
　本発明の第１の態様は、集積回路が配置された内部回路領域を有する回路領域と、回路領域の周囲に配置されたスクライブ領域とを含む半導体基板と、半導体基板を覆い、複数の配線を備えた多層配線層と、回路領域の内部回路領域とスクライブ領域との間の多層配線層に形成されたガードリングと、スクライブ領域の多層配線層に形成された検査用パッドと、スクライブ領域内の検査用パッドと内部回路領域内の集積回路とを電気的に接続する導通部であって、ガードリングと交差する部分では、半導体基板に形成された拡散層で構成された導通部と、を有する半導体ウェハである。 According to a first aspect of the present invention, there is provided a semiconductor substrate including a circuit region having an internal circuit region in which an integrated circuit is disposed, a scribe region disposed around the circuit region, a semiconductor substrate covering the semiconductor substrate, and a plurality of wirings. A multilayer wiring layer provided, a guard ring formed in the multilayer wiring layer between the internal circuit region and the scribe region in the circuit region, an inspection pad formed in the multilayer wiring layer in the scribe region, A conductive portion for electrically connecting the test pad and the integrated circuit in the internal circuit region, and a conductive portion formed of a diffusion layer formed on the semiconductor substrate at a portion intersecting the guard ring; It is a semiconductor wafer.
　本発明の第２の態様は、半導体基板と、半導体基板に形成され、集積回路が配置された回路領域と、半導体基板を覆い、複数の配線を備えた多層配線層と、回路領域を囲むように多層配線層に形成されたガードリングと、回路領域内の集積回路と電気的に接続された導通部であって、ガードリングと平面的に交差する部分において半導体基板に形成された拡散層を有する導通部と、を有し、導通部の拡散層は半導体基板の端部に達している半導体装置である。 According to a second aspect of the present invention, a semiconductor substrate, a circuit region formed on the semiconductor substrate and provided with an integrated circuit, a multilayer wiring layer that covers the semiconductor substrate and includes a plurality of wirings, and surrounds the circuit region And a diffusion layer formed on the semiconductor substrate at a portion that intersects the guard ring in a planar manner, and a conduction portion electrically connected to the integrated circuit in the circuit region. A semiconductor device having a conductive portion and a diffusion layer of the conductive portion reaching an end portion of the semiconductor substrate.
　本発明の第３の態様は、集積回路を備えた回路領域およびスクライブ領域を含む半導体基板と、スクライブ領域に配置された検査用パッドと、検査用パッドと集積回路とを電気的に接続する導通部と、導通部の一部を構成する半導体基板に形成された拡散層と、を有する半導体ウェハの検査用パッドにプローブを接触する工程と、プローブに信号を与えることで集積回路の動作テストを行なう工程と、動作テストを行った後、スクライブ領域を切断することで、半導体基板を個片化する工程と、を有することを特徴とする半導体装置の製造方法である。 According to a third aspect of the present invention, there is provided a semiconductor substrate including a circuit region having an integrated circuit and a scribe region, a test pad disposed in the scribe region, and electrical connection for electrically connecting the test pad and the integrated circuit. A step of bringing the probe into contact with an inspection pad of a semiconductor wafer having a portion and a diffusion layer formed on a semiconductor substrate that constitutes a part of the conductive portion, and performing an operation test of the integrated circuit by applying a signal to the probe A method for manufacturing a semiconductor device comprising: a step of performing, and a step of separating a semiconductor substrate by cutting a scribe region after performing an operation test.
　本発明によれば、回路領域からスクライブ領域に配線を引き出して、スクライブ領域にプロービングして回路領域に導通する半導体装置技術において、製造歩留まりを向上させることができる。 According to the present invention, it is possible to improve the manufacturing yield in the semiconductor device technology in which wiring is drawn from the circuit region to the scribe region, probing the scribe region, and conducting to the circuit region.
第１の実施形態に係る半導体ウェハ２００を示す平面図および拡大図である。It is the top view and enlarged view which show the semiconductor wafer 200 concerning 1st Embodiment. 半導体ウェハ２００を構成する回路領域１００の拡大図である。FIG. 3 is an enlarged view of a circuit region 100 constituting a semiconductor wafer 200. 図２のガードリング２０６付近を示す断面図である。FIG. 3 is a cross-sectional view showing the vicinity of a guard ring 206 in FIG. 2. 図２の各領域１０２，２０３の境界付近を示す断面図である。FIG. 3 is a cross-sectional view showing the vicinity of a boundary between regions 102 and 203 in FIG. 2. 図２の導電部２０４付近の拡大図である。FIG. 3 is an enlarged view near a conductive portion 204 in FIG. 2. 図５のＡ－Ａ’断面図である。FIG. 6 is a cross-sectional view taken along the line A-A ′ of FIG. 5. 拡散領域の断面図である。It is sectional drawing of a diffusion area | region. 導電部２０４の断面図である。3 is a cross-sectional view of a conductive part 204. FIG. 導電部２０４の配線を示す回路図である。6 is a circuit diagram showing wiring of a conductive portion 204. FIG. 第２の実施形態に係る半導体ウェハ２００ａを構成する半導体チップ１００ａの回路図である。It is a circuit diagram of the semiconductor chip 100a which comprises the semiconductor wafer 200a which concerns on 2nd Embodiment. 自動接続パッド２５１の形状を示す図である。It is a figure which shows the shape of the automatic connection pad 251. FIG. 第３の実施形態に係る半導体ウェハ２００ｂを構成する半導体チップ１００の平面図であって、隣接する２つの半導体チップ１００のみを図示している。It is a top view of the semiconductor chip 100 which comprises the semiconductor wafer 200b which concerns on 3rd Embodiment, Comprising: Only two adjacent semiconductor chips 100 are shown in figure. 第４の実施形態に係る半導体ウェハ２００ｃを構成する半導体チップ１００の平面図であって、隣接する２つの半導体チップ１００のみを図示している。It is a top view of the semiconductor chip 100 which comprises the semiconductor wafer 200c which concerns on 4th Embodiment, Comprising: Only two adjacent semiconductor chips 100 are shown in figure. 第５の実施形態に係る半導体ウェハ２００ｄを構成するＮＭＯＳトランジスタ３００ｄの断面図である。It is sectional drawing of NMOS transistor 300d which comprises the semiconductor wafer 200d which concerns on 5th Embodiment.
　以下、図面に基づいて本発明に好適な実施形態を詳細に説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
　まず、図１～図３を参照して、本発明の第１の実施形態に係る半導体ウェハ２００の概略構成について説明する。図１は半導体ウェハ２００の全体平面図、図２は半導体ウェハ２００が備える回路領域１００周辺の平面図、図３はガードリング２０６の構造を示す要部断面図である。 First, a schematic configuration of a semiconductor wafer 200 according to the first embodiment of the present invention will be described with reference to FIGS. 1 is an overall plan view of the semiconductor wafer 200, FIG. 2 is a plan view of the periphery of the circuit region 100 included in the semiconductor wafer 200, and FIG.
　半導体ウェハ２００は、円板状の半導体基板２０１を有する。半導体基板２０１には、所望の集積回路が形成された複数の同様の回路領域１００が、行列状に並んで配置されている。図１では、格子状に形成された線で構成される矩形の１つ１つが回路領域１００に該当する。回路領域１００に備えられた集積回路は所定のものに限定されないが、例えば、ＤＲＡＭ（Dynamic Random Access Memory）やロジック回路などで良い。 The semiconductor wafer 200 has a disk-shaped semiconductor substrate 201. On the semiconductor substrate 201, a plurality of similar circuit regions 100 in which a desired integrated circuit is formed are arranged in a matrix. In FIG. 1, each of rectangles formed by lines formed in a lattice shape corresponds to the circuit region 100. The integrated circuit provided in the circuit area 100 is not limited to a predetermined one, but may be a DRAM (Dynamic Random Access Memory) or a logic circuit, for example.
　図１中で格子状に形成された線は、隣り合って配置する回路領域１００同士を離間する領域であって、回路領域１００を分離して個片化する際に切断されるスクライブ領域２０３である。個片化された回路領域１００は、それぞれが半導体チップとなる。 The lines formed in a lattice shape in FIG. 1 are regions that separate circuit regions 100 arranged adjacent to each other, and are scribe regions 203 that are cut when the circuit regions 100 are separated and separated into individual pieces. is there. Each of the separated circuit regions 100 is a semiconductor chip.
　さらに、半導体ウェハ２００は、図２に示すように、回路領域１００において保護すべき内部回路を備えた内部回路領域１０２から、スクライブ領域２０３に引き出された導通部２０４を有する。また、回路領域１００の内部回路領域１０２の外周に設けられ、内部回路領域１０２を保護するガードリング２０６を有する。導通部２０４、および、ガードリング２０６の構成については、後に詳しく説明する。 Further, as shown in FIG. 2, the semiconductor wafer 200 has a conductive portion 204 drawn out from the internal circuit region 102 having the internal circuit to be protected in the circuit region 100 to the scribe region 203. Further, a guard ring 206 is provided on the outer periphery of the internal circuit region 102 in the circuit region 100 to protect the internal circuit region 102. The configurations of the conductive portion 204 and the guard ring 206 will be described in detail later.
　スクライブ領域２０３は、半導体ウェハ２００から回路領域１００を個片化して半導体チップを得る際に、切削されて消失する箇所である。言い換えれば、スクライブ領域２０３は、半導体ウェハ２００から回路領域１００を切り離すためのブレードが通る個所であり、これにより砕けて消失する。図１の矢印はチップを個片化するためのブレードの経路を示すが、ブレード進行方向は、図１のように列ごとに反転させるものに限定されない。スクライブ領域２０３の幅は数十μｍから数百μｍの幅があり、製造工程中で使用する各種プロセスモニターの他、完成ウェハの素子特性を測定するプローブ検査用の素子とそのための針当てパッド（プロービングパッド）等を搭載する場合が多い。本実施形態の半導体ウェハ２００では、針当てパッドである検査用パッド２０５がスクライブ領域２０３に設けられ、導通部２０４を介して回路領域１００内のチップ内パッド２０７と接続されている。チップ内パッド２０７は、針当てしないボンディング専用パッドである。検査用パッド２０５およびチップ内パッド２０７は、外部からのプロービングまたはボンディングに付すため、最上層に配置されている必要があり、かつ、各パッド２０５，２０７上面の保護膜は一部除去され、露出した状態となっている。 The scribe region 203 is a portion that is cut and disappears when the semiconductor region is separated from the semiconductor wafer 200 to obtain a semiconductor chip. In other words, the scribe region 203 is a portion through which a blade for separating the circuit region 100 from the semiconductor wafer 200 passes, and is thereby crushed and disappears. The arrows in FIG. 1 indicate the path of the blade for separating the chips into pieces, but the blade traveling direction is not limited to that reversed for each row as in FIG. The scribe region 203 has a width of several tens to several hundreds of μm. In addition to various process monitors used in the manufacturing process, a probe inspection element for measuring element characteristics of a completed wafer and a needle pad for the element ( Probing pads) are often installed. In the semiconductor wafer 200 of the present embodiment, a test pad 205 that is a needle pad is provided in the scribe region 203 and is connected to the in-chip pad 207 in the circuit region 100 via the conduction portion 204. The in-chip pad 207 is a bonding-dedicated pad that is not needle-contacted. The inspection pad 205 and the in-chip pad 207 need to be disposed on the uppermost layer in order to be subjected to external probing or bonding, and a part of the protective film on the upper surface of each pad 205, 207 is removed and exposed. It has become a state.
　図３に示すように、ガードリング２０６は、半導体基板２０１の主面（例えば、半導体基板２０１に形成された拡散領域の表面）から、その上層に形成される多層配線が用いられる。本実施形態では多層配線を構成する部材として、基板面に近い側から順に、コンタクトプラグ１０３、第１の配線１０４、第１のビアプラグ１０５、第１の金属配線１０６、第２のビアプラグ１０７、第２の金属配線１０８、第３のビアプラグ１０９、および、第３の金属配線１１０によって構成される例を示す。これらの多層配線は層間絶縁膜１１１によって互いに絶縁されるとともに、保護されている。コンタクトプラグ１０３および第１の配線１０４の材料は、例えば、タングステンや導電性ポリシリコン（多結晶シリコン）などを適用できる。第１～第３のビアプラグ１０５，１０７，１０９、および、第１～第３の金属配線１０６，１０８，１１０の材料は、例えば、アルミニウムや銅などを適用できる。層間絶縁膜１１１の材料は、例えば、酸化シリコンや窒化シリコンなどを適用できる。なお、上述の検査用パッド２０５やチップ内パッド２０６は、第３の金属配線１１０と同層に同材料で形成されていても良い。 As shown in FIG. 3, the guard ring 206 uses a multilayer wiring formed on the main surface of the semiconductor substrate 201 (for example, the surface of a diffusion region formed in the semiconductor substrate 201). In this embodiment, as members constituting the multilayer wiring, the contact plug 103, the first wiring 104, the first via plug 105, the first metal wiring 106, the second via plug 107, and the first are sequentially arranged from the side close to the substrate surface. An example constituted by two metal wirings 108, a third via plug 109, and a third metal wiring 110 is shown. These multilayer wirings are insulated from each other and protected by the interlayer insulating film 111. As a material for the contact plug 103 and the first wiring 104, for example, tungsten, conductive polysilicon (polycrystalline silicon), or the like can be used. As materials for the first to third via plugs 105, 107, 109 and the first to third metal wirings 106, 108, 110, for example, aluminum or copper can be applied. For example, silicon oxide, silicon nitride, or the like can be used as the material of the interlayer insulating film 111. Note that the above-described inspection pads 205 and in-chip pads 206 may be formed of the same material in the same layer as the third metal wiring 110.
　上述の多層配線を、内部回路領域１０２の周囲を囲うように配置して、本実施形態のガードリング２０６を構成する。このようなガードリング２０６を配置することで、回路領域１００を個片化して半導体チップを得るための切断の際、内部回路領域１０２を外部の汚染要因から保護できる。また、個片化後の機械強度を強化できる。図２および図３ではガードリング２０６が２重となっているが、１重でも３重以上としても良い。１重であれば回路領域１００の占有面積を縮小でき、一方、多重にするほど性能が強化される。 The above-described multilayer wiring is arranged so as to surround the inner circuit region 102 to constitute the guard ring 206 of the present embodiment. By disposing such a guard ring 206, the internal circuit region 102 can be protected from external contamination factors when cutting to obtain a semiconductor chip by dividing the circuit region 100 into individual pieces. Moreover, the mechanical strength after singulation can be strengthened. 2 and 3, the guard ring 206 is double, but it may be single or triple. If it is a single layer, the area occupied by the circuit region 100 can be reduced.
　導通部２０４は、回路領域１００内の内部回路領域１０２と、スクライブ領域２０３の検査用パッド２０５とを接続するための導電部である。本実施形態の導通部２０４は、図４に示すように、スクライブ領域２０３から、ガードリング２０６が配置された領域を通り、内部回路領域１０２に達する部分として、半導体基板２０１に形成された拡散層２１１を有している。ここで、拡散層（拡散領域、活性領域とも言う）とは、基板主面に形成された導電性の高い半導体領域であって、同じく基板主面に形成された溝型分離部（ＳＴＩ：Shallow Trench Isolation）などによって基板主面に区画された領域である。以後、拡散層については同様であるとして説明を省略する。本実施形態では、上述のような拡散層２１１により、ガードリング領域２０３の検査用パッド２０５と、内部回路領域１０２とを、上層配線を用いずに電気的に導通できる。なお、検査用パッド２０５と拡散層２１１とは、スクライブ領域側多層配線２１５を介して、ガードリング領域２０３内で接続される。また、内部回路領域１０２に属する被試験素子と拡散層２１１とは、内部回路側多層配線２１３を介して、内部回路領域１０２内で接続される。ここで、拡散層２１１はシリコンがドナー不純物を含んだＮ型導電型である例を示すが、シリコンがアクセプタ不純物を含んだＰ型導電型であっても良い。そして、不純物量を調整することで、導通部２０４の導電性を調整できる。 The conductive portion 204 is a conductive portion for connecting the internal circuit region 102 in the circuit region 100 and the inspection pad 205 in the scribe region 203. As shown in FIG. 4, the conductive portion 204 of the present embodiment is a diffusion layer formed in the semiconductor substrate 201 as a portion that reaches the internal circuit region 102 from the scribe region 203 through the region where the guard ring 206 is disposed. 211. Here, a diffusion layer (also referred to as a diffusion region or an active region) is a highly conductive semiconductor region formed on the main surface of the substrate, and is a groove type isolation portion (STI: Shallow) also formed on the main surface of the substrate. Trench (Isolation) etc. is a region partitioned on the main surface of the substrate. Hereinafter, the description of the diffusion layer is omitted because it is the same. In the present embodiment, the diffusion pad 211 as described above can electrically connect the inspection pad 205 in the guard ring region 203 and the internal circuit region 102 without using the upper layer wiring. The inspection pad 205 and the diffusion layer 211 are connected in the guard ring region 203 via the scribe region side multilayer wiring 215. Further, the device under test belonging to the internal circuit region 102 and the diffusion layer 211 are connected in the internal circuit region 102 via the internal circuit side multilayer wiring 213. Here, the diffusion layer 211 shows an example in which silicon is an N-type conductivity type including a donor impurity, but silicon may be a P-type conductivity type including an acceptor impurity. Then, the conductivity of the conductive portion 204 can be adjusted by adjusting the amount of impurities.
　このように、本実施形態では、内部回路領域１０２からスクライブ領域２０３に引き出す導通部２０４として、半導体基板２０１に形成した拡散層２１１を適用したことにより、回路領域１００を個片化して半導体チップを得る際に、金属配線が端部に露出することが無い。従って、配線材料と層間絶縁膜材料の界面などから侵入する水分や汚染要因の懸念が低減される。また、切断の際に生じる配線の切削屑等の付着により、配線と他の導通部（例えば拡散層など）との間で生じるショート不良の懸念が低減される。結果として、半導体装置の製造歩留まりが向上する。 As described above, in this embodiment, the diffusion layer 211 formed on the semiconductor substrate 201 is applied as the conductive portion 204 that is drawn from the internal circuit region 102 to the scribe region 203, whereby the circuit region 100 is separated into individual pieces. When obtained, the metal wiring is not exposed to the end. Therefore, the concern of moisture and contamination factors entering from the interface between the wiring material and the interlayer insulating film material is reduced. In addition, due to the attachment of cutting scraps or the like of the wiring generated at the time of cutting, the concern about short-circuit defects that occur between the wiring and other conductive parts (for example, a diffusion layer) is reduced. As a result, the manufacturing yield of the semiconductor device is improved.
　次に、図５～図８を参照して、本実施形態の導通部２０４のより好ましい構成について、より詳細に説明する。 Next, with reference to FIGS. 5 to 8, a more preferable configuration of the conduction unit 204 of the present embodiment will be described in more detail.
　図５は、半導体基板２０１の表面準位を見た平面図であり、導通部２０４のうちの拡散層２１１周辺を示している。図６は、図５のＡ－Ａ’線に沿って見た断面図である。本実施形態の導通部２０４は、ガードリング領域２０３から内部回路領域１０２にわたって半導体基板２０１の表面に形成された拡散層２１１を有している。拡散層２１１はその両端のうち、内部回路領域１０２において、多層配線からなる内部回路側多層配線２１３と接続され、スクライブ領域２０３において多層配線からなるスクライブ領域側多層配線２１５と接続されている。 FIG. 5 is a plan view of the surface level of the semiconductor substrate 201 and shows the periphery of the diffusion layer 211 in the conductive portion 204. FIG. 6 is a cross-sectional view taken along line A-A ′ of FIG. The conduction part 204 of the present embodiment has a diffusion layer 211 formed on the surface of the semiconductor substrate 201 from the guard ring region 203 to the internal circuit region 102. The diffusion layer 211 is connected to the internal circuit side multilayer wiring 213 made of multilayer wiring in the internal circuit region 102 at both ends thereof, and is connected to the scribe region side multilayer wiring 215 made of multilayer wiring in the scribe region 203.
　半導体基板２０１に導通部２０４の一部としての拡散層２１１が形成されている個所においては、ガードリング２０６の最下層であるコンタクトプラグ１０３を用いた層は省かれ、この個所で拡散層２１１とガードリング２０６とが接触しないようになっている。また、拡散層２１１内には、拡散層２１１を横断するように配置されたゲート電極２１７を有するＭＯＳトランジスタ（プレーナ型電界効果トランジスタ）３００が配置されていても良い。ＭＯＳトランジスタの断面図を図７に示す。ＭＯＳトランジスタ３００のオン／オフを切り替えることで、拡散層２１１の接続と分離を切り替えることができる。即ち、ＭＯＳトランジスタ３００をスイッチとして、内部回路領域１０２とスクライブ領域２０３の検査用パッド２０５との、拡散層２１１を介した接続状態を切り替えることができる。具体的な動作方法と構成については、後に図８および図９を用いて説明する。 In the portion where the diffusion layer 211 as a part of the conductive portion 204 is formed on the semiconductor substrate 201, the layer using the contact plug 103 which is the lowermost layer of the guard ring 206 is omitted. The guard ring 206 is prevented from contacting. Further, in the diffusion layer 211, a MOS transistor (planar field effect transistor) 300 having a gate electrode 217 disposed so as to cross the diffusion layer 211 may be disposed. A cross-sectional view of the MOS transistor is shown in FIG. By switching on / off the MOS transistor 300, connection and separation of the diffusion layer 211 can be switched. That is, the connection state of the internal circuit region 102 and the inspection pad 205 in the scribe region 203 via the diffusion layer 211 can be switched using the MOS transistor 300 as a switch. A specific operation method and configuration will be described later with reference to FIGS.
　導通部２０４のより好ましい構成として、拡散層２１１は、内部にＳＴＩ形状の分離部からなるクラックストッパ２３１を有していても良い。拡散層２１１はクラックストッパ２３１で分断されず、クラックストッパ２３１を迂回して形成されている。言い換えれば、拡散層２１１は内部に分離部からなるクラックストッパ２３１を有しているが、これを囲む様に迂回することで、内部回路側多層配線２１３～ＭＯＳトランジスタ３００～（クラックストッパ２３１）～拡散層２１１～（スクライブ領域２０３）～スクライブ領域側多層配線２１５へと電気的接続経路を形成している。 As a more preferable configuration of the conduction part 204, the diffusion layer 211 may have a crack stopper 231 formed of an STI-shaped separation part inside. The diffusion layer 211 is not divided by the crack stopper 231 and is formed around the crack stopper 231. In other words, the diffusion layer 211 has a crack stopper 231 composed of a separation portion inside, but by detouring to surround the diffusion stopper 211, the internal circuit side multilayer wiring 213, the MOS transistor 300, (the crack stopper 231), Electrical connection paths are formed from the diffusion layers 211 to (scribe region 203) to the scribe region-side multilayer wiring 215.
　このような構造とする理由について、説明する。半導体ウェハ２００から回路領域１００を個片化する際、拡散層２１１が横切る箇所のＳＴＩ形状が分断される際に、素材の強度が異なることが原因でクラックやチッピングが発生する可能性がある。そのため、拡散層２１１内にＳＴＩ構造を有するクラックストッパ２３１を配置することにより、回路領域１００の個片化の際にクラックが入ることを予防しつつ、スクライブ領域２０３のスクライブ領域側多層配線２１５への接続を果たしている。なお、ＳＴＩの溝がチップ内に向かって直線で延びている構造では、ガードリング２０６内でクラックが停止しない可能性が高くなるので、図５ではＳＴＩ溝が直線化しない構造にしてある。 The reason for this structure will be explained. When the circuit region 100 is separated from the semiconductor wafer 200, cracks and chipping may occur due to the difference in the strength of the material when the STI shape where the diffusion layer 211 crosses is divided. Therefore, by disposing a crack stopper 231 having an STI structure in the diffusion layer 211, the scribe region-side multilayer wiring 215 of the scribe region 203 is prevented while preventing cracks from occurring when the circuit region 100 is separated. Plays the connection. In the structure in which the STI groove extends linearly toward the inside of the chip, there is a high possibility that cracks will not stop in the guard ring 206, so the STI groove is not straightened in FIG.
　図８に示すように、拡散層２１１は半導体基板２０１（ここではＰ型導電型）上に形成されたＭＯＳトランジスタ３００のドレインおよびソース領域を構成しており、ゲート電極２１７が間に設けられている。ゲート電極２１７はスクライブ領域２０３に設けられた評価用パッド２１９に評価用拡散層２２１を介して接続されている。なお、図９に示すように、ゲート電極２１７用の配線は複数の拡散層２１１（および検査用パッド２０５）に共通して接続されている。この構造では、半導体ウェハ２００から回路領域１００を個片化する前の針当て試験などのモニター時のみ、評価用パッド２１９を介してゲート電極２１７に電流を流すことにより、ＭＯＳトランジスタ３００に電流が流れる（即ち、導通部２０４が導通状態となる）。一方、半導体ウェハ２００から回路領域１００を個片化した後は、ゲート電極２１７用の配線が消滅するため、ＭＯＳトランジスタ３００に電流が流れない（即ち、導通部２０４が非導通状態となる）。このように、拡散層２１１がスイッチ回路を内蔵することで、導通部２０４（拡散層２１１）を介した電流のリークを防ぐことができる。 As shown in FIG. 8, the diffusion layer 211 constitutes the drain and source regions of the MOS transistor 300 formed on the semiconductor substrate 201 (here, P-type conductivity type), and the gate electrode 217 is provided therebetween. Yes. The gate electrode 217 is connected to an evaluation pad 219 provided in the scribe region 203 via an evaluation diffusion layer 221. As shown in FIG. 9, the wiring for the gate electrode 217 is commonly connected to the plurality of diffusion layers 211 (and the inspection pad 205). In this structure, a current is supplied to the MOS transistor 300 by flowing a current to the gate electrode 217 via the evaluation pad 219 only during monitoring such as a needle contact test before the circuit region 100 is separated from the semiconductor wafer 200. It flows (that is, the conducting part 204 becomes conductive). On the other hand, after the circuit region 100 is separated from the semiconductor wafer 200, the wiring for the gate electrode 217 disappears, so that no current flows through the MOS transistor 300 (that is, the conducting portion 204 is turned off). In this manner, since the diffusion layer 211 has a built-in switch circuit, it is possible to prevent current leakage through the conduction portion 204 (diffusion layer 211).
　より詳細に説明すると、半導体ウェハ２００から回路領域１００が個片化されていない状態では、回路領域１００とスクライブ領域２０３が繋がった状態で半導体ウェハ２００を構成している。半導体チップ１００内には針当てしないボンディング専用パッドであるチップ内パッド２０７があり、スクライブ領域２０３にはプローブ専用パッドである検査用パッド２０５が設けられている。なお、テスト時に電源を共用化するチップ内のＶＳＳ端子はボンディングと針当て兼用である。プローブテストを行う場合、スイッチ（ＭＯＳトランジスタ３００）をＯＮにする必要があり、ＶＳＳ端子とモニターＥＮ端子間にスイッチ回路であるＭＯＳトランジスタ３００がＯＮする電圧を印加する。ＭＯＳトランジスタ３００がＯＮ状態となると、検査用パッド２０５とチップ内パッド２０７が導通し、検査用パッド２０５を使った検査が実施できる。 More specifically, when the circuit region 100 is not separated from the semiconductor wafer 200, the semiconductor wafer 200 is configured with the circuit region 100 and the scribe region 203 connected to each other. In the semiconductor chip 100, there is an in-chip pad 207 which is a bonding dedicated pad which is not touched by a needle, and a scribe area 203 is provided with an inspection pad 205 which is a probe dedicated pad. Note that the VSS terminal in the chip that shares the power supply during the test is used for both bonding and needle contact. When performing a probe test, it is necessary to turn on the switch (MOS transistor 300), and a voltage for turning on the MOS transistor 300 as a switch circuit is applied between the VSS terminal and the monitor EN terminal. When the MOS transistor 300 is turned on, the inspection pad 205 and the in-chip pad 207 are brought into conduction, and the inspection using the inspection pad 205 can be performed.
　一方、半導体ウェハ２００から回路領域１００が個片化された状態では、検査用パッド２０５はスクライビングにより消滅する。モニターＥＮ端子のノードはチップ内部のＶＳＳにプルダウンされているので、無接続状態となり、ＭＯＳトランジスタ３００はＯＦＦになる。この状態では、拡散層２１１の断面の電位は基板と同一であるため、外部で基板とショートしたとしても拡散層２１１に電流は流れない。他の端子断面はＭＯＳトランジスタ３００でＯＦＦしているため、同様に基板や他の拡散断面間でもリーク電流を流さない。 On the other hand, when the circuit region 100 is separated from the semiconductor wafer 200, the inspection pad 205 disappears by scribing. Since the node of the monitor EN terminal is pulled down to VSS in the chip, the node is not connected and the MOS transistor 300 is turned off. In this state, since the potential of the cross section of the diffusion layer 211 is the same as that of the substrate, no current flows through the diffusion layer 211 even if the substrate is short-circuited externally. Since the other terminal cross sections are turned off by the MOS transistor 300, similarly, no leakage current flows between the substrate and other diffusion cross sections.
　次に、第２の実施形態について、図１０を参照して説明する。 Next, a second embodiment will be described with reference to FIG.
　第２の実施形態は、第１の実施形態において、スクライブ領域２０３に評価用のバッファを設けたものである。 In the second embodiment, an evaluation buffer is provided in the scribe area 203 in the first embodiment.
　なお、第２の実施形態において、第１の実施形態と同様の機能を果たす要素については同一の番号を付し、主に第１の実施形態と異なる部分について説明する。 In the second embodiment, elements that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.
　前述のように、半導体ウェハ２００は導通部２０４が拡散層２１１を有しているが、拡散層２１１は多層配線の金属配線等に比較して電気抵抗が高い。そのため、拡散層２１１を介した出力信号をモニターする場合、図１０（ａ）に示すような構造では、拡散層２１１の抵抗値が影響して、出力信号を正しく測定できない可能性がある。 As described above, in the semiconductor wafer 200, the conductive portion 204 has the diffusion layer 211, but the diffusion layer 211 has a higher electrical resistance than a metal wiring or the like of a multilayer wiring. Therefore, when the output signal via the diffusion layer 211 is monitored, there is a possibility that the output signal cannot be measured correctly in the structure as shown in FIG. 10A due to the resistance value of the diffusion layer 211.
　そこで、第２の実施形態に係る半導体ウェハ２００ａでは、図１０（ｂ）に示すように、スクライブ領域２０３に評価用のバッファ２４１を設けている。なお、拡散層２１１が出力専用パッド２４３に接続されている場合であれば、図１０（ｂ）に示すように、外部バッファ直結で良いが、入出力の両方に用いられる入出力パッド２４５に接続されている場合、外部バッファが評価パッドに繋がったままでは、この端子からチップへの入力信号を与えることができない。これは、出力動作と入力動作が外部から明確に分らなければ、出力バッファと入力信号を正確に切り替えて動作させることができないためである。 Therefore, in the semiconductor wafer 200a according to the second embodiment, an evaluation buffer 241 is provided in the scribe area 203 as shown in FIG. In the case where the diffusion layer 211 is connected to the output dedicated pad 243, as shown in FIG. 10B, the external buffer may be directly connected, but it is connected to the input / output pad 245 used for both input and output. If the external buffer is connected to the evaluation pad, an input signal from this terminal to the chip cannot be applied. This is because the output buffer and the input signal cannot be switched accurately and operated unless the output operation and the input operation are clearly understood from the outside.
　そこで、拡散層２１１が入出力パッド２４５に接続されている場合は、図１０（ｃ）、図１０（ｄ）に示すような構成とするのが望ましい。具体的には、図１０（ｃ）では回路領域１００ａ内部の出力バッファのＯＵＴＰＵＴＥＮ信号をスクライブ領域２０３の入出力バッファ制御に割り当てる構成としている。この場合、スクライブ領域２０３内に入出力を切り替える切替回路２４７を設けている。 Therefore, when the diffusion layer 211 is connected to the input / output pad 245, it is desirable to have a configuration as shown in FIGS. 10 (c) and 10 (d). Specifically, in FIG. 10C, the OUTPUT signal in the output buffer in the circuit area 100 a is assigned to the input / output buffer control in the scribe area 203. In this case, a switching circuit 247 for switching input / output is provided in the scribe area 203.
　一方、図１０（ｄ）では、自動接続パッド２５１を用いている。図１１（ａ）に示すように、自動接続パッド２５１はチップ内の入出力パッドが、ワイヤボンディング前に入力パッド２５１ａと出力パッド２５１ｂに分離した構造を有しており、それぞれが入力用導通部２２１ａと、バッファ回路２４１を有する出力用導通部２２１ｂに接続されている。入力パッド２５１ａと出力パッド２５１ｂは互いに隣接して設けられており（パッドにスリットを設けて分離した構造を有しており）、入力パッド２５１ａと出力パッド２５１ｂを接続するようにワイヤボンディング２５２を行うことによって、入力パッド２５１ａと出力パッド２５１ｂが接続される構造となっている。自動接続パッド２５１を用いることで、スクライブ領域２０３に配置した出力バッファ（バッファ回路２４１）は、チップ内のＯＵＴ端子に接続すれば良く、また入力端子は独立してスクライブ領域２０３に配置すれば良い。 On the other hand, in FIG. 10D, the automatic connection pad 251 is used. As shown in FIG. 11A, the automatic connection pad 251 has a structure in which input / output pads in the chip are separated into an input pad 251a and an output pad 251b before wire bonding, and each of them is an input conduction portion. 221a and an output conducting portion 221b having a buffer circuit 241. The input pad 251a and the output pad 251b are provided adjacent to each other (having a structure in which the pads are separated by providing slits), and wire bonding 252 is performed so as to connect the input pad 251a and the output pad 251b. Thus, the input pad 251a and the output pad 251b are connected. By using the automatic connection pad 251, the output buffer (buffer circuit 241) disposed in the scribe area 203 may be connected to the OUT terminal in the chip, and the input terminal may be independently disposed in the scribe area 203. .
　なお、自動接続パッド２５１の平面形状は、ワイヤボンディング前は入力パッド２５１ａと出力パッド２５１ｂが互いに電気的に分離された構造で、ワイヤボンディング後に互いに接続された構造であれば特に限定されるものではない。ここでは自動接続パッド２５１の例として図１１（ｂ）に示す、長方形、図１１（ｃ）に示す凸凹型、図１１（ｄ）に示す、斜め型を例示するが、これ以外の形状でも良い。 The planar shape of the automatic connection pad 251 is not particularly limited as long as the input pad 251a and the output pad 251b are electrically separated from each other before wire bonding and are connected to each other after wire bonding. Absent. Here, as an example of the automatic connection pad 251, a rectangle illustrated in FIG. 11B, a concavo-convex shape illustrated in FIG. 11C, and an oblique shape illustrated in FIG. 11D are illustrated, but other shapes may be used. .
　このように、第２の実施形態によれば、半導体ウェハ２００ａは、回路領域１００ａの内部回路領域１０２からスクライブ領域２０３に引き出された導通部２０４と、回路領域１００ａの内部回路領域１０２の外周に設けられたガードリング２０６とを有し、導通部２０４は、ガードリング２０６が配置された領域を通過して内部回路領域１０２からスクライブ領域２０３に至る部分として、半導体基板の主面に形成された拡散層２１１を有している。従って第１の実施形態と同様の効果を奏する。 As described above, according to the second embodiment, the semiconductor wafer 200a is formed on the outer periphery of the conductive portion 204 drawn from the internal circuit region 102 of the circuit region 100a to the scribe region 203 and the internal circuit region 102 of the circuit region 100a. The conductive portion 204 is formed on the main surface of the semiconductor substrate as a portion extending from the internal circuit region 102 to the scribe region 203 through the region where the guard ring 206 is disposed. A diffusion layer 211 is provided. Therefore, the same effects as those of the first embodiment are obtained.
　また、第２の実施形態によれば、半導体ウェハ２００ａは、スクライブ領域２０３に評価用のバッファが設けられている。そのため、拡散層２１１の抵抗値の影響によらず、出力信号をモニターできる。 Further, according to the second embodiment, the semiconductor wafer 200 a is provided with an evaluation buffer in the scribe region 203. Therefore, the output signal can be monitored regardless of the influence of the resistance value of the diffusion layer 211.
　次に、第３の実施形態について図１２を参照して説明する。 Next, a third embodiment will be described with reference to FIG.
　第３の実施形態は、図１２に示すように、複数の回路領域１００間で検査用パッド２０５を共有し、それぞれが拡散層２１１を経てセンターパッド２７１に接続する。なお、第３の実施形態において、第１の実施形態と同様の機能を果たす要素については同一の番号を付し、主に第１の実施形態と異なる部分について説明する。 In the third embodiment, as shown in FIG. 12, the test pads 205 are shared among a plurality of circuit regions 100, and each is connected to the center pad 271 via the diffusion layer 211. Note that in the third embodiment, elements that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.
　第３の実施形態に係る半導体ウェハ２００ｂは、上記の構成により、ウェハ状態では、異なる回路領域１００間で電気的に接続されたセンターパッド２７１を有し、信号を共有できる。例えば、パラテストが可能となる。そして、各回路領域１００のガードリング２０６を跨ぐ部分の導通部２０４には、上記第１の実施形態と同様の拡散層２１１を適用している。一方、スクライブによる個片化後は、異なる回路領域１００間のセンターパッド２７１は切断される。なお、図１２では２個の半導体チップ１００のみを図示しているが、接続可能な半導体チップ１００の数は２つには限定されない。スクライブ領域２０３で見て、スクライビングブレードが通る幅の内側に導通部２０４の金属配線部２０８が収まるように、拡散層２１１の長さを設定することが、より好ましい。これにより、スクライブ後に金属配線部２０８が外部に露出することが無い。 The semiconductor wafer 200b according to the third embodiment has a center pad 271 that is electrically connected between different circuit regions 100 in the wafer state, and can share signals in the wafer state. For example, paratests are possible. And the diffusion layer 211 similar to the said 1st Embodiment is applied to the conduction | electrical_connection part 204 of the part straddling the guard ring 206 of each circuit area | region 100. FIG. On the other hand, after separation by scribing, the center pads 271 between different circuit regions 100 are cut. In FIG. 12, only two semiconductor chips 100 are illustrated, but the number of connectable semiconductor chips 100 is not limited to two. It is more preferable to set the length of the diffusion layer 211 so that the metal wiring portion 208 of the conducting portion 204 is accommodated inside the width through which the scribing blade passes when viewed in the scribe region 203. Thereby, the metal wiring part 208 is not exposed to the outside after scribing.
　このように、第３の実施形態によれば、半導体ウェハ２００ｂは、回路領域１００の内部回路領域１０２からスクライブ領域２０３に引き出された導通部２０４と、回路領域１００の内部回路領域１０２の外周に設けられたガードリング２０６とを有し、導通部２０４は、ガードリング２０６が配置された領域を通過して内部回路領域１０２からスクライブ領域２０３に至る部分として、半導体基板の主面に形成された拡散層２１１を有している。従って、第１の実施形態と同様の効果を奏する。 Thus, according to the third embodiment, the semiconductor wafer 200 b is formed on the outer periphery of the internal circuit region 102 in the circuit region 100 and the conductive portion 204 drawn from the internal circuit region 102 in the circuit region 100 to the scribe region 203. The conductive portion 204 is formed on the main surface of the semiconductor substrate as a portion extending from the internal circuit region 102 to the scribe region 203 through the region where the guard ring 206 is disposed. A diffusion layer 211 is provided. Accordingly, the same effects as those of the first embodiment are obtained.
　また、第３の実施形態によれば、半導体ウェハ２００ｂは、複数の回路領域１００間で検査用パッド２０５を共有し、それぞれが拡散層２１１を経由してセンターパッド２７１に接続する。そのため、異なる回路領域１００で信号を共有させることができ、パラテストが可能となる。 Further, according to the third embodiment, the semiconductor wafer 200 b shares the inspection pad 205 among the plurality of circuit regions 100, and each is connected to the center pad 271 via the diffusion layer 211. Therefore, signals can be shared by different circuit regions 100, and paratests are possible.
　次に、第４の実施形態について図１３を参照して説明する。 Next, a fourth embodiment will be described with reference to FIG.
　第４の実施形態は、図１３に示すように、第３の実施形態におけるスクライブ領域２０３の検査用パッドを設けず、スクライブ領域２０３においては金属配線部２０８で結線した構造としたものである。なお、第４の実施形態において、第３の実施形態と同様の機能を果たす要素については同一の番号を付し、主に第３の実施形態と異なる部分について説明する。 In the fourth embodiment, as shown in FIG. 13, the inspection pad of the scribe area 203 in the third embodiment is not provided, and the scribe area 203 is connected by a metal wiring portion 208. Note that in the fourth embodiment, elements that perform the same functions as those in the third embodiment are denoted by the same reference numerals, and different portions from the third embodiment will be mainly described.
　図１３に示すように、第４の実施形態に係る半導体ウェハ２００ｃはスクライブ領域２０３にパッドが設けられておらず、スクライブ領域２０３においては金属配線部２０８で直接結線した構造となっている。このような構造とすることにより、上記第３の実施形態と同様の効果が得られ、かつ、スクライブ領域２０３に配置する針当てパッド数を減らすことができる。結果として、パラテストが可能な複数の回路領域１００の数を増加させることが可能となる。 As shown in FIG. 13, the semiconductor wafer 200c according to the fourth embodiment has no pad provided in the scribe region 203, and the scribe region 203 has a structure in which the metal wiring part 208 is directly connected. By adopting such a structure, the same effects as those of the third embodiment can be obtained, and the number of needle pad pads arranged in the scribe region 203 can be reduced. As a result, it is possible to increase the number of the plurality of circuit regions 100 that can perform the paratest.
　次に、第５の実施形態について、図１４を参照して説明する。 Next, a fifth embodiment will be described with reference to FIG.
　第５の実施形態は、第１の実施形態において、拡散層２１１として、Ｎ型拡散層ではなく、Ｐ型拡散層を用いたものである。なお、第５の実施形態において、第１の実施形態と同様の機能を果たす要素については同一の番号を付し、主に第１の実施形態と異なる部分について説明する。 The fifth embodiment uses a P-type diffusion layer instead of an N-type diffusion layer as the diffusion layer 211 in the first embodiment. Note that in the fifth embodiment, elements that perform the same functions as in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.
　図１４に示すように、第４の実施形態に係る半導体ウェハ２００ｄ（回路領域１００ｄ）のＮＭＯＳトランジスタ３００ｄは、拡散層２１１ａとして、Ｎ型拡散層ではなく、Ｐ型拡散層を用いている。このように、拡散層２１１ａは、必ずしもＮ型拡散層に限定されるものではなく、Ｐ型拡散層を用いてもよい。このような構造とすることにより、Ｎ型拡散層を用いた場合と異なり、負電圧の導通も可能となる。拡散層２１１ａをＰ型拡散層で構成する場合は、図１４に示すように、拡散層２１１ａの周囲にＮＷｅｌｌ層２６１を設けて半導体基板２０１と分離する。 As shown in FIG. 14, the NMOS transistor 300d of the semiconductor wafer 200d (circuit region 100d) according to the fourth embodiment uses a P-type diffusion layer as the diffusion layer 211a, not an N-type diffusion layer. Thus, the diffusion layer 211a is not necessarily limited to the N-type diffusion layer, and a P-type diffusion layer may be used. By adopting such a structure, unlike the case where an N-type diffusion layer is used, conduction of a negative voltage is possible. When the diffusion layer 211a is formed of a P-type diffusion layer, an NWell layer 261 is provided around the diffusion layer 211a and separated from the semiconductor substrate 201 as shown in FIG.
　このように、第５の実施形態によれば、半導体ウェハ２００ｄは、回路領域１００ｄの内部回路領域１０２からスクライブ領域２０３に引き出された導通部２０４と、回路領域１００ｄの内部回路領域１０２の外周に設けられたガードリング２０６とを有し、導通部２０４は、ガードリング２０６が配置された領域を通過して内部回路領域１０２からスクライブ領域２０３に至る部分として半導体基板２０１主面に形成された拡散層２１１ａを有している。従って、第１の実施形態と同様の効果を奏する。 Thus, according to the fifth embodiment, the semiconductor wafer 200d is formed on the outer periphery of the conductive portion 204 drawn from the internal circuit region 102 of the circuit region 100d to the scribe region 203 and the internal circuit region 102 of the circuit region 100d. The conductive portion 204 is a diffusion formed on the main surface of the semiconductor substrate 201 as a portion extending from the internal circuit region 102 to the scribe region 203 through the region where the guard ring 206 is disposed. A layer 211a is provided. Accordingly, the same effects as those of the first embodiment are obtained.
　また、第５の実施形態によれば、半導体ウェハ２００ｄは、ＮＭＯＳトランジスタ３００ｄの拡散層２１１ａがＰ型拡散層で構成されている。そのため、負電圧の導通も可能となる。 Further, according to the fifth embodiment, in the semiconductor wafer 200d, the diffusion layer 211a of the NMOS transistor 300d is configured by a P-type diffusion layer. Therefore, it is possible to conduct a negative voltage.
　以上、本発明者によってなされた発明を実施形態に基づき説明したが、本発明は上記した実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, although the invention made by the present inventor has been described based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.
　例えば、上記した実施形態では、スクライブ領域２０３に評価用のバッファ２４１を設けた構造を例示したが、通常、プローブテストにおいては比較的低速な試験しか実施できないため、拡散層２１１で抵抗を持った信号であっても評価可能である場合は、必ずしも評価用のバッファ２４１を設ける必要はない。 For example, in the above-described embodiment, the structure in which the evaluation buffer 241 is provided in the scribe region 203 is illustrated. However, since only a relatively low-speed test can be normally performed in the probe test, the diffusion layer 211 has resistance. If a signal can be evaluated, the evaluation buffer 241 is not necessarily provided.
　本出願は、２０１２年９月２０日に出願された、日本国特許出願第２０１２－２０６５９２号からの優先権を基礎として、その利益を主張するものであり、その開示はここに全体として参考文献として取り込む。 This application claims its benefit on the basis of priority from Japanese Patent Application No. 2012-206592 filed on September 20, 2012, the disclosure of which is hereby incorporated by reference in its entirety. Capture as.
１００　　：回路領域
１０２　　：内部回路領域
２００　　：半導体ウェハ
２００ｂ　：半導体ウェハ
２００ｃ　：半導体ウェハ
２００ｄ　：半導体ウェハ
２０１　　：基板
２０３　　：スクライブ領域
２０４　　：導通部
２０５　　：検査用パッド
２０６　　：ガードリング
２０７　　：チップ内パッド
２１１　　：拡散層
２１１ａ　：拡散層
２１３　　：内部回路側多層配線
２１５　　：スクライブ領域側多層配線
２１７　　：ゲート電極
２１９　　：評価用パッド
２２１　　：評価用拡散層
２３１　　：クラックストッパ
２４１　　：バッファ
２４５　　：入出力パッド
２４７　　：切替回路
２５１　　：自動接続パッド
２５１ａ　：入力パッド
２５１ｂ　：出力パッド
２５２　　：ワイヤボンディング
２６１　　：ＮＷｅｌｌ層
２７１　　：センターパッド
３００　　：ＭＯＳトランジスタ（プレーナ型電界効果トランジスタ） 100: Circuit area 102: Internal circuit area 200: Semiconductor wafer 200b: Semiconductor wafer 200c: Semiconductor wafer 200d: Semiconductor wafer 201: Substrate 203: Scribe area 204: Conductive portion 205: Inspection pad 206: Guard ring 207: In-chip pad 211: diffusion layer 211a: diffusion layer 213: internal circuit side multilayer wiring 215: scribe region side multilayer wiring 217: gate electrode 219: evaluation pad 221: evaluation diffusion layer 231: crack stopper 241: buffer 245: input / output pad 247 : Switching circuit 251: automatic connection pad 251a: input pad 251b: output pad 252: wire bonding 261: NWell layer 271: center pad 300: MOS transistor (planar type field effect) Transistor)

Claims (17)

  1. 　集積回路が配置された内部回路領域を有する回路領域と、前記回路領域の周囲に配置されたスクライブ領域とを含む半導体基板と、
    　前記半導体基板を覆い、複数の配線を備えた多層配線層と、
    　前記回路領域の前記内部回路領域と前記スクライブ領域との間の前記多層配線層に形成されたガードリングと、
    　前記スクライブ領域の前記多層配線層に形成された検査用パッドと、
    　前記スクライブ領域内の前記検査用パッドと前記内部回路領域内の前記集積回路とを電気的に接続する導通部であって、前記ガードリングと交差する部分では、前記半導体基板に形成された拡散層で構成された導通部と、
    　を有することを特徴とする半導体ウェハ。     A semiconductor substrate including a circuit region having an internal circuit region in which an integrated circuit is disposed, and a scribe region disposed around the circuit region;
    A multilayer wiring layer covering the semiconductor substrate and having a plurality of wirings;
    A guard ring formed in the multilayer wiring layer between the internal circuit region of the circuit region and the scribe region;
    An inspection pad formed in the multilayer wiring layer of the scribe region;
    A diffusion portion formed in the semiconductor substrate at a portion that is a conductive portion that electrically connects the test pad in the scribe region and the integrated circuit in the internal circuit region and intersects the guard ring. A conduction part composed of:
    A semiconductor wafer comprising:
  2. 　前記ガードリングは前記内部回路領域を囲むようにして形成されていることを特徴とする請求項１記載の半導体ウェハ。 2. The semiconductor wafer according to claim 1, wherein the guard ring is formed so as to surround the internal circuit region.
  3. 　前記ガードリングは、前記導通部の前記拡散層と交差する部分において層間絶縁膜を介して前記半導体基板上に配置されていることを特徴とする請求項１または２に記載の半導体ウェハ。 3. The semiconductor wafer according to claim 1, wherein the guard ring is disposed on the semiconductor substrate through an interlayer insulating film at a portion intersecting the diffusion layer of the conducting portion.
  4. 　前記導通部は、前記検査用パッドと前記集積回路との導通を制御するスイッチを有することを特徴とする請求項１乃至３のいずれか１項に記載の半導体ウェハ。 4. The semiconductor wafer according to claim 1, wherein the conduction part includes a switch for controlling conduction between the inspection pad and the integrated circuit.
  5. 　前記スイッチは電界効果トランジスタを有し、
    　前記導通部は、前記スクライブ領域から前記電界効果トランジスタのゲートに接続されたゲート導通部を有することを特徴とする請求項３記載の半導体ウェハ。     The switch has a field effect transistor;
    The semiconductor wafer according to claim 3, wherein the conduction part has a gate conduction part connected to the gate of the field effect transistor from the scribe region.
  6. 　前記導通部の前記拡散層は、内部に分離部を有することを特徴とする請求項１乃至５のいずれか１項に記載の半導体ウェハ。 6. The semiconductor wafer according to claim 1, wherein the diffusion layer of the conduction portion has a separation portion therein.
  7. 　前記拡散層内の前記分離部は、前記集積回路を構成する素子どうしを分離するＳＴＩと同じ深さで形成されていることを特徴とする請求項６記載の半導体ウェハ。 7. The semiconductor wafer according to claim 6, wherein the isolation portion in the diffusion layer is formed at the same depth as the STI that isolates elements constituting the integrated circuit.
  8. 　前記導通部は、
    　バッファ回路と、
    　前記導通部の入出力を切り替える切り替え回路と、
    　を有し、前記切り替え回路は前記回路領域から出力される出力バッファ信号により制御されることを特徴とする請求項１乃至７のいずれか１項に記載の半導体ウェハ。     The conduction part is
    A buffer circuit;
    A switching circuit for switching input / output of the conductive portion;
    The semiconductor wafer according to claim 1, wherein the switching circuit is controlled by an output buffer signal output from the circuit region.
  9. 　前記導通部は、
    　入力用導通部と、
    　バッファ回路を有する出力用導通部と、
    　前記入力用導通部と前記出力用導通部を接続可能な自動接続パッドと、
    　を有することを特徴とする請求項１乃至８のいずれか１項に記載の半導体ウェハ。     The conduction part is
    A conduction part for input;
    An output conducting portion having a buffer circuit;
    An automatic connection pad capable of connecting the conduction part for input and the conduction part for output;
    The semiconductor wafer according to claim 1, comprising:
  10. 　前記拡散層は、前記半導体基板に形成されたＮ型半導体層内に配置されたＰ型半導体層であることを特徴とする請求項１乃至９のいずれか１項に記載の半導体ウェハ。 10. The semiconductor wafer according to claim 1, wherein the diffusion layer is a P-type semiconductor layer arranged in an N-type semiconductor layer formed on the semiconductor substrate.
  11. 　前記導通部は、複数の前記回路領域の入力信号が共通に入出力されるセンターパッドを有することを特徴とする請求項１乃至１０のいずれか１項に記載の半導体ウェハ。 11. The semiconductor wafer according to claim 1, wherein the conduction portion has a center pad through which input signals of the plurality of circuit regions are input / output in common.
  12. 　前記導通部は、前記回路領域の前記多層配線層に形成されたパッドを有することを特徴とする請求項１乃至１１のいずれか１項に記載の半導体ウェハ。 The semiconductor wafer according to claim 1, wherein the conductive portion includes a pad formed on the multilayer wiring layer in the circuit region.
  13. 　前記検査用パッドは、前記スクライブ領域の前記多層配線層の最上層に配置され、
    　前記導通部において、前記検査用パッドと前記拡散層は前記多層配線層の前記複数の配線によって電気的に接続されていることを特徴とする請求項１乃至１２のいずれか１項に記載の半導体ウェハ。     The inspection pad is disposed on the uppermost layer of the multilayer wiring layer in the scribe region,
    13. The semiconductor according to claim 1, wherein in the conductive portion, the inspection pad and the diffusion layer are electrically connected by the plurality of wirings of the multilayer wiring layer. Wafer.
  14. 　前記回路領域は複数あって、それぞれは前記半導体基板上で行列状に配置され、
    　前記スクライブ領域は、行列状に配置された複数の前記回路領域のそれぞれを離間するように、前記回路領域の周囲に配置されていることを特徴とする請求項１乃至１３のいずれか１項に記載の半導体ウェハ。     There are a plurality of the circuit regions, each arranged in a matrix on the semiconductor substrate,
    14. The scribe area according to claim 1, wherein the scribe area is arranged around the circuit area so as to separate each of the plurality of circuit areas arranged in a matrix. The semiconductor wafer as described.
  15. 　半導体基板と、
    　前記半導体基板に形成され、集積回路が配置された回路領域と、
    　前記半導体基板を覆い、複数の配線を備えた多層配線層と、
    　前記回路領域を囲むように前記多層配線層に形成されたガードリングと、
    　前記回路領域内の前記集積回路と電気的に接続された導通部であって、前記ガードリングと平面的に交差する部分において前記半導体基板に形成された拡散層を有する導通部と、
    　を有し、
    　前記導通部の前記拡散層は、前記半導体基板の端部に達していることを特徴とする半導体装置。     A semiconductor substrate;
    A circuit region formed on the semiconductor substrate and provided with an integrated circuit;
    A multilayer wiring layer covering the semiconductor substrate and having a plurality of wirings;
    A guard ring formed in the multilayer wiring layer so as to surround the circuit region;
    A conductive portion electrically connected to the integrated circuit in the circuit region, the conductive portion having a diffusion layer formed on the semiconductor substrate in a portion intersecting the guard ring in a plane;
    Have
    The semiconductor device according to claim 1, wherein the diffusion layer of the conductive portion reaches an end portion of the semiconductor substrate.
  16. 　集積回路を備えた回路領域およびスクライブ領域を含む半導体基板と、前記スクライブ領域に配置された検査用パッドと、前記検査用パッドと前記集積回路とを電気的に接続する導通部と、前記導通部の一部を構成する前記半導体基板に形成された拡散層と、を有する半導体ウェハの前記検査用パッドに、プローブを接触する工程と、
    　前記プローブに信号を与えることで、前記集積回路の動作テストを行なう工程と、
    　前記動作テストを行った後、前記スクライブ領域を切断することで、前記半導体基板を個片化する工程と、を有することを特徴とする半導体装置の製造方法。     A semiconductor substrate including a circuit region and a scribe region provided with an integrated circuit, a test pad disposed in the scribe region, a conductive portion that electrically connects the test pad and the integrated circuit, and the conductive portion A step of contacting a probe to the inspection pad of the semiconductor wafer having a diffusion layer formed on the semiconductor substrate constituting a part of the semiconductor substrate;
    Performing an operation test of the integrated circuit by providing a signal to the probe;
    And a step of separating the semiconductor substrate by cutting the scribe region after performing the operation test.
  17. 　前記半導体ウェハは、更に、前記回路領域と前記スクライブ領域との間の前記半導体基板上に配置されたガードリングを有し、
    　前記拡散層は、前記導通部のうち、前記ガードリングと交差する部分に配置されていることを特徴とする請求項１６記載の半導体装置の製造方法。     The semiconductor wafer further includes a guard ring disposed on the semiconductor substrate between the circuit region and the scribe region;
    The method of manufacturing a semiconductor device according to claim 16, wherein the diffusion layer is disposed in a portion of the conducting portion that intersects the guard ring.
PCT/JP2013/074642 2012-09-20 2013-09-12 Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor device WO2014045989A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3439032A1 (en) * 2017-08-04 2019-02-06 MediaTek Inc. Semiconductor package assembly and method for forming the same
US20230120504A1 (en) * 2021-10-18 2023-04-20 Artilux, Inc. Wafer-Level Device Measurement for Optical Sensors

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211843A (en) * 1990-01-17 1991-09-17 Matsushita Electron Corp Semiconductor integrated circuit
JP2002217367A (en) * 2001-01-15 2002-08-02 Mitsubishi Electric Corp Semiconductor chip, semiconductor device and method for manufacturing the same
JP2003203913A (en) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd Semiconductor device and semiconductor chip
JP2003209148A (en) * 2002-01-16 2003-07-25 Sony Corp Semiconductor wafer, method for inspecting semiconductor wafer and method for manufacturing semiconductor device
JP2005150514A (en) * 2003-11-18 2005-06-09 Matsushita Electric Ind Co Ltd Semiconductor wafer
JP2006041236A (en) * 2004-07-28 2006-02-09 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2010153753A (en) * 2008-12-26 2010-07-08 Renesas Electronics Corp Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211843A (en) * 1990-01-17 1991-09-17 Matsushita Electron Corp Semiconductor integrated circuit
JP2002217367A (en) * 2001-01-15 2002-08-02 Mitsubishi Electric Corp Semiconductor chip, semiconductor device and method for manufacturing the same
JP2003203913A (en) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd Semiconductor device and semiconductor chip
JP2003209148A (en) * 2002-01-16 2003-07-25 Sony Corp Semiconductor wafer, method for inspecting semiconductor wafer and method for manufacturing semiconductor device
JP2005150514A (en) * 2003-11-18 2005-06-09 Matsushita Electric Ind Co Ltd Semiconductor wafer
JP2006041236A (en) * 2004-07-28 2006-02-09 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2010153753A (en) * 2008-12-26 2010-07-08 Renesas Electronics Corp Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3439032A1 (en) * 2017-08-04 2019-02-06 MediaTek Inc. Semiconductor package assembly and method for forming the same
CN109411463A (en) * 2017-08-04 2019-03-01 联发科技股份有限公司 Semiconductor package and forming method thereof
TWI676240B (en) * 2017-08-04 2019-11-01 聯發科技股份有限公司 A semiconductor package assembly and method for forming the same
US10497689B2 (en) 2017-08-04 2019-12-03 Mediatek Inc. Semiconductor package assembly and method for forming the same
US10903198B2 (en) 2017-08-04 2021-01-26 Mediatek Inc Semiconductor package assembly and method for forming the same
CN109411463B (en) * 2017-08-04 2021-03-12 联发科技股份有限公司 Semiconductor packaging assembly and forming method thereof
EP4235766A3 (en) * 2017-08-04 2023-10-04 MediaTek Inc. Semiconductor package assembly and method for forming the same
US20230120504A1 (en) * 2021-10-18 2023-04-20 Artilux, Inc. Wafer-Level Device Measurement for Optical Sensors

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