WO2014036676A1 - Multiple time programmable semiconductor device and manufacturing method thereof - Google Patents

Multiple time programmable semiconductor device and manufacturing method thereof Download PDF

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Publication number
WO2014036676A1
WO2014036676A1 PCT/CN2012/001536 CN2012001536W WO2014036676A1 WO 2014036676 A1 WO2014036676 A1 WO 2014036676A1 CN 2012001536 W CN2012001536 W CN 2012001536W WO 2014036676 A1 WO2014036676 A1 WO 2014036676A1
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Prior art keywords
layer
substrate
semiconductor device
gate
programmable semiconductor
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PCT/CN2012/001536
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French (fr)
Chinese (zh)
Inventor
梁擎擎
钟汇才
朱慧珑
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中国科学院微电子研究所
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Publication of WO2014036676A1 publication Critical patent/WO2014036676A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the present invention relates to a multi-programmable semiconductor device and a method of fabricating the same, and more particularly to a high-density, multi-programmable semiconductor device suitable for fin field effect transistor (FinFET) technology and a method of fabricating the same.
  • FinFET fin field effect transistor
  • the electrical erasing is realized by the FN tunneling effect of the thin oxide layer, which usually includes super-thin tunnel oxide layer, polysilicon floating gate, interlayer dielectric, polysilicon sequentially stacked on the channel region. Or a metal control grid.
  • the thin oxide layer usually includes super-thin tunnel oxide layer, polysilicon floating gate, interlayer dielectric, polysilicon sequentially stacked on the channel region. Or a metal control grid.
  • the performance of this structure in small-sized devices is greatly reduced.
  • changes in threshold voltage severely limit drive strength and response speed.
  • An effective solution is to use FinFET to implement E 2 PROM, to increase or decrease the threshold voltage of the transistor by changing the charge of the floating gate, thereby providing higher performance and lower power consumption for the chip.
  • the existing FinFET realized E 2 PROM structure is too complicated, the device area is large, the process cost is high, and the integration density is low, which is difficult to be applied to large-scale memory cell array fabrication.
  • the present invention provides a multi-programmable semiconductor device comprising: a plurality of fin structures on a substrate and extending along a first direction parallel to a surface of the substrate, including a bottom implant region, a buried oxide layer, and a top layer a channel region located in a top layer of the plurality of fin structures; a source and drain region located at both ends of the channel region in the top layer of the plurality of fin structures; a gate insulating layer located at a top portion and a side portion of the channel region And extending in a second direction parallel to the surface of the substrate; a floating gate on both sides of the plurality of fin structures in the second direction; and a program/erase gate formed by the substrate implantation region under the buried oxide layer.
  • the method further includes: an interlayer dielectric layer covering a plurality of fin structures, a gate insulating layer, a control gate, and a floating gate; a source/drain contact hole and a program/erase gate contact hole formed in the interlayer dielectric layer, respectively exposing the source a drain region and a substrate implant region as a program/erase gate; a metal silicide formed in the source/drain contact hole and the program/erase gate contact hole; a connection line through the metal silicide and the source and drain regions and as a programming/ The substrate implantation region of the erase gate is electrically connected.
  • the plurality of fin structures further include a cap layer on the top layer.
  • the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof.
  • the high-k material comprises a material selected Hf0 2, HfSiO x, HfSiON, HfA10 x, HfTaO x, HfLaO x, a hafnium-based material HfAlSiO x HfLaSiO x, or selected from the group comprising Zr ⁇ 2, 2 0 3, LaA10 3 , A rare earth-based high-k dielectric material of Ti0 2 , Y 2 0 3 or a composite layer comprising A1 2 0 3 and the above materials.
  • the floating gate comprises polysilicon, a metal, an alloy of the metal, a nitride of the metal, and a combination thereof.
  • the metal comprises Al, Ta, Ti, and combinations thereof.
  • the material of the metal silicide includes NiSi 2-y , PtSi 2-y , CoSi 2-y , Ni, -x Pt x Si 2-y , Ni 1-x Co x Si 2-y , Pt 1 -x Co x Si 2-y , Ni 2-xz Pt x Co z Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.
  • the material of the connecting line includes W, Cu, Al, Ti, Ta and combinations thereof.
  • the present invention also provides a method of fabricating a multi-programmable semiconductor device, comprising the steps of: forming a plurality of fin structures extending along a first direction parallel to a surface of the substrate, including a substrate implantation region, and burying on the substrate Oxygen layer, top layer; forming a gate insulating layer on top of and on both sides of the fin structure; forming a gate conductive layer on both sides of the gate insulating layer; lithography/etching the gate conductive layer, only in the top layer a portion of the gate conductive layer remains on both sides of the channel region as a floating gate; lithography/etching a plurality of fin structures, exposing portions of the substrate implantation region; forming source-drain Touching, and forming a program/erase gate contact connected to the exposed substrate implant region.
  • the step of forming a plurality of fin structures further includes: performing doping implantation on a substrate including a bottom layer, a buried oxide layer, and a top layer, and forming a substrate implantation region in a bottom layer below the buried oxide layer to form a program/erase gate
  • the lithography/etching of the substrate until the undoped underlayer is exposed forms a plurality of fin structures extending in a first direction parallel to the surface of the substrate.
  • the step of photolithography/etching the gate conductive layer further includes: forming a hard mask pattern on the substrate, the gate conductive layer, and the gate insulating layer along a second direction extending parallel to the surface of the substrate;
  • the hard mask pattern is used as a mask to etch the gate conductive layer, leaving only a portion of the gate conductive layer covered by the hard mask pattern, wherein the top layer under the hard mask pattern constitutes a channel region, and the top layer at both ends of the channel region Form the source and drain areas.
  • the step of exposing a portion of the substrate implant region further includes: forming a hard mask layer over the entire device; planarizing until the gate insulating layer is exposed; lithography/etching portion of the gate insulating layer, top layer, buried oxide layer Until the substrate implant region is exposed, a program/erase gate contact hole is formed, wherein the program/erase gate contact hole is located at one end of the source and drain regions in the first direction.
  • the step of forming a source/drain contact and forming a program/erase gate contact hole connected to the exposed substrate implant region further comprises: forming an interlayer dielectric layer over the entire device; photolithography/etching to form a source/drain contact hole, And a program/erase gate contact hole connected to the exposed substrate implantation region; forming a metal silicide in the source/drain contact hole and the program/erase gate contact hole; at the source/drain contact hole and the program/erase gate contact hole
  • the conductive material is filled to form a connecting line.
  • the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, high k materials, and combinations thereof.
  • the high-k material comprises a germanium-based material selected from the group consisting of Hf0 2 , HfSiO x , HfSiON, HfA10 x , HfTaO x , HfLaO x , HfAlSiO x , HfLaSiO x , or includes a material selected from the group consisting of Zr0 2 , La 2 0 3 , and LaA10 3 a rare earth-based high-k dielectric material of Ti0 2 , Y 2 0 3 or a composite layer comprising the above materials of A1 2 0 3 .
  • the floating gate comprises polysilicon, a metal, an alloy of the metal, a nitride of the metal, and a combination thereof.
  • the metal comprises Al, Ta, Ti, and combinations thereof.
  • the material of the metal silicide includes NiSi 2- y, PtSi 2-y , CoSi 2-y , Ni 1-x Pt x Si 2-y , Ni 1-x Co x Si 2-y , Pt 1 -x Co x Si 2-y , Ni 2-xz Pt x Co z Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.
  • the material of the connecting wire includes W, Cu, Al, Ti, Ta and a combination thereof.
  • the substrate injection region is used to form the program/erase gate of the FinFET, which simplifies the device structure, reduces the manufacturing process, and improves the integration density of the device, and is suitable for Multiple programmable memory.
  • Figure 1A shows a top view of method step S1 in accordance with the present invention, wherein a fin structure extending in a first direction is formed on the SOI substrate;
  • Figure 1B is a cross-sectional view taken along line A A ' in Figure 1A;
  • FIG. 2A shows a top view of method step S2 in accordance with the present invention, wherein a gate insulating layer and a gate conductive layer are formed on the fin structure and on the sides;
  • Figure 2B is a cross-sectional view taken along line AA' of Figure 2A;
  • Figure 2C is a cross-sectional view taken along line BB of Figure 2A;
  • Figure 2D is a cross-sectional view taken along line CC' of Figure 2A;
  • Figure 2E is a cross-sectional view taken along line DD' of Figure 2A;
  • Figure 3A shows a top view of method step S3 in accordance with the present invention, wherein a mask is formed along the second direction and the gate insulating layer and the gate conductive layer are etched;
  • Figure 3B is a cross-sectional view taken along line AA' of Figure 3A;
  • Figure 3C is a cross-sectional view taken along line BB' of Figure 3A;
  • Figure 3D is a cross-sectional view taken along line CC of Figure 3A;
  • Figure 3E is a cross-sectional view taken along line DD' of Figure 3A;
  • FIG. 4A shows a top view of method step S4 in accordance with the present invention, wherein etching forms a programming/erasing gate contact hole;
  • Figure 4B is a cross-sectional view taken along line AA of Figure 4A;
  • Figure 4C is a cross-sectional view taken along line BB' of Figure 4A;
  • Figure 4D is a cross-sectional view taken along line CC' of Figure 4A;
  • Figure 4E is a cross-sectional view taken along line DD' of Figure 4A;
  • Figure 4F is a cross-sectional view taken along line EE' of Figure 4A;
  • Figure 5A shows a top view of method step S5 in accordance with the present invention in which source and drain contacts and program/erase gate contacts are formed;
  • Figure 5B is a cross-sectional view taken along line AA' of Figure 5A;
  • Figure 5C is a cross-sectional view taken along line BB' of Figure 5A
  • Figure 5D is a cross-sectional view along line CC of Figure 5A;
  • Figure 5E is a cross-sectional view taken along line DD' of Figure 5A;
  • Figure 5F is a cross-sectional view taken along line EE of Figure 5A;
  • Figure 6 shows a flow chart of a method in accordance with the present invention. detailed description
  • a semiconductor substrate is provided which is made of silicon-on-insulator (SOI) and includes a bottom layer 1, a buried oxide layer 2, and a top layer 3.
  • SOI silicon-on-insulator
  • the bottom layer 1 and the top layer 3 are all made of silicon (Si), and the thickness of the top layer 3 is smaller than the thickness of the bottom layer 1.
  • the buried oxide layer 2 is made of a corresponding oxide of the top layer 3 material, for example, silicon oxide (Si0 2 ), and the thickness of the buried oxide layer 2 is smaller than the thickness of the top layer 3.
  • the semiconductor substrate is doped and implanted, and different types of dopant ions are implanted according to different types of PMOS and NMOS conductivity.
  • the peak of the doping ion implantation is located below the buried oxide layer 2, for example, 1 to 10 nm from the bottom surface of the buried oxide layer 2, so that a portion of the underlying layer 1 has a higher n+ or p+ doping concentration, which constitutes the underlying implantation region 1D. Used later as a program/erase gate (or called a word line).
  • a smaller portion of the dopant ions are also distributed in the top layer 3 such that the top layer 3 has a lower n- or P-doping concentration to facilitate later formation of source and drain regions.
  • the cap layer 4 is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and the material thereof is, for example, silicon nitride or silicon oxynitride, which is used to form a hard mask for fin structure etching and blocking by subsequent etching.
  • Floor Photolithographically and anisotropically etching the cap layer 4, the top layer 3, the buried oxide layer 2, and the underlying implant region 1 D until the undoped underlayer 1 is exposed, forming a first layer on the underlayer 1 parallel to the surface of the underlayer 1 A plurality of fin structures extending in the direction.
  • FIG. 1A in a top view, a plurality of fin structures extend in a first direction parallel to a surface of the substrate, and a line AA' is a second direction parallel to the surface of the substrate passing through the plurality of fin structures.
  • the line of intersection which will be the position of the gate (floating gate) of the FinFET device, where the second direction intersects the first direction, Optionally vertical.
  • 1B is a cross-sectional view taken along line AA' of FIG. 1A, wherein the plurality of fin structures include a cap layer 4, a top layer 3, a buried oxide layer 2, and an underlying implantation region 1D from top to bottom.
  • a step S2 of the method according to the present invention wherein a gate insulating layer extending in a first direction is formed on a side surface and a top surface of the plurality of fin structures, and a gate insulating layer is provided A gate conductive layer extending in the first direction is formed on both sides.
  • a gate insulating material is deposited on the fin structure (4/3/2/1A) and the underlayer 1 by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, and photolithography/etching, leaving only on the top and side of the fin structure.
  • a gate insulating layer 5 extending in the first direction.
  • the material of the gate insulating layer 5 includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof.
  • the high-k material comprises a germanium-based material selected from the group consisting of: 2 , HfSiO x , HfSiON , HfA10 x , HfTaO x , HfLaO x , HfAlSiO x , HfLaSiO x , or includes Zr0 2 , La 2 0 3 , LaA10 3 , A rare earth-based high-k dielectric material of Ti0 2 , Y 2 0 3 or a composite layer comprising A1 2 0 3 and the above materials.
  • a high-k material is selected as the gate insulating layer 5 so as to be suitable for a small-sized device, so that an ultra-thin gate insulating layer can be used as a tunnel oxide layer to realize electrical erasing using FN tunneling.
  • the thickness of the gate insulating layer 5 is, for example, 1 to 10 nm.
  • a gate conductive material is deposited on the gate insulating layer 5 and the underlayer 1 by a conventional method such as LPCVD, PECVD, HDPCVD, ALD, etc., and photolithography/etching is performed only on the substrate underside of the gate insulating layer 5.
  • a gate conductive layer 6 extending in the first direction is left on 1 and will later be patterned to serve as a floating gate.
  • the material of the gate conductive layer 6 includes polysilicon, metal, alloy of metal, nitride of metal, and combinations thereof, wherein the metal includes Al, Ta, Ti, and combinations thereof.
  • the thickness of the gate conductive layer 6 is, for example, 1 to 10 nm.
  • Figure 2A is a top view, wherein the section line AA' is the same as the section line AA' in Figure 1A; the section line BB is parallel to the section line AA, and also in the second direction, but with a certain distance, its position is later Used as the source and drain region of the device; the line CC, passing through the fin structure, and in the first direction, its position including the later channel region and the connection region of the program/erase gate; the cross-line DD, not crossed The fin structure, and in the first direction, is used to supplement the spatial structure of the device.
  • 2B and FIG. 2C are cross-sectional views of FIG.
  • FIG. 2A is a cross-sectional view taken along line AA' and line BB, respectively, showing that the gate insulating layer 5 is distributed on the top and sides of the fin structure (4/3/2/1 A ) on the substrate underlayer 1;
  • the gate conductive layer 6 is distributed on both sides of the gate insulating layer 5 on the underlayer 1 of the substrate, and its top portion is lower than the top of the gate insulating layer 5.
  • 2D is a cross-sectional view taken along line CC' of FIG. 2A, and it can be seen that the gate insulating layer 5 is located at the top of the fin structure and also extends along the first direction.
  • Figure 2E is a cross-sectional view taken along line DD' of Figure 2A, See that there is no gate insulating layer 5 and gate conductive layer outside the fin structure region on the substrate underlayer 1.
  • step S3 of the method according to the present invention is shown, wherein a mask is formed along the second direction and a portion of the gate insulating layer and the gate conductive layer are etched away, only in the mask covering region. A portion of the gate insulating layer and the gate conductive layer are reserved.
  • the first hard mask material is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride.
  • the lithographic/etching hard mask material forms a plurality of first hard mask patterns 7 extending along the second direction, wherein at least one of the first hard mask patterns 7 passes through the cross-sectional line AA to retain the gate underneath
  • the insulating layer 5 and the gate conductive layer 6 serve as an insulating layer and a floating gate on both sides of the channel region of the device.
  • the gate conductive layer 6 is anisotropically etched using the first hard mask pattern 7 as a mask so that only the gate conductive layer 6 under the first hard mask pattern 7 remains as a floating gate.
  • Fig. 3A is a top view, showing that the first hard mask pattern 7 extends in the second direction and passes at least through the line AA'.
  • 3B and 3C are cross-sectional views taken along line AA, BB of Fig. 3A, respectively, showing that the gate conductive layer 6 is removed on the region not covered by the first hard mask pattern 7.
  • 3D and 3E are cross-sectional views of FIG. 3A along line CC: ', DD', respectively, wherein AA, the top layer 3 portion of the region through which the line passes constitutes the channel region 3C, and the remaining top portion 3 portion constitutes the source/drain region 3S/ 3D, the future will be used as the control part (or bit line) of the device.
  • step S4 of the method in accordance with the present invention is shown wherein etching forms a control gate contact hole.
  • a second hard mask layer 8 is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and is made of, for example, silicon oxide, silicon nitride or silicon oxynitride, preferably a second hard mask layer 8 and The material of a hard mask layer/pattern 7 is the same.
  • the second hard mask layer 8 is then planarized by a process such as CMP until the gate insulating layer 5 is exposed.
  • FIG. 4A is a top view in which the cut line EE' passes through the position where the program/erase gate contact hole 8H is located, and in the second direction, the program/erase gate contact hole 8H extends in the first direction.
  • 4B and FIG. 4C are cross-sectional views along line AA, BB, respectively, of FIG. 4A. Similar to FIGS. 3B and 3C, it can be seen that the gate conductive layer 6 is removed on the region not covered by the original first hard mask pattern 7.
  • FIG. 4D is a cross-sectional view along line CC' of FIG. 4A, showing that the program/erase gate contact hole 8H is directed to the underlying implant region 1 D such that the doped underlying implant region 1 D as a program/erase gate can be electrically connected to the outside.
  • Figure 4E is a cross-sectional view of Figure 4A taken along line DD.
  • Figure 4F is a cross-sectional view of Figure 4A taken along line EE', visible in the program/erase gate contact hole In 8H, the top portion of the gate insulating layer 5 and a portion of the side portion are removed, and only the portions on both sides of the underlying implantation region 1 D are retained.
  • step S5 of the method in accordance with the present invention is shown in which source-drain contacts and program/erase gate contacts are formed.
  • the interlayer dielectric layer 9 is deposited on the entire device by conventional methods such as LPC VD, PECVD, HDPCVD, ALD, etc., and is made of, for example, silicon oxide, silicon nitride or silicon oxynitride, preferably with the first hard mask layer/pattern 7 And/or the material of the second hard mask layer 8 is the same.
  • the photolithography/etching interlayer dielectric layer 9 forms a source/drain contact hole 9SD at a position corresponding to the source/drain region 3S/3D, and forms a program/erase gate at a position corresponding to the program/erase gate contact hole 8H.
  • Metal silicide 10 is then formed in each contact hole to lower the contact resistance.
  • the material of the metal silicide 10 includes NiSi 2-y , PtSi 2-y , CoSi 2-y , Ni Ix Pt x Si 2-y , Ni Bu x Co x Si 2-y , Pti - x Co x Si 2- y Ni 2-xz Pt x Co z Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.
  • the conductive material 11 is then filled in each contact hole to form a contact plug and a connecting line, such as W, Cu, Al, Ti, Ta, and combinations thereof.
  • 5A is a top view, wherein AA, the line passes through the channel region and the gate insulating layer and the gate conductive layer on both sides of the channel region, BB, through the source and drain regions and the gate insulating layers on both sides of the source and drain regions , CC, through the source and drain regions, the channel region, the program/erase gate contact hole, DD' only passes through the substrate underlayer 1, EE, through the village implant region 1 D.
  • 5B is a cross-sectional view along line AA of FIG. 5A, and it can be seen that a gate insulating layer 5 is provided on both sides of the channel region 3C, and a gate conductive layer 6 (floating gate) is provided on both sides of the gate insulating layer 5.
  • 5C is a cross-sectional view along line BB' of FIG. 5A, showing that the source-drain connection line 1 1 SD (as a bit line of the device unit) is electrically connected to the source and drain regions 3S/3D through the metal silicide 10, and only the gates are provided on both sides of the source and drain regions.
  • the pole insulating layer 5 has no gate conductive layer 6.
  • 5D and FIG. 5E are respectively a cross-sectional view of FIG.
  • Fig. 5E is a cross-sectional view taken along line DD' of Fig. 5A.
  • the resulting multi-programmable semiconductor device includes: a plurality of fin structures on the substrate, including a substrate implant region 1 D, a buried oxide layer 2, a top layer 3, and optionally a cover layer 4, a plurality of fin structures extending in a first direction parallel to the bottom surface of the substrate; a channel region 3C located in the top layer 3 of the plurality of fin structures; a source/drain region 3S/3D located in the plurality of fins
  • the top layer 3 of the structure has two ends of the channel region 3C;
  • the gate insulating layer 5 is located at the top and the side of the channel region 3C, and extends in a second direction parallel to the surface of the substrate, and the second direction intersects the first direction And preferably perpendicular;
  • the floating gate 6 is located on both sides in the second direction of the fin structure, in contact with the gate insulating layer 5;
  • the program/erase gate is formed by the substrate implantation region 1 D, located in the channel Below the region 3C; the inter
  • the multi-programmable semiconductor device utilizes a substrate implant region to form a FinFET program/erase gate, simplifies device structure, reduces manufacturing processes, and increases device integration density, and is suitable for multiple programmable Memory.

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Abstract

Provided is a multiple time programmable semiconductor device, comprising: a plurality of fin-shaped structures located on a substrate, extending in a first direction parallel with the surface of the substrate, and comprising a substrate injection region (1D), a buried oxide layer (2), and a top layer (3); a groove region (3C) located in the top layers (3) of the plurality of fin-shaped structures; drain/source regions (3S/3D) located at the two ends of the groove region (3C) in the top layers (3) of the plurality of fin-shaped structures; a gate insulation layer (5) located at the top and the side of the groove region (3C) and extending in a second direction parallel with the surface of the substrate; a floating gate (6) located in the second direction on the two sides of the plurality of fin-shaped structures; and a programming/erase gate formed by the substrate injection region (1D) and located under the buried oxide layer (2). The multiple time programmable semiconductor device and manufacturing method thereof utilize a substrate injection region to form a FinFET programming/erase gate, simplify device structure, and reduce manufacturing processes, thus improving device integration density and being suitable for a multiple time programmable memory.

Description

多次可编程半导体器件及其制造方法 优先权要求  Multi-programmable semiconductor device and its manufacturing method
本申请要求了 2012年 9月 5日提交的、 申请号为 201210326597.X、 发 明名称为 "多次可编程半导体器件及其制造方法" 的中国专利申请的 优先权， 其全部内容通过引用结合在本申请中。 技术领域  The present application claims priority to Chinese Patent Application No. 201210326597.X, entitled "Multi-Programmable Semiconductor Device and Its Manufacturing Method", filed on September 5, 2012, the entire contents of In this application. Technical field
本发明涉及一种多次可编程半导体器件及其制造方法， 特别是涉 及一种高密度、 适用于鳍形场效应晶体管 （FinFET ) 技术的多次可编 程半导体器件及其制造方法。 背景技术  The present invention relates to a multi-programmable semiconductor device and a method of fabricating the same, and more particularly to a high-density, multi-programmable semiconductor device suitable for fin field effect transistor (FinFET) technology and a method of fabricating the same. Background technique
随着 CMOS工艺特征尺寸持续等比例缩减， MOS存储器结构发展 迅速， 出现了各种类型的存储器单元结构。 DRAM 虽然集成度高功耗 低但是无法长期保存信息， 而 SRAM虽然可以长期保存信息但是面积 大集成度低。 当前的技术发展逐渐着眼于 ROM , 特别是电可擦除的 E2PROM。 As CMOS process feature sizes continue to scale down, MOS memory structures are evolving rapidly, and various types of memory cell structures have emerged. Although DRAM has low integration and low power consumption, it cannot store information for a long time, while SRAM can store information for a long time but has a large area and low integration. Current technology developments are increasingly focused on ROM, especially the electrically erasable E 2 PROM.
现有的 E2PROM单元中， 利用薄氧化层的 F-N隧道效应实现电擦 除， 通常包括沟道区上依次叠置超薄的隧道氧化层、 多晶硅的浮栅、 层间介电质、 多晶硅或金属的控制栅。 然而因为传统的 MOSFET中亚 阔值漏电， 这种结构在小尺寸器件中的性能大大降低。 此外， 阈值电 压的变化严重限制了驱动强度和响应速度。 In the existing E 2 PROM unit, the electrical erasing is realized by the FN tunneling effect of the thin oxide layer, which usually includes super-thin tunnel oxide layer, polysilicon floating gate, interlayer dielectric, polysilicon sequentially stacked on the channel region. Or a metal control grid. However, due to the sub-bump leakage in conventional MOSFETs, the performance of this structure in small-sized devices is greatly reduced. In addition, changes in threshold voltage severely limit drive strength and response speed.
一种有效地解决方案是利用 FinFET来实现 E2PROM， 通过改变浮 栅的电荷来提高或减小晶体管的阈值电压， 从而为芯片提供较高的性 能和较低的功耗。然而，现有的 FinFET实现的 E2PROM结构过于复杂、 器件面积较大， 工艺成本高昂、 集成密度低， 难以适用于大规模的存 储器单元阵列制造。 An effective solution is to use FinFET to implement E 2 PROM, to increase or decrease the threshold voltage of the transistor by changing the charge of the floating gate, thereby providing higher performance and lower power consumption for the chip. However, the existing FinFET realized E 2 PROM structure is too complicated, the device area is large, the process cost is high, and the integration density is low, which is difficult to be applied to large-scale memory cell array fabrication.
总而言之， 当前的多次可编程半导体器件结构复杂、 成本高昂、 效率较低， 亟需改进。 发明内容 因此， 本发明的目的在于提供一种高密度集成的、 适用于 FinFET 技术的多次可编程半导体器件及其制造方法。 In summary, current multi-programmable semiconductor devices are complex, costly, and inefficient, and need to be improved. Summary of the invention Accordingly, it is an object of the present invention to provide a high density integrated multi-programmable semiconductor device suitable for FinFET technology and a method of fabricating the same.
本发明提供了一种多次可编程半导体器件， 包括： 多个鳍形结构， 位于衬底上且沿平行于衬底表面的第一方向延伸分布， 包括村底注入 区、 埋氧层、 顶层； 沟道区， 位于多个鳍形结构的顶层中； 源漏区， 位于多个鳍形结构的顶层中沟道区两端； 栅极绝缘层， 位于沟道区的 顶部以及侧部， 沿平行于衬底表面的第二方向延伸分布； 浮栅， 位于 多个鳍形结构的第二方向上的两侧； 编程 /擦除栅， 由衬底注入区构成， 位于埋氧层下方。  The present invention provides a multi-programmable semiconductor device comprising: a plurality of fin structures on a substrate and extending along a first direction parallel to a surface of the substrate, including a bottom implant region, a buried oxide layer, and a top layer a channel region located in a top layer of the plurality of fin structures; a source and drain region located at both ends of the channel region in the top layer of the plurality of fin structures; a gate insulating layer located at a top portion and a side portion of the channel region And extending in a second direction parallel to the surface of the substrate; a floating gate on both sides of the plurality of fin structures in the second direction; and a program/erase gate formed by the substrate implantation region under the buried oxide layer.
进一步包括： 层间介质层， 覆盖多个鳍形结构、 栅极绝缘层、 控 制栅、 浮栅； 源漏接触孔与编程 /擦除栅接触孔， 形成在层间介质层中， 分别暴露源漏区以及作为编程 /擦除栅的衬底注入区； 金属硅化物， 形 成在源漏接触孔与编程 /擦除栅接触孔中； 连接线， 通过金属硅化物与 源漏区以及作为编程 /擦除栅的衬底注入区电连接。  The method further includes: an interlayer dielectric layer covering a plurality of fin structures, a gate insulating layer, a control gate, and a floating gate; a source/drain contact hole and a program/erase gate contact hole formed in the interlayer dielectric layer, respectively exposing the source a drain region and a substrate implant region as a program/erase gate; a metal silicide formed in the source/drain contact hole and the program/erase gate contact hole; a connection line through the metal silicide and the source and drain regions and as a programming/ The substrate implantation region of the erase gate is electrically connected.
其中， 多个鳍形结构还包括位于顶层之上的盖层。  Wherein, the plurality of fin structures further include a cap layer on the top layer.
其中， 栅极绝缘层包括氧化硅、 氮化硅、 氮氧化硅、 高 k材料及其 组合。其中，高 k材料包括选自 Hf02、HfSiOx、 HfSiON、HfA10x、HfTaOx、 HfLaOx、 HfAlSiOx HfLaSiOx的铪基材料， 或是包括选自 Zr〇2、 203、 LaA103、 Ti02、 Y203的稀土基高 K介质材料， 或是包括 A1203， 以其上 述材料的复合层。 The gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof. Wherein the high-k material comprises a material selected Hf0 2, HfSiO x, HfSiON, HfA10 x, HfTaO x, HfLaO x, a hafnium-based material HfAlSiO x HfLaSiO x, or selected from the group comprising Zr〇 2, 2 0 3, LaA10 3 , A rare earth-based high-k dielectric material of Ti0 2 , Y 2 0 3 or a composite layer comprising A1 2 0 3 and the above materials.
其中， 浮栅包括多晶硅、 金属、 所述金属的合金、 所述金属的氮 化物及其组合。 其中， 所述金属包括 Al、 Ta、 Ti及其组合。  Wherein, the floating gate comprises polysilicon, a metal, an alloy of the metal, a nitride of the metal, and a combination thereof. Wherein, the metal comprises Al, Ta, Ti, and combinations thereof.
其中，金属硅化物的材质包括 NiSi2-y、 PtSi2-y、 CoSi2-y、 Ni,-xPtxSi2-y, Ni1-xCoxSi2-y, Pt1 -xCoxSi2-y, Ni2-x-zPtxCozSi3-y , 其中 x、 z大于 0小于 1 , y 大于等于 0小于等于 1。 Among them, the material of the metal silicide includes NiSi 2-y , PtSi 2-y , CoSi 2-y , Ni, -x Pt x Si 2-y , Ni 1-x Co x Si 2-y , Pt 1 -x Co x Si 2-y , Ni 2-xz Pt x Co z Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.
其中， 连接线的材质包括 W、 Cu、 Al、 Ti、 Ta及其组合。  The material of the connecting line includes W, Cu, Al, Ti, Ta and combinations thereof.
本发明还提供了一种多次可编程半导体器件制造方法， 包括步骤： 在衬底上形成沿平行于衬底表面的第一方向延伸分布的多个鳍形结 构， 包括衬底注入区、 埋氧层、 顶层； 在多个鳍形结构顶部以及两侧 形成栅极绝缘层； 在栅极绝缘层两侧形成栅极导电层； 光刻 /刻蚀栅极 导电层， 仅在位于顶层中的沟道区两侧保留部分的栅极导电层， 作为 浮栅； 光刻 /刻蚀多个鳍形结构， 暴露部分的衬底注入区； 形成源漏接 触， 以及形成连接到暴露的衬底注入区的编程 /擦除栅接触。 The present invention also provides a method of fabricating a multi-programmable semiconductor device, comprising the steps of: forming a plurality of fin structures extending along a first direction parallel to a surface of the substrate, including a substrate implantation region, and burying on the substrate Oxygen layer, top layer; forming a gate insulating layer on top of and on both sides of the fin structure; forming a gate conductive layer on both sides of the gate insulating layer; lithography/etching the gate conductive layer, only in the top layer a portion of the gate conductive layer remains on both sides of the channel region as a floating gate; lithography/etching a plurality of fin structures, exposing portions of the substrate implantation region; forming source-drain Touching, and forming a program/erase gate contact connected to the exposed substrate implant region.
其中， 形成多个鳍形结构的步骤进一步包括： 对包括底层、 埋氧 层和顶层的衬底进行掺杂注入， 在埋氧层下方的底层中形成衬底注入 区， 构成编程 /擦除栅； 光刻 /刻蚀衬底， 直至暴露未掺杂的底层， 形成 沿平行于衬底表面的第一方向延伸分布的多个鳍形结构。  The step of forming a plurality of fin structures further includes: performing doping implantation on a substrate including a bottom layer, a buried oxide layer, and a top layer, and forming a substrate implantation region in a bottom layer below the buried oxide layer to form a program/erase gate The lithography/etching of the substrate until the undoped underlayer is exposed forms a plurality of fin structures extending in a first direction parallel to the surface of the substrate.
其中， 光刻 /刻蚀栅极导电层的步骤进一步包括： 在衬底、 栅极导 电层、 栅极绝缘层上形成沿平行于衬底表面的第二方向延伸部分的硬 掩膜图形； 以硬掩膜图形为掩膜， 刻蚀栅极导电层， 仅留下被硬掩膜 图形覆盖的部分栅极导电层， 其中硬掩膜图形下方的顶层构成沟道区， 沟道区两端的顶层构成源漏区。  The step of photolithography/etching the gate conductive layer further includes: forming a hard mask pattern on the substrate, the gate conductive layer, and the gate insulating layer along a second direction extending parallel to the surface of the substrate; The hard mask pattern is used as a mask to etch the gate conductive layer, leaving only a portion of the gate conductive layer covered by the hard mask pattern, wherein the top layer under the hard mask pattern constitutes a channel region, and the top layer at both ends of the channel region Form the source and drain areas.
其中， 暴露部分的衬底注入区的步骤进一步包括： 在整个器件上 形成硬掩膜层； 平坦化直至暴露栅极绝缘层； 光刻 /刻蚀部分的栅极绝 缘层、 顶层、 埋氧层， 直至暴露衬底注入区， 形成编程 /擦除栅接触孔， 其中编程 /擦除栅接触孔位于第一方向上源漏区的一端。  The step of exposing a portion of the substrate implant region further includes: forming a hard mask layer over the entire device; planarizing until the gate insulating layer is exposed; lithography/etching portion of the gate insulating layer, top layer, buried oxide layer Until the substrate implant region is exposed, a program/erase gate contact hole is formed, wherein the program/erase gate contact hole is located at one end of the source and drain regions in the first direction.
其中， 形成源漏接触以及形成连接到暴露的衬底注入区的编程 /擦 除栅接触孔的步骤进一步包括： 在整个器件上形成层间介质层； 光刻 / 刻蚀形成源漏接触孔， 以及连接到暴露的衬底注入区的编程 /擦除栅接 触孔； 在源漏接触孔和编程 /擦除栅接触孔中形成金属硅化物； 在源漏 接触孔和编程 /擦除栅接触孔中填充导电材料， 形成连接线。  Wherein the step of forming a source/drain contact and forming a program/erase gate contact hole connected to the exposed substrate implant region further comprises: forming an interlayer dielectric layer over the entire device; photolithography/etching to form a source/drain contact hole, And a program/erase gate contact hole connected to the exposed substrate implantation region; forming a metal silicide in the source/drain contact hole and the program/erase gate contact hole; at the source/drain contact hole and the program/erase gate contact hole The conductive material is filled to form a connecting line.
其中， 栅极绝缘层包括氧化硅、 氮化硅、 氮氧化硅、 高 k材料及其 组合。  The gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, high k materials, and combinations thereof.
其中， 高 k材料包括选自 Hf02、 HfSiOx、 HfSiON、 HfA10x、 HfTaOx、 HfLaOx、 HfAlSiOx、 HfLaSiOx的铪基材料， 或是包括选自 Zr02、 La203、 LaA103、 Ti02、 Y203的稀土基高 K介质材料， 或是包括 A1203 , 以其上 述材料的复合层。 Wherein, the high-k material comprises a germanium-based material selected from the group consisting of Hf0 2 , HfSiO x , HfSiON, HfA10 x , HfTaO x , HfLaO x , HfAlSiO x , HfLaSiO x , or includes a material selected from the group consisting of Zr0 2 , La 2 0 3 , and LaA10 3 a rare earth-based high-k dielectric material of Ti0 2 , Y 2 0 3 or a composite layer comprising the above materials of A1 2 0 3 .
其中， 浮栅包括多晶硅、 金属、 所述金属的合金、 所述金属的氮 化物及其组合。  Wherein, the floating gate comprises polysilicon, a metal, an alloy of the metal, a nitride of the metal, and a combination thereof.
其中， 所述金属包括 Al、 Ta、 Ti及其组合。  Wherein, the metal comprises Al, Ta, Ti, and combinations thereof.
其中，金属硅化物的材质包括 NiSi2-y、 PtSi2-y、 CoSi2-y、 Ni1-xPtxSi2-y、 Ni1-xCoxSi2-y、 Pt1 -xCoxSi2-y、 Ni2-x-zPtxCozSi3-y, 其中 x、 z大于 0小于 1 , y 大于等于 0小于等于 1。 Among them, the material of the metal silicide includes NiSi 2- y, PtSi 2-y , CoSi 2-y , Ni 1-x Pt x Si 2-y , Ni 1-x Co x Si 2-y , Pt 1 -x Co x Si 2-y , Ni 2-xz Pt x Co z Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.
其中， 连接线的材质包括 W、 Cu、 Al、 Ti、 Ta及其组合。 依照本发明的多次可编程半导体器件及其制造方法， 利用衬底注 入区来形成 FinFET的编程 /擦除栅， 简化了器件结构， 并缩减了制造工 序， 提高了器件的集成密度， 适用于多次可编程存储器。 附图说明 The material of the connecting wire includes W, Cu, Al, Ti, Ta and a combination thereof. According to the multiple-programmable semiconductor device and the method of fabricating the same according to the present invention, the substrate injection region is used to form the program/erase gate of the FinFET, which simplifies the device structure, reduces the manufacturing process, and improves the integration density of the device, and is suitable for Multiple programmable memory. DRAWINGS
以下参照附图来详细说明本发明的技术方案， 其中：  The technical solution of the present invention will be described in detail below with reference to the accompanying drawings, in which:
图 1 A显示了依照本发明的方法步骤 S 1的顶视图，其中在 SOI衬底上 形成沿第一方向延伸的鳍形结构；  Figure 1A shows a top view of method step S1 in accordance with the present invention, wherein a fin structure extending in a first direction is formed on the SOI substrate;
图 1 B为图 1 A中沿线 A A '的剖视图；  Figure 1B is a cross-sectional view taken along line A A ' in Figure 1A;
图 2A显示了依照本发明的方法步骤 S2的顶视图， 其中在鳍形结构 上以及侧面形成栅极绝缘层和栅极导电层；  2A shows a top view of method step S2 in accordance with the present invention, wherein a gate insulating layer and a gate conductive layer are formed on the fin structure and on the sides;
图 2B为图 2A沿线 AA'的剖视图；  Figure 2B is a cross-sectional view taken along line AA' of Figure 2A;
图 2C为图 2A沿线 BB，的剖视图；  Figure 2C is a cross-sectional view taken along line BB of Figure 2A;
图 2D为图 2A沿线 CC'的剖视图；  Figure 2D is a cross-sectional view taken along line CC' of Figure 2A;
图 2E为图 2A沿线 DD'的剖视图；  Figure 2E is a cross-sectional view taken along line DD' of Figure 2A;
图 3 A显示了依照本发明的方法步骤 S 3的顶视图， 其中沿第二方向 形成掩膜并刻蚀栅极绝缘层和栅极导电层；  Figure 3A shows a top view of method step S3 in accordance with the present invention, wherein a mask is formed along the second direction and the gate insulating layer and the gate conductive layer are etched;
图 3B为图 3 A沿线 AA'的剖视图；  Figure 3B is a cross-sectional view taken along line AA' of Figure 3A;
图 3C为图 3A沿线 BB'的剖视图；  Figure 3C is a cross-sectional view taken along line BB' of Figure 3A;
图 3D为图 3A沿线 CC，的剖视图；  Figure 3D is a cross-sectional view taken along line CC of Figure 3A;
图 3E为图 3 A沿线 DD'的剖视图；  Figure 3E is a cross-sectional view taken along line DD' of Figure 3A;
图 4A显示了依照本发明的方法步骤 S4的顶视图， 其中刻蚀形成编 程 /擦除栅接触孔；  4A shows a top view of method step S4 in accordance with the present invention, wherein etching forms a programming/erasing gate contact hole;
图 4B为图 4A沿线 AA，的剖视图；  Figure 4B is a cross-sectional view taken along line AA of Figure 4A;
图 4C为图 4A沿线 BB'的剖视图；  Figure 4C is a cross-sectional view taken along line BB' of Figure 4A;
图 4D为图 4A沿线 CC'的剖视图；  Figure 4D is a cross-sectional view taken along line CC' of Figure 4A;
图 4E为图 4A沿线 DD'的剖视图；  Figure 4E is a cross-sectional view taken along line DD' of Figure 4A;
图 4F为图 4A沿线 EE'的剖视图；  Figure 4F is a cross-sectional view taken along line EE' of Figure 4A;
图 5 A显示了依照本发明的方法步骤 S5的顶视图， 其中形成源漏接 触以及编程 /擦除栅接触；  Figure 5A shows a top view of method step S5 in accordance with the present invention in which source and drain contacts and program/erase gate contacts are formed;
图 5B为图 5A沿线 AA'的剖视图；  Figure 5B is a cross-sectional view taken along line AA' of Figure 5A;
图 5C为图 5A沿线 BB'的剖视图； 图 5D为图 5 A沿线 CC，的剖视图； Figure 5C is a cross-sectional view taken along line BB' of Figure 5A; Figure 5D is a cross-sectional view along line CC of Figure 5A;
图 5E为图 5A沿线 DD'的剖视图；  Figure 5E is a cross-sectional view taken along line DD' of Figure 5A;
图 5F为图 5A沿线 EE，的剖视图； 以及  Figure 5F is a cross-sectional view taken along line EE of Figure 5A;
图 6显示了依照本发明的方法的流程图。 具体实施方式  Figure 6 shows a flow chart of a method in accordance with the present invention. detailed description
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了高密度集成的、 适用于 FinFET技术的多 次可编程半导体器件及其制造方法。 需要指出的是， 类似的附图标记 表示类似的结构， 本申请中所用的术语 "第一" 、 "第二" 、 "上" 、 "下" 等等可用于修饰各种器件结构或工艺步骤。 这些修饰除非特别 说明并非暗示所修饰器件结构或工艺步骤的空间、 次序或层级关系。  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, features of the technical solutions of the present invention and their technical effects will be described in detail with reference to the accompanying drawings in conjunction with the exemplary embodiments, and a high-density integrated multi-time programmable semiconductor device suitable for FinFET technology and a method of fabricating the same are disclosed. It should be noted that like reference numerals indicate similar structures, and the terms "first", "second", "upper", "lower", etc., used in the present application may be used to modify various device structures or process steps. . These modifications are not intended to suggest a spatial, order, or hierarchical relationship to the structure or process steps of the device.
参照图 6以及图 1 A、 图 I B , 显示了依照本发明的方法步骤 S I , 其 中在衬底上形成沿第一方向延伸的多个鳍形结构。 提供半导体衬底， 其材质为绝缘体上硅 （SOI ) , 包括底层 1、 埋氧层 2以及顶层 3。 其中 底层 1与顶层 3材质相同均为硅 （ Si ) , 且顶层 3厚度小于底层 1的厚度。 埋氧层 2材质为顶层 3材质的相应氧化物， 例如为氧化硅（ Si02 ) ， 且埋 氧层 2厚度小于顶层 3的厚度。对半导体衬底进行掺杂注入，依照 PMOS、 NMOS导电类型不同而注入不同类型的掺杂离子。掺杂离子注入的峰值 位于埋氧层 2下方， 例如距离埋氧层 2的底面 1 ~ 10nm， 使得底层 1中的 一部分具有较高的 n+或者 p+的掺杂浓度， 构成底层注入区 1D而利于稍 后用作编程 /擦除栅 （或称为字线） 。 与此同时， 较少部分的掺杂离子 也分布在顶层 3中， 使得顶层 3具有较低的 n-或者 P-的掺杂浓度， 以利于 稍后形成源漏区。在整个器件上通过 LPCVD、 PECVD、 HDPCVD、 ALD 等常规方法沉积盖层 4 , 其材质例如为氮化硅或氮氧化硅， 用于构成鳍 形结构刻蚀的硬掩膜以及后续刻蚀的阻挡层。 光刻并各向异性地刻蚀 盖层 4、 顶层 3、 埋氧层 2以及底层注入区 1 D, 直至暴露未掺杂的底层 1 , 在底层 1上形成沿平行于底层 1表面的第一方向延伸的多个鳍形结构。 刻蚀停止的界面例如位于埋氧层 2底面下方 10 ~ 20nm。 如图 1A所示， 在顶视图中， 多个鳍形结构沿平行于衬底表面的第一方向延伸， 线 AA' 为穿过多个鳍形结构的沿平行于衬底表面的第二方向的剖线， 将作为 FinFET器件的栅极（浮栅）所在位置， 其中第二方向与第一方向相交， 可选地为垂直。 并且以下如果没有明确相反指示， 所有相同标记的剖 线的空间位置均相同。 图 1 B为图 1A沿剖线 AA'截得的剖视图， 其中多 个鳍形结构由上至下依次包括盖层 4、 顶层 3、 埋氧层 2以及底层注入区 1 D。 Referring to Figure 6 and Figures 1 A and IB, a method step SI in accordance with the present invention is shown in which a plurality of fin structures extending in a first direction are formed on a substrate. A semiconductor substrate is provided which is made of silicon-on-insulator (SOI) and includes a bottom layer 1, a buried oxide layer 2, and a top layer 3. The bottom layer 1 and the top layer 3 are all made of silicon (Si), and the thickness of the top layer 3 is smaller than the thickness of the bottom layer 1. The buried oxide layer 2 is made of a corresponding oxide of the top layer 3 material, for example, silicon oxide (Si0 2 ), and the thickness of the buried oxide layer 2 is smaller than the thickness of the top layer 3. The semiconductor substrate is doped and implanted, and different types of dopant ions are implanted according to different types of PMOS and NMOS conductivity. The peak of the doping ion implantation is located below the buried oxide layer 2, for example, 1 to 10 nm from the bottom surface of the buried oxide layer 2, so that a portion of the underlying layer 1 has a higher n+ or p+ doping concentration, which constitutes the underlying implantation region 1D. Used later as a program/erase gate (or called a word line). At the same time, a smaller portion of the dopant ions are also distributed in the top layer 3 such that the top layer 3 has a lower n- or P-doping concentration to facilitate later formation of source and drain regions. The cap layer 4 is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and the material thereof is, for example, silicon nitride or silicon oxynitride, which is used to form a hard mask for fin structure etching and blocking by subsequent etching. Floor. Photolithographically and anisotropically etching the cap layer 4, the top layer 3, the buried oxide layer 2, and the underlying implant region 1 D until the undoped underlayer 1 is exposed, forming a first layer on the underlayer 1 parallel to the surface of the underlayer 1 A plurality of fin structures extending in the direction. The interface where the etching stops is, for example, 10 to 20 nm below the bottom surface of the buried oxide layer 2. As shown in FIG. 1A, in a top view, a plurality of fin structures extend in a first direction parallel to a surface of the substrate, and a line AA' is a second direction parallel to the surface of the substrate passing through the plurality of fin structures. The line of intersection, which will be the position of the gate (floating gate) of the FinFET device, where the second direction intersects the first direction, Optionally vertical. And if there is no clear indication to the contrary below, the spatial positions of the sections of all the same marks are the same. 1B is a cross-sectional view taken along line AA' of FIG. 1A, wherein the plurality of fin structures include a cap layer 4, a top layer 3, a buried oxide layer 2, and an underlying implantation region 1D from top to bottom.
参照图 6以及图 2A至 2E, 显示了依照本发明的方法的步骤 S2 , 其中 在多个鳍形结构的侧面以及顶面形成沿第一方向延伸的栅极绝缘层， 并且在栅极绝缘层两侧形成沿第一方向延伸的栅极导电层。 通过 LPCVD, PECVD、 HDPCVD、 ALD等常规方法在鳍形结构 （4/3/2/1A ) 以及底层 1上沉积栅极绝缘材料， 并光刻 /刻蚀， 仅在鳍形结构顶部以及 侧面留下沿第一方向延伸的栅极绝缘层 5。 栅极绝缘层 5的材质包括氧 化硅、 氮化硅、 氮氧化硅、 高 k材料及其组合。 其中， 高 k材料包括选 自動2、 HfSiOx、 HfSiON , HfA10x、 HfTaOx、 HfLaOx、 HfAlSiOx、 HfLaSiOx的铪基材料， 或是包括选自 Zr02、 La203、 LaA103、 Ti02、 Y203 的稀土基高 K介质材料， 或是包括 A1203 , 以其上述材料的复合层。 优 选地， 选用高 k材料作为栅极绝缘层 5 , 以便适用于小尺寸器件， 使得 能够采用超薄的栅极绝缘层作为隧道氧化层而利用 F-N隧道效应实现 电擦除。 栅极绝缘层 5的厚度例如为 1 ~ 10nm。 随后， 在栅极绝缘层 5 以及底层 1上通过 LPCVD、 PECVD、 HDPCVD、 ALD等常规方法沉积 栅极导电材料， 并光刻 /刻蚀， 仅在栅极绝缘层 5的两侧的衬底底层 1上 留下沿第一方向延伸的栅极导电层 6， 稍后将经过图形化以用作浮栅。 栅极导电层 6的材质包括多晶硅、 金属、 金属的合金、 金属的氮化物及 其组合， 其中， 金属包括 Al、 Ta、 Ti及其组合。 栅极导电层 6的厚度例 如为 l ~ 10nm。 图 2A为顶视图， 其中剖线 AA'与图 1 A中剖线 AA'相同； 剖线 BB，平行于剖线 AA，、 且也沿第二方向， 但是与其具有一定距离， 其位置稍后用作器件的源漏区；剖线 CC，穿过鳍形结构、且沿第一方向， 其位置包括稍后的沟道区以及编程 /擦除栅的连接区； 剖线 DD，未穿过 鳍形结构、 且沿第一方向， 用于对器件的空间结构进行补充说明。 图 2B、 图 2C分别为图 2A沿线 AA'和线 BB，的剖视图， 可见栅极绝缘层 5分 布在衬底底层 1上鳍形结构 （4/3/2/1 A ) 的顶部以及侧面； 栅极导电层 6 分布在衬底底层 1上栅极绝缘层 5的两侧， 并且其顶部低于栅极绝缘层 5 的顶部。 图 2D为图 2A沿线 CC'的剖视图， 可见栅极绝缘层 5位于鳍形结 构顶部， 也沿第一方向延伸分布。 图 2E为图 2A沿线 DD'的剖视图， 可 见在衬底底层 1上鳍形结构区域之外， 没有栅极绝缘层 5和栅极导电层Referring to FIG. 6 and FIGS. 2A to 2E, there is shown a step S2 of the method according to the present invention, wherein a gate insulating layer extending in a first direction is formed on a side surface and a top surface of the plurality of fin structures, and a gate insulating layer is provided A gate conductive layer extending in the first direction is formed on both sides. A gate insulating material is deposited on the fin structure (4/3/2/1A) and the underlayer 1 by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, and photolithography/etching, leaving only on the top and side of the fin structure. A gate insulating layer 5 extending in the first direction. The material of the gate insulating layer 5 includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof. Wherein, the high-k material comprises a germanium-based material selected from the group consisting of: 2 , HfSiO x , HfSiON , HfA10 x , HfTaO x , HfLaO x , HfAlSiO x , HfLaSiO x , or includes Zr0 2 , La 2 0 3 , LaA10 3 , A rare earth-based high-k dielectric material of Ti0 2 , Y 2 0 3 or a composite layer comprising A1 2 0 3 and the above materials. Preferably, a high-k material is selected as the gate insulating layer 5 so as to be suitable for a small-sized device, so that an ultra-thin gate insulating layer can be used as a tunnel oxide layer to realize electrical erasing using FN tunneling. The thickness of the gate insulating layer 5 is, for example, 1 to 10 nm. Subsequently, a gate conductive material is deposited on the gate insulating layer 5 and the underlayer 1 by a conventional method such as LPCVD, PECVD, HDPCVD, ALD, etc., and photolithography/etching is performed only on the substrate underside of the gate insulating layer 5. A gate conductive layer 6 extending in the first direction is left on 1 and will later be patterned to serve as a floating gate. The material of the gate conductive layer 6 includes polysilicon, metal, alloy of metal, nitride of metal, and combinations thereof, wherein the metal includes Al, Ta, Ti, and combinations thereof. The thickness of the gate conductive layer 6 is, for example, 1 to 10 nm. Figure 2A is a top view, wherein the section line AA' is the same as the section line AA' in Figure 1A; the section line BB is parallel to the section line AA, and also in the second direction, but with a certain distance, its position is later Used as the source and drain region of the device; the line CC, passing through the fin structure, and in the first direction, its position including the later channel region and the connection region of the program/erase gate; the cross-line DD, not crossed The fin structure, and in the first direction, is used to supplement the spatial structure of the device. 2B and FIG. 2C are cross-sectional views of FIG. 2A along line AA' and line BB, respectively, showing that the gate insulating layer 5 is distributed on the top and sides of the fin structure (4/3/2/1 A ) on the substrate underlayer 1; The gate conductive layer 6 is distributed on both sides of the gate insulating layer 5 on the underlayer 1 of the substrate, and its top portion is lower than the top of the gate insulating layer 5. 2D is a cross-sectional view taken along line CC' of FIG. 2A, and it can be seen that the gate insulating layer 5 is located at the top of the fin structure and also extends along the first direction. Figure 2E is a cross-sectional view taken along line DD' of Figure 2A, See that there is no gate insulating layer 5 and gate conductive layer outside the fin structure region on the substrate underlayer 1.
6。 6.
参照图 6以及图 3A至图 3E, 显示了依照本发明的方法的步骤 S3， 其 中沿第二方向形成掩膜并刻蚀去除部分栅极绝缘层和栅极导电层， 仅 在掩膜覆盖区域保留部分的栅极绝缘层和栅极导电层。 在整个器件上 通过 LPCVD、 PECVD、 HDPCVD, ALD等常规方法沉积第一硬掩膜材 料， 其材质例如为氧化硅、 氮化硅、 氮氧化硅。 光刻 /刻蚀硬掩膜材料 形成沿第二方向延伸分布的多个第一硬掩膜图案 7， 其中至少一个第一 硬掩膜图案 7穿过剖线 AA，以保留其下方的栅极绝缘层 5和栅极导电层 6 , 用作器件沟道区两侧的绝缘层和浮栅。 然后以第一硬掩膜图案 7作 为掩膜， 各向异性地刻蚀栅极导电层 6 , 使得仅保留位于第一硬掩膜图 案 7下方的栅极导电层 6， 作为浮栅。 图 3A是顶视图， 可见第一硬掩膜 图案 7沿第二方向延伸， 并至少穿过剖线 AA'。 图 3B、 图 3C分别是图 3A 沿线 AA，、 BB，的剖视图， 可见未被第一硬掩膜图案 7覆盖的区域上， 栅极导电层 6被移除。 图 3D、 图 3E分别是图 3A沿线 CC：'、 DD'的剖视图， 其中 AA，线穿过的区域中的顶层 3部分构成沟道区 3C， 其余的顶层 3部 分则构成源漏区 3S/3D, 未来将用作器件的控制部分 （或称为位线） 。  Referring to FIG. 6 and FIG. 3A to FIG. 3E, step S3 of the method according to the present invention is shown, wherein a mask is formed along the second direction and a portion of the gate insulating layer and the gate conductive layer are etched away, only in the mask covering region. A portion of the gate insulating layer and the gate conductive layer are reserved. The first hard mask material is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. The lithographic/etching hard mask material forms a plurality of first hard mask patterns 7 extending along the second direction, wherein at least one of the first hard mask patterns 7 passes through the cross-sectional line AA to retain the gate underneath The insulating layer 5 and the gate conductive layer 6 serve as an insulating layer and a floating gate on both sides of the channel region of the device. Then, the gate conductive layer 6 is anisotropically etched using the first hard mask pattern 7 as a mask so that only the gate conductive layer 6 under the first hard mask pattern 7 remains as a floating gate. Fig. 3A is a top view, showing that the first hard mask pattern 7 extends in the second direction and passes at least through the line AA'. 3B and 3C are cross-sectional views taken along line AA, BB of Fig. 3A, respectively, showing that the gate conductive layer 6 is removed on the region not covered by the first hard mask pattern 7. 3D and 3E are cross-sectional views of FIG. 3A along line CC: ', DD', respectively, wherein AA, the top layer 3 portion of the region through which the line passes constitutes the channel region 3C, and the remaining top portion 3 portion constitutes the source/drain region 3S/ 3D, the future will be used as the control part (or bit line) of the device.
参照图 6以及图 4A至图 4F， 显示了依照本发明的方法的步骤 S4， 其 中刻蚀形成控制栅接触孔。 在整个器件上通过 LPCVD、 PECVD、 HDPCVD、 ALD等常规方法沉积第二硬掩膜层 8 ,其材质例如为氧化硅、 氮化硅或氮氧化硅， 优选地第二硬掩膜层 8与第一硬掩膜层 /图案 7的材 料相同。 然后采用 CMP等工艺平坦化第二硬掩膜层 8直至暴露栅极绝缘 层 5。 然后光刻 /刻蚀部分的第二硬掩膜层 8、 栅极绝缘层 5、 盖层 4、 顶 层 3、 埋氧层 2、 直至暴露底层注入区 1D, 形成多个编程 /擦除栅接触孔 8H。 图 4A为顶视图， 其中剖线 EE'穿过编程 /擦除栅接触孔 8H所在的位 置、 且沿笫二方向， 编程 /擦除栅接触孔 8H沿第一方向延伸。 图 4B、 图 4C分别是图 4A沿线 AA，、 BB，的剖视图， 与图 3B、 3C类似， 可见在未 被原第一硬掩膜图案 7覆盖的区域上， 栅极导电层 6被移除， 而第二硬 掩膜层 8顶部与栅极绝缘层 5顶部齐平。 图 4D是图 4A沿线 CC'的剖视图， 可见编程 /擦除栅接触孔 8H直达底层注入区 1 D, 从而使得作为编程 /擦 除栅的掺杂的底层注入区 1 D能与外部电连接。 图 4E是图 4A沿线 DD，的 剖视图。 图 4F是图 4A沿剖线 EE'的剖视图， 可见在编程 /擦除栅接触孔 8H中， 栅极绝缘层 5的顶部以及侧部的一部分被移除， 而仅保留了在底 层注入区 1 D两侧的部分。 Referring to Figure 6 and Figures 4A through 4F, step S4 of the method in accordance with the present invention is shown wherein etching forms a control gate contact hole. A second hard mask layer 8 is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and is made of, for example, silicon oxide, silicon nitride or silicon oxynitride, preferably a second hard mask layer 8 and The material of a hard mask layer/pattern 7 is the same. The second hard mask layer 8 is then planarized by a process such as CMP until the gate insulating layer 5 is exposed. Then lithographically/etching portions of the second hard mask layer 8, the gate insulating layer 5, the cap layer 4, the top layer 3, and the buried oxide layer 2 until the underlying implant region 1D is exposed to form a plurality of program/erase gate contacts Hole 8H. 4A is a top view in which the cut line EE' passes through the position where the program/erase gate contact hole 8H is located, and in the second direction, the program/erase gate contact hole 8H extends in the first direction. 4B and FIG. 4C are cross-sectional views along line AA, BB, respectively, of FIG. 4A. Similar to FIGS. 3B and 3C, it can be seen that the gate conductive layer 6 is removed on the region not covered by the original first hard mask pattern 7. And the top of the second hard mask layer 8 is flush with the top of the gate insulating layer 5. 4D is a cross-sectional view along line CC' of FIG. 4A, showing that the program/erase gate contact hole 8H is directed to the underlying implant region 1 D such that the doped underlying implant region 1 D as a program/erase gate can be electrically connected to the outside. Figure 4E is a cross-sectional view of Figure 4A taken along line DD. Figure 4F is a cross-sectional view of Figure 4A taken along line EE', visible in the program/erase gate contact hole In 8H, the top portion of the gate insulating layer 5 and a portion of the side portion are removed, and only the portions on both sides of the underlying implantation region 1 D are retained.
参照图 6以及图 5A至图 5F, 显示了依照本发明的方法的步骤 S5 , 其 中形成源漏接触以及编程 /擦除栅接触。 在整个器件上通过 LPC VD、 PECVD、 HDPCVD、 ALD等常规方法沉积层间介质层 9 , 其材质例如为 氧化硅、 氮化硅或氮氧化硅， 优选地与第一硬掩膜层 /图案 7和 /或第二 硬掩膜层 8的材料相同。 光刻 /刻蚀层间介质层 9 , 在与源漏区 3S/3D对应 的位置处形成源漏接触孔 9SD， 而在与编程 /擦除栅接触孔 8H对应的位 置形成编程 /擦除栅接触孔 9P。 然后在各个接触孔中形成金属硅化物 10 以降低接触电阻。 金属硅化物 10的材质包括 NiSi2-y、 PtSi2-y、 CoSi2-y, NiI-xPtxSi2-y、 Ni卜 xCoxSi2-y、 Pti-xCoxSi2-y、 Ni2-x-zPtxCozSi3-y， 其中 x、 z 大于 0小于 1， y大于等于 0小于等于 1。 然后在各个接触孔中填充导电材 料 1 1形成接触塞以及连接线， 导电材料 1 1例如为 W、 Cu、 Al、 Ti、 Ta 及其组合。 图 5A为顶视图， 其中 AA，线穿过沟道区以及沟道区两侧的 栅极绝缘层和栅极导电层， BB，穿过源漏区以及源漏区两侧的栅极绝缘 层， CC，穿过源漏区、 沟道区、 编程 /擦除栅接触孔， DD'仅穿过衬底底 层 1 , EE，穿过村底注入区 1 D。 图 5B为图 5A沿 AA，的剖视图， 可见在沟 道区 3C两侧具有栅极绝缘层 5 , 栅极绝缘层 5两侧具有栅极导电层 6 (浮 栅） 。 图 5C为图 5A沿 BB'的剖视图， 可见源漏连接线 1 1 SD (作为器件 单元的位线）通过金属硅化物 10与源漏区 3S/3D电连接， 源漏区两侧仅 有栅极绝缘层 5而没有栅极导电层 6。 图 5D、 图 5E分别为图 5 沿( ( ，、 EE，的剖视图， 可见编程 /擦除栅连接线 1 1C (作为器件单元的字线） 通 过金属硅化物 10而与衬底注入区 1 D电连接， 且衬底注入区 1 D两侧具有 部分的栅极绝缘层 5。 图 5E为图 5 A沿 DD'的剖视图。 Referring to Figure 6 and Figures 5A through 5F, step S5 of the method in accordance with the present invention is shown in which source-drain contacts and program/erase gate contacts are formed. The interlayer dielectric layer 9 is deposited on the entire device by conventional methods such as LPC VD, PECVD, HDPCVD, ALD, etc., and is made of, for example, silicon oxide, silicon nitride or silicon oxynitride, preferably with the first hard mask layer/pattern 7 And/or the material of the second hard mask layer 8 is the same. The photolithography/etching interlayer dielectric layer 9 forms a source/drain contact hole 9SD at a position corresponding to the source/drain region 3S/3D, and forms a program/erase gate at a position corresponding to the program/erase gate contact hole 8H. Contact hole 9P. Metal silicide 10 is then formed in each contact hole to lower the contact resistance. The material of the metal silicide 10 includes NiSi 2-y , PtSi 2-y , CoSi 2-y , Ni Ix Pt x Si 2-y , Ni Bu x Co x Si 2-y , Pti - x Co x Si 2- y Ni 2-xz Pt x Co z Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1. The conductive material 11 is then filled in each contact hole to form a contact plug and a connecting line, such as W, Cu, Al, Ti, Ta, and combinations thereof. 5A is a top view, wherein AA, the line passes through the channel region and the gate insulating layer and the gate conductive layer on both sides of the channel region, BB, through the source and drain regions and the gate insulating layers on both sides of the source and drain regions , CC, through the source and drain regions, the channel region, the program/erase gate contact hole, DD' only passes through the substrate underlayer 1, EE, through the village implant region 1 D. 5B is a cross-sectional view along line AA of FIG. 5A, and it can be seen that a gate insulating layer 5 is provided on both sides of the channel region 3C, and a gate conductive layer 6 (floating gate) is provided on both sides of the gate insulating layer 5. 5C is a cross-sectional view along line BB' of FIG. 5A, showing that the source-drain connection line 1 1 SD (as a bit line of the device unit) is electrically connected to the source and drain regions 3S/3D through the metal silicide 10, and only the gates are provided on both sides of the source and drain regions. The pole insulating layer 5 has no gate conductive layer 6. 5D and FIG. 5E are respectively a cross-sectional view of FIG. 5 (( , , EE, seeing the program/erase gate connection line 1 1C (as a word line of the device unit) through the metal silicide 10 and the substrate implantation region 1 D Electrically connected, and a portion of the gate insulating layer 5 is provided on both sides of the substrate implantation region 1 D. Fig. 5E is a cross-sectional view taken along line DD' of Fig. 5A.
最终得到的多次可编程半导体器件如图 5A至图 5F所示， 包括： 多 个鳍形结构， 位于衬底上， 包括衬底注入区 1 D、 埋氧层 2、 顶层 3以及 可选地盖层 4 , 多个鳍形结构沿平行于村底表面的第一方向延伸分布； 沟道区 3C , 位于多个鳍形结构的顶层 3中； 源漏区 3S/3D, 位于多个鳍 形结构的顶层 3中沟道区 3C两端； 栅极绝缘层 5 , 位于沟道区 3C的顶部 以及侧部， 沿平行于衬底表面的第二方向延伸分布， 第二方向与第一 方向相交并优选地垂直； 浮栅 6 , 位于鳍形结构的第二方向上的两侧， 与栅极绝缘层 5接触； 编程 /擦除栅， 由衬底注入区 1 D构成， 位于沟道 区 3C下方； 层间介质层 9， 覆盖多个鳍形结构、 栅极绝缘层以及浮栅； 源漏接触孔 9SD与编程 /擦除栅接触孔 9P形成在层间介质层 9中， 分别暴 露源漏区 3S/3D以及作为编程 /擦除栅的衬底注入区 1 D; 金属硅化物 10 , 形成在源漏接触孔 9SD与编程 /擦除栅接触孔 9P中； 连接线 1 1， 通过金 属硅化物 10与源漏区 3S/3D以及作为编程 /擦除栅的衬底注入区 1 D电连 接， 其中源漏区连接线 1 1 SD沿第二方向延伸分布。 The resulting multi-programmable semiconductor device, as shown in FIGS. 5A-5F, includes: a plurality of fin structures on the substrate, including a substrate implant region 1 D, a buried oxide layer 2, a top layer 3, and optionally a cover layer 4, a plurality of fin structures extending in a first direction parallel to the bottom surface of the substrate; a channel region 3C located in the top layer 3 of the plurality of fin structures; a source/drain region 3S/3D located in the plurality of fins The top layer 3 of the structure has two ends of the channel region 3C; the gate insulating layer 5 is located at the top and the side of the channel region 3C, and extends in a second direction parallel to the surface of the substrate, and the second direction intersects the first direction And preferably perpendicular; the floating gate 6 is located on both sides in the second direction of the fin structure, in contact with the gate insulating layer 5; the program/erase gate is formed by the substrate implantation region 1 D, located in the channel Below the region 3C; the interlayer dielectric layer 9, covering the plurality of fin structures, the gate insulating layer, and the floating gate; the source/drain contact hole 9SD and the program/erase gate contact hole 9P are formed in the interlayer dielectric layer 9, respectively exposed Source/drain region 3S/3D and substrate implantation region 1 D as a program/erase gate; metal silicide 10 is formed in source/drain contact hole 9SD and program/erase gate contact hole 9P; The metal silicide 10 is electrically connected to the source and drain regions 3S/3D and the substrate implantation region 1 D as a program/erase gate, wherein the source and drain region connection lines 1 1 SD are distributed in the second direction.
上述各个部件的具体材质和几何结构参数已在制造方法各个步骤 中详细描述， 此外， 后续制造工艺， 例如字线、 位线的连接， 选择电 路的制造等等， 这些已广为技术人员所熟知， 因此也不再赘述。  The specific material and geometry parameters of the various components described above have been described in detail in the various steps of the fabrication process, and further, subsequent fabrication processes, such as word line, bit line connections, fabrication of select circuits, etc., are well known to those skilled in the art. Therefore, it will not be repeated.
依照本发明的多次可编程半导体器件， 利用衬底注入区来形成 FinFET的编程 /擦除栅， 简化了器件结构， 并缩减了制造工序， 提高了 器件的集成密度， 适用于多次可编程存储器。  The multi-programmable semiconductor device according to the present invention utilizes a substrate implant region to form a FinFET program/erase gate, simplifies device structure, reduces manufacturing processes, and increases device integration density, and is suitable for multiple programmable Memory.
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。  While the invention has been described with respect to the embodiments of the embodiments of the present invention, various modifications and equivalents of the device structure may be made without departing from the scope of the invention. In addition, many modifications may be made to the particular situation or materials without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the specific embodiments disclosed as the preferred embodiments of the invention, and the disclosed device structure and method of manufacture thereof will include all embodiments falling within the scope of the invention. .

Claims

权 利 要 求 Rights request
1. 一种多次可编程半导体器件， 包括： A multi-programmable semiconductor device comprising:
多个鳍形结构， 位于衬底上且沿平行于衬底表面的第一方向延伸 分布， 包括衬底注入区、 埋氧层、 顶层；  a plurality of fin structures on the substrate and extending along a first direction parallel to the surface of the substrate, including a substrate implantation region, a buried oxide layer, and a top layer;
沟道区， 位于多个鳍形结构的顶层中；  a channel region located in a top layer of the plurality of fin structures;
源漏区， 位于多个鳍形结构的顶层中沟道区两端；  a source/drain region located at both ends of the channel region in the top layer of the plurality of fin structures;
栅极绝缘层， 位于沟道区的顶部以及侧部， 沿平行于衬底表面的 第二方向延伸分布；  a gate insulating layer, located at a top portion and a side portion of the channel region, extending in a second direction parallel to the surface of the substrate;
浮栅， 位于多个鳍形结构的第二方向上的两侧；  a floating gate located on both sides of the plurality of fin structures in the second direction;
编程 /擦除栅， 由衬底注入区构成， 位于埋氧层下方。  The program/erase gate is formed by a substrate implant region located below the buried oxide layer.
2. 如权利要求 1的多次可编程半导体器件， 进一步包括：  2. The multi-programmable semiconductor device of claim 1 further comprising:
层间介质层， 覆盖多个鳍形结构、 柵极绝缘层、 浮栅；  An interlayer dielectric layer covering a plurality of fin structures, a gate insulating layer, and a floating gate;
源漏接触孔与控制栅接触孔， 形成在层间介质层中， 分别暴露源 漏区以及作为编程 /擦除栅的衬底注入区；  a source/drain contact hole and a control gate contact hole are formed in the interlayer dielectric layer, respectively exposing the source and drain regions and the substrate implantation region as a program/erase gate;
金属硅化物， 形成在源漏接触孔与编程 /擦除栅接触孔中； 连接线， 通过金属硅化物与源漏区以及作为编程 /擦除栅的衬底注 入区电连接。  A metal silicide is formed in the source/drain contact hole and the program/erase gate contact hole; the connection line is electrically connected to the source and drain regions and the substrate injection region as a program/erase gate through the metal silicide.
3. 如权利要求 1多次可编程半导体器件， 其中， 多个鳍形结构还包 括位于顶层之上的盖层。  3. The multi-programmable semiconductor device of claim 1, wherein the plurality of fin structures further comprise a cap layer over the top layer.
4. 如权利要求 1的多次可编程半导体器件， 其中， 栅极绝缘层包括 氧化硅、 氮化硅、 氮氧化硅、 高 k材料及其组合。  The multi-programmable semiconductor device of claim 1, wherein the gate insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, a high-k material, and combinations thereof.
5. 如权利要求 4的多次可编程半导体器件， 其中， 高 k材料包括选 自動2、 HfSiOx、 HfSiON、 HfA10x、 HfTaOx、 HfLaOx、 HfAlSiOx、 HfLaSiOx的铪基材料， 或是包括选自 Zr〇2、 La203 > LaA103、 Ti02、 Y203 的稀土基高 K介质材料， 或是包括 A1203 , 以其上述材料的复合层。 5. The multi-time programmable semiconductor device as claimed in claim 4, wherein the high-k material selected from the group comprising auto 2, HfSiO x, HfSiON, HfA10 x, HfTaO x, HfLaO x, HfAlSiO x, HfLaSiO x hafnium-based material, or The invention comprises a rare earth-based high-k dielectric material selected from the group consisting of Zr〇 2 , La 2 0 3 >LaA10 3 , Ti0 2 , Y 2 0 3 , or a composite layer comprising A1 2 0 3 and the above materials.
6. 如权利要求 1的多次可编程半导体器件，其中，浮栅包括多晶硅、 金属、 所述金属的合金、 所述金属的氮化物及其组合。  6. The multi-programmable semiconductor device of claim 1 wherein the floating gate comprises polysilicon, a metal, an alloy of said metal, a nitride of said metal, and combinations thereof.
7. 如权利要求 6的多次可编程半导体器件， 其中， 所迷金属包括 Al、 Ta、 Ti及其组合。  7. The multi-programmable semiconductor device of claim 6, wherein the metal comprises Al, Ta, Ti, and combinations thereof.
8. 如权利要求 2的多次可编程半导体器件， 其中， 金属硅化物的材 质包括 NiSi2-y、 PtSi2-y、 CoSi2-y、 Ni xPtxSi2-y、 Ni1-xCoxSi2->,、 Pt xCoxSi2->,、 Ni2-x-zPtxCo2Si3-y, 其中 x、 z大于 0小于 1 , y大于等于 0小于等于 1。 8. The multi-programmable semiconductor device according to claim 2, wherein the material of the metal silicide comprises NiSi 2- y, PtSi 2-y , CoSi 2-y , Ni x Pt x Si 2- y , Ni 1-x Co x Si 2-> ,, Pt x Co x Si 2-> , , Ni 2-xz Pt x Co 2 Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.
9. 如权利要求 2的多次可编程半导体器件， 其中， 连接线的材质包 括\¥、 Cu、 Al、 Ti、 Ta及其组合。  9. The multi-programmable semiconductor device according to claim 2, wherein the material of the connection line comprises \¥, Cu, Al, Ti, Ta, and combinations thereof.
10. 一种多次可编程半导体器件制造方法， 包括步骤：  10. A method of fabricating a multi-programmable semiconductor device, comprising the steps of:
在衬底上形成沿平行于衬底表面的第一方向延伸分布的多个鳍形 结构， 包括村底注入区、 埋氧层、 顶层；  Forming a plurality of fin structures extending along a first direction parallel to the surface of the substrate, including a substrate implantation region, a buried oxide layer, and a top layer;
在多个鳍形结构顶部以及两侧形成栅极绝缘层；  Forming a gate insulating layer on top of and on both sides of the plurality of fin structures;
在栅极绝缘层两侧形成栅极导电层；  Forming a gate conductive layer on both sides of the gate insulating layer;
光刻 /刻蚀栅极导电层， 仅在位于顶层中的沟道区两侧保留部分的 栅极导电层， 作为浮栅；  Photolithography/etching the gate conductive layer, leaving only a portion of the gate conductive layer on both sides of the channel region in the top layer as a floating gate;
光刻 /刻蚀多个鳍形结构， 暴露部分的衬底注入区；  Photolithography/etching a plurality of fin structures, exposing portions of the substrate implantation region;
形成源漏接触， 以及形成连接到暴露的衬底注入区的编程 /擦除栅 接触。  A source/drain contact is formed and a program/erase gate contact is formed that is connected to the exposed substrate implant region.
1 1. 如权利要求 10的多次可编程半导体器件制造方法， 其中， 形成 多个鳍形结构的步骤进一步包括： 对包括底层、 埋氧层和顶层的衬底 进行掺杂注入， 在埋氧层下方的底层中形成衬底注入区， 构成编程 /擦 除栅； 光刻 /刻蚀衬底， 直至暴露未掺杂的底层， 形成沿平行于衬底表 面的第一方向延伸分布的多个鳍形结构。  1 . The method of manufacturing a multiple-programmable semiconductor device according to claim 10, wherein the step of forming the plurality of fin structures further comprises: doping implants on the substrate including the underlayer, the buried oxide layer, and the top layer, in the buried oxide Forming a substrate implant region in the underlayer below the layer to form a program/erase gate; lithography/etching the substrate until the undoped underlayer is exposed, forming a plurality of regions extending in a first direction parallel to the surface of the substrate Fin structure.
12. 如权利要求 10的多次可编程半导体器件制造方法， 其中， 光刻 /刻蚀栅极导电层的步骤进一步包括： 在衬底、 栅极导电层、 栅极绝缘 层上形成沿平行于衬底表面的第二方向延伸部分的硬掩膜图形； 以硬 掩膜图形为掩膜， 刻蚀栅极导电层， 仅留下被硬掩膜图形覆盖的部分 栅极导电层， 其中硬掩膜图形下方的顶层构成沟道区， 沟道区两端的 顶层构成源漏区。  12. The method of fabricating a multiple-programmable semiconductor device according to claim 10, wherein the step of photolithography/etching the gate conductive layer further comprises: forming a parallel on the substrate, the gate conductive layer, and the gate insulating layer a hard mask pattern extending in a second direction of the surface of the substrate; using a hard mask pattern as a mask, etching the gate conductive layer leaving only a portion of the gate conductive layer covered by the hard mask pattern, wherein the hard mask The top layer under the film pattern constitutes a channel region, and the top layer at both ends of the channel region constitutes a source and drain region.
13. 如权利要求 10的多次可编程半导体器件制造方法， 其中， 暴露 部分的村底注入区的步骤进一步包括： 在整个器件上形成硬掩膜层； 平坦化直至暴露栅极绝缘层； 光刻 /刻蚀部分的栅极绝缘层、 顶层、 埋 氧层， 直至暴露衬底注入区， 形成编程 /擦除栅接触孔， 其中编程 /擦除 栅接触孔位于第一方向上源漏区的一端。  13. The method of fabricating a multi-programmable semiconductor device according to claim 10, wherein the step of exposing the portion of the substrate implant region further comprises: forming a hard mask layer over the entire device; planarizing until the gate insulating layer is exposed; Etching/etching a portion of the gate insulating layer, the top layer, and the buried oxide layer until the substrate implant region is exposed to form a program/erase gate contact hole, wherein the program/erase gate contact hole is located in the source and drain regions in the first direction One end.
14. 如权利要求 10的多次可编程半导体器件制造方法， 其中， 形成 源漏接触以及形成连接到暴露的衬底注入区的编程 /擦除栅接触孔的步 骤进一步包括： 在整个器件上形成层间介质层； 光刻 /刻蚀形成源漏接 触孔， 以及连接到暴露的衬底注入区的编程 /擦除栅接触孔； 在源漏接 触孔和编程 /擦除栅接触孔中形成金属硅化物； 在源漏接触孔和编程 / 擦除栅接触孔中填充导电材料， 形成连接线。 14. The multi-programmable semiconductor device manufacturing method of claim 10, wherein the step of forming a source/drain contact and forming a program/erase gate contact hole connected to the exposed substrate implant region further comprises: forming over the entire device Interlayer dielectric layer; photolithography/etching to form source drain a contact hole, and a program/erase gate contact hole connected to the exposed substrate implantation region; forming a metal silicide in the source/drain contact hole and the program/erase gate contact hole; at the source/drain contact hole and programming/erasing The gate contact hole is filled with a conductive material to form a connecting line.
15. 如权利要求 10的多次可编程半导体器件制造方法， 其中， 栅极 绝缘层包括氧化硅、 氮化硅、 氮氧化硅、 高 k材料及其组合。  The multi-programmable semiconductor device manufacturing method according to claim 10, wherein the gate insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, a high-k material, and combinations thereof.
16. 如权利要求 10的多次可编程半导体器件制造方法， 其中， 高 k 材料包括选自 Hf02、 HfSiOx、 HfSiON、 HfA10x、 HiTaOx、 HfLaOx、 HfAlSiOx、 HfLaSiOx的铪基材料， 或是包括选自 Zr02、 La203、 LaA103、 Ti02、 Y203的稀土基高 K介质材料， 或是包括 A1203 , 以其上述材料的 复合层。 16. The multi-time programmable semiconductor device manufacturing method as claimed in claim 10, wherein the high-k material comprises HfO 2, hafnium-based material is selected from HfSiO x, HfSiON, HfA10 x, HiTaO x, HfLaO x, HfAlSiO x, HfLaSiO x of Or a rare earth-based high-k dielectric material selected from the group consisting of Zr0 2 , La 2 0 3 , LaA10 3 , Ti0 2 , Y 2 0 3 , or a composite layer comprising A1 2 0 3 , the above materials.
17. 如权利要求 16的多次可编程半导体器件制造方法， 其中， 浮栅 包括多晶硅、 金属、 所述金属的合金、 所述金属的氮化物及其组合。  17. The method of fabricating a multi-programmable semiconductor device according to claim 16, wherein the floating gate comprises polysilicon, a metal, an alloy of the metal, a nitride of the metal, and a combination thereof.
18. 如权利要求 17的多次可编程半导体器件制造方法， 其中， 所述 金属包括 Al、 Ta、 Ti及其组合。  18. The method of fabricating a multi-programmable semiconductor device according to claim 17, wherein said metal comprises Al, Ta, Ti, and combinations thereof.
19. 如权利要求 14的多次可编程半导体器件制造方法， 其中， 金属 硅化物的材质包括 NiSi2-v、 PtSi2— y、 CoSi2-v、 Ni1-xPtxSi2-v、 Ni1 -xCoxSi2.v、 Pti-xCoxSi2-y, Ni2-x-zPtxCozSi3-y, 其中 x、 z大于 0小于 1 , y大于等于 0小于 等于 1。 19. The method of fabricating a multi-programmable semiconductor device according to claim 14, wherein the material of the metal silicide comprises NiSi 2-v , PtSi 2 — y , CoSi 2-v , Ni 1-x Pt x Si 2-v , Ni 1 -x Co x Si 2 . v , Pti -x Co x Si 2-y , Ni 2- x -z Pt x Co z Si 3-y , wherein x, z are greater than 0 and less than 1, and y is greater than or equal to 0. Equal to 1.
20. 如权利要求 14的多次可编程半导体器件制造方法， 其中， 连接 线的材质包括 W、 Cu、 AI、 Ti、 Ta及其组合。  20. The method of fabricating a multi-programmable semiconductor device according to claim 14, wherein the material of the connection line comprises W, Cu, AI, Ti, Ta, and combinations thereof.
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