WO2014032610A1 - 一种面向cpu流水线的错误恢复电路 - Google Patents

一种面向cpu流水线的错误恢复电路 Download PDF

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Publication number
WO2014032610A1
WO2014032610A1 PCT/CN2013/082643 CN2013082643W WO2014032610A1 WO 2014032610 A1 WO2014032610 A1 WO 2014032610A1 CN 2013082643 W CN2013082643 W CN 2013082643W WO 2014032610 A1 WO2014032610 A1 WO 2014032610A1
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Prior art keywords
error
circuit
signal
error recovery
input
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PCT/CN2013/082643
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English (en)
French (fr)
Inventor
单伟伟
田朝轩
朱肖
郭银涛
茅锦亮
金海坤
孙华芳
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东南大学
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Priority claimed from CN201210319577.XA external-priority patent/CN103678017B/zh
Priority claimed from CN201210574735.6A external-priority patent/CN103019876B/zh
Application filed by 东南大学 filed Critical 东南大学
Priority to US14/442,071 priority Critical patent/US9600382B2/en
Publication of WO2014032610A1 publication Critical patent/WO2014032610A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
    • G06F11/3093—Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G06F11/3062—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/805—Real-time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/85—Active fault masking without idle spares
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to an error recovery circuit for a CPU pipeline, and particularly relates to an error recovery circuit based on on-chip error monitoring, which is oriented to a CPU pipeline application and switchable according to a monitoring result, and belongs to the field of integrated circuit design. Background technique
  • Dynamic voltage frequency regulation relies on monitoring the operating state and performance of the main circuit.
  • the system-level monitoring method is mainly a sensor. This method can reflect the current working condition of the system to a certain extent. However, off-chip monitoring often depends on the accuracy of the sensor, and it is difficult to select a reliable monitoring point, so it is difficult to truly reflect the internal parts of the chip. The actual situation.
  • the method of inserting key elements and copying critical paths inside the chip can more realistically reflect the changes of the global parameters of the chip, but since these copies are not exactly the same as the on-chip environment where the key elements and paths are located, for local parameters, such as local Noise and process fluctuations are not sensitive, so they do not reflect the real situation of the circuit, which greatly affects the effect of voltage regulation.
  • the on-chip monitoring method converts the operation of the circuit in real time by inserting an on-chip monitoring circuit at the end of the critical path of the main circuit of the system chip, and the effects of process deviation, power supply voltage fluctuation, temperature variation, noise, etc. are attributed to the on-chip monitoring circuit on the critical path. Change in delay characteristics. When the voltage drops below the critical threshold voltage of the circuit, the on-chip logic will have timing violations. These timing violations are monitored by the on-chip monitoring circuit, and corresponding error signals are generated as the basis for adjusting the operating voltage regulation module.
  • On-chip monitoring method can monitor the error level of the main circuit during operation in real time, reflect the real impact of global and local disturbance on the circuit, and introduce the error correction mechanism to further release the main circuit design stage to overcome process deviation, operating voltage fluctuation, Temperature fluctuations, environmental noise and other adverse effects affect the reserved voltage margin, and dynamically adjust the operating voltage to optimize power consumption.
  • the circuit's working conditions such as temperature, process, noise, etc.
  • the on-chip monitoring means monitors the timing changes of the circuit in real time, and guides the circuit to dynamically adjust the work. parameter. Only by finding the lowest operating voltage point that satisfies the performance of the system can the voltage or frequency margin reserved for the worst case (Worst Case) in the circuit design be minimized for maximum power gain.
  • the in-situ error recovery method is to use the gated clock method to pause the clock signal of the circuit for one cycle after the on-chip monitoring unit of the circuit detects the timing error, during which the error signal is replaced by the correct signal. Errors generated at each stage of the pipeline in the same cycle can be recovered within one clock cycle of the pause, but for the errors generated in different cycles, the clock signal must be suspended immediately after the error to recover.
  • the on-chip monitoring unit of this error recovery method has a complicated structure, and the power consumption of the monitoring unit itself is high; and when the operating conditions such as the operating voltage, frequency, and temperature cause frequent circuit errors, the CPU clock is required for each erroneous clock cycle. Suspending one cycle waits for the recovery of the error signal, so the cost of recovery is high, which greatly affects the throughput of the system and reduces the power consumption effect.
  • the upper error recovery method is mostly used in the design of the pipeline structure. It also needs to rely on the on-chip monitoring unit. Unlike the in-situ recovery, this recovery method reduces all the errors generated in the same cycle to one error, and on the chip. After the monitoring unit detects the timing error, it does not immediately correct the error, but waits for the completion of the operation of each stage in the pipeline without error, that is, the first-level operation waiting for the error is executed before the pipeline reaches the last stage, and then re-executed. An error occurred to recover the error. When the error instruction is re-executed, the instruction following the instruction is also re-executed.
  • the upper recovery mode can complete a pipeline cycle by one recovery operation (refer to the number of cycles required to fill the full pipeline, N cycles, N is Recovery of all errors in the pipeline stage).
  • This recovery method takes N cycles for a recovery.
  • the system error rate is high and multiple errors occur in the same pipeline cycle, these errors can be recovered by an upper recovery. Therefore, when the system error rate is high, the upper layer error recovery mode has less impact on the system throughput rate, and the power consumption reduction effect is better; but when the system error rate is lower, the recovery cost is higher, and the power consumption effect is lower. Not obvious.
  • the recovery method of the dynamic voltage frequency adjustment circuit is only one of the above two methods, but its system application has a large limitation, and the error rate changes for applications that need to work in a relatively wide frequency range. Larger, single error recovery methods are difficult to optimize system throughput and power consumption.
  • the object of the present invention is to provide an error recovery circuit for a CPU pipeline in response to the limitations of the error recovery method in the existing on-chip monitoring system, which can be based on the system requirements of the circuit after the on-chip monitoring circuit monitors the circuit timing error. Dynamically selecting the error recovery mode of the system and the working state can flexibly switch between the error recovery mode of the in-situ error recovery mode and the upper-layer error recovery mode.
  • the error recovery circuit for the CPU pipeline includes an on-chip monitoring circuit, and an error The error signal statistics module, the voltage frequency control module, the error recovery control module, the in-situ error recovery module, and the upper layer error recovery module.
  • the on-chip monitoring circuit is integrated at each end of the pipeline of the front N-1 stage pipeline of the CPU core having the N-stage pipeline structure, and monitors the timing information of each clock cycle of the working circuit, where N is greater than or equal to 3 and less than 20 An integer; the on-chip monitoring circuit sends the monitored error signal to the error signal statistics module.
  • the error signal statistics module counts the percentage of the number of error signals in a clock cycle as a percentage of the total number of cycles, that is, the error rate R OTOT .
  • Raising and lowering the frequency of the voltage control module controls the system voltage and frequency, while controlling the accuracy of adjustment, the frequency of the voltage control module and the respective error statistics module system state and error rate " ⁇ into said error Recovering the control module; the voltage frequency control module performs adjustment of the system operating voltage and frequency according to the corresponding control signal in the error recovery control module.
  • the error recovery control module has a set comparison threshold rth resh . Ld , and according to the result of the threshold comparison selection mechanism, determining to input the in-situ error recovery mode selection signal to the in-situ error recovery module or input the upper layer error recovery mode selection signal to the upper layer error recovery module, dynamically selecting the in-situ error recovery mode or The upper layer error recovery mode, and the voltage frequency adjustment signal is sent to the voltage frequency control module to guide the adjustment of the system state, and realize dynamic switching of two different error recovery modes.
  • the on-chip monitoring circuit includes a master latch circuit, a slave latch circuit, a shadow latch circuit, an error signal generating circuit, an in-situ error correcting selector, a metastable monitoring circuit, and an error signal integrating circuit;
  • the rising edge and the falling edge of the clock respectively sample the input signal, compare the sampling results, determine whether the circuit has a timing violation, and realize the data replacement function in the original error recovery.
  • the input end of the main latch circuit and the shadow latch circuit is connected to the data input end of the on-chip monitoring circuit; the in-situ data signal to be restored of the main latch circuit is connected with the in-situ recovered data signal of the shadow latch circuit
  • the output signal of the slave latch circuit is respectively connected to the data output terminal, the metastable monitoring circuit input terminal, and the error signal generating circuit input terminal; the delayed sampling data output signal of the shadow latch circuit is connected to the error signal generating circuit
  • the other input terminal; the error signal generating circuit generates a timing monitoring error signal input to the error signal integration circuit input terminal; the metastable monitoring error signal generated by the metastable monitoring circuit is input to the other input terminal of the error signal integration circuit;
  • the output of the signal integration circuit is the error signal
  • the on-chip monitoring circuit includes two input ports and two output ports, which are a data input terminal, an in-situ error recovery control signal input terminal, a data output terminal, and an error signal output terminal.
  • the data input end is connected to the data signal output end of the previous stage pipeline where the on-chip monitoring circuit is inserted;
  • the in-situ error recovery control signal input end is connected to the in-situ error recovery control signal output end of the in-situ error recovery module;
  • the data output end Connected to the data signal input of the downstream stage of the position where the on-chip monitoring circuit is inserted; the error signal output is connected to an error signal transmission integrated circuit input.
  • the error signal transmission integration circuit is composed of N-1 registers and N-2 two-input or gate alternately, which is used for transmitting the error signals generated by the pipeline stages to the subsequent stages and finally integrating into an error signal;
  • One input of the OR gate is connected to the register output, and the other input is connected to the error signal output of the on-chip monitoring circuit.
  • the error signal statistics module includes two counters for respectively calculating the number of cycles in which the CPU operates and the number of error signals.
  • the error recovery control module has three input terminals and three output terminals, respectively an error rate input terminal, a system state input terminal, a comparison threshold input terminal, a voltage frequency adjustment signal output terminal, and an in-situ error recovery mode selection signal output terminal.
  • the upper error recovery mode selects a signal output terminal; wherein, the error rate input terminal, the system state input terminal, and the comparison threshold value input terminal are respectively connected to an 8-bit register input terminal, and the error rate input terminal is connected to the register one, and the system state input terminal is connected To register two, the comparison threshold input is connected to register three; the output of register one and register two are respectively connected to the data input of an 8-bit adder, and the carry input of the adder is set to 0; the adder is connected to the output To the data input of one comparator, the output of register three is connected to the other data input of the comparator; the other three inputs of the comparator are set to 0; the greater than and equal to the output of the comparator is connected to an OR gate, The output of the
  • the error recovery control module generates a corresponding voltage frequency control signal input to the voltage frequency control module when the error is recovered, and the voltage frequency control signal includes a clock control signal and a voltage control signal, and the clock control signal adjusts the clock frequency and the phase.
  • the voltage control signal is used to adjust the operating voltage of the system to cooperate with the re-execution of the instruction or the in-place replacement of the data, the clock control signal and the voltage control.
  • the signals are matched with each other. When there is no timing error in the system, the frequency is raised or the voltage is reduced. When the system has an error signal, the frequency is raised while the voltage is raised, and the system timing error is restored and the system works normally under low power consumption conditions. purpose.
  • the threshold comparison selection mechanism is a comparison comparison parameter 7 and a comparison threshold rth resh .
  • the comparison threshold is the selected threshold value, and the comparison parameter r ref includes the arithmetic sum of the three values (note: fitting the three important influence factors to form a comprehensive influence result), which are the error rate, the operating voltage ratio, and the operating frequency ratio, respectively. .
  • the error rate is the error rate of the system within a certain clock cycle of the error signal statistics module.
  • the working voltage ratio is the ratio of the current working voltage of the circuit to the maximum operating voltage of the circuit.
  • the operating frequency ratio is the current operating frequency and circuit of the circuit. The ratio of the maximum operating frequency.
  • the threshold comparison selection mechanism is established by the following process:
  • the comparison threshold In the design stage of the circuit, according to the adjustment mode of the circuit power management module, the arithmetic sum of the error rate, the working voltage ratio and the working frequency ratio of each working point of the circuit under a certain adjustment step is calculated, which is a comparison parameter, and the upper layer is respectively adopted.
  • the error recovery mode and the in-situ error recovery mode perform error recovery, and the power consumption gains in the two error recovery modes are obtained.
  • the comparison parameter under this working point is the comparison threshold.
  • the threshold rth resh is compared by a programmable method.
  • Ld is set to the error recovery control module.
  • the error recovery control module compares the comparison parameter with the predetermined comparison threshold. If the comparison parameter is greater than or equal to the comparison threshold, the upper error recovery mode is selected. If the comparison parameter is smaller than the comparison threshold, the local error is selected.
  • Recovery method When the comparison parameter 7 exceeds the comparison threshold rth ⁇ Md, the power consumption gain of the upper layer error recovery mode is higher. When the comparison parameter 7 is smaller than the comparison threshold rth resh . When ld , the power loss of the in-situ error recovery mode is higher.
  • the error recovery control module will generate a corresponding voltage frequency control signal according to the corresponding error recovery mode, and the voltage frequency control module adjusts the system operating voltage and frequency to corresponding values to achieve the optimal power consumption effect.
  • the invention has the following beneficial effects:
  • the present invention provides on-line timing monitoring of a CPU core having an N-stage pipeline, finding the lowest possible operating voltage of the circuit, and reducing the operating voltage margin reserved for the circuit in the design phase, thereby greatly reducing circuit power consumption. Improve the energy efficiency of the circuit.
  • the present invention provides two different error recovery methods, one is an in situ error recovery method, and the other is an upper Layer error recovery mode, which can flexibly select the system's error recovery mode according to the system requirements and working conditions of the circuit, and dynamically switch between the two recovery methods.
  • the present invention is more suitable for more applications than a single in-situ error recovery or upper layer error recovery mode, with higher throughput, lower power consumption, and overcomes the upper layer.
  • the limitation of the error recovery method is small, which solves the problem that the single error recovery method has limited system application, low throughput and poor power consumption in a wide operating frequency range.
  • the present invention sets a threshold comparison selection mechanism for switching selection between the two recovery modes.
  • the comparison threshold is the selected threshold value.
  • the three important influencing factors are considered together, that is, the combined error rate, operating voltage ratio and working frequency ratio are converted into the final switching threshold. In this way, the working state of the circuit can be comprehensively considered, so as to better judge the error recovery mode of the circuit to achieve the best low power consumption effect.
  • Figure 1 is a block diagram showing the structure of the present invention
  • FIG. 2 is a structural block diagram of an error recovery circuit in the present invention
  • FIG. 3 is a circuit diagram of an error recovery control module in the present invention.
  • FIG. 4 is a structural block diagram of an on-chip monitoring circuit of the present invention.
  • FIG. 5 is a flowchart of establishing a threshold comparison selection mechanism according to the present invention.
  • Figure 6 is a graph of the function of the comparison parameter r ref (note: where the abscissa is the error rate and the ordinate is the comparison parameter);
  • Figure 7 is the recovery efficiency Erecovery (including the in-situ error recovery efficiency Erecovery-local and upper-layer error recovery efficiency) Erecovery— global )
  • a graph of the function of the comparison parameter r ref (note: where the abscissa is the comparison parameter and the ordinate is the recovery efficiency).
  • the error recovery circuit for the CPU pipeline of the present invention includes an on-chip monitoring circuit 1, an error signal statistics module 2, a voltage frequency control module 3, an error recovery control module 4, and an in-situ error recovery module 5.
  • the upper layer error recovery module 6 the on-chip monitoring circuit 1 is integrated at each end of the pipeline of the front N-1 stage pipeline of the CPU core having the N-stage pipeline structure (where N is a positive integer greater than 3 and less than 20), and the monitoring circuit is monitored.
  • the timing information of each clock cycle generates an error signal; and for the Nth stage pipeline without the on-chip monitoring unit, it is necessary to ensure that the timing is loose at the time of design, making it less prone to error.
  • the specific composition of the error recovery circuit is shown in Figure 2.
  • the on-chip monitoring circuit 1 sends the detected error signal.
  • Error signal statistics module 2 error signal statistics module 2 counts the error rate monitored within a certain clock cycle, including two counters, respectively calculating the number of CPU duty cycles and the number of error signals; error signal statistics module 2 error rate and voltage
  • the system state (operating voltage and operating frequency) of the frequency control module 3 is sent to the error recovery control module 4, and the voltage frequency control module 3 performs system voltage and frequency adjustment according to the corresponding control signals in the error recovery control module 4, and simultaneously controls and adjusts Precision.
  • the error recovery control module 4 has a set comparison threshold r thresh .
  • the error recovery control module 4 sends the voltage frequency adjustment signal of the system to the voltage frequency control module 3 to achieve dynamic adjustment of the system operating state.
  • the on-chip monitoring circuit 1 is structured as shown in FIG. 4, including a master latch circuit, a slave latch circuit, a shadow latch circuit, an error signal generating circuit, an in-situ error correcting selector, a metastable monitoring circuit, and an error signal.
  • the integrated circuit separately samples the input signal on the rising edge and the falling edge of the clock, compares the sampling results, determines whether the circuit has a timing violation, and realizes the data replacement function in the original error recovery.
  • the on-chip monitoring circuit 1 includes two input ports and two output ports, which are a data input terminal, an in-situ error recovery control signal input terminal, a data output terminal, and an error signal output terminal.
  • the input end of the main latch circuit and the shadow latch circuit is connected to the data input end of the on-chip monitoring circuit; the in-situ data signal to be restored of the main latch circuit is connected with the in-situ recovered data signal of the shadow latch circuit
  • the output signal of the slave latch circuit is respectively connected to the data output terminal, the metastable monitoring circuit input terminal, and the error signal generating circuit input terminal; the delayed sampling data output signal of the shadow latch circuit is connected to the error signal generating circuit
  • the other input terminal; the error signal generating circuit generates a timing monitoring error signal input to the error signal integration circuit input terminal; the metastable monitoring error signal generated by the metastable monitoring circuit is input to the other input terminal of the error signal integration circuit;
  • the output of the signal integration circuit is the error signal
  • the connection mode of the on-chip monitoring circuit in the pipeline is as shown in Fig. 1.
  • the data input terminal is connected to the data signal output end of the previous stage pipeline where the on-chip monitoring circuit is inserted; the in-situ error recovery control signal input terminal and the in-situ error recovery
  • the module's in-situ error recovery control signal output terminal is connected; the data output terminal is connected to the data signal input end of the subsequent stage pipeline where the on-chip monitoring circuit is inserted; the error signal output terminal is connected to an error signal transmission integrated circuit input terminal.
  • the error signal transmission integration circuit is composed of N-1 registers and N-2 two-input or gate alternately, which is used for transmitting the error signals generated by the pipeline stages to the subsequent stages and finally integrating into an error signal;
  • One input of the OR gate is connected to the register output, and the other input is connected to the error signal output of the on-chip monitoring circuit. Connected to the end.
  • the circuit diagram of the error recovery control module is shown in Figure 3. It has three inputs and three outputs, which are error rate input, system status input, comparison threshold input, voltage frequency adjustment signal output, and local error. Recovery mode selection signal output terminal, upper layer error recovery mode selection signal output terminal.
  • the error rate input terminal, the system state input terminal, and the comparison threshold input terminal are respectively connected to an 8-bit register input terminal, the error rate input terminal is connected to the register one, the system state input terminal is connected to the register 2, and the comparison threshold input terminal is connected to Register 3; the output of register 1 and register 2 are respectively connected to the data input of an 8-bit adder, the carry input of the adder is set to 0; the sum and output of the adder are connected to the data input of a comparator, the register The output of the three is connected to the other data input of the comparator; the other three inputs of the comparator are set to 0; the greater than and equal to the output of the comparator is connected to an OR gate, and the output of the OR gate is connected to a multiple selection Selector of the device (MUX1); the comparator is smaller than the output connected to another multiplexer (MUX2); the "1" terminal of MUX1 and MUX2 is connected high, the "0" terminal is low; the output of MUX1 The signal is
  • the error recovery selection module 4 includes a threshold comparison selection mechanism, and generates a voltage frequency adjustment signal to guide the voltage frequency control module 3 to dynamically adjust the system operating state; the error recovery control module 4 generates a corresponding voltage frequency adjustment signal input to the error recovery.
  • the voltage frequency control module includes a clock control signal and a voltage control signal, and the clock control signal cooperates with the re-execution of the instruction or the in-place replacement of the data by adjusting the clock frequency and the phase, and the voltage control signal adjusts the operating voltage of the system.
  • the clock control signal and the voltage control signal cooperate with each other. When there is no timing error in the system, the frequency is lowered while the voltage is lowered. When the system has an error signal, the frequency is lowered while the voltage is raised. , to achieve the purpose of restoring system timing errors while working under low power conditions.
  • the voltage frequency control module 3 sends the clock gating signal to the in-situ error recovery module 5, stops the clock signal of the relevant circuit, and the in-situ error recovery module 5 recovers the original error.
  • the control signal is sent to the on-chip monitoring circuit 1 to complete the in-situ replacement of the error signal by the correct signal.
  • the upper layer error recovery module 6 sends the pipeline refresh signal to the pipeline related circuit module, and cooperates with other control modules to complete the upper layer error recovery.
  • the threshold comparison selection mechanism in the error recovery control module 4 is established by the following process: First, the comparison threshold r thresh is found . Ld .
  • the circuit operates in different operating points At each working point, the upper layer error recovery mode and the in-situ error recovery mode are used to restore the circuit working state, and the recovery efficiency when using the two recovery modes is measured, wherein the in-situ error recovery efficiency is E re ⁇ TOry — 1 ⁇ al , the upper layer error recovery efficiency is E re . OTery — g i. ba i. Get recovery efficiency E re .. TOry (in situ error recovery efficiency E re .. TOry — i.. a i and upper layer error Recovery efficiency E recOTery — g i. ba i) vs.
  • the in-situ error recovery efficiency is E re ⁇ TOry — 1 ⁇ al
  • the upper layer error recovery efficiency is E re . OTery — g i. ba i.
  • E re .. TOry in situ error recovery efficiency E re .. TOry — i.. a i
  • comparison parameter r ref the recovery efficiency E re ⁇ very is linear with the comparison parameter r ref , as shown in Figure 7.
  • the comparison parameter exceeds a certain value, The upper-layer error recovery mode has higher power consumption gain.
  • r ref is less than this value, the power loss of the in- situ error recovery mode is higher. This value is the comparison threshold ⁇ ⁇ . ⁇ .
  • the comparison threshold rth resh is selected. After ld , the comparison threshold r thresh will be found in a programmable manner. The ld is set to the error recovery control module 4 as a comparison criterion for selecting an error recovery method. Once the circuit is given, this compares the threshold r thresh . Ld is fixed and does not need to be changed during the work process.
  • the error recovery control module 4 sends the upper layer error recovery mode selection signal to the upper layer recovery mode module 6, and selects the upper layer error recovery mode; if the comparison parameter 7 is smaller than the comparison threshold value ⁇ ⁇ ⁇ ⁇ ⁇ . ⁇ , the error recovery control module 4 sends the in-situ error recovery mode selection signal to the in-situ error recovery module 5 to select the in-situ error recovery mode.
  • the error recovery control module 4 selects a corresponding error recovery mode according to the comparison threshold rtn ⁇ Md, and generates a corresponding voltage control signal and a frequency control signal according to the corresponding error recovery mode, and the power management module 3 adjusts the system operating voltage to corresponding The value of the power consumption is optimal.
  • the present invention selects an appropriate error recovery mode by comparing with a predetermined comparison threshold to obtain the maximum power consumption gain.

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Abstract

本发明公开一种面向CPU流水线的错误恢复电路，包括片上监测电路（1）、错误信号统计模块（2）、电压频率控制模块（3）、错误恢复控制模块（4）、原地错误恢复模块（5）和上层错误恢复模块（6），所述片上监测电路（1）集成在具有N级流水线结构的CPU内核的前N-1级流水线的各级流水线末端，监测工作电路每个时钟周期的时序信息，其中N是大于等于3且小于20的正整数。本发明提供了对具有N级流水线的CPU内核的在线时序监测，寻找电路的最低可能工作电压，减小在设计阶段为电路预留的工作电压余量，从而大幅度降低电路功耗，地提高电路的能效。

Description

一种面向 CPU流水线的错误恢复电路
技术领域
本发明涉及一种面向 CPU流水线的错误恢复电路， 具体涉及一种基于片上错误监测， 面向 CPU流水线应用并根据监测结果可切换的错误恢复电路， 属于集成电路设计领域。 背景技术
随着晶体管尺寸的不断縮小， 单位面积上集成的晶体管数急剧增加， 集成电路的功 耗问题成为和功能、 面积同等重要的考虑因素。 旨在降低电路功耗的动态电压频率调节
(DVFS) 技术， 因其显著地效果， 逐渐成为重要的低功耗技术。
动态电压频率调节依赖于对主电路工作状态和性能的监测。 ***级监测手段主要是 传感器， 这种方法能一定程度地反映***当前工作情况， 但是片外监测往往依赖于传感 器的精度， 且很难选择可靠的监测点， 因而难以真实反映芯片内部各部分的实际情况。 在芯片内部***关键单元和复制关键路径的方法可以较真实地反映芯片内部全局参数的 变化， 但由于这些副本与关键单元和路径所处的片内环境并不完全相同， 对局部参数， 如局部噪声、 工艺波动的变化并不敏感， 因而它们反映出的也不是电路的真实情况， 大 大影响了电压调节的效果。
片上监测方法通过在***芯片主电路关键路径的末端***片上监测电路， 实时监测 电路的工作情况， 将工艺偏差、 电源电压波动、 温度变化、 噪声等因素的影响归结为关 键路径上的片上监测电路延时特性的变化。 当电压降低到电路会出现错误的临界电压以 下时， 片内逻辑就会出现时序违规， 这些时序违规被片上监测电路监测， 就会产生相应 的错误信号， 作为工作电压调节模块的调节依据。 片上监测的方法可以实时监测主电路 在工作时的出错水平， 反映全局和局部扰动对电路的真实影响， 同时通过引入错误纠正 机制， 可进一步释放主电路设计阶段为克服工艺偏差、 工作电压波动、 温度变化、 环境 噪声等不利影响预留的电压余量， 对工作电压进行动态的调节， 从而使功耗达到最优。
基于片上监测的动态电压频率调节技术， 将电路的工作条件， 如温度、 工艺、 噪声 等的变化归结为电路的时序变化， 通过片上监测手段实时监测电路工作的时序变化， 指 导电路动态地调节工作参数。 只有找到满足***性能的最低工作电压点， 才能尽可能地 减小电路设计时为最坏情况 (Worst Case)预留的电压或频率余量，以获得最大的功耗收益。
在动态地寻找***工作任意时刻的最低电压点时， 会让***产生出错的风险， 因此 必须设置一定的错误恢复机制， 在***出错时， 可以帮助其从错误状态中恢复过来。 国 内外实现这种错误恢复的方式主要有两种： 原地错误恢复方式和上层错误恢复方式。 原地错误恢复方式是在电路的片上监测单元监测到时序错误后， 使用门控时钟的方 法， 将电路的时钟信号暂停一个周期， 在此期间用正确的信号取代错误信号输出。 在同 一个周期中流水线各级产生的错误都可以在暂停的一个时钟周期内被恢复， 但是对于不 同周期中产生的错误必须分别在出错后立即暂停时钟信号进行恢复。 这种错误恢复方式 的片上监测单元结构复杂， 监测单元本身的功耗较高； 且对于工作电压、 频率以及温度 等工作条件使电路频繁出错时， 对每个出错的时钟周期， CPU时钟都要暂停一个周期等 待错误信号的恢复， 因此恢复时的代价较高， 极大影响了***的吞吐率且降低功耗效果 不显著。
上层错误恢复方式多用于流水线结构的设计中， 也须借助于片上监测单元， 与原地 恢复不同的是， 这种恢复方式将所有同一个周期中产生的错误都归结为一个错误， 而且 在片上监测单元监测到时序错误后， 并不立即进行改错， 而是等待流水线中没有出错的 各级操作执行完成， 即等待出错的那一级操作随流水线执行至最后一级之前， 然后通过 重新执行出错的指令来恢复错误。 在重新执行出错的指令时， 该指令后面的指令也在重 新执行， 因此上层恢复方式可以通过一次恢复操作完成对一个流水线周期 （指填充满流 水线所要花费的周期数， 为 N个周期， N为流水线级数） 中所有错误的恢复。 这种恢复方 式进行一次恢复要耗费 N个周期， 当***错误率很高， 同一个流水线周期中有多个错误产 生时， 这些错误都可以通过一次上层恢复而得到恢复。 因此在***错误率较高时， 上层 错误恢复方式对***吞吐率的影响更小， 降低功耗的效果更好； 但是当***错误率较低 时， 恢复时的代价较高， 降低功耗效果不明显。
目前动态电压频率调节电路的恢复方式只是单一地使用上面两种方式中的一种， 但 是其***应用具有较大的局限性， 对于需要在比较宽的频率范围内工作的应用， 错误率 的变化较大， 单一的错误恢复方式很难使***的吞吐率和功耗达到最优化。
发明内容
发明目的： 本发明的目的在于针对现有片上监测***中错误恢复方式的局限性， 提 供一种面向 CPU流水线的错误恢复电路， 可以在片上监测电路监测到电路时序错误后， 根 据电路的***需求和工作状态动态地选择***的错误恢复方式， 能够在原地错误恢复方 式和上层错误恢复方式两种错误恢复方式间灵活切换。
技术方案： 本发明所述的面向 CPU流水线的错误恢复电路， 包括片上监测电路、 错 误信号统计模块、 电压频率控制模块、 错误恢复控制模块、 原地错误恢复模块和上层错 误恢复模块。
所述片上监测电路集成在具有 N级流水线结构的 CPU内核的前 N-1级流水线的各级流 水线末端， 监测工作电路每个时钟周期的时序信息， 其中 N是大于等于 3且小于 20的正整 数； 所述片上监测电路将监测到的错误信号送入所述错误信号统计模块。
所述错误信号统计模块统计一段时钟周期内错误信号数量占总的周期数的百分比， 即为错误率 ROTOT。
所述电压频率控制模块控制***工作电压与频率的升高和降低， 同时控制调节的精 度， 所述电压频率控制模块和所述错误统计模块分别将***状态和错误率 „∞送入所述 错误恢复控制模块； 所述电压频率控制模块根据所述错误恢复控制模块中的相应控制信 号进行***工作电压与频率的调节。
所述错误恢复控制模块中有设定好的比较阈值 rthresh。ld， 并根据阈值比较选择机制的 结果， 确定将原地错误恢复方式选择信号输入到原地错误恢复模块或将上层错误恢复方 式选择信号输入到上层错误恢复模块，动态选择原地错误恢复方式或上层错误恢复方式， 并将电压频率调节信号送到所述电压频率控制模块， 指导***状态的调节， 实现两种不 同错误恢复方式的动态切换。
所述片上监测电路中包括主锁存器电路、 从锁存器电路、 影子锁存器电路、 错误信 号产生电路、 原地错误纠正选择器、 亚稳态监测电路和错误信号整合电路； 通过在时钟 上升沿和下降沿分别对输入信号采样， 将采样结果对比， 判断电路是否出现时序违规， 同时实现原地错误恢复时的数据替换功能。 其中主锁存器电路与影子锁存器电路的输入 端与片上监测电路的数据输入端相连； 主锁存器电路的原地待恢复数据信号与影子锁存 器电路的原地恢复数据信号连接到原地错误纠正选择器输入端， 原地错误恢复控制信号 输入端连接到原地错误纠正选择器的另一个输入端； 原地错误纠正选择器的原地恢复数 据输出信号连接到从锁存器电路； 从锁存器电路的输出信号分别连接到数据输出端、 亚 稳态监测电路输入端、 错误信号产生电路输入端； 影子锁存器电路的延迟采样数据输出 信号连接到错误信号产生电路的另一个输入端； 错误信号产生电路产生时序监测错误信 号输入到错误信号整合电路输入端； 亚稳态监测电路产生的亚稳态监测错误信号输入到 错误信号整合电路的另一个输入端； 错误信号整合电路的输出为上监测电路的错误信号 输出端。 所述片上监测电路包括两个输入端口和两个输出端口， 分别为数据输入端、 原地错 误恢复控制信号输入端、 数据输出端和错误信号输出端。 数据输入端与片上监测电路所 ***位置的前一级流水线的数据信号输出端相连； 原地错误恢复控制信号输入端与原地 错误恢复模块的原地错误恢复控制信号输出端相连； 数据输出端与片上监测电路所*** 位置的后一级流水线的数据信号输入端相连； 错误信号输出端与一个错误信号传递整合 电路输入端相连。 错误信号传递整合电路由 N-1个寄存器与 N-2个两输入或门交替连接组 成， 用于将流水线各级产生的错误信号随指令向后级传递并最终整合为一个错误信号； 两输入或门的一个输入端连接寄存器输出端， 另一个输入端与片上监测电路的错误信号 输出端相连。
所述错误信号统计模块包括两个计数器， 分别计算 CPU工作的周期数和错误信号的 数量。
所述错误恢复控制模块具有三个输入端及三个输出端， 分别为错误率输入端、 *** 状态输入端、 比较阈值输入端以及电压频率调节信号输出端、 原地错误恢复方式选择信 号输出端、 上层错误恢复方式选择信号输出端； 其中， 错误率输入端、 ***状态输入端、 比较阈值输入端分别连接到一个 8位寄存器输入端， 错误率输入端连接到寄存器一， *** 状态输入端连接到寄存器二， 比较阈值输入端连接到寄存器三； 寄存器一和寄存器二的 输出端分别连接到一个 8位加法器的数据输入端， 加法器的进位输入端置 0; 加法器的和 输出端连接到一个比较器的数据输入端， 寄存器三的输出端连接到比较器的另一个数据 输入端； 比较器的另外三个输入端置 0; 比较器的大于和等于输出端连接到一个或门， 或 门的输出连接到一个多路选择器 MUX1的选择端； 比较器小于输出端连接到另一个多路 选择器 MUX2； 多路选择器 MUX1和多路选择器 MUX2的 " 1 "端接高电平， "0 "端接低 电平； 多路选择器 MUX1的输出信号为原地错误恢复方式选择信号， 多路选择器 MUX2 的输出信号为上层错误恢复方式选择信号； 错误率输入端、 ***状态输入端、 原地错误 恢复方式选择信号以及上层错误恢复方式选择信号同时还连接到一个状态机， 状态机的 输出为电压频率调节信号。
所述错误恢复控制模块在错误恢复时产生相应的电压频率控制信号输入到所述电压 频率控制模块， 电压频率控制信号中包含时钟控制信号和电压控制信号， 时钟控制信号 通过调节时钟频率和相位来配合指令的重新执行或数据的原地替换， 电压控制信号通过 调节***的工作电压来配合指令的重新执行或数据的原地替换， 时钟控制信号和电压控 制信号相互配合， ***没有时序错误时， 升高频率或者降低电压， ***出现错误信号时， 降低频率的同时升高电压， 达到恢复***时序错误同时使***在较低功耗条件下正常工 作的目的。
所述阈值比较选择机制是比较比较参数 7 和比较阈值 rthresh。ld的大小， 比较参数 7 由公式 rref = ROTOT + Vtemp /Vmax + Ftemp /Fmax得到。 比较阈值是选择的界限值， 比较参数 rref 包括三个数值的算术和 （注： 对三个重要影响因子拟合， 形成综合的影响结果） ， 分别 为错误率、 工作电压比和工作频率比。 其中， 错误率即为错误信号统计模块统计的*** 一定时钟周期内的错误率， 工作电压比是电路的当前工作电压与电路的最大工作电压的 比值， 工作频率比是电路的当前工作频率与电路的最大工作频率的比值。
所述阈值比较选择机制通过以下过程建立：
首先， 找出比较阈值。 在电路的设计阶段， 根据电路电源管理模块的调节方式， 计 算一定调节步长下电路的各工作点的错误率、 工作电压比和工作频率比的算术和， 即为 比较参数， 并分别采用上层错误恢复方式和原地错误恢复方式进行错误恢复， 得到两种 错误恢复方式下的功耗收益。 找出上层错误恢复方式功耗收益大于原地错误恢复方式功 耗收益的工作点， 在此工作点下的比较参数即为比较阈值。 设定比较阈值， 通过可编程 的方式将找出的比较阈值设定到错误恢复控制模块中， 作为选择错误恢复方式的比较标 准。
其次， 选择错误恢复方式。 通过可编程方式将比较阈值 rthresh。ld设定到错误恢复控制 模块中， 错误恢复控制模块通过将比较参数与既定的比较阈值比较， 如果比较参数大于 等于比较阈值则选择上层错误恢复方式， 如果比较参数小于比较阈值则选择原地错误恢 复方式。 当比较参数 7 超过比较阈值 rth^Md时， 上层错误恢复方式的功耗收益较高。 当 比较参数 7 小于比较阈值 rthresh。ld时， 原地错误恢复方式的功耗收益较高。 同时错误恢复 控制模块会根据相应的错误恢复方式产生相应的电压频率控制信号， 电压频率控制模块 调节***工作电压与频率到相应的值， 达到功耗最优的效果。
本发明与现有技术相比， 其有益效果是：
1、本发明提供了对具有 N级流水线的 CPU内核的在线时序监测， 寻找电路的最低可能 工作电压， 减小在设计阶段为电路预留的工作电压余量， 从而大幅度降低电路功耗， 地 提高电路的能效。
2、 本发明提供了两种不同的错误恢复方法， 一种是原地错误恢复方式， 另一种是上 层错误恢复方式， 从而可以根据电路的***需求和工作状态灵活的选择***的错误恢复 方式， 并动态的在两种恢复方法中切换。 当电路工作在比较宽的工作频率范围时， 本发 明比单一的原地错误恢复或者上层错误恢复方式适用于更多的应用场合， 吞吐率更高， 功耗降低的收益更高， 克服了上层错误恢复方式适用范围小的局限， 解决了单一的错误 恢复方式在比较宽的工作频率范围内的***应用场合局限、 吞吐率低和功耗收益不理想 的问题。
3、 本发明设置了阈值比较选择机制， 用于在两种恢复方式中的切换选择。 比较阈值 是选择的界限值， 将三个重要影响因素进行综合考虑， 即综合错误率、 工作电压比和工 作频率比三者的影响， 折算成最终的切换阈值。 这样可以综合考虑电路的工作状态， 从 而更好的判断电路进行何种错误恢复方式才能达到最佳的低功耗效果。
附图说明
图 1为本发明的结构框图；
图 2为本发明中错误恢复电路的结构框图；
图 3为本发明中错误恢复控制模块的电路图；
图 4为本发明中片上监测电路的结构框图；
图 5为本发明阈值比较选择机制建立的流程图；
图 6为比较参数 rref的函数曲线图（注： 其中， 横坐标为错误率， 纵坐标为比较参数）; 图 7为恢复效率 Erecovery (包括原地错误恢复效率 Erecovery— local和上层错误恢复 效率 Erecovery— global ) 对比较参数 rref的函数曲线图 （注： 其中， 横坐标为比较参数， 纵坐标为恢复效率）。
具体实施方式
下面对本发明技术方案进行详细说明，但是本发明的保护范围不局限于所述实施例。 实施例 1 :如图 1所示，本发明面向 CPU流水线的错误恢复电路，包括片上监测电路 1、 错误信号统计模块 2、 电压频率控制模块 3、 错误恢复控制模块 4、 原地错误恢复模块 5和 上层错误恢复模块 6， 片上监测电路 1集成在具有 N级流水线结构的 CPU内核的前 N-1级流 水线的各级流水线末端 （其中 N是大于 3且小于 20的正整数） ， 监测工作电路每个时钟周 期的时序信息， 生成错误信号； 而对于没有添加片上监测单元的第 N级流水线， 需在设计 时保证其时序的宽松， 使其不易出错。
错误恢复电路的具体组成结构如图 2所示， 片上监测电路 1将监测到的错误信号送到 错误信号统计模块 2， 错误信号统计模块 2统计一定时钟周期内监测到的错误率， 包括两 个计数器， 分别计算 CPU工作周期数和错误信号的数量； 错误信号统计模块 2统计的错误 率和电压频率控制模块 3的***状态 （工作电压和工作频率） 送到错误恢复控制模块 4， 电压频率控制模块 3根据错误恢复控制模块 4中的相应控制信号进行***工作电压与频率 的调节， 同时控制调节的精度。 错误恢复控制模块 4中有设定好的比较阈值 rthresh。ld， 并根 据阈值比较选择机制的结果选择将原地错误恢复方式选择信号送到原地错误恢复模块 5 或将上层错误恢复方式选择信号送到上层错误恢复模块 6。 同时， 错误恢复控制模块 4将 ***的电压频率调节信号送到电压频率控制模块 3中， 以实现***工作状态的动态调节。
片上监测电路 1结构如图 4所示， 包括主锁存器电路， 从锁存器电路， 影子锁存器电 路， 错误信号产生电路， 原地错误纠正选择器， 亚稳态监测电路， 错误信号整合电路， 通过在时钟上升沿和下降沿分别对输入信号采样， 将采样结果对比， 判断电路是否出现 时序违规， 同时实现原地错误恢复时的数据替换功能。 片上监测电路 1包括两个输入端口 和两个输出端口， 分别为数据输入端、 原地错误恢复控制信号输入端、 数据输出端和错 误信号输出端。 其中主锁存器电路与影子锁存器电路的输入端与片上监测电路的数据输 入端相连； 主锁存器电路的原地待恢复数据信号与影子锁存器电路的原地恢复数据信号 连接到原地错误纠正选择器输入端， 原地错误恢复控制信号输入端连接到原地错误纠正 选择器的另一个输入端； 原地错误纠正选择器的原地恢复数据输出信号连接到从锁存器 电路； 从锁存器电路的输出信号分别连接到数据输出端、 亚稳态监测电路输入端、 错误 信号产生电路输入端； 影子锁存器电路的延迟采样数据输出信号连接到错误信号产生电 路的另一个输入端； 错误信号产生电路产生时序监测错误信号输入到错误信号整合电路 输入端； 亚稳态监测电路产生的亚稳态监测错误信号输入到错误信号整合电路的另一个 输入端； 错误信号整合电路的输出为上监测电路的错误信号输出端。
片上监测电路在流水线中的连接方式如图 1所示，数据输入端与片上监测电路所*** 位置的前一级流水线的数据信号输出端相连； 原地错误恢复控制信号输入端与原地错误 恢复模块的原地错误恢复控制信号输出端相连； 数据输出端与片上监测电路所***位置 的后一级流水线的数据信号输入端相连； 错误信号输出端与一个错误信号传递整合电路 输入端相连。 错误信号传递整合电路由 N-1个寄存器与 N-2个两输入或门交替连接组成， 用于将流水线各级产生的错误信号随指令向后级传递并最终整合为一个错误信号； 两输 入或门的一个输入端连接寄存器输出端， 另一个输入端与片上监测电路的错误信号输出 端相连。
错误恢复控制模块的电路图如图 3所示， 具有三个输入端及三个输出端， 分别为错误 率输入端、 ***状态输入端、 比较阈值输入端以及电压频率调节信号输出端、 原地错误 恢复方式选择信号输出端、 上层错误恢复方式选择信号输出端。 其中， 错误率输入端、 ***状态输入端、 比较阈值输入端分别连接到一个 8位寄存器输入端， 错误率输入端连接 到寄存器一， ***状态输入端连接到寄存器二， 比较阈值输入端连接到寄存器三； 寄存 器一和寄存器二的输出端分别连接到一个 8位加法器的数据输入端，加法器的进位输入端 置 0; 加法器的和输出端连接到一个比较器的数据输入端， 寄存器三的输出端连接到比较 器的另一个数据输入端； 比较器的另外三个输入端置 0; 比较器的大于和等于输出端连接 到一个或门， 或门的输出连接到一个多路选择器 （MUX1 ) 的选择端； 比较器小于输出 端连接到另一个多路选择器 （MUX2) ； MUX1和 MUX2的 "1"端接高电平， "0"端接低电 平； MUX1的输出信号为原地错误恢复方式选择信号， MUX2的输出信号为上层错误恢复 方式选择信号； 错误率输入端、 ***状态输入端、 原地错误恢复方式选择信号以及上层 错误恢复方式选择信号同时还连接到一个状态机， 状态机的输出为电压频率调节信号。
错误恢复选择模块 4包含阈值比较选择机制，并且生成电压频率调节信号来指导电压 频率控制模块 3对***工作状态动态调节； 错误恢复控制模块 4在错误恢复时会产生相应 的电压频率调节信号输入到电压频率控制模块， 电压频率控制信号中包含时钟控制信号 和电压控制信号， 时钟控制信号通过调节时钟频率和相位来配合指令的重新执行或数据 的原地替换， 电压控制信号通过调节***的工作电压来配合指令的重新执行或数据的原 地替换， 时钟控制信号和电压控制信号相互配合， ***没有时序错误时， 升高频率的同 时降低电压， ***出现错误信号时， 降低频率的同时升高电压， 达到恢复***时序错误 同时较低功耗条件下正常工作的目的。
当选择原地错误恢复方式时， 电压频率控制模块 3会将时钟门控信号送到原地错误恢 复模块 5， 把相关电路的时钟信号停一拍， 原地错误恢复模块 5将原地错误恢复控制信号 送到片上监测电路 1，完成正确信号对错误信号的原地替换。当选择上层错误恢复方式时， 上层错误恢复模块 6将流水线刷新信号送到流水线相关电路模块，并配合其他控制模块完 成上层错误恢复。
如图 5所示， 错误恢复控制模块 4中的阈值比较选择机制通过以下过程建立： 首先， 找出比较阈值 rthresh。ld。 在电路的设计阶段， 假设电路的动态电压调节的步长 为^ ， 电路的动态频率调节的步长为 ^， 电路的动态电压调节的最小工作电压为 ^„， 最大工作电压为 Vmax， 电路的动态频率调节的最小工作频率为 Fmm，最大工作频率为 Fmax。 电路动态调节的工作点分别为 υη*^ 或 ^皿+！^ ， 其中， 0 n=^Vmax-VmmyVstep， 0 ^ ^iF^-F^/F^, 且 n， k均为整数。 比较阈值 rthresh。ld包括错误率 ROTOT、 工作电压比 Vtemp /Vmax和工作频率比 Ftemp /Fmax， 其中， 电路的当前工作电压 Vtemp=Vmm+ *Vstep， 电路的 当前工作频率 = 匪+ ， o^ ^ (ymax-ymm)/ystep , o^j^ iF^-F^/F^ , 且， j 均为整数。 在电路动态调节的各工作点分别计算比较参数 rref = ROTOT + Vtemp /Vmax + Ftemp /Fmax的值。 由于错误率 ROTOT与工作电压比 Vtemp /Vmax成反比关系， 与工作频率比 Ftemp /F 成正比关系， 公式 rref = Rerror + ¼emp /Vmax + Ftemp /Fmax可改与为 ef = Rerror + HI /Rerror + n*ROTOT， 其中， m，n为大于 0的常数， 所以 rref对于错误率 ROTOT的函数曲线在第一象限内具 有最低点， 如图 6所示。 在电路设计阶段， 电路工作在不同的工作点时， 分别在每一个工 作点上使用上层错误恢复方式和原地错误恢复方式去恢复电路工作状态， 同时测量使用 这两种恢复方式时的恢复效率， 其中原地错误恢复效率为 Ere∞TOry— 1∞al， 上层错误恢复效率 为 Ere。OTery— gi。bai。 得到恢复效率 Ere。。TOry (分别为原地错误恢复效率 Ere。。TOry— i。。ai和上层错误恢 复效率 ErecOTery— gi。bai)与比较参数 rref的关系曲线， 恢复效率 Ere∞very与比较参数 rref成线性关 系， 如图 7所示。 当比较参数 超过某一个值时， 上层错误恢复方式的功耗收益较高。 当 rref小于这个数值时，原地错误恢复方式的功耗收益较高。这个值即为比较阈值 ΓΛκΒΐι。ω。
选定好比较阈值 rthresh。ld后， 通过可编程的方式将找出的比较阈值 rthresh。ld设定到错误 恢复控制模块 4中，作为选择错误恢复方式的比较标准。电路一旦给定，此比较阈值 rthresh。ld 就是固定的， 在工作过程中无须更改。
其次， 选择错误恢复方式。 由于错误信号统计模块 2和电源管理模块 3每个时钟周期 都会更新传递到错误恢复控制模块 4的错误率 ROTOT、 工作电压比 Vtemp /Vmax和工作频率比 Ftemp /Fmax, 错误恢复控制模块 4每个时钟周期都会计算当前的比较参数 rref的值， 并将电 路当前工作时的比较参数 7 与既定的比较阈值 rtn^Md比较。如果比较参数 rref大于比较阈 值 rthresh。ld，则错误恢复控制模块 4将上层错误恢复方式选择信号送到上层恢复方式模块 6， 选择上层错误恢复方式； 如果比较参数 7 小于比较阈值 ΓΛκΜΐι。ω， 则错误恢复控制模块 4 将原地错误恢复方式选择信号送到原地错误恢复模块 5， 选择原地错误恢复方式。错误恢 复控制模块 4根据比较阈值 rtn^Md选择相应的错误恢复方式， 同时会根据相应的错误恢复 方式产生相应的电压控制信号和频率控制信号， 电源管理模块 3调节***工作电压到相应 的值， 达到功耗最优的效果。
本发明根据电路的错误率和***状态， 通过和既定的比较阈值进行比较来选择合适 的错误恢复方式， 取得最大的功耗收益。
如上所述， 尽管参照特定的优选实施例已经表示和表述了本发明， 但其不得解释为 对本发明自身的限制。 在不脱离所附权利要求定义的本发明的精神和范围前提下， 可对 其在形式上和细节上作出各种变化。

Claims

权利要求书
1、 一种面向 CPU流水线的错误恢复电路， 包括片上监测电路 （1 ) 、 错误信号统计模 块 （2 ) 、 电压频率控制模块 （3 ) 、 错误恢复控制模块 （4 ) 、 原地错误恢复模块 （5 ) 和上层错误恢复模块 （6 ) ， 其特征在于：
所述片上监测电路 （1 ) 集成在具有 N级流水线结构的 CPU内核的前 N-1级流水线的各 级流水线末端， 监测工作电路每个时钟周期的时序信息， 其中 N是大于等于 3且小于 20的 正整数； 所述片上监测电路 （1 ) 将监测到的错误信号送入所述错误信号统计模块 ( 2) ；
所述错误信号统计模块 （2 ) 统计一段时钟周期内错误信号数量占总的周期数的百分 比， 即为错误率 Re ；
所述电压频率控制模块 （3 ) 控制***工作电压与频率的升高和降低， 同时控制调节 的精度， 所述电压频率控制模块 （3 ) 和所述错误统计模块 （2 ) 分别将***状态和错误 率 ROTOT送入所述错误恢复控制模块 （4) ； 所述电压频率控制模块 （3 ) 根据所述错误恢复 控制模块 （4) 中的相应控制信号进行***工作电压与频率的调节；
所述错误恢复控制模块 （4 ) 中有设定好的比较阈值 Γώκ^1(1， 并根据阈值比较选择机 制的结果， 确定将原地错误恢复方式选择信号输入到原地错误恢复模块 （5 ) 或将上层错 误恢复方式选择信号输入到上层错误恢复模块 （6 ) ， 动态选择原地错误恢复方式或上层 错误恢复方式， 并将电压频率调节信号送到所述电压频率控制模块 （3 ) ， 指导***状态 的调节， 实现两种不同错误恢复方式的动态切换。
2、 根据权利要求 1所述的面向 CPU流水线的错误恢复电路， 其特征在于： 所述片上监 测电路 （1 ) 包括主锁存器电路、 从锁存器电路、 影子锁存器电路、 错误信号产生电路、 原地错误纠正选择器、 亚稳态监测电路和错误信号整合电路； 通过在时钟上升沿和下降 沿分别对输入信号采样， 将采样结果对比， 判断电路是否出现时序违规， 同时实现原地 错误恢复时的数据替换功能； 其中主锁存器电路与影子锁存器电路的输入端与片上监测 电路的数据输入端相连； 主锁存器电路的原地待恢复数据信号与影子锁存器电路的原地 恢复数据信号连接到原地错误纠正选择器输入端， 原地错误恢复控制信号输入端连接到 原地错误纠正选择器的另一个输入端； 原地错误纠正选择器的原地恢复数据输出信号连 接到从锁存器电路； 从锁存器电路的输出信号分别连接到数据输出端、 亚稳态监测电路 输入端、 错误信号产生电路输入端； 影子锁存器电路的延迟采样数据输出信号连接到错 误信号产生电路的另一个输入端； 错误信号产生电路产生时序监测错误信号输入到错误 信号整合电路输入端； 亚稳态监测电路产生的亚稳态监测错误信号输入到错误信号整合 电路的另一个输入端； 错误信号整合电路的输出为上监测电路的错误信号输出端。
3、 根据权利要求 2所述的面向 CPU流水线的错误恢复电路， 其特征在于： 所述片上监 测电路 （1 ) 包括两个输入端口和两个输出端口， 分别为数据输入端、 原地错误恢复控制 信号输入端、 数据输出端和错误信号输出端； 数据输入端与片上监测电路所***位置的 前一级流水线的数据信号输出端相连； 原地错误恢复控制信号输入端与原地错误恢复模 块的原地错误恢复控制信号输出端相连； 数据输出端与片上监测电路所***位置的后一 级流水线的数据信号输入端相连； 错误信号输出端与一个错误信号传递整合电路输入端 相连； 错误信号传递整合电路由 N-1个寄存器与 N-2个两输入或门交替连接组成， 用于将 流水线各级产生的错误信号随指令向后级传递并最终整合为一个错误信号； 两输入或门 的一个输入端连接寄存器输出端， 另一个输入端与片上监测电路的错误信号输出端相 连。
4、 根据权利要求 1所述的面向 CPU流水线的错误恢复电路， 其特征在于： 所述错误信 号统计模块 （2) 包括两个计数器， 分别计算 CPU工作的周期数和错误信号的数量。
5、 根据权利要求 1所述的面向 CPU流水线的错误恢复电路， 其特征在于： 所述错误恢 复控制模块 （4) 具有三个输入端及三个输出端， 分别为错误率输入端、 ***状态输入 端、 比较阈值输入端以及电压频率调节信号输出端、 原地错误恢复方式选择信号输出 端、 上层错误恢复方式选择信号输出端； 其中， 错误率输入端、 ***状态输入端、 比较 阈值输入端分别连接到一个 8位寄存器输入端， 错误率输入端连接到寄存器一， ***状态 输入端连接到寄存器二， 比较阈值输入端连接到寄存器三；
寄存器一和寄存器二的输出端分别连接到一个 8位加法器的数据输入端， 加法器的进 位输入端置 0; 加法器的和输出端连接到一个比较器的数据输入端， 寄存器三的输出端连 接到比较器的另一个数据输入端； 比较器的另外三个输入端置 0; 比较器的大于和等于输 出端连接到一个或门， 或门的输出连接到一个多路选择器 （MUX1 ) 的选择端； 比较器小 于输出端连接到另一个多路选择器 （MUX2 ) ； 多路选择器 （MUX1 ) 和多路选择器 (MUX2) 的 " 1 "端接高电平， "0"端接低电平； 多路选择器 （MUX1 ) 的输出信号为 原地错误恢复方式选择信号， 多路选择器 （MUX2) 的输出信号为上层错误恢复方式选择 信号； 错误率输入端、 ***状态输入端、 原地错误恢复方式选择信号以及上层错误恢复 方式选择信号同时还连接到一个状态机， 状态机的输出为电压频率调节信号。
6、 根据权利要求 1所述的面向 CPU流水线的错误恢复电路， 其特征在于： 所述错误恢 复控制模块 （4 ) 在错误恢复时产生相应的电压频率控制信号输入到所述电压频率控制模 块 （3 ) ， 电压频率控制信号中包含时钟控制信号和电压控制信号， 时钟控制信号通过调 节时钟频率和相位来配合指令的重新执行或数据的原地替换， 电压控制信号通过调节系 统的工作电压来配合指令的重新执行或数据的原地替换， 时钟控制信号和电压控制信号 相互配合， ***没有时序错误时， 升高频率或者降低电压， ***出现错误信号时， 降低 频率的同时升高电压， 达到恢复***时序错误同时使***在较低功耗条件下正常工作的 目的。
7、 根据权利要求 1所述的面向 CPU流水线的错误恢复电路， 其特征在于： 所述阈值比 较选择机制是比较比较参数 rref和比较阈值 rthresh。ld的大小， 比较参数 rref由公式 rref = Rerror +
V emp
Figure imgf000015_0001
I ^ma i^至 'J。
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