WO2014025110A1 - Appareil de commande de dispositifs électriques, et procédé de commande de dispositifs électriques à l'aide de cet appareil - Google Patents

Appareil de commande de dispositifs électriques, et procédé de commande de dispositifs électriques à l'aide de cet appareil Download PDF

Info

Publication number
WO2014025110A1
WO2014025110A1 PCT/KR2013/000961 KR2013000961W WO2014025110A1 WO 2014025110 A1 WO2014025110 A1 WO 2014025110A1 KR 2013000961 W KR2013000961 W KR 2013000961W WO 2014025110 A1 WO2014025110 A1 WO 2014025110A1
Authority
WO
WIPO (PCT)
Prior art keywords
pulse
power
inductor
power device
duty ratio
Prior art date
Application number
PCT/KR2013/000961
Other languages
English (en)
Korean (ko)
Inventor
김재하
하정익
강태욱
Original Assignee
서울대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020120152968A external-priority patent/KR101506069B1/ko
Application filed by 서울대학교 산학협력단 filed Critical 서울대학교 산학협력단
Publication of WO2014025110A1 publication Critical patent/WO2014025110A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Definitions

  • the present invention relates to a power device control device and a power device control method using the same.
  • Switching loss power in power devices such as IGBTs, MOSFETs, and GaN FETs whose gate input impedance mainly consists of capacitance components is expressed by the formula Q * Vdd * f.
  • Q is the total charge required to drive the transistor
  • Vdd is the supply voltage
  • f is the switching frequency of the gate driver. That is, the greater the amount of parasitic capacitance or capacitance electrically connected to the gate, the greater the voltage applied to the gate driver, and the higher the frequency, the higher the power loss.
  • a device for controlling power uses a buffer. Recently, a configuration of controlling a turn-on / turn-off time of a power control device by using a resonant circuit together with a buffer and adjusting a resonant frequency has been proposed.
  • the power transistor When the power transistor is controlled using the above-described CMOS inverter as a buffer, power consumption is large and power consumption cannot be recovered.
  • the turn on / off time of the power control element is determined by the resonance frequency, but the resonance frequency is different from the parasitic inductance and the gate capacitance value of the driven device. As a result, the turn on / turn off time cannot be accurately controlled.
  • the manufacturing cost is high because additional elements are required.
  • the present invention is to solve the above-mentioned disadvantages, one of the object of the present invention is to provide a gate driver and a gate driving method with low energy consumption. Another object of the present invention is to provide a gate driver and a gate driving method capable of accurately controlling the turn-on / turn-off time of a controlled transistor.
  • An apparatus for controlling a power device includes a pulse generator for outputting a pulse having an adjustable duty ratio, a switching unit for connecting a power supply and a ground power source to the output terminal, and the switching unit. And an inductor unit having one end connected to an output terminal of the unit, wherein the power device control device controls a power device connected to the inductor unit by adjusting a duty ratio of the pulse.
  • the power control device device further includes a dead time generating circuit unit for preventing a leakage current of the switching unit.
  • the switching unit comprises a CMOS inverter.
  • the other end of the inductor is connected to the control terminal of the power device.
  • the power device control device controls the power device by converting a current supplied by the power source into a voltage signal using a capacitance of the power device.
  • the pulse generator adjusts the duty of the pulse so that the period connected to the output terminal of the switching unit and the power supply is reduced over time.
  • the inductor unit applies a voltage rising to the power device as the time elapses.
  • the pulse generator adjusts the duty of the pulse so that the period connected to the output terminal of the switching unit and the ground power supply decreases with time.
  • the inductor unit applies a voltage that decreases as the time elapses.
  • the pulse generator adjusts the duty of the pulse linearly.
  • the pulse generator adjusts the duty ratio of the pulse so that the switching unit is connected only to the output terminal of the switching unit and the ground power supply, or only the output terminal and the supply power of the switching unit during a predetermined period (period).
  • the inductor unit applies a constant voltage to the power device during the predetermined time period.
  • the inductor unit includes at least one of at least one inductor and a simulated inductor.
  • a method of controlling a power device comprising: outputting a pulse having an adjustable duty ratio, switching one end of an inductor unit with the pulse, and connecting one of a supply power supply and a ground power supply; and Controlling to control a power device connected to the inductor unit.
  • the duty of the pulse is adjusted so that the period connecting the supply power and the inductor unit decreases with time.
  • the inductor unit applies a voltage rising to the power device as the time elapses.
  • the duty of the pulse is adjusted so that the section connecting the ground power source and the inductor unit decreases with time.
  • the inductor unit applies a voltage that decreases as the time elapses.
  • the duty ratio of the pulse is linearly adjusted over time.
  • the outputting of the pulse having the variable duty ratio may output a pulse by adjusting a duty ratio so as to connect only the inductor unit and the supply power or only connect the inductor unit and the ground power for a predetermined time interval.
  • the inductor unit applies a constant voltage to the power device during the predetermined time period.
  • the power device control apparatus since the energy applied to turn on the power device can be recovered in the process of turning off, energy consumption can be reduced.
  • the power device control apparatus and control method according to an embodiment of the present invention provides an advantage that the power control device can be turned on / off with high precision without being affected by parasitic resistance, parasitic capacitance and parasitic inductance. .
  • FIG. 1 is a block diagram showing an outline of a gate driver configuration according to an embodiment of the present invention.
  • FIG. 3 is a diagram illustrating an embodiment of a switching unit 200.
  • FIG. 4 is a view for explaining a dead time insertion circuit according to an embodiment of the present invention.
  • FIG. 5 is an equivalent circuit for a power control device and a power device according to an embodiment of the present invention.
  • FIG. 6 is a timing diagram of a voltage illustrating a state in which a power device is connected to a control device.
  • FIG. 7 is a diagram illustrating current flow in a P2 section.
  • FIG. 8 is a diagram illustrating a current flow in a P4 section.
  • FIG. 9 is a diagram illustrating a simulation test result.
  • 10 is a diagram showing simulation test results regarding power loss.
  • a gate driver may include a pulse generator capable of adjusting a duty ratio of an output pulse, and a switching unit connecting the output node by switching a supply power and a ground power with the pulse. And an inductor unit having one end connected to an output node of the switching unit, wherein the power device control device controls a power device connected to the inductor unit by adjusting a duty ratio of the pulse. .
  • a power device control apparatus includes a pulse generator 100, and the pulse generator 100 may adjust a duty ratio of an output pulse Vpulse.
  • the pulse generator 100 is driven by receiving an input signal.
  • the input signal is a signal for driving a power device connected to a gate driver according to an embodiment of the present invention. Since the input signal itself is insufficient in voltage level or current amount to directly drive the power control device, the input signal is input to the driving device to provide a driving device. To drive a power device.
  • the power device is a power controlling semiconductor, and includes a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an Insulated Gate Bipolar mode Transistor (IGBT), and a GaN FET (Gallium Nitride Field Effect Transistor).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • IGBT Insulated Gate Bipolar mode Transistor
  • GaN FET GaN Nitride Field Effect Transistor
  • the duty ratio is used in various meanings, but in the present specification, it is defined as meaning the ratio of the high interval H to the period T in pulses having the same period.
  • 2 is a diagram for explaining a duty ratio defined in the present specification.
  • the period of the illustrated pulse is T and the high period H of the pulse corresponds to the half period T / 2
  • the duty ratio of the pulse illustrated in FIG. to be.
  • the period of the pulse shown is T, as in the pulse shown in FIG. 2A.
  • the high period H of the pulse corresponds to T / 3
  • the duty ratio of the pulse shown in FIG. 2B is maintained in the entire region of the pulse. to be.
  • the duty ratio may have a value of 0 or more and 1 or less.
  • the pulse generator 100 may receive an active high signal and output a pulse signal.
  • the pulse generator 100 may include an active low signal, a predetermined digital code, and a predetermined pulse. Can be driven by input.
  • the pulse generator 100 controls the output ratio of the power device control device by adjusting the duty ratio of the output pulse Vpulse.
  • the switching unit 200 is a pulse (Vpulse) output from the pulse generator 100 to switch the power supply and the ground power is connected to the output terminal.
  • 3 is a diagram illustrating an embodiment of a switching unit 200.
  • the switching unit 200 according to an embodiment of the present invention receives a pulse Vpulse having a predetermined duty ratio output by the pulse generator 100 and supplies an output node x of the switching unit. Connect to the power supply (Vdd) or to the ground power supply. Therefore, the potential Vx of the switching unit output node x is equal to the potential of the supply power when connected to the supply power, and equal to the ground power when connected to the ground power supply. In one embodiment, as shown in FIG.
  • the switching unit 200a connects the output node x to the supply power when the pulse Vpulse is high, and grounds the output node x when the pulse is low. Connect with the power. Accordingly, as shown in the timing diagram on the right, the potential Vx of the output node x is synchronized in a non-inverted state with the pulse train output by the pulse generator 100, and the amplitude is increased between the supply power supply Vdd and the ground power supply. Swing
  • the switching unit 200 may be implemented by including a complementary metal oxide semiconductor inverter (CMOS inverter) as shown in FIG. 2B.
  • CMOS inverter complementary metal oxide semiconductor inverter
  • the switching unit 200b including the CMOS inverter since the PMOS switch 212 is turned off in the high state of the pulse Vpulse, and the NMOS switch 214 is turned on, the switching unit 200b The potential of the output node (x) of) is equal to that of the ground power source.
  • the NMOS switch 214 is turned off, and the PMOS switch 212 is turned on, so that the output node x of the switching node 200b is turned off.
  • the potential is equal to the potential Vdd of the power supply.
  • the potential Vx of the output node x of the switching unit 200b is inverted and synchronized with the pulse, and the amplitude is increased between the supply power supply Vdd and the ground power supply. Swing Therefore, the switching unit 200 is synchronized to the pulse output by the pulse generator 100 and outputs a pulse whose amplitude swings between the supply power supply Vdd and the ground power supply.
  • FIG. 4 is a view for explaining the dead time insertion circuit 300 according to an embodiment of the present invention.
  • (Px) is present, a very low impedance conductive path is formed from the supply to the ground supply, resulting in a large leakage current (ic, Crowbar current).
  • the dead time insertion circuit 300 includes a dead time in which both the PMOS switch and the NMOS switch are turned off to the pulse Vpulse output by the pulse generator as shown in FIG. 4B. Insert it. Therefore, there is a dead time at which all switches are turned off between the time points when one switch is turned off and the other switch is turned on, thereby preventing a current (ic) from leaking from the power supply to the ground power source. Can be.
  • inductor unit 400 includes at least one inductor.
  • the inductor according to the present embodiment includes a wire inductor, a planar coil type formed by a metal pattern on an insulating substrate, and a multi-layered coil type formed by a metal pattern and vias on a multilayer substrate. coil type) and the like.
  • the inductor unit may be a simulated inductor consisting of a capacitor and an operational amplifier.
  • FIG. 5 is an equivalent circuit for a power control device and a power device according to an embodiment of the present invention.
  • the other end of the inductor unit 400 is connected to the control end of the power device 500 to be controlled.
  • the power device 500 is generally formed to drive a large current to control large power. Therefore, since the channel width is larger than that of the small signal transistor in order to improve the current driving capability, the gate capacitance value is also larger than that of the small signal transistor.
  • Cg is the gate capacitance of the above-described power device.
  • the power control apparatus controls the power device from the time when the power device 500 is in the off state, and then turn on (turn on), the power device is turned off (turn off) again Describe the process of control.
  • the power device will be described by exemplifying an N-type power control MOSFET.
  • the power device control device P-type power control MOSFET, IGBT, GaN compound power It is also possible to control an element or the like.
  • FIG. 6 is a timing diagram of a voltage illustrating a state in which a power device is connected to a control device.
  • the pulse generator 100 outputs a pulse Vpulse having a duty ratio of 1 to control the power device 500 in an off state. Therefore, since the PMOS switch 212 of the switching unit 200 is turned off and the NMOS switch 214 is turned on, the potential Vx of the switching unit output node x is equal to the potential of the ground power source. In addition, since there is no stored energy in the inductor unit 400 and the capacitor Cg including the energy storage element, the output terminal potential Vout of the power control device is equal to the potential of the ground power source. Accordingly, the power device 500 is in an off state during the P1 period.
  • the pulse generator 100 adjusts the duty of the pulse Vpulse so that the section connected to the output node x and the supply power supply Vdd of the switching unit 200 decreases with time, and outputs the result.
  • the output voltage Vout of the power device control device increases with time to turn on the power device.
  • the pulse generator adjusts to linearly reduce the duty ratio (Duty) of the output pulse (Vpulse). That is, when the pulse Vpulse output by the pulse generator 100 becomes high, the PMOS switch 212 is turned off and the NMOS switch 210 is turned on, so that the NMOS switch is changed as time passes in the P2 section.
  • the energization time of the 210 is shortened, and the energization time of the PMOS switch 212 becomes long.
  • the power device control apparatus enters a steady state through a transient state.
  • the voltage Vout of the output terminal rises, but as it enters the steady state, the voltage Vout of the output terminal converges to a value determined by the following equation.
  • the output voltage Vout reaches the voltage value obtained by multiplying the duty ratio D by the input voltage Vin finally applied in the steady state through the transient state.
  • the amount of temporal change of the current flowing in the inductor unit 400 is proportional to the potential difference V L across the inductor unit.
  • Vdd the potential of the supply power supply
  • Is the potential of the potential. Therefore, in the period in which the PMOS switch 212 is turned on, current flows through the supply power, the PMOS switch 212, and the inductor unit 400 to the capacitor Cg as shown by i1a in FIG. 7.
  • the PMOS switch 212 is turned off and the NMOS switch 214 is turned on, even if the potential of one end of the inductor unit 400 is equal to the potential of the ground power supply, The current is not reversed in direction, and flows current to the capacitor Cg through the ground power source, the NMOS switch 214 and the inductor unit 400 as shown by i1b.
  • Equation 2 The amount of temporal change of the current i1a flowing through the inductor in the section in which the PMOS switch 212 in the P2 section is turned on is described by Equation 2 below.
  • the molecule on the right side of the equation (2) is Vdd-Vout, and since the charge is not accumulated in the capacitor in the period in which the PMOS switch 212 is first turned on in the initial period of the P2 interval, the voltage Vout across the capacitor Cg is zero.
  • the numerator of the right side of Equation 2 is Vdd, and the temporal change of the current is Corresponds to Subsequently, the direction of the current in the section in which the PMOS switch 212 is turned off and the NMOS switch 214 is turned on is the same as i1b as described above, but the magnitude of the current decreases. This is because as the NMOS switch is turned on, the potential at one end of the inductor unit becomes equal to the ground potential, and the potential across the inductor is reversed.
  • the NMOS switch 212 is turned off and the PMOS switch 214 is turned on.
  • the numerator on the right side of Equation 2 which determines the amount of temporal change of current in the period in which the PMOS switch 214 of the second period is turned on, is Vdd-Vout and Vout is greater than 0, so small.
  • the pulse generator linearly adjusts the duty ratio of the output pulse (Vpulse). As the duty ratio changes linearly, the magnitude of the current I L flowing through the inductor varies between Imax and Imin, but the average value Iavg remains constant as shown. When a current having a constant average value is applied to the capacitor Cg, the voltage Vout at both ends of the capacitor is determined according to Equation 3 below.
  • the voltage Vout formed across the capacitor has a linear shape.
  • the pulse generator outputs a linearly reduced duty of the pulse
  • the duty of the pulse output by the switching unit 200 including the CMOS inverter increases linearly.
  • a linearly increasing output voltage Vout can be applied.
  • the duty ratio of Vpulse is shown in the form of a straight line, but this is for concise, clear explanation and easy understanding.
  • the duty ratio of Vpulse is kept constant for the period of one pulse applied by the pulse generator 100, and the reduced duty ratio compared to the duty ratio of the previous pulse is maintained for the period of the next pulse. That is, the duty ratio of the Vpulse in the P2 section has the form of falling stairs, and the width of the falling decreases linearly with time. However, for the sake of brevity and clear explanation and easy understanding, these are illustrated as linear.
  • the pulse generator 100 outputs a pulse Vpulse having a zero duty ratio. Since the switching unit 200 only turns on the PMOS switch 212 during the P3 period, the potential Vx of the switching unit output node outputs a DC voltage equal to the potential Vdd of the power supply. Accordingly, the power device 500 is controlled to be in an on state during the P3 period, and the capacitor Cg connected to the supply power through the inductor is charged to the supply power supply potential Vdd.
  • the pulse generator 100 adjusts the duty of the pulse Vpulse so that the section connected to the output node x and the supply power supply Vdd of the switching unit 200 increases with time, and outputs the result.
  • the output voltage Vout of the power device control device decreases with time to turn off the power device.
  • the pulse generator 100 adjusts to linearly increase the duty ratio (Duty) of the output pulse (Vpulse). That is, when the pulse Vpulse output by the pulse generator 100 becomes high, the PMOS switch 212 is turned off and the NMOS switch 210 is turned on, so as the time passes within the P4 section, the NMOS switch is turned on.
  • the energization time of 212 becomes long, and the energization time of the PMOS switch 214 becomes short.
  • the output voltage Vout of the power device control apparatus may be adjusted by adjusting the duty ratio of the pulse output by the pulse generator.
  • the current flowing through the inductor unit 400 in the P4 section is described.
  • the current voltage relationship in the inductor unit 400 is shown in Equation 2.
  • the NMOS switch 214 is turned on during the initial period of V4 in the P4 section, the potential of one end of the inductor unit 400 is equal to the potential of the ground power supply, but the capacitor is charged to the potential of the supply power supply (Vdd).
  • the potential is equal to the potential Vdd of the power supply. Therefore, current flows to the inductor unit 400, the NMOS switch 214, and the ground power source as shown by i2a in FIG. 8 in the period where the NMOS switch 214 is turned on.
  • Equation 2 The numerator on the right side of Equation 2 that describes the temporal variation of the current i2a flowing through the inductor in the section where the NMOS switch 212 is turned on in the section P4 is 0-Vout, and the capacitor is charged to Vdd at the beginning of the section P4. Therefore, the molecule on the right side of Equation 2 is -Vdd. That is, it can be seen that the current flows at the same slope as the beginning of the P2 section, and the direction is reversed. Subsequently, the current direction in the section in which the NMOS switch 212 is turned off and the PMOS switch 214 is turned on is the same as i2b as described above, but the current magnitude decreases. This is because, as the PMOS switch 214 is turned on, the potential at one end of the inductor becomes equal to the potential of the power supply, so that the voltage across the inductor is reversed.
  • the PMOS switch 212 is turned off and the NMOS switch 214 is turned on.
  • the capacitor Cg discharges an initially charged charge in the form of a current, so that the potential Vout across the capacitor is It has a reduced value at Vdd. Therefore, since the absolute value of the right-side molecule of Equation 2, which determines the amount of temporal change of current in the period in which the PMOS switch 214 of the second period is turned on, is smaller than Vdd, the amount of change with time of the current is changed in the initial period. It is smaller than the temporal change of the current.
  • the NMOS switch 212 of the first period of the P4 period when the NMOS switch 212 of the first period of the P4 period is turned on, current flows at the most rapid rate of change, and even when the NMOS switch 212 is turned on in the next period, the energy accumulated in the capacitor Cg is discharged. As the potential at both ends decreases, the rate of increase of the current over time is less than the rate of increase of the current flowing in the section where the NMOS switch is turned on in the previous period.
  • the pulse generator linearly adjusts the duty ratio of the output pulse (Vpulse). As the duty ratio changes linearly, the magnitude of the current I L flowing through the inductor varies between I2max and I2min, but the average value I2avg remains constant as shown. As described above, by adjusting the duty ratio of the pulse (Vpulse) linearly to maintain a constant average value of the current flowing through the inductor, and flowing through the capacitor to adjust the voltage Vout formed across the capacitor in a linear form. .
  • the output voltage depends only on the voltage (Vx) and the duty ratio (D) applied to the inductor unit, regardless of the magnitude of the capacitance and the like according to the embodiment of the present invention
  • the device control device provides an advantage of precisely controlling the rise time and fall time of the voltage applied to the power device. Therefore, it is possible to solve the disadvantage that it is impossible to accurately control the turn-on / turn-off time that occurs when conventionally controlling by using the resonance phenomenon, and since the additional element is unnecessary as compared with the case of using the resonance circuit, the power device control device at low cost. It is also provided with the advantage that it can be prepared.
  • the energy charged in the inductor and the capacitor is switched to apply a falling voltage to the control terminal as time passes. Since it is discharged to the power supply again in the switching section, there is no substantial energy consumption.
  • the duty ratio of Vpulse is shown in the form of a straight line, but this is for concise, clear explanation and easy understanding.
  • the duty ratio of Vpulse is kept constant for the period of one pulse applied by the pulse generator 100, and the duty ratio increased compared to the duty ratio of the previous pulse is maintained for the period of the next pulse.
  • the duty ratio of the Vpulse in the P4 section will be in the form of a rising step, and the width of the rising increases linearly with time.
  • these are illustrated as linear.
  • FIG. 6 illustrates a case in which four periods are applied to a pulse having a duty ratio that varies linearly for each section in order to control the power device 500, but this is simple and clear. It is for the purpose of description and not to limit the scope of the present invention. That is, assuming that the P2 section or the P4 section is 10 msec, when 10 cycles of pulses are applied, the frequency of each pulse is 1 msec, so the frequency of the applied pulse is 1 KHz. Similarly, if a pulse period of 100 cycles is applied, the period of each pulse is 1 msec, which is 10 KHz.
  • the frequency of each pulse is 10MHz when 10 pulses are applied, and the frequency of each pulse is 100MHz when 100 pulses are applied and switched.
  • the envelope of the current IL in the P2 section and the P4 section shown in Figure 6 is shown in the form of a straight line, which is shown for simplicity for clarity, in practice, the frequency and pulse of the applied pulse The shape may change depending on the size and the like. For example, according to the test example of the present invention to be described later, the envelope of the current is changed in the form of a quadratic function.
  • a pulse in which the duty ratio changes linearly is applied to the driving section P2 for turning on the power device 500 and / or the driving section P4 for turning off the power device 500. Compared with this, the energy consumption is lower and the power device can be controlled with higher precision.
  • FIG. 9 is a diagram illustrating a simulation test result, and FIG. 9B illustrates a response to a portion corresponding to 5.2usec to 5.5usec of a portion in which the duty ratio changes linearly in FIG. 9A.
  • the simulation results show that the output voltage Vout increases or decreases linearly according to the duty ratio that changes linearly.
  • the inductor current IL maintains the average value completely due to the duty ratio which changes in the ripple component of the current but changes linearly.
  • the power device control device consumes only about 20% of the energy when the gate capacitance is 1 nF. You can see that.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un appareil de commande de dispositifs électriques, comprenant : un générateur d'impulsion émettant une impulsion ayant un rapport de fonctionnement ajustable ; une unité de commutation connectant une tension d'alimentation et une tension de terre à une extrémité de sortie par commutation ; et une unité d'inducteur dont une extrémité est connectée à l'extrémité de sortie de l'unité de commutation. L'appareil de commande des dispositifs électriques ajuste le rapport de fonctionnement de l'impulsion afin de commander un dispositif électrique connecté à l'unité d'inducteur.
PCT/KR2013/000961 2012-08-09 2013-02-07 Appareil de commande de dispositifs électriques, et procédé de commande de dispositifs électriques à l'aide de cet appareil WO2014025110A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2012-0087475 2012-08-09
KR20120087475 2012-08-09
KR10-2012-0152968 2012-12-26
KR1020120152968A KR101506069B1 (ko) 2012-08-09 2012-12-26 전력 소자 제어 장치 및 이를 이용한 전력 소자 제어 방법

Publications (1)

Publication Number Publication Date
WO2014025110A1 true WO2014025110A1 (fr) 2014-02-13

Family

ID=50068307

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2013/000961 WO2014025110A1 (fr) 2012-08-09 2013-02-07 Appareil de commande de dispositifs électriques, et procédé de commande de dispositifs électriques à l'aide de cet appareil

Country Status (1)

Country Link
WO (1) WO2014025110A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049561A1 (fr) * 1998-03-24 1999-09-30 The Ohio State Research Foundation Generateur d'impulsions haute tension
JP2004080985A (ja) * 2002-06-17 2004-03-11 Hitachi Ltd 電源装置及びそれを用いたハードディスク装置，ｉｃ
KR20100055672A (ko) * 2008-11-18 2010-05-27 한국전기연구원 직류 고전압 전원 발생장치 및 임펄스 측정기의 응답특성 평가를 위한 고압 교정 파형 발생장치.
KR20110034998A (ko) * 2009-09-29 2011-04-06 (주)제이디에이테크놀로지 승압형 직류/직류 변환기
US20110084736A1 (en) * 2009-10-12 2011-04-14 Cyclos Semiconductor, Inc. Architecture for controlling clock characteristics

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049561A1 (fr) * 1998-03-24 1999-09-30 The Ohio State Research Foundation Generateur d'impulsions haute tension
JP2004080985A (ja) * 2002-06-17 2004-03-11 Hitachi Ltd 電源装置及びそれを用いたハードディスク装置，ｉｃ
KR20100055672A (ko) * 2008-11-18 2010-05-27 한국전기연구원 직류 고전압 전원 발생장치 및 임펄스 측정기의 응답특성 평가를 위한 고압 교정 파형 발생장치.
KR20110034998A (ko) * 2009-09-29 2011-04-06 (주)제이디에이테크놀로지 승압형 직류/직류 변환기
US20110084736A1 (en) * 2009-10-12 2011-04-14 Cyclos Semiconductor, Inc. Architecture for controlling clock characteristics

Similar Documents

Publication Publication Date Title
US11245324B2 (en) Switching converter and a method thereof
US20080285312A1 (en) Phase Compensation Driving Scheme for Synchronous Rectifiers
US20060226819A1 (en) Self-driven scheme for synchronous rectifier
US20190326806A1 (en) Gate drive adapter
US9985626B2 (en) Bidirectional GaN switch with built-in bias supply and integrated gate drivers
KR101293811B1 (ko) Ｄｃ-ｄｃ 컨버터, 모듈, 전원 장치 및 전자 기기
CN103023310A (zh) 开关装置及其控制方法
KR20060059996A (ko) 제어 회로 및 공진 드라이버 회로 동작 방법
US11196348B2 (en) Methods and systems of controlling switching frequency of a switching power converter
US8558525B1 (en) Power supply circuit and reuse of gate charge
WO2014171633A1 (fr) Dispositif de pilotage de grille pour un élément de commutation à entrée isolée
CN106712513B (zh) 峰值电流检测电路及功率变换装置
CN113261201A (zh) 用于优化共栅共源放大器关闭的装置
WO2014025110A1 (fr) Appareil de commande de dispositifs électriques, et procédé de commande de dispositifs électriques à l'aide de cet appareil
Hua et al. A 1.2-A dual-output SC DC–DC regulator with continuous gate-drive modulation achieving≤ 0.01-mV/mA cross regulation
TWI810702B (zh) 功率模組
WO2018149098A1 (fr) Circuit continu-continu parallèle multiphase et sa structure de puce
KR20140021466A (ko) 전력 소자 제어 장치 및 이를 이용한 전력 소자 제어 방법
KR101232605B1 (ko) 스위치드 커패시터 컨버터를 이용한 전력 변환 장치 및 방법
JP3696211B2 (ja) パワースイッチング装置
US10819234B2 (en) Switching converter with a self-operated negative boost switch
Ming et al. An up to 10MHz 6.8% minimum duty ratio GaN driver with dual-mos-switches bootstrap and adaptive short-pulse based high-CMTI level shifter achieving 6.05% efficiency improvement
Van Nguyen et al. Design and control of a demagnetization circuit for permanent ON OFF operation in pulse transformer gate driver
US5821803A (en) Method and electronic device for reducing transition time of transistor switching circuits
TWI804034B (zh) 雙極脈衝電壓閘極驅動器、電源電路及操作閘極驅動器總成的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13828487

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13828487

Country of ref document: EP

Kind code of ref document: A1