WO2014021249A1 - Dispositif à semi-conducteur et son procédé de production - Google Patents

Dispositif à semi-conducteur et son procédé de production Download PDF

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Publication number
WO2014021249A1
WO2014021249A1 PCT/JP2013/070442 JP2013070442W WO2014021249A1 WO 2014021249 A1 WO2014021249 A1 WO 2014021249A1 JP 2013070442 W JP2013070442 W JP 2013070442W WO 2014021249 A1 WO2014021249 A1 WO 2014021249A1
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Prior art keywords
electrode
insulating layer
layer
forming
pixel electrode
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PCT/JP2013/070442
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English (en)
Japanese (ja)
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安弘 小原
森永　潤一
原田　光徳
政行 山中
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シャープ株式会社
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an active matrix substrate of a liquid crystal display device or an organic EL display device and a manufacturing method thereof.
  • the semiconductor device includes an active matrix substrate and a display device including the active matrix substrate.
  • An active matrix substrate used in a liquid crystal display device or the like includes a switching element such as a thin film transistor (hereinafter referred to as “TFT”) for each pixel.
  • TFT thin film transistor
  • An active matrix substrate including TFTs as switching elements is called a TFT substrate.
  • amorphous silicon TFT amorphous silicon film as an active layer
  • polycrystalline silicon TFT a polycrystalline silicon film as an active layer
  • Patent Document 1 it has been proposed to use an oxide semiconductor instead of amorphous silicon or polycrystalline silicon as the material of the active layer of the TFT.
  • oxide semiconductor TFT An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT.
  • the oxide semiconductor film can be formed by a simpler process than the polycrystalline silicon film.
  • Patent Document 1 discloses an IPS (In-Plain Switching) type liquid crystal display device.
  • IPS In-Plain Switching
  • a pixel electrode and a drain electrode are connected in a contact hole formed in an interlayer insulating layer.
  • the step shape of the contact hole connecting the pixel electrode and the drain electrode affects the liquid crystal alignment of the liquid crystal layer, causing a display defect. Can be.
  • an embodiment of the present invention is mainly intended to provide a semiconductor device in which display defects are unlikely to occur and a method for manufacturing the same.
  • a semiconductor device includes a substrate, a gate electrode and a pixel electrode formed on the substrate, a first insulating layer formed on the gate electrode and the pixel electrode, and the first insulating layer. And a source electrode and a drain electrode electrically connected to the semiconductor layer, and the drain electrode is interposed through an insulating layer including the first insulating layer.
  • the pixel electrode is disposed on the pixel electrode and connected to the pixel electrode in an opening formed in the insulating layer.
  • the semiconductor device described above includes a conductive layer formed of the same conductive film as the pixel electrode, and the gate electrode is formed on the conductive layer.
  • the semiconductor device described above further includes a second insulating layer formed between the gate electrode and the first insulating layer, and the pixel electrode is formed of the second insulating layer. Formed on top.
  • the above-described semiconductor device further includes a base insulating layer formed on the substrate, and the gate electrode is formed on the base insulating layer.
  • the pixel electrode is formed on the base insulating layer.
  • the above-described semiconductor device further includes a protective layer formed on the source electrode and the drain electrode, and a common electrode that overlaps at least a part of the pixel electrode with the protective layer interposed therebetween.
  • each of the source electrode and the drain electrode has a lower layer and an upper layer formed on the lower layer, and the lower layer is made of a refractory metal nitride.
  • the semiconductor layer is an oxide semiconductor layer.
  • the oxide semiconductor layer contains In, Ga, and Zn.
  • the process of forming electrodes , Formed on the first insulating layer includes the step (f) comprising the step of forming the drain electrode connected to the pixel electrode in the opening.
  • a method of manufacturing a semiconductor device includes a step (a) of preparing a substrate, a step (b) of forming a gate electrode and a pixel electrode on the substrate, and the gate electrode and the pixel electrode.
  • Forming an insulating film on the insulating film, and forming a semiconductor film on the insulating film (c), and patterning the insulating film and the semiconductor film from one photomask by a halftone exposure method A first insulating layer is formed from the insulating film, an opening exposing a part of the pixel electrode is formed in the insulating layer including the first insulating layer, and the first insulating layer is formed from the semiconductor film.
  • Is includes the step (e) comprising the step of forming the drain electrode connected to the pixel electrode in the opening.
  • the step (b) includes a step (b1) of forming a second insulating layer on the gate electrode and a step (b2) of forming the pixel electrode on the second insulating layer. are further included.
  • the step (b) further includes a step (b3) of forming a base insulating layer on the substrate and a step (b4) of forming the gate electrode on the base insulating layer.
  • the step (b4) further includes a step (b5) of forming the pixel electrode on the base insulating layer.
  • a step (g) of forming a protective layer on the source electrode and the drain electrode overlaps at least a part of the pixel electrode with the protective layer interposed therebetween. And (h) forming a common electrode.
  • the semiconductor layer is an oxide semiconductor layer.
  • the oxide semiconductor layer contains In, Ga, and Zn.
  • a semiconductor device in which display defects are unlikely to occur and a manufacturing method thereof are provided.
  • FIG. 1 is a schematic plan view of a TFT substrate 100A according to an embodiment of the present invention
  • (b) is a schematic cross-sectional view of the TFT substrate 100A along the line AA ′ of (a)
  • (C) is a schematic cross-sectional view of the TFT substrate 100A along the BB ′ line in (a)
  • (d) is a schematic cross-sectional view of the TFT substrate 100A along the CC ′ line in (a).
  • FIG. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100A.
  • (A)-(f) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100A, respectively. It is typical sectional drawing of TFT substrate 100B by other embodiment of this invention.
  • FIG. 100B It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100B.
  • A)-(e) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100B, respectively.
  • (A) And (b) is typical sectional drawing of TFT substrate 100C in further another embodiment of this invention. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100C.
  • (A)-(g) is typical sectional drawing for demonstrating an example of the manufacturing method of TFT substrate 100C, respectively.
  • (A) And (b) is typical sectional drawing of TFT substrate 100D in other embodiment of this invention. It is a block diagram for demonstrating an example of the manufacturing method of TFT substrate 100D.
  • FIG. 1 is a schematic plan view of the TFT substrate 200 of the comparative example
  • FIG. 4A is a schematic cross-sectional view of the TFT substrate 200 taken along line BB ′ in FIG. 4A
  • FIG. 3D is a schematic cross-sectional view of the TFT substrate 200 taken along line CC ′ in FIG. It is.
  • the semiconductor device of this embodiment includes an active matrix substrate, various display devices, electronic devices, and the like.
  • the semiconductor device of the embodiment according to the present invention will be described by taking a semiconductor device (TFT substrate) used for a liquid crystal display device as an example.
  • FIG. 1A is a schematic plan view of a TFT substrate 100A according to an embodiment of the present invention.
  • FIG. 1B is a schematic cross-sectional view of the TFT substrate 100A taken along the line A-A ′ of FIG.
  • FIG. 1C is a schematic cross-sectional view of the TFT substrate 100A along the line B-B ′ of FIG.
  • FIG. 1D is a schematic cross-sectional view of the TFT substrate 100A along the line C-C ′ of FIG.
  • v shown in FIG. 1A is an effective opening area.
  • the TFT substrate 100A includes a substrate 2, a gate electrode 4 and a pixel electrode 3 formed on the substrate 2, and a gate electrode 4 and the pixel electrode 3.
  • the insulating layer 5 formed, the semiconductor layer 6 overlapping the gate electrode 4 with the insulating layer 5 interposed therebetween, and the source electrode 7s and the drain electrode 7d electrically connected to the semiconductor layer 6 are provided.
  • the drain electrode 7d is disposed on the pixel electrode 3 through an insulating layer including the insulating layer 5, and is connected to the pixel electrode 3 in an opening 5u formed in the insulating layer.
  • the insulating layer 5 functions as a gate insulating layer.
  • a contact hole (opening 5u) for connecting the drain electrode 7d and the pixel electrode 3 is formed in the insulating layer (gate insulating layer) 5, and for example, the protective layer 8 formed thereon is almost formed. It is formed flat.
  • a contact hole is formed in the interlayer insulating layer, and the vicinity of the contact hole is not flat. For this reason, in the liquid crystal display device disclosed in Patent Document 1, the shape of the contact hole affects the liquid crystal alignment of the liquid crystal layer, which may cause display defects.
  • the protective layer 8 on the contact hole (opening 5u) is formed almost flat, so that the shape of the contact hole affects the liquid crystal alignment. It is difficult to cause display defects.
  • the TFT substrate 100A has a protective layer 8 formed on the source electrode 7s and the drain electrode 7d, and a common electrode 9 that overlaps at least a part of the pixel electrode 3 with the protective layer 8 interposed therebetween.
  • a transparent electrode material for example, ITO (Indium Tin Oxide)
  • ITO Indium Tin Oxide
  • An auxiliary capacitor formed of a transparent material may be referred to as a transparent auxiliary capacitor. Note that the above-described opening 5u is closer to the substrate 2 than the common electrode 9 is.
  • the TFT substrate 100A has source wirings 7 (m) and 7 (m + 1) electrically connected to the source electrode 7s of the corresponding pixel.
  • Source wirings 7 (m) and 7 (m + 1) are formed on the insulating layer 5.
  • the gate wiring 14 is formed between the pixel electrodes 3 (m) and 3 (m + 1) of the adjacent pixels.
  • the pixel electrodes 3 (m) and 3 (m + 1) and the gate wiring 14 are all formed between the substrate 2 and the insulating layer 5. Furthermore, the common electrode 9 is not separated for each pixel.
  • the semiconductor layer 6 is preferably an oxide semiconductor layer.
  • a TFT including an oxide semiconductor layer has high mobility, can reduce the size of the TFT, and can suppress a decrease in the aperture ratio of the pixel.
  • FIG. 16A is a schematic plan view of a TFT substrate 200 of a comparative example.
  • FIG. 16B is a schematic cross-sectional view along the line A-A ′ of FIG.
  • FIG. 16C is a schematic cross-sectional view along the line B-B ′ in FIG.
  • FIG. 16D is a schematic cross-sectional view along the line C-C ′ in FIG.
  • the pixel electrode 3 (m) is formed on the insulating layer 5, and the drain electrode 7d is formed so as to be in contact with a part of the upper surface of the pixel electrode 3 (m).
  • the TFT substrate 200 does not have the opening 5u formed in the insulating layer 5, and the drain electrode 7d and the pixel electrode 3 (m) are not connected in the opening 5u.
  • the source wirings 7 (m) and 7 (m + 1) and the pixel electrode 3 (m) are formed on the gate insulating layer 5, and the adjacent source wiring 7 A pixel electrode 3 (m) is formed between (m) and 7 (m + 1).
  • the pixel electrodes 3 (m) and 3 (m + 1) are formed on the insulating layer 5 formed on the gate wiring.
  • the distance between the gate wiring 14 and the pixel electrodes 3 (m) and 3 (m + 1) shown in FIG. 1D and the pixel electrode 3 and the source wirings 7 (m) and 7 (7) shown in FIG. m + 1) is 5 ⁇ m or more. This is because each electrode and wiring are formed in the same layer, and if this distance is not 5 ⁇ m or more, there is a possibility of short-circuiting between the electrodes.
  • the electrodes and the wirings are formed in different layers, even if the electrodes and the wirings are formed to overlap each other by about 1 ⁇ m at the maximum, the possibility of short-circuiting between the electrodes is low.
  • the gate wiring 14 and the pixel electrodes 3 (m) and 3 (3) are formed by forming each electrode and wiring so that the distance between the source wirings 7 (m) and 7 (m + 1) and the pixel electrode 3 is small.
  • the effect of increasing the area of the effective opening region v of the pixel is greater than that of forming each electrode and wiring so that the distance to m + 1) is reduced, and the effect of improving the aperture ratio of the pixel is large.
  • the source wirings 7 (m) and 7 (m + 1) and the pixel electrode 3 are formed in different layers, and the distance between each wiring and the electrode is large. Since each wiring and electrode can be formed so as not to become defective, the effective opening area v (see FIG. 1A) can be made larger than that of the TFT substrate 200, and the aperture ratio of the pixel can be increased.
  • the substrate 2 is typically a transparent substrate, for example, a glass substrate.
  • a plastic substrate can also be used.
  • the plastic substrate includes a substrate formed of a thermosetting resin or a thermoplastic resin, and a composite substrate of these resins and inorganic fibers (for example, glass fibers or glass fiber nonwoven fabrics).
  • the heat-resistant resin material include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic resin, and polyimide resin.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyethersulfone
  • acrylic resin acrylic resin
  • polyimide resin polyimide resin
  • the pixel electrodes 3 (m), 3 (m + 1) and the common electrode 9 are each formed of, for example, a transparent conductive film (for example, an ITO (Indium Tin Oxide) or IZO (registered trademark) (Indium Zinc Oxide) film).
  • the thicknesses of the pixel electrodes 3 (m), 3 (m + 1) and the common electrode 9 are preferably 20 nm or more and 200 nm or less, respectively.
  • Each of the pixel electrodes 3 (m), 3 (m + 1) and the common electrode 9 has a thickness of about 100 nm, for example.
  • the gate electrode 4 is electrically connected to the gate wiring 14.
  • the gate electrode 4 and the gate wiring 14 have, for example, a stacked structure in which an upper layer is a W (tungsten) layer and a lower layer is a TaN (tantalum nitride) layer.
  • the gate electrode 4 and the gate wiring 14 may have a laminated structure formed of Mo (molybdenum) / Al (aluminum) / Mo, and have a single-layer structure, a two-layer structure, a four-layer structure or more. You may have.
  • the gate electrode 4 and the gate wiring 14 are composed of an element selected from Cu (copper), Al, Cr (chromium), Ta (tantalum), Ti (titanium), Mo and W, or these elements.
  • each of the gate electrode 4 and the gate wiring 14 is preferably about 50 nm to 600 nm. Each thickness of the gate electrode 4 and the gate wiring 14 is, for example, about 420 nm.
  • the gate insulating layer 5 is made of, for example, SiO 2 (silicon oxide), SiN x (silicon nitride), SiO x N y (silicon oxynitride, x> y), SiN x O y (silicon nitride oxide, x> y), Al A single layer or a laminate formed of 2 O 3 (aluminum oxide) or tantalum oxide (Ta 2 O 5 ) can be used.
  • the thickness of the gate insulating layer 5 is, for example, not less than about 50 nm and not more than 600 nm.
  • the gate insulating layer 5 is preferably formed using a rare gas such as Ar (argon).
  • the semiconductor layer 6 is preferably an oxide semiconductor layer, for example.
  • the semiconductor layer 6 can be formed at a lower temperature than the silicon-based semiconductor layer. Therefore, the semiconductor layer 6 can be formed on a plastic substrate, for example, and can be applied to a flexible display.
  • the oxide semiconductor layer is formed of, for example, an In—Ga—Zn—O based semiconductor film containing In (indium), Ga (gallium), and Zn (zinc) at a ratio of 1: 1: 1. The ratio of In, G, and Zn can be selected as appropriate.
  • the semiconductor layer 6 may be formed using another oxide semiconductor film instead of the In—Ga—Zn—O-based semiconductor film.
  • Zn—O based semiconductor (ZnO) film Zn—O based semiconductor (ZnO) film, In—Zn—O based semiconductor (IZO) film, Zn—Ti—O based semiconductor (ZTO) film, Cd—Ge—O based semiconductor film, Cd—Pb—O based film
  • ZnO zinc oxide
  • ZTO zinc oxide
  • Cd—Ge—O based semiconductor film Cd—Pb—O based film
  • CdO (cadmium oxide), Mg—Zn—O based semiconductor film, or the like may be used.
  • an oxide semiconductor layer an amorphous ZnO film to which one or a plurality of impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element, Group 17 element and the like are added is added.
  • a state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.
  • the thickness of the semiconductor layer 6 is preferably about 30 nm to 100 nm, for example.
  • the thickness of the semiconductor layer 6 is about 50 nm, for example.
  • the semiconductor layer 6 may be a silicon-based semiconductor layer such as an amorphous silicon (a-Si) layer, a polysilicon (p-Si) layer, or a microcrystalline silicon ( ⁇ -Si) layer.
  • the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1) have, for example, a stacked structure having a lower layer and an upper layer formed on the lower layer.
  • the lower layer and the upper layer are made of different metals.
  • the lower layer is made of, for example, MoN (molybdenum nitride), and the upper layer is made of, for example, Mo.
  • the pixel electrode 3 (m) is formed from a transparent conductive film (for example, an ITO film)
  • the lower layer in contact with the pixel electrode 3 (m) is preferably formed from a refractory metal nitride.
  • the adhesion between the pixel electrode 3 (m) formed from the transparent conductive film and the drain electrode 7d is improved, and the contact resistance between the pixel electrode 3 (m) and the drain electrode 7d can be reduced. Furthermore, it is possible to prevent a change in the state of the surface of the pixel electrode 3 (m) due to the influence of the manufacturing process after the formation of the pixel electrode 3 (m).
  • the source electrode 7s and the drain electrode 7d may have a laminated structure formed of Mo / Al / Mo, and may have a single-layer structure, a two-layer structure, or a laminated structure of four or more layers. .
  • the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1) are composed of an element selected from Al, Cr, Ta, Ti, Mo, and W, or an alloy containing these elements as components. It may be formed from a metal nitride or the like.
  • the thicknesses of the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1) are each preferably about 50 nm to 600 nm.
  • the thickness of the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1) is, for example, about 350 nm.
  • the protective layer 8 is made of, for example, SiN x .
  • the protective layer 8 is formed on the source electrode 7s, the drain electrode 7d, and the source wirings 7 (m) and 7 (m + 1).
  • the protective layer 8 is formed between the common electrode 9 and the pixel electrode 3 (m), for example.
  • an auxiliary capacitor is formed from the transparent common electrode 9 and the pixel electrode 3 (m) and the transparent protective layer 8, a display panel having a high aperture ratio can be manufactured when the TFT substrate 100A is used for the display panel.
  • the thickness of the protective layer 8 is preferably about 50 nm to 300 nm, for example.
  • the thickness of the protective layer 8 is about 200 nm, for example.
  • the protective layer 8 is made of, for example, SiO x N y (silicon oxynitride, x> y), SiN x O y (silicon nitride oxide, x> y), Al 2 O 3 (aluminum oxide) or Ta 2 O 5 ( Tantalum oxide).
  • the TFT substrate 100A is used, for example, in a fringe field switching (FFS) mode liquid crystal display device.
  • FFS fringe field switching
  • the display signal voltage is supplied to the lower pixel electrode, and the common voltage or the counter voltage is supplied to the upper common electrode 9.
  • the common electrode 9 is provided with at least one or more slits 19 (see FIGS. 1A and 1C).
  • FIG. 2 is a block diagram for explaining a manufacturing method of the TFT substrate 100A.
  • FIG. 3A to FIG. 3F are schematic cross-sectional views for explaining a manufacturing method of the TFT substrate 100A.
  • the manufacturing method of the TFT substrate 100A includes a pixel electrode forming step PX, a gate electrode forming step GT, a gate insulating layer / semiconductor layer forming step GI / PS, a source / drain electrode forming step SD, and a protective layer forming.
  • a process PAS and a common electrode formation process CT are provided, and the process proceeds in this order.
  • a conductive film (for example, a transparent conductive film such as an ITO film) is formed on the substrate 2 by sputtering, for example, The conductive film is patterned by wet etching or the like to form the pixel electrode 3.
  • the resist (not shown) used for patterning is peeled off.
  • the gate electrode formation step GT after forming a conductive film on the substrate 2 by, for example, sputtering, the conductive film is formed by photolithography, wet or dry etching, or the like.
  • the gate electrode 4 is formed by patterning. Note that the gate electrode 4 is formed so as not to be electrically connected to the pixel electrode 3. Further, after the gate electrode 4 is patterned, the resist (not shown) used for patterning is peeled off.
  • an insulating film (not shown) is formed on the gate electrode 4 and the pixel electrode 3 by, for example, a CVD (Chemical Vapor Deposition) method.
  • the insulating layer 5 is formed by patterning the insulating film by a photolithography method, a dry etching method, or the like. In the insulating layer 5, an opening 5 u that exposes a part of the pixel electrode 3 is formed. Further, after the insulating layer 5 is patterned, the resist (not shown) used for patterning is peeled off.
  • a semiconductor film (for example, an In—Ga—Zn—O-based semiconductor film) is formed on the insulating layer 5 by, for example, a sputtering method, and this semiconductor film is formed by a photolithography method, a dry etching method, or the like.
  • the semiconductor layer 6 is formed by patterning.
  • the semiconductor layer 6 is formed so as to overlap the gate electrode 4 with the insulating layer 5 interposed therebetween. Further, after the semiconductor layer 6 is patterned, the resist (not shown) used for patterning is peeled off.
  • a conductive film (not shown) is formed on the semiconductor layer 6 by, for example, sputtering, and then by photolithography or wet etching.
  • the conductive film is patterned to form the source electrode 7s and the drain electrode 7d. Further, after the source electrode 7s and the drain electrode 7d are patterned, the resist (not shown) used for patterning is peeled off.
  • the source electrode 7s and the drain electrode 7d are electrically connected to the semiconductor layer 6. Further, the drain electrode 7d is connected to the pixel electrode 3 in the opening 5u.
  • an insulating film (not shown) is formed on the source electrode 7s and the drain electrode 7d by, for example, a CVD method, and a photolithography method, a dry etching method, or the like.
  • this insulating film is patterned to form the protective layer 8.
  • the resist (not shown) used for patterning is peeled off.
  • a conductive film (for example, a transparent conductive film) is formed on the protective layer 8 by sputtering, for example, and photolithography and wet processing are performed.
  • the conductive film is patterned by an etching method or the like to form the common electrode 9. Further, after the common electrode 9 is patterned, the resist (not shown) used for patterning is peeled off.
  • the common electrode 9 is formed so as to overlap a part of the pixel electrode 3 with the insulating layer 5 and the protective layer 8 interposed therebetween.
  • FIG. 1A a plan view of the TFT substrate 100B
  • FIG. 1C which is a cross-sectional view common to the TFT substrate 100B
  • FIG. 4 is a schematic cross-sectional view taken along the line A-A ′ of FIG.
  • Constituent elements common to the TFT substrate 100A are denoted by the same reference numerals to avoid duplication of description.
  • the TFT substrate 100B has a TFT substrate 100A in that a gate electrode 4 (and a gate wiring 14) is formed on a conductive layer 3a formed of the same conductive film as the pixel electrode 3. And different.
  • the gate electrode 4 and the pixel electrode 3 can be formed from one photomask, so the number of photomasks can be reduced and the manufacturing cost can be reduced. Can do.
  • the step (a) of preparing the substrate 2 the first conductive film is formed on the substrate 2, and the second conductive film is formed on the first conductive film.
  • the TFT substrate 100B is manufactured by patterning the first conductive film and the second conductive film from one photomask by a halftone exposure method, thereby forming the conductive layer 3a and the pixel electrode 3 from the first conductive film.
  • Forming (c) a step of forming the gate electrode 4 from the second conductive film on the conductive layer 3a.
  • the manufacturing method of the TFT substrate 100B includes a step (d) of forming an insulating layer 5 having an opening 5u exposing a part of the pixel electrode 3 on the gate electrode 4 and the pixel electrode 3, and the insulating layer 5 (E) forming a semiconductor layer 6 overlapping with the gate electrode 4 through the step.
  • the manufacturing method of the TFT substrate 100B is a step of forming a source electrode 7s and a drain electrode 7d that are electrically connected to the semiconductor layer 6, and is formed on the insulating layer 5 and within the opening 5u.
  • such a manufacturing method of the TFT substrate 100B can manufacture the TFT substrate 100B without increasing the manufacturing cost.
  • the manufacturing method of the TFT substrate 100B includes the step (g) of forming the protective layer 8 on the source electrode 7s and the drain electrode 7d, and the common electrode 9 that overlaps at least a part of the pixel electrode 3 with the protective layer 8 interposed therebetween. It is preferable to include the process (h) of forming.
  • FIG. 5 is a block diagram for explaining an example of a manufacturing method of the TFT substrate 100B.
  • 6A to 6E are schematic cross-sectional views for explaining an example of the manufacturing method of the TFT substrate 100B, and correspond to FIG.
  • the manufacturing method of the TFT substrate 100B includes the gate electrode / pixel electrode forming step GT / PX, the gate insulating layer / semiconductor layer forming step GI / PS, the source / drain electrode forming step SD, and the protective layer forming step. It has PAS and common electrode formation process CT, and the process proceeds in this order.
  • the gate electrode / pixel electrode formation step GT / PX will be described with reference to FIGS. 6 (a) to 6 (e).
  • a first conductive film (for example, a transparent conductive film) 3 ′ is formed on the substrate 2 by sputtering or the like, and a second conductive film is formed on the first conductive film 3 ′. 4 ′ is formed.
  • resist films R1 and R2 having different thicknesses are desired on the second conductive film 4 ′ from one photomask (halftone mask) by a halftone exposure method.
  • the pattern shape is formed. Note that the thickness of the resist film R2 is larger than the thickness of the resist film R1.
  • the first conductive film 3 'and the second conductive film 4' in the region not covered with the resist films R1 and R2 are patterned by a wet etching method.
  • the conductive layer 3a and the pixel electrode 3 are formed from the first conductive film 3 '.
  • the gate electrode 4 and the conductive layer 4 '' are formed from the second conductive film 4 '.
  • the resist film R1 is removed by a dry etching method.
  • a part of the resist film R2 is scraped to obtain a resist film R2 'having a smaller thickness than the resist film R2.
  • the conductive layer 4 ′′ is removed by a further dry etching method. The gate electrode 4 below the resist film R2 'remains.
  • the resist film R2 ' is removed by a known method.
  • the gate electrode 4 and the pixel electrode 3 can be formed from one photomask, the number of photomasks can be reduced, and the manufacturing cost can be reduced.
  • FIG. 1A is referred to for a plan view of the TFT substrate 100C.
  • FIG. 7A is a schematic cross-sectional view taken along the line A-A ′ of FIG.
  • FIG. 7B is a schematic cross-sectional view along the line B-B ′ of FIG.
  • the TFT substrate 100C further includes an insulating layer 5a formed between the gate electrode 4 and the insulating layer 5b, and the pixel electrode 3 (m) is insulated. It differs from the TFT substrate 100A in that it is formed on the layer 5a.
  • the gate insulating layer 5 is formed of the insulating layer 5a and the insulating layer 5b.
  • the insulating layer 5a and the insulating layer 5b are, for example, SiO 2 (silicon oxide), SiN x (silicon nitride), SiO x N y (silicon oxynitride, x> y), SiN x O y (silicon nitride oxide, x> y). ), Al 2 O 3 (aluminum oxide) or tantalum oxide (Ta 2 O 5 ).
  • the lower insulating layer 5a is formed of SiN x or SiN x O y (silicon nitride oxide, x> y). Is preferred. Since the insulating layer formed from the silicon nitride film has a high etching rate, the processing time can be shortened.
  • the upper insulating layer 5b is preferably formed of SiO 2 or SiO x N y (silicon oxynitride, x> y) from the viewpoint of preventing deterioration of semiconductor characteristics.
  • FIG. 8 is a block diagram for explaining a manufacturing method of the TFT substrate 100C.
  • FIG. 9A to FIG. 9G are schematic cross-sectional views for explaining a manufacturing method of the TFT substrate 100C. 9A to 9G correspond to FIG. 7A.
  • the manufacturing method of the TFT substrate 100C includes the gate electrode forming step GT, the first gate insulating layer step GI-1, the pixel electrode forming step PX, and the second gate insulating layer / semiconductor layer forming step GI-2. / PS, source / drain electrode formation step SD, protective layer formation step PAS, and common electrode formation step CT, and the process proceeds in this order.
  • the gate electrode 4 is formed by the method described above.
  • the first gate insulating layer step GI-1 after forming an insulating film (not shown) on the gate electrode 4 by, for example, CVD, photolithography and wet or This insulating film is patterned by a dry etching method or the like to form the insulating layer 5a. Further, after the insulating layer 5a is patterned, the resist (not shown) used for patterning is peeled off.
  • the pixel electrode 3 is formed on the insulating layer 5a by the method described above.
  • an insulating film (not shown) is formed on the insulating layer 5a and the pixel electrode 3 by, for example, a CVD method, and a photolithography method and dry etching are performed.
  • This insulating film is patterned by a method or the like to form the insulating layer 5b.
  • an opening 5u that exposes a part of the pixel electrode 3 is formed in the insulating layer 5b.
  • the resist (not shown) used for patterning is peeled off.
  • the semiconductor layer 6 is formed on the insulating layer 5b by the method described above.
  • the semiconductor layer 6 is formed so as to overlap the gate electrode 4 through the insulating layers 5a and 5b.
  • the source / drain electrode forming step SD, the protective layer forming step PAS and the common electrode forming step CT shown in FIGS. 9 (e) to 9 (f) are performed, and then the source electrode 7s, the drain electrode 7d, the protective layer 8 and The common electrode 9 is formed by the method described above, and the TFT substrate 100C is manufactured.
  • the manufacturing method of the TFT substrate 100C includes the step (a) of preparing the substrate 2, the step (b) of forming the gate electrode 4 and the pixel electrode 3 on the substrate 2, and the gate electrode 4 And a step (c) of forming an insulating film on the pixel electrode 3 and forming a semiconductor film on the insulating film. Further, the TFT substrate 100C is manufactured by patterning the insulating film and the semiconductor film from one photomask by halftone exposure, thereby forming the insulating layer 5b from the insulating film and including the insulating layer 5b.
  • the manufacturing method of the TFT substrate 100C is a step of forming the source electrode 7s and the drain electrode 7d that are electrically connected to the semiconductor layer 6, and is formed on the insulating layer 5b and is formed in the opening 5u.
  • the step (b) preferably further includes a step (b1) of forming the insulating layer 5a on the gate electrode 4 and a step (b2) of forming the pixel electrode 3 on the insulating layer 5a.
  • the step (g) of forming the protective layer 8 on the source electrode 7s and the drain electrode 7d and the common electrode 9 that overlaps at least part of the pixel electrode 3 through the protective layer 8 are formed. It is preferable to further include the step (h).
  • the main difference between the above-described manufacturing method of the TFT substrate 100C and the modified example of the manufacturing method of the TFT substrate 100C is that the semiconductor layer 6 and the insulating layer 5b shown in FIG.
  • the halftone mask is formed by a halftone exposure method.
  • an insulating film (not shown) is formed on the insulating layer 5a and the pixel electrode 3 by, for example, the CVD method.
  • a semiconductor film (not shown) is formed on the insulating film by sputtering, for example.
  • the insulating film and the semiconductor film are patterned.
  • An insulating layer 5b having an opening 5u exposing a part of the pixel electrode 3 from the insulating film is formed, and a semiconductor layer 6 overlapping the gate electrode 4 is formed from the semiconductor film via the insulating layers 5a and 5b.
  • the insulating layer 5b having the opening 5u and the semiconductor layer 6 can be formed from one photomask, the number of photomasks can be reduced, and the manufacturing cost can be reduced.
  • FIG. 10A is a schematic cross-sectional view along the line A-A ′ of FIG.
  • FIG. 10B is a schematic cross-sectional view along the line B-B ′ of FIG.
  • Constituent elements common to the TFT substrate 100A are denoted by the same reference numerals to avoid duplication of description.
  • the main difference between the TFT substrate 100D and the TFT substrate 100A is that a base insulating layer (buffer layer) 5c is formed on the substrate 2, and a gate electrode 4 and a pixel electrode 3 (m) are formed on the base insulating layer 5c. It is a point that has been.
  • the selectivity of the substrate 2 is increased.
  • a plastic substrate can be used as the substrate 2.
  • the base insulating layer 5c for example, SiO 2 (silicon oxide), SiN x (silicon nitride), SiO x N y (silicon oxynitride, x> y), SiN x O y (silicon nitride oxide, x> y), Al
  • a single layer or a laminate formed of 2 O 3 (aluminum oxide) or tantalum oxide (Ta 2 O 5 ) can be used.
  • the thickness of the base insulating layer 5c is, for example, not less than about 50 nm and not more than 600 nm.
  • FIG. 10 is a block diagram for explaining the TFT substrate 100D.
  • 12 (a) to 12 (g) are schematic cross-sectional views for explaining the manufacturing method of the TFT substrate 100D, and correspond to FIG. 10 (a).
  • the manufacturing method of the TFT substrate 100D includes a buffer layer forming step BU, a pixel electrode forming step PX, a gate electrode forming step GT, a gate insulating layer / semiconductor layer forming step GI / PS, a source / drain electrode forming step SD, and a protective layer forming step. It has PAS and common electrode formation process CT, and the process proceeds in this order.
  • the base insulating layer 5c is formed on the substrate 2 by, for example, the CVD method.
  • the pixel electrode 3, the gate electrode 4, the gate insulating layer 5, the semiconductor layer 6, the source electrode 7s, the drain electrode 7d, the protective layer 8 and the common electrode 9 are formed by the method described above.
  • the TFT substrate 100D is manufactured.
  • the insulating layer 5 and the semiconductor layer 6 may be formed from one photomask (halftone mask) by the above-described halftone exposure method.
  • the number of photomasks can be reduced and manufacturing costs can be reduced.
  • FIG. 13A is a schematic cross-sectional view along the line A-A ′ of FIG.
  • FIG. 13B is a schematic cross-sectional view along the line B-B ′ of FIG.
  • Constituent elements common to the TFT substrate 100A are denoted by the same reference numerals to avoid duplication of description.
  • the main difference between the TFT substrate 100E and the TFT substrate 100A is that it has a base insulating layer (buffer layer) 5c formed on the substrate 2, and the pixel electrode 3 (m) is formed under the base insulating layer 5c. It is a point.
  • FIG. 14 is a block diagram illustrating an example of a manufacturing method of the TFT substrate 100E.
  • FIGS. 15A to 15G are schematic cross-sectional views for explaining an example of a manufacturing method of the TFT substrate 100E. 15A to 15G correspond to FIG. 13A.
  • the manufacturing method of the TFT substrate 100E includes a pixel electrode formation step PX, a buffer layer formation step BU, a gate electrode formation step GT, a gate insulating layer / semiconductor layer formation step GI / PS, and source / drain electrode formation.
  • a process SD, a protective layer forming process PAS, and a common electrode forming process CT are provided, and the process proceeds in this order.
  • the pixel electrode 3 is formed on the substrate 2 by the method described above.
  • the base insulating layer 5c is formed on the pixel electrode 3 by the method described above.
  • the gate electrode 4 is formed on the base insulating layer 5c by the method described above.
  • the gate electrode 4 is formed so as not to overlap the pixel electrode 3 through the base insulating layer 5c.
  • the insulating layer 5 is formed on the gate electrode 4 by the method described above. At this time, an opening 5u exposing a part of the pixel electrode 3 is formed in the insulating layer 5 and the base insulating layer 5c.
  • the semiconductor layer 6 that overlaps the gate electrode 4 through the insulating layer 5 is formed on the insulating layer 5 by the method described above.
  • the insulating layer 5 and the semiconductor layer 6 may be formed from one photomask (halftone mask) by the above-described halftone exposure method.
  • the source / drain electrode forming step SD, the protective layer forming step PAS and the common electrode forming step CT shown in FIGS. 15 (e) to 15 (g) are performed, and then the source electrode 7s, the drain electrode 7d, the protective layer 8 and the common The electrode 9 is formed by the method described above, and the TFT substrate 100E is manufactured.
  • the common electrode 9 is a transparent electrode formed of a transparent conductive film (for example, an ITO film). Instead of functioning as a common electrode, a transparent auxiliary capacitor is simply formed.
  • the electrode may function as an electrode.
  • the above-described TFT substrates 100A to 100E have a two-layer electrode structure having the pixel electrode 3 (m) and the common electrode 9, but for example, a TFT for a liquid crystal display device in a VA (Vertical Alignment) mode.
  • the common electrode 9 may not be formed.
  • a semiconductor device in which display defects are unlikely to occur and a method for manufacturing the same are provided.
  • Embodiments of the present invention include a circuit board such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, and an image input
  • a circuit board such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, and an image input
  • EL organic electroluminescence
  • an imaging device such as an image sensor device
  • image input an image input
  • the present invention can be widely applied to devices including thin film transistors, such as electronic devices such as devices and fingerprint readers.

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Abstract

L'objet de la présente invention est de fournir un dispositif à semi-conducteur qui est moins susceptible d'afficher des défauts et son procédé de production. Pour ce faire, la présente invention a trait à un dispositif à semi-conducteur (100A) qui comprend : un substrat (2), une électrode de grille (4) et une électrode de pixel (3(m)) qui sont formées sur le substrat (2) ; une première couche isolante (5) qui est formée sur l'électrode de grille (4) et l'électrode de pixel (3(m)) ; une couche semi-conductrice (6) qui se chevauche avec la première couche isolante (5) par l'intermédiaire de l'électrode de grille (4) ; et une électrode de source (7s) ainsi qu'une électrode de drain (7d) qui sont électriquement connectées à la couche semi-conductrice (6). L'électrode de drain (7d) est agencée sur l'électrode de pixel (3(m)) par l'intermédiaire d'une couche isolante qui inclut la première couche isolante (5), et est connectée à l'électrode de pixel (3(m)) à l'intérieur d'une ouverture (5u) qui est formée dans la couche isolante.
PCT/JP2013/070442 2012-08-02 2013-07-29 Dispositif à semi-conducteur et son procédé de production WO2014021249A1 (fr)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH052190A (ja) * 1991-06-24 1993-01-08 Hitachi Ltd アクテイブマトリクス基板
JPH07120790A (ja) * 1993-08-31 1995-05-12 Kyocera Corp アクティブマトリックス基板およびその製造方法
JP2009031750A (ja) * 2007-06-28 2009-02-12 Fujifilm Corp 有機ｅｌ表示装置およびその製造方法
JP2010256556A (ja) * 2009-04-23 2010-11-11 Hitachi Displays Ltd 画像表示装置およびその製造方法
JP2011023728A (ja) * 2009-07-17 2011-02-03 Beijing Boe Optoelectronics Technology Co Ltd Ｔｆｔ−ｌｃｄアレイ基板及びその製造方法
JP2011171727A (ja) * 2010-01-24 2011-09-01 Semiconductor Energy Lab Co Ltd 表示装置とその作製方法
WO2012066755A1 (fr) * 2010-11-17 2012-05-24 シャープ株式会社 Substrat de transistor à couches minces, dispositif d'affichage pourvu dudit substrat, et procédé de fabrication d'un substrat de transistor à couches minces
JP2012134475A (ja) * 2010-12-03 2012-07-12 Semiconductor Energy Lab Co Ltd 酸化物半導体膜および半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH052190A (ja) * 1991-06-24 1993-01-08 Hitachi Ltd アクテイブマトリクス基板
JPH07120790A (ja) * 1993-08-31 1995-05-12 Kyocera Corp アクティブマトリックス基板およびその製造方法
JP2009031750A (ja) * 2007-06-28 2009-02-12 Fujifilm Corp 有機ｅｌ表示装置およびその製造方法
JP2010256556A (ja) * 2009-04-23 2010-11-11 Hitachi Displays Ltd 画像表示装置およびその製造方法
JP2011023728A (ja) * 2009-07-17 2011-02-03 Beijing Boe Optoelectronics Technology Co Ltd Ｔｆｔ−ｌｃｄアレイ基板及びその製造方法
JP2011171727A (ja) * 2010-01-24 2011-09-01 Semiconductor Energy Lab Co Ltd 表示装置とその作製方法
WO2012066755A1 (fr) * 2010-11-17 2012-05-24 シャープ株式会社 Substrat de transistor à couches minces, dispositif d'affichage pourvu dudit substrat, et procédé de fabrication d'un substrat de transistor à couches minces
JP2012134475A (ja) * 2010-12-03 2012-07-12 Semiconductor Energy Lab Co Ltd 酸化物半導体膜および半導体装置

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