WO2014015635A1 - 数据线-数据线短路检测***及检测方法 - Google Patents

数据线-数据线短路检测***及检测方法 Download PDF

Info

Publication number
WO2014015635A1
WO2014015635A1 PCT/CN2012/087199 CN2012087199W WO2014015635A1 WO 2014015635 A1 WO2014015635 A1 WO 2014015635A1 CN 2012087199 W CN2012087199 W CN 2012087199W WO 2014015635 A1 WO2014015635 A1 WO 2014015635A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
dds
lines
data
detection system
Prior art date
Application number
PCT/CN2012/087199
Other languages
English (en)
French (fr)
Inventor
贾丕健
郝昭慧
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2014015635A1 publication Critical patent/WO2014015635A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display device detection technologies, and in particular, to a DDS detection system and a detection method. Background technique
  • the thin film field effect transistor liquid crystal display (TFT-LCD) industrial array (Array) production line test needs to detect data line open (Data Open), DDS (data line - data line short circuit Data-Data Short), etc., its circuit test
  • the main method is: in the peripheral circuit, the odd lines of all data lines (Data lines) are connected into an odd total circuit line DO through a shorting bar, and all the even lines are connected to each other through a shorting bar in the peripheral circuit.
  • Even total circuit line DE when different voltages are applied to the odd total circuit line DO and the even total circuit line DE respectively, if no short circuit occurs, the current flows smoothly, if a short circuit occurs between different data lines, A circuit loop is formed, which in turn detects the DDS.
  • the advantage of the shorting bar is that it can be flexibly designed according to the size of the display panel to be inspected, and with multiple movement tests, so that the large-size display panel can be detected.
  • the circuit test by the shorting bar is only a very general test, and the DDS cannot be classified, which makes the analysis process cumbersome in the future, increases the analysis time, and cannot confirm the cause of the defect more effectively and timely, thereby improving the yield.
  • the technical problem to be solved by the present invention is to provide a DDS detection system to minimize the search range of the DDS occurrence location and the type search range of the DDS, so that the cause of the DDS can be found more quickly and accurately.
  • an embodiment of the present invention provides a DDS detection system, including:
  • the display panel has a plurality of data lines arranged in sequence in the peripheral circuit area, and each adjacent two data lines includes an odd line and an even line;
  • An odd total circuit line connected to all odd lines of the data line, having an odd voltage input;
  • the even total circuit line is connected to all the even lines of the data line and has an even voltage input end;
  • the display panel is provided with an on/off switch on each data line of the peripheral circuit area.
  • the on/off switch is a thin film field effect transistor switch
  • the detection system further comprises a control line for controlling on and off of the thin film field effect transistor switch.
  • control line is fabricated in the same layer as the gate line on the display panel.
  • the detection system is provided with at least N control lines, N is greater than or equal to 3 and less than the total number of data lines; and the thin film field effect transistor switches on each of the N data lines arranged in sequence are respectively controlled by different control lines.
  • the detection system is provided with three control lines.
  • an embodiment of the present invention further provides a method for performing DDS detection using the DDS detection system described above, including the following steps:
  • step S1 inputting a high potential to one of the odd voltage input terminal and the even voltage input terminal, and inputting a low potential to the other; turning off all the on/off switches, so that the circuit in the display panel is disconnected from the data line of the peripheral circuit; if there is a signal Output from the input of the low-potential total circuit line, it means that the peripheral circuit is abnormal, the data line is short-circuited, and the detection ends; if there is no signal output from the input low-potential total circuit line, it means that the peripheral circuit has no problem, go to step S2;
  • S2 input a high potential to one of the odd voltage input terminal and the even voltage input terminal, and input another low potential potential; divide the on/off switch into at least three groups, respectively connect at least one group of on/off switches, and other on and off The switch remains off. If a signal is output from the total circuit line that inputs the low potential, an abnormality occurs on the data line where the connected on/off switch is located, and the detection ends. If no signal is output from the total circuit line of the input low potential, It indicates that there is no problem with the data line where the connected on/off switch is located.
  • the at least one set of on/off switches are respectively connected to: firstly, a group of on/off switches are sequentially connected, and the total circuit lines that input the low potential are not output after the plurality of groups of on/off switches are respectively connected.
  • the two sets of on-off switches are connected in sequence, and when the plurality of on-off switches are respectively connected and the input of the low-potential total circuit line has no output signal, the number of connected on-off switch groups is continuously increased until there is a signal The output is terminated from the total circuit line input with low potential.
  • the detection system is provided with at least N control lines, N is greater than or equal to 3 and less than the equator control, and the on/off switch 4 is divided into N groups according to different control lines.
  • the N is 3, and the control line includes a first control line, a second control line, and a third control line.
  • the invention can reduce the position of the DDS phenomenon and the search range of the DDS type as soon as possible, so that the cause of the DDS phenomenon can be found more quickly and accurately, and the product yield can be improved.
  • FIG. 1 is a schematic diagram of a DDS detection structure according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing the positional relationship between a control line, a thin film field effect transistor switch, and an odd and even total circuit line in a DDS detection structure according to an embodiment of the present invention
  • FIG. 3 is a flow chart showing the steps of the DDS detecting method according to an embodiment of the present invention. detailed description
  • this embodiment describes a DDS detection structure, including:
  • the display panel has a plurality of data lines D1 ⁇ Dm (m is a natural number) arranged in sequence in the peripheral circuit area, and each adjacent two data lines includes an odd line and an even line;
  • An odd total circuit line DO connected to all odd lines D1, D3, D5... of the data line, having an odd voltage input terminal;
  • the even total circuit line DE is connected to all even lines D2, D4, D6... of the data line, and has an even voltage input terminal;
  • the display panel is provided with an on/off switch on each of the data lines of the peripheral circuit area (in this embodiment, each of the on/off switches is not shown in FIG. 1, but all the on/off switches are located in FIG. In the data line D1 ⁇ Dm in the peripheral circuit area indicated by the dotted line frame in the middle I.
  • the peripheral circuit has a DDS (data line to data line short circuit) phenomenon. If it is detected that there is no significant change in the voltage of the two input terminals, it means that the DDS phenomenon is not generated in the peripheral circuit, so that the data lines in the peripheral circuit have no problem; then the control part or all the disconnection is closed, and the inside of the display panel is closed. Whether the data line has a short circuit
  • the detection reduces the search range of the position and type generated by the DDS phenomenon, and can quickly find out the cause of the DDS.
  • the embodiment is an example extended on the basis of the first embodiment.
  • the on/off switch is a thin film field effect transistor (TFT) switching TFT, and the detecting structure further includes controlling the film.
  • the field effect transistor switches the control line of the TFT on and off.
  • control line is fabricated in the same layer as the gate line on the display panel.
  • the detecting structure is provided with at least N control lines, N is greater than or equal to 3 and less than or equal to the total number of data lines; and the thin film field effect transistor switching TFTs on each of the N data lines arranged in sequence are respectively controlled by different control lines.
  • the control lines in this embodiment are three, which are a first control line G1, a second control line G2, and a third control line G3, respectively.
  • the first control line G1 is used to control the on/off of the thin film field effect transistor switching TFT on the data lines D1, D4...D3i+1;
  • the second control line G2 is used for control.
  • the thin film field effect transistor switching TFT on the data line D2, D5...D3i+2 is turned on and off;
  • the third control line G3 is used to control the thin film field effect transistor switching TFT on the data lines D3, D6...D3i+3 On/off, where i is an integer greater than or equal to zero. That is, the thin film field effect transistor switching TFTs on each of the adjacent three data lines are controlled by the first control line G1, the second control line G2, and the third control line G3, respectively.
  • Embodiment 3 is an integer greater than or equal to zero.
  • this embodiment describes a method for performing DDS detection by using the DDS detection structure described in Embodiment 1 or Embodiment 2, including the following steps:
  • step S1 inputting a high potential to one of the odd voltage input terminal and the even voltage input terminal, and inputting a low potential to the other; turning off all the on/off switches, so that the circuit in the display panel is disconnected from the data line of the peripheral circuit; if there is a signal Output from the input of the low-potential total circuit line, it means that the peripheral circuit is abnormal, the data line is short-circuited, and the detection ends; if there is no signal output from the input low-potential total circuit line, it means that the peripheral circuit has no problem, go to step S2;
  • S2 input a high potential to one of the odd voltage input terminal and the even voltage input terminal, and input another low potential potential; divide the on/off switch into at least three groups, respectively connect at least one group of on/off switches, and other on and off The switch remains off, if there is a signal output from the total circuit line that inputs the low potential, then the description An abnormality occurs on the data line where the connected on/off switch is located, and the detection ends. If no signal is output from the total circuit line that inputs the low potential, the data line where the connected on/off switch is located has no problem.
  • the at least one set of on/off switches are respectively connected to: firstly, a group of on/off switches are sequentially connected, and the total circuit lines of the low potential are input after the plurality of groups of on/off switches are respectively connected.
  • the two sets of on/off switches are connected in sequence, and when the plurality of on/off switches are respectively connected and the input of the low-potential total circuit line has no output signal, the number of connected on-off switch groups is continuously increased until A signal is output from the total circuit line that inputs the low potential, and the detection ends.
  • This embodiment is an example extended on the basis of the third embodiment. Specifically, when the DDS detection structure described in the second embodiment is used for DDS detection:
  • a high potential is input to the odd voltage input terminal of the odd total circuit line DO, and the odd voltage input terminal of the even total circuit line DE inputs a low potential, and at this time, the first control line G1, the second control line G2, and the third control line G3 inputs low voltage, that is, the thin film FET switching TFTs of all data lines are disconnected at this time.
  • the even total circuit line DE it means that there is SD metal in the peripheral circuit (the metal of the data line) Residue, causing two adjacent data lines to conduct, causing a short circuit. If no signal is output from the even total circuit line DE, there is no problem with the peripheral circuit.
  • the even total circuit line DE is input to the low potential
  • the first control line G1 is input to the high potential (ie, controlling the thin film field effect on the data line controlled by the first control line G1)
  • the transistor switching TFT is turned on
  • the second control line G2 and the third control line G3 are input with a low potential
  • the even total circuit line DE has a signal output, it indicates that a DDS phenomenon occurs, but the possibility of causing the DDS phenomenon at this time is : 1)
  • the data line affected by the thin film field effect transistor switching TFT controlled by the first control line G1 has ESD (electrostatic discharge) and causes DDS failure phenomenon (this can be determined that the two points where ESD occurs are the same
  • the control line controls on and off, and is not adjacent to two adjacent parity data lines); or 2) - a residual SD metal that can span three data lines or more.
  • the first control line G1 is input to the low potential
  • the second control line G2 and the third control line G3 are added to the high potential
  • the even total circuit line DE has no signal output, so that the second case can be excluded. That is, a large DDS caused by SD metal residue;
  • the second control line G2 inputs a high potential
  • the first control line G1 the third control line G3 inputs a low potential
  • the third control line G3 inputs a high potential
  • a control line G1 and a second control line G2 input a low potential
  • the even total circuit line DE when the odd total circuit line DO is input to a high potential, the even total circuit line DE is input to a low potential, and the first control line G1, the second control line G2, and the third control line G3 are individually input with a high potential, the even total circuit line DE If there is no signal output, it can be excluded that there is a large SD metal residue in the display panel (crossing the three data lines or more of the SD metal residue), and then the first control line G1 and the second control line G2 input a high potential, the third control line G3 input low potential, even total circuit line DE has signal output, first control line G1 and third control line G3 input high potential, second control line G2 input low potential, even total circuit line DE has no signal output, indicating possible For: 1) the data line controlled by the first control line G1 and the second control line G2 has SD metal residual, and this residue occupies only one pixel size; or 2) is controlled by the first control line G1 and the second control ESD is generated by two adjacent data lines controlled by line G2, and the
  • the TFT switch (where the TFT switch is the TFT switch in the display panel) (the ESD in the display panel generally occurs at the intersection of the data line and the gate line, that is, the TFT switch, so that the ESD causes the data line and the gate line to lead
  • the control lines Gl, G2, and G3 of the peripheral circuits reach the above conditions, the corresponding conclusions can be drawn.
  • the above embodiment of the present invention can quickly confirm whether the DDS occurs in the display panel or in the peripheral circuit; in some cases, it can be quickly confirmed whether the DDS is caused by metal residue or ESD.
  • the test device can only check whether there is DDS in the display panel, the specific location and how many points are not reported), therefore the solution It is only a rough confirmation of the extent and cause of the DDS.
  • more control lines can be used as needed to make a more accurate search for the range and range of the DDS.
  • the invention can reduce the position of the DDS phenomenon and the search range of the DDS type as soon as possible, so that the cause of the DDS phenomenon can be found more quickly and accurately, and the product yield can be improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种数据线-数据线短路（DDS）检测***以及采用该DDS检测***进行DDS检测的方法。该DDS检测***包括：显示面板，在***电路区中具有依次排列的若干数据线，每相邻两根数据线包括一根奇数线和一根偶数线；奇数总电路线（DO），与所述数据线的所有奇数线（D1、D3、D5……）连接，具有奇数电压输入端；偶数总电路线（DE），与所述数据线的所有偶数线（D2、D4、D6……）连接，具有偶数电压输入端；所述显示面板位于***电路区的每根数据线上各设置有一个通断开关。该DDS检测***以及采用该DDS检测***进行DDS检测的方法能尽快的缩小DDS现象发生的位置和DDS的种类的查找范围，从而可以更快更准确的找到DDS现象发生的原因，提高产品良率。

Description

数据线-数据线短路检测***及检测方法 技术领域
本发明涉及液晶显示装置检测技术领域，尤其涉及一种 DDS检测***及 检测方法。 背景技术
目前薄膜场效应晶体管液晶显示器（TFT-LCD )产业阵列 （Array )产线 测试中需要检测数据线开路 （Data Open )、 DDS (数据线 -数据线短路 Data-Data Short ) 等， 其电路测试的主要方法是： 在***电路将所有数据线 ( Data线） 的奇数线通过一条短路条（shorting bar )连成一条奇数总电路线 DO,在***电路将所有的偶数线通过一条短路条连成一条偶数总电路线 DE; 当分别在所述奇数总电路线 DO和偶数总电路线 DE上加不同的电压时， 如 果没有发生短路， 则电流顺利流走， 如果不同的数据线之间发生短路， 形成 电路回路， 进而检测到 DDS。 短路条的优势在于可以依照所检查的显示面板 尺寸来弹性设计， 并配合多次移动测试， 如此可进行大尺寸显示面板的检测。 但通过短路条进行的电路测试只是很笼统的测试， 不能对 DDS进行分类， 从 而使得以后的分析过程很繁瑣， 增加分析时间， 不能更有效及时地确认不良 的原因， 进而提高良率。 发明内容
(一）要解决的技术问题
本发明要解决的技术问题是：提供一种 DDS检测***，以尽量缩小 DDS 发生位置的查找范围和 DDS 的种类查找范围， 从而可以更快更准确的找到 DDS产生的原因。
(二）技术方案
为解决上述问题， 一方面， 本发明的实施例提供了一种 DDS检测***， 包括：
显示面板， 具有在***电路区中依次排列的若干数据线， 每相邻两根数 据线包括一根奇数线和一根偶数线；
奇数总电路线，与所述数据线的所有奇数线连接，具有奇数电压输入端； 偶数总电路线，与所述数据线的所有偶数线连接，具有偶数电压输入端； 所述显示面板位于***电路区的每根数据线上设置有通断开关。
优选地， 所述通断开关为薄膜场效应晶体管开关， 所述检测***还包括 控制所述薄膜场效应晶体管开关通断的控制线。
优选地， 所述控制线与所述显示面板上的栅线同层制作。
优选地， 所述检测***至少设有 N根控制线， N大于等于 3并且小于等 于数据线的总数； 每依次排列的 N根数据线上的薄膜场效应晶体管开关分别 由不同的控制线控制。
优选地， 所述检测***设有 3根控制线。
另一方面， 本发明的实施例还提供了一种釆用上述 DDS检测***进行 DDS检测的方法， 包括以下步骤：
S1 : 向所述奇数电压输入端和偶数电压输入端之一输入高电势， 另一个 输入低电势； 关断所有通断开关， 使得显示面板内电路与***电路的数据线 断开； 如果有信号从输入低电势的总电路线输出， 则说明***电路异常， 发 生数据线短路， 检测结束； 如果没有信号从输入低电势的总电路线输出， 则 说明***电路没有问题， 转到步骤 S2;
S2: 向所述奇数电压输入端和偶数电压输入端之一输入高电势， 另一个 输入低电势； 将所述通断开关分为至少三组， 分别连通至少一组通断开关， 其它通断开关保持关断， 如果有信号从输入低电势的总电路线输出， 则说明 连通的通断开关所在的数据线上发生异常， 检测结束； 如果没有信号从输入 低电势的总电路线输出， 则说明连通的通断开关所在的数据线没有问题。
优选地， 所述步骤 S2中， 分别连通至少一组通断开关具体为： 首先依次 连通一组通断开关， 在所述若干组通断开关都分别连通后输入低电势的总电 路线没有输出信号时， 再依次连通两组通断开关， 在所述若干组通断开关都 分别连通后输入低电势的总电路线没有输出信号时， 再不断增加连通的通断 开关组数， 直到有信号从输入低电势的总电路线输出， 检测结束。
优选地， 所述检测***至少设有 N根控制线， N大于等于 3并且小于等 线控制， 所述通断开关 4艮据控制线的不同分为 N组。
优选地， 所述 N为 3 , 所述控制线包括第一控制线、 第二控制线和第三 控制线。 (三）有益效果
本发明能尽快的缩小 DDS现象发生的位置和 DDS的种类的查找范围, 从而可以更快更准确的找到 DDS现象发生的原因， 提高产品良率。 附图说明
图 1为本发明实施例 DDS检测结构的示意图；
图 2为本发明实施例 DDS检测结构中控制线、薄膜场效应晶体管开关和 奇、 偶数总电路线的位置关系示意图； 以及
图 3为本发明实施例 DDS检测方法的步骤流程图。 具体实施方式
下面结合附图及实施例对本发明的实施例进行详细说明如下。 实施例一
如图 1所示， 本实施例记载了一种 DDS检测结构， 包括：
显示面板， 在***电路区中具有依次排列的若干数据线 Dl~Dm ( m为自 然数 ), 每相邻两根数据线包括一根奇数线和一根偶数线；
奇数总电路线 DO, 与所述数据线的所有奇数线 Dl、 D3、 D5...连接， 具 有奇数电压输入端；
偶数总电路线 DE, 与所述数据线的所有偶数线 D2、 D4、 D6...连接， 具 有偶数电压输入端；
其中， 所述显示面板位于***电路区的每根数据线上各设置有一个通断 开关 （本实施例中， 图 1中未示出具体每个通断开关， 但是所有通断开关位 于图 1中 I处所指虚线框所示***电路区中的数据线 Dl~Dm上）。
检测时， 先控制所有通断开关断开， 当在奇数电压输入端和偶数电压输 入端分别输入一高一低电压时，如果检测到这两条输入端电压有明显变化时， 由于在***电路区的所述通断开关是断开的， 所述两条输入端电压不会受到 显示面板内部数据线的影响， 因此此时说明***电路有 DDS (数据线到数据 线的短路）现象产生， 如检测到这两条输入端电压无明显变化时， 则说明外 围电路没有产生 DDS现象， 从而说明***电路中的数据线都没有问题； 然后 控制部分或所有通断开关闭合， 对显示面板内部数据线是否有短路现象进行 检测， 缩小了 DDS现象产生的位置和种类的查找范围， 能够快速找到 DDS 产生的原因。 实施例二：
如图 2所示， 本实施例是在实施例一基础上延伸的实例， 本实施例中所 述通断开关为薄膜场效应晶体管 （TFT )开关 TFT, 所述检测结构还包括控 制所述薄膜场效应晶体管开关 TFT通断的控制线。
在本实施例中， 所述控制线与所述显示面板上的栅线同层制作。
所述检测结构至少设有 N根控制线， N大于等于 3并且小于等于数据线 的总数；每依次排列的 N根数据线上的薄膜场效应晶体管开关 TFT分别由不 同的控制线控制。
如图 2所示， 本实施例中所述控制线为 3根， 分别为第一控制线 Gl、 第 二控制线 G2和第三控制线 G3。 由图 2可以看出，本实施例中第一控制线 G1 用于控制数据线 Dl、 D4...D3i+l上的薄膜场效应晶体管开关 TFT的通断； 第二控制线 G2用于控制数据线 D2、 D5...D3i+2上的薄膜场效应晶体管开关 TFT的通断； 第三控制线 G3用于控制数据线 D3、 D6...D3i+3上的薄膜场效 应晶体管开关 TFT的通断， 其中， i为大于等于 0的整数。 即每相邻 3根数 据线上的薄膜场效应晶体管开关 TFT分别由所述第一控制线 Gl、 第二控制 线 G2和第三控制线 G3控制。 实施例三：
如图 3所示， 本实施例记载了一种釆用实施例一或实施例二所述的 DDS 检测结构进行 DDS检测的方法， 包括以下步骤：
S1 : 向所述奇数电压输入端和偶数电压输入端之一输入高电势， 另一个 输入低电势； 关断所有通断开关， 使得显示面板内电路与***电路的数据线 断开； 如果有信号从输入低电势的总电路线输出， 则说明***电路异常， 发 生数据线短路， 检测结束； 如果没有信号从输入低电势的总电路线输出， 则 说明***电路没有问题， 转到步骤 S2;
S2: 向所述奇数电压输入端和偶数电压输入端之一输入高电势， 另一个 输入低电势； 将所述通断开关分为至少三组， 分别连通至少一组通断开关， 其它通断开关保持关断， 如果有信号从输入低电势的总电路线输出， 则说明 连通的通断开关所在的数据线上发生异常， 检测结束； 如果没有信号从输入 低电势的总电路线输出， 则说明连通的通断开关所在的数据线没有问题。
本实施例中， 所述步骤 S2中， 分别连通至少一组通断开关具体为： 首先 依次连通一组通断开关， 在所述若干组通断开关都分别连通后输入低电势的 总电路线没有输出信号时， 再依次连通两组通断开关， 在所述若干组通断开 关都分别连通后输入低电势的总电路线没有输出信号时， 再不断增加连通的 通断开关组数， 直到有信号从输入低电势的总电路线输出， 检测结束。 实施例四：
本实施例是在实施例三基础上延伸的实例， 具体为釆用实施例二记载的 DDS检测结构进行 DDS检测时：
首先， 在奇数总电路线 DO的奇数电压输入端输入高电势， 偶数总电路 线 DE的奇数电压输入端输入低电势， 且此时第一控制线 Gl、 第二控制线 G2和第三控制线 G3都输入低电压， 即此时所有数据线上的薄膜场效应晶体 管开关 TFT都是断开的， 如果有信号从偶数总电路线 DE输出， 则说明在外 围电路有 SD金属（数据线的金属材料）残留， 造成两条相邻的数据线导通， 从而造成短路， 如果没信号从偶数总电路线 DE输出， 则说明***电路没有 问题。 经过上述步骤可以确定***电路的状态。
然后， 当奇数总电路线 DO输入高电势， 偶数总电路线 DE输入低电势， 且第一控制线 G1输入高电势（即控制由所述第一控制线 G1控制的数据线上 的薄膜场效应晶体管开关 TFT导通）， 第二控制线 G2、 第三控制线 G3输入 低电势的时候，如果偶数总电路线 DE有信号输出，则说明有 DDS现象发生， 但此时造成 DDS现象的可能是： 1 ) 受第一控制线 G1控制的薄膜场效应晶 体管开关 TFT影响的数据线有发生 ESD (静电放电 )从而造成 DDS不良现 象的发生（此时可以确定发生 ESD的这两个点是由同一控制线控制通断， 且 不是相邻的两条奇偶相异的数据线）； 或 2 )—个能够跨越三根数据线或以上 的 SD金属残留。 此时， 再把第一控制线 G1输入低电势， 第二控制线 G2和 第三控制线 G3—起加入高电势， 偶数总电路线 DE都没有信号的输出，从而 可以排除是第二种情况即一个很大的 SD金属残留造成的 DDS; 同理， 如果 第二控制线 G2输入高电势， 第一控制线 Gl、 第三控制线 G3输入低电势或 第三控制线 G3输入高电势， 第一控制线 Gl、 第二控制线 G2输入低电势， 同理可得出相对应的结果。此时就可以将产生 DDS现象的种类缩小在两个数 据线发生 ESD上。
再次， 当奇数总电路线 DO输入高电势， 偶数总电路线 DE输入低电势， 第一控制线 Gl、 第二控制线 G2、 第三控制线 G3分别单独输入高电势时， 偶 数总电路线 DE都无信号输出， 则可以排除显示面板内有大的 SD金属残留 (跨越三根数据线或以上的 SD金属残留 ), 再第一控制线 G1和第二控制线 G2输入高电势， 第三控制线 G3输入低电势， 偶数总电路线 DE有信号输出， 第一控制线 G1和第三控制线 G3输入高电势， 第二控制线 G2输入低电势， 偶数总电路线 DE无信号输出时， 说明可能为： 1 )在受第一控制线 G1和第 二控制线 G2控制的数据线有 SD金属残留，且这个残留占且只占一个像素大 小；或 2 )受第一控制线 G1和第二控制线 G2控制的相邻两条数据线发生 ESD, 发生 ESD的这两个点是在受显示面板内的同一栅线（此处的栅线为显示面板 内的栅线）控制的相邻的两个 TFT开关 （此处的 TFT开关为显示面板内的 TFT开关 )处（显示面板内的 ESD—般发生在数据线和栅线的交叠处即 TFT 开关处， 这样 ESD造成数据线和栅线导通）； 同理当***电路的控制线 Gl、 G2、 G3只要达成以上条件， 都可以得出相应结论。
因此，本发明的上述实施例可以很快确认 DDS是发生在显示面板内还是 ***电路；一些情况下还可以很快确认 DDS是由金属残留引起的还是由 ESD 引起的。
上面仅是本申请的一种实施方式， 一些情况下由于阵列测试设备（Array Tester )限制（比如测试设备只能检查显示面板内是否有 DDS, 具***置以及 多少个点不报 ), 因此本方案只是对引起 DDS位置范围以及原因进行的大致 确认。 在实际的应用过程中， 根据需要可以使用更多的控制线， 对引起 DDS 的位置范围和种类范围进行更为精确的查找。
本发明能尽快的缩小 DDS现象发生的位置和 DDS的种类的查找范围， 从而可以更快更准确的找到 DDS现象发生的原因， 提高产品良率。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本发明的范畴， 本发明的专 利保护范围应由权利要求限定。

Claims

权 利 要 求 书
1、 一种 DDS检测***， 包括：
显示面板， 在***电路区中具有依次排列的若干数据线， 每相邻两根数 据线包括一根奇数线和一根偶数线；
奇数总电路线，与所述数据线的所有奇数线连接，具有奇数电压输入端； 偶数总电路线，与所述数据线的所有偶数线连接，具有偶数电压输入端； 以及
其中， 所述显示面板位于***电路区的每根数据线上设置有通断开关。
2、 如权利要求 1所述的 DDS检测***， 其中， 所述通断开关为薄膜场 效应晶体管开关， 所述检测***还包括控制所述薄膜场效应晶体管开关通断 的控制线。
3、 如权利要求 2所述的 DDS检测***， 其中， 所述控制线与所述显示 面板上的栅线同层制作。
4、 如权利要求 2所述的 DDS检测***， 其中， 所述检测***至少设有 N根控制线， N大于等于 3并且小于等于数据线的总数； 每依次排列的 N根 数据线上的薄膜场效应晶体管开关分别由不同的控制线控制。
5、 如权利要求 4所述的 DDS检测***， 其中， 所述检测***设有 3根 控制线。
6、一种釆用权利要求 1-3中任一项所述的 DDS检测***进行 DDS检测 的方法， 包括以下步骤：
S1 : 向所述奇数电压输入端和偶数电压输入端之一输入高电势， 另一个 输入低电势； 关断所有通断开关， 使得显示面板内电路与***电路的数据线 断开； 如果有信号从输入低电势的总电路线输出， 则说明***电路异常， 发 生数据线短路， 检测结束； 如果没有信号从输入低电势的总电路线输出， 则 说明***电路没有问题， 转到步骤 S2;
S2: 向所述奇数电压输入端和偶数电压输入端之一输入高电势， 另一个 输入低电势； 将所述通断开关分为至少三组， 分别连通至少一组通断开关， 其它通断开关保持关断， 如果有信号从输入低电势的总电路线输出， 则说明 连通的通断开关所在的数据线上发生异常， 检测结束； 如果没有信号从输入 低电势的总电路线输出， 则说明连通的通断开关所在的数据线没有问题。
7、 如权利要求 6所述的 DDS检测方法， 其中， 所述步骤 S2中， 分别连 通至少一组通断开关具体为： 首先依次连通一组通断开关， 在所述若干组通 断开关都分别连通后输入低电势的总电路线没有输出信号时， 再依次连通两 组通断开关， 在所述若干组通断开关都分别连通后输入低电势的总电路线没 有输出信号时， 再不断增加连通的通断开关组数， 直到有信号从输入低电势 的总电路线输出， 检测结束。
8、 如权利要求 6或 7所述的 DDS检测方法， 其中， 所述检测***至少 设有 N根控制线， N大于等于 3并且小于等于数据线的总数； 每依次排列的 N根数据线上的通断开关分别由不同的控制线控制， 所述通断开关根据控制 线的不同分为 N组。
9、 如权利要求 8所述的 DDS检测方法， 其中， 所述 N为 3 , 所述控制 线包括第一控制线、 第二控制线和第三控制线。
PCT/CN2012/087199 2012-07-23 2012-12-21 数据线-数据线短路检测***及检测方法 WO2014015635A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210257087.1A CN102768815B (zh) 2012-07-23 2012-07-23 Dds检测结构及检测方法
CN201210257087.1 2012-07-23

Publications (1)

Publication Number Publication Date
WO2014015635A1 true WO2014015635A1 (zh) 2014-01-30

Family

ID=47096200

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/087199 WO2014015635A1 (zh) 2012-07-23 2012-12-21 数据线-数据线短路检测***及检测方法

Country Status (2)

Country Link
CN (1) CN102768815B (zh)
WO (1) WO2014015635A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102768815B (zh) * 2012-07-23 2015-04-08 京东方科技集团股份有限公司 Dds检测结构及检测方法
CN103278948B (zh) 2013-05-30 2015-10-21 合肥京东方光电科技有限公司 用于显示面板的线类不良检测的方法和检测装置
CN103926717B (zh) 2013-12-31 2016-09-14 上海中航光电子有限公司 显示面板的检测电路、显示面板及其检测方法
CN104616612B (zh) * 2015-02-26 2018-05-25 上海和辉光电有限公司 Amoled显示器、其测试组件及其缺陷测试方法
CN105261317B (zh) * 2015-09-17 2018-05-29 京东方科技集团股份有限公司 数据线短接不良的检测方法和检测装置
CN110322819A (zh) * 2019-07-16 2019-10-11 武汉华星光电半导体显示技术有限公司 显示面板测试电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1218572A (zh) * 1996-03-28 1999-06-02 西门子公司 具有检测电路的电路装置
US6861665B2 (en) * 2000-12-29 2005-03-01 Lg.Philips Lcd Co., Ltd. Liquid crystal display device
TW200737078A (en) * 2006-03-21 2007-10-01 Au Optronics Corp Liquid crystal display device, thin-film transisor substrate and testing method
CN101515430A (zh) * 2009-03-30 2009-08-26 友达光电股份有限公司 显示面板及其线路检查方法
CN102110400A (zh) * 2009-12-29 2011-06-29 上海天马微电子有限公司 双栅极线显示装置的测试结构及线缺陷测试方法
CN102768815A (zh) * 2012-07-23 2012-11-07 京东方科技集团股份有限公司 Dds检测结构及检测方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1218572A (zh) * 1996-03-28 1999-06-02 西门子公司 具有检测电路的电路装置
US6861665B2 (en) * 2000-12-29 2005-03-01 Lg.Philips Lcd Co., Ltd. Liquid crystal display device
TW200737078A (en) * 2006-03-21 2007-10-01 Au Optronics Corp Liquid crystal display device, thin-film transisor substrate and testing method
CN101515430A (zh) * 2009-03-30 2009-08-26 友达光电股份有限公司 显示面板及其线路检查方法
CN102110400A (zh) * 2009-12-29 2011-06-29 上海天马微电子有限公司 双栅极线显示装置的测试结构及线缺陷测试方法
CN102768815A (zh) * 2012-07-23 2012-11-07 京东方科技集团股份有限公司 Dds检测结构及检测方法

Also Published As

Publication number Publication date
CN102768815B (zh) 2015-04-08
CN102768815A (zh) 2012-11-07

Similar Documents

Publication Publication Date Title
WO2014015635A1 (zh) 数据线-数据线短路检测***及检测方法
EP2983039B1 (en) Display panel and display device
CN103513454B (zh) 阵列基板及其检测方法和制备方法
US10977970B2 (en) Array substrate, display apparatus, detecting apparatus and detecting method for detecting defect connection of data line
TWI385452B (zh) 陣列基板以及具有陣列基板之顯示裝置
JP4281622B2 (ja) 表示装置及び検査方法
CN104483795B (zh) 阵列基板及其检测方法、显示面板和显示装置
US9146409B2 (en) LCD, array substrate of LCD and method for repairing broken line
US10102783B2 (en) Array substrate and detecting method for an array substrate
US10325535B2 (en) Circuit for testing display panel, method for testing display panel, and display panel
US9424792B2 (en) Test method and test device for line defect of display panel
CN102692774A (zh) 液晶显示面板
EP2991069B1 (en) Gate electrode drive circuit and array substrate
WO2015176367A1 (zh) 显示器阵列基板的***测试线路以及液晶显示面板
CN104880840A (zh) 触控显示基板、vt测试方法和液晶显示面板
CN101345018A (zh) 显示设备的数据驱动器、用于数据驱动器的测试方法及探针卡
WO2017150175A1 (ja) 表示装置及び表示装置の検査方法
KR20110029520A (ko) 액정표시소자 및 그 제조방법
WO2018152884A1 (zh) 一种测试阵列基板的栅极线的线路及方法
TW201437728A (zh) 顯示裝置和其操作方法
CN103149713A (zh) 阵列面板检测电路结构
CN102402031A (zh) 测试***
US8529307B1 (en) Detection circuit and manufacturing method for LCD panel
US20060028232A1 (en) Testing method for LCD panels
US7990486B2 (en) Liquid crystal display panel with line defect repairing mechanism and repairing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12881944

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09/06/2015)

122 Ep: pct application non-entry in european phase

Ref document number: 12881944

Country of ref document: EP

Kind code of ref document: A1