WO2013180653A1 - Hybrid solar cell and method of fabricating thereof - Google Patents

Hybrid solar cell and method of fabricating thereof Download PDF

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Publication number
WO2013180653A1
WO2013180653A1 PCT/SG2013/000216 SG2013000216W WO2013180653A1 WO 2013180653 A1 WO2013180653 A1 WO 2013180653A1 SG 2013000216 W SG2013000216 W SG 2013000216W WO 2013180653 A1 WO2013180653 A1 WO 2013180653A1
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heterojunction
layer
contact
doped
absorber layer
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PCT/SG2013/000216
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French (fr)
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Rolf Stangl
Thomas Mueller
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National University Of Singapore
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Priority to CN201390000632.7U priority Critical patent/CN204651337U/en
Priority to DE201321000122 priority patent/DE212013000122U1/en
Publication of WO2013180653A1 publication Critical patent/WO2013180653A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/078Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier including different types of potential barriers provided for in two or more of groups H01L31/062 - H01L31/075
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Definitions

  • the invention relates to a hybrid solar cell and a method of fabricating thereof, and more particularly, a hybrid homojunction/heterojunction solar cell (i.e., with homojunction and heterojunction contacts).
  • a conventional industrial silicon wafer solar cell 100 is shown in Fig. 1.
  • a p-type silicon (Si) wafer 102 is used.
  • Excess charge carrier separation is achieved by a front side full-area diffused p/n + homojunction (emitter layer for minority carrier collection) 104 with point (or line) metal contacts 106, and a rear side full-area diffused p/p + homojunction (back-surface field (BSF) layer for majority carrier collection) 108 with a full-area Al metal contact 110.
  • a passivation layer 112 made of silicon nitride (SiN x ) is deposited on the front side diffused homojunction 104.
  • the front side p/n + diffused homojunction 104 may be a phosphorus diffused crystalline silicon (Ph-diffused c-Si(n + )) and the rear side p/p + diffused homojunction 08 may be an aluminium diffused crystalline silicon (Al-diffused c-Si(p + )).
  • the front side and rear side homojunctions 104, 108 are each formed by a high-temperature thermal diffusion process and a high- temperature contact firing.
  • the emitter (i.e., the p/n junction) 104 is located at the front side of the solar cell 100.
  • n-type Si wafers In order to improve the cell efficiency, the use of n-type Si wafers is generally proposed. Thus the light-induced degradation observed in p-type Cz silicon (due to metastable boron-oxygen complexes) can be avoided, and furthermore, higher open-circuit voltages can be reached. This is because electron capture coefficient is usually higher than hole capture coefficient in c-Si, thus n-type c-Si has a lower minority carrier recombination rate.
  • Fig. 2A and 2B which involves homojunction solar cells 200, 220 having both front and rear diffused homojunctions with point (or line) metal contacts 204.
  • FIG. 2A illustrates full-area diffused homojunctions 202 with metal point (or line) contacts 204 and Fig. 2B illustrates local- area diffused homojunctions 222 with metal point (or line) contacts 204.
  • the second technique is illustrated in Fig. 2C which involves a heterojunction solar cell 240 having both front and rear full-area deposited heterojunctions 242 with full-area "metallic" contacts 244, consisting of transparent conductive oxide (TCO).
  • TCO transparent conductive oxide
  • surface passivation is usually achieved by providing electrically insulating passivation layers 224 which may contain a large amount of interface charges which enhance the surface passivation (field effect passivation).
  • electrically insulating passivation layers 224 which may contain a large amount of interface charges which enhance the surface passivation (field effect passivation).
  • silicon nitride, SiN x is used due to its large amount of positive interface charge.
  • Small openings are formed within this electrically insulating passivation layer 224 for metal contacts 204 to be formed therein.
  • diffused homojunction contacts i.e. either a full-area diffusion 202 is used which is locally contacted by the metal point/line contacts 204 (see Fig.
  • a local-area diffusion 222 underneath the metal point/line contacts 204 is used (see Fig. 2B).
  • the latter approach increases the open-circuit voltage potential of the solar cell 220, as there are less recombination active regions within the wafer, however at the expense of having to grow/deposit and pattern a diffusion mask.
  • a rear thin-film deposited full-area heterojunction 242 with full-area TCO contacts 244 is used (i.e., conventional heterojunction approach)
  • surface passivation is usually achieved by providing electrically conducting thin-film heterojunction layers.
  • This is typically ultra-thin film ( ⁇ 10 nm) intrinsic hydrogenated amorphous silicon, a-Si:H(i), which is further covered by thin film ( ⁇ 30 nm) p- or n-doped hydrogenated amorphous silicon (a-Si:H(p + ) or a-Si:H(n + )) in order to form the emitter and the back-surface-field (BSF) region of the solar cell 240.
  • BSF back-surface-field
  • a thin-film transparent conductive oxide (TCO) layer 244 is applied on top of the thin-film silicon layers.
  • the TCO ensures lateral conductance and also serves as an effective back reflector.
  • the metal contacts 204 are formed on top of the TCO to extract the current.
  • V oc open-circuit
  • the boron diffusion has a number of issues, including a relatively low throughput, a very high thermal budget (> 1000 °C), and a large maintenance requirement for the tube (removal of boron powder) and it is a comparatively unstable process.
  • thin-film deposited heteroj unction silicon wafer solar cells have proven to attain the highest V oc values.
  • the TCO layers which are needed to ensure a good lateral conductance as well as a good rear side reflectance, require an additional process (i.e. sputtering) and are thus adding significant cost.
  • a method of fabricating a hybrid homojunction/heterojunction solar cell comprising:
  • a passivation layer on a second side of the absorber layer, the second side being opposite to the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion; and forming a doped heterojunction contact on the second side of the absorber layer over the passivation layer for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer,
  • the step of forming the doped heterojunction contact comprises forming one or more contact openings in the passivation layer, and depositing a doped heterojunction layer over the passivation layer, the doped heterojunction layer including one or more heterojunction protruding contacts formed within respective said one or more contact openings.
  • the step of forming the homojunction contact comprises diffusing a dopant into the first side of the absorber layer to form a diffused region, and forming a first contact on the diffused region via screen printing and subsequent contact firing.
  • the step of depositing the doped heterojunction layer is performed prior to the step of forming the first contact, and portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a high temperature condition during the step of forming the first contact.
  • the step of forming the first contact is performed prior to the step of depositing the doped heterojunction layer, and portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a metal cross contamination during the step of depositing the doped heterojunction layer.
  • the contact firing is performed at a temperature of 800 °C or above.
  • the doped heterojunction layer is deposited using plasma enhanced chemical vapour deposition (PECVD) at a temperature of 350 °C or below.
  • PECVD plasma enhanced chemical vapour deposition
  • the dopant diffused into the first side of the absorber layer is phosphorus or aluminium.
  • the first contact is made of a metal or a stack of transparent conductive oxide (TCO) / metal.
  • TCO transparent conductive oxide
  • the heterojunction protruding contacts are point-like, stripe-like or grid-like in shape.
  • a percentage of the surface area of the heterojunction protruding contacts passivating a surface of the absorber layer to the total surface area passivating said surface of the absorber layer is about 3% to 20%.
  • the doped heterojunction layer comprises hydrogenated microcrystalline silicon ( c-Si:H) and the percentage is between about 4% to 6%.
  • the doped heterojunction layer comprises hydrogenated amorphous silicon (a-Si:H) and the percentage is between about 10% to 15%.
  • the passivation layer is made of silicon nitride (SiN x ) for the positive surface charge or aluminium oxide (AIO x ) for the negative surface charge.
  • the absorber layer is made of p-type or n-type crystalline silicon.
  • the doped heterojunction layer comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystalline silicon (pc-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiO x :H) / doped a-Si:H, or a stack of instrinsic a-SiO x :H / doped pc-Si:H.
  • a-Si:H doped hydrogenated amorphous silicon
  • pc-Si:H doped hydrogenated microcrystalline silicon
  • a stack of intrinsic a-Si:H / doped a-Si-H a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiO x :H)
  • the first side of the absorber layer is a front side and the second side of the absorber layer is a rear side.
  • a hybrid homojunction/heterojunction solar cell comprising:
  • an absorber layer for generating excess charge carriers of opposed polarity from light incident on a first side of the absorber layer
  • a passivation layer formed on a second side of the absorber layer, the second side being opposite to the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion; and a doped heterojunction contact formed on the second side of the absorber layer over the passivation layer for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer,
  • the passivation layer comprises one or more contact openings
  • the doped heterojunction contact comprises a doped heterojunction layer deposited over the passivation layer, the doped heterojunction layer including one or more heterojunction protruding contacts formed within respective said one or more contact openings.
  • the homojunction contact comprises a diffused region formed by diffusing a dopant into the first side of the absorber layer, and a first contact formed on the diffused region via screen printing and subsequent contact firing.
  • portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a high temperature condition during the formation of the first contact.
  • portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a metal cross contamination during the deposition of the doped heterojunction layer.
  • the dopant diffused into the first side of the absorber layer is phosphorus.
  • the first contact is made of a metal or a stack of transparent conductive oxide (TCQ) / metal
  • the heterojunction protruding contacts are point-like, stripe-like or grid-like in shape.
  • a percentage of the surface area of the heterojunction protruding contacts passivating a surface of the absorber layer to the total surface area passivating said surface of the absorber layer is about 3% to 20%.
  • the doped heterojunction layer comprises hydrogenated microcrystalline silicon ( c-Si:H) and the percentage is between about 4% to 6%.
  • the doped heterojunction layer comprises hydrogenated amorphous silicon (a-Si:H) and the percentage is between about 10% to 15%.
  • the passivation layer is made of silicon nitride (SiN x ) for the positive surface charge or aluminium oxide (AIO x ) for the negative surface charge.
  • the absorber layer is made of n-type or p-type crystalline silicon.
  • the heterjunction layer comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystalline silicon (pc-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiO x :H) / doped a-Si:H, or a stack of instrinsic a-SiO x :H / doped pc-Si:H.
  • a-Si:H doped hydrogenated amorphous silicon
  • pc-Si:H doped hydrogenated microcrystalline silicon
  • a stack of intrinsic a-Si:H / doped a-Si-H a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiO x :H)
  • the first side of the absorber layer is a front side and the second side of the absorber layer is a rear side.
  • Fig. 1 depicts a conventional homojunction solar cell
  • Fig. 2A depicts another conventional homojunction solar cell
  • Fig. 2B depicts yet another conventional homojunction solar cell
  • Fig. 2C depicts a conventional heterojunction solar cell
  • Fig. 3A depicts a hybrid homojunction/heterojunction solar cell according to an exemplary embodiment of the present invention
  • Fig. 3B depicts a hybrid homojunction/heterojunction solar cell according to another exemplary embodiment of the present invention
  • Fig. 3C depicts a hybrid homojunction/heterojunction solar cell according to yet another exemplary embodiment of the present invention
  • Fig. 4 illustrates a method of fabricating a hybrid homojunction/heterojunction solar cell according to an embodiment of the present invention
  • Fig. 5A to Fig. 5D illustrate initial steps of a method of fabrication a hybrid solar cell according to an embodiment of the present invention
  • Figs. 5E to 5H illustrate subsequent steps of the method that is able to tolerate metal cross contamination
  • Figs. 6A to 6D illustrate subsequent steps of the method that is able to tolerate a short high temperature treatment.
  • Embodiments of the present invention seek to provide an industrial viable high-efficiency hybrid homojunction/heterojunction solar cell with a homojunction contact on a first side (e.g., front side) and a heterojunction contact on a second opposing side (e.g., rear side) of the hybrid solar cell.
  • the hybrid solar cell comprises a diffused homojunction contact formation on the front side of the solar cell, and a thin-film deposited heterojunction contact formation on the rear side of the solar cell, whereby the heterojunction excess charge carrier extraction is realized by the heterojunction contact comprising one or more heterojunction protruding contacts (e.g, point-like, stripe or linelike or grid-like contacts) instead of full-area heterojunction contacts.
  • charge carrier separation of electrons or holes within the solar cell absorber is directly established by using an electrically insulating passivation layer for surface passivation, which exhibits either a large amount of positive charge (e.g., silicon nitride, SiN x ) or negative surface charge (e.g., aluminium oxide, AIO x ), thus driving the surface of the silicon wafer into strong inversion or into strong accumulation.
  • an electrically insulating passivation layer for surface passivation which exhibits either a large amount of positive charge (e.g., silicon nitride, SiN x ) or negative surface charge (e.g., aluminium oxide, AIO x ), thus driving the surface of the silicon wafer into strong inversion or into strong accumulation.
  • Charge carrier extraction is then realized by one or more local openings of the passivation layer followed by a full- area deposition of one (or several) electrical conducting thin-film heterojunction layers on top of the passivation layer, thereby forming heterojunction protruding contacts within the one or more local openings.
  • the effective doping of these thin-film heterojunction layers is opposite to the polarity of the surface charge of the passivation layer in order to be able to extract the collected excess charge carriers.
  • the heterojunction protruding contacts for excess charge carrier extraction of one type (i.e., electrons or holes) at the rear side of the solar cell is combined with a (full-area or locally) diffused homojunction contact for excess charge carrier extraction of the other type (i.e., holes or electrons) at the front side of the solar cell.
  • This hybrid solar cell architecture results in the following advantages:
  • Phosphorus diffusion (which is a robust and well established process in solar cell industry) can be used for the diffused homojunction contact formation, thereby keeping the advantage of "gettering", while omitting the problematic boron diffusion (which is a comparatively unstable process step with a very narrow process window) by using a p-doped thin-film deposited heterojunction layer instead.
  • the use of sputtered (and expensive) transparent conductive oxide layers may be avoided, thus reducing the number of process steps.
  • the standard processes used for homojunction contact formation (high temperature requirements in order to form ohmic metal/silicon contacts via screen printing) and for heterojunction contact formation (low temperature requirement, i.e. temperature ⁇ 350 °C, in order to avoid hydrogen effusion and therefore a degradation of surface passivation) are in principle not process compatible.
  • the high temperature requirement for the standard screen printed homojunction contact formation necessitates to completely finish the diffused homojunction contact by applying a high temperature contact firing (> 800 °C) before depositing the thin-film heterojunction layers.
  • a high temperature contact firing > 800 °C
  • Embodiments of the present invention seek to address the above problem(s) by using heterojunction protruding contacts (e.g, point-like, stripe or line-like, or grid-like contacts) rather than a conventional planar or full-area heterojunction contact 242 as for example illustrated in Fig. 2C.
  • This will advantageously allow for the homojunction and heterojunction contacts be formed in an industrially viable manner in such a way that either ensures (1) a process compatibility between the high temperature requirements needed ⁇ for conventional contact firing and the low temperature requirements needed for heterojunction contact formation (i.e., being able to tolerate a short high temperature treatment, or (2) a process compatibility between the front contact metallisation step and the heterojunction. layer deposition step via, e.g., PECVD (i.e., being able to tolerate metal cross contamination).
  • PECVD i.e., being able to tolerate metal cross contamination
  • the contact area percentage is about 3% to 20%. More preferably, the contact area percentage is about 4%-6% if microcrystalline silicon, ⁇ -5 ⁇ : ⁇ , is used as the thin-film deposited heterojunction layer, or about 10%-15% if amorphous silicon, a-Si:H is used..
  • a slightly worse surface passivation quality of the wafer as the majority of the wafer rear surface is passivated by an insulating passivation layer with a high positive or negative surface charge (e.g., SiN x or AIO x ).
  • a high positive or negative surface charge e.g., SiN x or AIO x
  • only about 3% to 20% of the wafer rear surface is passivated by the heterojunction protruding contacts needed for charge carrier extraction.
  • the high temperature contact firing step needed for the diffused homojunction contact formation will be performed after the deposition of the thin-film heterojunction layers (thus avoiding a metal-cross contamination during the deposition of the heterojunction layers via, e.g., PECVD, as metal deposition and contact firing will be applied after the heterojunction layer deposition).
  • the high temperature treatment during contact firing process will degrade the surface passivation quality of the wafer only at the portions interfaced with the heterojunction layer (i.e., with the surface of the heterojunction protruding contacts facing the wafer), but not outside these portions.
  • this advantageously allows the heterojunction contact formation process to (a) omit the intrinsic amorphous silicon buffer layer deposition and/or (b) deposit a microcrystalline silicon layer instead of an amorphous silicon layer as a doped thin-film layer.
  • the diffused homojunction contact formation is finished first (including contact firing), so that the heterojunction layers will not face any detrimental high temperature treatments. Instead, the heterojunction layers will face a metal cross contamination during the PECVD deposition process, as the finished metallized homojunction contacts will also have to enter into the PECVD deposition process. However, by forming the heterojunction protruding contacts, this metal cross contamination (which also leads to a degradation of surface passivation) can be tolerated for the same reasons as described above.
  • the insulating passivation layers e.g., SiN x or AIO x
  • the heterojunction layer i.e., the surface of the heterojunction protruding contacts facing the wafer
  • a hybrid homojunction/heterojunction solar cell 300 will now be described with reference to Fig. 3A according to an exemplary embodiment of the present invention.
  • the hybrid solar cell 300 comprises a silicon wafer or substrate 302 (i.e., absorber layer for generating excess charge carriers of opposed polarity from light incident on a front side 304 of the absorber layer), a homojunction contact 306 formed on a first side (e.g., front side) 304 of the wafer 302 for extracting generated excess charge carrier of a first polarity (e.g., electrons or holes), and a heterojunction contact 308 formed on a second side (e.g., rear side) 310 of the wafer 302 for extracting generated excess charge carrier of a second polarity (e.g., holes or electrons).
  • a silicon wafer or substrate 302 i.e., absorber layer for generating excess charge carriers of opposed polarity from light incident on a front side 304 of the absorber layer
  • a homojunction contact 306 formed on a first side (e.g., front side) 304 of the wafer 302 for extracting generated excess charge carrier of a first
  • the hybrid solar cell 300 further comprises a passivation layer 312 formed on the rear side 310 of the wafer 302 with one or more contact openings 314.
  • the passivation layer 312 exhibiting a surface charge of positive or negative polarity for driving the rear side 310 of the wafer 302 into charge carrier accumulation or into charge carrier inversion.
  • the heterojunction contact 308 comprises a doped heterojunction layer 315 deposited over the passivation layer 312 which also fills the contact openings 314. Therefore, the doped heterojunction layer 315 includes one or more heterojunction protruding contacts 316 formed within respective said one or more contact openings 314.
  • the wafer 302 may be an n-type or a p-type crystalline silicon (c-Si). If n-type c-Si wafer 302 is used, the emitter of the solar cell will be preferably located at the rear side 3 0 (rear side minority carrier collection) in order to be able to use phosphorous diffusion for forming the diffused contact. If p-type c-Si wafer 302 is used, the emitter of the solar cell will be preferably located at the front side 304 (front side minority carrier collection) in order to be able to use phosphorous diffusion for forming the diffused contact.
  • the homojunction contact 306 is preferably a phosphorus full-area diffused homojunction as shown in Fig.
  • the passivation layer 312 is an electrically insulating passivation layer for surface passivation which exhibits either a large amount of positive or negative surface charge, thus driving the rear surface of the wafer 302 into strong inversion or into strong accumulation.
  • the rear passivation layer 312 may be made of silicon nitride (SiN x ) and the front passivation layer 318 may be made of aluminium oxide ( ⁇ ) or vice versa depending on whether it is desirable to drive the front/rear surface of the wafer 302 into strong inversion or into strong accumulation.
  • SiN x silicon nitride
  • aluminium oxide
  • the heterojunction layer 315 comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystalline silicon (pc-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiO x :H) / doped a-Si:H, or a stack of instrinsic a-SiO x :H / doped c-Si:H.
  • a-Si:H doped hydrogenated amorphous silicon
  • pc-Si:H doped hydrogenated microcrystalline silicon
  • a stack of intrinsic a-Si:H / doped a-Si-H a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiO x :H) / doped a-Si:H
  • a-SiO x :H
  • the doped a-Si:H or pc-Si:H is of opposite polarity to the surface charge of the rear passivation layer 312 in order to support the extraction of electrons/holes.
  • the a-Si:H or pc-Si:H is n-doped (extraction of electrons).
  • the majority of the wafer's 302 rear surface is passivated by the rear passivation layer 312, which is locally opened in a point/line/grid-like manner for example.
  • only small/minor portions of the heterojunction layer 315 i.e., surface of the heterojunction protruding contacts 316 facing the wafer 302 will be in contact with the wafer 302 and exposed to the above-mentioned undesirable process conditions.
  • the slightly worse surface passivation quality of the absorber layer 302 after a high temperature treatment or after a deposition subjected to metal cross contamination, is tolerable as compared to a full area heterojunction contact.
  • the diffused homojunction contact 306 is positioned on the front side 304 of the wafer 302, thus advantageously allow for higher short-circuit current (l sc ) as there will be no front side TCO absorption.
  • this high short-circuit current potential of the front side diffused homojunction contact 306 is further combined with the high open-circuit voltage potential of the rear side heterojunction contact 308, thus realising a hybrid solar cell 300 having both advantages of high short-circuit potential l sc and high open-circuit potential V oc .
  • the exemplary embodiment avoids the problematic Boron diffusion by using phosphorous diffusion for the front side contact, that is, the diffused front side contact will be an n-type (electron extracting) contact.
  • Fig. 3B illustrates a schematic diagram of a hybrid solar cell 320 which has the same structure as the hybrid solar cell 300 shown in Fig. 3A except that the diffused homojunction contact 322 is local-area diffused instead of full-area diffused. Furthermore, this exemplary embodiment avoids any explicit diffusion process step, as the local aluminium inter-diffusion during contact firing is used to form the local-area diffused regions 322 within the wafer 302. That is, the diffused front side contact will be an p-type (hole extracting) contact.
  • parts/components which are the same as those in the hybrid solar cell 300 of Fig. 3A are indicated by the same reference numbers, and may have the same construction and same function, unless otherwise specified.
  • Fig. 3B parts/components which are the same as those in the hybrid solar cell 300 of Fig. 3A are indicated by the same reference numbers, and may have the same construction and same function, unless otherwise specified.
  • Fig. 3B parts/components which are the same as those in the hybrid solar
  • FIG. 3C illustrates a schematic diagram of a hybrid solar cell 340 which has the same structure as the hybrid solar cell 320 shown in Fig. 3B with the exception of the rear side metallisation.
  • the rear side metallisation is realised in the form of a metal grid 342 instead of a full area metal contact 319 as shown in Fig. 3B.
  • parts/components which are the same as those in the hybrid solar cell 320 of Fig. 3B are indicated by the same reference numbers, and may have the same construction and same function, unless otherwise specified.
  • the method 400 comprises a step 402 of providing an absorber layer 302 for generating excess charge carriers of opposed polarity from light incident on a first side (e.g., front side) 304 of the absorber layer 302, a step 404 of forming a homojunction contact 306 on the first side of the absorber layer 302 for extracting generated excess charge carrier of a first polarity, a step 406 of forming a passivation layer on a second side (e.g., rear side) of the absorber layer, the second side being opposite the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion, and a step 408 of forming a doped heterojunction contact 308 on the second side of the absorber layer 302 over the passivation layer 3
  • the step 408 of forming the doped heterojunction contact 308 comprises forming one or more contact openings 314 in the passivation layer 312, and depositing a doped heteroj unction layer 315 over the passivation layer 312, the heterojunction layer 315 including one or more heterojunction protruding contacts 316 formed within respective said one or more contact openings 314.
  • Figs. 5A to 5H and Figs. 6A to 6D the method 400 of fabricating a hybrid solar cell 300 will now be described in further details with reference to Figs. 5A to 5H and Figs. 6A to 6D according to an exemplary embodiment of the present invention.
  • the method 400 is not limited to the steps described hereinafter and furthermore, the steps may be performed in a different order than those described unless specifically stated otherwise.
  • parts/components which are the same as those in the hybrid solar cell 300 of Fig. 3A are indicated by the same reference numbers, and may have the same construction and same function, unless otherwise specified.
  • an n-type crystalline silicon wafer (c-Si) 302 is first provided as shown in Fig. 5A. Subsequently, a full-area diffused homojunction 306 is formed on the wafer 302 by phosphorous diffusion as shown in Fig. 5B.
  • Fig. 5C illustrates a front passivation layer 317 deposited on the diffused homojunction 306 using the plasma-enhanced chemical vapour deposition (PEVCD) process.
  • Fig. 5D illustrates a rear passivation layer 312 deposited on the rear side 310 of the wafer 302.
  • the front passivation layer 3 7 is SiN x for driving the front surface of the wafer 302 into accumulation (supporting the extraction of electrons) and the rear passivation layer 312 is AIO x for driving the rear surface of the wafer 302 into inversion (supporting the extraction of holes).
  • the rear passivation layer 312 it will be appreciated that a stack of AIO x /SiN x may be used and still be referred to as an AIO x passivation layer.
  • the method 400 proceeds depending on whether the above-mentioned process that is able to tolerate a short high temperature treatment according to the first embodiment or the other above-mentioned process that is able to tolerate metal cross contamination according to the second embodiment is selected or adopted.
  • Figs. 5E to 5H illustrate the case where the process according to the second embodiment is adopted.
  • front side metallisation is performed to form a metal contact 318 on the front side 304 of the wafer 302 using screen printing followed by a high temperature contact firing (about 800°C or higher for less than a minute).
  • contact holes 314 are formed in the rear passivation layer 312 by, for example, laser opening.
  • a p-doped heterojunction layer 315 is deposited via PECVD over the full area of the rear passivation layer 312 as shown in Fig. 5H for the extraction of holes.
  • the p-doped heterojunction layer 315 may be a thin- film layer in the form of a stack of intrinsic a-Si:H / p-doped a-Si:H, or intrinsic a-SiO x :H / p-doped a-Si:H, or intrinsic a-SiO x :H / p-doped pc-Si:H or just a single layer of p-doped a-Si:H or p-doped pc-Si:H. As shown in Fig.
  • a rear side metallisation is performed to form a metal contact 319 on the rear side 310 of the wafer 302 using screen printing followed by a low temperature contact firing (about 350°C or lower).
  • the rear metal contact 319 may be a metal or a stack of TCO/metal.
  • the front side metallisation is performed prior to the deposition of the heterojunction layer
  • this embodiment accepts metal cross contamination on the surface of the heterojunction protruding contacts 316 during thin-film silicon PECVD deposition. This can be tolerated as the expected degradation of surface passivation is restricted to only the surface of the heterojunction protruding contacts 316 facing the wafer 302, which has significantly less area than a full area heterojunction contact as for example illustrated in Fig. 2C.
  • Figs. 6A to 6D illustrate the case where the process according to the first embodiment is adopted.
  • contact holes 314 are formed on the rear passivation layer 312 by, for example, laser opening. Subsequently, to form the heterojunction protruding contacts
  • a p-doped heterojunction layer 315 is deposited over the full area of the rear passivation layer 408 as shown in Fig. 6B.
  • front side metallisation is performed to form the metal contacts 318 on the front side 304 of the wafer 302 using screen printing followed by a subsequent high temperature contact firing (about 800°C or higher). That is, the front side metallisation is performed after the deposition of the heterojunction layer 315 via PECVD.
  • a rear-side metallisation is performed to form the metal contacts 319 using screen printing followed by a subsequent low temperature contact firing (about 350°C or lower).
  • the rear metal contact 319 may be a metal or a stack of TCO/metal. Therefore, this embodiment avoids metal cross contamination by depositing the heterojunction layer 315 before the front-contact metallisation.
  • the expected degradation of surface passivation of the heterojunction layer 315 due to the high temperature treatment during contact firing can be tolerated as it is restricted to only the surface of the heterojunction protruding contacts 316 facing the wafer 302, which has significantly less area than a full area heterojunction contact.
  • both the front and rear side metal contacts 318, 319 can be also formed in one high-temperature process step (co-firing at about 800°C or higher), thereby tolerating a severe decrease of the heterojunction passivation quality within the regions of the heterojunction protruding contacts facing the wafer 302 due to the high temperature treatment.
  • This process is still understood to be better than conventional homojunction contact formations as shown in Figs. 2A and 2B, as there are less recombination active regions underneath the contacts and the contact recombination is suppressed more effectively if heterojunction layers are used.
  • embodiments of the present invention provide an industrial viable high- efficiency hybrid solar cell with a homojunction contact on one side (e.g., front side) and a heterojunction contact on an opposing side (e.g., rear side) of the hybrid solar cell.
  • the hybrid solar cells according to exemplary embodiments of the present invention is able to combine the advantages of diffused homojunction solar cells (high short-circuit current potential), with the advantages of thin-film deposited heterojunction solar cells (high open-circuit voltage potential), while at the same time allowing for conventional (high temperature) screen printing for the front contact formation.
  • a process compatibility between the conventional high temperature requirement for homojunction contact formation (contact firing) and the low temperature requirement for conventional heterojunction contact formation can be ensured, or a process compatibility between a finished front-contact metallisation and a thin-film PECVD heterojunction deposition (requiring to avoid metal cross contamination) can be ensured.
  • preferred embodiments make use of the robust phosphorus diffusion step for forming the diffused homojunction which avoids the problematic boron diffusion step used in conventional homojunction contact formation. This advantageously increases the bulk lifetime of the wafer ("gettering").
  • preferred embodiments do not necessarily require any costly TCO layer, which is usually needed in the formation of a full-area heterojunction contact.
  • the rear passivation layer is able to serve as an efficient back reflector, so that a metal layer can be directly applied on top of the thin film deposited heterojunction layers. This is not the case if full-area heterojunction back contacts are used instead, as a silicon/metal contact is a poor optical back reflector.
  • the doped heterojunction layer by using microcrystalline silicon, pc-Si:H, instead of amorphous silicon, a-Si:H, thus accepting a worse passivation quality but instead enabling a higher doping efficiency in order to realise a lower series resistance of the solar cell (due to its worse passivation quality ⁇ - Si:H cannot be used if full-area heterojunction contacts are used). It is also possible to omit the deposition of a thin-film intrinsic amorphous buffer layer prior to the doped layer deposition, in order to minimise process steps (which also cannot be achieved if using full-area heterojunction contacts are used).
  • the hybrid solar cell as described hereinbefore advantageously allows most of the currently used production equipments for standard solar cell production to be maintained, i.e. conventional phosphorus diffusion and conventional contact firing through an insulation layer (SiN x or AIO x ) may still be applied.
  • This enables the hybrid solar cell to be fabricated in an industrially viable manner.
  • a pure heterojunction solar cell i.e., front and rear heterojunction contacts
  • photovoltaic manufacturers would have to replace most of their existing equipments.
  • the heterojunction protruding contacts enable an even higher open-circuit potential (Voc) compared to the conventional full-area heterojunction contact. This is because the highly recombination active thin-film heterojunction layer(s) are decoupled from the wafer except at the heterojunction protruding contacts.

Abstract

There is provided a method of fabricating a hybrid homojunction/heterojunction solar cell. The method includes providing an absorber layer for generating excess charge carriers of opposed polarity from light incident on a first side of the absorber layer; forming a homojunction contact on the first side of the absorber layer for extracting generated excess charge carrier of a first polarity; forming a passivation layer on a second side of the absorber layer, the second side being opposite to the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion; and forming a doped heterojunction contact on the second side of the absorber layer over the passivation layer for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer, wherein the step of forming the doped heterojunction contact comprises forming one or more contact openings in the passivation layer, and depositing a doped heterojunction layer over the passivation layer, the doped heterojunction layer including one or more heterojunction protruding contacts formed within respective said one or more contact openings. There is also provided a corresponding hybrid homojunction/heterojunction solar cell.

Description

HYBRID SOLAR CELL AND METHOD OF FABRICATING THEREOF
FIELD OF INVENTION
The invention relates to a hybrid solar cell and a method of fabricating thereof, and more particularly, a hybrid homojunction/heterojunction solar cell (i.e., with homojunction and heterojunction contacts). BACKGROUND
A conventional industrial silicon wafer solar cell 100 is shown in Fig. 1. Usually, a p-type silicon (Si) wafer 102 is used. Excess charge carrier separation is achieved by a front side full-area diffused p/n+ homojunction (emitter layer for minority carrier collection) 104 with point (or line) metal contacts 106, and a rear side full-area diffused p/p+ homojunction (back-surface field (BSF) layer for majority carrier collection) 108 with a full-area Al metal contact 110. A passivation layer 112 made of silicon nitride (SiNx) is deposited on the front side diffused homojunction 104. For example, the front side p/n+ diffused homojunction 104 may be a phosphorus diffused crystalline silicon (Ph-diffused c-Si(n+)) and the rear side p/p+ diffused homojunction 08 may be an aluminium diffused crystalline silicon (Al-diffused c-Si(p+)). The front side and rear side homojunctions 104, 108 are each formed by a high-temperature thermal diffusion process and a high- temperature contact firing. In order to efficiently collect the generated minority carriers (electrons), the emitter (i.e., the p/n junction) 104 is located at the front side of the solar cell 100.
In order to improve the cell efficiency, the use of n-type Si wafers is generally proposed. Thus the light-induced degradation observed in p-type Cz silicon (due to metastable boron-oxygen complexes) can be avoided, and furthermore, higher open-circuit voltages can be reached. This is because electron capture coefficient is usually higher than hole capture coefficient in c-Si, thus n-type c-Si has a lower minority carrier recombination rate. Conventionally, there are generally two techniques of improving efficiency for a front-contacted solar cell. The first technique is illustrated in Figs. 2A and 2B which involves homojunction solar cells 200, 220 having both front and rear diffused homojunctions with point (or line) metal contacts 204. Fig. 2A illustrates full-area diffused homojunctions 202 with metal point (or line) contacts 204 and Fig. 2B illustrates local- area diffused homojunctions 222 with metal point (or line) contacts 204. The second technique is illustrated in Fig. 2C which involves a heterojunction solar cell 240 having both front and rear full-area deposited heterojunctions 242 with full-area "metallic" contacts 244, consisting of transparent conductive oxide (TCO).
If a rear diffused homojunction with metal point/line contacts 204 is used (i.e., conventional homojunction approach), surface passivation is usually achieved by providing electrically insulating passivation layers 224 which may contain a large amount of interface charges which enhance the surface passivation (field effect passivation). Typically silicon nitride, SiNx, is used due to its large amount of positive interface charge. Small openings are formed within this electrically insulating passivation layer 224 for metal contacts 204 to be formed therein. There are two types of diffused homojunction contacts, i.e. either a full-area diffusion 202 is used which is locally contacted by the metal point/line contacts 204 (see Fig. 2A), or a local-area diffusion 222 underneath the metal point/line contacts 204 is used (see Fig. 2B). The latter approach increases the open-circuit voltage potential of the solar cell 220, as there are less recombination active regions within the wafer, however at the expense of having to grow/deposit and pattern a diffusion mask.
If a rear thin-film deposited full-area heterojunction 242 with full-area TCO contacts 244 is used (i.e., conventional heterojunction approach), surface passivation is usually achieved by providing electrically conducting thin-film heterojunction layers. This is typically ultra-thin film (< 10 nm) intrinsic hydrogenated amorphous silicon, a-Si:H(i), which is further covered by thin film (< 30 nm) p- or n-doped hydrogenated amorphous silicon (a-Si:H(p+) or a-Si:H(n+)) in order to form the emitter and the back-surface-field (BSF) region of the solar cell 240. In order to form the full-area contacts, a thin-film transparent conductive oxide (TCO) layer 244 is applied on top of the thin-film silicon layers. The TCO ensures lateral conductance and also serves as an effective back reflector. The metal contacts 204 are formed on top of the TCO to extract the current. However, despite the success of these two approaches, both of them have disadvantages. For example, conventional diffused homojunction silicon wafer solar cells suffer from a comparatively low open-circuit (Voc) potential, due to (i) diffused regions within the wafer, which are also regions of enhanced recombination, and (ii) high contact recombination, as the metallic contact is directly touching the solar cell absorber. Furthermore, there is a technological obstruction concerning the boron p+ diffusion. The boron diffusion has a number of issues, including a relatively low throughput, a very high thermal budget (> 1000 °C), and a large maintenance requirement for the tube (removal of boron powder) and it is a comparatively unstable process. In comparison, thin-film deposited heteroj unction silicon wafer solar cells have proven to attain the highest Voc values. However, especially the TCO layers, which are needed to ensure a good lateral conductance as well as a good rear side reflectance, require an additional process (i.e. sputtering) and are thus adding significant cost. In addition, due to parasitic absorptions in the TCO, and the need for specialized low temperature compatible screen printed pastes, it is difficult to achieve high short-circuit current density (Jsc) and fill factors (FF) in heterojunction silicon solar cells that feature a front side contact.
On the other hand, combining the above two approaches (homojunction and heterojunction solar cells architectures) using standard industrial processes would encounter severe drawbacks. This is because the standard processes used for homojunction contact formation and heterojunction contact formation are in principle not process compatible. The standard homojunction contact formation (using screen printing) requires a high temperature process step (contact firing at temperature (T) > 800°C) in order to assure a low resistive ohmic contact of the metal grid to the silicon wafer. Contrary, thin-film deposited heterojunction layers cannot withstand temperatures above 350 °C because at elevated temperatures hydrogen starts to effuse out of the thin-film layers, which is correlated with a significant degradation of surface passivation (leading to a significant drop in the open-circuit voltage and thus in solar cell efficiency). Therefore the high temperature requirement for standard screen printed homojunction contact formation necessitates to completely finish the diffused homojunction contact before depositing the thin-film heterojunction layers. However, this would in turn create a problem that metallized layers will have to enter in the plasma enhanced chemical vapour deposition (PECVD) chamber used for the thin-film heterojunction layer deposition. This is again not compatible with the high surface passivation requirements of the thin-film PECVD layer deposition processes, as the metal cross contamination during the PECVD process will spoil the high-quality surface passivation of intrinsic amorphous silicon, which is usually used as a buffer layer in order to ensure highest surface passivation (again leading to a significant drop in the open-circuit voltage and thus in solar cell efficiency). Furthermore, the rear side TCO contact cannot be omitted using a full-area metallisation directly contacting the heterojunction layer asan a- Si:H/metal contact is a poor rear side reflector. Thus, there is presently no industrial viable hybrid (homojunction/heterojunction) solar cell architecture available, which could combine the advantages of heterojunction contact formation (i.e. higher open circuit voltage, no Boron diffusion) with the advantages of homojunction contact formation (i.e. no TCO contact and thus a higher short-circuit current).
It is against this background that the present invention has been developed. SUMMARY
According to a first aspect of the present invention, there is provided a method of fabricating a hybrid homojunction/heterojunction solar cell, comprising:
providing an absorber layer for generating excess charge carriers of opposed _ polarity from light incident on a first side of the absorber layer;
forming a homojunction contact on the first side of the absorber layer for extracting generated excess charge carrier of a first polarity;
forming a passivation layer on a second side of the absorber layer, the second side being opposite to the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion; and forming a doped heterojunction contact on the second side of the absorber layer over the passivation layer for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer,
wherein the step of forming the doped heterojunction contact comprises forming one or more contact openings in the passivation layer, and depositing a doped heterojunction layer over the passivation layer, the doped heterojunction layer including one or more heterojunction protruding contacts formed within respective said one or more contact openings.
Preferably, the step of forming the homojunction contact comprises diffusing a dopant into the first side of the absorber layer to form a diffused region, and forming a first contact on the diffused region via screen printing and subsequent contact firing.
In an embodiment, the step of depositing the doped heterojunction layer is performed prior to the step of forming the first contact, and portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a high temperature condition during the step of forming the first contact. In another embodiment, the step of forming the first contact is performed prior to the step of depositing the doped heterojunction layer, and portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a metal cross contamination during the step of depositing the doped heterojunction layer.
Preferably, the contact firing is performed at a temperature of 800 °C or above.
Preferably, the doped heterojunction layer is deposited using plasma enhanced chemical vapour deposition (PECVD) at a temperature of 350 °C or below.
Preferably, the dopant diffused into the first side of the absorber layer is phosphorus or aluminium.
Preferably, the first contact is made of a metal or a stack of transparent conductive oxide (TCO) / metal.
Preferably, the heterojunction protruding contacts are point-like, stripe-like or grid-like in shape. Preferably, a percentage of the surface area of the heterojunction protruding contacts passivating a surface of the absorber layer to the total surface area passivating said surface of the absorber layer is about 3% to 20%. In an embodiment, the doped heterojunction layer comprises hydrogenated microcrystalline silicon ( c-Si:H) and the percentage is between about 4% to 6%. In another embodiment, the doped heterojunction layer comprises hydrogenated amorphous silicon (a-Si:H) and the percentage is between about 10% to 15%. Preferably, the passivation layer is made of silicon nitride (SiNx) for the positive surface charge or aluminium oxide (AIOx) for the negative surface charge.
Preferably, the absorber layer is made of p-type or n-type crystalline silicon. Preferably, the doped heterojunction layer comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystalline silicon (pc-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiOx:H) / doped a-Si:H, or a stack of instrinsic a-SiOx:H / doped pc-Si:H.
Preferably, the first side of the absorber layer is a front side and the second side of the absorber layer is a rear side.
According to a second aspect of the present invention, there is provided a hybrid homojunction/heterojunction solar cell comprising:
an absorber layer for generating excess charge carriers of opposed polarity from light incident on a first side of the absorber layer;
a homojunction contact formed on the first side of the absorber layer for extracting generated excess charge carrier of a first polarity;
a passivation layer formed on a second side of the absorber layer, the second side being opposite to the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion; and a doped heterojunction contact formed on the second side of the absorber layer over the passivation layer for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer,
wherein the passivation layer comprises one or more contact openings, and the doped heterojunction contact comprises a doped heterojunction layer deposited over the passivation layer, the doped heterojunction layer including one or more heterojunction protruding contacts formed within respective said one or more contact openings.
Preferably, the homojunction contact comprises a diffused region formed by diffusing a dopant into the first side of the absorber layer, and a first contact formed on the diffused region via screen printing and subsequent contact firing.
In an embodiment, portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a high temperature condition during the formation of the first contact. In another embodiment, portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a metal cross contamination during the deposition of the doped heterojunction layer. Preferably, the dopant diffused into the first side of the absorber layer is phosphorus.
Preferably, the first contact is made of a metal or a stack of transparent conductive oxide (TCQ) / metal Preferably, the heterojunction protruding contacts are point-like, stripe-like or grid-like in shape. Preferably, a percentage of the surface area of the heterojunction protruding contacts passivating a surface of the absorber layer to the total surface area passivating said surface of the absorber layer is about 3% to 20%. In an embodiment, the doped heterojunction layer comprises hydrogenated microcrystalline silicon ( c-Si:H) and the percentage is between about 4% to 6%. In another embodiment, the doped heterojunction layer comprises hydrogenated amorphous silicon (a-Si:H) and the percentage is between about 10% to 15%. Preferably, the passivation layer is made of silicon nitride (SiNx) for the positive surface charge or aluminium oxide (AIOx) for the negative surface charge.
Preferably, the absorber layer is made of n-type or p-type crystalline silicon. Preferably, the heterjunction layer comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystalline silicon (pc-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiOx:H) / doped a-Si:H, or a stack of instrinsic a-SiOx:H / doped pc-Si:H.
Preferably, the first side of the absorber layer is a front side and the second side of the absorber layer is a rear side.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which: Fig. 1 depicts a conventional homojunction solar cell;
Fig. 2A depicts another conventional homojunction solar cell;
Fig. 2B depicts yet another conventional homojunction solar cell; Fig. 2C depicts a conventional heterojunction solar cell;
Fig. 3A depicts a hybrid homojunction/heterojunction solar cell according to an exemplary embodiment of the present invention;
Fig. 3B depicts a hybrid homojunction/heterojunction solar cell according to another exemplary embodiment of the present invention; Fig. 3C depicts a hybrid homojunction/heterojunction solar cell according to yet another exemplary embodiment of the present invention;
Fig. 4 illustrates a method of fabricating a hybrid homojunction/heterojunction solar cell according to an embodiment of the present invention;
Fig. 5A to Fig. 5D illustrate initial steps of a method of fabrication a hybrid solar cell according to an embodiment of the present invention;
Figs. 5E to 5H illustrate subsequent steps of the method that is able to tolerate metal cross contamination; and
Figs. 6A to 6D illustrate subsequent steps of the method that is able to tolerate a short high temperature treatment. DETAILED DESCRIPTIO
Embodiments of the present invention seek to provide an industrial viable high-efficiency hybrid homojunction/heterojunction solar cell with a homojunction contact on a first side (e.g., front side) and a heterojunction contact on a second opposing side (e.g., rear side) of the hybrid solar cell. In exemplary embodiments, the hybrid solar cell comprises a diffused homojunction contact formation on the front side of the solar cell, and a thin-film deposited heterojunction contact formation on the rear side of the solar cell, whereby the heterojunction excess charge carrier extraction is realized by the heterojunction contact comprising one or more heterojunction protruding contacts (e.g, point-like, stripe or linelike or grid-like contacts) instead of full-area heterojunction contacts.
With the heterojunction protruding contacts according to the exemplary embodiment, charge carrier separation of electrons or holes within the solar cell absorber is directly established by using an electrically insulating passivation layer for surface passivation, which exhibits either a large amount of positive charge (e.g., silicon nitride, SiNx) or negative surface charge (e.g., aluminium oxide, AIOx), thus driving the surface of the silicon wafer into strong inversion or into strong accumulation. Charge carrier extraction is then realized by one or more local openings of the passivation layer followed by a full- area deposition of one (or several) electrical conducting thin-film heterojunction layers on top of the passivation layer, thereby forming heterojunction protruding contacts within the one or more local openings. The effective doping of these thin-film heterojunction layers is opposite to the polarity of the surface charge of the passivation layer in order to be able to extract the collected excess charge carriers. With the heterojunction protruding contacts, since no diffused area is formed underneath the metal contacts, it enables the solar cell to reach higher open-circuit voltages due to reduced contact and bulk recombination. In the exemplary embodiment, the heterojunction protruding contacts for excess charge carrier extraction of one type (i.e., electrons or holes) at the rear side of the solar cell is combined with a (full-area or locally) diffused homojunction contact for excess charge carrier extraction of the other type (i.e., holes or electrons) at the front side of the solar cell. This hybrid solar cell architecture results in the following advantages:
(1) The high short-circuit potential lsc of a diffused homojunction solar cell can be exploited.
(2) The high open-circuit potential Voc of a heterojunction solar cell can be exploited.
(3) Phosphorus diffusion (which is a robust and well established process in solar cell industry) can be used for the diffused homojunction contact formation, thereby keeping the advantage of "gettering", while omitting the problematic boron diffusion (which is a comparatively unstable process step with a very narrow process window) by using a p-doped thin-film deposited heterojunction layer instead. (4) The use of sputtered (and expensive) transparent conductive oxide layers may be avoided, thus reducing the number of process steps.
(5) Most of the currently used production equipments at photovoltaic cell manufacturers can be maintained, while still exploiting the advantages of using heterojunctions for solar cell contact formation (i.e. achieving high Voc).
As described in the background, the standard processes used for homojunction contact formation (high temperature requirements in order to form ohmic metal/silicon contacts via screen printing) and for heterojunction contact formation (low temperature requirement, i.e. temperature < 350 °C, in order to avoid hydrogen effusion and therefore a degradation of surface passivation) are in principle not process compatible. The high temperature requirement for the standard screen printed homojunction contact formation necessitates to completely finish the diffused homojunction contact by applying a high temperature contact firing (> 800 °C) before depositing the thin-film heterojunction layers. However, this would in turn create a problem that metallized layers will have to enter in the plasma enhanced chemical vapour deposition (PECVD) chamber used for the thin-film heterojunction layer deposition. This is again not compatible with the high surface passivation requirements of the thin-film PECVD layer deposition processes, as a metal cross contamination during the PECVD process will spoil the high-quality surface passivation of intrinsic amorphous silicon, which is usually used as a buffer layer in order to ensure highest surface passivation.
Embodiments of the present invention seek to address the above problem(s) by using heterojunction protruding contacts (e.g, point-like, stripe or line-like, or grid-like contacts) rather than a conventional planar or full-area heterojunction contact 242 as for example illustrated in Fig. 2C. This will advantageously allow for the homojunction and heterojunction contacts be formed in an industrially viable manner in such a way that either ensures (1) a process compatibility between the high temperature requirements needed^for conventional contact firing and the low temperature requirements needed for heterojunction contact formation (i.e., being able to tolerate a short high temperature treatment, or (2) a process compatibility between the front contact metallisation step and the heterojunction. layer deposition step via, e.g., PECVD (i.e., being able to tolerate metal cross contamination).
The use of heterojunction protruding contacts instead of full-area contacts significantly reduces the contact area of the heterojunction layer with the wafer (i.e., absorber) surface. In a preferred embodiment, the contact area percentage is about 3% to 20%. More preferably, the contact area percentage is about 4%-6% if microcrystalline silicon, ο-5ϊ:Η, is used as the thin-film deposited heterojunction layer, or about 10%-15% if amorphous silicon, a-Si:H is used.. Thus, according to exemplary embodiments, it is possible to accept a slightly worse surface passivation quality of the wafer as the majority of the wafer rear surface is passivated by an insulating passivation layer with a high positive or negative surface charge (e.g., SiNx or AIOx). For example, in an embodiment, only about 3% to 20% of the wafer rear surface is passivated by the heterojunction protruding contacts needed for charge carrier extraction.
The above-mentioned process that is able to tolerate a short high temperature treatment will now be further described according to a first embodiment of the present invention. In this process, the high temperature contact firing step needed for the diffused homojunction contact formation will be performed after the deposition of the thin-film heterojunction layers (thus avoiding a metal-cross contamination during the deposition of the heterojunction layers via, e.g., PECVD, as metal deposition and contact firing will be applied after the heterojunction layer deposition). The high temperature treatment during contact firing process will degrade the surface passivation quality of the wafer only at the portions interfaced with the heterojunction layer (i.e., with the surface of the heterojunction protruding contacts facing the wafer), but not outside these portions. This is because the insulating passivation layers (e.g., SiNx or AIOx) are configured to withstand a high temperature contact firing. Therefore, this will result in a tolerable degradation of the surface passivation of the wafer as a whole as it is restricted to the portions of the wafer interfaced with the surface of the heterojunction protruding contacts. In certain embodiments, this advantageously allows the heterojunction contact formation process to (a) omit the intrinsic amorphous silicon buffer layer deposition and/or (b) deposit a microcrystalline silicon layer instead of an amorphous silicon layer as a doped thin-film layer. Both processes (a) and (b) lead to enhanced surface recombination (which cannot be accepted in the case of full-area heterojunction contacts but which can be accepted in the case of heterojunction protruding contacts). After a short high temperature treatment as needed for contact firing, the surface recombination of both processes (a) and (b) will be of substantially the same order of magnitude. However, process (a) requires less process steps and process (b) enables a higher doping efficiency for the doped thin-film layer, which in turn leads to a lower series resistance of the solar cell. The other above-mentioned process that is able to tolerate metal cross contamination will now be further described according to a second embodiment of the present invention. In this process, the diffused homojunction contact formation is finished first (including contact firing), so that the heterojunction layers will not face any detrimental high temperature treatments. Instead, the heterojunction layers will face a metal cross contamination during the PECVD deposition process, as the finished metallized homojunction contacts will also have to enter into the PECVD deposition process. However, by forming the heterojunction protruding contacts, this metal cross contamination (which also leads to a degradation of surface passivation) can be tolerated for the same reasons as described above. That is, the insulating passivation layers (e.g., SiNx or AIOx) will be able to protect large portions of the wafer from metal cross contamination, and only the portions of the wafer interfaced with the heterojunction layer (i.e., the surface of the heterojunction protruding contacts facing the wafer) will be vulnerable to the metal cross contamination. For illustration purposes and clarity, a hybrid homojunction/heterojunction solar cell 300 will now be described with reference to Fig. 3A according to an exemplary embodiment of the present invention.
In the exemplary embodiment, the hybrid solar cell 300 comprises a silicon wafer or substrate 302 (i.e., absorber layer for generating excess charge carriers of opposed polarity from light incident on a front side 304 of the absorber layer), a homojunction contact 306 formed on a first side (e.g., front side) 304 of the wafer 302 for extracting generated excess charge carrier of a first polarity (e.g., electrons or holes), and a heterojunction contact 308 formed on a second side (e.g., rear side) 310 of the wafer 302 for extracting generated excess charge carrier of a second polarity (e.g., holes or electrons). The hybrid solar cell 300 further comprises a passivation layer 312 formed on the rear side 310 of the wafer 302 with one or more contact openings 314. The passivation layer 312 exhibiting a surface charge of positive or negative polarity for driving the rear side 310 of the wafer 302 into charge carrier accumulation or into charge carrier inversion. The heterojunction contact 308 comprises a doped heterojunction layer 315 deposited over the passivation layer 312 which also fills the contact openings 314. Therefore, the doped heterojunction layer 315 includes one or more heterojunction protruding contacts 316 formed within respective said one or more contact openings 314.
The wafer 302 may be an n-type or a p-type crystalline silicon (c-Si). If n-type c-Si wafer 302 is used, the emitter of the solar cell will be preferably located at the rear side 3 0 (rear side minority carrier collection) in order to be able to use phosphorous diffusion for forming the diffused contact. If p-type c-Si wafer 302 is used, the emitter of the solar cell will be preferably located at the front side 304 (front side minority carrier collection) in order to be able to use phosphorous diffusion for forming the diffused contact. The homojunction contact 306 is preferably a phosphorus full-area diffused homojunction as shown in Fig. 3A (thus avoiding the problematic boron diffusion process), or a locally aluminium inter-diffused homojunction as shown in Figs. 3B and 3C (thus avoiding any additional diffusion process, as the contact firing process will already provide the locally diffused regions). The passivation layer 312 is an electrically insulating passivation layer for surface passivation which exhibits either a large amount of positive or negative surface charge, thus driving the rear surface of the wafer 302 into strong inversion or into strong accumulation. There is also another passivation layer 317 deposited on the homojunction contact 306. For example, the rear passivation layer 312 may be made of silicon nitride (SiNx) and the front passivation layer 318 may be made of aluminium oxide (ΑΙΟχ) or vice versa depending on whether it is desirable to drive the front/rear surface of the wafer 302 into strong inversion or into strong accumulation.
The heterojunction layer 315 comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystalline silicon (pc-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiOx:H) / doped a-Si:H, or a stack of instrinsic a-SiOx:H / doped c-Si:H. The doped a-Si:H or pc-Si:H is of opposite polarity to the surface charge of the rear passivation layer 312 in order to support the extraction of electrons/holes. For example, if the rear passivation layer 312 has a positive surface charge, the a-Si:H or pc-Si:H is n-doped (extraction of electrons).
As shown in Fig. 3A, the majority of the wafer's 302 rear surface is passivated by the rear passivation layer 312, which is locally opened in a point/line/grid-like manner for example. This allows the heterojunction layer 315 to form heterojunction protruding contacts 316 within the contact openings 314 of the rear passivation layer 312. Thus, only small/minor portions of the heterojunction layer 315 (i.e., surface of the heterojunction protruding contacts 316 facing the wafer 302) will be in contact with the wafer 302 and exposed to the above-mentioned undesirable process conditions. For example, as mentioned hereinbefore, only about 3% to 20% of the surface area of the heterojunction layer 315 facing the wafer 302 forms the heterojunction contact (i.e., 3% to 30% of the wafer rear surface is passivated by the heterojunction protruding contacts needed for charge carrier extraction), and the remaining surface area is under and protected by the rear passivation layer 312. Accordingly, the slightly worse surface passivation quality of the absorber layer 302 after a high temperature treatment or after a deposition subjected to metal cross contamination, is tolerable as compared to a full area heterojunction contact.
With the hybrid solar cell 300 as shown in Fig. 3A, the diffused homojunction contact 306 is positioned on the front side 304 of the wafer 302, thus advantageously allow for higher short-circuit current (lsc) as there will be no front side TCO absorption. According to the exemplary embodiment, this high short-circuit current potential of the front side diffused homojunction contact 306 is further combined with the high open-circuit voltage potential of the rear side heterojunction contact 308, thus realising a hybrid solar cell 300 having both advantages of high short-circuit potential lsc and high open-circuit potential Voc. Furthermore, the exemplary embodiment avoids the problematic Boron diffusion by using phosphorous diffusion for the front side contact, that is, the diffused front side contact will be an n-type (electron extracting) contact.
Fig. 3B illustrates a schematic diagram of a hybrid solar cell 320 which has the same structure as the hybrid solar cell 300 shown in Fig. 3A except that the diffused homojunction contact 322 is local-area diffused instead of full-area diffused. Furthermore, this exemplary embodiment avoids any explicit diffusion process step, as the local aluminium inter-diffusion during contact firing is used to form the local-area diffused regions 322 within the wafer 302. That is, the diffused front side contact will be an p-type (hole extracting) contact. In Fig. 3B, parts/components which are the same as those in the hybrid solar cell 300 of Fig. 3A are indicated by the same reference numbers, and may have the same construction and same function, unless otherwise specified. Fig. 3C illustrates a schematic diagram of a hybrid solar cell 340 which has the same structure as the hybrid solar cell 320 shown in Fig. 3B with the exception of the rear side metallisation. In Fig. 3C, the rear side metallisation is realised in the form of a metal grid 342 instead of a full area metal contact 319 as shown in Fig. 3B. In Fig. 3C, parts/components which are the same as those in the hybrid solar cell 320 of Fig. 3B are indicated by the same reference numbers, and may have the same construction and same function, unless otherwise specified.
A method 400 of fabricating a hybrid solar cell 300, 320, 340 according to an exemplary embodiment of the present invention will now be described with reference to Fig. 4. The method 400 comprises a step 402 of providing an absorber layer 302 for generating excess charge carriers of opposed polarity from light incident on a first side (e.g., front side) 304 of the absorber layer 302, a step 404 of forming a homojunction contact 306 on the first side of the absorber layer 302 for extracting generated excess charge carrier of a first polarity, a step 406 of forming a passivation layer on a second side (e.g., rear side) of the absorber layer, the second side being opposite the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion, and a step 408 of forming a doped heterojunction contact 308 on the second side of the absorber layer 302 over the passivation layer 312 for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer. According to the exemplary embodiment, the step 408 of forming the doped heterojunction contact 308 comprises forming one or more contact openings 314 in the passivation layer 312, and depositing a doped heteroj unction layer 315 over the passivation layer 312, the heterojunction layer 315 including one or more heterojunction protruding contacts 316 formed within respective said one or more contact openings 314.
For illustration purposes and clarity, the method 400 of fabricating a hybrid solar cell 300 will now be described in further details with reference to Figs. 5A to 5H and Figs. 6A to 6D according to an exemplary embodiment of the present invention. However, it will be appreciated that the method 400 is not limited to the steps described hereinafter and furthermore, the steps may be performed in a different order than those described unless specifically stated otherwise. In Figs. 5A to 5H and Figs. 6A to 6D, parts/components which are the same as those in the hybrid solar cell 300 of Fig. 3A are indicated by the same reference numbers, and may have the same construction and same function, unless otherwise specified.
In this exemplary embodiment, an n-type crystalline silicon wafer (c-Si) 302 is first provided as shown in Fig. 5A. Subsequently, a full-area diffused homojunction 306 is formed on the wafer 302 by phosphorous diffusion as shown in Fig. 5B. Fig. 5C illustrates a front passivation layer 317 deposited on the diffused homojunction 306 using the plasma-enhanced chemical vapour deposition (PEVCD) process. Fig. 5D illustrates a rear passivation layer 312 deposited on the rear side 310 of the wafer 302. In this exemplary embodiment, the front passivation layer 3 7 is SiNx for driving the front surface of the wafer 302 into accumulation (supporting the extraction of electrons) and the rear passivation layer 312 is AIOx for driving the rear surface of the wafer 302 into inversion (supporting the extraction of holes). For the rear passivation layer 312, it will be appreciated that a stack of AIOx/SiNx may be used and still be referred to as an AIOx passivation layer.
Thereafter, the method 400 proceeds depending on whether the above-mentioned process that is able to tolerate a short high temperature treatment according to the first embodiment or the other above-mentioned process that is able to tolerate metal cross contamination according to the second embodiment is selected or adopted. Figs. 5E to 5H illustrate the case where the process according to the second embodiment is adopted. In Fig. 5E, front side metallisation is performed to form a metal contact 318 on the front side 304 of the wafer 302 using screen printing followed by a high temperature contact firing (about 800°C or higher for less than a minute). Thereafter, as shown in Fig. 5F, contact holes 314 are formed in the rear passivation layer 312 by, for example, laser opening. Subsequently, to form the heterojunction protruding contacts 316, a p-doped heterojunction layer 315 is deposited via PECVD over the full area of the rear passivation layer 312 as shown in Fig. 5H for the extraction of holes. In certain embodiments, the p-doped heterojunction layer 315 may be a thin- film layer in the form of a stack of intrinsic a-Si:H / p-doped a-Si:H, or intrinsic a-SiOx:H / p-doped a-Si:H, or intrinsic a-SiOx:H / p-doped pc-Si:H or just a single layer of p-doped a-Si:H or p-doped pc-Si:H. As shown in Fig. 5H, a rear side metallisation is performed to form a metal contact 319 on the rear side 310 of the wafer 302 using screen printing followed by a low temperature contact firing (about 350°C or lower). For example, the rear metal contact 319 may be a metal or a stack of TCO/metal. In this embodiment, the front side metallisation is performed prior to the deposition of the heterojunction layer
315. Therefore, as the formed front-side metal contacts have to be placed within the PECVD reactor, this embodiment accepts metal cross contamination on the surface of the heterojunction protruding contacts 316 during thin-film silicon PECVD deposition. This can be tolerated as the expected degradation of surface passivation is restricted to only the surface of the heterojunction protruding contacts 316 facing the wafer 302, which has significantly less area than a full area heterojunction contact as for example illustrated in Fig. 2C. Figs. 6A to 6D illustrate the case where the process according to the first embodiment is adopted. In Fig. 6A, contact holes 314 are formed on the rear passivation layer 312 by, for example, laser opening. Subsequently, to form the heterojunction protruding contacts
316, a p-doped heterojunction layer 315 is deposited over the full area of the rear passivation layer 408 as shown in Fig. 6B. Thereafter, as shown in Fig. 6C, front side metallisation is performed to form the metal contacts 318 on the front side 304 of the wafer 302 using screen printing followed by a subsequent high temperature contact firing (about 800°C or higher). That is, the front side metallisation is performed after the deposition of the heterojunction layer 315 via PECVD. In Fig. 5D, a rear-side metallisation is performed to form the metal contacts 319 using screen printing followed by a subsequent low temperature contact firing (about 350°C or lower). For example, the rear metal contact 319 may be a metal or a stack of TCO/metal. Therefore, this embodiment avoids metal cross contamination by depositing the heterojunction layer 315 before the front-contact metallisation. The expected degradation of surface passivation of the heterojunction layer 315 due to the high temperature treatment during contact firing can be tolerated as it is restricted to only the surface of the heterojunction protruding contacts 316 facing the wafer 302, which has significantly less area than a full area heterojunction contact. In the first embodiment, both the front and rear side metal contacts 318, 319 can be also formed in one high-temperature process step (co-firing at about 800°C or higher), thereby tolerating a severe decrease of the heterojunction passivation quality within the regions of the heterojunction protruding contacts facing the wafer 302 due to the high temperature treatment. This process is still understood to be better than conventional homojunction contact formations as shown in Figs. 2A and 2B, as there are less recombination active regions underneath the contacts and the contact recombination is suppressed more effectively if heterojunction layers are used.
Accordingly, embodiments of the present invention provide an industrial viable high- efficiency hybrid solar cell with a homojunction contact on one side (e.g., front side) and a heterojunction contact on an opposing side (e.g., rear side) of the hybrid solar cell. In particular, the hybrid solar cells according to exemplary embodiments of the present invention is able to combine the advantages of diffused homojunction solar cells (high short-circuit current potential), with the advantages of thin-film deposited heterojunction solar cells (high open-circuit voltage potential), while at the same time allowing for conventional (high temperature) screen printing for the front contact formation. That is, either a process compatibility between the conventional high temperature requirement for homojunction contact formation (contact firing) and the low temperature requirement for conventional heterojunction contact formation can be ensured, or a process compatibility between a finished front-contact metallisation and a thin-film PECVD heterojunction deposition (requiring to avoid metal cross contamination) can be ensured. In addition, preferred embodiments make use of the robust phosphorus diffusion step for forming the diffused homojunction which avoids the problematic boron diffusion step used in conventional homojunction contact formation. This advantageously increases the bulk lifetime of the wafer ("gettering"). Furthermore, preferred embodiments do not necessarily require any costly TCO layer, which is usually needed in the formation of a full-area heterojunction contact. This is because the rear passivation layer is able to serve as an efficient back reflector, so that a metal layer can be directly applied on top of the thin film deposited heterojunction layers. This is not the case if full-area heterojunction back contacts are used instead, as a silicon/metal contact is a poor optical back reflector.
Contrary to using conventional full-area heterojunction contacts, it is not necessary to ensure perfect interface passivation with the heterojunction protruding contacts 316 as the percentage of the contact area (between the heterojunction protruding contacts and the wafer surface) to the total area passivating the surface of the wafer is about 3% to 20% only, such as 4% to 6% if microcrystalline silicon, MC-Si:H, is used as the thin-film deposited heterojunction layer, or about 10% to 15% if amorphous silicon, a-Si:H is used. As explained hereinbefore, this slightly higher interface recombination within these regions can be tolerated in order to ensure the above-mentioned process compatibility. Therefore it is also possible to realise the doped heterojunction layer by using microcrystalline silicon, pc-Si:H, instead of amorphous silicon, a-Si:H, thus accepting a worse passivation quality but instead enabling a higher doping efficiency in order to realise a lower series resistance of the solar cell (due to its worse passivation quality μο- Si:H cannot be used if full-area heterojunction contacts are used). It is also possible to omit the deposition of a thin-film intrinsic amorphous buffer layer prior to the doped layer deposition, in order to minimise process steps (which also cannot be achieved if using full-area heterojunction contacts are used).
The hybrid solar cell as described hereinbefore according to embodiments of the present invention advantageously allows most of the currently used production equipments for standard solar cell production to be maintained, i.e. conventional phosphorus diffusion and conventional contact firing through an insulation layer (SiNx or AIOx) may still be applied. This enables the hybrid solar cell to be fabricated in an industrially viable manner. Contrary, a pure heterojunction solar cell (i.e., front and rear heterojunction contacts) would substantially require a new pilot line including low temperature metallisation. In this case, photovoltaic manufacturers would have to replace most of their existing equipments. It has been realised that in principle, the heterojunction protruding contacts enable an even higher open-circuit potential (Voc) compared to the conventional full-area heterojunction contact. This is because the highly recombination active thin-film heterojunction layer(s) are decoupled from the wafer except at the heterojunction protruding contacts.
It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments without departing from the scope of the present invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive.

Claims

1. A method of fabricating a hybrid homojunction/heterojunction solar cell, comprising:
providing an absorber layer for generating excess charge carriers of opposed polarity from light incident on a first side of the absorber layer;
forming a home-junction contact on the first side of the absorber layer for extracting generated excess charge carrier of a first polarity;
forming a passivation layer on a second side of the absorber layer, the second side being opposite to the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion; and forming a doped heterojunction contact on the second side of the absorber layer over the passivation layer for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer,
wherein the step of forming the doped heterojunction contact comprises forming one or more contact openings in the passivation layer, and depositing a doped heterojunction layer over the passivation layer, the doped heterojunction layer including one or more heterojunction protruding contacts formed within respective said one or more contact openings.
2. The method according to claim 1 , wherein the step of forming the homojunction contact comprises diffusing a dopant into the first side of the absorber layer to form a diffused region, and forming a first contact on the diffused region via screen printing and subsequent contact firing.
3. The method according to claim 2, wherein the step of depositing the doped heterojunction layer is performed prior to the step of forming the first contact, and portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a high temperature condition during the step of forming the first contact.
4. The method according to claim 2, wherein the step of forming the first contact is performed prior to the step of depositing the doped heterojunction layer, and portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a metal cross contamination during the step of depositing the doped heterojunction layer.
5. The method according to any one of claims 2 to 4, wherein the contact firing is performed at a temperature of 800 °C or above.
6. The method according to any one of claims 2 to 5, the doped heterojunction layer is deposited using plasma enhanced chemical vapour deposition (PECVD) at a temperature of 350 °C or below.
7. The method according to any one of claims 2 to 6, wherein the dopant diffused into the first side of the absorber layer is phosphorus or aluminium.
8. The method according to any one of claims 2 to 7, wherein the first contact is made of a metal or a stack of transparent conductive oxide (TCO) / metal.
9. The method according to any one of claims 1 to 8,- wherein the heterojunction protruding contacts are point-like, stripe-like or grid-like in shape.
10. The method according to any one of claims 1 to 9, wherein a percentage of the surface area of the heterojunction protruding contacts passivating a surface of the absorber layer to the total surface area passivating said surface of the absorber layer is about 3% to 20%.
11. The method according to claim 10, wherein the doped heterojunction layer comprises hydrogenated microcrystalline silicon (MC-SI:H) and the percentage is between about 4% to 6%, or the doped heterojunction layer comprises hydrogenated amorphous silicon (a-Si:H) and the percentage is between about 10% to 15%.
12. The method according to any one of claims 1 to 11 , wherein the passivation layer is made of silicon nitride (SiNx) for the positive surface charge or aluminium oxide (AIOx) for the negative surface charge.
13. The method according to any one of claims 1 to 12, wherein the absorber layer is made of p-type or n-type crystalline silicon.
14. The method according to any one of claims 1 to 13, wherein the doped heterojunction layer comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystalline silicon ( c-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiOx:H) / doped a-Si:H, or a stack of instrinsic a-SiOx:H / doped c-Si:H.
15. The method according to any one of claims 1 to 14, wherein the first side of the absorber layer is a front side and the second side of the absorber layer is a rear side.
16. A hybrid homojunction/heterojunction solar cell comprising:
an absorber layer for generating excess charge carriers of opposed polarity from light incident on a first side of the absorber layer;
a homojunction contact formed on the first side of the absorber layer for extracting generated excess charge carrier of a first polarity;
a passivation layer formed on a second side of the absorber layer, the second side being opposite to the first side, and the passivation layer exhibiting a surface charge of positive or negative polarity for driving the second side of the absorber layer into charge carrier accumulation or into charge carrier inversion; and a doped heterojunction contact formed on the second side of the absorber layer over the passivation layer for extracting generated excess charge carrier of a second polarity, the second polarity being opposite to the first polarity, and the doped heterojunction contact being of opposite polarity to the polarity of the surface charge of the passivation layer,
wherein the passivation layer comprises one or more contact openings, and the doped heterojunction contact comprises a doped heterojunction layer deposited over the passivation layer, the doped heteroju notion layer including one or more heteroju notion protruding contacts formed within respective said one or more contact openings.
17. The hybrid solar cell according to claim 16, wherein the homojunction contact comprises a diffused region formed by diffusing a dopant into the first side of the absorber layer, and a first contact formed on the diffused region via screen printing and subsequent contact firing.
18. The hybrid solar cell according to claim 17, wherein portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a high temperature condition during the formation of the first contact.
19. The hybrid solar cell according to claim 17, wherein portions of the absorber layer interfaced with surfaces of the heterojunction protruding contacts are vulnerable to surface passivation degradation due to a metal cross contamination during the deposition of the doped heterojunction layer.
20. The hybrid solar cell according to any one of claims 17 to 19, wherein the dopant diffused into the first side of the absorber layer is phosphorus.
21 . The hybrid solar cell according to any one of claims 17 to 20, wherein the first contact is made of a metal or a stack of transparent conductive oxide (TCO) / metal.
22. The hybrid solar cell according to any one of claims 16 to 21 , wherein the heterojunction protruding contacts are point-like, stripe-like or grid-like in shape.
23. The hybrid solar cell according to any one of claims 16 to 22, wherein a percentage of the surface area of the heterojunction protruding contacts passivating a surface of the absorber layer to the total surface area passivating said surface of the absorber layer is about 3% to 20%.
24. The hybrid solar cell according to claim 23, wherein the doped heteroju notion layer comprises hydrogenated microcrystailine silicon (pc-Si:H) and the percentage is between about 4% to 6%, or the doped heteroju notion layer comprises hydrogenated amorphous silicon (a-Si:H) and the percentage is between about 10% to 15%.
25. The hybrid solar cell according to claim 24, wherein the passivation layer is made of silicon nitride (SiNx) for the positive surface charge or aluminium oxide (AIOx) for the negative surface charge.
26. The hybrid solar cell according to any one of claims 16 to 25, wherein the absorber layer is made of n-type or p-type crystalline silicon.
27. The hybrid solar cell according to any one of claims 16 to 26, wherein the heterjunction layer comprises one or more thin-film layers made of doped hydrogenated amorphous silicon (a-Si:H), doped hydrogenated microcrystailine silicon (pc-Si:H), a stack of intrinsic a-Si:H / doped a-Si-H, a stack of intrinsic hydrogenated amorphous silicon oxide (a-SiOx:H) / doped a-Si:H, or a stack of instrinsic a-SiOx:H / doped pc-Si:H.
28. The hybrid solar cell according to any one of claims 16 to 27, wherein the first side of the absorber layer is a front side and the second side of the absorber layer is a rear side.
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