WO2013172143A1 - Semiconductor device, display apparatus, electronic apparatus, and semiconductor device manufacturing method - Google Patents

Semiconductor device, display apparatus, electronic apparatus, and semiconductor device manufacturing method Download PDF

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WO2013172143A1
WO2013172143A1 PCT/JP2013/061364 JP2013061364W WO2013172143A1 WO 2013172143 A1 WO2013172143 A1 WO 2013172143A1 JP 2013061364 W JP2013061364 W JP 2013061364W WO 2013172143 A1 WO2013172143 A1 WO 2013172143A1
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organic semiconductor
layer
semiconductor layer
insulating layer
electrode
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PCT/JP2013/061364
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French (fr)
Japanese (ja)
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栗原　研一
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ソニー株式会社
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/60—Organic compounds having low molecular weight
    • H10K85/649—Aromatic compounds comprising a hetero atom
    • H10K85/653—Aromatic compounds comprising a hetero atom comprising only oxygen as heteroatom

Definitions

  • the technology of the present disclosure relates to a semiconductor device including an organic semiconductor layer, a display device, an electronic device, and a method for manufacturing the semiconductor device.
  • a thin film transistor which is one of semiconductor devices is used as, for example, a pixel switching element or a driving element in a display of an electronic device.
  • a thin film transistor is formed on the substrate as a switching element or a driving element.
  • those using an organic semiconductor layer as an active layer of a thin film transistor can form a thin film at a low temperature. Since the heat resistant temperature of a flexible substrate such as a plastic film tends to be lower than the heat resistant temperature of a rigid substrate such as a glass substrate, the organic semiconductor layer is particularly suitable for an active layer of a thin film transistor for a flexible substrate.
  • the thin film transistor includes an electrode bonded to the organic semiconductor layer.
  • the part where the electrode and the organic semiconductor layer are joined receives the film stress of the organic semiconductor layer and the film stress of the electrode.
  • the organic semiconductor layer and the electrode are formed of a material that hardly generates an adhesion force such as an intermolecular force or a Coulomb force between them. Therefore, part of the electrode may be peeled off from the organic semiconductor layer depending on the degree of film stress.
  • the portion where the organic semiconductor layer and the electrode are joined receives the bending stress of the flexible substrate in addition to the film stress.
  • the problem that a part of the electrode is peeled off from the organic semiconductor layer becomes more obvious.
  • One aspect of the semiconductor device in the present disclosure includes an insulating layer, an organic semiconductor layer formed on the insulating layer, and an electrode bonded to a bonding surface that is an upper surface of the organic semiconductor layer, and the bonding surface is Has irregularities.
  • One embodiment of the display device according to the present disclosure includes a thin film transistor, and the thin film transistor is bonded to an insulating layer, an organic semiconductor layer formed on the insulating layer, and a bonding surface that is an upper surface of the organic semiconductor layer.
  • the joint surface has irregularities.
  • One aspect of the electronic device in the present disclosure includes a display unit, the display unit includes a thin film transistor, the thin film transistor including an insulating layer, an organic semiconductor layer formed on the insulating layer, and the organic semiconductor layer.
  • the step of forming the organic semiconductor layer includes forming an organic semiconductor layer having irregularities on the bonding surface.
  • the bonding area between the organic semiconductor layer and the electrode is simply a flat surface between the organic semiconductor layer and the electrode. It is larger than the bonding area when bonding with. As a result, since the contact area between the organic semiconductor layer and the electrode increases and the bonding strength increases, it is possible to suppress peeling between the organic semiconductor layer and the electrode bonded thereto.
  • the bonding surface of the organic semiconductor layer formed by phase separation includes irregularities, and therefore, unnecessary substances are mixed between the insulating layer and the organic semiconductor layer.
  • the contact area between the organic semiconductor layer and the electrode can be increased while suppressing the above.
  • FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. It is a top view which shows the planar structure of the joint surface of the organic-semiconductor layer in one Embodiment.
  • FIG. 4 is a partial cross-sectional view taken along line BB in FIG. 3. It is process drawing which shows the process in which a gate electrode is formed in one Embodiment. It is process drawing which shows the process in which a liquid film is formed in one Embodiment. It is process drawing which shows the process in which an organic-semiconductor layer is formed in one Embodiment.
  • FIG. 1 It is a figure of the AFM picked-up image which shows the planar structure of the organic-semiconductor layer in an Example. It is sectional drawing of the semiconductor device of a modification. It is sectional drawing of the display apparatus of 1st Example. It is sectional drawing of the display apparatus of 2nd Example. It is sectional drawing of the display apparatus of 3rd Example. It is a perspective view of the electronic device of 4th Example. It is a perspective view of the electronic device of 5th Example. It is a perspective view of the electronic device of 6th Example. It is a perspective view of the electronic device of 7th Example. It is a top view of the electronic device of 7th Example. It is a perspective view of the electronic device of 8th Example. It is a perspective view of the electronic device of 9th Example. It is a perspective view of the electronic device of 9th Example. It is a perspective view of the electronic device of 9th Example.
  • the gate electrode 11 of the thin film transistor 10 is a conductive thin film having a strip shape extending in one direction.
  • a metal material such as tungsten, tantalum, molybdenum, aluminum, chromium, titanium, copper, nickel, or an alloy thereof is used.
  • a gate insulating layer 12 having a strip shape intersecting with the gate electrode 11 is laminated.
  • a material for forming the gate insulating layer 12 for example, inorganic materials such as silicon oxide, aluminum oxide, and hafnium oxide, or organic materials such as polybiphenol, polymethyl methacrylate, polyimide, and fluorine resin are used.
  • a rectangular insulating polymer compound layer 13 is laminated.
  • the polymer compound layer 13 is an example of an insulating layer.
  • the polymer compound layer 13 includes a soluble polymer compound.
  • the polymer compound layer 13 may be a single layer containing one kind of soluble polymer compound, may be a single layer containing different soluble polymer compounds, or may be different from each other. It may be a laminate of two or more layers containing a soluble polymer compound.
  • the solubility is a property in which a compound as a solute is dispersed for each molecule in a predetermined solvent. At this time, as long as the compound as the solute is dispersed, stirring or heating may be accompanied.
  • the molecular weight of the soluble polymer compound may be in a range having insulation and solubility, and is preferably 10,000 or more, more preferably 15000 or more, and 20000 or more from the viewpoint of enhancing the solubility. Is more preferable.
  • the gate insulating layer 12 is formed of a polymer compound of an organic material, the soluble polymer compound is not compatible with the polymer compound that constitutes the gate insulating layer 12.
  • soluble polymer compound examples include polystyrene, polycarbonate, polydimethylsiloxane, nylon, polyimide, cyclic olefin copolymer, epoxy polymer, cellulose, polyoxymethylene, polyolefin polymer, polyvinyl polymer, polyester polymer, and polyether.
  • Polymers, polyamide polymers, fluoropolymers, biodegradable plastics, phenol resins, amino resins, unsaturated polyester resins, diacryl phthalate resins, epoxy resins, polyimide resins, polyurethane resins, and silicone resins are used.
  • the soluble polymer compound may be a homopolymer of a monomer that forms the soluble polymer compound or a copolymer of two or more monomers that are different from each other.
  • the soluble polymer compound may have a crosslinked structure in which soluble polymer compounds are crosslinked with each other, or the soluble polymer compounds may be crosslinked with a crosslinking agent.
  • the polymer compound layer 13 may be composed of one type of soluble polymer compound among the soluble polymer compounds, or may be composed of a combination of two or more different soluble polymer compounds.
  • a solution in which the soluble polymer compound is dissolved may be used, or the monomer that forms the soluble polymer compound or the soluble polymer compound before crosslinking is dissolved.
  • a different solution may be used. That is, the polymer compound layer 13 may be polymerized after being formed as a liquid thin film, or may be crosslinked after being formed as a liquid thin film. Such a polymerization reaction and a crosslinking reaction proceed by heating the liquid thin film or irradiating light.
  • the solvent for dissolving the soluble polymer compound for example, a chlorine solvent, an aromatic solvent, a ketone solvent, a nitrogen-containing solvent, a sulfur-containing solvent, an aliphatic organic solvent, or the like is used.
  • a chlorine solvent for example, dichloromethane, trichloromethane, monochlorobenzene, o-dichlorobenzene, 1,2-dichloroethane, 1,1,1-trichloroethane, and 1,2,2-tetrachloroethane are used.
  • the aromatic solvent for example, anisole, toluene, o-xylene, m-xylene, p-xylene, and tetralin are used.
  • ketone solvents examples include 1,4-dioxane, acetone, methyl ethyl ketone, ethyl acetate, and n-butyl acetate.
  • nitrogen-containing solvent for example, dimethylformamide, dimethylacetamide, 2-methylpyrrolidone, dimethylimidazolidinone and the like are used.
  • dimethyl sulfoxide is used as the sulfur-containing solvent.
  • the aliphatic organic solvent for example, cyclopentane, cyclohexane, decalin and the like are used.
  • the solvent may be a mixed solvent.
  • a solvent having a boiling point higher than 100 ° C. is more preferable because it is easy to handle and stable during the preparation of the solution.
  • an organic semiconductor layer 14 as a low molecular compound layer having the same outer edge as that of the polymer compound layer 13 is laminated.
  • the organic semiconductor material forming the organic semiconductor layer 14 is a low molecular weight compound having a molecular weight smaller than that of the soluble high molecular compound, and has a low solubility with a solubility dispersed for each molecule in a solvent that dissolves the soluble high molecular compound. It is a molecular compound.
  • the organic semiconductor layer 14 may be a single layer containing one kind of soluble low molecular weight compound, may be a single layer containing different soluble low molecular weight compounds, or may be different from each other. It may be a laminate of two or more layers containing a low molecular compound.
  • the low molecular compound constituting the organic semiconductor layer 14 is compatible with the polymer compound constituting the polymer compound layer 13.
  • a conjugated aromatic material having three or more aromatic rings is used for the soluble low molecular weight compound.
  • the aromatic ring of the conjugated aromatic material is preferably a 5-membered ring or more and a 7-membered ring or more, and more preferably a 5-membered ring or a 6-membered ring.
  • the aromatic ring may contain heteroatoms such as selenium, tellurium, phosphorus, silicon, boron, arsenic, nitrogen, oxygen, and sulfur.
  • the aromatic ring contains at least one of nitrogen, oxygen, and sulfur.
  • the hydrogen on the aromatic ring is, for example, an alkyl group, an alkoxy group, a polyalkoxy group, a thioalkoxyl group, an acyl group, an aryl group, a halogen group, a cyano group, a nitro group, an alkylamino group, and an arylamino group. It may be substituted with a functional group.
  • a halogen group for example, a fluorine group is used, and as the alkylamino group and the arylamino group, secondary or tertiary is used.
  • the hydrogen on the aromatic ring may be substituted with a derivative of such a functional group.
  • soluble low molecular weight compounds include polythiophene, poly-3-hexylthiophene, pentacene, polyanthracene, polypyrrole, polyaniline, polyacetylene, polyphenylene, polyfuran, polyselenophene, polyisothianaphthene, polyphenylene sulfide, polyphenylene.
  • the soluble low molecular weight compound may be a derivative of these low molecular weight compounds.
  • the affinity of the soluble low molecular compound for the surface of the gate insulating layer 12 is preferably lower than that of the soluble high molecular compound.
  • the density of the soluble low molecular compound in the solidified state is preferably smaller than that of the solvent or the soluble high molecular compound.
  • the solubility of the soluble low molecular compound in the solvent is preferably smaller than that of the soluble high molecular compound.
  • the source electrode 15 is stacked on one end of the organic semiconductor layer 14 in the longitudinal direction of the gate insulating layer 12.
  • the drain electrode 16 is stacked on the other end portion of the organic semiconductor layer 14 in the longitudinal direction of the gate insulating layer 12.
  • the source electrode 15 and the drain electrode 16 are separated from each other by a channel length L on the organic semiconductor layer 14.
  • the source electrode 15 and the drain electrode 16 for example, a metal material such as gold, platinum, silver, copper, aluminum, and molybdenum, or a metal material such as an alloy, or an oxide of these metal materials is used.
  • the junction between the source electrode 15 and the organic semiconductor layer 14 and the junction between the drain electrode 16 and the organic semiconductor layer 14 may be ohmic junctions or Schottky junctions.
  • the driving method of the thin film transistor 10 may be restricted by a Schottky junction. Therefore, the junction between the source electrode 15 and the organic semiconductor layer 14 and the junction between the drain electrode 16 and the organic semiconductor layer 14 are preferably ohmic junctions.
  • the polymer compound layer 13 and the organic semiconductor layer 14 are stacked immediately above the gate electrode 11 with the gate insulating layer 12 interposed therebetween.
  • the polymer compound layer 13 is laminated on the reference surface 12 a that is the upper surface of the gate insulating layer 12.
  • a range corresponding to at least the polymer compound layer 13 in the reference surface 12a is flat. That is, at least the range in which the polymer compound layer 13 is laminated on the reference surface 12a is flat. In the illustrated example, the entire reference surface 12a is flat.
  • An insulating layer lower surface 13 b that is the lower surface of the polymer compound layer 13 is a flat surface that follows the shape of the reference surface 12 a of the gate insulating layer 12.
  • the organic semiconductor layer 14 is formed on the upper surface 13 a of the polymer compound layer 13.
  • the upper surface 13 a is an uneven surface in the entire range where the upper surface 13 a is bonded to the organic semiconductor layer 14.
  • the semiconductor layer lower surface 14 b that is the lower surface of the organic semiconductor layer 14 is a surface having a shape that coincides with the upper surface 13 a of the polymer compound layer 13.
  • the bonding surface 14a which is the upper surface of the organic semiconductor layer 14 has a convex portion at a position corresponding to the convex portion of the upper surface 13a, and has a concave portion at a position corresponding to the concave portion of the upper surface 13a.
  • the bonding surface 14a is convex on the convex portion of the upper surface 13a in the stacking direction of the polymer compound layer 13 and the organic semiconductor layer 14, and is concave in the concave portion of the upper surface 13a in the stacking direction. Therefore, the entire bonding surface 14a of the organic semiconductor layer 14 is an uneven surface that follows the shape of the upper surface 13a.
  • the joint surface 14 a includes a large number of wavy curved concave portions 14 s.
  • the wavy curved shape is a shape having a portion that is curved a plurality of times in various directions within the joint surface 14a.
  • the shape of the recess 14 s includes a curved shape that branches into two or more, a curved shape that is parallel to each other, a curved shape that spreads radially from a relatively high density portion, and an annular shape.
  • the recess 14s may include a curved portion and a portion extending in a linear shape, but the proportion of the linear portion is significantly smaller than the curved portion.
  • the width of the recess 14s is indicated by the thickness of the curve, and the portion sandwiched between the recesses 14s is indicated as a protrusion.
  • the wavy curved concave portion 14s is an irregularly shaped concave portion including a plurality of curved portions.
  • the upper surface 13a and the bonding surface 14a are irregular surfaces occupied by irregularly shaped convex portions and concave portions.
  • the level difference H is a difference in height between the convex portion 14c and the concave portion 14s.
  • This step H is 1 nm or more and 100 nm or less.
  • the step interval P is a distance between two concave portions 14s sandwiching one convex portion 14c. This step interval P is not less than 1 ⁇ m and not more than 10 ⁇ m.
  • the convex portion 14 c and the concave portion 14 s formed on the bonding surface 14 a of the organic semiconductor layer 14 have a shape following the concave portion and the convex portion formed on the upper surface 13 a of the polymer compound layer 13.
  • the bonding surface 14a of the organic semiconductor layer 14 is an uneven surface, the surface area of the bonding surface 14a is larger than the structure in which the bonding surface 14a is a flat surface. Therefore, compared to the structure in which the bonding surface 14a is a flat surface, the area where the organic semiconductor layer 14 and the source electrode 15 are bonded is large, and the adhesion between the organic semiconductor layer 14 and the source electrode 15 is enhanced. Since the area where the organic semiconductor layer 14 and the drain electrode 16 are joined similarly increases, the adhesion between the organic semiconductor layer 14 and the drain electrode 16 is enhanced.
  • the adhesion force between the bonding surface 14a of the organic semiconductor layer 14 and the electrodes 15 and 16 such as intermolecular force and Coulomb force is also greater. Therefore, the adhesion between the organic semiconductor layer 14 and the electrodes 15 and 16 is further enhanced.
  • the unevenness on the bonding surface 14a has a plurality of undulating curves, the unevenness on the bonding surface 14a extends in various directions. Therefore, the adhesion between the electrode bonded to the organic semiconductor layer 14 of the embodiment and the organic semiconductor layer 14 is enhanced as compared with the structure in which the unevenness on the bonding surface 14a extends linearly. In particular, when stress in various directions acts on the thin film transistor 10, the adhesion between the organic semiconductor layer 14 and the electrode bonded to the organic semiconductor layer 14 is significantly improved.
  • the step H is 2 nm or more and 100 nm or less, and is very small compared to the step interval P. That is, the aspect ratio, which is the ratio of the step H to the step interval P, is a very small value of 0.01 or less, so that the recess 14s is formed in the recess 14s by the same film forming technique as that when the bonding surface 14a is a flat surface. It is possible to embed an electrode material.
  • the source electrode 15 and the drain electrode 16 it is necessary to etch the electrode material embedded in the recess 14s. Also in this respect, since the aspect ratio of the concave portion 14s is very small, the electrode material can be etched from the concave portion 14s by the same etching technique as in the case where the bonding surface 14a is a flat surface.
  • the level difference H is as small as 2 nm or more and 100 nm or less
  • the level difference P between 1 ⁇ m or more and 10 ⁇ m or less is very large compared to the level difference H.
  • the step interval P is very small compared to the area of the portion where the organic semiconductor layer 14 and the source electrode 15 overlap and the area of the portion where the organic semiconductor layer 14 and the drain electrode 16 overlap. Therefore, it is possible to improve the adhesion between the organic semiconductor layer 14 and the source electrode 15 and the adhesion between the organic semiconductor layer 14 and the drain electrode 16 while obtaining the above-described processing effect due to the small step H. It becomes possible.
  • the thickness at the convex portion and the thickness at the concave portion are substantially equal, in the organic semiconductor layer 14 between the source electrode 15 and the drain electrode 16, the thickness of the organic semiconductor layer 14 is substantially uniform. Therefore, it is possible to suppress variations in electrical characteristics due to variations in the film thickness of the organic semiconductor layer 14.
  • a wet film-forming method such as a coating method using the organic semiconductor layer 14 and the polymer compound layer 13. Can be formed. Therefore, compared with the case where the organic semiconductor layer 14 and the polymer compound layer 13 are formed by a dry film forming method such as an evaporation method, the film forming method can be simplified. Variation in performance is suppressed.
  • the high-molecular compound layer is dissolved in a solvent that dissolves the low-molecular compound constituting the organic semiconductor layer 14. 13 can be dissolved. Therefore, since the organic semiconductor layer 14 and the polymer compound layer 13 can be formed by a phase separation method, unnecessary substances may be mixed between the organic semiconductor layer 14 and the polymer compound layer 13. It can be suppressed. As a result, the electrical characteristics of the thin film transistor 10 can be enhanced with respect to the polymer compound layer 13 and the organic semiconductor layer 14.
  • the carrier in the thin film transistor 10 is compared with a configuration in which the polymer compound layer 13 containing the above polymer material is not provided.
  • the mobility and the on / off ratio of the thin film transistor 10 can be prevented from varying for each thin film transistor 10.
  • the on / off ratio refers to the current between the source electrode 15 and the drain electrode 16 when the thin film transistor 10 is in the on state and the current between the source electrode 15 and the drain electrode 16 when the thin film transistor 10 is in the off state. It is the ratio to the current.
  • the high molecular compound which comprises the gate insulating layer 12 and the high molecular compound which comprises the high molecular compound layer 13 are incompatible, after the gate insulating layer 12 is formed, the high molecular compound layer 13 is made into a liquid phase. It becomes possible to form in the process. Therefore, even when the insulating properties required for the base of the organic semiconductor layer 14 cannot be obtained by the gate insulating layer 12, it can be supplemented by the polymer compound layer 13.
  • the gate electrode 11 is formed on the upper surface of the substrate S.
  • the metal layer containing the above-described metal material is formed on the entire top surface of the substrate S
  • the metal layer is processed by etching using a mask to form the gate electrode 11.
  • a metal substrate such as aluminum, nickel, and stainless steel, or a plastic film such as polycarbonate or polyethylene terephthalate is used.
  • a sputtering method, a vacuum evaporation method, an electroplating method, a printing method, or the like is used.
  • a resist mask, a hard mask containing a metal material or an insulating material is used.
  • etching of the metal layer ion milling, reactive ion etching, wet etching, or the like is used.
  • a gate insulating layer 12 covering the entire gate electrode 11 is formed.
  • a sputtering method using the above-described inorganic material as a target or a CVD method in which the above-described inorganic material is vapor-phase grown is used.
  • a coating method or a printing method using an ink containing the above-described organic material is used.
  • the film-forming solution is prepared by dissolving the above-described soluble polymer compound and soluble low-molecular compound in the above-described solvent.
  • the film-forming solution may be prepared by dissolving the above-described soluble molecular compound precursor and the soluble low-molecular compound in the above-described solvent.
  • a liquid film 17 is formed on the gate insulating layer 12 by supplying the film forming solution onto the gate insulating layer 12.
  • the liquid film 17 formed on the gate insulating layer 12 is baked by a heating device such as an oven.
  • a heating device such as an oven.
  • the polymerization reaction using the precursor is advanced by, for example, light irradiation or heating prior to the above-described baking treatment, and the liquid film 17 A soluble polymer compound is produced in the inside.
  • the solubility of the soluble low molecular compound in the solvent and the solubility of the soluble high molecular compound in the solvent are both preferably 0.1% by weight or more, more preferably 0.3% by weight or more. More preferably, it is 5% by weight or more.
  • the weight ratio of the soluble polymer compound to the soluble low-molecular compound is not particularly limited, but is preferably 1/10 or more, 10 or less, more preferably 1/5 or more and 5 or less, and further preferably 1/3 or more and 3 or less.
  • the dipping method, the spraying method, the coating method, and the printing method are used.
  • the coating method and the printing method for example, a cast coating method, a spray coating method, an ink jet printing method, a relief printing method, a flexographic printing method, a screen printing method, a gravure printing method, and a gravure offset printing method are used.
  • the liquid film 17 formed on the gate insulating layer 12 is baked, it is separated into a phase containing a high molecular compound and a phase containing a soluble low molecular weight compound.
  • the polymer compound layer 13 is formed on the gate insulating layer 12, and the organic semiconductor layer 14 is formed on the polymer compound layer 13.
  • concave portions and convex portions are formed on the upper surface 13 a of the polymer compound layer 13 and the bonding surface 14 a of the organic semiconductor layer 14.
  • a soluble molecular layer is formed on the entire upper surface of the gate insulating layer 12 as shown by a broken line in FIG. 7, the polymer compound layer 13 and the organic semiconductor are etched by etching the soluble molecular layer using a mask.
  • Layer 14 is formed.
  • a photolithography method or an electron beam lithography method is used as the mask patterning method, and a wet etching method is used as the etching method, for example.
  • the film-forming solution is supplied only to the site where the polymer compound layer 13 and the organic semiconductor layer 14 are formed, the film-forming solution is baked, so that the polymer compound layer 13 and An organic semiconductor layer 14 is formed.
  • the irregularities formed on the upper surface 13a and the bonding surface 14a can be prepared by the firing rate applied to the liquid film 17. For example, the higher the baking speed, the smaller the step H, and the electrical characteristics of the thin film transistor 10 are improved.
  • the evaporation of the solvent from the liquid film 17 is suppressed before the firing process. It is preferable to start the baking immediately after the liquid film 17 is formed, or to form the liquid film 17 under pressure.
  • the source electrode 15 and the drain electrode 16 are formed at two opposing ends in the surface direction of the organic semiconductor layer 14.
  • a metal film covering the entire gate insulating layer 12 is formed.
  • the metal film is etched using the resist pattern.
  • Example 1 As the substrate S, a silicon substrate into which at least one of boron, phosphorus, antimony, and arsenic is implanted is used. After a tungsten layer is formed as the gate electrode 11 on the surface of the substrate S, the gate insulating layer 12 is formed. A polybiphenol resin layer having a thickness of 500 nm was formed.
  • a film-forming solution was prepared using a cycloolefin copolymer, a dioxaneanthanthrene compound, and toluene, respectively, as a soluble polymer compound, a soluble low-molecular compound, and a solvent.
  • the cycloolefin copolymer is TOPAS6015 (TOPAS is a registered trademark of TopasTOAdvanced Polymers GmbH) manufactured by Polyplastics Co., Ltd.
  • the dioxaneanthanthrene compound is 3,9-bis (p-methylphenyl) perixanthenoxanthene as shown in the following chemical formula 1.
  • the cycloolefin copolymer and the dioxaneanthanthrene compound were 1: 1 by weight, and the concentration of these solutes was 0.45% by weight.
  • the film-forming solution described above was applied to the entire upper surface of the gate insulating layer 12 by a spin coating method to form a liquid film 17 made of the film-forming solution described above.
  • a spin coating method to form a liquid film 17 made of the film-forming solution described above.
  • the liquid film 17 was dried and baked. Thereby, the polymer compound layer 13 and the organic semiconductor layer 14 were formed.
  • the film thickness of the organic semiconductor layer 14 is about 20 nm, the channel length L that is the distance between the source electrode 15 and the drain electrode 16 is about 50 ⁇ m, and the channel width W that is the width of the source electrode 15 or the drain electrode 16.
  • the channel width W that is the width of the source electrode 15 or the drain electrode 16.
  • Example 2 The thin film transistor of Example 2 in which only the thickness of the liquid film 17 is made larger than that of Example 1, and the film thickness of the organic semiconductor layer 14 is about 30 nm by the same method as in Example 1 except for the capacity of the liquid film 17 10 was created.
  • Example 3 The thin film transistor of Example 3 in which only the thickness of the liquid film 17 is made larger than that of Example 2 and the film thickness of the organic semiconductor layer 14 is about 50 nm by the same method as in Example 1 except for the capacity of the liquid film 17 10 was created.
  • Example 4 Implementation in which polyalphamethylstyrene having an average molecular weight of 100,000 is used for the soluble polymer compound, and the film thickness of the organic semiconductor layer 14 is about 20 nm by the same method as in Example 1 except for the soluble polymer compound The thin film transistor 10 of Example 4 was produced.
  • Example 5 Only the capacity of the liquid film 17 is made larger than that of Example 4, and the film thickness of the organic semiconductor layer 14 is about 30 nm by the same method as in Example 4 except for the capacity of the liquid film 17. Was created.
  • Example 6 The thin film transistor of Example 6 in which only the thickness of the liquid film 17 is made larger than that of Example 5 and the film thickness of the organic semiconductor layer 14 is about 50 nm by the same method as in Example 4 except for the capacity of the liquid film 17 10 was created.
  • Comparative example in which a film forming solution containing only a soluble low molecular weight compound in a solvent is prepared, and the film thickness of the organic semiconductor layer is about 20 nm by the same method as in Example 1 except for the composition of the film forming solution. Thin film transistors were created.
  • the surface roughness of the organic semiconductor layer 14 in each of Examples 1 to 6 and Comparative Example was measured according to JISB0601.
  • the drain voltage Vd is set to be equal to or higher than the gate voltage Vg (Vd ⁇ Vg) as the voltage applied to the gate electrode 11.
  • Vg-Id curve showing the relationship between the square root of the drain current and the gate voltage Vg is measured in the range of ⁇ 30 V ⁇ Vg ⁇ 0 V, and the mobility is calculated from the slope of the square root of the drain current with respect to the gate voltage Vg. It was.
  • the mobility of the organic semiconductor layer 14 in each of Examples 1 to 6 and Comparative Example was measured after the following winding test. That is, in the winding test, the winding of the substrate around the test rod and the winding of the substrate wound around the test rod were repeated 10,000 times for each of Examples 1 to 6 and the substrate of the comparative example. A cylinder with a radius of 5 mm was used for the test bar.
  • Table 1 shows the measurement results of the surface roughness Ra and the mobility in each of Examples 1 to 6 and Comparative Example. As shown in Table 1, in any of Examples 1 to 6, it was recognized that the surface roughness Ra of the organic semiconductor layer 14 was 2 nm or more. From the measurement results in Example 1 to Example 3 and the measurement results in Example 4 to Example 6, it was recognized that the surface roughness Ra increases as the film thickness of the organic semiconductor layer 14 increases. Further, from the comparison between the measurement results in Example 1 to Example 3 and the measurement results in Example 4 to Example 6, the organic semiconductor layer can be used as long as the film thickness is the same even if the soluble polymer compounds are different. It was confirmed that the surface roughness Ra of 14 was substantially equal.
  • FIG. 8 The result of having imaged the joint surface 14a of the organic-semiconductor layer 14 in Example 4 with the atomic force microscope is shown in FIG.
  • the image of the organic semiconductor layer 14 is shown in black as the depth increases.
  • the entire bonding surface 14 a of the organic semiconductor layer 14 was formed with a number of wavy curved irregularities.
  • corrugation shown in FIG. 8 is formed also in the joint surface 14a of the organic-semiconductor layer 14 in Example 1- Example 3, Example 5, and Example 6.
  • the surface roughness Ra of the organic semiconductor layer of Comparative Example 1 was 1 nm or less, and the above-described unevenness was not observed on the surface.
  • Example 1 to Example 6 The mobility of each of Example 1 to Example 6 was about 0.5 (cm2 / Vs) as an initial value, and it was recognized that 90% or more of the initial value was exhibited even after the winding test. On the other hand, the mobility of the comparative example showed 0.4 (cm2 / Vs) as an initial value, and after the winding test, it was recognized that the mobility dropped to 12.5% of the initial value.
  • the following effects can be obtained.
  • -Since the joining surface 14a is an uneven surface, the area where the organic semiconductor layer 14 and the electrode are joined increases. As a result, the adhesion between the organic semiconductor layer 14 and the electrode is improved.
  • the unevenness on the bonding surface 14a has a plurality of undulating curves, particularly when stress in various directions acts on the thin film transistor 10, the improvement in adhesion between the organic semiconductor layer 14 and the electrode becomes remarkable. .
  • the aspect ratio which is the ratio of the step H to the step interval P, is a very small value of 0.01 or less, it is possible to form electrodes by the same processing technique as when the bonding surface 14a is a flat surface. It is.
  • an organic semiconductor layer 24 containing the above-described soluble low-molecular compound is laminated on the polymer compound layer 23 containing the above-mentioned soluble polymer compound.
  • the insulating layer lower surface 23 b which is the lower surface of the polymer compound layer 23, is a flat surface, while the upper surface 23 a of the polymer compound layer 23 is an uneven surface in the entire range bonded to the organic semiconductor layer 24.
  • the semiconductor layer lower surface 24 b that is the lower surface of the organic semiconductor layer 24 is a surface having a shape that coincides with the upper surface 23 a of the polymer compound layer 23.
  • the bonding surface 24a that is the upper surface of the organic semiconductor layer 24 has a convex portion at a position corresponding to the convex portion of the upper surface 23a, and has a concave portion at a position corresponding to the concave portion of the upper surface 23a. That is, the bonding surface 24a is convex on the convex portion of the upper surface 23a in the stacking direction of the polymer compound layer 23 and the organic semiconductor layer 24, and is concave on the concave portion of the upper surface 23a. Therefore, the entire organic semiconductor layer 24 is an uneven surface that follows the shape of the upper surface 23a.
  • the shape of the convex portion and the shape of the concave portion formed on the joint surface 24a include many undulating curved shapes as in the case of the joint surface 14a.
  • a part of the bonding surface 24 a of the organic semiconductor layer 24 is laminated with a source electrode 25 and a drain electrode 26 which are a pair of electrodes separated from each other.
  • a gate insulating layer 22 that covers the source electrode 25 and the drain electrode 26 is stacked on the remaining portion of the bonding surface 24a.
  • the gate electrode 21 is stacked above the source electrode 25 and the drain electrode 26.
  • the above-mentioned semiconductor device can also be changed as follows.
  • the organic semiconductor layer 14 and the polymer compound layer 13 do not have to be separated below the portion of the bonding surface 14a of the organic semiconductor layer 14 where the electrode is not bonded. That is, it is only necessary that the organic semiconductor layer 14 and the polymer compound layer 13 are separated at least below the portion of the bonding surface 14a where the electrodes are bonded. It is only necessary that the organic semiconductor layer 24 and the polymer compound layer 23 be separated at least below the portion of the bonding surface 24a where the electrodes are bonded.
  • the polymer compound layer 13 When the upper surface of the gate insulating layer 12 is an uneven surface, the polymer compound layer 13 may be omitted and the organic semiconductor layer 14 may be directly stacked on the gate insulating layer 12.
  • the polymer compound layer 23 When the upper surface of the substrate on which the organic semiconductor layer 24 is formed is an uneven surface, the polymer compound layer 23 may be omitted and the organic semiconductor layer 24 may be directly laminated on the upper surface of the substrate. In short, the organic semiconductor layer 14 may be laminated on the upper surface, which is an uneven surface in the insulating layer.
  • the shape of the concave portion provided in the joint surfaces 14a and 24a may be a linear shape extending in one direction or a lattice shape extending in a direction intersecting with each other.
  • the base of the polymer compound layers 13 and 23 may be provided with a linear or lattice pattern in advance.
  • linear or lattice-shaped recesses may be formed on the surface of the insulating layer, and the organic semiconductor layers 14 and 24 may be directly laminated on the insulating layer.
  • the semiconductor device is not limited to a thin film transistor, and may be a rectifying element in which electrodes are bonded to the bonding surfaces 14 a and 24 a of the organic semiconductor layers 14 and 24.
  • the semiconductor device includes an insulating layer having an upper surface including irregularities, an organic semiconductor layer formed on the upper surface of the insulating layer and having a bonding surface facing the upper surface, and an electrode bonded to the bonding surface.
  • the display device Next, a display device including the above-described thin film transistor will be described. Note that the thin film transistor can be applied to various uses, and the application target of the thin film transistor is not particularly limited. Therefore, in the following description, for example, a configuration in which a thin film transistor is applied to a driving element of a display device will be described. However, the configuration is merely an example, and appropriate changes can be made.
  • the plurality of thin film transistors 10 described above are formed as drive elements for driving the pixels.
  • a pixel electrode 53 is bonded to each of the plurality of thin film transistors 10 through an insulating layer 52 covering the thin film transistor 10.
  • Each pixel electrode 53 is formed between partition walls 54 formed on the insulating layer 52 at a predetermined interval.
  • a common counter electrode 56 is laminated via an organic EL layer 55 having a multilayer structure including an electron injection layer, a light emitting layer, and a hole transport layer.
  • the current supply mode between the pixel electrode 53 and the counter electrode 56 that is, the mode of light emission in the organic EL layer 55 sandwiched between the pixel electrode 53 and the counter electrode 56 is controlled by driving the thin film transistor 10.
  • the plurality of thin film transistors 10 described above are formed as drive elements for driving the pixels.
  • a pixel electrode 63 is bonded to each of the plurality of thin film transistors 10 through an insulating layer 62 covering the thin film transistor 10.
  • a common counter electrode 64 is stacked above the plurality of pixel electrodes 63 with the liquid crystal 65 interposed therebetween. The voltage application mode between the pixel electrode 63 and the counter electrode 64, that is, the alignment mode of the liquid crystal 65 sandwiched between the pixel electrode 63 and the counter electrode 64 is controlled by driving the thin film transistor 10.
  • the plurality of thin film transistors 10 described above are formed as drive elements for driving the pixels.
  • a pixel electrode 73 is bonded to each of the plurality of thin film transistors 10 through an insulating layer 72 covering the thin film transistor 10.
  • a counter electrode 77 common to each pixel electrode 73 is laminated with an insulating liquid layer 76 mixed with electrophoretic particles 75 interposed therebetween.
  • the voltage application mode between the pixel electrode 73 and the counter electrode 77 that is, the mode of migration of the electrophoretic particles 75 between the pixel electrode 73 and the counter electrode 77 is controlled by driving the thin film transistor 10. .
  • the housing 101 of the electronic book terminal 100 is equipped with a display unit 102 including the above-described display device and an operation button 103 for operating a display mode on the display unit 102.
  • a keyboard 112 and an operation unit 113 are mounted on the lower casing 111 of the personal computer 110, and a display section including the above-described display device is mounted on the upper casing 114 of the personal computer 110. 115 is installed.
  • a display unit 123 including the above-described display device is mounted on a housing 122 attached to a support base 121 of a television 120.
  • a lens 132 that captures an imaging target and an imaging button 133 for causing the digital still camera 130 to capture an image are formed on one surface side of the casing 131 of the digital still camera 130.
  • a display unit 134 including the above-described display device and operation buttons 135 are mounted on the other surface side of the housing 131.
  • a lens 142 and operation buttons 143 are mounted on the housing 141 of the digital video camera 140.
  • a display unit housing 145 is connected to the housing 141 via a connecting unit 144, and the display unit 145 including the above-described display device is mounted on the display unit housing 145.
  • an operation button 152 is mounted on the lower casing 151 included in the mobile phone terminal 150, and the upper casing 154 is connected to the lower casing 151 via a connecting portion 153. It is connected.
  • a display portion 155 including the above display device is mounted on the upper housing 154.
  • a back surface display unit 156 including the above-described display device is mounted on a surface of the upper housing 154 facing the display unit 155.
  • the thin film transistor of the present disclosure may be configured as follows. (1) A semiconductor device comprising an insulating layer, an organic semiconductor layer formed on the insulating layer, and an electrode bonded to a bonding surface which is an upper surface of the organic semiconductor layer, and the bonding surface has irregularities.
  • the step in the unevenness of the joint surface is 1 nm or more and 100 nm or less, and the interval of the step in the joint surface is 1 ⁇ m or more and 10 ⁇ m or less.
  • the organic semiconductor layer is a layer containing a low molecular compound
  • the insulating layer is a layer containing a polymer compound
  • the low molecular compound constituting the organic semiconductor layer and the insulating layer are high.
  • the insulating layer has irregularities on the surface on which the organic semiconductor layer is formed, and the irregularities on the bonding surface follow any one of the irregularities of the insulating layer.
  • the semiconductor device according to any one of (1) to (7), wherein the electrodes are a source electrode and a drain electrode of a thin film transistor. (9) The method further includes a gate electrode formed under the insulating layer, wherein the electrode includes a source electrode formed on the organic semiconductor layer and a drain electrode formed on the organic semiconductor layer. 1) The semiconductor device according to any one of (8).
  • the insulating layer is a first insulating layer
  • the semiconductor device further includes a second insulating layer formed under the first insulating layer, the first insulating layer, the second insulating layer, Is a layer containing a polymer compound, and the polymer compound constituting the first insulating layer and the polymer compound constituting the second insulating layer are not compatible with each other.
  • the semiconductor device according to one.

Abstract

This semiconductor device is provided with: an insulating layer; an organic semiconductor layer formed on the insulating layer; and electrodes bonded on the bonding surface of the organic semiconductor layer, said bonding surface having recesses and projections.

Description

半導体デバイス、表示装置、電子機器、及び、半導体デバイスの製造方法SEMICONDUCTOR DEVICE, DISPLAY DEVICE, ELECTRONIC DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
　本開示の技術は、有機半導体層を備える半導体デバイス、表示装置、電子機器、及び半導体デバイスの製造方法に関する。 The technology of the present disclosure relates to a semiconductor device including an organic semiconductor layer, a display device, an electronic device, and a method for manufacturing the semiconductor device.
　半導体デバイスの１つである薄膜トランジスタは、例えば、電子機器のディスプレイにおける画素のスイッチング素子や駆動素子として用いられる。例えば、プラスチックフィルム等を基板とするフレキシブルディスプレイでは、その基板に薄膜トランジスタがスイッチング素子や駆動素子として形成される。 A thin film transistor which is one of semiconductor devices is used as, for example, a pixel switching element or a driving element in a display of an electronic device. For example, in a flexible display using a plastic film or the like as a substrate, a thin film transistor is formed on the substrate as a switching element or a driving element.
　例えば、特許文献１に記載されるように、薄膜トランジスタの能動層として有機半導層を利用するものは、薄膜の形成を低い温度下で行うことができる。プラスチックフィルム等のフレキシブル基板の耐熱温度は、ガラス基板等のリジッド基板の耐熱温度と比べて低い傾向を有するから、有機半導体層は、フレキシブル基板用の薄膜トランジスタの能動層に特に適している。 For example, as described in Patent Document 1, those using an organic semiconductor layer as an active layer of a thin film transistor can form a thin film at a low temperature. Since the heat resistant temperature of a flexible substrate such as a plastic film tends to be lower than the heat resistant temperature of a rigid substrate such as a glass substrate, the organic semiconductor layer is particularly suitable for an active layer of a thin film transistor for a flexible substrate.
特開平７－２４９７７５号公報JP-A-7-249775
　ところで、薄膜トランジスタは、有機半導体層に接合される電極を備える。この電極と有機半導体層とが接合する部位は、有機半導体層の膜応力や電極の膜応力を受ける。有機半導体層と電極とは、それらの間に分子間力やクーロン力等の密着力を生じ難い材料から形成される。それゆえに、膜応力の程度によっては、電極の一部が有機半導体層から剥がれる場合がある。 Incidentally, the thin film transistor includes an electrode bonded to the organic semiconductor layer. The part where the electrode and the organic semiconductor layer are joined receives the film stress of the organic semiconductor layer and the film stress of the electrode. The organic semiconductor layer and the electrode are formed of a material that hardly generates an adhesion force such as an intermolecular force or a Coulomb force between them. Therefore, part of the electrode may be peeled off from the organic semiconductor layer depending on the degree of film stress.
　特に、有機半導体層と電極とがフレキシブル基板に形成される場合には、有機半導体層と電極とが接合する部位は、膜応力の他に、フレキシブル基板の曲げ応力も受ける。結果として、電極の一部が有機半導体層から剥がれる問題が一層顕在化する。 In particular, when the organic semiconductor layer and the electrode are formed on the flexible substrate, the portion where the organic semiconductor layer and the electrode are joined receives the bending stress of the flexible substrate in addition to the film stress. As a result, the problem that a part of the electrode is peeled off from the organic semiconductor layer becomes more obvious.
　したがって、電極と有機半導体層との剥離を抑制することの可能な半導体デバイス、表示装置、電子機器、及び、半導体デバイスの製造方法を提供することが望ましい。 Therefore, it is desirable to provide a semiconductor device, a display device, an electronic apparatus, and a method for manufacturing a semiconductor device that can suppress peeling between the electrode and the organic semiconductor layer.
　本開示における半導体デバイスの一態様は、絶縁層と、前記絶縁層上に形成された有機半導体層と、前記有機半導体層の上面である接合面に接合される電極とを備え、前記接合面は凹凸を有する。 One aspect of the semiconductor device in the present disclosure includes an insulating layer, an organic semiconductor layer formed on the insulating layer, and an electrode bonded to a bonding surface that is an upper surface of the organic semiconductor layer, and the bonding surface is Has irregularities.
　本開示における表示装置の一態様は、薄膜トランジスタを備え、前記薄膜トランジスタが、絶縁層と、前記絶縁層上に形成された有機半導体層と、前記有機半導体層の上面である接合面に接合される電極とを備え、前記接合面は凹凸を有する。 One embodiment of the display device according to the present disclosure includes a thin film transistor, and the thin film transistor is bonded to an insulating layer, an organic semiconductor layer formed on the insulating layer, and a bonding surface that is an upper surface of the organic semiconductor layer. The joint surface has irregularities.
　本開示における電子機器の一態様は、表示部を備え、前記表示部が、薄膜トランジスタを備え、前記薄膜トランジスタが、絶縁層と、前記絶縁層上に形成された有機半導体層と、前記有機半導体層の上面である接合面に接合される電極とを備え、前記接合面は凹凸を有する。 One aspect of the electronic device in the present disclosure includes a display unit, the display unit includes a thin film transistor, the thin film transistor including an insulating layer, an organic semiconductor layer formed on the insulating layer, and the organic semiconductor layer. An electrode bonded to a bonding surface which is an upper surface, and the bonding surface has irregularities.
　本開示における半導体デバイスの製造方法の一態様は、液膜を相分離させることによって、絶縁層上に有機半導体層を形成する工程と、前記有機半導体層の上面である接合面に電極を形成する工程とを備え、前記有機半導体層を形成する工程では、前記接合面に凹凸を有する有機半導体層が形成される。 In one embodiment of the method for manufacturing a semiconductor device according to the present disclosure, a step of forming an organic semiconductor layer on an insulating layer by phase-separating a liquid film and forming an electrode on a bonding surface that is an upper surface of the organic semiconductor layer And the step of forming the organic semiconductor layer includes forming an organic semiconductor layer having irregularities on the bonding surface.
　本開示における技術の一態様によれば、有機半導体層が有する凹凸面である接合面に電極が接合されるから、有機半導体層と電極との接合面積は、有機半導体層と電極とが単に平面で接合する場合の接合面積と比べて大きい。結果として、有機半導体層と電極との接触面積が増えてその接合強度が大きくなるから、有機半導体層とこれに接合される電極との剥離を抑制することができる。 According to one aspect of the technology of the present disclosure, since the electrode is bonded to the bonding surface that is the uneven surface of the organic semiconductor layer, the bonding area between the organic semiconductor layer and the electrode is simply a flat surface between the organic semiconductor layer and the electrode. It is larger than the bonding area when bonding with. As a result, since the contact area between the organic semiconductor layer and the electrode increases and the bonding strength increases, it is possible to suppress peeling between the organic semiconductor layer and the electrode bonded thereto.
　本開示における半導体デバイスの製造方法の一態様によれば、相分離によって形成された有機半導体層の接合面が凹凸を含むため、絶縁層と有機半導体層との間に不要な物質が混入することを抑えつつ、有機半導体層と電極との接触面積を増やすことができる。 According to one aspect of the semiconductor device manufacturing method of the present disclosure, the bonding surface of the organic semiconductor layer formed by phase separation includes irregularities, and therefore, unnecessary substances are mixed between the insulating layer and the organic semiconductor layer. The contact area between the organic semiconductor layer and the electrode can be increased while suppressing the above.
本開示の一実施形態における薄膜トランジスタの平面図である。有機半導体層の下にある高分子化合物層を示すべく有機半導体層の一部が切り欠かれている。It is a top view of a thin film transistor in one embodiment of this indication. A portion of the organic semiconductor layer is cut away to show the polymer compound layer below the organic semiconductor layer. 図１のＡ－Ａ線断面における断面図である。FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. 一実施形態における有機半導体層の接合面の平面構造を示す平面図である。It is a top view which shows the planar structure of the joint surface of the organic-semiconductor layer in one Embodiment. 図３のＢ－Ｂ線断面における部分断面図である。FIG. 4 is a partial cross-sectional view taken along line BB in FIG. 3. 一実施形態にてゲート電極が形成される工程を示す工程図である。It is process drawing which shows the process in which a gate electrode is formed in one Embodiment. 一実施形態にて液膜が形成される工程を示す工程図である。It is process drawing which shows the process in which a liquid film is formed in one Embodiment. 一実施形態にて有機半導体層が形成される工程を示す工程図である。It is process drawing which shows the process in which an organic-semiconductor layer is formed in one Embodiment. 実施例における有機半導体層の平面構造を示すＡＦＭ撮像画像の図である。It is a figure of the AFM picked-up image which shows the planar structure of the organic-semiconductor layer in an Example. 変形例の半導体デバイスの断面図である。It is sectional drawing of the semiconductor device of a modification. 第１実施例の表示装置の断面図である。It is sectional drawing of the display apparatus of 1st Example. 第２実施例の表示装置の断面図である。It is sectional drawing of the display apparatus of 2nd Example. 第３実施例の表示装置の断面図である。It is sectional drawing of the display apparatus of 3rd Example. 第４実施例の電子機器の斜視図である。It is a perspective view of the electronic device of 4th Example. 第５実施例の電子機器の斜視図である。It is a perspective view of the electronic device of 5th Example. 第６実施例の電子機器の斜視図である。It is a perspective view of the electronic device of 6th Example. 第７実施例の電子機器の斜視図である。It is a perspective view of the electronic device of 7th Example. 第７実施例の電子機器の平面図である。It is a top view of the electronic device of 7th Example. 第８実施例の電子機器の斜視図である。It is a perspective view of the electronic device of 8th Example. 第９実施例の電子機器の斜視図である。It is a perspective view of the electronic device of 9th Example. 第９実施例の電子機器の斜視図である。It is a perspective view of the electronic device of 9th Example.
　以下に、本開示の技術における半導体デバイス、及び、薄膜トランジスタの各々をボトムコンタクト型の薄膜トランジスタに具体化した一実施の形態について説明する。
　［半導体デバイスの構成］
　図１に示されるように、薄膜トランジスタ１０のゲート電極１１は、１つの方向に延びる帯状をなす導電性の薄膜である。ゲート電極１１の形成材料には、例えば、タングステン、タンタル、モリブデン、アルミニウム、クロム、チタン、銅、及び、ニッケルやこれらの合金等の金属材料が用いられる。 Hereinafter, an embodiment in which each of the semiconductor device and the thin film transistor in the technology of the present disclosure is embodied as a bottom contact thin film transistor will be described.
[Configuration of semiconductor device]
As shown in FIG. 1, the gate electrode 11 of the thin film transistor 10 is a conductive thin film having a strip shape extending in one direction. As the material for forming the gate electrode 11, for example, a metal material such as tungsten, tantalum, molybdenum, aluminum, chromium, titanium, copper, nickel, or an alloy thereof is used.
　ゲート電極１１上には、ゲート電極１１と交差する帯状をなすゲート絶縁層１２が積層されている。ゲート絶縁層１２の形成材料には、例えば、酸化ケイ素、酸化アルミニウム、酸化ハフニウム等の無機材料、又は、ポリビフェノール、ポリメタクリル酸メチル、ポリイミド、及び、フッ素樹脂等の有機材料が用いられる。 On the gate electrode 11, a gate insulating layer 12 having a strip shape intersecting with the gate electrode 11 is laminated. As a material for forming the gate insulating layer 12, for example, inorganic materials such as silicon oxide, aluminum oxide, and hafnium oxide, or organic materials such as polybiphenol, polymethyl methacrylate, polyimide, and fluorine resin are used.
　ゲート電極１１とゲート絶縁層１２とが重なる部分には、矩形形状をなす絶縁性の高分子化合物層１３が積層されている。高分子化合物層１３は絶縁層の一例である。高分子化合物層１３は、可溶性高分子化合物を含む。高分子化合物層１３は、一種類の可溶性高分子化合物を含む単一の層であってもよいし、相互に異なる可溶性高分子化合物を含む単一の層であってもよいし、相互に異なる可溶性高分子化合物を含む２つ以上の層の積層体であってもよい。なお、可溶性は、溶質としての化合物が所定の溶媒の中で分子ごとに分散される性質である。この際、溶質としての化合物が分散するのであれば、攪拌や加熱が伴ってもよい。可溶性高分子化合物の分子量は、絶縁性と可溶性とを備える範囲であればよく、可溶性が高められる観点では、１００００以上であることが好ましく、１５０００以上であることがより好ましく、２００００以上であることがさらに好ましい。ゲート絶縁層１２が有機材料の高分子化合物で形成される場合、可溶性高分子化合物は、ゲート絶縁層１２を構成する高分子化合物と相溶しない。 In the portion where the gate electrode 11 and the gate insulating layer 12 overlap, a rectangular insulating polymer compound layer 13 is laminated. The polymer compound layer 13 is an example of an insulating layer. The polymer compound layer 13 includes a soluble polymer compound. The polymer compound layer 13 may be a single layer containing one kind of soluble polymer compound, may be a single layer containing different soluble polymer compounds, or may be different from each other. It may be a laminate of two or more layers containing a soluble polymer compound. The solubility is a property in which a compound as a solute is dispersed for each molecule in a predetermined solvent. At this time, as long as the compound as the solute is dispersed, stirring or heating may be accompanied. The molecular weight of the soluble polymer compound may be in a range having insulation and solubility, and is preferably 10,000 or more, more preferably 15000 or more, and 20000 or more from the viewpoint of enhancing the solubility. Is more preferable. When the gate insulating layer 12 is formed of a polymer compound of an organic material, the soluble polymer compound is not compatible with the polymer compound that constitutes the gate insulating layer 12.
　可溶性高分子化合物には、例えば、ポリスチレン、ポリカーボネート、ポリジメチルシロキサン、ナイロン、ポリイミド、環状オレフィンコポリマー、エポキシポリマー、セルロース、ポリオキシメチレン、及び、ポリオレフィン系ポリマー、ポリビニル系ポリマー、ポリエステル系ポリマー、ポリエーテル系ポリマー、ポリアミド系ポリマー、フッ素系ポリマー、生分解性プラスチック、フェノール樹脂、アミノ樹脂、不飽和ポリエステル樹脂、ジアクリルフタレート樹脂、エポキシ樹脂、ポリイミド樹脂、ポリウレタン樹脂、及び、シリコーン樹脂等が用いられる。 Examples of the soluble polymer compound include polystyrene, polycarbonate, polydimethylsiloxane, nylon, polyimide, cyclic olefin copolymer, epoxy polymer, cellulose, polyoxymethylene, polyolefin polymer, polyvinyl polymer, polyester polymer, and polyether. Polymers, polyamide polymers, fluoropolymers, biodegradable plastics, phenol resins, amino resins, unsaturated polyester resins, diacryl phthalate resins, epoxy resins, polyimide resins, polyurethane resins, and silicone resins are used.
　可溶性高分子化合物は、可溶性高分子化合物を形成する単量体の単独重合体（ホモポリマー）でもよく、相互に異なる２以上の単量体の共重合体（コポリマー）でもよい。可溶性高分子化合物は、可溶性高分子化合物同士が架橋された架橋構造をなすものでもよいし、可溶性高分子化合物同士が架橋剤を介して架橋されたものでもよい。 The soluble polymer compound may be a homopolymer of a monomer that forms the soluble polymer compound or a copolymer of two or more monomers that are different from each other. The soluble polymer compound may have a crosslinked structure in which soluble polymer compounds are crosslinked with each other, or the soluble polymer compounds may be crosslinked with a crosslinking agent.
　なお、高分子化合物層１３は、可溶性高分子化合物のうち、一種類の可溶性高分子化合物から構成されてもよいし、相互に異なる２以上の可溶性高分子化合物の組み合わせから構成されてもよい。高分子化合物層１３の形成には、可溶性高分子化合物が溶解された溶液が用いられてもよいし、可溶性高分子化合物を形成する単量体、あるいは、架橋前の可溶性高分子化合物が溶解された溶液が用いられてもよい。すなわち、高分子化合物層１３は、液状の薄膜として形成された後に重合が開始されてもよいし、液状の薄膜として形成された後に架橋が開始されてもよい。なお、こうした重合反応や架橋反応は、液状の薄膜に対する加熱や光の照射によって進行する。 The polymer compound layer 13 may be composed of one type of soluble polymer compound among the soluble polymer compounds, or may be composed of a combination of two or more different soluble polymer compounds. For the formation of the polymer compound layer 13, a solution in which the soluble polymer compound is dissolved may be used, or the monomer that forms the soluble polymer compound or the soluble polymer compound before crosslinking is dissolved. A different solution may be used. That is, the polymer compound layer 13 may be polymerized after being formed as a liquid thin film, or may be crosslinked after being formed as a liquid thin film. Such a polymerization reaction and a crosslinking reaction proceed by heating the liquid thin film or irradiating light.
　可溶性高分子化合物を溶解する溶媒には、例えば、塩素系溶媒、芳香族系溶媒、ケトン類溶媒、含窒素類溶媒、含硫黄類溶媒、及び、脂肪族有機系溶媒等が用いられる。塩素系溶媒には、例えば、ジクロロメタン、トリクロロメタン、モノクロロベンゼン、ｏ－ジクロロベンゼン、１，２－ジクロロエタン、１，１，１－トリクロロエタン、及び、１，２，２－テトラクロロエタンが用いられる。芳香族系溶媒には、例えば、アニソール、トルエン、ｏ－キシレン、ｍ－キシレン、ｐ－キシレン、及び、テトラリンが用いられる。ケトン類溶媒には、例えば、１，４－ジオキサン、アセトン、メチルエチルケトン、酢酸エチル、及び、酢酸ｎ－ブチル等が用いられる。含窒素類溶媒には、例えば、ジメチルホルムアミド、ジメチルアセトアミド、２－メチルピロリドン、及び、ジメチルイミダゾリジノン等が用いられる。含硫黄類溶媒には、例えば、ジメチルスルホキシド等が用いられる。脂肪族有機系溶媒には、例えば、シクロペンタン、シクロヘキサン、及び、デカリン等が用いられる。なお、溶媒は、混合溶媒でもよい。沸点が１００℃よりも高い溶媒は、溶液の調製時において扱いやすく、且つ、安定であるため、より好ましい。 As the solvent for dissolving the soluble polymer compound, for example, a chlorine solvent, an aromatic solvent, a ketone solvent, a nitrogen-containing solvent, a sulfur-containing solvent, an aliphatic organic solvent, or the like is used. As the chlorinated solvent, for example, dichloromethane, trichloromethane, monochlorobenzene, o-dichlorobenzene, 1,2-dichloroethane, 1,1,1-trichloroethane, and 1,2,2-tetrachloroethane are used. As the aromatic solvent, for example, anisole, toluene, o-xylene, m-xylene, p-xylene, and tetralin are used. Examples of ketone solvents include 1,4-dioxane, acetone, methyl ethyl ketone, ethyl acetate, and n-butyl acetate. As the nitrogen-containing solvent, for example, dimethylformamide, dimethylacetamide, 2-methylpyrrolidone, dimethylimidazolidinone and the like are used. For example, dimethyl sulfoxide is used as the sulfur-containing solvent. As the aliphatic organic solvent, for example, cyclopentane, cyclohexane, decalin and the like are used. The solvent may be a mixed solvent. A solvent having a boiling point higher than 100 ° C. is more preferable because it is easy to handle and stable during the preparation of the solution.
　高分子化合物層１３には、高分子化合物層１３の外縁と同じ外縁を有する低分子化合物層としての有機半導体層１４が積層されている。有機半導体層１４を形成する有機半導体材料は、可溶性高分子化合物よりも小さい分子量を有する低分子化合物であって、可溶性高分子化合物を溶解する溶媒に分子ごとに分散される可溶性を備えた可溶性低分子化合物である。有機半導体層１４は、一種類の可溶性低分子化合物を含む単一の層であってもよいし、相互に異なる可溶性低分子化合物を含む単一の層であってもよいし、相互に異なる可溶性低分子化合物を含む２つ以上の層の積層体であってもよい。有機半導体層１４を構成する低分子化合物は、高分子化合物層１３を構成する高分子化合物と相溶する。 On the polymer compound layer 13, an organic semiconductor layer 14 as a low molecular compound layer having the same outer edge as that of the polymer compound layer 13 is laminated. The organic semiconductor material forming the organic semiconductor layer 14 is a low molecular weight compound having a molecular weight smaller than that of the soluble high molecular compound, and has a low solubility with a solubility dispersed for each molecule in a solvent that dissolves the soluble high molecular compound. It is a molecular compound. The organic semiconductor layer 14 may be a single layer containing one kind of soluble low molecular weight compound, may be a single layer containing different soluble low molecular weight compounds, or may be different from each other. It may be a laminate of two or more layers containing a low molecular compound. The low molecular compound constituting the organic semiconductor layer 14 is compatible with the polymer compound constituting the polymer compound layer 13.
　可溶性低分子化合物には、３つ以上の芳香族環を備える共役芳香族材料が用いられる。共役芳香族材料の芳香族環は、５員環以上７員環以上が好ましく、更には、５員環あるいは６員環がより好ましい。芳香族環は、セレン、テルル、リン、ケイ素、ホウ素、ヒ素、窒素、酸素、及び、硫黄等のヘテロ原子を含んでいてもよい。なお、有機半導体層１４の移動度が高められる観点では、芳香族環は、窒素、酸素、及び、硫黄の少なくとも１つを含んでいることがより好ましい。 A conjugated aromatic material having three or more aromatic rings is used for the soluble low molecular weight compound. The aromatic ring of the conjugated aromatic material is preferably a 5-membered ring or more and a 7-membered ring or more, and more preferably a 5-membered ring or a 6-membered ring. The aromatic ring may contain heteroatoms such as selenium, tellurium, phosphorus, silicon, boron, arsenic, nitrogen, oxygen, and sulfur. In addition, from the viewpoint of increasing the mobility of the organic semiconductor layer 14, it is more preferable that the aromatic ring contains at least one of nitrogen, oxygen, and sulfur.
　芳香族環上の水素は、例えば、アルキル基、アルコキシ基、ポリアルコキシ基、チオアルコキシル基、アシル基、アリール基、ハロゲン基、シアノ基、ニトロ基、アルキルアミノ基、及び、アリールアミノ基等の官能基に置換されていてもよい。なお、ハロゲン基には、例えば、フッ素基が用いられ、アルキルアミノ基、及び、アリールアミノ基には、第二級若しくは第三級が用いられる。芳香族環上の水素は、こうした官能基の誘導体で置換されていてもよい。 The hydrogen on the aromatic ring is, for example, an alkyl group, an alkoxy group, a polyalkoxy group, a thioalkoxyl group, an acyl group, an aryl group, a halogen group, a cyano group, a nitro group, an alkylamino group, and an arylamino group. It may be substituted with a functional group. As the halogen group, for example, a fluorine group is used, and as the alkylamino group and the arylamino group, secondary or tertiary is used. The hydrogen on the aromatic ring may be substituted with a derivative of such a functional group.
　可溶性低分子化合物には、より具体的には、ポリチオフェン、ポリ－３－ヘキシルチオフェン、ペンタセン、ポリアントラセン、ポリピロール、ポリアニリン、ポリアセチレン、ポリフェニレン、ポリフラン、ポリセレノフェン、ポリイソチアナフテン、ポリフェニレンスルフィド、ポリフェニレンビニレン、ポリチエニレンビニレン、ポリナフタレン、ポリピレン、ポリアズレン、フタロシアニン、メロシアニン、ポリエチレンジオキシチオフェン、ポリ［３，４－エチレンジオキシチオフェン］－ポリ［スチレンスルホン酸］、及び、６，１２－ジオキサンアンタントレンが用いられる。可溶性低分子化合物は、これらの低分子化合物の誘導体でもよい。 More specifically, soluble low molecular weight compounds include polythiophene, poly-3-hexylthiophene, pentacene, polyanthracene, polypyrrole, polyaniline, polyacetylene, polyphenylene, polyfuran, polyselenophene, polyisothianaphthene, polyphenylene sulfide, polyphenylene. Vinylene, polythienylene vinylene, polynaphthalene, polypyrene, polyazulene, phthalocyanine, merocyanine, polyethylenedioxythiophene, poly [3,4-ethylenedioxythiophene] -poly [styrenesulfonic acid], and 6,12-dioxaneanthane Tren is used. The soluble low molecular weight compound may be a derivative of these low molecular weight compounds.
　ゲート絶縁層１２の表面に対する可溶性低分子化合物の親和性は、可溶性高分子化合物のものより低いことが好ましい。固化した状態での可溶性低分子化合物の密度は、溶媒や可溶性高分子化合物より小さいことが好ましい。溶媒に対する可溶性低分子化合物の溶解度は、可溶性高分子化合物のものよりも小さいことが好ましい。 The affinity of the soluble low molecular compound for the surface of the gate insulating layer 12 is preferably lower than that of the soluble high molecular compound. The density of the soluble low molecular compound in the solidified state is preferably smaller than that of the solvent or the soluble high molecular compound. The solubility of the soluble low molecular compound in the solvent is preferably smaller than that of the soluble high molecular compound.
　ゲート絶縁層１２の長手方向の両端部には、有機半導体層１４と高分子化合物層１３とを挟む一対の電極であるソース電極１５とドレイン電極１６とが積層されている。ソース電極１５は、ゲート絶縁層１２の長手方向にて、有機半導体層１４の一端部に積層される。ドレイン電極１６は、ゲート絶縁層１２の長手方向にて、有機半導体層１４の他端部に積層される。ソース電極１５とドレイン電極１６とは、有機半導体層１４上においてチャンネル長Ｌだけ離間している。 A source electrode 15 and a drain electrode 16, which are a pair of electrodes sandwiching the organic semiconductor layer 14 and the polymer compound layer 13, are stacked on both ends in the longitudinal direction of the gate insulating layer 12. The source electrode 15 is stacked on one end of the organic semiconductor layer 14 in the longitudinal direction of the gate insulating layer 12. The drain electrode 16 is stacked on the other end portion of the organic semiconductor layer 14 in the longitudinal direction of the gate insulating layer 12. The source electrode 15 and the drain electrode 16 are separated from each other by a channel length L on the organic semiconductor layer 14.
　ソース電極１５とドレイン電極１６とには、例えば、金、白金、銀、銅、アルミニウム、及び、モリブデン等の単体や合金等の金属材料、あるいは、これら金属材料の酸化物が用いられる。ソース電極１５と有機半導体層１４との接合、及び、ドレイン電極１６と有機半導体層１４との接合は、オーミック接合であってもよいし、ショットキー接合であってもよい。薄膜トランジスタ１０の駆動方式は、ショットキー接合によって制約される場合がある。それゆえに、ソース電極１５と有機半導体層１４との接合、及び、ドレイン電極１６と有機半導体層１４との接合は、オーミック接合が好ましい。 For the source electrode 15 and the drain electrode 16, for example, a metal material such as gold, platinum, silver, copper, aluminum, and molybdenum, or a metal material such as an alloy, or an oxide of these metal materials is used. The junction between the source electrode 15 and the organic semiconductor layer 14 and the junction between the drain electrode 16 and the organic semiconductor layer 14 may be ohmic junctions or Schottky junctions. The driving method of the thin film transistor 10 may be restricted by a Schottky junction. Therefore, the junction between the source electrode 15 and the organic semiconductor layer 14 and the junction between the drain electrode 16 and the organic semiconductor layer 14 are preferably ohmic junctions.
　図２に示されるように、高分子化合物層１３と有機半導体層１４とは、ゲート絶縁層１２を挟んで、ゲート電極１１の直上に積層されている。
　ゲート絶縁層１２の上面である基準面１２ａに高分子化合物層１３は積層される。基準面１２ａのうち、少なくとも高分子化合物層１３に対応する範囲は平坦である。つまり、基準面１２ａにおける少なくとも高分子化合物層１３の積層される範囲は平坦である。図示した例では、基準面１２ａの全体が平坦である。高分子化合物層１３の下面である絶縁層下面１３ｂは、ゲート絶縁層１２の基準面１２ａの形状に倣う平坦な面である。 As shown in FIG. 2, the polymer compound layer 13 and the organic semiconductor layer 14 are stacked immediately above the gate electrode 11 with the gate insulating layer 12 interposed therebetween.
The polymer compound layer 13 is laminated on the reference surface 12 a that is the upper surface of the gate insulating layer 12. A range corresponding to at least the polymer compound layer 13 in the reference surface 12a is flat. That is, at least the range in which the polymer compound layer 13 is laminated on the reference surface 12a is flat. In the illustrated example, the entire reference surface 12a is flat. An insulating layer lower surface 13 b that is the lower surface of the polymer compound layer 13 is a flat surface that follows the shape of the reference surface 12 a of the gate insulating layer 12.
　高分子化合物層１３の上面１３ａに有機半導体層１４は形成される。上面１３ａは、有機半導体層１４と接合する全ての範囲で凹凸面である。有機半導体層１４の下面である半導体層下面１４ｂは、高分子化合物層１３の上面１３ａと一致する形状を有する面である。有機半導体層１４の上面である接合面１４ａは、上面１３ａの凸部に対応する位置に凸部を有し、上面１３ａの凹部に対応する位置に凹部を有する。つまり、接合面１４ａは、高分子化合物層１３と有機半導体層１４との積層方向における上面１３ａの凸部上で凸となり、積層方向における上面１３ａの凹部で凹となる。したがって、有機半導体層１４の接合面１４ａの全体は上面１３ａの形状に倣う凹凸面である。 The organic semiconductor layer 14 is formed on the upper surface 13 a of the polymer compound layer 13. The upper surface 13 a is an uneven surface in the entire range where the upper surface 13 a is bonded to the organic semiconductor layer 14. The semiconductor layer lower surface 14 b that is the lower surface of the organic semiconductor layer 14 is a surface having a shape that coincides with the upper surface 13 a of the polymer compound layer 13. The bonding surface 14a which is the upper surface of the organic semiconductor layer 14 has a convex portion at a position corresponding to the convex portion of the upper surface 13a, and has a concave portion at a position corresponding to the concave portion of the upper surface 13a. That is, the bonding surface 14a is convex on the convex portion of the upper surface 13a in the stacking direction of the polymer compound layer 13 and the organic semiconductor layer 14, and is concave in the concave portion of the upper surface 13a in the stacking direction. Therefore, the entire bonding surface 14a of the organic semiconductor layer 14 is an uneven surface that follows the shape of the upper surface 13a.
　例えば、図３に示されるように、接合面１４ａは、うねる曲線形状の凹部１４ｓを多数含む。うねる曲線形状は、接合面１４ａ内にて様々な方向に複数回湾曲した部分を有する形状である。例えば、凹部１４ｓの形状には、２つ以上に分岐する曲線形状、相互に平行な曲線形状、相対的に密度の高い部分から放射状に広がる曲線形状、及び、環状が含まれている。凹部１４ｓは、湾曲部分と直線形状に延びる部分とを含むことがあるが、湾曲部分に対し、直線形状部分の占める割合は顕著に小さい。なお、図３では、凹部１４ｓの幅が曲線の太さで示されて、凹部１４ｓに挟まれる部分が凸部として示されている。うねる曲線形状の凹部１４ｓとは、すなわち、複数の湾曲部分を含む不規則な形状の凹部である。上面１３ａ及び接合面１４ａは、すなわち、不規則な形状の凸部と凹部に占有された凹凸面である。 For example, as shown in FIG. 3, the joint surface 14 a includes a large number of wavy curved concave portions 14 s. The wavy curved shape is a shape having a portion that is curved a plurality of times in various directions within the joint surface 14a. For example, the shape of the recess 14 s includes a curved shape that branches into two or more, a curved shape that is parallel to each other, a curved shape that spreads radially from a relatively high density portion, and an annular shape. The recess 14s may include a curved portion and a portion extending in a linear shape, but the proportion of the linear portion is significantly smaller than the curved portion. In FIG. 3, the width of the recess 14s is indicated by the thickness of the curve, and the portion sandwiched between the recesses 14s is indicated as a protrusion. The wavy curved concave portion 14s is an irregularly shaped concave portion including a plurality of curved portions. The upper surface 13a and the bonding surface 14a are irregular surfaces occupied by irregularly shaped convex portions and concave portions.
　図４に示されるように、段差Ｈは、凸部１４ｃと凹部１４ｓとの高さの差である。この段差Ｈは、１ｎｍ以上１００ｎｍ以下である。段差間隔Ｐは、１つの凸部１４ｃを挟む２つの凹部１４ｓの距離である。この段差間隔Ｐは、１μｍ以上１０μｍ以下である。有機半導体層１４の接合面１４ａに形成された凸部１４ｃと凹部１４ｓとは、高分子化合物層１３の上面１３ａに形成された凹部と凸部とに追従した形状である。 As shown in FIG. 4, the level difference H is a difference in height between the convex portion 14c and the concave portion 14s. This step H is 1 nm or more and 100 nm or less. The step interval P is a distance between two concave portions 14s sandwiching one convex portion 14c. This step interval P is not less than 1 μm and not more than 10 μm. The convex portion 14 c and the concave portion 14 s formed on the bonding surface 14 a of the organic semiconductor layer 14 have a shape following the concave portion and the convex portion formed on the upper surface 13 a of the polymer compound layer 13.
　有機半導体層１４の接合面１４ａが凹凸面であるから、接合面１４ａが平坦な面である構造と比べて、接合面１４ａの表面積は大きい。それゆえに、接合面１４ａが平坦な面である構造と比べて、有機半導体層１４とソース電極１５との接合する面積は大きく、有機半導体層１４とソース電極１５との密着性は高められる。有機半導体層１４とドレイン電極１６との接合する面積も同様に拡大するから、有機半導体層１４とドレイン電極１６との密着性は高められる。さらに、段差Ｈ及び段差間隔Ｐが上述した大きさに設定されることにより、有機半導体層１４の接合面１４ａと各電極１５，１６との間の分子間力やクーロン力等の密着力もより大きなものとなるため、有機半導体層１４と各電極１５，１６との密着性がさらに高められる。 Since the bonding surface 14a of the organic semiconductor layer 14 is an uneven surface, the surface area of the bonding surface 14a is larger than the structure in which the bonding surface 14a is a flat surface. Therefore, compared to the structure in which the bonding surface 14a is a flat surface, the area where the organic semiconductor layer 14 and the source electrode 15 are bonded is large, and the adhesion between the organic semiconductor layer 14 and the source electrode 15 is enhanced. Since the area where the organic semiconductor layer 14 and the drain electrode 16 are joined similarly increases, the adhesion between the organic semiconductor layer 14 and the drain electrode 16 is enhanced. Furthermore, by setting the step H and the step interval P to the above-described sizes, the adhesion force between the bonding surface 14a of the organic semiconductor layer 14 and the electrodes 15 and 16 such as intermolecular force and Coulomb force is also greater. Therefore, the adhesion between the organic semiconductor layer 14 and the electrodes 15 and 16 is further enhanced.
　接合面１４ａにおける凹凸が複数のうねる曲線状であるから、接合面１４ａにおける凹凸は、様々な方向に延びることになる。それゆえに、接合面１４ａにおける凹凸が直線状に延びる構造と比べて、実施形態の有機半導体層１４に接合される電極と有機半導体層１４との密着性が高められる。特に、様々な方向への応力が薄膜トランジスタ１０に作用する場合には、有機半導体層１４に接合される電極と有機半導体層１４との密着性の向上が顕著になる。 Since the unevenness on the bonding surface 14a has a plurality of undulating curves, the unevenness on the bonding surface 14a extends in various directions. Therefore, the adhesion between the electrode bonded to the organic semiconductor layer 14 of the embodiment and the organic semiconductor layer 14 is enhanced as compared with the structure in which the unevenness on the bonding surface 14a extends linearly. In particular, when stress in various directions acts on the thin film transistor 10, the adhesion between the organic semiconductor layer 14 and the electrode bonded to the organic semiconductor layer 14 is significantly improved.
　一方で、有機半導体層１４の接合面１４ａが凹凸であるから、ソース電極１５やドレイン電極１６の形成に際して、凹部１４ｓに電極材料を埋め込む必要がある。この点で、段差Ｈは、２ｎｍ以上１００ｎｍ以下であって、段差間隔Ｐと比べて非常に小さい。すなわち、段差間隔Ｐに対する段差Ｈの比であるアスペクト比は、０．０１以下と非常に小さい値であるから、接合面１４ａが平坦な面である場合と同様の成膜技術によって、凹部１４ｓに電極材料を埋め込むことが可能である。ソース電極１５やドレイン電極１６の形成に際しては、凹部１４ｓに埋め込まれた電極材料をエッチングする必要もある。この点でも、凹部１４ｓのアスペクト比が非常に小さいから、接合面１４ａが平坦な面である場合と同様のエッチング技術によって、凹部１４ｓから電極材料をエッチングすることが可能にもなる。 On the other hand, since the bonding surface 14a of the organic semiconductor layer 14 is uneven, it is necessary to embed an electrode material in the recess 14s when the source electrode 15 and the drain electrode 16 are formed. In this respect, the step H is 2 nm or more and 100 nm or less, and is very small compared to the step interval P. That is, the aspect ratio, which is the ratio of the step H to the step interval P, is a very small value of 0.01 or less, so that the recess 14s is formed in the recess 14s by the same film forming technique as that when the bonding surface 14a is a flat surface. It is possible to embed an electrode material. In forming the source electrode 15 and the drain electrode 16, it is necessary to etch the electrode material embedded in the recess 14s. Also in this respect, since the aspect ratio of the concave portion 14s is very small, the electrode material can be etched from the concave portion 14s by the same etching technique as in the case where the bonding surface 14a is a flat surface.
　なお、段差Ｈが２ｎｍ以上１００ｎｍ以下と非常に小さいから、その段差Ｈに比べれば、１μｍ以上１０μｍ以下の段差間隔Ｐは非常に大きい。しかし、有機半導体層１４とソース電極１５とが重なる部分の面積や有機半導体層１４とドレイン電極１６とが重なる部分の面積と比べれば、段差間隔Ｐは非常に小さい。それゆえに、段差Ｈが小さいことによって上述の加工上の効果が得られつつも、有機半導体層１４とソース電極１５との密着性や有機半導体層１４とドレイン電極１６との密着性を高めることが可能となる。 In addition, since the level difference H is as small as 2 nm or more and 100 nm or less, the level difference P between 1 μm or more and 10 μm or less is very large compared to the level difference H. However, the step interval P is very small compared to the area of the portion where the organic semiconductor layer 14 and the source electrode 15 overlap and the area of the portion where the organic semiconductor layer 14 and the drain electrode 16 overlap. Therefore, it is possible to improve the adhesion between the organic semiconductor layer 14 and the source electrode 15 and the adhesion between the organic semiconductor layer 14 and the drain electrode 16 while obtaining the above-described processing effect due to the small step H. It becomes possible.
　凸部における厚さと凹部における厚さとが略等しいから、ソース電極１５とドレイン電極１６との間の有機半導体層１４では、有機半導体層１４の膜厚が略均一となる。それゆえに、有機半導体層１４の膜厚のばらつきに起因する電気特性のばらつきを抑えることが可能でもある。 Since the thickness at the convex portion and the thickness at the concave portion are substantially equal, in the organic semiconductor layer 14 between the source electrode 15 and the drain electrode 16, the thickness of the organic semiconductor layer 14 is substantially uniform. Therefore, it is possible to suppress variations in electrical characteristics due to variations in the film thickness of the organic semiconductor layer 14.
　有機半導体層１４に含まれる低分子化合物と高分子化合物層１３に含まれる高分子化合物とが可溶性を備えるから、有機半導体層１４と高分子化合物層１３とを塗布法等の湿式の成膜方法によって形成することが可能となる。それゆえに、有機半導体層１４と高分子化合物層１３とを蒸着法等の乾式の成膜方法によって形成する場合と比べて、成膜方法の簡素化を図ることが可能であって、薄膜トランジスタ１０ごとの性能のばらつきが抑えられる。 Since the low-molecular compound contained in the organic semiconductor layer 14 and the polymer compound contained in the polymer compound layer 13 are soluble, a wet film-forming method such as a coating method using the organic semiconductor layer 14 and the polymer compound layer 13. Can be formed. Therefore, compared with the case where the organic semiconductor layer 14 and the polymer compound layer 13 are formed by a dry film forming method such as an evaporation method, the film forming method can be simplified. Variation in performance is suppressed.
　有機半導体層１４を構成する低分子化合物と高分子化合物層１３を構成する高分子化合物とが相溶性を備えるから、有機半導体層１４を構成する低分子化合物を溶解する溶媒に、高分子化合物層１３を構成する高分子化合物を溶解することが可能になる。それゆえに、有機半導体層１４と高分子化合物層１３とを相分離法で形成することが可能であるから、有機半導体層１４と高分子化合物層１３との間に不要な物質が混入することが抑えられる。結果として、高分子化合物層１３と有機半導体層１４とに対し、薄膜トランジスタ１０の電気的な特性を高めることが可能となる。 Since the low-molecular compound constituting the organic semiconductor layer 14 and the high-molecular compound constituting the high-molecular compound layer 13 have compatibility, the high-molecular compound layer is dissolved in a solvent that dissolves the low-molecular compound constituting the organic semiconductor layer 14. 13 can be dissolved. Therefore, since the organic semiconductor layer 14 and the polymer compound layer 13 can be formed by a phase separation method, unnecessary substances may be mixed between the organic semiconductor layer 14 and the polymer compound layer 13. It can be suppressed. As a result, the electrical characteristics of the thin film transistor 10 can be enhanced with respect to the polymer compound layer 13 and the organic semiconductor layer 14.
　例えば、有機半導体層１４と高分子化合物層１３との界面が、薄膜トランジスタ１０ごとに安定するから、上述の高分子材料を含む高分子化合物層１３が備えられない構成と比べて、薄膜トランジスタ１０におけるキャリアの移動度やオンオフ比が、薄膜トランジスタ１０ごとにばらつくことが抑えられる。なお、オンオフ比とは、薄膜トランジスタ１０がオン状態であるときのソース電極１５とドレイン電極１６との間の電流と、薄膜トランジスタ１０がオフ状態であるときのソース電極１５とドレイン電極１６との間の電流に対する比である。 For example, since the interface between the organic semiconductor layer 14 and the polymer compound layer 13 is stabilized for each thin film transistor 10, the carrier in the thin film transistor 10 is compared with a configuration in which the polymer compound layer 13 containing the above polymer material is not provided. The mobility and the on / off ratio of the thin film transistor 10 can be prevented from varying for each thin film transistor 10. Note that the on / off ratio refers to the current between the source electrode 15 and the drain electrode 16 when the thin film transistor 10 is in the on state and the current between the source electrode 15 and the drain electrode 16 when the thin film transistor 10 is in the off state. It is the ratio to the current.
　そして、ゲート絶縁層１２を構成する高分子化合物と高分子化合物層１３を構成する高分子化合物とが相溶しないから、ゲート絶縁層１２が形成された後に、高分子化合物層１３を液相のプロセスで形成することが可能になる。それゆえに、有機半導体層１４の下地に求められる絶縁性がゲート絶縁層１２で得られない場合であっても、高分子化合物層１３によってそれを補うことが可能となる。 And since the high molecular compound which comprises the gate insulating layer 12 and the high molecular compound which comprises the high molecular compound layer 13 are incompatible, after the gate insulating layer 12 is formed, the high molecular compound layer 13 is made into a liquid phase. It becomes possible to form in the process. Therefore, even when the insulating properties required for the base of the organic semiconductor layer 14 cannot be obtained by the gate insulating layer 12, it can be supplemented by the polymer compound layer 13.
　［半導体デバイスの製造方法］
　次に、上述の薄膜トランジスタ１０の製造方法の一例について説明する。
　図５に示されるように、まず、基板Ｓの上面にゲート電極１１が形成される。例えば、上述の金属材料を含む金属層が基板Ｓの上面の全体に形成された後に、マスクを用いるエッチングによって金属層が加工されて、ゲート電極１１が形成される。基板Ｓには、例えば、アルミニウム、ニッケル、及び、ステンレス等の金属基板、あるいは、ポリカーボネートやポリエチレンテレフタレート等のプラスチックフィルムが用いられる。金属層の形成には、例えば、スパッタリング法、真空蒸着法、電界めっき、及び、印刷法等が用いられる。マスクには、レジストマスク、金属材料や絶縁材料を含むハードマスクが用いられる。金属層のエッチングには、イオンミリング、反応性イオンエッチング、及び、ウェットエッチング等が用いられる。 [Method for Manufacturing Semiconductor Device]
Next, an example of a method for manufacturing the above-described thin film transistor 10 will be described.
As shown in FIG. 5, first, the gate electrode 11 is formed on the upper surface of the substrate S. For example, after the metal layer containing the above-described metal material is formed on the entire top surface of the substrate S, the metal layer is processed by etching using a mask to form the gate electrode 11. For the substrate S, for example, a metal substrate such as aluminum, nickel, and stainless steel, or a plastic film such as polycarbonate or polyethylene terephthalate is used. For the formation of the metal layer, for example, a sputtering method, a vacuum evaporation method, an electroplating method, a printing method, or the like is used. As the mask, a resist mask, a hard mask containing a metal material or an insulating material is used. For the etching of the metal layer, ion milling, reactive ion etching, wet etching, or the like is used.
　次いで、ゲート電極１１の全体を覆うゲート絶縁層１２が形成される。ゲート絶縁層１２の形成には、例えば、上述の無機材料をターゲットに用いるスパッタリング法、上述の無機材料を気相成長させるＣＶＤ法が用いられる。ゲート絶縁層１２の形成には、例えば、上述の有機材料が含まれるインクを用いる塗布法や印刷法が用いられる。 Next, a gate insulating layer 12 covering the entire gate electrode 11 is formed. For forming the gate insulating layer 12, for example, a sputtering method using the above-described inorganic material as a target or a CVD method in which the above-described inorganic material is vapor-phase grown is used. For forming the gate insulating layer 12, for example, a coating method or a printing method using an ink containing the above-described organic material is used.
　成膜用溶液は、上述の可溶性高分子化合物と可溶性低分子化合物とが上述の溶媒に溶解されることで調製される。あるいは、上述の可溶性分子化合物の前駆体と可溶性低分子化合物とが上述の溶媒に溶解されることで、成膜用溶液が調製されてもよい。 The film-forming solution is prepared by dissolving the above-described soluble polymer compound and soluble low-molecular compound in the above-described solvent. Alternatively, the film-forming solution may be prepared by dissolving the above-described soluble molecular compound precursor and the soluble low-molecular compound in the above-described solvent.
　図６に示されるように、成膜用溶液がゲート絶縁層１２上に供給されることによって、ゲート絶縁層１２上に液膜１７が形成される。そして、ゲート絶縁層１２上に形成された液膜１７は、例えば、オーブン等の加熱装置によって焼成処理が施される。なお、可溶性高分子化合物の前駆体が成膜用溶液に含まれる場合には、上述の焼成処理に先立って、例えば、光照射や加熱によって前駆体を用いる重合反応が進行されて、液膜１７の内部に可溶性高分子化合物が生成される。 As shown in FIG. 6, a liquid film 17 is formed on the gate insulating layer 12 by supplying the film forming solution onto the gate insulating layer 12. The liquid film 17 formed on the gate insulating layer 12 is baked by a heating device such as an oven. When the precursor of the soluble polymer compound is contained in the film forming solution, the polymerization reaction using the precursor is advanced by, for example, light irradiation or heating prior to the above-described baking treatment, and the liquid film 17 A soluble polymer compound is produced in the inside.
　この際に、高分子化合物層１３と有機半導体層１４とが、これらが積層される方向にて完全に分離されるうえでは、以下に示される成膜用溶液の調製が好ましい。すなわち、可溶性低分子化合物の溶媒に対する溶解度、及び可溶性高分子化合物の溶媒に対する溶解度はいずれも、０．１重量％以上であることが好ましく、０．３重量％以上であることがより好ましく、０．５重量％以上であることがさらに好ましい。可溶性低分子化合物に対する可溶性高分子化合物の重量比は、特に限定されないが、中でも、１／１０以上１０以下が好ましく、１／５以上５以下がより好ましく、１／３以上３以下がさらに好ましい。 At this time, in order to completely separate the polymer compound layer 13 and the organic semiconductor layer 14 in the direction in which they are laminated, it is preferable to prepare a film forming solution shown below. That is, the solubility of the soluble low molecular compound in the solvent and the solubility of the soluble high molecular compound in the solvent are both preferably 0.1% by weight or more, more preferably 0.3% by weight or more. More preferably, it is 5% by weight or more. The weight ratio of the soluble polymer compound to the soluble low-molecular compound is not particularly limited, but is preferably 1/10 or more, 10 or less, more preferably 1/5 or more and 5 or less, and further preferably 1/3 or more and 3 or less.
　上述の液膜１７の形成には、浸漬法、噴霧法、塗布法、及び、印刷法が用いられる。塗布法や印刷法には、例えば、キャストコーティング法、スプレーコーティング法、インクジェット印刷法、凸版印刷法、フレキソ印刷法、スクリーン印刷法、グラビア印刷法、及び、グラビアオフセット印刷法等が用いられる。 For the formation of the liquid film 17, the dipping method, the spraying method, the coating method, and the printing method are used. As the coating method and the printing method, for example, a cast coating method, a spray coating method, an ink jet printing method, a relief printing method, a flexographic printing method, a screen printing method, a gravure printing method, and a gravure offset printing method are used.
　図７に示されるように、ゲート絶縁層１２上に形成された液膜１７に焼成処理が施されると、高分子化合物を含む相と可溶性低分子化合物を含む相とに相分離する。これにより、ゲート絶縁層１２上には高分子化合物層１３が形成され、且つ、高分子化合物層１３上には有機半導体層１４が形成される。この際に、高分子化合物層１３の上面１３ａと有機半導体層１４の接合面１４ａとに凹部と凸部とが形成される。 As shown in FIG. 7, when the liquid film 17 formed on the gate insulating layer 12 is baked, it is separated into a phase containing a high molecular compound and a phase containing a soluble low molecular weight compound. As a result, the polymer compound layer 13 is formed on the gate insulating layer 12, and the organic semiconductor layer 14 is formed on the polymer compound layer 13. At this time, concave portions and convex portions are formed on the upper surface 13 a of the polymer compound layer 13 and the bonding surface 14 a of the organic semiconductor layer 14.
　なお、図７の破線で示されるように、ゲート絶縁層１２の上面の全体に可溶性分子層が形成される場合には、マスクを用いた可溶性分子層のエッチングによって高分子化合物層１３と有機半導体層１４とが形成される。マスクのパターニング方法には、例えば、フォトリソグラフィ法、又は、電子ビームリソグラフィ法等が用いられ、エッチング方法には、例えば、ウェットエッチング法等が用いられる。なお、高分子化合物層１３と有機半導体層１４とが形成される部位にのみ成膜用溶液が供給される場合には、その成膜用溶液が焼成されることによって、高分子化合物層１３と有機半導体層１４とが形成される。 In the case where a soluble molecular layer is formed on the entire upper surface of the gate insulating layer 12 as shown by a broken line in FIG. 7, the polymer compound layer 13 and the organic semiconductor are etched by etching the soluble molecular layer using a mask. Layer 14 is formed. For example, a photolithography method or an electron beam lithography method is used as the mask patterning method, and a wet etching method is used as the etching method, for example. In addition, when the film-forming solution is supplied only to the site where the polymer compound layer 13 and the organic semiconductor layer 14 are formed, the film-forming solution is baked, so that the polymer compound layer 13 and An organic semiconductor layer 14 is formed.
　上述の上面１３ａや接合面１４ａに形成される凹凸は、液膜１７に施される焼成の速度によって調製することが可能である。例えば、焼成の速度が高いほど、段差Ｈは小さくなり、薄膜トランジスタ１０の電気的な特性が高められる。液膜１７にて焼成処理の開始状態の均一化を図り、薄膜トランジスタ１０ごとの電気的な特性の均一性を高めるうえでは、液膜１７から溶媒が蒸発することを焼成処理前に抑える、例えば、液膜１７が形成された直後に焼成処理を開始する、あるいは、液膜１７の形成を加圧下で行うことが好ましい。 The irregularities formed on the upper surface 13a and the bonding surface 14a can be prepared by the firing rate applied to the liquid film 17. For example, the higher the baking speed, the smaller the step H, and the electrical characteristics of the thin film transistor 10 are improved. In order to equalize the starting state of the firing process in the liquid film 17 and to increase the uniformity of the electrical characteristics of each thin film transistor 10, the evaporation of the solvent from the liquid film 17 is suppressed before the firing process. It is preferable to start the baking immediately after the liquid film 17 is formed, or to form the liquid film 17 under pressure.
　高分子化合物層１３と有機半導体層１４とが形成されると、有機半導体層１４の面方向における対向する２つの端部に、ソース電極１５とドレイン電極１６とが形成される。この際に、まず、金属膜の形成時には、ゲート絶縁層１２の全体を覆う金属膜が形成される。そして、金属膜における有機半導体層１４の上方の領域を覆うレジスパターンが形成された後、レジストパターンを用いた金属膜のエッチングが行われる。 When the polymer compound layer 13 and the organic semiconductor layer 14 are formed, the source electrode 15 and the drain electrode 16 are formed at two opposing ends in the surface direction of the organic semiconductor layer 14. At this time, first, when forming the metal film, a metal film covering the entire gate insulating layer 12 is formed. Then, after a resist pattern covering the region above the organic semiconductor layer 14 in the metal film is formed, the metal film is etched using the resist pattern.
　［実施例１］
　基板Ｓとして、ホウ素、リン、アンチモン、及び、ヒ素の少なくとも１つが注入されたシリコン基板が用いられて、基板Ｓの表面に、ゲート電極１１としてタングステン層が形成された後に、ゲート絶縁層１２として、膜厚が５００ｎｍのポリビフェノール樹脂層が形成された。 [Example 1]
As the substrate S, a silicon substrate into which at least one of boron, phosphorus, antimony, and arsenic is implanted is used. After a tungsten layer is formed as the gate electrode 11 on the surface of the substrate S, the gate insulating layer 12 is formed. A polybiphenol resin layer having a thickness of 500 nm was formed.
　可溶性高分子化合物と可溶性低分子化合物と溶媒とに、それぞれシクロオレフィンコポリマーとジオキサンアンタントレン系化合物とトルエンとが用いられて成膜用溶液が調製された。シクロオレフィンコポリマーとは、ポリプラスチックス株式会社製のＴＯＰＡＳ６０１５（ＴＯＰＡＳはTopas Advanced Polymers GmbHの登録商標）である。ジオキサンアンタントレン系化合物とは、以下の化学式１に示されるように、３，９－ビス（ｐ－メチルフェニル）ペリキサンテノキサンテンである。成膜用溶液では、シクロオレフィンコポリマーとジオキサンアンタントレン系化合物とが重量比で１：１とされて、これら溶質の濃度が０．４５重量％とされた。 A film-forming solution was prepared using a cycloolefin copolymer, a dioxaneanthanthrene compound, and toluene, respectively, as a soluble polymer compound, a soluble low-molecular compound, and a solvent. The cycloolefin copolymer is TOPAS6015 (TOPAS is a registered trademark of TopasＴＯAdvanced Polymers GmbH) manufactured by Polyplastics Co., Ltd. The dioxaneanthanthrene compound is 3,9-bis (p-methylphenyl) perixanthenoxanthene as shown in the following chemical formula 1. In the film-forming solution, the cycloolefin copolymer and the dioxaneanthanthrene compound were 1: 1 by weight, and the concentration of these solutes was 0.45% by weight.
Figure JPOXMLDOC01-appb-C000001
 　ゲート絶縁層１２の上面の全体に上述の成膜用溶液がスピンコート法によって塗布されて、上述の成膜用溶液からなる液膜１７が形成された。不活性ガスの雰囲気で液膜１７が１４０℃に加熱されることによって、液膜１７が乾燥、及び焼成された。これにより、高分子化合物層１３と有機半導体層１４とが形成された。
Figure JPOXMLDOC01-appb-C000001
 The film-forming solution described above was applied to the entire upper surface of the gate insulating layer 12 by a spin coating method to form a liquid film 17 made of the film-forming solution described above. By heating the liquid film 17 to 140 ° C. in an inert gas atmosphere, the liquid film 17 was dried and baked. Thereby, the polymer compound layer 13 and the organic semiconductor layer 14 were formed.
　高分子化合物層１３と有機半導体層１４とがエッチングされた後に、有機半導体層１４にて相互に対向する２つの端部に金のソース電極１５と金のドレイン電極１６とが形成されて、実施例１の薄膜トランジスタ１０が作成された。 After the polymer compound layer 13 and the organic semiconductor layer 14 are etched, a gold source electrode 15 and a gold drain electrode 16 are formed at two ends facing each other in the organic semiconductor layer 14. The thin film transistor 10 of Example 1 was produced.
　有機半導体層１４の膜厚は約２０ｎｍであり、ソース電極１５とドレイン電極１６との距離であるチャンネル長Ｌは約５０μｍであり、ソース電極１５の幅あるいはドレイン電極１６の幅であるチャンネル幅Ｗは３０ｍｍであった。 The film thickness of the organic semiconductor layer 14 is about 20 nm, the channel length L that is the distance between the source electrode 15 and the drain electrode 16 is about 50 μm, and the channel width W that is the width of the source electrode 15 or the drain electrode 16. Was 30 mm.
　［実施例２］
　液膜１７の厚さのみが実施例１よりも大きくされ、液膜１７の容量以外の条件が実施例１と同じ方法によって、有機半導体層１４の膜厚が約３０ｎｍである実施例２の薄膜トランジスタ１０が作成された。 [Example 2]
The thin film transistor of Example 2 in which only the thickness of the liquid film 17 is made larger than that of Example 1, and the film thickness of the organic semiconductor layer 14 is about 30 nm by the same method as in Example 1 except for the capacity of the liquid film 17 10 was created.
　［実施例３］
　液膜１７の厚さのみが実施例２よりも大きくされ、液膜１７の容量以外の条件が実施例１と同じ方法によって、有機半導体層１４の膜厚が約５０ｎｍである実施例３の薄膜トランジスタ１０が作成された。 [Example 3]
The thin film transistor of Example 3 in which only the thickness of the liquid film 17 is made larger than that of Example 2 and the film thickness of the organic semiconductor layer 14 is about 50 nm by the same method as in Example 1 except for the capacity of the liquid film 17 10 was created.
　［実施例４］
　平均分子量が１０万であるポリアルファメチルスチレンが可溶性高分子化合物に用いられて、可溶性高分子化合物以外の条件が実施例１と同じ方法によって、有機半導体層１４の膜厚が約２０ｎｍである実施例４の薄膜トランジスタ１０が作成された。 [Example 4]
Implementation in which polyalphamethylstyrene having an average molecular weight of 100,000 is used for the soluble polymer compound, and the film thickness of the organic semiconductor layer 14 is about 20 nm by the same method as in Example 1 except for the soluble polymer compound The thin film transistor 10 of Example 4 was produced.
　［実施例５］
　液膜１７の容量のみが実施例４よりも大きくされ、液膜１７の容量以外の条件が実施例４と同じ方法によって、有機半導体層１４の膜厚が約３０ｎｍである実施例５の薄膜トランジスタ１０が作成された。 [Example 5]
Only the capacity of the liquid film 17 is made larger than that of Example 4, and the film thickness of the organic semiconductor layer 14 is about 30 nm by the same method as in Example 4 except for the capacity of the liquid film 17. Was created.
　［実施例６］
　液膜１７の厚さのみが実施例５よりも大きくされ、液膜１７の容量以外の条件が実施例４と同じ方法によって、有機半導体層１４の膜厚が約５０ｎｍである実施例６の薄膜トランジスタ１０が作成された。 [Example 6]
The thin film transistor of Example 6 in which only the thickness of the liquid film 17 is made larger than that of Example 5 and the film thickness of the organic semiconductor layer 14 is about 50 nm by the same method as in Example 4 except for the capacity of the liquid film 17 10 was created.
　［比較例］
　可溶性低分子化合物のみが溶媒に含まれる成膜用溶液が調製されて、成膜用溶液の組成以外の条件が実施例１と同じ方法によって、有機半導体層の膜厚が約２０ｎｍである比較例の薄膜トランジスタが作成された。 [Comparative example]
Comparative example in which a film forming solution containing only a soluble low molecular weight compound in a solvent is prepared, and the film thickness of the organic semiconductor layer is about 20 nm by the same method as in Example 1 except for the composition of the film forming solution. Thin film transistors were created.
　実施例１～６、及び、比較例の各々における有機半導体層１４の表面粗さが、ＪＩＳＢ０６０１に準じて測定された。
　実施例１～６、及び、比較例の各々における有機半導体層１４の移動度が、以下の方法で測定された。すなわち、移動度の測定では、各薄膜トランジスタが、２３℃の不活性ガスの雰囲気に置かれて、ソース電極１５にソース電圧Ｖｓ（Ｖｓｓ＝０Ｖ）が印加され、且つ、ドレイン電極１６への印加電圧であるドレイン電圧Ｖｄが、ゲート電極１１への印加電圧であるゲート電圧Ｖｇ以上（Ｖｄ≧Ｖｇ）に設定された。そして、ドレイン電流の平方根とゲート電圧Ｖｇとの関係を示すＶｇ－Ｉｄ曲線が、－３０Ｖ≦Ｖｇ≦０Ｖの範囲で測定されて、ゲート電圧Ｖｇに対するドレイン電流の平方根の傾きから移動度が算出された。 The surface roughness of the organic semiconductor layer 14 in each of Examples 1 to 6 and Comparative Example was measured according to JISB0601.
The mobility of the organic semiconductor layer 14 in each of Examples 1 to 6 and Comparative Example was measured by the following method. That is, in the measurement of mobility, each thin film transistor is placed in an atmosphere of an inert gas at 23 ° C., a source voltage Vs (Vss = 0 V) is applied to the source electrode 15, and an applied voltage to the drain electrode 16. The drain voltage Vd is set to be equal to or higher than the gate voltage Vg (Vd ≧ Vg) as the voltage applied to the gate electrode 11. Then, a Vg-Id curve showing the relationship between the square root of the drain current and the gate voltage Vg is measured in the range of −30 V ≦ Vg ≦ 0 V, and the mobility is calculated from the slope of the square root of the drain current with respect to the gate voltage Vg. It was.
　実施例１～６、及び、比較例の各々における有機半導体層１４の移動度が、以下の巻き付け試験後に測定された。すなわち、巻き付け試験では、テスト棒に対する基板の巻き付けと、テスト棒に巻き付けられた基板の巻き取りとが、実施例１～６、及び、比較例の基板の各々で１万回繰り返された。テスト棒には、半径が５ｍｍの円柱が用いられた。 The mobility of the organic semiconductor layer 14 in each of Examples 1 to 6 and Comparative Example was measured after the following winding test. That is, in the winding test, the winding of the substrate around the test rod and the winding of the substrate wound around the test rod were repeated 10,000 times for each of Examples 1 to 6 and the substrate of the comparative example. A cylinder with a radius of 5 mm was used for the test bar.
　実施例１～６、及び、比較例の各々における表面粗さＲａ、及び、移動度の測定結果を表１に示す。表１に示されるように、実施例１から実施例６のいずれにおいても、有機半導体層１４の表面粗さＲａは、２ｎｍ以上であることが認められた。実施例１から実施例３における測定結果、及び、実施例４から実施例６における測定結果から、有機半導体層１４の膜厚が大きいほど、表面粗さＲａは大きくなることが認められた。さらに、実施例１から実施例３における測定結果と、実施例４から実施例６における測定結果との比較から、可溶性高分子化合物が異なっていても、膜厚が同一であれば、有機半導体層１４の表面粗さＲａは略等しいことが認められた。 Table 1 shows the measurement results of the surface roughness Ra and the mobility in each of Examples 1 to 6 and Comparative Example. As shown in Table 1, in any of Examples 1 to 6, it was recognized that the surface roughness Ra of the organic semiconductor layer 14 was 2 nm or more. From the measurement results in Example 1 to Example 3 and the measurement results in Example 4 to Example 6, it was recognized that the surface roughness Ra increases as the film thickness of the organic semiconductor layer 14 increases. Further, from the comparison between the measurement results in Example 1 to Example 3 and the measurement results in Example 4 to Example 6, the organic semiconductor layer can be used as long as the film thickness is the same even if the soluble polymer compounds are different. It was confirmed that the surface roughness Ra of 14 was substantially equal.
Figure JPOXMLDOC01-appb-T000002
 　実施例４における有機半導体層１４の接合面１４ａを原子間力顕微鏡によって撮像した結果を図８に示す。なお、図８では、深さの大きい部分ほど有機半導体層１４の像が黒く示されている。図８に示されるように、有機半導体層１４の接合面１４ａの全体は、多数のうねる曲線状をなす凹凸が形成されていることが認められた。なお、実施例１から実施例３、実施例５、及び、実施例６における有機半導体層１４の接合面１４ａにも、図８に示される凹凸と略同様の凹凸が形成されていることが認められた。これに対し、比較例１の有機半導体層における表面粗さＲａは１ｎｍ以下であって、その表面には、上述の凹凸が認められなかった。
Figure JPOXMLDOC01-appb-T000002
 The result of having imaged the joint surface 14a of the organic-semiconductor layer 14 in Example 4 with the atomic force microscope is shown in FIG. In FIG. 8, the image of the organic semiconductor layer 14 is shown in black as the depth increases. As shown in FIG. 8, it was recognized that the entire bonding surface 14 a of the organic semiconductor layer 14 was formed with a number of wavy curved irregularities. In addition, it is recognized that the unevenness | corrugation substantially the same as the unevenness | corrugation shown in FIG. 8 is formed also in the joint surface 14a of the organic-semiconductor layer 14 in Example 1- Example 3, Example 5, and Example 6. FIG. It was. On the other hand, the surface roughness Ra of the organic semiconductor layer of Comparative Example 1 was 1 nm or less, and the above-described unevenness was not observed on the surface.
　実施例１から実施例６の各々の移動度は、初期値として約０．５（ｃｍ２／Ｖｓ）を示し、巻き付け試験後にも、初期値の９０％以上を示すことが認められた。これに対し、比較例の移動度は、初期値として０．４（ｃｍ２／Ｖｓ）を示し、巻き付け試験後には、初期値の１２．５％にまで低下していることが認められた。 The mobility of each of Example 1 to Example 6 was about 0.5 (cm2 / Vs) as an initial value, and it was recognized that 90% or more of the initial value was exhibited even after the winding test. On the other hand, the mobility of the comparative example showed 0.4 (cm2 / Vs) as an initial value, and after the winding test, it was recognized that the mobility dropped to 12.5% of the initial value.
　以上説明したように、上述の実施形態によれば、以下の効果を得ることができる。
　・接合面１４ａが凹凸面であるから、有機半導体層１４と電極との接合する面積が大きくなる。結果として、有機半導体層１４と電極との密着性が高められる。 As described above, according to the above-described embodiment, the following effects can be obtained.
-Since the joining surface 14a is an uneven surface, the area where the organic semiconductor layer 14 and the electrode are joined increases. As a result, the adhesion between the organic semiconductor layer 14 and the electrode is improved.
　・接合面１４ａにおける凹凸が複数のうねる曲線状であるから、特に、様々な方向への応力が薄膜トランジスタ１０に作用する場合には、有機半導体層１４と電極との密着性の向上が顕著になる。 -Since the unevenness on the bonding surface 14a has a plurality of undulating curves, particularly when stress in various directions acts on the thin film transistor 10, the improvement in adhesion between the organic semiconductor layer 14 and the electrode becomes remarkable. .
　・段差間隔Ｐに対する段差Ｈの比であるアスペクト比が０．０１以下と非常に小さい値であるから、接合面１４ａが平坦な面である場合と同様の加工技術によって電極を形成することが可能である。 Since the aspect ratio, which is the ratio of the step H to the step interval P, is a very small value of 0.01 or less, it is possible to form electrodes by the same processing technique as when the bonding surface 14a is a flat surface. It is.
　・凸部における厚さと凹部における厚さとが略等しいから、有機半導体層１４の膜厚のばらつきに起因する電気特性のばらつきを抑えることが可能でもある。
　・有機半導体層１４の形成材料と高分子化合物層１３の形成材料とが相溶性を備えるから、有機半導体層１４と高分子化合物層１３とを湿式の相分離法によって形成することが可能となる。それゆえに、有機半導体層１４と高分子化合物層１３との形成方法の簡素化を図ること、薄膜トランジスタ１０ごとの性能のばらつきを抑えること、これらが可能にもなる。
［半導体デバイスの変形例］
　以下に、本開示の技術における半導体デバイスをトップコンタクト型の薄膜トランジスタに具体化した変形例について説明する。 -Since the thickness in the convex part and the thickness in the concave part are substantially equal, it is also possible to suppress the dispersion | variation in the electrical property resulting from the dispersion | variation in the film thickness of the organic-semiconductor layer 14. FIG.
Since the material for forming the organic semiconductor layer 14 and the material for forming the polymer compound layer 13 have compatibility, the organic semiconductor layer 14 and the polymer compound layer 13 can be formed by a wet phase separation method. . Therefore, it is possible to simplify the formation method of the organic semiconductor layer 14 and the polymer compound layer 13 and to suppress variation in performance of each thin film transistor 10.
[Modification of semiconductor device]
Hereinafter, a modified example in which the semiconductor device according to the technology of the present disclosure is embodied as a top contact type thin film transistor will be described.
　図９に示されるように、上述の可溶性高分子化合物を含む高分子化合物層２３には、上述の可溶性低分子化合物を含む有機半導体層２４が積層されている。高分子化合物層２３の下面である絶縁層下面２３ｂは、平坦な面である一方、高分子化合物層２３の上面２３ａは、有機半導体層２４と接合する全ての範囲で凹凸面である。有機半導体層２４の下面である半導体層下面２４ｂは、高分子化合物層２３の上面２３ａと一致する形状を有する面である。有機半導体層２４の上面である接合面２４ａは、上面２３ａの凸部に対応する位置に凸部を有し、上面２３ａの凹部に対応する位置に凹部を有する。つまり、接合面２４ａは、高分子化合物層２３と有機半導体層２４との積層方向における上面２３ａの凸部上で凸となり、上面２３ａの凹部上で凹となる。したがって、有機半導体層２４の全体は上面２３ａの形状に倣う凹凸面である。接合面２４ａに形成される凸部の形状と凹部の形状とには、上述の接合面１４ａと同様に、うねる曲線形状が多数含まれている。 As shown in FIG. 9, an organic semiconductor layer 24 containing the above-described soluble low-molecular compound is laminated on the polymer compound layer 23 containing the above-mentioned soluble polymer compound. The insulating layer lower surface 23 b, which is the lower surface of the polymer compound layer 23, is a flat surface, while the upper surface 23 a of the polymer compound layer 23 is an uneven surface in the entire range bonded to the organic semiconductor layer 24. The semiconductor layer lower surface 24 b that is the lower surface of the organic semiconductor layer 24 is a surface having a shape that coincides with the upper surface 23 a of the polymer compound layer 23. The bonding surface 24a that is the upper surface of the organic semiconductor layer 24 has a convex portion at a position corresponding to the convex portion of the upper surface 23a, and has a concave portion at a position corresponding to the concave portion of the upper surface 23a. That is, the bonding surface 24a is convex on the convex portion of the upper surface 23a in the stacking direction of the polymer compound layer 23 and the organic semiconductor layer 24, and is concave on the concave portion of the upper surface 23a. Therefore, the entire organic semiconductor layer 24 is an uneven surface that follows the shape of the upper surface 23a. The shape of the convex portion and the shape of the concave portion formed on the joint surface 24a include many undulating curved shapes as in the case of the joint surface 14a.
　有機半導体層２４の接合面２４ａの一部には、相互に離れた一対の電極であるソース電極２５とドレイン電極２６とが積層されている。接合面２４ａの残部には、ソース電極２５とドレイン電極２６とを覆うゲート絶縁層２２が積層されている。ゲート絶縁層２２の上面のうちソース電極２５とドレイン電極２６との間の上方には、ゲート電極２１が積層されている。 A part of the bonding surface 24 a of the organic semiconductor layer 24 is laminated with a source electrode 25 and a drain electrode 26 which are a pair of electrodes separated from each other. A gate insulating layer 22 that covers the source electrode 25 and the drain electrode 26 is stacked on the remaining portion of the bonding surface 24a. On the upper surface of the gate insulating layer 22, the gate electrode 21 is stacked above the source electrode 25 and the drain electrode 26.
　こうしたトップゲート型の薄膜トランジスタでも、先に説明されたボトムゲート型の薄膜トランジスタと同様に、接合面２４ａが凹凸面であるから、有機半導体層２４と電極との接合する面積が大きくなる。結果として、有機半導体層２４と電極との密着性が高められる。 Even in such a top gate type thin film transistor, as in the case of the bottom gate type thin film transistor described above, since the bonding surface 24a is an uneven surface, the area where the organic semiconductor layer 24 and the electrode are bonded increases. As a result, the adhesion between the organic semiconductor layer 24 and the electrode is improved.
　なお、上述の半導体デバイスは、以下のように変更することもできる。
　・有機半導体層１４の接合面１４ａのうち電極が接合されていない部位の下方では、有機半導体層１４と高分子化合物層１３とが分離されていなくともよい。すなわち、接合面１４ａのうち少なくとも電極が接合される部位の下方で、有機半導体層１４と高分子化合物層１３とが分離されていればよい。接合面２４ａのうち少なくとも電極が接合される部位の下方で、有機半導体層２４と高分子化合物層２３とが分離されていればよい。 In addition, the above-mentioned semiconductor device can also be changed as follows.
The organic semiconductor layer 14 and the polymer compound layer 13 do not have to be separated below the portion of the bonding surface 14a of the organic semiconductor layer 14 where the electrode is not bonded. That is, it is only necessary that the organic semiconductor layer 14 and the polymer compound layer 13 are separated at least below the portion of the bonding surface 14a where the electrodes are bonded. It is only necessary that the organic semiconductor layer 24 and the polymer compound layer 23 be separated at least below the portion of the bonding surface 24a where the electrodes are bonded.
　・ゲート絶縁層１２の上面が凹凸面である場合には、高分子化合物層１３が割愛されて、有機半導体層１４がゲート絶縁層１２に直接積層されてもよい。有機半導体層２４の形成される基板の上面が凹凸面である場合には、高分子化合物層２３が割愛されて、有機半導体層２４が基板の上面に直接積層されてもよい。要は、有機半導体層１４は、絶縁層における凹凸面である上面に積層されていればよい。 When the upper surface of the gate insulating layer 12 is an uneven surface, the polymer compound layer 13 may be omitted and the organic semiconductor layer 14 may be directly stacked on the gate insulating layer 12. When the upper surface of the substrate on which the organic semiconductor layer 24 is formed is an uneven surface, the polymer compound layer 23 may be omitted and the organic semiconductor layer 24 may be directly laminated on the upper surface of the substrate. In short, the organic semiconductor layer 14 may be laminated on the upper surface, which is an uneven surface in the insulating layer.
　・接合面１４ａ，２４ａの備える凹部の形状は、１つの方向に延びる直線形状であってもよいし、相互に交差する方向に延びる格子形状であってもよい。例えば、高分子化合物層１３，２３の下地が、予め直線形状や格子形状のパターンを備えていてもよい。あるいは、絶縁層の表面に直線形状や格子形状の凹部が形成されて、この絶縁層に有機半導体層１４，２４が直接積層されてもよい。 The shape of the concave portion provided in the joint surfaces 14a and 24a may be a linear shape extending in one direction or a lattice shape extending in a direction intersecting with each other. For example, the base of the polymer compound layers 13 and 23 may be provided with a linear or lattice pattern in advance. Alternatively, linear or lattice-shaped recesses may be formed on the surface of the insulating layer, and the organic semiconductor layers 14 and 24 may be directly laminated on the insulating layer.
　・半導体デバイスは、薄膜トランジスタに限らず、有機半導体層１４，２４の接合面１４ａ，２４ａに電極が接合された整流素子であってもよい。要は、凹凸を含む上面を有した絶縁層と、絶縁層の上面に形成され、上面と対向する接合面を有する有機半導体層と、接合面に接合される電極とを備える半導体デバイスであればよい。
［表示装置］
　次に、上述の薄膜トランジスタを備える表示装置について説明する。なお、薄膜トランジスタは、様々な用途に適用可能であって、薄膜トランジスタの適用対象は、特に限定されるものではない。そこで、以下では、例えば、薄膜トランジスタが表示装置の駆動素子に適用された構成について説明するものの、その構成はあくまでも一例であり、適宜の変更が可能である。 The semiconductor device is not limited to a thin film transistor, and may be a rectifying element in which electrodes are bonded to the bonding surfaces 14 a and 24 a of the organic semiconductor layers 14 and 24. The point is that the semiconductor device includes an insulating layer having an upper surface including irregularities, an organic semiconductor layer formed on the upper surface of the insulating layer and having a bonding surface facing the upper surface, and an electrode bonded to the bonding surface. Good.
[Display device]
Next, a display device including the above-described thin film transistor will be described. Note that the thin film transistor can be applied to various uses, and the application target of the thin film transistor is not particularly limited. Therefore, in the following description, for example, a configuration in which a thin film transistor is applied to a driving element of a display device will be described. However, the configuration is merely an example, and appropriate changes can be made.
　図１０に示されるように、有機ＥＬ表示装置５０の備える支持基板５１上には、上述の複数の薄膜トランジスタ１０が、画素を駆動する駆動素子として形成されている。複数の薄膜トランジスタ１０の各々には、薄膜トランジスタ１０を覆う絶縁層５２を通じて画素電極５３が接合されている。各画素電極５３は、絶縁層５２上に所定の間隔を置いて形成された隔壁５４の間に形成されている。複数の画素電極５３の各々には、電子注入層と発光層と正孔輸送層とが含まれる多層構造の有機ＥＬ層５５を介して、共通する対向電極５６が積層されている。そして、画素電極５３と対向電極５６との間における電流の供給態様が、すなわち、画素電極５３と対向電極５６とに挟まれる有機ＥＬ層５５での発光の態様が、薄膜トランジスタ１０の駆動によって制御される。 As shown in FIG. 10, on the support substrate 51 provided in the organic EL display device 50, the plurality of thin film transistors 10 described above are formed as drive elements for driving the pixels. A pixel electrode 53 is bonded to each of the plurality of thin film transistors 10 through an insulating layer 52 covering the thin film transistor 10. Each pixel electrode 53 is formed between partition walls 54 formed on the insulating layer 52 at a predetermined interval. In each of the plurality of pixel electrodes 53, a common counter electrode 56 is laminated via an organic EL layer 55 having a multilayer structure including an electron injection layer, a light emitting layer, and a hole transport layer. The current supply mode between the pixel electrode 53 and the counter electrode 56, that is, the mode of light emission in the organic EL layer 55 sandwiched between the pixel electrode 53 and the counter electrode 56 is controlled by driving the thin film transistor 10. The
　図１１に示されるように、液晶表示装置６０の備える支持基板６１上には、上述の複数の薄膜トランジスタ１０が、画素を駆動する駆動素子として形成されている。複数の薄膜トランジスタ１０の各々には、薄膜トランジスタ１０を覆う絶縁層６２を通じて画素電極６３が接合されている。複数の画素電極６３の上方には、共通する対向電極６４が液晶６５を挟んで積層されている。そして、画素電極６３と対向電極６４との間における電圧の印加態様が、すなわち、画素電極６３と対向電極６４とに挟まれる液晶６５の配向の態様が、薄膜トランジスタ１０の駆動によって制御される。 As shown in FIG. 11, on the support substrate 61 provided in the liquid crystal display device 60, the plurality of thin film transistors 10 described above are formed as drive elements for driving the pixels. A pixel electrode 63 is bonded to each of the plurality of thin film transistors 10 through an insulating layer 62 covering the thin film transistor 10. A common counter electrode 64 is stacked above the plurality of pixel electrodes 63 with the liquid crystal 65 interposed therebetween. The voltage application mode between the pixel electrode 63 and the counter electrode 64, that is, the alignment mode of the liquid crystal 65 sandwiched between the pixel electrode 63 and the counter electrode 64 is controlled by driving the thin film transistor 10.
　図１２に示されるように、電気泳動表示装置７０の備える支持基板７１上には、上述した複数の薄膜トランジスタ１０が、画素を駆動する駆動素子として形成されている。複数の薄膜トランジスタ１０の各々には、薄膜トランジスタ１０を覆う絶縁層７２を通じて画素電極７３が接合されている。複数の画素電極７３を覆う封止層７４には、電気泳動粒子７５が混ぜられた絶縁性の液層７６を挟んで、各画素電極７３に共通する対向電極７７が積層されている。そして、画素電極７３と対向電極７７との間における電圧の印加態様が、すなわち、画素電極７３と対向電極７７との間における電気泳動粒子７５の泳動の態様が、薄膜トランジスタ１０の駆動によって制御される。 As shown in FIG. 12, on the support substrate 71 provided in the electrophoretic display device 70, the plurality of thin film transistors 10 described above are formed as drive elements for driving the pixels. A pixel electrode 73 is bonded to each of the plurality of thin film transistors 10 through an insulating layer 72 covering the thin film transistor 10. On the sealing layer 74 covering the plurality of pixel electrodes 73, a counter electrode 77 common to each pixel electrode 73 is laminated with an insulating liquid layer 76 mixed with electrophoretic particles 75 interposed therebetween. The voltage application mode between the pixel electrode 73 and the counter electrode 77, that is, the mode of migration of the electrophoretic particles 75 between the pixel electrode 73 and the counter electrode 77 is controlled by driving the thin film transistor 10. .
　［電子機器］
　次に、上述の表示装置を備える電子機器について説明する。なお、表示装置は、さまざまな用途に適用可能であって、特に限定されるものではない。そこで、以下では、例えば、表示装置が表示部を備える電子機器に適用された構成について説明するものの、その構成はあくまでも一例であり、適宜の変更が可能である。 [Electronics]
Next, an electronic device including the above display device will be described. Note that the display device is applicable to various uses and is not particularly limited. Therefore, in the following description, for example, a configuration in which the display device is applied to an electronic device including a display unit will be described. However, the configuration is merely an example, and appropriate changes can be made.
　図１３に示されるように、電子書籍端末１００の筐体１０１には、上述の表示装置を含む表示部１０２と、表示部１０２における表示の態様を操作する操作ボタン１０３とが搭載されている。 As shown in FIG. 13, the housing 101 of the electronic book terminal 100 is equipped with a display unit 102 including the above-described display device and an operation button 103 for operating a display mode on the display unit 102.
　図１４に示されるように、パーソナルコンピューター１１０の下側筐体１１１には、キーボード１１２と操作部１１３とが搭載され、パーソナルコンピューター１１０の上側筐体１１４には、上述の表示装置を含む表示部１１５が搭載されている。 As shown in FIG. 14, a keyboard 112 and an operation unit 113 are mounted on the lower casing 111 of the personal computer 110, and a display section including the above-described display device is mounted on the upper casing 114 of the personal computer 110. 115 is installed.
　図１５に示されるように、テレビジョン１２０の支持台１２１に取り付けられた筐体１２２には、上述の表示装置を含む表示部１２３が搭載されている。
　図１６に示されるように、デジタルスチルカメラ１３０の筐体１３１の１つの面側には、撮像対象を写すレンズ１３２と、デジタルスチルカメラ１３０に撮像させるための撮像ボタン１３３とが形成されている。また、図１７に示されるように、筐体１３１の他の面側には、上述の表示装置を含む表示部１３４と、操作ボタン１３５とが搭載されている。 As shown in FIG. 15, a display unit 123 including the above-described display device is mounted on a housing 122 attached to a support base 121 of a television 120.
As shown in FIG. 16, on one surface side of the casing 131 of the digital still camera 130, a lens 132 that captures an imaging target and an imaging button 133 for causing the digital still camera 130 to capture an image are formed. . As shown in FIG. 17, a display unit 134 including the above-described display device and operation buttons 135 are mounted on the other surface side of the housing 131.
　図１８に示されるように、デジタルビデオカメラ１４０の筐体１４１には、レンズ１４２と、操作ボタン１４３とが搭載されている。また、筐体１４１には、連結部１４４を介して表示部用筐体１４５が連結され、表示部用筐体１４５には、上述の表示装置を含む表示部１４６が搭載されている。 As shown in FIG. 18, a lens 142 and operation buttons 143 are mounted on the housing 141 of the digital video camera 140. In addition, a display unit housing 145 is connected to the housing 141 via a connecting unit 144, and the display unit 145 including the above-described display device is mounted on the display unit housing 145.
　図１９に示されるように、携帯電話端末１５０の備える下側筐体１５１には、操作ボタン１５２が搭載され、また、下側筐体１５１には、連結部１５３を介して上側筐体１５４が連結されている。上側筐体１５４には、上述の表示装置を含む表示部１５５が搭載されている。また、図２０に示されるように、上側筐体１５４における表示部１５５とは対向する面には、上述の表示装置を含む裏面表示部１５６が搭載されている。 As shown in FIG. 19, an operation button 152 is mounted on the lower casing 151 included in the mobile phone terminal 150, and the upper casing 154 is connected to the lower casing 151 via a connecting portion 153. It is connected. A display portion 155 including the above display device is mounted on the upper housing 154. Further, as shown in FIG. 20, a back surface display unit 156 including the above-described display device is mounted on a surface of the upper housing 154 facing the display unit 155.
　本開示の薄膜トランジスタは、以下のような構成とすることもできる。
　（１）絶縁層と、前記絶縁層上に形成された有機半導体層と、前記有機半導体層の上面である接合面に接合される電極とを備え、前記接合面は凹凸を有する半導体デバイス。 The thin film transistor of the present disclosure may be configured as follows.
(1) A semiconductor device comprising an insulating layer, an organic semiconductor layer formed on the insulating layer, and an electrode bonded to a bonding surface which is an upper surface of the organic semiconductor layer, and the bonding surface has irregularities.
　（２）前記接合面の凹凸が、複数のうねる曲線状を含む前記（１）に記載の半導体デバイス。
　（３）前記接合面の凹凸が、複数の湾曲部分を含む不規則な形状を含む前記（１）又は（２）に記載の半導体デバイス。 (2) The semiconductor device according to (1), wherein the unevenness of the joint surface includes a plurality of wavy curved shapes.
(3) The semiconductor device according to (1) or (2), wherein the unevenness of the joint surface includes an irregular shape including a plurality of curved portions.
　（４）前記接合面の凹凸における段差は、１ｎｍ以上１００ｎｍ以下であり、前記接合面における前記段差の間隔は、１μｍ以上１０μｍ以下である前記（１）～（３）のいずれか１つに記載の半導体デバイス。 (4) The step in the unevenness of the joint surface is 1 nm or more and 100 nm or less, and the interval of the step in the joint surface is 1 μm or more and 10 μm or less. Semiconductor devices.
　（５）前記絶縁層は高分子化合物層である前記（１）～（４）のいずれか１つに記載の半導体デバイス。
　（６）前記有機半導体層が、低分子化合物を含む層であり、前記絶縁層が、高分子化合物を含む層であり、前記有機半導体層を構成する低分子化合物と前記絶縁層を構成する高分子化合物とが相溶性を有する前記（１）～（５）のいずれか１つに記載の半導体デバイス。 (5) The semiconductor device according to any one of (1) to (4), wherein the insulating layer is a polymer compound layer.
(6) The organic semiconductor layer is a layer containing a low molecular compound, the insulating layer is a layer containing a polymer compound, and the low molecular compound constituting the organic semiconductor layer and the insulating layer are high. The semiconductor device according to any one of (1) to (5), wherein the molecular compound is compatible with the molecular compound.
　（７）前記絶縁層は、前記有機半導体層の形成される面に凹凸を有し、前記接合面の凹凸は、前記絶縁層の凹凸に倣う前記（１）～（６）のいずれか１つに記載の半導体デバイス。 (7) The insulating layer has irregularities on the surface on which the organic semiconductor layer is formed, and the irregularities on the bonding surface follow any one of the irregularities of the insulating layer. A semiconductor device according to 1.
　（８）前記電極が、薄膜トランジスタのソース電極とドレイン電極とである前記（１）～（７）のいずれか１つに記載の半導体デバイス。
　（９）前記絶縁層下に形成されたゲート電極をさらに備え、前記電極が、前記有機半導体層上に形成されたソース電極と、前記有機半導体層上に形成されたドレイン電極とを備える前記（１）～（８）のいずれか１つに記載の半導体デバイス。 (8) The semiconductor device according to any one of (1) to (7), wherein the electrodes are a source electrode and a drain electrode of a thin film transistor.
(9) The method further includes a gate electrode formed under the insulating layer, wherein the electrode includes a source electrode formed on the organic semiconductor layer and a drain electrode formed on the organic semiconductor layer. 1) The semiconductor device according to any one of (8).
　（１０）前記絶縁層が、第１絶縁層であり、前記半導体デバイスは、前記第１絶縁層下に形成された第２絶縁層をさらに備え、前記第１絶縁層と前記第２絶縁層とが、高分子化合物を含む層であり、前記第１絶縁層を構成する高分子化合物と前記第２絶縁層を構成する高分子化合物とが相溶しない前記（１）～（９）のいずれか１つに記載の半導体デバイス。 (10) The insulating layer is a first insulating layer, and the semiconductor device further includes a second insulating layer formed under the first insulating layer, the first insulating layer, the second insulating layer, Is a layer containing a polymer compound, and the polymer compound constituting the first insulating layer and the polymer compound constituting the second insulating layer are not compatible with each other. The semiconductor device according to one.
　（１１）前記有機半導体層上に形成されたゲート絶縁層と、前記ゲート絶縁層上に形成されたゲート電極とをさらに備え、前記電極が、前記有機半導体層上に形成されたソース電極と、前記有機半導体層上に形成されたドレイン電極とを備える前記（１）～（１０）のいずれか１つに記載の半導体デバイス。 (11) a gate insulating layer formed on the organic semiconductor layer; and a gate electrode formed on the gate insulating layer, wherein the electrode is a source electrode formed on the organic semiconductor layer; The semiconductor device according to any one of (1) to (10), further comprising a drain electrode formed on the organic semiconductor layer.
　本出願は、日本国特許庁において２０１２年５月１６日に出願された日本特許出願番号２０１２－１１２８５２号を基礎として優先権を主張するものであり、この出願のすべての内容を参照によって本出願に援用する。 This application claims priority on the basis of Japanese Patent Application No. 2012-112852 filed on May 16, 2012 at the Japan Patent Office. The entire contents of this application are hereby incorporated by reference. Incorporated into.
　当業者であれば、設計上の要件や他の要因に応じて、種々の修正、コンビネーション、サブコンビネーション、および変更を想到し得るが、それらは添付の請求の範囲やその均等物の範囲に含まれるものであることが理解される。 Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (14)

  1. 　絶縁層と、
    　前記絶縁層上に形成された有機半導体層と、
    　前記有機半導体層の上面である接合面に接合される電極とを備え、
    　前記接合面は凹凸を有する
    　半導体デバイス。     An insulating layer;
    An organic semiconductor layer formed on the insulating layer;
    An electrode bonded to a bonding surface which is an upper surface of the organic semiconductor layer,
    The bonding surface has irregularities. Semiconductor device.
  2. 　前記接合面の凹凸が、複数のうねる曲線状を含む
    　請求項１に記載の半導体デバイス。     The semiconductor device according to claim 1, wherein the unevenness of the joint surface includes a plurality of wavy curved shapes.
  3. 　前記接合面の凹凸が、複数の湾曲部分を含む不規則な形状を含む
    　請求項１に記載の半導体デバイス。     The semiconductor device according to claim 1, wherein the unevenness of the joint surface includes an irregular shape including a plurality of curved portions.
  4. 　前記接合面の凹凸における段差は、１ｎｍ以上１００ｎｍ以下であり、
    　前記接合面における前記段差の間隔は、１μｍ以上１０μｍ以下である
    　請求項１に記載の半導体デバイス。     The step in the unevenness of the joint surface is 1 nm or more and 100 nm or less,
    The semiconductor device according to claim 1, wherein an interval between the steps on the bonding surface is 1 μm or more and 10 μm or less.
  5. 　前記絶縁層は高分子化合物層である
    　請求項１に記載の半導体デバイス。     The semiconductor device according to claim 1, wherein the insulating layer is a polymer compound layer.
  6. 　前記有機半導体層が、低分子化合物を含む層であり、
    　前記絶縁層が、高分子化合物を含む層であり、
    　前記有機半導体層を構成する低分子化合物と前記絶縁層を構成する高分子化合物とが相溶性を有する
    　請求項１に記載の半導体デバイス。     The organic semiconductor layer is a layer containing a low molecular compound,
    The insulating layer is a layer containing a polymer compound;
    The semiconductor device according to claim 1, wherein the low-molecular compound constituting the organic semiconductor layer and the polymer compound constituting the insulating layer have compatibility.
  7. 　前記絶縁層は、前記有機半導体層の形成される面に凹凸を有し、
    　前記接合面の凹凸は、前記絶縁層の凹凸に倣う
    　請求項１に記載の半導体デバイス。     The insulating layer has irregularities on the surface on which the organic semiconductor layer is formed,
    The semiconductor device according to claim 1, wherein the unevenness of the bonding surface follows the unevenness of the insulating layer.
  8. 　前記電極が、
    　薄膜トランジスタのソース電極とドレイン電極とである
    　請求項１に記載の半導体デバイス。     The electrode is
    The semiconductor device according to claim 1, wherein the semiconductor device is a source electrode and a drain electrode of the thin film transistor.
  9. 　前記絶縁層下に形成されたゲート電極をさらに備え、
    　前記電極が、
    　前記有機半導体層上に形成されたソース電極と、
    　前記有機半導体層上に形成されたドレイン電極とを備える
    　請求項１に記載の半導体デバイス。     A gate electrode formed under the insulating layer;
    The electrode is
    A source electrode formed on the organic semiconductor layer;
    The semiconductor device according to claim 1, further comprising a drain electrode formed on the organic semiconductor layer.
  10. 　前記絶縁層が、第１絶縁層であり、
    　前記半導体デバイスは、前記第１絶縁層下に形成された第２絶縁層をさらに備え、
    　前記第１絶縁層と前記第２絶縁層とが、高分子化合物を含む層であり、
    　前記第１絶縁層を構成する高分子化合物と前記第２絶縁層を構成する高分子化合物とが相溶しない
    　請求項１に記載の半導体デバイス。     The insulating layer is a first insulating layer;
    The semiconductor device further includes a second insulating layer formed under the first insulating layer,
    The first insulating layer and the second insulating layer are layers containing a polymer compound,
    The semiconductor device according to claim 1, wherein the polymer compound constituting the first insulating layer and the polymer compound constituting the second insulating layer are not compatible.
  11. 　前記有機半導体層上に形成されたゲート絶縁層と、
    　前記ゲート絶縁層上に形成されたゲート電極とをさらに備え、
    　前記電極が、
    　前記有機半導体層上に形成されたソース電極と、
    　前記有機半導体層上に形成されたドレイン電極とを備える
    　請求項１に記載の半導体デバイス。     A gate insulating layer formed on the organic semiconductor layer;
    A gate electrode formed on the gate insulating layer,
    The electrode is
    A source electrode formed on the organic semiconductor layer;
    The semiconductor device according to claim 1, further comprising a drain electrode formed on the organic semiconductor layer.
  12. 　薄膜トランジスタを備え、
    　前記薄膜トランジスタが、
    　絶縁層と、
    　前記絶縁層上に形成された有機半導体層と、
    　前記有機半導体層の上面である接合面に接合される電極とを備え、
    　前記接合面は凹凸を有する
    　表示装置。     A thin film transistor,
    The thin film transistor is
    An insulating layer;
    An organic semiconductor layer formed on the insulating layer;
    An electrode bonded to a bonding surface which is an upper surface of the organic semiconductor layer,
    The bonding surface has irregularities.
  13. 　表示部を備え、
    　前記表示部が、薄膜トランジスタを備え、
    　前記薄膜トランジスタが、
    　絶縁層と、
    　前記絶縁層上に形成された有機半導体層と、
    　前記有機半導体層の上面である接合面に接合される電極とを備え、
    　前記接合面は凹凸を有する
    　電子機器。     With a display,
    The display unit includes a thin film transistor,
    The thin film transistor is
    An insulating layer;
    An organic semiconductor layer formed on the insulating layer;
    An electrode bonded to a bonding surface which is an upper surface of the organic semiconductor layer,
    The joint surface has an uneven surface.
  14. 　液膜を相分離させることによって、絶縁層上に有機半導体層を形成することと、
    　前記有機半導体層の上面である接合面に電極を形成することとを備え、
    　前記有機半導体層を形成することでは、前記接合面に凹凸を有する有機半導体層が形成される
    　半導体デバイスの製造方法。     Forming an organic semiconductor layer on the insulating layer by phase-separating the liquid film;
    Forming an electrode on a bonding surface that is an upper surface of the organic semiconductor layer,
    By forming the organic semiconductor layer, an organic semiconductor layer having irregularities on the bonding surface is formed. A method for manufacturing a semiconductor device.
PCT/JP2013/061364 2012-05-16 2013-04-17 Semiconductor device, display apparatus, electronic apparatus, and semiconductor device manufacturing method WO2013172143A1 (en)

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