WO2013161570A1 - Field effect transistor and method for manufacturing same, display device, image sensor, and x-ray sensor - Google Patents

Field effect transistor and method for manufacturing same, display device, image sensor, and x-ray sensor Download PDF

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WO2013161570A1
WO2013161570A1 PCT/JP2013/060865 JP2013060865W WO2013161570A1 WO 2013161570 A1 WO2013161570 A1 WO 2013161570A1 JP 2013060865 W JP2013060865 W JP 2013060865W WO 2013161570 A1 WO2013161570 A1 WO 2013161570A1
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region
film
field effect
effect transistor
tft
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PCT/JP2013/060865
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French (fr)
Japanese (ja)
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雅司 小野
真宏 高田
田中　淳
鈴木　真之
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富士フイルム株式会社
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to a field effect transistor, a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor.
  • InGaZnO oxide semiconductor thin film As an oxide semiconductor layer (channel layer), particularly a thin film transistor (Thin Film Transistor: TFT).
  • TFT Thi Film Transistor
  • An oxide semiconductor thin film can be formed at a low temperature, exhibits higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible TFT should be formed on a substrate such as a plastic plate or film. Is possible (eg CS Chuang et al., SID 08 DIGEST, P-13).
  • Japanese Patent Laying-Open No. 2010-21555 includes a first region containing ITO (In, Sn, and O) on the side close to the gate electrode.
  • ITO In, Sn, and O
  • a TFT using an oxide semiconductor layer having a two-layer structure in which a second region containing InGaZnO is disposed on a side far from the gate electrode is disclosed.
  • a first region containing an In—Zn—O-based (hereinafter referred to as InZnO) oxide semiconductor is disposed on the side close to the gate electrode, and the side far from the gate electrode is disclosed.
  • Japanese Laid-Open Patent Publication No. 2006-165529 discloses a TFT in which an amorphous oxide including an In—Sn—Zn—O-based (hereinafter referred to as InSnZnO) oxide semiconductor is used for an oxide semiconductor layer. Yes.
  • a blue light emitting layer used for an organic EL (Electro Luminescence) including TFT and a liquid crystal shows broad light emission having a peak of about 450 nm, but the tail of the emission spectrum of blue light of the organic EL element continues to a wavelength of 420 nm.
  • the blue color filter allows light having a wavelength of 400 nm to pass through about 70%, it is required that the characteristic deterioration with respect to light irradiation in a wavelength region smaller than the wavelength 450 nm is low. If the optical band gap of the InGaZnO film is relatively narrow and the region has optical absorption, there arises a problem that a threshold shift of the transistor occurs.
  • CS Chuang et al., SID 08 DIGEST, P-13 evaluates the deterioration of characteristics of a TFT using conventional InGaZnO as an oxide semiconductor layer against light irradiation.
  • of the threshold shift amount with respect to irradiation exceeds 1V.
  • the first region as the current path layer contains ITO, and a high mobility TFT can be realized, but the light irradiation characteristic is not mentioned.
  • the mobility of the first region as the current path layer containing InZnO is lower than 10 cmA 2 / Vs, and the light irradiation characteristics are not mentioned.
  • InZnO a combination in which Sn is included in the first region at a level equal to or higher than inevitable impurities is described, but the TFT, mobility, and light irradiation characteristics according to the example are not mentioned.
  • the present invention has been made in view of the above circumstances, and has a high mobility exceeding 20 cm 2 / Vs and a high light stability in which the absolute value
  • ⁇ 2> The field effect transistor according to ⁇ 1>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 0.200.
  • ⁇ 3> The field effect transistor according to ⁇ 1> or ⁇ 2>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 0.700.
  • ⁇ 4> The field effect transistor according to any one of ⁇ 1> to ⁇ 3>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 1/3.
  • ⁇ 5> The field effect transistor according to any one of ⁇ 1> to ⁇ 4>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 0.400.
  • ⁇ 6> The field effect transistor according to any one of ⁇ 1> to ⁇ 5>, wherein the composition of the first region is represented by a / (a + b + c) ⁇ 1/3.
  • ⁇ 7> The field effect transistor according to any one of ⁇ 1> to ⁇ 6>, wherein the film thickness of the first region is 50 nm or less.
  • ⁇ 8> The field effect transistor according to ⁇ 7>, wherein the film thickness of the first region is 16 nm or less.
  • ⁇ 9> The field effect transistor according to any one of ⁇ 1> to ⁇ 8>, wherein the film thickness of the first region is 5 nm or more.
  • ⁇ 10> The field effect transistor according to any one of ⁇ 1> to ⁇ 9>, wherein the composition of the second region is represented by f / (e + f) ⁇ 0.875.
  • ⁇ 11> The field effect transistor according to any one of ⁇ 1> to ⁇ 10>, wherein the composition of the second region is represented by f / (e + f)> 0.250.
  • ⁇ 12> The field effect transistor according to any one of ⁇ 1> to ⁇ 11>, wherein the film thickness of the second region is more than 10 nm and less than 70 nm.
  • ⁇ 13> The field effect transistor according to any one of ⁇ 1> to ⁇ 12>, wherein the oxide semiconductor layer is an amorphous film.
  • ⁇ 14> The field effect transistor according to any one of ⁇ 1> to ⁇ 13>, wherein the second region has lower electrical conductivity than the first region.
  • a method of manufacturing a field effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, wherein the oxide semiconductor layer is formed as a step of In (A) Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0, a + b + c 1)
  • a display device comprising the field-effect transistor according to any one of ⁇ 1> to ⁇ 14>.
  • An image sensor comprising the field-effect transistor according to any one of ⁇ 1> to ⁇ 14>.
  • An X-ray sensor comprising the field effect transistor according to any one of ⁇ 1> to ⁇ 14>.
  • a field effect that achieves both high mobility exceeding 20 cm 2 / Vs and high light stability in which the absolute value
  • of the threshold shift amount is 1 V or less with respect to light irradiation with a wavelength of 420 nm.
  • Type transistor, manufacturing method thereof, display device, image sensor, and X-ray sensor can be provided.
  • FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1B is a schematic diagram showing an example of a bottom contact type TFT with a top gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1C is a schematic diagram showing an example of a top contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1D is a schematic diagram showing an example of a bottom contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1B is a schematic diagram showing an example of a bottom contact type TFT with a top gate structure, which is a TFT according
  • FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the invention.
  • FIG. 3 is a schematic configuration diagram of electrical wiring of the liquid crystal display device shown in FIG.
  • FIG. 4 is a schematic sectional view of a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the invention.
  • FIG. 5 is a schematic configuration diagram of the electrical wiring of the electro-optical device shown in FIG.
  • FIG. 6 is a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention.
  • FIG. 7 is a schematic configuration diagram of electrical wiring of the sensor shown in FIG. FIG.
  • FIG. 8A is a plan view of the TFTs of the example and the comparative example
  • FIG. 8B is a cross-sectional view of the TFT shown in FIG.
  • FIG. 9 is a diagram showing a ternary phase diagram focusing on the composition of the first region in Examples 1 to 10 and Comparative Examples 2 to 4.
  • FIG. 10 is a diagram showing representative Vg-Id characteristics among the measurement results of transistor characteristics (Vg-Id characteristics) for the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 6.
  • FIG. 11 is a diagram illustrating the IV characteristics when the TFT according to Example 3 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light.
  • FIG. 10 is a diagram showing representative Vg-Id characteristics among the measurement results of transistor characteristics (Vg-Id characteristics) for the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 6.
  • FIG. 11 is a diagram illustrating the IV characteristics when the TFT according to Example
  • FIG. 12 is a diagram illustrating the IV characteristics when the TFT according to Example 5 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light.
  • FIG. 13 is a diagram illustrating the IV characteristics when the TFT according to Example 6 is irradiated with monochrome light, together with the IV characteristics before monochrome light irradiation.
  • FIG. 14 is a diagram illustrating the IV characteristics when the TFT according to Example 7 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light.
  • FIG. 18 is a graph in which the relationship between the mobility and the In ratio ⁇ a / (a + b + c) ⁇ with respect to the total composition ratio of In, Sn, and Zn in the first region is plotted based on Table 3.
  • FIG. 19 is a graph plotting the relationship between the threshold shift amount ⁇ Vth and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3.
  • FIG. 20 is a diagram showing the composition dependence of the carrier concentration in the InSnZnO single film.
  • a field effect transistor according to an embodiment of the present invention will be specifically described by taking a TFT as an example.
  • a TFT according to an embodiment of the present invention includes a gate electrode, a gate insulating film, an oxide semiconductor layer (active layer), a source electrode, and a drain electrode, and applies a voltage to the gate electrode to flow through the oxide semiconductor layer. It is an active element having a function of controlling current and switching current between a source electrode and a drain electrode.
  • the oxide semiconductor layer further includes a first region in the film thickness direction and a second region disposed on the side farther from the gate electrode than the first region. I have.
  • no layer other than the oxide semiconductor layer such as an electrode layer is inserted between the first region and the second region.
  • the TFT may be formed on the substrate, or when a component (for example, an electrode) of the TFT functions as the substrate, a separate substrate may be omitted. Further, the TFT and the substrate may be in direct contact, or an additional layer or element may be provided between the TFT and the substrate.
  • the element structure of the TFT may be any of a so-called reverse stagger structure (also referred to as a bottom gate structure (type)) and a stagger structure (also referred to as a top gate structure (type)) based on the position of the gate electrode. Good. Further, based on a contact portion between the oxide semiconductor layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be employed. Note that the top gate structure is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an oxide semiconductor layer is formed on the lower side of the gate insulating film.
  • the gate electrode is disposed on the side, and the oxide semiconductor layer is formed on the upper side of the gate insulating film.
  • the bottom contact type is a form in which the source / drain electrodes are formed before the oxide semiconductor layer and the lower surface of the oxide semiconductor layer is in contact with the source / drain electrodes.
  • the top contact type is an oxide In this embodiment, the semiconductor layer is formed before the source / drain electrodes, and the upper surface of the oxide semiconductor layer is in contact with the source / drain electrodes.
  • FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • the second region 14 ⁇ / b> B of the oxide semiconductor layer 14 and the first region 14 ⁇ / b> A of the oxide semiconductor layer 14 are sequentially stacked on one surface in the thickness direction of the substrate 12.
  • the source electrode 18 and the drain electrode 20 are spaced apart from each other on the first region 14A (surface), and the gate insulating film 22 and the gate electrode 24 are sequentially stacked on these (surface). ing.
  • FIG. 1B is a schematic view showing an example of a bottom contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • the source electrode 18 and the drain electrode 20 are provided on one surface in the thickness direction of the substrate 12 so as to be separated from each other. Then, the second region 14B of the oxide semiconductor layer 14, the first region 14A of the oxide semiconductor layer 14, the gate insulating film 22, and the gate electrode 24 are sequentially stacked.
  • FIG. 1C is a schematic diagram showing an example of a top contact type TFT having a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • the gate electrode 24, the gate insulating film 22, the first region 14 ⁇ / b> A of the oxide semiconductor layer 14, and the second region of the oxide semiconductor layer 14 are formed on one surface in the thickness direction of the substrate 12.
  • the regions 14B are sequentially stacked.
  • the source electrode 18 and the drain electrode 20 are spaced from each other on the second region 14B (surface).
  • FIG. 1D is a schematic view showing an example of a bottom contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • the gate electrode 24 and the gate insulating film 22 are sequentially stacked on one surface of the substrate 12 in the thickness direction.
  • the source electrode 18 and the drain electrode 20 are disposed on the surface of the gate insulating film 22 so as to be separated from each other, and further on the (surface) thereof, the first region 14A of the oxide semiconductor layer 14 and the oxide semiconductor
  • the second region 14B of the layer 14 is sequentially stacked.
  • the TFT according to this embodiment can have various configurations other than the above, and may have a configuration including a protective layer over an oxide semiconductor layer, an insulating layer over a substrate, and the like as appropriate. Good.
  • top contact type TFT 40 having a bottom gate structure shown in FIG. 1C is specifically described as a representative example, but the following materials, thicknesses, and the like can be similarly applied to other types of TFTs. .
  • the shape, structure, size, etc. of the substrate 12 for forming the TFT 40 are not particularly limited and can be appropriately selected depending on the purpose.
  • the structure of the substrate 12 may be a single layer structure or a laminated structure.
  • an inorganic material such as glass or YSZ (yttrium stabilized zirconium), a resin such as polyethylene terephthalate or polyethylene naphthalate, or a resin such as a composite plastic material with clay mineral or particles having a mica-derived crystal structure
  • a substrate formed of a composite material or the like can be used.
  • a substrate formed of a resin or a resin composite material is preferable from the viewpoint of light weight and flexibility.
  • the resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion to the lower electrode, and the like.
  • the gate electrode 24 is not particularly limited as long as it has high conductivity.
  • a metal such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, zinc oxide, indium oxide,
  • a metal oxide conductive film such as indium tin oxide (ITO) or zinc indium oxide (InZnO) can be used as a single layer or a stacked structure of two or more layers.
  • the gate insulating film 22 is preferably one having high insulation properties, for example, an insulating film such as SiO 2 , SiNx, SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , HfO 2 , or a compound thereof. Can be made of an insulating film or the like containing at least two.
  • the first region 14A including the first region 14A and the first region 14A farther from the gate electrode 24 than the first region 14A.
  • In (e) Ga (f) Zn (g) O (h) (e ) > 0, f> 0, g> 0, h> 0, e + f + g 1, and may be abbreviated as InGaZnO film hereinafter).
  • the second region 14B is disposed on the side far from the gate electrode 24, and preferably has lower electrical conductivity than the first region 14A.
  • the carriers are electrons
  • the carrier concentration indicates the electron carrier concentration
  • the carrier mobility indicates the electron mobility.
  • the carriers are holes
  • the carrier concentration indicates the hole carrier concentration
  • the carrier mobility indicates the hole mobility.
  • the carrier concentration and carrier mobility of the substance can be obtained by Hall measurement.
  • the electric conductivity can be obtained by measuring the specific resistance of the film whose thickness is known, thereby obtaining the electric conductivity of the film.
  • composition of the first region 14A and the second region 14B is recognized by using, for example, fluorescent X-ray analysis or ICP emission analysis as a single film, and secondary ion mass spectrometry (SIMS) as a laminated film, for example. I can do it.
  • fluorescent X-ray analysis or ICP emission analysis as a single film
  • SIMS secondary ion mass spectrometry
  • the TFT 40 of the present embodiment having the above oxide semiconductor layer 14 has a high mobility exceeding 20 cm 2 / Vs and a high threshold shift amount absolute value
  • the second region 14B is a so-called “resistance layer”.
  • the first region 14A is an InSnZnO film in the TFT of this embodiment, both high light stability can be achieved as compared with the case where an InGaZnO film is used as the first region 14A, for example.
  • the composition in the vicinity of In: Sn: Zn 1.000: 1.000: 1.000 which does not require extreme compositional modulation as compared with the InGaZnO film. It is also possible to achieve higher mobility. In an InGaZnO film, it was difficult to achieve high mobility only in a composition region having an extremely high In content.
  • a high mobility and high switching performance e.g. On / Off ratio is more than 10 6
  • the TFT was constituted of only one layer of the oxide semiconductor layer 14 InSnZnO film. This is because the carrier concentration of the InSnZnO film is relatively high, so that pinch-off is difficult only with the InSnZnO film.
  • high mobility and high switching performance are realized by using a stacked structure of the first region 14A and the second region 14B.
  • the oxide semiconductor layer 14 has a two-layer structure of the first region 14A and the second region 14B, the first region 14A is an InSnZnO film, and the second region 14B is an InGaZnO film. Yes.
  • the oxide semiconductor layer 14 may be either an amorphous film or a crystalline film. However, in the case of an amorphous film, since it can be formed at a low temperature, it is preferably formed on the flexible substrate 12. In the case of an amorphous film, a crystal grain boundary does not exist and a highly uniform film can be obtained. Note that whether or not the oxide semiconductor layer 14 is an amorphous film can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer 14 can be determined to be an amorphous film.
  • the film thickness (total film thickness) including the first region 14A and the second region 14B in the oxide semiconductor layer 14 is not particularly limited, but the film uniformity and the total carriers in the oxide semiconductor layer 14 are not limited. From the viewpoint of controlling the concentration, it is preferably 10 nm or more and 200 nm or less.
  • the first region 14A of the oxide semiconductor layer 14 preferably includes In, Sn, Zn, and O as main constituent elements.
  • the “main constituent element” means that the total ratio of In, Sn, Zn, and O with respect to all the constituent elements in the first region 14A is 98% or more. Therefore, the first region 14A may also contain other elements such as Mg as described later.
  • the first region 14A contains In (a) Sn (b) Zn (c) O (d) , and the composition of the first region 14A is c / (a + b + c) ⁇ 0.200. It is preferable to be represented by This is because the threshold voltage (Vth) of the TFT 40 can be suppressed from appearing significantly on the negative side. Note that the above composition does not consider other elements other than In, Sn, Zn, and O described above, but does not indicate that the first region 14A does not contain other elements. The same applies to the subsequent compositional expressions.
  • the composition of the first region 14A is more preferably represented by c / (a + b + c) ⁇ 1/3.
  • the threshold voltage of the TFT 40 can be made higher on the plus side than 0V. It is even more preferable that the composition of the first region 14A is represented by c / (a + b + c) ⁇ 0.400. This is because when c / (a + b + c) ⁇ 0.400, the threshold voltage is almost saturated, so that fluctuation of the threshold voltage with respect to the Zn composition ratio can be suppressed.
  • the composition of the first region 14A is preferably represented by c / (a + b + c) ⁇ 0.700. This is because the mobility of the TFT 40 can be more than 30 cm 2 / Vs. Furthermore, the composition of the first region 14A is more preferably 0.200 ⁇ c / (a + b + c) ⁇ 0.700. This is because the absolute value
  • the composition of the first region 14A is expressed by a / (a + b + c) ⁇ 1/3 by changing the viewpoint to the composition ratio of In. This is because the mobility of the TFT 40 can be more than 40 cm 2 / Vs.
  • the film thickness of the first region 14A is preferably 50 nm or less. This is because it is possible to suppress the threshold voltage of the TFT 40 from appearing on the minus side and to suppress the deterioration of the S value.
  • the film thickness of the first region 14A is preferably 5 nm or more. This is because the flatness of the film can be improved.
  • the film thickness of the first region 14A is preferably 16 nm or less from the following fully depleted theoretical formulas (1) to (3).
  • Table 1 shows the meanings of symbols in each theoretical formula. The parameters in Table 1 are as follows. ) ”) Is used.
  • the film thickness of 16 nm or less satisfies the condition of complete depletion. Therefore, it can be seen from the above theoretical formula that the film thickness of the first region 14A is preferably 16 nm or less in order to realize good switching characteristics and low off-state current.
  • the electric conductivity of the first region 14A is preferably 10 ⁇ 6 Scm ⁇ 1 or more and less than 10 2 Scm ⁇ 1 . More preferably, it is 10 ⁇ 4 Scm ⁇ 1 or more and less than 10 2 Scm ⁇ 1 , and further preferably 10 ⁇ 1 Scm ⁇ 1 or more and less than 10 2 Scm ⁇ 1 .
  • the second region 14B of the oxide semiconductor layer 14 contains In (e) Ga (f) Zn (g) O (h) as described above, but In, Ga, Zn, and O Is the main constituent element.
  • the “main constituent element” means that the total ratio of In, Ga, Zn, and O with respect to all the constituent elements in the second region 14B is 98% or more. Accordingly, the second region 14B may also contain other elements such as Mg as described later.
  • the composition of the second region 14B is preferably represented by f / (e + f) ⁇ 0.875. This is because high mobility is easily achieved when the composition of the second region 14B is a composition range represented by f / (e + f) ⁇ 0.875.
  • the composition of the second region 14B is e / (e + f)> 0.875, the resistance value of the second region 14B becomes relatively high, so that it is difficult to secure an ohmic contact, and high movement is caused. Getting a degree is likely to be difficult.
  • the composition of the second region 14B is preferably represented by f / (e + f)> 0.250.
  • the composition of the second region 14B is f / (e + f) ⁇ 0.250, the carrier concentration of the second region 14B is relatively high, and the second region 14B is changed to the first region 14A. Since the effect of carrier inflow increases, the hump effect may occur in the Vg-Id characteristic, or the threshold voltage may be greatly negative. Therefore, the composition of the second region 14B is preferably represented by f / (e + f)> 0.250.
  • the film thickness of the second region 14B is preferably more than 10 nm and less than 70 nm. This is because when the film thickness of the second region 14B is more than 10 nm, reduction of off-current and suppression of deterioration of the S value can be expected. Further, when the film thickness of the second region 14B is less than 70 nm, an increase in resistance between the source / drain electrodes 18 and 20 and the first region 14A is suppressed, and consequently a decrease in mobility is suppressed. Because it can be done.
  • the electric conductivity of the second region 14B can take the same range as that of the first region 14A, but is preferably lower than the first region 14A by 10 ⁇ 7 Scm ⁇ 1 or more and 10 1 Scm ⁇ 1. Is less than. More preferably, it is 10 ⁇ 7 Scm ⁇ 1 or more and less than 10 ⁇ 1 Scm ⁇ 1 .
  • the carrier concentration of the oxide semiconductor layer in other words, the electric conductivity can be controlled not only by the composition modulation of the first region 14A and the second region 14B, but also by the oxygen partial pressure control at the time of film formation. .
  • the oxygen concentration can be controlled by controlling the oxygen partial pressure during film formation in the first region 14A and the second region 14B, respectively. If the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly. On the other hand, if the oxygen partial pressure during film formation is lowered, the carrier concentration can be increased, and an increase in field effect mobility can be expected accordingly. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after forming the first region 14A, the oxidation of the film can be promoted and the amount of oxygen vacancies in the first region can be reduced.
  • the band gap of the film can be increased by doping Mg.
  • the band profile of the laminated film is compared with a system in which the composition ratio of only In, Sn (or Ga), and Zn is controlled by doping Mg in each of the first region 14A and the second region 14B.
  • the band gap can be increased while maintaining In this case, since the first region 14A is an InSnZnO film, the band gap is relatively narrower than that of the InGaZnO film in the second region 14B. Therefore, the Mg in the first region 14A than in the second region 14B. It is considered that doping with a larger amount of can expand the band gap contributing to the light irradiation stability more efficiently.
  • the blue light emitting layer used in the organic EL exhibits broad light emission having a peak at a wavelength of about 450 nm
  • the optical band gaps of the first region 14A and the second region 14B are relatively narrow, and optical absorption occurs in that region.
  • the material used for the channel layer has a larger band gap, particularly for a thin film transistor used for driving an organic EL.
  • the carrier concentration of the first region 14A and the second region 14B can be arbitrarily controlled by cation doping.
  • a material for example, Ti, Ta, etc.
  • the carrier concentration is preferably controlled by the amount).
  • TFT manufacturing method Next, a TFT manufacturing method according to an embodiment of the present invention will be briefly described using a top contact type TFT 40 having a bottom gate structure shown in FIG. 1C as a representative example. Note that the following method can be similarly applied to the manufacturing method of TFTs of other forms.
  • the substrate 12 is prepared, and the gate electrode 24 is formed on one surface of the substrate 12 in the thickness direction.
  • the method for forming the gate electrode 24 include a wet method such as a printing method and a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, and a chemical method such as a CVD method and a plasma CVD method. It is done.
  • the sputtering method after forming an electrode film by the sputtering method, the gate electrode 24 is formed by patterning into a predetermined shape by an etching or lift-off method. At this time, it is preferable to pattern the gate electrode 24 and the gate wiring simultaneously.
  • the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition.
  • a complex oxide target adjusted to have a desired cation composition may be used, or ternary co-sputtering may be used.
  • the second film forming step of forming the second region 14B with the second oxygen partial pressure / argon partial pressure inside the sputter film forming chamber is sequentially performed.
  • the order of the first film forming process and the second film forming process is reversed.
  • the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.
  • the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.
  • the oxygen partial pressure of the first region 14A it is possible to reduce defects related to oxygen in the first region 14A that can be a carrier traveling layer. Because it can. Thereby, excess carriers can be suppressed and high switching characteristics can be obtained.
  • an oxide semiconductor system such as InGaZnO, it is said that a deep level due to an oxygen defect exists immediately above a valence body.
  • this deep level can degrade the light stability, if this level is suppressed by increasing the oxygen partial pressure, the effect of increasing the light stability can be expected even though the effect is not as great as the composition.
  • the effect of ionized impurity scattering (which acts as a scattering source when there are ionized oxygen defects serving as donors) can be suppressed, so that relatively high mobility is likely to be realized. .
  • the substrate 12 it is preferable not to expose the substrate 12 to the air during the film forming process of the oxide semiconductor layer 14. That is, it is preferable to perform the first film formation step and the second film formation step continuously without exposing the substrate 12 to the atmosphere. This is for preventing impurities from being mixed into the oxide semiconductor layer 14.
  • Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and the pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.
  • an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.
  • a metal film for forming the source / drain electrodes 18 and 20 is formed on the surface of the oxide semiconductor layer 14.
  • the method for forming the source / drain electrodes 18 and 20 can be the same as that for the gate electrode 24.
  • the metal film is patterned into a predetermined shape by etching or a lift-off method, and the source electrode 18 and the drain electrode 20 are formed. At this time, it is preferable to pattern the source / drain electrodes 18 and 20 and wiring (not shown) connected to these electrodes simultaneously.
  • the atmosphere during post-annealing is preferably an inert atmosphere or an oxidizing atmosphere.
  • oxygen in the oxide semiconductor layer is difficult to escape, and generation of surplus carriers and variation in electrical characteristics can be suppressed.
  • the post-annealing time it is preferable to hold it for at least 10 minutes in consideration of the time required for the film temperature to become uniform.
  • the TFT 40 of the present embodiment high mobility and high light irradiation stability can be obtained without using a protective layer or the like on the oxide semiconductor layer 14 for reducing deterioration in characteristics due to light irradiation.
  • the oxide semiconductor layer 14 may be provided with a protective layer as described above.
  • a protective layer that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less)
  • the stability against light irradiation can be further improved.
  • a top contact type TFT 40 with a bottom gate structure as shown in FIG. 1C can be manufactured.
  • the InSnZnO film in the first region 14A and the InGaZnO film in the second region 14B can be formed at a low temperature (for example, 400 ° C. or lower).
  • a flexible TFT device can be manufactured as the entire TFT 40.
  • the TFT according to this embodiment can have various configurations other than the above.
  • an insulating layer is provided on the substrate 12 or exposed from between the source electrode 18 and the drain electrode 20.
  • a single protective layer or a plurality of protective layers may be provided on the surface of the oxide semiconductor layer 14.
  • electro-optical devices for example, display devices such as liquid crystal display devices, organic EL (Electro Luminescence) display devices, inorganic EL display devices, etc.
  • a driving element in the above, particularly for a large area device.
  • the TFT of this embodiment is particularly suitable for a device that can be manufactured by a low-temperature process using a resin substrate (for example, a flexible display), and various sensors such as an X-ray sensor, MEMS (Micro Electro Mechanical System), and the like. It is suitably used as a drive element (drive circuit) in this electronic device.
  • the electro-optical device or sensor includes the above-described TFT of the present invention.
  • electro-optical devices include display devices (eg, liquid crystal display devices, organic EL display devices, inorganic EL display devices, etc.).
  • an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), an X-ray sensor, or the like is suitable.
  • the electro-optical device or sensor of the present embodiment exhibits good characteristics with low power consumption.
  • the characteristics referred to here indicate display characteristics in the case of an electro-optical device (display device), and sensitivity characteristics in the case of a sensor.
  • a liquid crystal display device, an organic EL display device, and an X-ray sensor will be described as representative examples of an electro-optical device or sensor including a field effect transistor manufactured according to the present invention.
  • FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention.
  • the liquid crystal display device 100 of this embodiment includes a substrate 12, a top contact type TFT 10 having the top gate structure shown in FIG. 1A, and a gate electrode protected by a passivation layer 102 of the TFT 10.
  • 24 includes a liquid crystal layer 108 sandwiched between the pixel lower electrode 104 and the counter upper electrode 106, and an RGB color filter 110 for developing different colors corresponding to each pixel.
  • polarizing plates 112a and 112b are provided on the color filter 110, respectively.
  • the liquid crystal display device 100 of the present embodiment includes a plurality of gate lines 112 parallel to each other and data lines 114 parallel to each other intersecting the gate lines 112.
  • the gate wiring 112 and the data wiring 114 are electrically insulated.
  • the TFT 10 is provided in the vicinity of the intersection between the gate wiring 112 and the data wiring 114.
  • the gate electrode 24 of the TFT 10 is connected to the gate wiring 112, and the source electrode 18 of the TFT 10 is connected to the data wiring 114.
  • the drain electrode 20 of the TFT 10 is connected to the pixel lower electrode 104 through a contact hole 116 provided in the gate insulating film 22 (a conductor is embedded in the contact hole 116).
  • the pixel lower electrode 104 forms a capacitor 118 together with the grounded counter upper electrode 106.
  • the TFT 10 having the top gate structure is provided in the liquid crystal device of the present embodiment shown in FIG. 2.
  • the TFT used in the liquid crystal device which is the display device of the present invention is not limited to the top gate structure.
  • a TFT having a bottom gate structure may be used.
  • the TFT 10 manufactured according to the present invention has a high mobility, a high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen.
  • a high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen.
  • the InGaZnO film or the InSnZnO film of the oxide semiconductor layer 14 is amorphous, variation in element characteristics can be suppressed, and excellent display quality without unevenness can be realized on a large screen.
  • the gate voltage can be reduced, and thus the power consumption of the display device can be reduced.
  • a thin film transistor can be manufactured using an amorphous InGaZnO film or an InSnZnO film that can be formed at a low temperature (for example, 200 ° C. or lower) as a semiconductor layer.
  • a plastic substrate can be used. Therefore, according to the present invention, a flexible liquid crystal display device excellent in display quality can be provided.
  • FIG. 4 is a schematic sectional view of a part of an active matrix type organic EL display device according to an embodiment of the electro-optical device of the present invention
  • FIG. 5 is a schematic configuration diagram of the electric wiring. .
  • the simple matrix method has an advantage that it can be manufactured at low cost.
  • the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size.
  • the active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel.
  • it is suitable for high definition and large screen.
  • the organic EL display device 200 of this embodiment includes a plurality of gate wirings 220 that are parallel to each other, and data wirings 222 and driving wirings that are parallel to each other and intersect the gate wirings 220. 224.
  • the gate wiring 220, the data wiring 222, and the drive wiring 224 are electrically insulated.
  • the gate electrode 24 of the switching TFT 206 is connected to the gate wiring 220, and the source electrode 18 of the switching TFT 206 is connected to the data wiring 222.
  • the drain electrode 20 of the switching TFT 206 is connected to the driving TFT 204 gate electrode 24, and the driving TFT 10 a is kept on by using the capacitor 226.
  • the source electrode 18 of the driving TFT 204 is connected to the driving wiring 224, and the drain electrode 20 is connected to the organic EL light emitting element 214.
  • the organic EL device of this embodiment shown in FIG. 4 includes the top-gate driving TFT 204 and the switching TF 206.
  • the TFT used in the organic EL device which is the display device of the present invention is the top.
  • the TFT is not limited to the gate structure and may be a bottom gate TFT.
  • a thin film transistor can be manufactured using an amorphous InGaZnO film or an InSnZnO film that can be formed at a low temperature (for example, 200 ° C. or less) as the oxide semiconductor layer 14.
  • a resin substrate plastic substrate
  • FIG. 6 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention
  • FIG. 7 shows a schematic configuration diagram of its electric wiring.
  • FIG. 6 is a schematic cross-sectional view in which a part of the X-ray sensor array is enlarged more specifically.
  • the X-ray sensor 300 of this embodiment includes the TFT 10 and the capacitor 310 formed on the substrate 12, the charge collection electrode 302 formed on the capacitor 310, the X-ray conversion layer 304, and the upper electrode 306. Composed.
  • a passivation film 308 is provided on the TFT 10.
  • the capacitor 310 has a structure in which an insulating film 316 is sandwiched between a capacitor lower electrode 312 and a capacitor upper electrode 314.
  • the capacitor upper electrode 314 is connected to one of the source electrode 18 and the drain electrode 20 (the drain electrode 20 in FIG. 6) of the TFT 10 through a contact hole 318 provided in the insulating film 316.
  • the charge collection electrode 302 is provided on the capacitor upper electrode 314 in the capacitor 310 and is in contact with the capacitor upper electrode 314.
  • the X-ray conversion layer 304 is a layer containing amorphous selenium and is provided so as to cover the TFT 10 and the capacitor 310.
  • the upper electrode 306 is provided on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.
  • the X-ray sensor 300 of this embodiment includes a plurality of gate wirings 320 that are parallel to each other and a plurality of data wirings 322 that intersect with the gate wirings 320 and are parallel to each other.
  • the gate wiring 320 and the data wiring 322 are electrically insulated.
  • the TFT 10 is provided in the vicinity of the intersection between the gate wiring 320 and the data wiring 322.
  • the gate electrode 24 of the TFT 10 is connected to the gate wiring 320, and the source electrode 18 of the TFT 10 is connected to the data wiring 322.
  • the drain electrode 20 of the TFT 10 is connected to the charge collecting electrode 302, and the charge collecting electrode 302 is connected to the capacitor 310.
  • X-rays are irradiated from the upper part (upper electrode 306 side) in FIG. 6, and electron-hole pairs are generated in the X-ray conversion layer 304.
  • the generated charge is accumulated in the capacitor 310 and read out by sequentially scanning the TFT 10.
  • the X-ray sensor 300 of the present embodiment includes a TFT 10 with high mobility and on-current and excellent sensitivity characteristics, and thus has a high S / N and is suitable for a large screen. Moreover, since it has excellent sensitivity characteristics, an image with a wide dynamic range can be obtained when used in an X-ray digital imaging apparatus.
  • the X-ray digital imaging apparatus according to the present embodiment is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when the InGaZnO film or InSnZnO film in the TFT 10 is amorphous, an image with excellent uniformity can be obtained.
  • the TFT 10 having the top gate structure is provided in the X-ray sensor 300 of the present embodiment shown in FIG. 6, the TFT 10 having the top gate structure is provided.
  • the TFT used in the sensor of the present invention is not limited to the top gate structure, but the bottom gate structure.
  • a TFT having a gate structure may be used.
  • composition modulation is performed for each of the examples and the comparative examples, so that the first region 506 of the oxide semiconductor layer has a thickness of 5 nm.
  • a sputtering film formation As shown in FIGS. 8A and 8B, a p-type Si substrate 502 with a thermal oxide film 504 (1 inch angle ⁇ 1 mm, thickness) as a substrate. : 525 ⁇ mt, thermal oxide film (SiO 2 ): 100 nmt), and a simple TFT 500 using the thermal oxide film 504 as a gate insulating film was manufactured.
  • composition modulation is performed for each of the examples and the comparative examples, so that the first
  • the film formation conditions were as follows: ultimate vacuum during film formation: 6 ⁇ 10 ⁇ 6 Pa, pressure during film formation: 4.4 ⁇ 10 ⁇ 1 Pa, film formation temperature: room temperature, oxygen partial pressure / argon partial pressure: 0.00. 067 was common to all examples and comparative examples.
  • the first region 506 is not an InSnZnO film but an InGaZnO film.
  • the second region 508 of the oxide semiconductor layer was formed by sputtering with a thickness of 50 nm and a vertical and horizontal width of 3 mm ⁇ 4 mm.
  • a pattern was formed using a metal mask, and the oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere.
  • Sputtering of each region was performed by ternary co-sputtering using an In 2 O 3 target, a SnO 2 (or Ga 2 O 3 ) target, and a ZnO target in the first region 506 and the second region 508. .
  • the film thickness in each region was adjusted by adjusting the film formation time.
  • composition analysis is performed by fluorescent X-ray analysis on a film-formed sample formed by performing film formation under the same conditions as those of the first region 506 and the second region 508 according to Examples 1 to 10 and Comparative Examples 1 to 4. Thus, it was confirmed that each of the first region 506 and the second region 508 had the above composition. In addition, it was confirmed by X-ray diffraction measurement that each film formation sample was an amorphous film.
  • source / drain electrodes 510 and 512 were formed on the surface of the second region 508 by sputtering.
  • the source / drain electrodes 510 and 512 were formed by pattern film formation using a metal mask. After depositing 10 nm of Ti, 40 nm of Au was deposited.
  • post-annealing was performed in an atmosphere of 300 ° C. and oxygen partial pressure of 100%.
  • FIG. 9 is a diagram showing a ternary phase diagram focusing on the composition of the first region 506 in Examples 1 to 10 and Comparative Examples 2 to 4. Note that the first region 506 in Comparative Example 1 is not shown in the ternary phase diagram because part of its composition is Ga, not Sn.
  • the TFTs according to Comparative Example 5 and Comparative Example 6 have the same configuration as the TFT according to Example 1 except for the configuration of the oxide semiconductor layer.
  • the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 4 were evaluated for Vg-Id characteristics and then irradiated with wavelength-variable monochrome light, so that the TFT characteristics were stable with respect to light irradiation. Evaluated.
  • each TFT was placed on a probe stage stage and dried air was allowed to flow for 2 hours or more, and then TFT characteristics were measured in the dried air atmosphere.
  • the irradiation intensity of the monochrome light source is 10 ⁇ W / cm 2
  • the wavelength ⁇ is 360 to 700 nm
  • the Vg-Id characteristics when the monochrome light is not irradiated are compared with the Vg-Id characteristics when the monochrome light is irradiated.
  • Stability ( ⁇ Vth) was evaluated.
  • the threshold shift amount ⁇ Vth for light irradiation of 420 nm was used as an indicator of TFT light stability.
  • Vg-Id characteristics among the measurement results of IV characteristics during monochrome light irradiation are shown in FIGS. 11 to 15 together with the characteristics before monochrome light irradiation.
  • the said evaluation method is common in a following example.
  • Table 3 summarizes the measurement results of the mobility, the threshold voltage Vth obtained from the IV characteristics, and the threshold shift amount ⁇ Vth obtained from the IV characteristics before and after the monochrome light irradiation.
  • Comparative Examples 5 and 6 when a film having the same composition as that of Example 5 or Example 3 was used as a single film of the oxide semiconductor layer, the threshold voltage was greatly negative, It was found that the situation does not show clear switching characteristics (indicated by “-” in Table 3). Therefore, from this example, the InSnZnO film is disposed on the side closer to the gate electrode, and the InGaZnO film is disposed on the side far from the gate electrode, thereby exhibiting high mobility, good On / Off ratio, and switching characteristics in the TFT. I understood it.
  • the threshold fluctuation amount (threshold shift amount ⁇ Vth) at the time of light irradiation is smaller than the results of Comparative Examples 1 to 4.
  • of the threshold shift amount is within 1V
  • of the threshold shift amount is a large value exceeding 1V. I understand.
  • FIG. 16 is a graph plotting the relationship between the threshold voltage and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the total composition ratio of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of the threshold voltage in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the threshold voltage depends on the Zn ratio ⁇ c / (a + b + c) ⁇ , and it can be seen that the threshold voltage tends to increase as the Zn ratio increases.
  • the threshold voltage is on the minus side compared to the other embodiments, and the second embodiment is also close to 0, indicating that the off-current is slightly higher. This is presumably because the carrier concentration in Examples 1 to 4 is higher than that in other Examples.
  • the carrier concentration is considered to be higher when the element content of Zn is lower than that of In or Sn elements that are likely to induce carriers. . Therefore, it can be said that the Zn content in the InSnZnO film (first region) is preferably higher to some extent from the viewpoint of threshold voltage and off-current.
  • the threshold voltage appears significantly on the negative side.
  • the threshold voltage is close to 0 or takes a positive value. Therefore, it can be seen that the composition of the first region is preferably expressed by c / (a + b + c) ⁇ 0.200 from the viewpoint of suppressing the threshold voltage of the TFT from appearing on the minus side.
  • the composition of the first region is expressed by c / (a + b + c) ⁇ 1/3 from the viewpoint that the threshold voltage of the TFT 40 can be made higher on the positive side than 0V. It can be seen that is more preferable.
  • the composition of the first region is expressed by c / (a + b + c) ⁇ 0.400. It turns out that it is even more preferable.
  • FIG. 17 is a graph plotting the relationship between the mobility and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the total composition ratio of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of the mobility in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the mobility depends on the Zn ratio ⁇ c / (a + b + c) ⁇ , and it can be seen that the mobility increases as the Zn ratio decreases. It was also confirmed that the Zn ratio rapidly increased as the Zn ratio decreased from 0.800 to 0.700, and that the mobility was higher than 30 cm 2 / Vs at 0.700 or less. Therefore, it can be seen that the composition of the first region is preferably expressed by c / (a + b + c) ⁇ 0.700 from the viewpoint of setting the mobility to more than 30 cm 2 / Vs.
  • FIG. 18 is a graph plotting the relationship between the mobility and the In ratio ⁇ a / (a + b + c) ⁇ with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of the mobility in each In ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the mobility depends on the In ratio ⁇ a / (a + b + c) ⁇ , and it can be seen that the mobility increases as the In ratio increases. It was also confirmed that the In ratio increased rapidly from 0.100 to 1/3, and that the mobility was over 40 cm 2 / Vs after 1/3. Therefore, it was found that the composition of the first region is preferably represented by a / (a + b + c) ⁇ 1/3.
  • FIG. 19 is a graph plotting the relationship between the threshold shift amount ⁇ Vth and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of threshold value shift amount (DELTA) Vth in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the threshold shift amount ⁇ Vth does not depend on the Zn ratio compared to the mobility and the threshold voltage.
  • the Zn ratio c is 0.1 and 0.8
  • of the threshold shift amount is 0.8 V or more and approaches 1 V as a reference, but the Zn ratio c is 0.200 ⁇ c / If it is within the range of (a + b + c) ⁇ 0.700 (hatching range shown in FIG. 9), the absolute value of the threshold shift amount
  • TFTs according to Examples 11 to 15 were produced.
  • the film thicknesses of the first regions of the TFTs according to Examples 11 to 15 were 10, 15, 30, 50, and 70 nm, respectively.
  • the thickness of the first region is preferably 50 nm or less. This is because if it is 50 nm or less, the threshold voltage of the TFT can be suppressed from appearing on the negative side, and the deterioration of the S value can be suppressed. Further, it can be seen that the threshold voltage takes a positive value when the film thickness of the first region is 30 nm or less. Therefore, it was found that the thickness of the first region is preferably 30 nm or less.
  • the disclosure of Japanese application 2012-101414 is incorporated herein by reference in its entirety. All documents, patent applications, and technical standards mentioned in this specification are to the same extent as if each individual document, patent application, and technical standard were specifically and individually described to be incorporated by reference, Incorporated herein by reference.

Abstract

A field effect transistor includes an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulation film, and a gate electrode, wherein the oxide semiconductor layer has a first region including In(a) Sn(b) Zn(c) O(d) (where a > 0, b > 0, c > 0, d > 0, a + b + c = 1) and a second region including In(e) Ga(f) Zn(g) O(h) (where e > 0, f > 0, g > 0, h > 0, e + f + g = 1) disposed on a side further from the gate electrode than the first region.

Description

電界効果型トランジスタ及びその製造方法、表示装置、イメージセンサ並びにＸ線センサFIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE, IMAGE SENSOR, AND X-RAY SENSOR
　本発明は、電界効果型トランジスタ及びその製造方法、表示装置、イメージセンサ並びにＸ線センサに関する。 The present invention relates to a field effect transistor, a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor.
　近年、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系（以下、ＩｎＧａＺｎＯと称す）の酸化物半導体薄膜を酸化物半導体層（チャネル層）に用いた電界効果型トランジスタ、特に薄膜トランジスタ（Ｔｈｉｎ　Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ：ＴＦＴ）の研究開発が盛んである。酸化物半導体薄膜は低温成膜が可能であり、且つアモルファスシリコンよりも高移動度を示し、更に可視光に透明であることから、プラスチック板やフィルム等の基板上にフレキシブルなＴＦＴを形成することが可能である（例えばC.S. Chuang et al., SID 08 DIGEST, P-13）。 In recent years, research on a field effect transistor using an In—Ga—Zn—O-based (hereinafter referred to as InGaZnO) oxide semiconductor thin film as an oxide semiconductor layer (channel layer), particularly a thin film transistor (Thin Film Transistor: TFT). Development is thriving. An oxide semiconductor thin film can be formed at a low temperature, exhibits higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible TFT should be formed on a substrate such as a plastic plate or film. Is possible (eg CS Chuang et al., SID 08 DIGEST, P-13).
　このようなＩｎＧａＺｎＯを酸化物半導体層に用いたＴＦＴの変形例として、特開２０１０－２１５５５号公報には、ゲート電極に近い側にＩＴＯ（ＩｎとＳｎとＯ）を含む第１の領域が配置され、ゲート電極から遠い側にＩｎＧａＺｎＯを含む第２の領域が配置された二層構造の酸化物半導体層を用いたＴＦＴが開示されている。 As a modified example of such a TFT using InGaZnO as an oxide semiconductor layer, Japanese Patent Laying-Open No. 2010-21555 includes a first region containing ITO (In, Sn, and O) on the side close to the gate electrode. A TFT using an oxide semiconductor layer having a two-layer structure in which a second region containing InGaZnO is disposed on a side far from the gate electrode is disclosed.
　同様に、特開２０１０－２１３３３号公報には、ゲート電極に近い側にＩｎ－Ｚｎ－Ｏ系（以下ＩｎＺｎＯと称す）の酸化物半導体を含む第１の領域が配置され、ゲート電極から遠い側にＩｎＧａＺｎＯを含む第２の領域が配置された二層構造の酸化物半導体層を用いたＴＦＴが開示されている。 Similarly, in Japanese Patent Application Laid-Open No. 2010-21333, a first region containing an In—Zn—O-based (hereinafter referred to as InZnO) oxide semiconductor is disposed on the side close to the gate electrode, and the side far from the gate electrode is disclosed. Discloses a TFT using an oxide semiconductor layer having a two-layer structure in which a second region containing InGaZnO is disposed.
　また、特開２００６－１６５５２９号公報には、Ｉｎ－Ｓｎ－Ｚｎ－Ｏ系（以下ＩｎＳｎＺｎＯと称す）の酸化物半導体を含む非晶質酸化物を酸化物半導体層に用いたＴＦＴが開示されている。 Japanese Laid-Open Patent Publication No. 2006-165529 discloses a TFT in which an amorphous oxide including an In—Sn—Zn—O-based (hereinafter referred to as InSnZnO) oxide semiconductor is used for an oxide semiconductor layer. Yes.
　ところで、ＴＦＴを含む有機ＥＬ（Ｅｌｅｃｔｒｏ Ｌｕｍｉｎｅｓｃｅｎｃｅ）や液晶に用いられる青色発光層は波長４５０ｎｍ程度のピークを持つブロードな発光を示すが、有機ＥＬ素子の青色光の発光スペクトルの裾は波長４２０ｎｍまで続いていること、青色カラーフィルタは波長４００ｎｍの光を７０％程度は通すこと、を考慮すると、波長４５０ｎｍよりも小さい波長域での光照射に対する特性劣化が低いことが要求される。仮にＩｎＧａＺｎＯ膜の光学バンドギャップが比較的狭く、その領域に光学吸収を持つ場合には、トランジスタの閾値シフトが起こってしまうという問題が生じる。 By the way, a blue light emitting layer used for an organic EL (Electro Luminescence) including TFT and a liquid crystal shows broad light emission having a peak of about 450 nm, but the tail of the emission spectrum of blue light of the organic EL element continues to a wavelength of 420 nm. In consideration of the fact that the blue color filter allows light having a wavelength of 400 nm to pass through about 70%, it is required that the characteristic deterioration with respect to light irradiation in a wavelength region smaller than the wavelength 450 nm is low. If the optical band gap of the InGaZnO film is relatively narrow and the region has optical absorption, there arises a problem that a threshold shift of the transistor occurs.
　ここで、例えば、光照射に対する安定性の指標として、４２０ｎｍの光照射に対する閾値シフト量の絶対値｜ΔＶｔｈ｜を１Ｖ以下という基準を設けると、４２０ｎｍの光照射に対して｜ΔＶｔｈ｜≦１Ｖを満たすようなＴＦＴを実現する事は困難である。 Here, for example, as a measure of stability against light irradiation, if a criterion that the absolute value | ΔVth | of the threshold shift amount for 420 nm light irradiation is 1 V or less is provided, | ΔVth | ≦ 1 V is set for 420 nm light irradiation. It is difficult to realize a TFT that satisfies the requirements.
　具体的に、C.S. Chuang et al., SID 08 DIGEST, P-13では、従来のＩｎＧａＺｎＯを酸化物半導体層に用いたＴＦＴに対して光照射に対する特性劣化を評価しているが、波長４２０ｎｍの光照射に対する閾値シフト量の絶対値｜ΔＶｔｈ｜が１Ｖを超えてしまう。 Specifically, CS Chuang et al., SID 08 DIGEST, P-13 evaluates the deterioration of characteristics of a TFT using conventional InGaZnO as an oxide semiconductor layer against light irradiation. The absolute value | ΔVth | of the threshold shift amount with respect to irradiation exceeds 1V.
　一方で、ディスプレイの大型化、高精細化に伴い、ディスプレイ駆動用のＴＦＴの更なる高移動度化（例えば２０ｃｍ２／Ｖｓ超）が求められており、C.S. Chuang et al., SID 08 DIGEST, P-13のような従来のＴＦＴ(移動度１０ｃｍＡ２／Ｖｓ程度)ではカバーできないような高機能ディスプレイも提案されつつある。 On the other hand, with the increase in size and resolution of displays, there is a demand for higher mobility of display driving TFTs (for example, more than 20 cm 2 / Vs). CS Chuang et al., SID 08 DIGEST, High-performance displays that cannot be covered with conventional TFTs (mobility of about 10 cmA 2 / Vs) such as P-13 are also being proposed.
　特開２０１０－２１５５５号公報では、電流パス層としての第１の領域がＩＴＯを含んでおり高移動度のＴＦＴは実現可能であるが、光照射特性について言及されていない。 In Japanese Patent Laid-Open No. 2010-21555, the first region as the current path layer contains ITO, and a high mobility TFT can be realized, but the light irradiation characteristic is not mentioned.
　また、特開２０１０－２１３３３号公報では、電流パス層としての第１の領域がＩｎＺｎＯを含んでいるものの移動度は１０ｃｍＡ２／Ｖｓよりも低く、光照射特性については言及されていない。なお、ＩｎＺｎＯの他にＳｎを第１の領域に不可避不純物以上のレベルで含ませる組み合わせも記載されているが、その場合の実施例に係るＴＦＴや移動度、光照射特性について言及されていない。 In Japanese Patent Laid-Open No. 2010-21333, the mobility of the first region as the current path layer containing InZnO is lower than 10 cmA 2 / Vs, and the light irradiation characteristics are not mentioned. In addition to InZnO, a combination in which Sn is included in the first region at a level equal to or higher than inevitable impurities is described, but the TFT, mobility, and light irradiation characteristics according to the example are not mentioned.
　また、特開２００６－１６５５２９号公報のようにＩｎＳｎＺｎＯ膜を単層の酸化物半導体層に用いたＴＦＴだと、高移動度と高いスイッチング性能（例えばＯｎ／Ｏｆｆ比が１０６超）を実現する事は困難である。これは比較的ＩｎＳｎＺｎＯ膜のキャリア濃度が高いために、ＩｎＳｎＺｎＯ膜単独ではピンチオフが困難であるためである。さらに特開２００６－１６５５２９号公報には、光照射特性について言及されていない。 Further, to realize that's a TFT using a InSnZnO film as in JP-A No. 2006-165529 to the oxide semiconductor layer having a single layer, high mobility and high switching performance (e.g. On / Off ratio is more than 10 6) Things are difficult. This is because the carrier concentration of the InSnZnO film is relatively high, so that pinch-off is difficult with the InSnZnO film alone. Furthermore, Japanese Patent Application Laid-Open No. 2006-165529 does not mention light irradiation characteristics.
　本発明は上記事情に鑑みてなされたものであり、２０ｃｍ２／Ｖｓ超の高い移動度と、波長４２０ｎｍの光照射に対して閾値シフト量の絶対値｜ΔＶｔｈ｜が１Ｖ以下となる高い光安定性と、を両立する電界効果型トランジスタ及びその製造方法、表示装置、イメージセンサ並びにＸ線センサを提供することを目的とする。 The present invention has been made in view of the above circumstances, and has a high mobility exceeding 20 cm 2 / Vs and a high light stability in which the absolute value | ΔVth | of the threshold shift amount is 1 V or less with respect to light irradiation with a wavelength of 420 nm. It is an object of the present invention to provide a field effect transistor and a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor.
　本発明の上記課題は下記の手段によって解決された。
＜１＞酸化物半導体層と、ソース電極と、ドレイン電極と、ゲート絶縁膜と、ゲート電極とを有する電界効果型トランジスタであって、前記酸化物半導体層は、Ｉｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）（ａ＞０，ｂ＞０，ｃ＞０，ｄ＞０，ａ＋ｂ＋ｃ＝１）を含む第１の領域と、前記第１の領域よりも前記ゲート電極から遠い側に配置されており、Ｉｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）（ｅ＞０，ｆ＞０，ｇ＞０，ｈ＞０，ｅ＋ｆ＋ｇ＝１）を含む第２の領域と、を有する、電界効果型トランジスタ。
＜２＞前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧０．２００で表される、前記＜１＞に記載の電界効果型トランジスタ。
＜３＞前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≦０．７００で表される、前記＜１＞又は前記＜２＞に記載の電界効果型トランジスタ。
＜４＞前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧１／３で表される、前記＜１＞～前記＜３＞の何れか１つに記載の電界効果型トランジスタ。
＜５＞前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧０．４００で表される、前記＜１＞～前記＜４＞の何れか１つに記載の電界効果型トランジスタ。
＜６＞前記第１の領域の組成は、ａ／（ａ＋ｂ＋ｃ）≧１／３で表される、前記＜１＞～前記＜５＞の何れか１つに記載の電界効果型トランジスタ。
＜７＞前記第１の領域の膜厚は、５０ｎｍ以下である、前記＜１＞～前記＜６＞の何れか１つに記載の電界効果型トランジスタ。
＜８＞前記第１の領域の膜厚は、１６ｎｍ以下である、前記＜７＞に記載の電界効果型トランジスタ。
＜９＞前記第１の領域の膜厚は、５ｎｍ以上である、前記＜１＞～前記＜８＞の何れか１つに記載の電界効果型トランジスタ。
＜１０＞前記第２の領域の組成は、ｆ／（ｅ＋ｆ）≦０．８７５で表される、前記＜１＞～前記＜９＞の何れか１つに記載の電界効果型トランジスタ。
＜１１＞前記第２の領域の組成は、ｆ／（ｅ＋ｆ）＞０．２５０で表される、前記＜１＞～前記＜１０＞の何れか１つに記載の電界効果型トランジスタ。
＜１２＞前記第２の領域の膜厚は、１０ｎｍ超７０ｎｍ未満である、前記＜１＞～前記＜１１＞の何れか１つに記載の電界効果型トランジスタ。
＜１３＞前記酸化物半導体層は非晶質膜である、前記＜１＞～前記＜１２＞の何れか１つに記載の電界効果型トランジスタ。
＜１４＞前記第２の領域は、前記第１の領域よりも電気伝導度が低い、前記＜１＞～前記＜１３＞の何れか１つに記載の電界効果型トランジスタ。 The above-described problems of the present invention have been solved by the following means.
<1> A field effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, wherein the oxide semiconductor layer is made of In (a) Sn (b) A first region containing Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0, a + b + c = 1), and a side farther from the gate electrode than the first region And a second region including In (e) Ga (f) Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0, e + f + g = 1) A field effect transistor.
<2> The field effect transistor according to <1>, wherein the composition of the first region is represented by c / (a + b + c) ≧ 0.200.
<3> The field effect transistor according to <1> or <2>, wherein the composition of the first region is represented by c / (a + b + c) ≦ 0.700.
<4> The field effect transistor according to any one of <1> to <3>, wherein the composition of the first region is represented by c / (a + b + c) ≧ 1/3.
<5> The field effect transistor according to any one of <1> to <4>, wherein the composition of the first region is represented by c / (a + b + c) ≧ 0.400.
<6> The field effect transistor according to any one of <1> to <5>, wherein the composition of the first region is represented by a / (a + b + c) ≧ 1/3.
<7> The field effect transistor according to any one of <1> to <6>, wherein the film thickness of the first region is 50 nm or less.
<8> The field effect transistor according to <7>, wherein the film thickness of the first region is 16 nm or less.
<9> The field effect transistor according to any one of <1> to <8>, wherein the film thickness of the first region is 5 nm or more.
<10> The field effect transistor according to any one of <1> to <9>, wherein the composition of the second region is represented by f / (e + f) ≦ 0.875.
<11> The field effect transistor according to any one of <1> to <10>, wherein the composition of the second region is represented by f / (e + f)> 0.250.
<12> The field effect transistor according to any one of <1> to <11>, wherein the film thickness of the second region is more than 10 nm and less than 70 nm.
<13> The field effect transistor according to any one of <1> to <12>, wherein the oxide semiconductor layer is an amorphous film.
<14> The field effect transistor according to any one of <1> to <13>, wherein the second region has lower electrical conductivity than the first region.
＜１５＞酸化物半導体層と、ソース電極と、ドレイン電極と、ゲート絶縁膜と、ゲート電極とを有する電界効果型トランジスタの製造方法であって、前記酸化物半導体層の成膜工程として、Ｉｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）（ａ＞０，ｂ＞０，ｃ＞０，ｄ＞０、ａ＋ｂ＋ｃ＝１）を含む第１の領域を、成膜室内を第１の酸素分圧／アルゴン分圧としてスパッタリング法により成膜する第１成膜工程と、前記第１の領域よりも前記ゲート電極から遠い側に配置され、Ｉｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）（ｅ＞０，ｆ＞０，ｇ＞０，ｈ＞０、ｅ＋ｆ＋ｇ＝１）を含む第２の領域を、前記成膜室内を第２の酸素分圧／アルゴン分圧としてスパッタリング法により成膜する第２成膜工程と、を有する、電界効果型トランジスタの製造方法。
＜１６＞前記第１の酸素分圧／アルゴン分圧が、前記第２の酸素分圧／アルゴン分圧よりも高い、前記＜１５＞に記載の電界効果型トランジスタの製造方法。
＜１７＞前記＜１＞～前記＜１４＞の何れか１つに記載の電界効果型トランジスタを備える表示装置。
＜１８＞前記＜１＞～前記＜１４＞の何れか１つに記載の電界効果型トランジスタを備えるイメージセンサ。
＜１９＞前記＜１＞～前記＜１４＞の何れか１つに記載の電界効果型トランジスタを備えるＸ線センサ。 <15> A method of manufacturing a field effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, wherein the oxide semiconductor layer is formed as a step of In (A) Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0, a + b + c = 1) A first film forming step of forming a film by a sputtering method at an oxygen partial pressure / argon partial pressure of In (e) Ga (f) Zn (g ) disposed on a side farther from the gate electrode than the first region. ) O (h) The second region including (e> 0, f> 0, g> 0, h> 0, e + f + g = 1) is set as the second oxygen partial pressure / argon partial pressure in the film formation chamber. And a second film forming step of forming a film by a sputtering method. Manufacturing method.
<16> The method for producing a field effect transistor according to <15>, wherein the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.
<17> A display device comprising the field-effect transistor according to any one of <1> to <14>.
<18> An image sensor comprising the field-effect transistor according to any one of <1> to <14>.
<19> An X-ray sensor comprising the field effect transistor according to any one of <1> to <14>.
　本発明によれば、２０ｃｍ２／Ｖｓ超の高い移動度と、波長４２０ｎｍの光照射に対して閾値シフト量の絶対値｜ΔＶｔｈ｜が１Ｖ以下となる高い光安定性と、を両立する電界効果型トランジスタ及びその製造方法、表示装置、イメージセンサ並びにＸ線センサを提供することができる。 According to the present invention, a field effect that achieves both high mobility exceeding 20 cm 2 / Vs and high light stability in which the absolute value | ΔVth | of the threshold shift amount is 1 V or less with respect to light irradiation with a wavelength of 420 nm. Type transistor, manufacturing method thereof, display device, image sensor, and X-ray sensor can be provided.
図１（Ａ）は、本発明の実施形態に係るＴＦＴであって、トップゲート構造でトップコンタクト型のＴＦＴの一例を示す模式図である。図１（Ｂ）は、本発明の実施形態に係るＴＦＴであって、トップゲート構造でボトムコンタクト型のＴＦＴの一例を示す模式図である。図１（Ｃ）は、本発明の実施形態に係るＴＦＴであって、ボトムゲート構造でトップコンタクト型のＴＦＴの一例を示す模式図である。図１（Ｄ）は、本発明の実施形態に係るＴＦＴであって、ボトムゲート構造でボトムコンタクト型のＴＦＴの一例を示す模式図である。FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention. FIG. 1B is a schematic diagram showing an example of a bottom contact type TFT with a top gate structure, which is a TFT according to an embodiment of the present invention. FIG. 1C is a schematic diagram showing an example of a top contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention. FIG. 1D is a schematic diagram showing an example of a bottom contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention. 図２は、本発明の電気光学装置の一実施形態の液晶表示装置について、その一部分の概略断面図である。FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the invention. 図３は、図２に示す液晶表示装置の電気配線の概略構成図である。FIG. 3 is a schematic configuration diagram of electrical wiring of the liquid crystal display device shown in FIG. 図４は、本発明の電気光学装置の一実施形態のアクティブマトリックス方式の有機ＥＬ表示装置について、その一部分の概略断面図である。FIG. 4 is a schematic sectional view of a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the invention. 図５は、図４に示す電気光学装置の電気配線の概略構成図である。FIG. 5 is a schematic configuration diagram of the electrical wiring of the electro-optical device shown in FIG. 図６は、本発明のセンサの一実施形態であるＸ線センサについて、その一部分の概略断面図である。FIG. 6 is a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention. 図７は、図６に示すセンサの電気配線の概略構成図である。FIG. 7 is a schematic configuration diagram of electrical wiring of the sensor shown in FIG. 図８（Ａ）は実施例及び比較例のＴＦＴの平面図であり、図８（Ｂ）は図８（Ａ）に示すＴＦＴのＡ－Ａ線矢視断面図である。FIG. 8A is a plan view of the TFTs of the example and the comparative example, and FIG. 8B is a cross-sectional view of the TFT shown in FIG. 図９は、実施例１～１０及び比較例２～４における第１の領域の組成に着目した三元相図を示す図である。FIG. 9 is a diagram showing a ternary phase diagram focusing on the composition of the first region in Examples 1 to 10 and Comparative Examples 2 to 4. 図１０は、実施例１～１０および比較例１～６に係るＴＦＴについてトランジスタ特性（Ｖｇ－Ｉｄ特性）の測定結果のうち代表的なＶｇ－Ｉｄ特性を示す図である。FIG. 10 is a diagram showing representative Vg-Id characteristics among the measurement results of transistor characteristics (Vg-Id characteristics) for the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 6. 図１１は、実施例３に係るＴＦＴのモノクロ光照射時のＩ－Ｖ特性を、モノクロ光照射前のＩ－Ｖ特性と共に示す図である。FIG. 11 is a diagram illustrating the IV characteristics when the TFT according to Example 3 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light. 図１２は、実施例５に係るＴＦＴのモノクロ光照射時のＩ－Ｖ特性を、モノクロ光照射前のＩ－Ｖ特性と共に示す図である。FIG. 12 is a diagram illustrating the IV characteristics when the TFT according to Example 5 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light. 図１３は、実施例６に係るＴＦＴのモノクロ光照射時のＩ－Ｖ特性を、モノクロ光照射前のＩ－Ｖ特性と共に示す図である。FIG. 13 is a diagram illustrating the IV characteristics when the TFT according to Example 6 is irradiated with monochrome light, together with the IV characteristics before monochrome light irradiation. 図１４は、実施例７に係るＴＦＴのモノクロ光照射時のＩ－Ｖ特性を、モノクロ光照射前のＩ－Ｖ特性と共に示す図である。FIG. 14 is a diagram illustrating the IV characteristics when the TFT according to Example 7 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light. 図１５は、比較例１に係るＴＦＴのモノクロ光照射時のＩ－Ｖ特性を、モノクロ光照射前のＩ－Ｖ特性と共に示す図である。FIG. 15 is a diagram illustrating the IV characteristics when the TFT according to Comparative Example 1 is irradiated with monochrome light, together with the IV characteristics before monochrome light irradiation. 図１６は、閾値電圧と、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。FIG. 16 is a graph plotting the relationship between the threshold voltage and the Zn ratio {c / (a + b + c)} with respect to the total composition ratio of In, Sn, and Zn in the first region based on Table 3. 図１７は、移動度と、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。FIG. 17 is a graph plotting the relationship between the mobility and the Zn ratio {c / (a + b + c)} with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3. 図１８は、移動度と、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＩｎ比｛ａ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。FIG. 18 is a graph in which the relationship between the mobility and the In ratio {a / (a + b + c)} with respect to the total composition ratio of In, Sn, and Zn in the first region is plotted based on Table 3. 図１９は、閾値シフト量ΔＶｔｈと、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。FIG. 19 is a graph plotting the relationship between the threshold shift amount ΔVth and the Zn ratio {c / (a + b + c)} with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3. . 図２０は、ＩｎＳｎＺｎＯ単膜におけるキャリア濃度の組成依存性を示す図である。FIG. 20 is a diagram showing the composition dependence of the carrier concentration in the InSnZnO single film.
　以下、添付の図面を参照しながら、本発明の実施形態に係る電界効果型トランジスタ及びその製造方法、表示装置、イメージセンサ並びにＸ線センサについて具体的に説明する。なお、図中、同一又は対応する機能を有する部材（構成要素）には同じ符号を付して適宜説明を省略する。また、以下で説明する場合に用いる「上」及び「下」という用語は、便宜的に用いるものであって、方向に拘束されるべきでない。 Hereinafter, with reference to the attached drawings, a field effect transistor and a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor according to an embodiment of the present invention will be described in detail. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals and description thereof is omitted as appropriate. In addition, the terms “upper” and “lower” used in the following description are used for convenience and should not be constrained in a direction.
１．電界効果型トランジスタ
　本発明の実施形態に係る電界効果型トランジスタについて、ＴＦＴを一例に挙げて具体的に説明する。 1. Field Effect Transistor A field effect transistor according to an embodiment of the present invention will be specifically described by taking a TFT as an example.
＜ＴＦＴの概略構成＞
　本発明の実施形態に係るＴＦＴは、ゲート電極、ゲート絶縁膜、酸化物半導体層（活性層）、ソース電極及びドレイン電極を有し、ゲート電極に電圧を印加して、酸化物半導体層に流れる電流を制御し、ソース電極とドレイン電極間の電流をスイッチングする機能を有するアクテイブ素子である。そして、本発明の実施形態に係るＴＦＴではさらに、酸化物半導体層が、膜厚方向に第１の領域と、当該第１の領域よりもゲート電極から遠い側に配置された第２の領域を備えている。なお、本実施形態のＴＦＴにおいては、第１の領域と第２の領域間に電極層等の酸化物半導体層以外の層は挿入されない。なお、本発明において、ＴＦＴは基板上に形成されていてもよいし、あるいは、ＴＦＴの構成要素（例えば、電極）が基板として働く場合には、別途の基板を省略してもよい。また、ＴＦＴと基板とは直接接していても、ＴＦＴと基板との間に追加的な層や要素が設けられていてもよい。 <Schematic configuration of TFT>
A TFT according to an embodiment of the present invention includes a gate electrode, a gate insulating film, an oxide semiconductor layer (active layer), a source electrode, and a drain electrode, and applies a voltage to the gate electrode to flow through the oxide semiconductor layer. It is an active element having a function of controlling current and switching current between a source electrode and a drain electrode. In the TFT according to the embodiment of the present invention, the oxide semiconductor layer further includes a first region in the film thickness direction and a second region disposed on the side farther from the gate electrode than the first region. I have. In the TFT of this embodiment, no layer other than the oxide semiconductor layer such as an electrode layer is inserted between the first region and the second region. In the present invention, the TFT may be formed on the substrate, or when a component (for example, an electrode) of the TFT functions as the substrate, a separate substrate may be omitted. Further, the TFT and the substrate may be in direct contact, or an additional layer or element may be provided between the TFT and the substrate.
　ＴＦＴの素子構造としては、ゲート電極の位置に基づいた、いわゆる逆スタガ構造（ボトムゲート構造（型）とも呼ばれる）及びスタガ構造（トップゲート構造（型）とも呼ばれる）のいずれの態様であってもよい。また、酸化物半導体層とソース電極及びドレイン電極（適宜、「ソース・ドレイン電極」という。）との接触部分に基づき、いわゆるトップコンタクト型、ボトムコンタクト型のいずれの態様であってもよい。
　なお、トップゲート構造とは、ゲート絶縁膜の上側にゲート電極が配置され、ゲート絶縁膜の下側に酸化物半導体層が形成された形態であり、ボトムゲート構造とは、ゲート絶縁膜の下側にゲート電極が配置され、ゲート絶縁膜の上側に酸化物半導体層が形成された形態である。また、ボトムコンタクト型とは、ソース・ドレイン電極が酸化物半導体層よりも先に形成されて酸化物半導体層の下面がソース・ドレイン電極に接触する形態であり、トップコンタクト型とは、酸化物半導体層がソース・ドレイン電極よりも先に形成されて酸化物半導体層の上面がソース・ドレイン電極に接触する形態である。 The element structure of the TFT may be any of a so-called reverse stagger structure (also referred to as a bottom gate structure (type)) and a stagger structure (also referred to as a top gate structure (type)) based on the position of the gate electrode. Good. Further, based on a contact portion between the oxide semiconductor layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be employed.
Note that the top gate structure is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an oxide semiconductor layer is formed on the lower side of the gate insulating film. The gate electrode is disposed on the side, and the oxide semiconductor layer is formed on the upper side of the gate insulating film. The bottom contact type is a form in which the source / drain electrodes are formed before the oxide semiconductor layer and the lower surface of the oxide semiconductor layer is in contact with the source / drain electrodes. The top contact type is an oxide In this embodiment, the semiconductor layer is formed before the source / drain electrodes, and the upper surface of the oxide semiconductor layer is in contact with the source / drain electrodes.
　図１（Ａ）は、本発明の実施形態に係るＴＦＴであって、トップゲート構造でトップコンタクト型のＴＦＴの一例を示す模式図である。図１（Ａ）に示すＴＦＴ１０では、基板１２の厚み方向の一面に酸化物半導体層１４の第２の領域１４Ｂと、酸化物半導体層１４の第１の領域１４Ａとが、順に積層されている。そして、この第１の領域１４Ａ上（表面）にソース電極１８及びドレイン電極２０が互いに離間して設置され、更にこれらの上（表面）にゲート絶縁膜２２と、ゲート電極２４とが順に積層されている。 FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention. In the TFT 10 illustrated in FIG. 1A, the second region 14 </ b> B of the oxide semiconductor layer 14 and the first region 14 </ b> A of the oxide semiconductor layer 14 are sequentially stacked on one surface in the thickness direction of the substrate 12. . Then, the source electrode 18 and the drain electrode 20 are spaced apart from each other on the first region 14A (surface), and the gate insulating film 22 and the gate electrode 24 are sequentially stacked on these (surface). ing.
　図１（Ｂ）は、本発明の実施形態に係るＴＦＴであって、トップゲート構造でボトムコンタクト型のＴＦＴの一例を示す模式図である。図１（Ｂ）に示すＴＦＴ３０では、基板１２の厚み方向の一面にソース電極１８及びドレイン電極２０が互いに離間して設置されている。そして、酸化物半導体層１４の第２の領域１４Ｂと、酸化物半導体層１４の第１の領域１４Ａと、ゲート絶縁膜２２と、ゲート電極２４と、が順に積層されている。 FIG. 1B is a schematic view showing an example of a bottom contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention. In the TFT 30 illustrated in FIG. 1B, the source electrode 18 and the drain electrode 20 are provided on one surface in the thickness direction of the substrate 12 so as to be separated from each other. Then, the second region 14B of the oxide semiconductor layer 14, the first region 14A of the oxide semiconductor layer 14, the gate insulating film 22, and the gate electrode 24 are sequentially stacked.
　図１（Ｃ）は、本発明の実施形態に係るＴＦＴであって、ボトムゲート構造でトップコンタクト型のＴＦＴの一例を示す模式図である。図１（Ｃ）に示すＴＦＴ４０では、基板１２の厚み方向の一面にゲート電極２４と、ゲート絶縁膜２２と、酸化物半導体層１４の第１の領域１４Ａと、酸化物半導体層１４の第２の領域１４Ｂと、が順に積層されている。そして、この第２の領域１４Ｂ上（表面）にソース電極１８及びドレイン電極２０が互いに離間して設置されている。 FIG. 1C is a schematic diagram showing an example of a top contact type TFT having a bottom gate structure, which is a TFT according to an embodiment of the present invention. In the TFT 40 illustrated in FIG. 1C, the gate electrode 24, the gate insulating film 22, the first region 14 </ b> A of the oxide semiconductor layer 14, and the second region of the oxide semiconductor layer 14 are formed on one surface in the thickness direction of the substrate 12. The regions 14B are sequentially stacked. The source electrode 18 and the drain electrode 20 are spaced from each other on the second region 14B (surface).
　図１（Ｄ）は、本発明の実施形態に係るＴＦＴであって、ボトムゲート構造でボトムコンタクト型のＴＦＴの一例を示す模式図である。図１（Ｄ）に示すＴＦＴ５０では、基板１２の厚み方向の一面にゲート電極２４と、ゲート絶縁膜２２と、が順に積層されている。そして、このゲート絶縁膜２２の表面にソース電極１８及びドレイン電極２０が互いに離間して設置され、更にこれらの上（表面）に、酸化物半導体層１４の第１の領域１４Ａと、酸化物半導体層１４の第２の領域１４Ｂと、が順に積層されている。 FIG. 1D is a schematic view showing an example of a bottom contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention. In the TFT 50 illustrated in FIG. 1D, the gate electrode 24 and the gate insulating film 22 are sequentially stacked on one surface of the substrate 12 in the thickness direction. Then, the source electrode 18 and the drain electrode 20 are disposed on the surface of the gate insulating film 22 so as to be separated from each other, and further on the (surface) thereof, the first region 14A of the oxide semiconductor layer 14 and the oxide semiconductor The second region 14B of the layer 14 is sequentially stacked.
　なお、本実施形態に係るＴＦＴは、上記以外にも、様々な構成をとることが可能であり、適宜、酸化物半導体層上に保護層や基板上に絶縁層等を備える構成であってもよい。 Note that the TFT according to this embodiment can have various configurations other than the above, and may have a configuration including a protective layer over an oxide semiconductor layer, an insulating layer over a substrate, and the like as appropriate. Good.
　以下、各構成要素について詳述する。なお、代表例として図１（Ｃ）に示すボトムゲート構造でトップコンタクト型のＴＦＴ４０について具体的に説明するが、他の形態のＴＦＴについても同様に下記の材料や厚み等を適用することができる。 Hereinafter, each component will be described in detail. Note that a top contact type TFT 40 having a bottom gate structure shown in FIG. 1C is specifically described as a representative example, but the following materials, thicknesses, and the like can be similarly applied to other types of TFTs. .
＜ＴＦＴの詳細構成＞
－基板－
　ＴＦＴ４０を形成するための基板１２の形状、構造、大きさ等については特に制限はなく、目的に応じて適宜選択することができる。基板１２の構造は単層構造であってもよいし、積層構造であってもよい。基板１２としては、例えば、ガラスやＹＳＺ（イットリウム安定化ジルコニウム）等の無機材料、ポリエチレンテレフタレートやポリエチレンナフタレート等の樹脂、或いは粘土鉱物や雲母派生結晶構造を有する粒子との複合プラスチック材料等の樹脂複合材料等から形成される基板を用いることができる。中でも軽量である点、可撓性を有する点から樹脂あるいは樹脂複合材料から形成される基板が好ましい。なお、樹脂基板は、水分や酸素の透過を防止するためのガスバリア層や、樹脂基板の平坦性や下部電極との密着性を向上するためのアンダーコート層等を備えていてもよい。 <Detailed configuration of TFT>
-substrate-
The shape, structure, size, etc. of the substrate 12 for forming the TFT 40 are not particularly limited and can be appropriately selected depending on the purpose. The structure of the substrate 12 may be a single layer structure or a laminated structure. As the substrate 12, for example, an inorganic material such as glass or YSZ (yttrium stabilized zirconium), a resin such as polyethylene terephthalate or polyethylene naphthalate, or a resin such as a composite plastic material with clay mineral or particles having a mica-derived crystal structure A substrate formed of a composite material or the like can be used. Among these, a substrate formed of a resin or a resin composite material is preferable from the viewpoint of light weight and flexibility. Note that the resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion to the lower electrode, and the like.
－ゲート電極－
　ゲート電極２４としては、高い導電性を有するものであれば特に制限なく、例えばＡｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ａｕ、Ａｇ等の金属、Ａｌ－Ｎｄ、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩｎＺｎＯ）等の金属酸化物導電膜等を、単層または２層以上の積層構造として用いることができる。 -Gate electrode-
The gate electrode 24 is not particularly limited as long as it has high conductivity. For example, a metal such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, zinc oxide, indium oxide, A metal oxide conductive film such as indium tin oxide (ITO) or zinc indium oxide (InZnO) can be used as a single layer or a stacked structure of two or more layers.
－ゲート絶縁膜－
　ゲート絶縁膜２２としては、高い絶縁性を有するものが好ましく、例えばＳｉＯ２、ＳｉＮｘ、ＳｉＯＮ、Ａｌ２Ｏ３、Ｙ２Ｏ３、Ｔａ２Ｏ５、ＨｆＯ２等の絶縁膜、またはこれらの化合物を少なくとも二つ以上含む絶縁膜等から構成することができる。 -Gate insulation film-
The gate insulating film 22 is preferably one having high insulation properties, for example, an insulating film such as SiO 2 , SiNx, SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , HfO 2 , or a compound thereof. Can be made of an insulating film or the like containing at least two.
－酸化物半導体層－
　酸化物半導体層１４は、Ｉｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）（ａ＞０，ｂ＞０，ｃ＞０，ｄ＞０，ａ＋ｂ＋ｃ＝１，以降ＩｎＳｎＺｎＯ膜と略す場合がある）を含む第１の領域１４Ａと、当該第１の領域１４Ａよりもゲート電極２４から遠い側に配置されており、Ｉｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）（ｅ＞０，ｆ＞０，ｇ＞０，ｈ＞０，ｅ＋ｆ＋ｇ＝１，以降ＩｎＧａＺｎＯ膜と略す場合がある）を含む第２の領域１４Ｂと、を有する。 -Oxide semiconductor layer-
The oxide semiconductor layer 14 is In (a) Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0, a + b + c = 1, hereinafter abbreviated as InSnZnO film) The first region 14A including the first region 14A and the first region 14A farther from the gate electrode 24 than the first region 14A. In (e) Ga (f) Zn (g) O (h) (e ) > 0, f> 0, g> 0, h> 0, e + f + g = 1, and may be abbreviated as InGaZnO film hereinafter).
　なお、第２の領域１４Ｂは、ゲート電極２４から遠い側に配置されており、第１の領域１４Ａよりも電気伝導度が低いことが好ましい。
　上記「電気伝導度」とは、物質の電気伝導のしやすさを表す物性値であり、物質のキャリア濃度ｎ、電気素量をｅ、キャリア移動度μとするとｄｒｕｄｅモデルを仮定した場合、物質の電気伝導度σは以下の式で表される。
　　　σ＝ｎｅμ
　第１の領域１４Ａ、又は第２の領域１４Ｂがｎ型半導体である時キャリアは電子であり、キャリア濃度とは電子キャリア濃度を、キャリア移動度とは電子移動度を示す。同様に第１の領域１４Ａ、又は第２の領域１４Ｂがｐ型半導体ではキャリアは正孔であり、キャリア濃度とは、正孔キャリア濃度を、キャリア移動度とは正孔移動度を示す。尚、物質のキャリア濃度とキャリア移動度は、ホール測定により求めることができる。
　電気伝導度の求め方は、厚みが分かっている膜の比抵抗を測定することにより、膜の電気伝導度を求めることができる。半導体の電気伝導度は温度より変化するが、本文記載の電気伝導度は、室温（２０℃）での電気伝導度を示す。
　なお、第１の領域１４Ａ及び第２の領域１４Ｂの組成は、それぞれ単膜としては蛍光Ｘ線分析やＩＣＰ発光分析、積層膜としては例えば二次イオン質量分析（ＳＩＭＳ）を用いる事で認定する事が出来る。 Note that the second region 14B is disposed on the side far from the gate electrode 24, and preferably has lower electrical conductivity than the first region 14A.
The above “electrical conductivity” is a physical property value indicating the ease of electric conduction of a substance, and assuming a drude model assuming that the carrier concentration n of the substance is e, the elementary charge is e, and the carrier mobility is μ, Is represented by the following equation.
σ = neμ
When the first region 14A or the second region 14B is an n-type semiconductor, the carriers are electrons, the carrier concentration indicates the electron carrier concentration, and the carrier mobility indicates the electron mobility. Similarly, in the case where the first region 14A or the second region 14B is a p-type semiconductor, the carriers are holes, the carrier concentration indicates the hole carrier concentration, and the carrier mobility indicates the hole mobility. The carrier concentration and carrier mobility of the substance can be obtained by Hall measurement.
The electric conductivity can be obtained by measuring the specific resistance of the film whose thickness is known, thereby obtaining the electric conductivity of the film. Although the electrical conductivity of a semiconductor varies with temperature, the electrical conductivity described in the text indicates the electrical conductivity at room temperature (20 ° C.).
Note that the composition of the first region 14A and the second region 14B is recognized by using, for example, fluorescent X-ray analysis or ICP emission analysis as a single film, and secondary ion mass spectrometry (SIMS) as a laminated film, for example. I can do it.
　以上の酸化物半導体層１４を有する本実施形態のＴＦＴ４０は、２０ｃｍ２／Ｖｓ超の高い移動度と、波長４２０ｎｍの光照射に対して閾値シフト量の絶対値｜ΔＶｔｈ｜が１Ｖ以下となる高い光安定性と、を両立することができる。
　具体的に、第２の領域１４Ｂよりも電気伝導度が高いことで所謂「キャリア走行層」となる第１の領域１４ＡにＩｎＳｎＺｎＯ膜を用いることで２０ｃｍ２／Ｖｓ超の高い移動度が実現できる。なお、第２の領域１４Ｂは、所謂「抵抗層」となる。
　また、本実施形態のＴＦＴでは第１の領域１４ＡをＩｎＳｎＺｎＯ膜としているために、例えば第１の領域１４ＡとしてＩｎＧａＺｎＯ膜を用いた場合と比較して高い光安定性を両立できる。その要因の一つとして、ＩｎＳｎＺｎＯ膜を用いた場合にはＩｎＧａＺｎＯ膜に比べて、極端な組成変調が必要のないＩｎ：Ｓｎ：Ｚｎ＝１．０００：１．０００：１．０００付近の組成においても高移動度化が実現できる事が挙げられる。ＩｎＧａＺｎＯ膜では極めてＩｎ含有量が高い組成領域でしか高移動度を実現する事は困難であったが、ＩｎＧａＺｎＯ膜の酸化物半導体においてはＩｎ：Ｇａ：Ｚｎ＝１．０００：１．０００：１．０００から大きく外れる組成に変調した場合、光安定性が悪化する事が示唆されている。そのため本実施形態においては第１の領域１４ＡとしてＩｎＳｎＺｎＯ膜を用いる事によって高移動度と光安定性を両立する事が可能となっている。 The TFT 40 of the present embodiment having the above oxide semiconductor layer 14 has a high mobility exceeding 20 cm 2 / Vs and a high threshold shift amount absolute value | ΔVth | of 1 V or less with respect to light irradiation with a wavelength of 420 nm. It is possible to achieve both light stability.
Specifically, the mobility higher than 20 cm 2 / Vs can be realized by using an InSnZnO film in the first region 14A serving as a so-called “carrier traveling layer” because the electric conductivity is higher than that of the second region 14B. . The second region 14B is a so-called “resistance layer”.
In addition, since the first region 14A is an InSnZnO film in the TFT of this embodiment, both high light stability can be achieved as compared with the case where an InGaZnO film is used as the first region 14A, for example. As one of the factors, in the case of using an InSnZnO film, the composition in the vicinity of In: Sn: Zn = 1.000: 1.000: 1.000 which does not require extreme compositional modulation as compared with the InGaZnO film. It is also possible to achieve higher mobility. In an InGaZnO film, it was difficult to achieve high mobility only in a composition region having an extremely high In content. However, in an oxide semiconductor of an InGaZnO film, In: Ga: Zn = 1.000: 1.000: 1. It is suggested that the light stability deteriorates when the composition is changed to a composition greatly deviating from .000. Therefore, in this embodiment, it is possible to achieve both high mobility and light stability by using an InSnZnO film as the first region 14A.
　また、酸化物半導体層１４をＩｎＳｎＺｎＯ膜の一層のみで構成したＴＦＴにおいては高移動度と高いスイッチング性能（例えばＯｎ／Ｏｆｆ比が１０６超）を実現する事は困難である。これは比較的ＩｎＳｎＺｎＯ膜のキャリア濃度が高いために、ＩｎＳｎＺｎＯ膜のみではピンチオフが困難であるためである。本実施形態では第１の領域１４Ａと第２の領域１４Ｂの積層構造を用いる事で、高移動度と高いスイッチング性能を実現している。 Further, it is difficult to realize a high mobility and high switching performance (e.g. On / Off ratio is more than 10 6) in the TFT was constituted of only one layer of the oxide semiconductor layer 14 InSnZnO film. This is because the carrier concentration of the InSnZnO film is relatively high, so that pinch-off is difficult only with the InSnZnO film. In the present embodiment, high mobility and high switching performance are realized by using a stacked structure of the first region 14A and the second region 14B.
　また、第１の領域１４ＡをＩｎＧａＺｎＯ膜とし、第２の領域１４ＢをＩｎＳｎＺｎＯ膜とすることも考えられる。しかしながら、この場合、ＩｎＳｎＺｎＯがＩｎＧａＺｎＯと比べて大きな組成変調を行わなくとも広い組成範囲でキャリア濃度が高いため第２の領域１４Ｂのキャリア濃度を十分に抑制する事ができず、第２の領域表面のＩｎＳｎＺｎＯを単膜として測定している状態か、あるいは第１の領域１４Ａに多量のキャリアが流れ込むために、第１の領域１４Ａ（ＩｎＧａＺｎＯ膜）の伝導を観測できたとしても良好なスイッチング特性を示さない事が予想される。 It is also conceivable that the first region 14A is an InGaZnO film and the second region 14B is an InSnZnO film. However, in this case, the carrier concentration in the second region 14B cannot be sufficiently suppressed because InSnZnO has a high carrier concentration in a wide composition range without performing a large compositional modulation as compared with InGaZnO. InSnZnO is measured as a single film, or since a large amount of carriers flow into the first region 14A, even if the conduction of the first region 14A (InGaZnO film) can be observed, good switching characteristics can be obtained. It is expected not to show.
　以上より、本実施形態では、酸化物半導体層１４を第１の領域１４Ａと第２の領域１４Ｂの二層構造とし、第１の領域１４ＡをＩｎＳｎＺｎＯ膜とし、第２の領域１４ＢをＩｎＧａＺｎＯ膜としている。 As described above, in this embodiment, the oxide semiconductor layer 14 has a two-layer structure of the first region 14A and the second region 14B, the first region 14A is an InSnZnO film, and the second region 14B is an InGaZnO film. Yes.
　この酸化物半導体層１４は、非晶質膜又は結晶質膜のいずれであってもよい。ただし、非晶質膜の場合には、低温で成膜可能であるために、可撓性のある基板１２上に好適に形成される。また、非晶質膜の場合には、結晶粒界が存在せず、均一性の高い膜が得られる。なお、酸化物半導体層１４が非晶質膜であるかどうかは、Ｘ線回折測定により確認することができる。即ち、Ｘ線回折測定により、結晶構造を示す明確なピークが検出されなかった場合は、その酸化物半導体層１４は非晶質膜であると判断することができる。 The oxide semiconductor layer 14 may be either an amorphous film or a crystalline film. However, in the case of an amorphous film, since it can be formed at a low temperature, it is preferably formed on the flexible substrate 12. In the case of an amorphous film, a crystal grain boundary does not exist and a highly uniform film can be obtained. Note that whether or not the oxide semiconductor layer 14 is an amorphous film can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer 14 can be determined to be an amorphous film.
　酸化物半導体層１４における第１の領域１４Ａと第２の領域１４Ｂを含めた膜厚（総膜厚）は、特に限定されないが、膜の均一性、及び酸化物半導体層１４中のトータルのキャリア濃度を制御するという観点から１０ｎｍ以上２００ｎｍ以下であることが好ましい。 The film thickness (total film thickness) including the first region 14A and the second region 14B in the oxide semiconductor layer 14 is not particularly limited, but the film uniformity and the total carriers in the oxide semiconductor layer 14 are not limited. From the viewpoint of controlling the concentration, it is preferably 10 nm or more and 200 nm or less.
　酸化物半導体層１４の第１の領域１４Ａは、ＩｎとＳｎとＺｎとＯとを主たる構成元素としていることが好ましい。なお、「主たる構成元素」とは、第１の領域１４Ａの全構成元素に対するＩｎとＳｎとＺｎとＯとの合計割合が９８％以上であることを意味するものとする。したがって、第１の領域１４Ａには後述するようなＭｇ等の他の元素も含んでいてもよい。 The first region 14A of the oxide semiconductor layer 14 preferably includes In, Sn, Zn, and O as main constituent elements. The “main constituent element” means that the total ratio of In, Sn, Zn, and O with respect to all the constituent elements in the first region 14A is 98% or more. Therefore, the first region 14A may also contain other elements such as Mg as described later.
　第１の領域１４Ａは、上述したようにＩｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）を含んでおり、第１の領域１４Ａの組成は、ｃ／（ａ＋ｂ＋ｃ）≧０．２００で表されることが好ましい。ＴＦＴ４０の閾値電圧（Ｖｔｈ）が著しくマイナス側に現れることを抑制できるからである。なお、上記組成は、上述のＩｎとＳｎとＺｎとＯ以外の他の元素は考慮していないが、第１の領域１４Ａが他の元素を非含有であることを示すものではない。以降の組成の表現も同様である。
　また、第１の領域１４Ａの組成は、ｃ／（ａ＋ｂ＋ｃ）≧１／３で表されることがより好ましい。ＴＦＴ４０の閾値電圧を０Ｖよりもプラス側により高くすることができるからである。
　また、第１の領域１４Ａの組成は、ｃ／（ａ＋ｂ＋ｃ）≧０．４００で表されることがさらにより好ましい。ｃ／（ａ＋ｂ＋ｃ）≧０．４００であると閾値電圧がほぼ飽和するため、Ｚｎの組成比率に対する閾値電圧の変動を抑えることができるからである。 As described above, the first region 14A contains In (a) Sn (b) Zn (c) O (d) , and the composition of the first region 14A is c / (a + b + c) ≧ 0.200. It is preferable to be represented by This is because the threshold voltage (Vth) of the TFT 40 can be suppressed from appearing significantly on the negative side. Note that the above composition does not consider other elements other than In, Sn, Zn, and O described above, but does not indicate that the first region 14A does not contain other elements. The same applies to the subsequent compositional expressions.
The composition of the first region 14A is more preferably represented by c / (a + b + c) ≧ 1/3. This is because the threshold voltage of the TFT 40 can be made higher on the plus side than 0V.
It is even more preferable that the composition of the first region 14A is represented by c / (a + b + c) ≧ 0.400. This is because when c / (a + b + c) ≧ 0.400, the threshold voltage is almost saturated, so that fluctuation of the threshold voltage with respect to the Zn composition ratio can be suppressed.
　また、第１の領域１４Ａの組成は、ｃ／（ａ＋ｂ＋ｃ）≦０．７００で表されることが好ましい。ＴＦＴ４０の移動度を３０ｃｍ２／Ｖｓ超とすることができるからである。
　さらに、第１の領域１４Ａの組成は、０．２００≦ｃ／（ａ＋ｂ＋ｃ）≦０．７００であることがより好ましい。波長（λ）４２０ｎｍの光照射に対する閾値シフト量の絶対値｜ΔＶｔｈ｜を０．６Ｖ未満に抑えることができるからである。 The composition of the first region 14A is preferably represented by c / (a + b + c) ≦ 0.700. This is because the mobility of the TFT 40 can be more than 30 cm 2 / Vs.
Furthermore, the composition of the first region 14A is more preferably 0.200 ≦ c / (a + b + c) ≦ 0.700. This is because the absolute value | ΔVth | of the threshold shift amount for light irradiation with a wavelength (λ) of 420 nm can be suppressed to less than 0.6V.
　Ｉｎの組成比に視点を変えて、第１の領域１４Ａの組成は、ａ／（ａ＋ｂ＋ｃ）≧１／３で表されることがより好ましい。ＴＦＴ４０の移動度を４０ｃｍ２／Ｖｓ超とすることができるからである。 More preferably, the composition of the first region 14A is expressed by a / (a + b + c) ≧ 1/3 by changing the viewpoint to the composition ratio of In. This is because the mobility of the TFT 40 can be more than 40 cm 2 / Vs.
　膜厚に視点を変えて、第１の領域１４Ａの膜厚は、５０ｎｍ以下であることが好ましい。ＴＦＴ４０の閾値電圧が著しくマイナス側に現れることを抑制でき、またＳ値の悪化も抑制できるからである。また、第１の領域１４Ａの膜厚は、５ｎｍ以上であることが好ましい。膜の平坦性を高めることができるからである。 Changing the viewpoint to the film thickness, the film thickness of the first region 14A is preferably 50 nm or less. This is because it is possible to suppress the threshold voltage of the TFT 40 from appearing on the minus side and to suppress the deterioration of the S value. The film thickness of the first region 14A is preferably 5 nm or more. This is because the flatness of the film can be improved.
　さらに、第１の領域１４Ａの膜厚は、下記の完全空乏型の理論式（１）～（３）から、１６ｎｍ以下であることが好ましい。なお、各理論式中の記号の意味を表１に示す。表１のパラメータは、T. Kawamura著 1.5-V Operating Fully-Depleted Amorphous Oxide Thin Film Transistors Achieved by 63-mV/decSubthreshold Slope, IEDM08 Digest p.77 (2008)（以下、「IEDM08 Digest p.77 (2008)」とも称する）に記載のものを用いている。 Furthermore, the film thickness of the first region 14A is preferably 16 nm or less from the following fully depleted theoretical formulas (1) to (3). Table 1 shows the meanings of symbols in each theoretical formula. The parameters in Table 1 are as follows. ) ”) Is used.
Figure JPOXMLDOC01-appb-M000001
 
Figure JPOXMLDOC01-appb-M000001
 
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
　（１）及び（３）式を同時に満たすと、完全空乏状態が実現される。この場合にはノーマリーオフ駆動や極めて良好なＳ値を実現する事が可能であると考えられている。
　計算に用いるパラメータによって完全空乏状態を満たす条件は若干異なるものの、特開2007-250987やIEDM08 Digest p.77 (2008)によればＮｅの値は
例えばｔｃｈ=５ｎｍとするとおよそＮｅ≦５×１０１９ｃｍ－３以下となっている。後述する実施例の中で最も高いキャリア濃度を有するのは、第１の領域１４Ａがａ:ｂ:ｃ＝０．４:０．４:０．２の場合であり、キャリア濃度は５×１０１８ｃｍ－３であった。この場合に完全空乏の条件を満たすのは膜厚が１６ｎｍ以下となる。
　したがって、良好なスイッチング特性と低いオフ電流を実現するためには、第１の領域１４Ａの膜厚は１６ｎｍ以下が好ましいことが上記理論式から分かる。 When the expressions (1) and (3) are satisfied at the same time, a fully depleted state is realized. In this case, it is considered that normally-off driving and a very good S value can be realized.
Although conditions satisfying the full depletion state by the parameters used in the calculation is slightly different, JP 2007-250987 and IEDM08 Digest p.77 value of N e according to (2008), for example t ch = 5 nm to the approximately N e ≦ 5 × 10 19 cm −3 or less. In the examples described later, the highest carrier concentration is obtained when the first region 14A is a: b: c = 0.4: 0.4: 0.2, and the carrier concentration is 5 × 10. 18 cm −3 . In this case, the film thickness of 16 nm or less satisfies the condition of complete depletion.
Therefore, it can be seen from the above theoretical formula that the film thickness of the first region 14A is preferably 16 nm or less in order to realize good switching characteristics and low off-state current.
　第１の領域１４Ａの電気伝導度は、好ましくは、１０－６Ｓｃｍ－１以上１０２Ｓｃｍ－１未満である。より好ましくは１０－４Ｓｃｍ－１以上１０２Ｓｃｍ－１未満であり、さらに好ましくは１０－１Ｓｃｍ－１以上１０２Ｓｃｍ－１未満である。 The electric conductivity of the first region 14A is preferably 10 −6 Scm −1 or more and less than 10 2 Scm −1 . More preferably, it is 10 −4 Scm −1 or more and less than 10 2 Scm −1 , and further preferably 10 −1 Scm −1 or more and less than 10 2 Scm −1 .
　一方で、酸化物半導体層１４の第２の領域１４Ｂは、上述したようにＩｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）を含んでいるが、ＩｎとＧａとＺｎとＯとを主たる構成元素としていることが好ましい。なお、「主たる構成元素」とは、第２の領域１４Ｂの全構成元素に対するＩｎとＧａとＺｎとＯとの合計割合が９８％以上であることを意味するものとする。したがって、第２の領域１４Ｂには後述するようなＭｇ等の他の元素も含んでいてもよい。
　また、第２の領域１４Ｂの組成は、ｆ／（ｅ＋ｆ）≦０．８７５で表されることが好ましい。第２の領域１４Ｂの組成がｆ／（ｅ＋ｆ）≦０．８７５で表される組成範囲であれば高い移動度を実現しやすくなるからである。一方で、第２の領域１４Ｂの組成をｅ／（ｅ＋ｆ）＞０．８７５とした場合には第２の領域１４Ｂの抵抗値が比較的高くなるためにオーミックコンタクトの確保が困難となり、高い移動度を得る事は困難となり易い。
　また、第２の領域１４Ｂの組成は、ｆ／（ｅ＋ｆ）＞０．２５０で表されることが好ましい。第２の領域１４Ｂの組成が、ｆ／（ｅ＋ｆ）≦０．２５０であると、第２の領域１４Ｂのキャリア濃度が比較的高い状態であり、第２の領域１４Ｂから第１の領域１４Ａへのキャリア流入の効果が大きくなるため、Ｖｇ－Ｉｄ特性中にｈｕｍｐ効果が生じたり、閾値電圧が大きくマイナス値を取ったりする事がある。そのため、第２の領域１４Ｂの組成はｆ／（ｅ＋ｆ）＞０．２５０で表される事が好ましい。 On the other hand, the second region 14B of the oxide semiconductor layer 14 contains In (e) Ga (f) Zn (g) O (h) as described above, but In, Ga, Zn, and O Is the main constituent element. The “main constituent element” means that the total ratio of In, Ga, Zn, and O with respect to all the constituent elements in the second region 14B is 98% or more. Accordingly, the second region 14B may also contain other elements such as Mg as described later.
The composition of the second region 14B is preferably represented by f / (e + f) ≦ 0.875. This is because high mobility is easily achieved when the composition of the second region 14B is a composition range represented by f / (e + f) ≦ 0.875. On the other hand, when the composition of the second region 14B is e / (e + f)> 0.875, the resistance value of the second region 14B becomes relatively high, so that it is difficult to secure an ohmic contact, and high movement is caused. Getting a degree is likely to be difficult.
Further, the composition of the second region 14B is preferably represented by f / (e + f)> 0.250. When the composition of the second region 14B is f / (e + f) ≦ 0.250, the carrier concentration of the second region 14B is relatively high, and the second region 14B is changed to the first region 14A. Since the effect of carrier inflow increases, the hump effect may occur in the Vg-Id characteristic, or the threshold voltage may be greatly negative. Therefore, the composition of the second region 14B is preferably represented by f / (e + f)> 0.250.
　膜厚に視点を変えて、第２の領域１４Ｂの膜厚は、１０ｎｍ超７０ｎｍ未満であることが好ましい。第２の領域１４Ｂの膜厚が１０ｎｍ超であると、オフ電流の低減やＳ値の劣化の抑制を期待できるからである。また、第２の領域１４Ｂの膜厚が７０ｎｍ未満であると、ソース・ドレイン電極１８，２０と第１の領域１４Ａ間の抵抗が増大することを抑制し、結果的に移動度の低下を抑制することができるからである。 Changing the viewpoint to the film thickness, the film thickness of the second region 14B is preferably more than 10 nm and less than 70 nm. This is because when the film thickness of the second region 14B is more than 10 nm, reduction of off-current and suppression of deterioration of the S value can be expected. Further, when the film thickness of the second region 14B is less than 70 nm, an increase in resistance between the source / drain electrodes 18 and 20 and the first region 14A is suppressed, and consequently a decrease in mobility is suppressed. Because it can be done.
　第２の領域１４Ｂの電気伝導度は、第１の領域１４Ａと同様の範囲を取り得るが、第１の領域１４Ａより低くなるように好ましくは、１０－７Ｓｃｍ－１以上１０１Ｓｃｍ－１未満である。より好ましくは１０－７Ｓｃｍ－１以上１０－１Ｓｃｍ－１未満である。 The electric conductivity of the second region 14B can take the same range as that of the first region 14A, but is preferably lower than the first region 14A by 10 −7 Scm −1 or more and 10 1 Scm −1. Is less than. More preferably, it is 10 −7 Scm −1 or more and less than 10 −1 Scm −1 .
　また、酸化物半導体層のキャリア濃度、言い換えれば電気伝導度の制御は第１の領域１４Ａ及び第２の領域１４Ｂの組成変調によって行う他、成膜時の酸素分圧制御によっても行うことができる。
　酸素濃度の制御は、具体的には第１の領域１４Ａ及び第２の領域１４Ｂにおける成膜時の酸素分圧をそれぞれ制御することによって行う事が出来る。成膜時の酸素分圧を高めれば、キャリア濃度を低減させることが出来、それに伴ってオフ電流の低減が期待できる。一方、成膜時の酸素分圧を低くすれば、キャリア濃度を増大させることが出来、それに伴って電界効果移動度の増大が期待できる。又、例えば第１の領域１４Ａ成膜後に酸素ラジカルやオゾンを照射する処理を施すことによっても膜の酸化を促進し、第１の領域中の酸素欠損量を低減させる事が可能である。 Further, the carrier concentration of the oxide semiconductor layer, in other words, the electric conductivity can be controlled not only by the composition modulation of the first region 14A and the second region 14B, but also by the oxygen partial pressure control at the time of film formation. .
Specifically, the oxygen concentration can be controlled by controlling the oxygen partial pressure during film formation in the first region 14A and the second region 14B, respectively. If the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly. On the other hand, if the oxygen partial pressure during film formation is lowered, the carrier concentration can be increased, and an increase in field effect mobility can be expected accordingly. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after forming the first region 14A, the oxidation of the film can be promoted and the amount of oxygen vacancies in the first region can be reduced.
　また、第１の領域１４Ａ及び第２の領域１４Ｂを含む酸化物半導体層１４のＺｎの一部を、よりバンドギャップの広がる元素イオンをドーピングすることによって、光学バンドギャップ増大に伴う光照射安定性を付与することができる。具体的には、Ｍｇをドーピングすることにより膜のバンドギャップを大きくすることが可能である。例えば、第１の領域１４Ａ及び第２の領域１４Ｂの各領域にＭｇをドープすることで、Ｉｎ、Ｓｎ（又はＧａ）、Ｚｎのみの組成比を制御した系に比べて、積層膜のバンドプロファイルを保ったままバンドギャップの増大が可能である。なお、この場合、第１の領域１４ＡはＩｎＳｎＺｎＯ膜なので、第２の領域１４ＢのＩｎＧａＺｎＯ膜よりも相対的にバンドギャップが狭くなり易いため、第２の領域１４Ｂよりも第１の領域１４ＡにＭｇを多くドープする方が、光照射安定性に寄与するバンドギャップをより効率的に拡大することができるものと考えられる。 Further, by doping a part of Zn in the oxide semiconductor layer 14 including the first region 14A and the second region 14B with element ions having a wider band gap, light irradiation stability accompanying an increase in the optical band gap is achieved. Can be granted. Specifically, the band gap of the film can be increased by doping Mg. For example, the band profile of the laminated film is compared with a system in which the composition ratio of only In, Sn (or Ga), and Zn is controlled by doping Mg in each of the first region 14A and the second region 14B. The band gap can be increased while maintaining In this case, since the first region 14A is an InSnZnO film, the band gap is relatively narrower than that of the InGaZnO film in the second region 14B. Therefore, the Mg in the first region 14A than in the second region 14B. It is considered that doping with a larger amount of can expand the band gap contributing to the light irradiation stability more efficiently.
　有機ＥＬに用いられる青色発光層は波長４５０ｎｍ程度にピークを持つブロードな発光を示すことから、仮に第１の領域１４Ａ及び第２の領域１４Ｂの光学バンドギャップが比較的狭く、その領域に光学吸収を持つ場合には、トランジスタの閾値シフトが起こってしまうという問題が生じる。従って、特に有機ＥＬ駆動用に用いられる薄膜トランジスタとしては、チャネル層に用いる材料のバンドギャップが、より大きいことが好ましい。 Since the blue light emitting layer used in the organic EL exhibits broad light emission having a peak at a wavelength of about 450 nm, the optical band gaps of the first region 14A and the second region 14B are relatively narrow, and optical absorption occurs in that region. In the case of having, there arises a problem that the threshold shift of the transistor occurs. Therefore, it is preferable that the material used for the channel layer has a larger band gap, particularly for a thin film transistor used for driving an organic EL.
　また、第１の領域１４Ａ及び第２の領域１４Ｂのキャリア濃度はカチオンドーピングによっても任意に制御することができる。キャリア濃度を増やしたい際には、相対的に価数の大きなカチオンになりやすい材料（例えばＴｉ、Ｔａ等）をドーピングすればよい。但し、価数の大きいカチオンをドーピングする場合は、酸化物半導体層１４の構成元素数が増えるため、成膜プロセスの単純化、低コスト化の面で不利であることから、酸素濃度（酸素欠損量）により、キャリア濃度を制御することが好ましい。 Further, the carrier concentration of the first region 14A and the second region 14B can be arbitrarily controlled by cation doping. In order to increase the carrier concentration, a material (for example, Ti, Ta, etc.) that tends to be a cation having a relatively large valence may be doped. However, when doping a cation having a large valence, the number of constituent elements of the oxide semiconductor layer 14 is increased, which is disadvantageous in terms of simplifying the film formation process and reducing the cost. The carrier concentration is preferably controlled by the amount).
－ソース・ドレイン電極－
　ソース電極１８およびドレイン電極２０はいずれも高い導電性を有するものであれば特に制限なく、例えばＡｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ａｕ、Ａｇ等の金属、Ａｌ－Ｎｄ、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩｎＺｎＯ）等の金属酸化物導電膜等を、単層または２層以上の積層構造として用いることができる。 -Source / drain electrodes-
The source electrode 18 and the drain electrode 20 are not particularly limited as long as they have high conductivity. For example, metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, and zinc oxide A metal oxide conductive film such as indium oxide, indium tin oxide (ITO), or indium zinc oxide (InZnO) can be used as a single layer or a stacked structure of two or more layers.
＜ＴＦＴの製造方法＞
　次に、本発明の実施形態に係るＴＦＴの製造方法について、代表例として図１（Ｃ）に示すボトムゲート構造でトップコンタクト型のＴＦＴ４０を用いて簡単に説明する。なお、他の形態のＴＦＴの製造方法についても同様に下記の方法を適用することができる。 <TFT manufacturing method>
Next, a TFT manufacturing method according to an embodiment of the present invention will be briefly described using a top contact type TFT 40 having a bottom gate structure shown in FIG. 1C as a representative example. Note that the following method can be similarly applied to the manufacturing method of TFTs of other forms.
　ＴＦＴ４０の製造方法では、まず基板１２を用意し、基板１２の厚み方向の一面にゲート電極２４を形成する。このゲート電極２４の形成方法は、例えば印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等が挙げられる。例えば、スパッタリング法を用いる場合、当該スパッタリング法により電極膜を成膜後、エッチングまたはリフトオフ法により所定の形状にパターンニングすることによって、ゲート電極２４を形成する。この際、ゲート電極２４およびゲート配線を同時にパターンニングすることが好ましい。 In the manufacturing method of the TFT 40, first, the substrate 12 is prepared, and the gate electrode 24 is formed on one surface of the substrate 12 in the thickness direction. Examples of the method for forming the gate electrode 24 include a wet method such as a printing method and a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, and a chemical method such as a CVD method and a plasma CVD method. It is done. For example, when the sputtering method is used, after forming an electrode film by the sputtering method, the gate electrode 24 is formed by patterning into a predetermined shape by an etching or lift-off method. At this time, it is preferable to pattern the gate electrode 24 and the gate wiring simultaneously.
　次いで、ゲート電極２４の表面及び当該ゲート電極２４側にある基板１２の一面にゲート絶縁膜２２を形成する。ゲート絶縁膜２２の形成方法は、ゲート電極２４と同様の形成方法を用いることができる。例えば、スパッタリング法を用いる場合、当該スパッタリング法により絶縁膜を成膜後、エッチングまたはリフトオフ法により所定の形状にパターンニングすることによって、ゲート絶縁膜２２を形成する。 Next, a gate insulating film 22 is formed on the surface of the gate electrode 24 and one surface of the substrate 12 on the gate electrode 24 side. As a method for forming the gate insulating film 22, a method similar to that for the gate electrode 24 can be used. For example, when a sputtering method is used, the gate insulating film 22 is formed by forming an insulating film by the sputtering method and then patterning the insulating film into a predetermined shape by an etching or lift-off method.
　その後、ゲート絶縁膜２２の表面に酸化物半導体層１４を成膜（形成）する成膜工程を行う。
　この酸化物半導体層１４の成膜方法は、ゲート電極２４と同様の方法を用いることができる。中でも、膜厚の制御がし易いという観点から、真空蒸着法、スパッタリング法、イオンプレーティング法、ＣＶＤ又はプラズマＣＶＤ法等の気相成膜法を用いるのが好ましい。気相成膜法の中でも、スパッタリング法、パルスレーザー蒸着法（ＰＬＤ法）がより好ましい。さらに、量産性の観点から、スパッタリング法がさらに好ましい。例えば、ＲＦマグネトロンスパッタリング蒸着法により、真空度及び酸素流量を制御して成膜される。なお、スパッタリング法を用いる場合、所望のカチオン組成になるように調整した複合酸化物ターゲットを用いても良いし、３元共スパッタを用いても良い。 After that, a film forming process for forming (forming) the oxide semiconductor layer 14 on the surface of the gate insulating film 22 is performed.
As a method for forming the oxide semiconductor layer 14, a method similar to that for the gate electrode 24 can be used. Among these, from the viewpoint of easy control of the film thickness, it is preferable to use a vapor deposition method such as a vacuum deposition method, a sputtering method, an ion plating method, a CVD or a plasma CVD method. Among vapor phase film forming methods, sputtering method and pulsed laser deposition method (PLD method) are more preferable. Furthermore, the sputtering method is more preferable from the viewpoint of mass productivity. For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition. Note that when the sputtering method is used, a complex oxide target adjusted to have a desired cation composition may be used, or ternary co-sputtering may be used.
　具体的に、スパッタリング法を用いる場合、酸化物半導体層１４の成膜工程では、Ｉｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）（ａ＞０，ｂ＞０，ｃ＞０，ｄ＞０、ａ＋ｂ＋ｃ＝１）を含む第１の領域１４Ａを、スパッタ成膜室内を第１の酸素分圧／アルゴン分圧として成膜する第１成膜工程と、第１の領域１４Ａよりもゲート電極２４から遠い側に配置され、Ｉｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）（ｅ＞０，ｆ＞０，ｇ＞０，ｈ＞０、ｅ＋ｆ＋ｇ＝１）を含む第２の領域１４Ｂを、上記スパッタ成膜室内を第２の酸素分圧／アルゴン分圧として成膜する第２成膜工程と、を順に行う。ただし、トップゲート型のＴＦＴ１０，ＴＦＴ３０の場合には、第１成膜工程と第２成膜工程の順番は逆になる。 Specifically, in the case where the sputtering method is used, In (a) Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, a first film formation step of forming a first region 14A including d> 0, a + b + c = 1) in the sputter film formation chamber with a first oxygen partial pressure / argon partial pressure, and more than the first region 14A. The first electrode is disposed on the side far from the gate electrode 24 and includes In (e) Ga (f) Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0, e + f + g = 1). The second film forming step of forming the second region 14B with the second oxygen partial pressure / argon partial pressure inside the sputter film forming chamber is sequentially performed. However, in the case of the top gate type TFT 10 and TFT 30, the order of the first film forming process and the second film forming process is reversed.
　この酸化物半導体層１４の成膜工程の際に、第１の酸素分圧／アルゴン分圧が、第２の酸素分圧／アルゴン分圧よりも高いことが好ましい。
　第２の領域１４Ｂのコンタクト抵抗を下げるという効果の他、第１の領域１４Ａの酸素分圧を高める事で、キャリア走行層となり得る第１の領域１４Ａの酸素に関連する欠陥を少なくすることができるからである。これにより、過剰なキャリアを抑制することができ、高いスイッチング特性が得られる。またＩｎＧａＺｎＯを初めとする酸化物半導体系では、酸素欠陥に起因する深い準位が価電子体直上に存在することが言われている。この深い準位のため光安定性が悪化し得るが、酸素分圧を高めてこの準位を抑制すると、組成ほど大きな効果は無いにせよ光安定性を高める効果が期待できる。また、酸素欠陥を減らす事で、イオン化不純物散乱の効果(ドナーとなっているイオン化した酸素欠陥があると散乱源として働く)を抑制できるため、比較的高い移動度が実現しやすくなるものと考える。 In the step of forming the oxide semiconductor layer 14, it is preferable that the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.
In addition to the effect of reducing the contact resistance of the second region 14B, by increasing the oxygen partial pressure of the first region 14A, it is possible to reduce defects related to oxygen in the first region 14A that can be a carrier traveling layer. Because it can. Thereby, excess carriers can be suppressed and high switching characteristics can be obtained. In addition, in an oxide semiconductor system such as InGaZnO, it is said that a deep level due to an oxygen defect exists immediately above a valence body. Although this deep level can degrade the light stability, if this level is suppressed by increasing the oxygen partial pressure, the effect of increasing the light stability can be expected even though the effect is not as great as the composition. In addition, by reducing oxygen defects, the effect of ionized impurity scattering (which acts as a scattering source when there are ionized oxygen defects serving as donors) can be suppressed, so that relatively high mobility is likely to be realized. .
　また、酸化物半導体層１４の成膜工程の間、基板１２を大気に曝さないことが好ましい。すなわち、基板１２を大気に曝すことなく、第１成膜工程と第２成膜工程を連続して行うことが好ましい。不純物が酸化物半導体層１４に混じることを抑制するためである。 In addition, it is preferable not to expose the substrate 12 to the air during the film forming process of the oxide semiconductor layer 14. That is, it is preferable to perform the first film formation step and the second film formation step continuously without exposing the substrate 12 to the atmosphere. This is for preventing impurities from being mixed into the oxide semiconductor layer 14.
　次いで酸化物半導体層１４をパターンニングする。パターンニングはフォトリソグラフィーおよびエッチングにより行うことができる。具体的には、残存させる部分にフォトリソグラフィーによりレジストパターンを形成し、塩酸、硝酸、希硫酸、または燐酸、硝酸および酢酸の混合液等の酸溶液によりエッチングすることによりパターンを形成する。 Next, the oxide semiconductor layer 14 is patterned. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and the pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.
　そして、酸化物半導体層１４の表面にソース・ドレイン電極１８、２０を形成するための金属膜を形成する。ソース・ドレイン電極１８、２０の形成方法は、ゲート電極２４と同様の形成方法を用いることができる。次いで金属膜をエッチングまたはリフトオフ法により所定の形状にパターンニングし、ソース電極１８およびドレイン電極２０を形成する。この際、ソース・ドレイン電極１８、２０および図示しない、これらの電極に接続する配線を同時にパターンニングすることが好ましい。 Then, a metal film for forming the source / drain electrodes 18 and 20 is formed on the surface of the oxide semiconductor layer 14. The method for forming the source / drain electrodes 18 and 20 can be the same as that for the gate electrode 24. Next, the metal film is patterned into a predetermined shape by etching or a lift-off method, and the source electrode 18 and the drain electrode 20 are formed. At this time, it is preferable to pattern the source / drain electrodes 18 and 20 and wiring (not shown) connected to these electrodes simultaneously.
　なお、上記ソース・ドレイン電極形成後或いは成膜工程直後等の酸化物半導体層１４の成膜工程終了後に、３００℃以上の温度でポストアニール処理を行うことが好ましい。ポストアニール処理温度を３００℃以上とすることによって、酸素結合状態に関連する欠陥の構造緩和が起こるために深い欠陥準位の低減が起こり、高い光安定性を実現しやすくなるからである。 In addition, it is preferable to perform post-annealing at a temperature of 300 ° C. or higher after the formation of the oxide semiconductor layer 14 after the formation of the source / drain electrodes or immediately after the film formation. This is because by setting the post-annealing temperature to 300 ° C. or higher, the structure relaxation of defects related to the oxygen-bonded state occurs, so that deep defect levels are reduced and high light stability is easily realized.
　ポストアニール温度は、６００℃未満であることが望ましい。熱処理工程において６００℃以上の温度で処理した場合、第１の領域１４Ａと第２の領域１４Ｂの間でカチオンの相互拡散が起こり、２つの領域が交じりあってしまう虞があるからである。この場合には第１の領域１４Ａだけに伝導キャリアを集中させる事が難しくなる。従って、ポストアニール温度は６００℃未満であることが望ましい。なお、第１の領域１４Ａと第２の領域１４Ｂでのカチオンの相互拡散が起こっているかどうかは、例えば断面ＴＥＭによる分析を行うことで確認できる。 The post-annealing temperature is preferably less than 600 ° C. This is because when the heat treatment is performed at a temperature of 600 ° C. or higher, cation mutual diffusion occurs between the first region 14A and the second region 14B, and the two regions may be mixed. In this case, it is difficult to concentrate conductive carriers only in the first region 14A. Therefore, the post-annealing temperature is desirably less than 600 ° C. Whether or not cation mutual diffusion occurs in the first region 14A and the second region 14B can be confirmed, for example, by performing analysis by a cross-sectional TEM.
　また、ポストアニール中の雰囲気は不活性雰囲気又は酸化性雰囲気にすることが好ましい。特に、酸化性雰囲気であれば、酸化物半導体層中の酸素が抜け難く、余剰キャリアが発生して電気特性バラツキが起こることを抑制できる。ポストアニール時間に特に限定はないが、膜温度が均一になるのに要する時間等を考慮し、少なくとも１０分以上保持することが好ましい。 Also, the atmosphere during post-annealing is preferably an inert atmosphere or an oxidizing atmosphere. In particular, in an oxidizing atmosphere, oxygen in the oxide semiconductor layer is difficult to escape, and generation of surplus carriers and variation in electrical characteristics can be suppressed. Although there is no particular limitation on the post-annealing time, it is preferable to hold it for at least 10 minutes in consideration of the time required for the film temperature to become uniform.
　また、本実施形態のＴＦＴ４０を用いることで、光照射に対する特性劣化を低減するための保護層等を酸化物半導体層１４上に用いることなく、高い移動度と、高い光照射安定性が得られるが、もちろん酸化物半導体層１４に上記の様な保護層を設けてもよい。例えば紫外領域（波長４００ｎｍ以下）の光を吸収、反射するような保護層を設けることで、更に光照射に対する安定性を向上させることが可能である。 In addition, by using the TFT 40 of the present embodiment, high mobility and high light irradiation stability can be obtained without using a protective layer or the like on the oxide semiconductor layer 14 for reducing deterioration in characteristics due to light irradiation. Needless to say, the oxide semiconductor layer 14 may be provided with a protective layer as described above. For example, by providing a protective layer that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less), the stability against light irradiation can be further improved.
　以上の手順により、図１（Ｃ）に示すようなボトムゲート構造でトップコンタクト型のＴＦＴ４０を作製することができる。
　以上の製造方法によれば、第１の領域１４ＡのＩｎＳｎＺｎＯ膜や第２の領域１４ＢのＩｎＧａＺｎＯ膜は低温（例えば４００℃以下）で成膜が可能なため、基板１２も樹脂基板等を用いればＴＦＴ４０全体としてフレキシブルなＴＦＴデバイスの作製が可能となる。 Through the above procedure, a top contact type TFT 40 with a bottom gate structure as shown in FIG. 1C can be manufactured.
According to the above manufacturing method, the InSnZnO film in the first region 14A and the InGaZnO film in the second region 14B can be formed at a low temperature (for example, 400 ° C. or lower). A flexible TFT device can be manufactured as the entire TFT 40.
２．変形例
　なお、本発明を特定の実施形態について詳細に説明したが、本発明はかかる実施形態に限定されるものではなく、本発明の範囲内にて他の種々の実施形態が可能であることは当業者にとって明らかであり、例えば上述の複数の実施形態は、適宜、組み合わせて実施可能である。 2. Although the present invention has been described in detail with respect to specific embodiments, the present invention is not limited to such embodiments, and various other embodiments are possible within the scope of the present invention. Will be apparent to those skilled in the art. For example, the above-described plurality of embodiments can be implemented in appropriate combination.
　例えば、本実施形態に係るＴＦＴは、上記以外にも、様々な構成をとることが可能であり、例えば基板１２上に絶縁層を設けたり、ソース電極１８とドレイン電極２０との間から露出する酸化物半導体層１４の面上に、単層の保護層や複数層の保護層を設けたりすることもできる。 For example, the TFT according to this embodiment can have various configurations other than the above. For example, an insulating layer is provided on the substrate 12 or exposed from between the source electrode 18 and the drain electrode 20. A single protective layer or a plurality of protective layers may be provided on the surface of the oxide semiconductor layer 14.
３．応用
　以上で説明した本実施形態のＴＦＴの用途には特に限定はないが、例えば電気光学装置（例えば液晶表示装置、有機ＥＬ（Ｅｌｅｃｔｒｏ Ｌｕｍｉｎｅｓｃｅｎｃｅ）表示装置、無機ＥＬ表示装置等の表示装置、等）における駆動素子、特に大面積デバイスに用いる場合に好適である。
　さらに本実施形態のＴＦＴは、樹脂基板を用いた低温プロセスで作製可能なデバイスに特に好適であり(例えばフレキシブルディスプレイ等)、Ｘ線センサなどの各種センサ、ＭＥＭＳ(Ｍｉｃｒｏ Ｅｌｅｃｔｒｏ Ｍｅｃｈａｎｉｃａｌ Ｓｙｓｔｅｍ）等、種々の電子デバイスにおける駆動素子(駆動回路)として、好適に用いられるものである。 3. Applications There are no particular limitations on the application of the TFT of the present embodiment described above. For example, electro-optical devices (for example, display devices such as liquid crystal display devices, organic EL (Electro Luminescence) display devices, inorganic EL display devices, etc.) It is suitable for use in a driving element in the above, particularly for a large area device.
Furthermore, the TFT of this embodiment is particularly suitable for a device that can be manufactured by a low-temperature process using a resin substrate (for example, a flexible display), and various sensors such as an X-ray sensor, MEMS (Micro Electro Mechanical System), and the like. It is suitably used as a drive element (drive circuit) in this electronic device.
４．電気光学装置及びセンサ 4). Electro-optical device and sensor
　本実施形態の電気光学装置又はセンサは、前述の本発明のＴＦＴを備えて構成される。
　電気光学装置の例としては、表示装置（例えば液晶表示装置、有機ＥＬ表示装置、無機ＥＬ表示装置、等）がある。
　センサの例としては、ＣＣＤ（Ｃｈａｒｇｅ　Ｃｏｕｐｌｅｄ　Ｄｅｖｉｃｅ）又はＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）等のイメージセンサや、Ｘ線センサ等が好適である。
　本実施形態の電気光学装置又はセンサは、低い消費電力により良好な特性を示す。ここで言うところの特性とは、電気光学装置（表示装置）の場合には表示特性、センサの場合には感度特性を示す。
　以下、本発明によって製造される電界効果型トランジスタを備えた電気光学装置又はセンサの代表例として、液晶表示装置、有機ＥＬ表示装置、Ｘ線センサについて説明する。 The electro-optical device or sensor according to this embodiment includes the above-described TFT of the present invention.
Examples of electro-optical devices include display devices (eg, liquid crystal display devices, organic EL display devices, inorganic EL display devices, etc.).
As an example of the sensor, an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), an X-ray sensor, or the like is suitable.
The electro-optical device or sensor of the present embodiment exhibits good characteristics with low power consumption. The characteristics referred to here indicate display characteristics in the case of an electro-optical device (display device), and sensitivity characteristics in the case of a sensor.
Hereinafter, a liquid crystal display device, an organic EL display device, and an X-ray sensor will be described as representative examples of an electro-optical device or sensor including a field effect transistor manufactured according to the present invention.
５．液晶表示装置
　図２に、本発明の電気光学装置の一実施形態の液晶表示装置について、その一部分の概略断面図を示し、図３にその電気配線の概略構成図を示す。 5. Liquid Crystal Display Device FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention, and FIG.
　図２に示すように、本実施形態の液晶表示装置１００は、基板１２、図１（Ａ）に示したトップゲート構造でトップコンタクト型のＴＦＴ１０と、ＴＦＴ１０のパッシベーション層１０２で保護されたゲート電極２４上に画素下部電極１０４およびその対向上部電極１０６で挟まれた液晶層１０８と、各画素に対応させて異なる色を発色させるためのＲＧＢカラーフィルタ１１０とを備え、ＴＦＴ１０の基板１２側およびＲＧＢカラーフィルタ１１０上にそれぞれ偏光板１１２ａ、１１２ｂを備えた構成である。 As shown in FIG. 2, the liquid crystal display device 100 of this embodiment includes a substrate 12, a top contact type TFT 10 having the top gate structure shown in FIG. 1A, and a gate electrode protected by a passivation layer 102 of the TFT 10. 24 includes a liquid crystal layer 108 sandwiched between the pixel lower electrode 104 and the counter upper electrode 106, and an RGB color filter 110 for developing different colors corresponding to each pixel. In this configuration, polarizing plates 112a and 112b are provided on the color filter 110, respectively.
　また、図３に示すように、本実施形態の液晶表示装置１００は、互いに平行な複数のゲート配線１１２と、該ゲート配線１１２と交差する、互いに平行なデータ配線１１４とを備えている。ここでゲート配線１１２とデータ配線１１４は電気的に絶縁されている。ゲート配線１１２とデータ配線１１４との交差部付近に、ＴＦＴ１０が備えられている。 Further, as shown in FIG. 3, the liquid crystal display device 100 of the present embodiment includes a plurality of gate lines 112 parallel to each other and data lines 114 parallel to each other intersecting the gate lines 112. Here, the gate wiring 112 and the data wiring 114 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 112 and the data wiring 114.
　図２及び図３に示すように、ＴＦＴ１０のゲート電極２４は、ゲート配線１１２に接続されており、ＴＦＴ１０のソース電極１８はデータ配線１１４に接続されている。また、ＴＦＴ１０のドレイン電極２０はゲート絶縁膜２２に設けられたコンタクトホール１１６を介して（コンタクトホール１１６に導電体が埋め込まれて）画素下部電極１０４に接続されている。この画素下部電極１０４は、接地された対向上部電極１０６とともにキャパシタ１１８を構成している。 2 and 3, the gate electrode 24 of the TFT 10 is connected to the gate wiring 112, and the source electrode 18 of the TFT 10 is connected to the data wiring 114. The drain electrode 20 of the TFT 10 is connected to the pixel lower electrode 104 through a contact hole 116 provided in the gate insulating film 22 (a conductor is embedded in the contact hole 116). The pixel lower electrode 104 forms a capacitor 118 together with the grounded counter upper electrode 106.
　図２に示した本実施形態の液晶装置においては、トップゲート構造のＴＦＴ１０を備えるものとしたが、本発明の表示装置である液晶装置において用いられるＴＦＴはトップゲート構造に限定されることなく、ボトムゲート構造のＴＦＴであってもよい。 In the liquid crystal device of the present embodiment shown in FIG. 2, the TFT 10 having the top gate structure is provided. However, the TFT used in the liquid crystal device which is the display device of the present invention is not limited to the top gate structure. A TFT having a bottom gate structure may be used.
　本発明により製造されるＴＦＴ１０は、高い移動度を有するため、液晶表示装置において高精細、高速応答、高コントラスト等の高品位表示が可能となり、大画面化にも適している。また、酸化物半導体層１４のＩｎＧａＺｎＯ膜やＩｎＳｎＺｎＯ膜が非晶質である場合には素子特性のバラツキを抑えることができ、大画面でムラのない優れた表示品位が実現される。しかも特性シフトが少ないため、ゲート電圧を低減でき、ひいては表示装置の消費電力を低減できる。また、本発明によると、半導体層として低温（例えば２００℃以下）での成膜が可能な非晶質ＩｎＧａＺｎＯ膜やＩｎＳｎＺｎＯ膜を用いて薄膜トランジスタを作製することができるため、基板としては樹脂基板（プラスチック基板）を用いることができる。従って、本発明によれば、表示品質に優れフレキシブルな液晶表示装置を提供することができる。 Since the TFT 10 manufactured according to the present invention has a high mobility, a high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen. In addition, when the InGaZnO film or the InSnZnO film of the oxide semiconductor layer 14 is amorphous, variation in element characteristics can be suppressed, and excellent display quality without unevenness can be realized on a large screen. In addition, since the characteristic shift is small, the gate voltage can be reduced, and thus the power consumption of the display device can be reduced. In addition, according to the present invention, a thin film transistor can be manufactured using an amorphous InGaZnO film or an InSnZnO film that can be formed at a low temperature (for example, 200 ° C. or lower) as a semiconductor layer. A plastic substrate) can be used. Therefore, according to the present invention, a flexible liquid crystal display device excellent in display quality can be provided.
６．有機ＥＬ表示装置
　図４に、本発明の電気光学装置の一実施形態のアクティブマトリックス方式の有機ＥＬ表示装置について、その一部分の概略断面図を示し、図５にその電気配線の概略構成図を示す。 6). Organic EL Display Device FIG. 4 is a schematic sectional view of a part of an active matrix type organic EL display device according to an embodiment of the electro-optical device of the present invention, and FIG. 5 is a schematic configuration diagram of the electric wiring. .
　有機ＥＬ表示装置の駆動方式には、単純マトリックス方式とアクティブマトリックス方式の２種類がある。単純マトリックス方式は低コストで作製できるメリットがあるが、走査線を１本ずつ選択して画素を発光させることから、走査線数と走査線あたりの発光時間は反比例する。そのため高精細化、大画面化が困難となっている。アクティブマトリックス方式は画素ごとにトランジスタやキャパシタを形成するため製造コストが高くなるが、単純マトリックス方式のように走査線数を増やせないという問題はないため高精細化、大画面化に適している。 There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at low cost. However, since the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size. The active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel. However, since there is no problem that the number of scanning lines cannot be increased unlike the simple matrix method, it is suitable for high definition and large screen.
　本実施形態のアクティブマトリックス方式の有機ＥＬ表示装置２００は、図１（Ａ）に示したトップゲート構造のＴＦＴ１０が、パッシベーション層２０２を備えた基板１２上に、駆動用ＴＦＴ２０４およびスイッチング用ＴＦＴ２０６として備えられ、駆動用ＴＦＴ２０４およびスイッチング用ＴＦＴ２０６上に下部電極２０８および上部電極２１０に挟まれた有機発光層２１２から形成される有機ＥＬ発光素子２１４を備え、上面もパッシベーション層２１６により保護された構成となっている。 In the active matrix organic EL display device 200 of this embodiment, the top gate TFT 10 shown in FIG. 1A is provided as a driving TFT 204 and a switching TFT 206 on a substrate 12 having a passivation layer 202. In addition, an organic EL light emitting element 214 formed of an organic light emitting layer 212 sandwiched between the lower electrode 208 and the upper electrode 210 is provided on the driving TFT 204 and the switching TFT 206, and the upper surface is also protected by the passivation layer 216. ing.
　また、図４及び図５に示すように、本実施形態の有機ＥＬ表示装置２００は、互いに平行な複数のゲート配線２２０と、該ゲート配線２２０と交差する、互いに平行なデータ配線２２２および駆動配線２２４とを備えている。ここで、ゲート配線２２０とデータ配線２２２、駆動配線２２４とは電気的に絶縁されている。スイッチング用ＴＦＴ２０６のゲート電極２４は、ゲート配線２２０に接続されており、スイッチング用ＴＦＴ２０６のソース電極１８はデータ配線２２２に接続されている。また、スイッチング用ＴＦＴ２０６のドレイン電極２０は駆動用ＴＦＴ２０４ゲート電極２４に接続されるとともに、キャパシタ２２６を用いることで駆動用ＴＦＴ１０ａをオン状態に保つ。駆動用ＴＦＴ２０４のソース電極１８は駆動配線２２４に接続され、ドレイン電極２０は有機ＥＬ発光素子２１４に接続される。 As shown in FIGS. 4 and 5, the organic EL display device 200 of this embodiment includes a plurality of gate wirings 220 that are parallel to each other, and data wirings 222 and driving wirings that are parallel to each other and intersect the gate wirings 220. 224. Here, the gate wiring 220, the data wiring 222, and the drive wiring 224 are electrically insulated. The gate electrode 24 of the switching TFT 206 is connected to the gate wiring 220, and the source electrode 18 of the switching TFT 206 is connected to the data wiring 222. Further, the drain electrode 20 of the switching TFT 206 is connected to the driving TFT 204 gate electrode 24, and the driving TFT 10 a is kept on by using the capacitor 226. The source electrode 18 of the driving TFT 204 is connected to the driving wiring 224, and the drain electrode 20 is connected to the organic EL light emitting element 214.
　図４に示した本実施形態の有機ＥＬ装置においては、トップゲート構造の駆動用ＴＦＴ２０４およびスイッチング用ＴＦ２０６を備えるものとしたが、本発明の表示装置である有機ＥＬ装置において用いられるＴＦＴは、トップゲート構造に限定されることなく、ボトムゲート構造のＴＦＴであってもよい。 The organic EL device of this embodiment shown in FIG. 4 includes the top-gate driving TFT 204 and the switching TF 206. However, the TFT used in the organic EL device which is the display device of the present invention is the top. The TFT is not limited to the gate structure and may be a bottom gate TFT.
　本実施形態により製造されるＴＦＴ１０は、高い移動度を有するため、低消費電力で且つ高品位な表示が可能となる。また、本実施形態によると、酸化物半導体層１４として低温（例えば２００℃以下）での成膜が可能な非晶質ＩｎＧａＺｎＯ膜やＩｎＳｎＺｎＯ膜を用いて薄膜トランジスタを作製することができるため、基板として樹脂基板（プラスチック基板）を用いることができる。従って、本実施形態によれば、表示品質に優れフレキシブルな有機ＥＬ表示装置２００を提供することができる。 Since the TFT 10 manufactured according to this embodiment has high mobility, low power consumption and high-quality display can be achieved. In addition, according to this embodiment, a thin film transistor can be manufactured using an amorphous InGaZnO film or an InSnZnO film that can be formed at a low temperature (for example, 200 ° C. or less) as the oxide semiconductor layer 14. A resin substrate (plastic substrate) can be used. Therefore, according to the present embodiment, it is possible to provide a flexible organic EL display device 200 with excellent display quality.
　なお、図４に示した有機ＥＬ表示装置２００において、上部電極２１０を透明電極としてトップエミッション型としてもよいし、下部電極２０８およびＴＦＴの各電極を透明電極とすることによりボトムエミッション型としてもよい。 In the organic EL display device 200 shown in FIG. 4, the upper electrode 210 may be a top emission type with a transparent electrode, or the bottom electrode 208 and each electrode of the TFT may be a bottom electrode type by using a transparent electrode. .
７．Ｘ線センサ
　図６に、本発明のセンサの一実施形態であるＸ線センサについて、その一部分の概略断面図を示し、図７にその電気配線の概略構成図を示す。 7). X-ray sensor FIG. 6 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention, and FIG. 7 shows a schematic configuration diagram of its electric wiring.
　図６は、より具体的にはＸ線センサアレイの一部を拡大した概略断面図である。本実施形態のＸ線センサ３００は基板１２上に形成されたＴＦＴ１０およびキャパシタ３１０と、キャパシタ３１０上に形成された電荷収集用電極３０２と、Ｘ線変換層３０４と、上部電極３０６とを備えて構成される。ＴＦＴ１０上にはパッシベーション膜３０８が設けられている。 FIG. 6 is a schematic cross-sectional view in which a part of the X-ray sensor array is enlarged more specifically. The X-ray sensor 300 of this embodiment includes the TFT 10 and the capacitor 310 formed on the substrate 12, the charge collection electrode 302 formed on the capacitor 310, the X-ray conversion layer 304, and the upper electrode 306. Composed. A passivation film 308 is provided on the TFT 10.
　キャパシタ３１０は、キャパシタ用下部電極３１２とキャパシタ用上部電極３１４とで絶縁膜３１６を挟んだ構造となっている。キャパシタ用上部電極３１４は絶縁膜３１６に設けられたコンタクトホール３１８を介し、ＴＦＴ１０のソース電極１８およびドレイン電極２０のいずれか一方（図６においてはドレイン電極２０）と接続されている。 The capacitor 310 has a structure in which an insulating film 316 is sandwiched between a capacitor lower electrode 312 and a capacitor upper electrode 314. The capacitor upper electrode 314 is connected to one of the source electrode 18 and the drain electrode 20 (the drain electrode 20 in FIG. 6) of the TFT 10 through a contact hole 318 provided in the insulating film 316.
　電荷収集用電極３０２は、キャパシタ３１０におけるキャパシタ用上部電極３１４上に設けられており、キャパシタ用上部電極３１４に接している。
　Ｘ線変換層３０４はアモルファスセレンを含む層であり、ＴＦＴ１０およびキャパシタ３１０を覆うように設けられている。
　上部電極３０６はＸ線変換層３０４上に設けられており、Ｘ線変換層３０４に接している。 The charge collection electrode 302 is provided on the capacitor upper electrode 314 in the capacitor 310 and is in contact with the capacitor upper electrode 314.
The X-ray conversion layer 304 is a layer containing amorphous selenium and is provided so as to cover the TFT 10 and the capacitor 310.
The upper electrode 306 is provided on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.
　図７に示すように、本実施形態のＸ線センサ３００は、互いに平行な複数のゲート配線３２０と、ゲート配線３２０と交差する、互いに平行な複数のデータ配線３２２とを備えている。ここでゲート配線３２０とデータ配線３２２は電気的に絶縁されている。ゲート配線３２０とデータ配線３２２との交差部付近に、ＴＦＴ１０が備えられている。 As shown in FIG. 7, the X-ray sensor 300 of this embodiment includes a plurality of gate wirings 320 that are parallel to each other and a plurality of data wirings 322 that intersect with the gate wirings 320 and are parallel to each other. Here, the gate wiring 320 and the data wiring 322 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 320 and the data wiring 322.
　ＴＦＴ１０のゲート電極２４は、ゲート配線３２０に接続されており、ＴＦＴ１０のソース電極１８はデータ配線３２２に接続されている。また、ＴＦＴ１０のドレイン電極２０は電荷収集用電極３０２に接続されており、さらにこの電荷収集用電極３０２は、キャパシタ３１０に接続されている。 The gate electrode 24 of the TFT 10 is connected to the gate wiring 320, and the source electrode 18 of the TFT 10 is connected to the data wiring 322. The drain electrode 20 of the TFT 10 is connected to the charge collecting electrode 302, and the charge collecting electrode 302 is connected to the capacitor 310.
　本実施形態のＸ線センサ３００において、Ｘ線は図６中、上部（上部電極３０６側）から照射され、Ｘ線変換層３０４で電子－正孔対を生成する。このＸ線変換層３０４に上部電極３０６によって高電界を印加しておくことにより、生成した電荷はキャパシタ３１０に蓄積され、ＴＦＴ１０を順次走査することによって読み出される。 In the X-ray sensor 300 of this embodiment, X-rays are irradiated from the upper part (upper electrode 306 side) in FIG. 6, and electron-hole pairs are generated in the X-ray conversion layer 304. By applying a high electric field to the X-ray conversion layer 304 by the upper electrode 306, the generated charge is accumulated in the capacitor 310 and read out by sequentially scanning the TFT 10.
　本実施形態のＸ線センサ３００は、移動度及びオン電流が高く、感度特性に優れたＴＦＴ１０を備えるため、Ｓ／Ｎが高く、大画面化に適している。また、感度特性に優れているため、Ｘ線デジタル撮影装置に用いた場合に広ダイナミックレンジの画像が得られる。特に本実施形態のＸ線デジタル撮影装置は、静止画撮影のみ可能なものではなく、動画による透視と静止画の撮影が１台で行えるＸ線デジタル撮影装置に用いるのが好適である。さらにＴＦＴ１０におけるＩｎＧａＺｎＯ膜やＩｎＳｎＺｎＯ膜が非晶質である場合には均一性に優れた画像が得られる。 The X-ray sensor 300 of the present embodiment includes a TFT 10 with high mobility and on-current and excellent sensitivity characteristics, and thus has a high S / N and is suitable for a large screen. Moreover, since it has excellent sensitivity characteristics, an image with a wide dynamic range can be obtained when used in an X-ray digital imaging apparatus. In particular, the X-ray digital imaging apparatus according to the present embodiment is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when the InGaZnO film or InSnZnO film in the TFT 10 is amorphous, an image with excellent uniformity can be obtained.
　なお、図６に示した本実施形態のＸ線センサ３００においては、トップゲート構造のＴＦＴ１０を備えるものとしたが、本発明のセンサにおいて用いられるＴＦＴはトップゲート構造に限定されることなく、ボトムゲート構造のＴＦＴであってもよい。 In the X-ray sensor 300 of the present embodiment shown in FIG. 6, the TFT 10 having the top gate structure is provided. However, the TFT used in the sensor of the present invention is not limited to the top gate structure, but the bottom gate structure. A TFT having a gate structure may be used.
　以下に実施例を説明するが、本発明はこれら実施例により何ら限定されるものではない。 Examples will be described below, but the present invention is not limited to these examples.
＜ＴＦＴ特性に対する第１の領域組成依存性＞
－実施例１～１０及び比較例１～４－
　まず、第１の領域の組成依存性について以下のような実施例１～１０及び比較例１～４に係るボトムゲート構造でトップコンタクト型のＴＦＴを作製することで検証した。 <Dependence of first region composition on TFT characteristics>
Examples 1 to 10 and Comparative Examples 1 to 4
First, the composition dependency of the first region was verified by fabricating a top contact type TFT with a bottom gate structure according to Examples 1 to 10 and Comparative Examples 1 to 4 as described below.
　図８（Ａ）は実施例及び比較例のＴＦＴの平面図であり、図８（Ｂ）は図８（Ａ）に示すＴＦＴのＡ－Ａ線矢視断面図である。 FIG. 8A is a plan view of the TFTs of the example and the comparative example, and FIG. 8B is a cross-sectional view of the TFT shown in FIG.
　まず、実施例１～１０及び比較例１～４では、図８（Ａ）及び図８（Ｂ）に示すように、基板として熱酸化膜５０４付ｐ型Ｓｉ基板５０２（１ｉｎｃｈ角×１ｍｍ、厚み：５２５μｍｔ、熱酸化膜（ＳｉＯ２）：１００ｎｍｔ）を用い、熱酸化膜５０４をゲート絶縁膜として用いる簡易型のＴＦＴ５００を作製した。
　具体的には、熱酸化膜付ｐ型Ｓｉ基板５０２上に、以下表２に示すように、実施例及び比較例毎に組成変調を行って酸化物半導体層の第１の領域５０６を厚み５ｎｍとしてスパッタ成膜した。この成膜条件は、成膜時到達真空度：６×１０－６Ｐａ、成膜時圧力：４．４×１０－１Ｐａ、成膜温度：室温、酸素分圧／アルゴン分圧：０．０６７で実施例及び比較例全てにおいて共通にした。なお、比較例１のみは、第１の領域５０６がＩｎＳｎＺｎＯ膜ではなく、ＩｎＧａＺｎＯ膜となっている。 First, in Examples 1 to 10 and Comparative Examples 1 to 4, as shown in FIGS. 8A and 8B, a p-type Si substrate 502 with a thermal oxide film 504 (1 inch angle × 1 mm, thickness) as a substrate. : 525 μmt, thermal oxide film (SiO 2 ): 100 nmt), and a simple TFT 500 using the thermal oxide film 504 as a gate insulating film was manufactured.
Specifically, on the p-type Si substrate with thermal oxide film 502, as shown in Table 2 below, composition modulation is performed for each of the examples and the comparative examples, so that the first region 506 of the oxide semiconductor layer has a thickness of 5 nm. As a sputtering film formation. The film formation conditions were as follows: ultimate vacuum during film formation: 6 × 10 −6 Pa, pressure during film formation: 4.4 × 10 −1 Pa, film formation temperature: room temperature, oxygen partial pressure / argon partial pressure: 0.00. 067 was common to all examples and comparative examples. In Comparative Example 1 only, the first region 506 is not an InSnZnO film but an InGaZnO film.
Figure JPOXMLDOC01-appb-T000005
 
Figure JPOXMLDOC01-appb-T000005
 
　その後、成膜時到達真空度及び成膜時圧力、成膜温度を同一としたまま酸素分圧／アルゴン分圧を先の値よりも約２分の１の０．３３に変えて連続して酸化物半導体層の第２の領域５０８を、厚み５０ｎｍ、縦横幅３ｍｍ×４ｍｍとしてスパッタ成膜した。 Subsequently, the oxygen partial pressure / argon partial pressure was changed to 0.33, which is about one-half of the previous value, with the ultimate vacuum during film formation, the pressure during film formation, and the film formation temperature kept the same. The second region 508 of the oxide semiconductor layer was formed by sputtering with a thickness of 50 nm and a vertical and horizontal width of 3 mm × 4 mm.
　ここで、第２の領域５０８の組成は、Ｉｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）（１／６：０．５：１／３，ｆ／（ｅ＋ｆ）＝０．７５０，ｈ＞０）で実施例及び比較例全てにおいて共通にした。
　なお、各スパッタ成膜では、メタルマスクを用いてパターン成膜しており、酸化物半導体層は各領域間で大気中に暴露することなく連続して成膜を行った。各領域のスパッタは、第１の領域５０６及び第２の領域５０８においてはＩｎ２Ｏ３ターゲット、ＳｎＯ２（又はＧａ２Ｏ３）ターゲット、ＺｎＯターゲットを用いた３元共スパッタを用いて行った。各領域の膜厚調整は成膜時間の調整にて行った。
　また、実施例１～１０及び比較例１～４に係る第１の領域５０６及び第２の領域５０８と同じ条件で成膜を施し作製した成膜試料について、蛍光Ｘ線分析で組成分析することにより、第１の領域５０６及び第２の領域５０８のそれぞれが上記の組成となることを確認した。また、Ｘ線回折測定により各成膜試料が非晶質膜であることを確認した。 Here, the composition of the second region 508 is In (e) Ga (f) Zn (g) O (h) (1/6: 0.5: 1/3, f / (e + f) = 0.750. , H> 0) and common to all the examples and comparative examples.
Note that in each sputtering film formation, a pattern was formed using a metal mask, and the oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere. Sputtering of each region was performed by ternary co-sputtering using an In 2 O 3 target, a SnO 2 (or Ga 2 O 3 ) target, and a ZnO target in the first region 506 and the second region 508. . The film thickness in each region was adjusted by adjusting the film formation time.
In addition, composition analysis is performed by fluorescent X-ray analysis on a film-formed sample formed by performing film formation under the same conditions as those of the first region 506 and the second region 508 according to Examples 1 to 10 and Comparative Examples 1 to 4. Thus, it was confirmed that each of the first region 506 and the second region 508 had the above composition. In addition, it was confirmed by X-ray diffraction measurement that each film formation sample was an amorphous film.
　その後、第２の領域５０８の表面にソース・ドレイン電極５１０,５１２をスパッタにより成膜した。ソース・ドレイン電極５１０,５１２の成膜はメタルマスクを用いたパターン成膜にて作製し、Ｔｉを１０ｎｍ成膜後、Ａｕを４０ｎｍ成膜した。 Thereafter, source / drain electrodes 510 and 512 were formed on the surface of the second region 508 by sputtering. The source / drain electrodes 510 and 512 were formed by pattern film formation using a metal mask. After depositing 10 nm of Ti, 40 nm of Au was deposited.
　電極層形成後、３００℃、酸素分圧１００％の雰囲気下でポストアニール処理を行った。 After the electrode layer was formed, post-annealing was performed in an atmosphere of 300 ° C. and oxygen partial pressure of 100%.
以上により、チャネル長１８０μｍでチャネル幅１ｍｍのボトムゲート型ＴＦＴの実施例１～１０及び比較例１～４を得た。
図９は、実施例１～１０及び比較例２～４における第１の領域５０６の組成に着目した三元相図を示す図である。なお、比較例１における第１の領域５０６は、その組成の一部がＳｎでなくＧａなので三元相図に示していない。 Thus, Examples 1 to 10 and Comparative Examples 1 to 4 of bottom gate TFTs having a channel length of 180 μm and a channel width of 1 mm were obtained.
FIG. 9 is a diagram showing a ternary phase diagram focusing on the composition of the first region 506 in Examples 1 to 10 and Comparative Examples 2 to 4. Note that the first region 506 in Comparative Example 1 is not shown in the ternary phase diagram because part of its composition is Ga, not Sn.
－比較例５及び比較例６－
　また、さらなる比較例５及び比較例６として、酸化物半導体層を５０ｎｍのＩｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）（ａ＝１／３，ｂ＝１／３，ｃ＝１／３）と（ａ＝２／５，ｂ＝２／５，ｃ＝１／５）単膜としたＴＦＴもあわせて作製した。なお、比較例５及び比較例６に係るＴＦＴは、酸化物半導体層の構成以外は、上記実施例１に係るＴＦＴと同一の構成である。 -Comparative Example 5 and Comparative Example 6-
Further, as Comparative Example 5 and Comparative Example 6, the oxide semiconductor layer was formed with a 50 nm In (a) Sn (b) Zn (c) O (d) (a = 1/3, b = 1/3, c = 1/3) and (a = 2/5, b = 2/5, c = 1/5) TFTs made as single films were also produced. The TFTs according to Comparative Example 5 and Comparative Example 6 have the same configuration as the TFT according to Example 1 except for the configuration of the oxide semiconductor layer.
－評価－
　作製した上記実施例１～１０および比較例１～６について、半導体パラメータ・アナライザー４１５６Ｃ（アジレントテクノロジー社製）を用い、トランジスタ特性（Ｖｇ－Ｉｄ特性）および移動度μの測定を行った。測定結果のうち代表的なＶｇ－Ｉｄ特性を図１０に示した。Ｖｇ－Ｉｄ特性の測定は、ドレイン電圧（Ｖｄ）を１０Ｖに固定し、ゲート電圧（Ｖｇ）を－３０Ｖ～＋３０Ｖの範囲内で掃引し、各ゲート電圧（Ｖｇ）におけるドレイン電流（Ｉｄ）を測定することにて行った。また、移動度は、ドレイン電圧（Ｖｄ）を１Ｖに固定した状態でゲート電圧（Ｖｇ）を－３０Ｖ～＋３０Ｖの範囲内で掃引して得た、線形領域でのＶｇ－Ｉｄ特性から線形移動度を算出して記している。 -Evaluation-
For the produced Examples 1 to 10 and Comparative Examples 1 to 6, transistor characteristics (Vg-Id characteristics) and mobility μ were measured using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies). A typical Vg-Id characteristic among the measurement results is shown in FIG. Vg-Id characteristics are measured by fixing the drain voltage (Vd) to 10V, sweeping the gate voltage (Vg) within the range of -30V to + 30V, and measuring the drain current (Id) at each gate voltage (Vg). I went to do it. The mobility is linear mobility from the Vg-Id characteristic in the linear region obtained by sweeping the gate voltage (Vg) in the range of -30V to + 30V with the drain voltage (Vd) fixed at 1V. Is calculated and written.
　また、作製したＴＦＴのうち実施例１～１０および比較例１～４に係るＴＦＴはＶｇ－Ｉｄ特性を評価した後、波長可変のモノクロ光を照射することで、光照射に対するＴＦＴ特性の安定性を評価した。 Among the fabricated TFTs, the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 4 were evaluated for Vg-Id characteristics and then irradiated with wavelength-variable monochrome light, so that the TFT characteristics were stable with respect to light irradiation. Evaluated.
　この安定性の評価では、プローブステージ台に各ＴＦＴを置き、乾燥大気を２時間以上流した後、当該乾燥大気雰囲気下にてＴＦＴ特性を測定した。モノクロ光源の照射強度は１０μＷ／ｃｍ２、波長λの範囲を３６０～７００ｎｍとし、モノクロ光非照射時のＶｇ－Ｉｄ特性と、モノクロ光照射時のＶｇ－Ｉｄ特性を比較することで、光照射安定性（ΔＶｔｈ）を評価した。モノクロ光照射下におけるＴＦＴ特性の測定条件は、Ｖｄｓ＝１０Ｖに固定し、Ｖｇ＝－１５～１５Ｖの範囲でゲート電圧を掃引して測定した。なお、以下で特に言及している場合を除き、全ての測定は、モノクロ光を１０分照射した後に行っている。４２０ｎｍの光照射に対する閾値シフト量ΔＶｔｈをＴＦＴの光安定性の指標とした。 In this stability evaluation, each TFT was placed on a probe stage stage and dried air was allowed to flow for 2 hours or more, and then TFT characteristics were measured in the dried air atmosphere. The irradiation intensity of the monochrome light source is 10 μW / cm 2 , the wavelength λ is 360 to 700 nm, and the Vg-Id characteristics when the monochrome light is not irradiated are compared with the Vg-Id characteristics when the monochrome light is irradiated. Stability (ΔVth) was evaluated. The measurement conditions of the TFT characteristics under monochrome light irradiation were fixed by Vds = 10 V and measured by sweeping the gate voltage in the range of Vg = −15 to 15V. Unless otherwise specified below, all measurements are performed after irradiating with monochromatic light for 10 minutes. The threshold shift amount ΔVth for light irradiation of 420 nm was used as an indicator of TFT light stability.
　モノクロ光照射時のＩ－Ｖ特性の測定結果のうち代表的なＶｇ－Ｉｄ特性を、モノクロ光照射前の特性と共に図１１～図１５に示す。なお、上記評価方法は以降の実施例において共通である。 Representative Vg-Id characteristics among the measurement results of IV characteristics during monochrome light irradiation are shown in FIGS. 11 to 15 together with the characteristics before monochrome light irradiation. In addition, the said evaluation method is common in a following example.
　以下の表３に、移動度、Ｉ－Ｖ特性から求めた閾値電圧Ｖｔｈ、及び、モノクロ光照射前後のＩ－Ｖ特性から求めた閾値シフト量ΔＶｔｈの測定結果をまとめた。 Table 3 below summarizes the measurement results of the mobility, the threshold voltage Vth obtained from the IV characteristics, and the threshold shift amount ΔVth obtained from the IV characteristics before and after the monochrome light irradiation.
Figure JPOXMLDOC01-appb-T000006
 
Figure JPOXMLDOC01-appb-T000006
 
　図１０及び表３より、実施例１～１０及び比較例１～４に関していずれも２０ｃｍ２／Ｖｓ超の高い移動度と１０８程度の良好なＯｎ／Ｏｆｆ比が実現していることが分かる。 From FIG. 10 and Table 3, it can be seen that in each of Examples 1 to 10 and Comparative Examples 1 to 4, a high mobility of over 20 cm 2 / Vs and a good On / Off ratio of about 10 8 are realized.
　一方で、比較例５及び６に示すように実施例５や実施例３と同様の組成の膜を酸化物半導体層の単膜として用いた場合には、閾値電圧が大きくマイナス値を取ったり、明瞭なスイッチング特性を示さない状況（表３中「－」で示す）であったりすることが分かった。したがって、本実施例から、ＩｎＳｎＺｎＯ膜をゲート電極に近い側に配し、ＩｎＧａＺｎＯ膜をゲート電極に遠い側に配すことにより、ＴＦＴにおいて高い移動度と良好なＯｎ／Ｏｆｆ比、スイッチング特性を示すことがわかった。 On the other hand, as shown in Comparative Examples 5 and 6, when a film having the same composition as that of Example 5 or Example 3 was used as a single film of the oxide semiconductor layer, the threshold voltage was greatly negative, It was found that the situation does not show clear switching characteristics (indicated by “-” in Table 3). Therefore, from this example, the InSnZnO film is disposed on the side closer to the gate electrode, and the InGaZnO film is disposed on the side far from the gate electrode, thereby exhibiting high mobility, good On / Off ratio, and switching characteristics in the TFT. I understood it.
　また、表３及び図１１～図１５から、実施例１～１０は比較例１～４の結果に比べて、光照射時の閾値の変動量（閾値シフト量ΔＶｔｈ）が小さくなっていることが分かる。実施例１～１０では閾値シフト量の絶対値｜ΔＶｔｈ｜が１Ｖ以内に収まっているのに対し、比較例１～４では閾値シフト量の絶対値｜ΔＶｔｈ｜が１Ｖ超と大きい値をとることが分かる。したがって、以上の結果からＩｎＳｎＺｎＯ／ＩｎＧａＺｎＯの積層型の酸化物半導体層を有するＴＦＴでは、２０ｃｍ２／Ｖｓ超の高い移動度と、波長４２０ｎｍの光照射に対して閾値シフト量の絶対値｜ΔＶｔｈ｜が１Ｖ以下となる高い光安定性と、を両立することが確認できた。 Further, from Table 3 and FIGS. 11 to 15, in Examples 1 to 10, the threshold fluctuation amount (threshold shift amount ΔVth) at the time of light irradiation is smaller than the results of Comparative Examples 1 to 4. I understand. In Examples 1 to 10, the absolute value | ΔVth | of the threshold shift amount is within 1V, whereas in Comparative Examples 1 to 4, the absolute value | ΔVth | of the threshold shift amount is a large value exceeding 1V. I understand. Therefore, from the above results, in a TFT having a stacked oxide semiconductor layer of InSnZnO / InGaZnO, a mobility higher than 20 cm 2 / Vs and an absolute value of the threshold shift amount with respect to light irradiation with a wavelength of 420 nm | ΔVth | Has been confirmed to be compatible with high light stability of 1 V or less.
　次に、閾値電圧について着目する。 Next, focus on the threshold voltage.
　図１６は、閾値電圧と、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。なお、図中の点線は、ＩｎとＳｎとＺｎの組成比の合計に対する各Ｚｎ比における閾値電圧のプロットの平均値を結んだ線である。 FIG. 16 is a graph plotting the relationship between the threshold voltage and the Zn ratio {c / (a + b + c)} with respect to the total composition ratio of In, Sn, and Zn in the first region based on Table 3. In addition, the dotted line in a figure is a line which connected the average value of the plot of the threshold voltage in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
　図１０，１６及び表３から、閾値電圧はＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝に依存しており、このＺｎ比が増大するにつれて閾値電圧が上昇している傾向が見て取れる。そして、実施例１，３，４では閾値電圧が他の実施例よりもマイナス側にあり、実施例２もほぼ０に近く、オフ電流が若干高いことが分かる。これは実施例１～４の場合には他の実施例と比較してキャリア濃度が高いためであることが予想される。図２０に示すＩｎＳｎＺｎＯ単膜におけるキャリア濃度の組成依存性を参考にすると、キャリアを誘起しやすいと考えられるＩｎやＳｎ元素に比べてＺｎの元素含有量が低い場合、キャリア濃度が高くなると考えられる。したがって、閾値電圧・オフ電流の観点からＩｎＳｎＺｎＯ膜（第１の領域）中のＺｎの含有量はある程度高い方が好ましいと言える。 10 and 16 and Table 3, the threshold voltage depends on the Zn ratio {c / (a + b + c)}, and it can be seen that the threshold voltage tends to increase as the Zn ratio increases. In the first, third, and fourth embodiments, the threshold voltage is on the minus side compared to the other embodiments, and the second embodiment is also close to 0, indicating that the off-current is slightly higher. This is presumably because the carrier concentration in Examples 1 to 4 is higher than that in other Examples. Referring to the composition dependence of the carrier concentration in the InSnZnO single film shown in FIG. 20, the carrier concentration is considered to be higher when the element content of Zn is lower than that of In or Sn elements that are likely to induce carriers. . Therefore, it can be said that the Zn content in the InSnZnO film (first region) is preferably higher to some extent from the viewpoint of threshold voltage and off-current.
　例えば図１６に示すように、実施例１｛ｃ／（ａ＋ｂ＋ｃ）＝０．１｝では、閾値電圧が著しくマイナス側に現れている。一方で、実施例２～１０｛ｃ／（ａ＋ｂ＋ｃ）≧０．２００｝では、閾値電圧が０付近か正の値をとっている。したがって、ＴＦＴの閾値電圧が著しくマイナス側に現れることを抑制するという観点から、第１の領域の組成がｃ／（ａ＋ｂ＋ｃ）≧０．２００で表されるのが好ましいことが分かる。 For example, as shown in FIG. 16, in Example 1 {c / (a + b + c) = 0.1}, the threshold voltage appears significantly on the negative side. On the other hand, in Examples 2 to 10 {c / (a + b + c) ≧ 0.200}, the threshold voltage is close to 0 or takes a positive value. Therefore, it can be seen that the composition of the first region is preferably expressed by c / (a + b + c) ≧ 0.200 from the viewpoint of suppressing the threshold voltage of the TFT from appearing on the minus side.
　また、図１６に示すように、ＴＦＴ４０の閾値電圧を０Ｖよりもプラス側により高くすることができるという観点から、第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧１／３で表されるのがより好ましいことが分かる。 In addition, as shown in FIG. 16, the composition of the first region is expressed by c / (a + b + c) ≧ 1/3 from the viewpoint that the threshold voltage of the TFT 40 can be made higher on the positive side than 0V. It can be seen that is more preferable.
　さらに、閾値電圧がほぼ飽和し、Ｚｎの組成比率に対する閾値電圧の変動を抑えることができるという観点から、第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧０．４００で表されるのがさらにより好ましいことが分かる。 Furthermore, from the viewpoint that the threshold voltage is almost saturated and fluctuation of the threshold voltage with respect to the Zn composition ratio can be suppressed, the composition of the first region is expressed by c / (a + b + c) ≧ 0.400. It turns out that it is even more preferable.
　次に、移動度について再着目する。 Next, focus on mobility again.
　図１７は、移動度と、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。なお、図中の点線は、ＩｎとＳｎとＺｎの組成比の合計に対する各Ｚｎ比における移動度のプロットの平均値を結んだ線である。 FIG. 17 is a graph plotting the relationship between the mobility and the Zn ratio {c / (a + b + c)} with respect to the total composition ratio of In, Sn, and Zn in the first region based on Table 3. In addition, the dotted line in a figure is a line which connected the average value of the plot of the mobility in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
　図１７に示すように、移動度はＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝に依存しており、このＺｎ比が減少するにつれて移動度が上昇している傾向が見て取れる。そして、Ｚｎ比が０．８００から０．７００に減少するにつれて急激に上昇し、０．７００以下で移動度が３０ｃｍ２／Ｖｓ超となっていることも確認できた。したがって、移動度を３０ｃｍ２／Ｖｓ超にするという観点から、第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≦０．７００で表されるのが好ましいことが分かる。 As shown in FIG. 17, the mobility depends on the Zn ratio {c / (a + b + c)}, and it can be seen that the mobility increases as the Zn ratio decreases. It was also confirmed that the Zn ratio rapidly increased as the Zn ratio decreased from 0.800 to 0.700, and that the mobility was higher than 30 cm 2 / Vs at 0.700 or less. Therefore, it can be seen that the composition of the first region is preferably expressed by c / (a + b + c) ≦ 0.700 from the viewpoint of setting the mobility to more than 30 cm 2 / Vs.
　移動度について、Ｉｎ比に視点を変えて考察する。 ∙ Consider the mobility by changing the viewpoint to the In ratio.
　図１８は、移動度と、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＩｎ比｛ａ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。なお、図中の点線は、ＩｎとＳｎとＺｎの組成比の合計に対する各Ｉｎ比における移動度のプロットの平均値を結んだ線である。 FIG. 18 is a graph plotting the relationship between the mobility and the In ratio {a / (a + b + c)} with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3. In addition, the dotted line in a figure is a line which connected the average value of the plot of the mobility in each In ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
　図１８に示すように、移動度はＩｎ比｛ａ／（ａ＋ｂ＋ｃ）｝に依存しており、このＩｎ比が増大するにつれて移動度が上昇している傾向が見て取れる。そして、Ｉｎ比が０．１００から１／３に増大するにつれて急激に上昇し、１／３以降で移動度が４０ｃｍ２／Ｖｓ超となっていることも確認できた。したがって、第１の領域の組成は、ａ／（ａ＋ｂ＋ｃ）≧１／３で表されるのが好ましいことが分かった。 As shown in FIG. 18, the mobility depends on the In ratio {a / (a + b + c)}, and it can be seen that the mobility increases as the In ratio increases. It was also confirmed that the In ratio increased rapidly from 0.100 to 1/3, and that the mobility was over 40 cm 2 / Vs after 1/3. Therefore, it was found that the composition of the first region is preferably represented by a / (a + b + c) ≧ 1/3.
　次に、閾値シフト量ΔＶｔｈについて再着目する。 Next, focus on the threshold shift amount ΔVth again.
　図１９は、閾値シフト量ΔＶｔｈと、第１の領域におけるＩｎとＳｎとＺｎの組成比の合計に対するＺｎ比｛ｃ／（ａ＋ｂ＋ｃ）｝との関係を表３に基づいてプロットしたグラフ図である。なお、図中の点線は、ＩｎとＳｎとＺｎの組成比の合計に対する各Ｚｎ比における閾値シフト量ΔＶｔｈのプロットの平均値を結んだ線である。 FIG. 19 is a graph plotting the relationship between the threshold shift amount ΔVth and the Zn ratio {c / (a + b + c)} with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3. . In addition, the dotted line in a figure is a line which connected the average value of the plot of threshold value shift amount (DELTA) Vth in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
　図１９に示すように、移動度や閾値電圧に比べて、閾値シフト量ΔＶｔｈはＺｎ比に依存していないように見て取れる。しかしながら、Ｚｎ比ｃが０．１と０．８の時では、閾値シフト量の絶対値｜ΔＶｔｈ｜が０．８Ｖ以上となり基準となる１Ｖに近づくものの、Ｚｎ比ｃが０．２００≦ｃ／（ａ＋ｂ＋ｃ）≦０．７００の範囲内（図９に示すハッチング範囲）であると、その両端のｃ＝０．１とｃ＝０．８のときに比べて閾値シフト量の絶対値｜ΔＶｔｈ｜を顕著に低減でき、０．６Ｖ未満に抑えることができるのが確認できた。
　したがって、第１の領域の組成は、０．２００≦ｃ／（ａ＋ｂ＋ｃ）≦０．７００であることがより好ましいことが分かった。 As shown in FIG. 19, it can be seen that the threshold shift amount ΔVth does not depend on the Zn ratio compared to the mobility and the threshold voltage. However, when the Zn ratio c is 0.1 and 0.8, the absolute value | ΔVth | of the threshold shift amount is 0.8 V or more and approaches 1 V as a reference, but the Zn ratio c is 0.200 ≦ c / If it is within the range of (a + b + c) ≦ 0.700 (hatching range shown in FIG. 9), the absolute value of the threshold shift amount | ΔVth | as compared to when both ends are c = 0.1 and c = 0.8 It has been confirmed that can be significantly reduced and can be suppressed to less than 0.6V.
Therefore, it was found that the composition of the first region is more preferably 0.200 ≦ c / (a + b + c) ≦ 0.700.
＜ＴＦＴ特性に対する第１の領域膜厚依存性＞
　次に、ＴＦＴ特性に対する第１の領域の膜厚依存性について検討した。 <Dependence of TFT thickness on first region thickness>
Next, the film thickness dependence of the first region with respect to TFT characteristics was examined.
　検討するにあたって、実施例６と構成（第１の領域の組成はａ：ｂ：ｃ＝０．２：０．２：０．４）が同じで第１の領域の膜厚のみがそれぞれ異なる実施例１１～１５に係るＴＦＴを作製した。実施例１１～１５に係るＴＦＴの第１の領域の膜厚は、それぞれ１０，１５，３０，５０，７０ｎｍとした。 In the examination, the configuration (the composition of the first region is a: b: c = 0.2: 0.2: 0.4) is the same as that of Example 6, but only the thickness of the first region is different. TFTs according to Examples 11 to 15 were produced. The film thicknesses of the first regions of the TFTs according to Examples 11 to 15 were 10, 15, 30, 50, and 70 nm, respectively.
　次に、作製した実施例１１～１５及び実施例６に係るＴＦＴについて、上述した方法を用いてそれぞれ、移動度、閾値電圧、オフ電流、及びＳ値を測定した。そして、測定した結果を以下の表４にまとめた。 Next, for the fabricated TFTs according to Examples 11 to 15 and Example 6, the mobility, threshold voltage, off-current, and S value were measured using the above-described methods, respectively. The measured results are summarized in Table 4 below.
Figure JPOXMLDOC01-appb-T000007
 
Figure JPOXMLDOC01-appb-T000007
 
　表４に示すように、第１の領域の膜厚が７０ｎｍであると、閾値電圧が大幅にマイナス側に現れるとともに、若干のＳ値の悪化が見て取れる。したがって、第１の領域の膜厚は、５０ｎｍ以下であることが好ましいことが分かった。５０ｎｍ以下であるとＴＦＴの閾値電圧が著しくマイナス側に現れることを抑制でき、またＳ値の悪化も抑制できるからである。
　また、第１の領域の膜厚が３０ｎｍ以下であると、閾値電圧が正の値をとることが見て取れる。したがって、第１の領域の膜厚は、３０ｎｍ以下であることが好ましいことが分かった。
　日本出願２０１２－１０１４１４の開示はその全体が参照により本明細書に取り込まれる。
　本明細書に記載された全ての文献、特許出願、および技術規格は、個々の文献、特許出願、および技術規格が参照により取り込まれることが具体的かつ個々に記載された場合と同程度に、本明細書中に参照により取り込まれる。 As shown in Table 4, when the film thickness of the first region is 70 nm, the threshold voltage appears significantly on the negative side, and a slight deterioration of the S value can be seen. Therefore, it was found that the thickness of the first region is preferably 50 nm or less. This is because if it is 50 nm or less, the threshold voltage of the TFT can be suppressed from appearing on the negative side, and the deterioration of the S value can be suppressed.
Further, it can be seen that the threshold voltage takes a positive value when the film thickness of the first region is 30 nm or less. Therefore, it was found that the thickness of the first region is preferably 30 nm or less.
The disclosure of Japanese application 2012-101414 is incorporated herein by reference in its entirety.
All documents, patent applications, and technical standards mentioned in this specification are to the same extent as if each individual document, patent application, and technical standard were specifically and individually described to be incorporated by reference, Incorporated herein by reference.

Claims (19)

  1. 　酸化物半導体層と、ソース電極と、ドレイン電極と、ゲート絶縁膜と、ゲート電極とを有する電界効果型トランジスタであって、
    　前記酸化物半導体層は、
    　Ｉｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）（ａ＞０，ｂ＞０，ｃ＞０，ｄ＞０，ａ＋ｂ＋ｃ＝１）を含む第１の領域と、
    　前記第１の領域よりも前記ゲート電極から遠い側に配置されており、Ｉｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）（ｅ＞０，ｆ＞０，ｇ＞０，ｈ＞０，ｅ＋ｆ＋ｇ＝１）を含む第２の領域と、を有する、
    　電界効果型トランジスタ。     A field effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode,
    The oxide semiconductor layer is
    A first region including In (a) Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0, a + b + c = 1);
    In (e) Ga (f) Zn (g) O (h) (e> 0, f> 0, g> 0, h>, which is disposed on the side farther from the gate electrode than the first region. A second region including 0, e + f + g = 1),
    Field effect transistor.
  2. 　前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧０．２００で表される、請求項１に記載の電界効果型トランジスタ。 2. The field effect transistor according to claim 1, wherein the composition of the first region is represented by c / (a + b + c) ≧ 0.200.
  3. 　前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≦０．７００で表される、請求項１又は請求項２に記載の電界効果型トランジスタ。 3. The field effect transistor according to claim 1, wherein the composition of the first region is represented by c / (a + b + c) ≦ 0.700.
  4. 　前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧１／３で表される、請求項１～請求項３の何れか１項に記載の電界効果型トランジスタ。 4. The field effect transistor according to claim 1, wherein the composition of the first region is expressed by c / (a + b + c) ≧ 1/3.
  5. 　前記第１の領域の組成は、ｃ／（ａ＋ｂ＋ｃ）≧０．４００で表される、請求項１～請求項４の何れか１項に記載の電界効果型トランジスタ。 5. The field effect transistor according to claim 1, wherein the composition of the first region is expressed by c / (a + b + c) ≧ 0.400.
  6. 　前記第１の領域の組成は、ａ／（ａ＋ｂ＋ｃ）≧１／３で表される、請求項１～請求項５の何れか１項に記載の電界効果型トランジスタ。 6. The field effect transistor according to claim 1, wherein the composition of the first region is represented by a / (a + b + c) ≧ 1/3.
  7. 　前記第１の領域の膜厚は、５０ｎｍ以下である、請求項１～請求項６の何れか１項に記載の電界効果型トランジスタ。 The field effect transistor according to any one of claims 1 to 6, wherein a film thickness of the first region is 50 nm or less.
  8. 　前記第１の領域の膜厚は、１６ｎｍ以下である、請求項７に記載の電界効果型トランジスタ。 The field effect transistor according to claim 7, wherein the film thickness of the first region is 16 nm or less.
  9. 　前記第１の領域の膜厚は、５ｎｍ以上である、請求項１～請求項８の何れか１項に記載の電界効果型トランジスタ。 The field effect transistor according to any one of claims 1 to 8, wherein the film thickness of the first region is 5 nm or more.
  10. 　前記第２の領域の組成は、ｆ／（ｅ＋ｆ）≦０．８７５で表される、請求項１～請求項９の何れか１項に記載の電界効果型トランジスタ。 10. The field effect transistor according to claim 1, wherein the composition of the second region is represented by f / (e + f) ≦ 0.875.
  11. 　前記第２の領域の組成は、ｆ／（ｅ＋ｆ）＞０．２５０で表される、請求項１～請求項１０の何れか１項に記載の電界効果型トランジスタ。 11. The field effect transistor according to claim 1, wherein the composition of the second region is represented by f / (e + f)> 0.250.
  12. 　前記第２の領域の膜厚は、１０ｎｍ超７０ｎｍ未満である、請求項１～請求項１１の何れか１項に記載の電界効果型トランジスタ。 12. The field effect transistor according to claim 1, wherein a film thickness of the second region is more than 10 nm and less than 70 nm.
  13. 　前記酸化物半導体層は非晶質膜である、請求項１～請求項１２の何れか１項に記載の電界効果型トランジスタ。 The field effect transistor according to any one of claims 1 to 12, wherein the oxide semiconductor layer is an amorphous film.
  14. 　前記第２の領域は、前記第１の領域よりも電気伝導度が低い、請求項１～請求項１３の何れか１項に記載の電界効果型トランジスタ。 The field effect transistor according to any one of claims 1 to 13, wherein the second region has lower electrical conductivity than the first region.
  15. 　酸化物半導体層と、ソース電極と、ドレイン電極と、ゲート絶縁膜と、ゲート電極とを有する電界効果型トランジスタの製造方法であって、
    　前記酸化物半導体層の成膜工程として、
    　Ｉｎ（ａ）Ｓｎ（ｂ）Ｚｎ（ｃ）Ｏ（ｄ）（ａ＞０，ｂ＞０，ｃ＞０，ｄ＞０、ａ＋ｂ＋ｃ＝１）を含む第１の領域を、成膜室内を第１の酸素分圧／アルゴン分圧としてスパッタリング法により成膜する第１成膜工程と、
    　前記第１の領域よりも前記ゲート電極から遠い側に配置され、Ｉｎ（ｅ）Ｇａ（ｆ）Ｚｎ（ｇ）Ｏ（ｈ）（ｅ＞０，ｆ＞０，ｇ＞０，ｈ＞０、ｅ＋ｆ＋ｇ＝１）を含む第２の領域を、前記成膜室内を第２の酸素分圧／アルゴン分圧としてスパッタリング法により成膜する第２成膜工程と、を有する、
    　電界効果型トランジスタの製造方法。     A method of manufacturing a field effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode,
    As a film forming step of the oxide semiconductor layer,
    In (a) Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0, a + b + c = 1) A first film forming step of forming a film by a sputtering method with an oxygen partial pressure / argon partial pressure of 1;
    In (e) Ga (f) Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0, disposed farther from the gate electrode than the first region. a second film formation step of forming a second region including e + f + g = 1) by sputtering using the film formation chamber as a second oxygen partial pressure / argon partial pressure.
    A method of manufacturing a field effect transistor.
  16. 　前記第１の酸素分圧／アルゴン分圧が、前記第２の酸素分圧／アルゴン分圧よりも高い、請求項１５に記載の電界効果型トランジスタの製造方法。 16. The method of manufacturing a field effect transistor according to claim 15, wherein the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.
  17. 　請求項１～請求項１４の何れか１項に記載の電界効果型トランジスタを備える表示装置。 A display device comprising the field effect transistor according to any one of claims 1 to 14.
  18. 　請求項１～請求項１４の何れか１項に記載の電界効果型トランジスタを備えるイメージセンサ。 An image sensor comprising the field effect transistor according to any one of claims 1 to 14.
  19. 　請求項１～請求項１４の何れか１項に記載の電界効果型トランジスタを備えるＸ線センサ。 An X-ray sensor comprising the field effect transistor according to any one of claims 1 to 14.
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