WO2013147453A1 - Gallium nitride-based light-emitting diode - Google Patents

Gallium nitride-based light-emitting diode Download PDF

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WO2013147453A1
WO2013147453A1 PCT/KR2013/002320 KR2013002320W WO2013147453A1 WO 2013147453 A1 WO2013147453 A1 WO 2013147453A1 KR 2013002320 W KR2013002320 W KR 2013002320W WO 2013147453 A1 WO2013147453 A1 WO 2013147453A1
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layer
semiconductor layer
gallium nitride
emitting diode
light emitting
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PCT/KR2013/002320
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French (fr)
Korean (ko)
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최승규
김재헌
정정환
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서울옵토디바이스주식회사
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Publication of WO2013147453A1 publication Critical patent/WO2013147453A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a gallium nitride based light emitting diode, and more particularly to a gallium nitride based light emitting diode using a gallium nitride substrate as a growth substrate.
  • nitrides of group III elements such as gallium nitride (GaN)
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • Such a nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing them, and therefore, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., on heterogeneous substrates having a similar crystal structure. It has been grown through the process of.
  • a hetero substrate a sapphire substrate having a hexagonal structure is mainly used.
  • epitaxial layers grown on dissimilar substrates have a relatively high dislocation density due to lattice mismatch with the growth substrate and differences in coefficient of thermal expansion.
  • Epilayers grown on sapphire substrates are generally known to have dislocation densities of at least 1E8 / cm 2.
  • the epitaxial layer having such a high dislocation density has a limit in improving the luminous efficiency of the light emitting diode.
  • the luminous efficiency is further reduced compared to when operating at a low current.
  • the lattice mismatch and thermal expansion coefficient difference between the epi layer and the growth substrate limits the thickness of the epi layer grown on the sapphire substrate.
  • the thickness of the n-type contact layer grown on the sapphire substrate is generally in the range of 1 to 2um.
  • the thickness limitation of the n-type contact layer increases the resistance of the light emitting diode and thus the forward voltage.
  • the problem to be solved by the present invention is to provide a light emitting diode having an improved luminous efficiency.
  • Another object of the present invention is to provide a light emitting diode capable of driving under high current.
  • Another object of the present invention is to provide a light emitting diode that can lower the forward voltage.
  • a light emitting diode a gallium nitride substrate; A gallium nitride based first semiconductor layer on the gallium nitride substrate; A gallium nitride based second semiconductor layer positioned on the first semiconductor layer; An active layer having a multi-quantum well structure positioned between the first semiconductor layer and the second semiconductor layer; And a gallium nitride based electronic block layer positioned between the active layer and the second semiconductor layer.
  • the first semiconductor layer has a thickness in the range of 5um to 15um
  • the electron block layer is a quaternary gallium nitride based semiconductor layer containing aluminum and indium.
  • the electron block layer may be formed of a four-component gallium nitride based semiconductor layer to form a thicker thickness of the first semiconductor layer.
  • the first semiconductor layer is formed of a single GaN layer.
  • the first semiconductor layer may be an n-type contact layer.
  • the light emitting diode may further include a first electrode contacting the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer.
  • the semiconductor device may further include a superlattice layer having a multilayer structure positioned between the first semiconductor layer and the active layer.
  • the superlattice layer may have a structure in which an InGaN layer, an AlGaN layer, and a GaN layer are repeatedly stacked in a plurality of cycles.
  • the superlattice layer of the multilayer structure may further include a GaN layer between the InGaN layer and the AlGaN layer in each period.
  • the active layer includes a barrier layer and a well layer, and the well layer is formed of InGaN.
  • the barrier layers in the active layer may be formed of GaN, but are not limited thereto, and may be formed of AlGaN or AlInGaN.
  • the present invention by adopting a gallium nitride substrate it is possible to improve the crystallinity of the semiconductor layers grown thereon to improve the luminous efficiency of the light emitting diode. Furthermore, by forming the first semiconductor layer thickly, the crystallinity of the semiconductor layers can be further improved, and the forward voltage can be reduced. In addition, by arranging a superlattice layer between the first semiconductor layer and the active layer, it is possible to prevent crystal defects that may be generated in the active layer.
  • FIG. 1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view illustrating a superlattice layer according to an embodiment of the present invention.
  • FIG 3 is a cross-sectional view illustrating a superlattice layer according to another exemplary embodiment of the present invention.
  • FIG. 4 is a cross-sectional view for describing an active layer according to an embodiment of the present invention.
  • FIG. 5 shows an energy band for explaining the active layer of FIG. 4.
  • FIG. 6 is a cross-sectional view illustrating a change in stress caused by epitaxial layers grown on a gallium nitride substrate.
  • FIG. 7 is a graph for explaining the increase in light output according to the use of gallium nitride substrate.
  • FIG 8 is a graph illustrating an increase in light output according to a thickness of a first semiconductor layer.
  • FIG. 1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
  • the light emitting diode includes a gallium nitride substrate 11, a first semiconductor layer 13, an active layer 30, an electron block layer 41, and a second semiconductor layer 43.
  • the light emitting diode may include a superlattice layer 20, a transparent electrode layer 45, a first electrode 47, and a second electrode 49.
  • the gallium nitride substrate 11 may have a c-plane growth surface.
  • the growth surface of the gallium nitride substrate 11 may have an inclination angle to help the growth of the epi layer.
  • Such gallium nitride substrate 11 can be manufactured using, for example, HVPE technology.
  • the gallium nitride substrate 11 may have a thickness of about 100um to 450um.
  • the first semiconductor layer 13 is formed of GaN doped with Si.
  • the first semiconductor layer 13 may be directly grown on the gallium nitride substrate 11. As illustrated, the first electrode 47 may be in ohmic contact on the first semiconductor layer 13.
  • the first semiconductor layer 13 may have a thickness of about 5um to about 15um. Preferably, the first semiconductor layer 13 may have a thickness of 7um to 10um.
  • the thickness of the first semiconductor layer 13 means the thickness of a single GaN layer. That is, the semiconductor layer 13 continuously grown with the same composition has a thickness of 5 ⁇ m or more.
  • the substrate 11 is a gallium nitride substrate, a single semiconductor layer of 2 ⁇ m or more can be grown thereon.
  • a superlattice layer 20 having a multilayer structure is positioned on the first semiconductor layer 13.
  • the superlattice layer 20 is located between the first semiconductor layer 13 and the active layer 30, and thus is located on the current path.
  • the superlattice layer 20 may be formed by repeatedly stacking a pair of InGaN / GaN (for example, 15 to 20 cycles), but is not limited thereto.
  • the three-layer structure of the InGaN layer 21 / AlGaN layer 22 / GaN layer 23 has a plurality of cycles (for example, about 10 to 20 cycles). ) May have a repeatedly stacked structure.
  • the order of the AlGaN layer 22 and the InGaN layer 21 may be reversed.
  • the InGaN layer 21 has a wider band gap than the well layer in the active layer 30.
  • the AlGaN layer 22 preferably has a wider band gap than the barrier layer in the active layer 30.
  • the InGaN layer 21 and the AlGaN layer 22 may be formed of an undoped layer that is not intentionally doped with impurities, and the GaN layer 23 may be formed of a Si doped layer.
  • the uppermost layer of the superlattice layer 20 is preferably a GaN layer 23 doped with impurities.
  • the AlGaN layer 22 may be formed to a thickness of less than 1 nm.
  • the superlattice layer 20 forms the AlGaN layer 22 on the InGaN layer 21, lattice mismatch between them is large and crystal defects are likely to be formed at the interface. Therefore, an AlInGaN layer may be used instead of the AlGaN layer 22 to reduce the lattice mismatch with the InGaN layer 21.
  • a GaN layer 24 may be inserted between the InGaN layer 21 and the AlGaN layer 22 as shown in FIG. 3.
  • the GaN layer 24 may be formed of an undoped layer or a Si doped layer.
  • the active layer 30 of the multi-quantum well structure is positioned on the superlattice layer 20.
  • the active layer 30 has a structure in which barrier layers 31a and 31b and well layers 33n, 33, and 33p are alternately stacked.
  • 33n represents the well layer (first well layer) closest to the superlattice layer 20 or the first semiconductor layer 13
  • 33p represents the electron block layer 41 or the p-type contact layer 23.
  • the nearest well layer (nth well layer) is shown.
  • 5 illustrates an energy band of the active layer 30.
  • a plurality of (n-1) barrier layers 31a and 31b and a plurality of (n-2) well layers are formed between the well layer 33n and the well layer 33p.
  • the fields 33 are stacked alternately with each other.
  • the barrier layers 31a have a thickness thicker than the average thickness of these (n-1) plurality of barrier layers 31a 31b, and the barrier layers 31b have a thickness thinner than the average thickness. Further, as shown, the barrier layers 31a are disposed close to the first well layer 33n and the barrier layers 31b are disposed close to the nth well layer 33p.
  • five well layers 33n, 33, 33p are used, but not limited thereto, and a larger number of well layers may be used.
  • the efficiency decrease caused by the increase of the current density that is, the droop phenomenon may be alleviated.
  • the barrier layer 31a may be positioned in contact with the uppermost layer of the superlattice layer 20. That is, the barrier layer 31a may be located between the superlattice layer 20 and the first well layer 33n. In addition, the barrier layer 35 may be positioned on the nth well layer 33p. The barrier layer 35 may have a relatively thicker thickness than the barrier layer 31a.
  • a relatively thin thickness of the barrier layers 31b close to the nth well layer 33p reduces the resistive component of the active layer 30 and also injects holes injected from the second semiconductor layer 43 into the active layer 30. It is possible to disperse the well layers 33, thereby lowering the forward voltage of the light emitting diode.
  • the crystallization of epitaxial layers formed thereon to heal crystal defects generated during the growth of the active layer 30, especially the well layers 33n, 33, 33p. Can be improved.
  • the number of the barrier layers 31b is greater than the number of the barrier layers 31a, the defect density may increase in the active layer 30, thereby reducing the light emission efficiency. Therefore, it is preferable to form the number of the barrier layers 31a more than the number of the barrier layers 31b.
  • the well layers 33n, 33, 33p may have almost the same thickness as each other, thereby emitting light having a very small half width.
  • the thicknesses of the well layers 33n, 33, and 33p may be adjusted differently to emit light having a relatively wide half width.
  • the thickness of the well layer 33 positioned between the barrier layers 31b relatively thin compared to the well layer 33 positioned between the barrier layers 31a, it is possible to prevent the formation of crystal defects. Can be.
  • the thickness of the well layers 33n, 33, 33p is, for example, in the range of 10 to 30 kPa
  • the thickness of the barrier layers 31a is in the range of 50 to 70 kPa
  • the thickness of the barrier layers 31b The thickness may be in the range of 30 to 50 mm 3.
  • the well layers 33n, 33, 33p may be formed of a gallium nitride based layer that emits light in the near ultraviolet or blue region.
  • the well layers 33n, 33, 33p may be formed of InGaN, and the In composition ratio is adjusted according to a required wavelength.
  • the barrier layers 31a and 31b are gallium nitride based layers having a wider bandgap than the well layers 33n, 33, 33p to trap electrons and holes in the well layers 33n, 33, 33p. Is formed.
  • the barrier layers 31a and 31b may be formed of GaN, AlGaN or AlInGaN.
  • the barrier layers 31a and 31b may be formed of a gallium nitride based layer containing Al to further increase the band gap.
  • the composition ratio of Al in the barrier layers 31a and 31b is preferably greater than 0 and less than 0.1, and in particular, may be 0.02 to 0.05.
  • the light output can be increased by limiting the Al composition ratio within the above range.
  • a cap layer may be formed between the well layers 33n, 33, 33p and the barrier layers 31a and 31b disposed thereon.
  • the cap layer is formed to prevent the well layer from being damaged while raising the chamber temperature to grow the barrier layers 31a and 31b.
  • the well layers 33n, 33, 33p may be grown at a temperature of about 780 ° C
  • the barrier layers 31a, 31b may be grown at a temperature of about 800 ° C.
  • the electron block layer 41 is positioned on the active layer 30 and is formed of AlInGaN.
  • the electron block layer 41 prevents electrons from moving to the second semiconductor layer 43 to improve luminous efficiency.
  • the thickness of the electron block layer 41 may be formed to be equal to or smaller than the sum of the thicknesses of the well layers in the active layer 30.
  • the conventional electron block layer 41 has generally been formed of AlGaN. However, since AlGaN has a large lattice constant difference from InGaN, more compressive stress is applied to the active layer 30. In addition, as the thickness of the first semiconductor layer 13 increases, additional compressive stress is generated in the active layer 30, and compressive stress by the electron block layer 41 is added.
  • the electron block layer 41 is formed of AlInGaN to reduce the compressive stress applied to the active layer 30 compared to AlGaN. Accordingly, by adopting the AlInGan electron block layer 41, the thickness of the first semiconductor layer 13 can be further increased as compared with the case of using AlGaN.
  • the second semiconductor layer 43 may be formed of GaN doped with Mg.
  • the second semiconductor layer 43 is located on the electron block layer 41.
  • a transparent conductive layer 45 such as ITO or ZnO is formed on the second semiconductor layer 43 to make ohmic contact with the second semiconductor layer 43.
  • the second electrode 49 is electrically connected to the second semiconductor layer 43.
  • the second electrode 49 may be connected to the second semiconductor layer 43 through the transparent conductive layer 45.
  • the first semiconductor layer 13 may be exposed by removing a portion of the second semiconductor layer 43, the electron block layer 41, the active layer 30, and the superlattice layer 20 by an etching process.
  • the first electrode 47 is formed on the exposed first semiconductor layer 13.
  • the epitaxial layers 13 to 43 grown on the gallium nitride substrate 11 may be formed using MOCVD.
  • TMAl, TMGa, and TMIn may be used as the sources of Al, Ga, and In
  • NH 3 may be used as the source of N.
  • SiH 4 may be used as a source of Si which is an n-type impurity
  • Cp 2 Mg may be used as a source of Mg that is a p-type impurity.
  • 6 is a schematic cross-sectional view for explaining a change in stress caused by epitaxial layers grown on a gallium nitride substrate.
  • 6 (a) is a cross-sectional view for explaining the initial state of the gallium nitride substrate 11, and FIG. 6 (b) shows the GaN layer grown on the gallium nitride substrate 11 as the first semiconductor layer 13.
  • 6 (c) is a cross-sectional view for describing a state after growth of the superlattice layer 20 and the active layer 30 on the first semiconductor layer 13, and FIG. It is sectional drawing for demonstrating the state after growth of the electron block layer 41.
  • the gallium nitride substrate 11 is a single layer and there is no stress applied from the outside. Thus, the gallium nitride substrate 11 is shown as having no substrate warpage.
  • the n-type GaN layer is grown as the first semiconductor layer 13 on the gallium nitride substrate 11
  • the n-type GaN layer is formed of the same GaN layer.
  • the gallium nitride substrate 11 is subjected to tensile stress due to the type impurity doping and crystal defects. Accordingly, the n-type GaN layer 13 generates tensile strain.
  • the superlattice layer 20 and the active layer 30 are subjected to compressive stress by the GaN layer 13 because they have a relatively large lattice constant compared to the GaN layer 13.
  • the superlattice layer 20 and the active layer 30 include InGaN
  • the superlattice layer 20 and the active layer 30 tend to have a relatively large lattice constant compared to the GaN layer 13 and the gallium nitride substrate 11. Accordingly, greater compressive stress is applied to the active layer 30 by the gallium nitride substrate 11 and the GaN layer 13.
  • the electron block layer 41 generally contains Al, and thus has a smaller lattice constant than the GaN layer 13. Therefore, the electron block layer 41 applies compressive stress to the active layer 30.
  • compressive stress is applied to the active layer 30 by the substrate 11, the first semiconductor layer 13, and the electron block layer 41 to generate a compressive strain. Moreover, as the thickness of the first semiconductor layer 13 is increased, the compressive strain is further increased. Such a compressive strain may further increase the piezoelectric polarization applied to the well layer to reduce the luminous efficiency.
  • the compressive stress applied to the active layer 30 can be alleviated by forming the electron block layer 41 made of AlInGaN having a larger lattice constant than AlGaN.
  • FIG. 7 is a graph for explaining the increase in light output according to the use of gallium nitride substrate.
  • a c-plane gallium nitride substrate was used as a growth substrate, and epitaxial layers were grown thereon to form a light emitting diode.
  • the superlattice layer 20 was formed by repeatedly stacking InGaN / GaN for 20 cycles, the well layer was formed of an InGaN layer emitting near ultraviolet rays, and the barrier layer was formed of GaN.
  • the first semiconductor layer 13 was 2 um.
  • a sapphire substrate was used as a growth substrate to form a light emitting diode emitting near ultraviolet rays on the sapphire substrate.
  • the thicknesses of the barrier layers and the well layers are the same in the comparative example and the example in order to confirm the light output change according to the difference of the growth substrate.
  • the gallium nitride substrate when used, the light output is increased by 30% or more compared with the case where the sapphire substrate is used.
  • the change in the light output according to the growth substrate difference is determined by the difference in dislocation density in the epi layer, particularly in the active layer 30.
  • FIG. 8 is a graph illustrating an increase in light output according to a thickness of a first semiconductor layer.
  • a GaN layer is formed as a first semiconductor layer 13 on a gallium nitride substrate having a c-plane growth surface, and the light emitting diode is manufactured by varying the thickness of the first semiconductor layer to 2um, 3.5um, 5um, and 10um. It was.
  • the relative light output is shown in FIG. 8 based on the light emitting diode having the first semiconductor layer 13 having a thickness of 2 ⁇ m.
  • the superlattice layer 20, the active layer 30, the electron block layer 41, and the second semiconductor layer 43 were all formed in the same manner.
  • the light output increases as the thickness of the first semiconductor layer 13 increases. In particular, as the thickness of the first semiconductor layer 13 exceeds 5um, it can be seen that the light output further increases.

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Abstract

A gallium nitride-based light-emitting diode is disclosed. The light-emitting diode includes: a gallium nitride substrate; a first gallium nitride-based semiconductor layer that is located on the gallium nitride substrate; a second gallium nitride-based semiconductor layer that is located on the first semiconductor layer; an active layer having a multiple quantum well structure that is located between the first semiconductor layer and the second semiconductor layer; and a gallium nitride-based electron blocking layer that is located between the active layer and the second semiconductor layer. Furthermore, the first semiconductor layer has a thickness of 5 μm to 15μm, and the electron blocking layer is a four-component gallium nitride-based semiconductor layer that contains aluminum and indium. It is possible to reduce forward voltage and improve light-emitting efficiency by increasing the relative thickness of the first semiconductor layer.

Description

질화갈륨계 발광 다이오드Gallium Nitride Light Emitting Diode
본 발명은 질화갈륨계 발광 다이오드에 관한 것으로, 특히 질화갈륨 기판을 성장기판으로 사용한 질화갈륨계 발광 다이오드에 관한 것이다.The present invention relates to a gallium nitride based light emitting diode, and more particularly to a gallium nitride based light emitting diode using a gallium nitride substrate as a growth substrate.
일반적으로 질화갈륨(GaN)과 같은 Ⅲ족 원소의 질화물은 열적 안정성이 우수하고 직접 천이형의 에너지 밴드(band) 구조를 가지므로, 최근 가시광선 및 자외선 영역의 발광소자용 물질로 많은 각광을 받고 있다. 특히, 질화인듐갈륨(InGaN)을 이용한 청색 및 녹색 발광 소자는 대규모 천연색 평판 표시 장치, 신호등, 실내 조명, 고밀도광원, 고해상도 출력 시스템과 광통신 등 다양한 응용 분야에 활용되고 있다.In general, nitrides of group III elements, such as gallium nitride (GaN), have excellent thermal stability and have a direct transition type energy band structure, and thus have recently received a lot of attention as materials for light emitting devices in the visible and ultraviolet regions. have. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.
이러한 III족 원소의 질화물 반도체층은 그것을 성장시킬 수 있는 동종의 기판을 제작하는 것이 어려워, 유사한 결정 구조를 갖는 이종 기판에서 금속유기화학기상증착법(MOCVD) 또는 분자선 증착법(molecular beam epitaxy; MBE) 등의 공정을 통해 성장되어 왔다. 이종기판으로는 육방 정계의 구조를 갖는 사파이어(Sapphire) 기판이 주로 사용된다. Such a nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing them, and therefore, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., on heterogeneous substrates having a similar crystal structure. It has been grown through the process of. As a hetero substrate, a sapphire substrate having a hexagonal structure is mainly used.
그러나, 이종 기판 상에 성장된 에피층은 성장 기판과의 격자 부정합 및 열팽창 계수 차이에 기인하여 전위 밀도가 상대적으로 높다. 사파이어 기판 상에 성장된 에피층은 일반적으로 1E8/㎠ 이상의 전위밀도를 갖는 것으로 알려져 있다. 이러한 높은 전위밀도를 갖는 에피층으로는 발광 다이오드의 발광 효율을 개선하는데 한계가 있다. 나아가, 고전류에서 발광 다이오드를 동작시킬 경우, 전위를 통해 전류가 집중되기 때문에 저전류에서 동작하는 경우에 비해, 발광 효율이 더욱 감소된다.However, epitaxial layers grown on dissimilar substrates have a relatively high dislocation density due to lattice mismatch with the growth substrate and differences in coefficient of thermal expansion. Epilayers grown on sapphire substrates are generally known to have dislocation densities of at least 1E8 / cm 2. The epitaxial layer having such a high dislocation density has a limit in improving the luminous efficiency of the light emitting diode. Furthermore, when operating the light emitting diode at a high current, since the current is concentrated through the potential, the luminous efficiency is further reduced compared to when operating at a low current.
또한, 에피층과 성장 기판과의 격자 부정합 및 열팽창 계수 차이는 사파이어 기판 상에 성장되는 에피층의 두께를 제한한다. 에피층을 두껍게 형성할 경우, 에피층에 크랙이 발생되기 쉽다. 이에 따라, 상기 사파이어 기판 상에 성장되는 n형 콘택층의 두께는 일반적으로 1~2um의 범위 내에 있다. n형 콘택층의 두께 제한은 발광 다이오드의 저항을 증가시키고 이에 따라 순방향 전압을 증가시킨다.Further, the lattice mismatch and thermal expansion coefficient difference between the epi layer and the growth substrate limits the thickness of the epi layer grown on the sapphire substrate. When the epi layer is formed thick, cracks are likely to occur in the epi layer. Accordingly, the thickness of the n-type contact layer grown on the sapphire substrate is generally in the range of 1 to 2um. The thickness limitation of the n-type contact layer increases the resistance of the light emitting diode and thus the forward voltage.
본 발명이 해결하고자 하는 과제는, 개선된 발광 효율을 갖는 발광 다이오드를 제공하는 것이다.The problem to be solved by the present invention is to provide a light emitting diode having an improved luminous efficiency.
본 발명이 해결하고자 하는 또 다른 과제는, 고전류 하에서 구동할 수 있는 발광 다이오드를 제공하는 것이다.Another object of the present invention is to provide a light emitting diode capable of driving under high current.
본 발명이 해결하고자 하는 또 다른 과제는, 순방향 전압을 낮출 수 있는 발광 다이오드를 제공하는 것이다.Another object of the present invention is to provide a light emitting diode that can lower the forward voltage.
본 발명의 일 실시예에 따른 발광 다이오드는, 질화갈륨 기판; 상기 질화갈륨 기판 상에 위치하는 질화갈륨계 제1 반도체층; 상기 제1 반도체층 상부에 위치하는 질화갈륨계 제2 반도체층; 상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 다중양자우물 구조의 활성층; 및 상기 활성층과 상기 제2 반도체층 사이에 위치하는 질화갈륨계 전자 블록층을 포함한다. 나아가, 상기 제1 반도체층은 5um 내지 15um 범위 내의 두께를 갖고, 상기 전자 블록층은 알루미늄과 인디움을 함유하는 4성분계 질화갈륨계 반도체층이다.A light emitting diode according to an embodiment of the present invention, a gallium nitride substrate; A gallium nitride based first semiconductor layer on the gallium nitride substrate; A gallium nitride based second semiconductor layer positioned on the first semiconductor layer; An active layer having a multi-quantum well structure positioned between the first semiconductor layer and the second semiconductor layer; And a gallium nitride based electronic block layer positioned between the active layer and the second semiconductor layer. Further, the first semiconductor layer has a thickness in the range of 5um to 15um, and the electron block layer is a quaternary gallium nitride based semiconductor layer containing aluminum and indium.
상기 제1 반도체층을 상대적으로 두껍게 형성함으로써 발광 다이오드의 저항을 감소시킬 수 있어 순방향 전압을 낮출 수 있다. 나아가, 상기 전자 블록층을 4성분계 질화갈륨계 반도체층으로 형성함으로써 상기 제1 반도체층의 두께를 더 두껍게 형성할 수 있다.By forming the first semiconductor layer to be relatively thick, the resistance of the light emitting diode can be reduced, and the forward voltage can be lowered. In addition, the electron block layer may be formed of a four-component gallium nitride based semiconductor layer to form a thicker thickness of the first semiconductor layer.
여기서, 상기 제1 반도체층은 단일의 GaN층으로 형성된다. 상기 제1 반도체층은 n형 콘택층일 수 있다.Here, the first semiconductor layer is formed of a single GaN layer. The first semiconductor layer may be an n-type contact layer.
상기 발광 다이오드는, 상기 제1 반도체층에 콘택하는 제1 전극, 및 상기 제2 반도체층에 전기적으로 접속된 제2 전극을 더 포함할 수 있다.The light emitting diode may further include a first electrode contacting the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer.
몇몇 실시예들에 있어서, 상기 제1 반도체층과 상기 활성층 사이에 위치하는 다층 구조의 초격자층을 더 포함할 수 있다. 나아가, 상기 초격자층은 InGaN층, AlGaN층 및 GaN층을 복수 주기로 반복 적층한 구조를 가질 수 있다. 또한, 상기 다층 구조의 초격자층은 각 주기 내에서 InGaN층과 AlGaN층 사이에 GaN층을 더 포함할 수 있다.In some embodiments, the semiconductor device may further include a superlattice layer having a multilayer structure positioned between the first semiconductor layer and the active layer. In addition, the superlattice layer may have a structure in which an InGaN layer, an AlGaN layer, and a GaN layer are repeatedly stacked in a plurality of cycles. In addition, the superlattice layer of the multilayer structure may further include a GaN layer between the InGaN layer and the AlGaN layer in each period.
한편, 상기 활성층은 장벽층과 우물층을 포함하고, 상기 우물층은 InGaN으로 형성된다. 또한, 상기 활성층 내의 장벽층들은 GaN으로 형성될 수 있으나, 이에 한정되는 것은 아니며, AlGaN 또는 AlInGaN으로 형성될 수 있다.Meanwhile, the active layer includes a barrier layer and a well layer, and the well layer is formed of InGaN. In addition, the barrier layers in the active layer may be formed of GaN, but are not limited thereto, and may be formed of AlGaN or AlInGaN.
본 발명에 따르면, 질화갈륨 기판을 채택함으로써 그 위에 성장된 반도체층들의 결정질을 개선하여 발광 다이오드의 발광 효율을 향상시킬 수 있다. 더욱이, 제1 반도체층을 두껍게 형성함으로써 반도체층들의 결정질을 더욱 향상시킬 수 있으며, 순방향 전압을 감소시킬 수 있다. 또한, 제1 반도체층과 활성층 사이에 초격자층을 배치함으로써 활성층 내에서 생성될 수 있는 결정 결함을 방지할 수 있다.According to the present invention, by adopting a gallium nitride substrate it is possible to improve the crystallinity of the semiconductor layers grown thereon to improve the luminous efficiency of the light emitting diode. Furthermore, by forming the first semiconductor layer thickly, the crystallinity of the semiconductor layers can be further improved, and the forward voltage can be reduced. In addition, by arranging a superlattice layer between the first semiconductor layer and the active layer, it is possible to prevent crystal defects that may be generated in the active layer.
더욱이, 에피층 내에 형성되는 전위 밀도를 낮추어 고전류 하에서 구동할 수 있는 발광 다이오드를 제공할 수 있다.Furthermore, it is possible to provide a light emitting diode capable of driving under high current by lowering the dislocation density formed in the epi layer.
도 1은 본 발명의 일 실시예에 따른 발광 다이오드를 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
도 2는 본 발명의 일 실시예에 따른 초격자층을 설명하기 위한 단면도이다.2 is a cross-sectional view illustrating a superlattice layer according to an embodiment of the present invention.
도 3은 본 발명의 다른 실시예에 따른 초격자층을 설명하기 위한 단면도이다.3 is a cross-sectional view illustrating a superlattice layer according to another exemplary embodiment of the present invention.
도 4는 본 발명의 일 실시예에 따른 활성층을 설명하기 위한 단면도이다.4 is a cross-sectional view for describing an active layer according to an embodiment of the present invention.
도 5는 도 4의 활성층을 설명하기 위한 에너지 밴드를 나타낸다.FIG. 5 shows an energy band for explaining the active layer of FIG. 4.
도 6은 질화갈륨 기판 상에 성장되는 에피층들에 의해 발생되는 스트레스 변화를 설명하기 위한 단면도들이다.FIG. 6 is a cross-sectional view illustrating a change in stress caused by epitaxial layers grown on a gallium nitride substrate.
도 7은 질화갈륨 기판 사용에 따른 광 출력 증가를 설명하기 위한 그래프이다.7 is a graph for explaining the increase in light output according to the use of gallium nitride substrate.
도 8은 제1 반도체층의 두께에 따른 광 출력 증가를 설명하기 위한 그래프이다.8 is a graph illustrating an increase in light output according to a thickness of a first semiconductor layer.
이하, 첨부한 도면들을 참조하여 본 발명의 실시예들을 상세히 설명하기로 한다. 다음에 소개되는 실시예들은 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 예로서 제공되는 것이다. 따라서, 본 발명은 이하 설명되는 실시예들에 한정되지 않고 다른 형태로 구체화될 수도 있다. 그리고, 도면들에 있어서, 동일한 참조번호는 동일한 구성요소를 나타내며, 구성요소의 폭, 길이, 두께 등은 편의를 위하여 과장되어 표현될 수 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the same reference numerals denote the same components, and the width, length, thickness, etc. of the components may be exaggerated for convenience.
도 1은 본 발명의 일 실시예에 따른 발광 다이오드를 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
도 1을 참조하면, 상기 발광 다이오드는, 질화갈륨 기판(11), 제1 반도체층(13), 활성층(30), 전자 블록층(41) 및 제2 반도체층(43)을 포함한다. 나아가, 상기 발광 다이오드는, 초격자층(20), 투명 전극층(45), 제1 전극(47) 및 제2 전극(49)을 포함할 수 있다.Referring to FIG. 1, the light emitting diode includes a gallium nitride substrate 11, a first semiconductor layer 13, an active layer 30, an electron block layer 41, and a second semiconductor layer 43. In addition, the light emitting diode may include a superlattice layer 20, a transparent electrode layer 45, a first electrode 47, and a second electrode 49.
상기 질화갈륨 기판(11)은 c면 성장면을 가질 수 있다. 또한, 상기 질화갈륨 기판(11)의 성장면은 에피층의 성장을 돕기 위한 경사각을 가질 수 있다. 이러한 질화갈륨 기판(11)은 예컨대 HVPE 기술을 사용하여 제조될 수 있다. 상기 질화갈륨 기판(11)은 약 100um 내지 450um의 두께를 가질 수 있다.The gallium nitride substrate 11 may have a c-plane growth surface. In addition, the growth surface of the gallium nitride substrate 11 may have an inclination angle to help the growth of the epi layer. Such gallium nitride substrate 11 can be manufactured using, for example, HVPE technology. The gallium nitride substrate 11 may have a thickness of about 100um to 450um.
상기 제1 반도체층(13)은 Si이 도핑된 GaN으로 형성된다. 상기 제1 반도체층(13)은 질화갈륨 기판(11) 상에서 직접 성장될 수 있다. 도시한 바와 같이, 상기 제1 반도체층(13) 상에 제1 전극(47)이 오믹 콘택할 수 있다.The first semiconductor layer 13 is formed of GaN doped with Si. The first semiconductor layer 13 may be directly grown on the gallium nitride substrate 11. As illustrated, the first electrode 47 may be in ohmic contact on the first semiconductor layer 13.
상기 제1 반도체층(13)은 5um 내지 15um의 두께를 가질 수 있다. 바람직하게, 상기 제1 반도체층(13)은 7um 내지 10um의 두께를 가질 수 있다. 여기서, 상기 제1 반도체층(13)의 두께는 단일 GaN층의 두께를 의미한다. 즉, 동일한 조성으로 연속적으로 성장된 반도체층(13)이 5um 이상의 두께를 갖는 것이다. 종래, 사파이어 기판 상에 반도체층을 성장하는 경우, 기판과 반도체층 사이의 격자 부정합에 기인하여, 질화갈륨계 반도체층을 2um 이상 성장하기 어렵다. 이에 반해, 본 실시예에 있어서, 상기 기판(11)이 질화갈륨 기판이기 때문에, 그 위에 2um 이상의 단일 반도체층을 성장시킬 수 있다.The first semiconductor layer 13 may have a thickness of about 5um to about 15um. Preferably, the first semiconductor layer 13 may have a thickness of 7um to 10um. Here, the thickness of the first semiconductor layer 13 means the thickness of a single GaN layer. That is, the semiconductor layer 13 continuously grown with the same composition has a thickness of 5 μm or more. Conventionally, when growing a semiconductor layer on a sapphire substrate, due to the lattice mismatch between the substrate and the semiconductor layer, it is difficult to grow a gallium nitride based semiconductor layer by more than 2um. In contrast, in the present embodiment, since the substrate 11 is a gallium nitride substrate, a single semiconductor layer of 2 μm or more can be grown thereon.
한편, 상기 제1 반도체층(13) 상에 다층 구조의 초격자층(20)이 위치한다. 상기 초격자층(20)은 제1 반도체층(13)과 활성층(30) 사이에 위치하며, 따라서 전류 경로 상에 위치한다. 상기 초격자층(20)은 InGaN/GaN의 쌍을 복수 주기(예컨대, 15 내지 20 주기) 반복 적층하여 형성할 수 있으나, 이에 한정되지 않는다. 예컨대, 도 2에 도시한 바와 같이, 상기 초격자층(20)은 InGaN층(21)/AlGaN층(22)/GaN층(23)의 3층 구조가 복수 주기(예컨대, 약 10 내지 20 주기) 반복 적층된 구조를 가질 수 있다. AlGaN층(22)과 InGaN층(21)의 순서는 서로 바뀔 수도 있다. 여기서, 상기 InGaN층(21)은 활성층(30) 내의 우물층에 비해 넓은 밴드갭을 갖는다. 또한, 상기 AlGaN층(22)은 활성층(30) 내의 장벽층에 비해 넓은 밴드갭을 갖는 것이 바람직하다. 나아가, 상기 InGaN층(21) 및 AlGaN층(22)은 불순물을 의도적으로 도핑하지 않은 언도프트층으로 형성되고, 상기 GaN층(23)은 Si 도핑층으로 형성될 수 있다. 상기 초격자층(20)의 최상층은 불순물이 도핑된 GaN층(23)인 것이 바람직하다.Meanwhile, a superlattice layer 20 having a multilayer structure is positioned on the first semiconductor layer 13. The superlattice layer 20 is located between the first semiconductor layer 13 and the active layer 30, and thus is located on the current path. The superlattice layer 20 may be formed by repeatedly stacking a pair of InGaN / GaN (for example, 15 to 20 cycles), but is not limited thereto. For example, as shown in FIG. 2, the three-layer structure of the InGaN layer 21 / AlGaN layer 22 / GaN layer 23 has a plurality of cycles (for example, about 10 to 20 cycles). ) May have a repeatedly stacked structure. The order of the AlGaN layer 22 and the InGaN layer 21 may be reversed. Here, the InGaN layer 21 has a wider band gap than the well layer in the active layer 30. In addition, the AlGaN layer 22 preferably has a wider band gap than the barrier layer in the active layer 30. Further, the InGaN layer 21 and the AlGaN layer 22 may be formed of an undoped layer that is not intentionally doped with impurities, and the GaN layer 23 may be formed of a Si doped layer. The uppermost layer of the superlattice layer 20 is preferably a GaN layer 23 doped with impurities.
초격자층(20) 내에 AlGaN층(22)을 포함함으로써 활성층(30) 내의 정공이 제1 반도체층(13) 쪽으로 이동하는 것을 차단할 수 있어, 활성층(30)의 내의 발광 재결합율을 향상시킬 수 있다. 상기 AlGaN층(22)은 1nm 미만의 두께로 형성될 수 있다. By including the AlGaN layer 22 in the superlattice layer 20, it is possible to block holes in the active layer 30 from moving toward the first semiconductor layer 13, thereby improving the rate of light recombination in the active layer 30. have. The AlGaN layer 22 may be formed to a thickness of less than 1 nm.
한편, 상기 초격자층(20)은 InGaN층(21) 상에 AlGaN층(22)을 형성하기 때문에, 이들 사이의 격자부정합이 커서 계면에 결정 결함이 형성되기 쉽다. 따라서, InGaN층(21)과의 격자부정합을 감소시키기 위해 AlGaN층(22) 대신에 AlInGaN층이 사용될 수도 있다. 또는, 상기 InGaN층(21)과 AlGaN층(22) 사이에 도 3에 도시한 바와 같이 GaN층(24)을 삽입할 수 있다. 상기 GaN층(24)은 언도프트층 또는 Si 도핑된 층으로 형성될 수 있다.On the other hand, since the superlattice layer 20 forms the AlGaN layer 22 on the InGaN layer 21, lattice mismatch between them is large and crystal defects are likely to be formed at the interface. Therefore, an AlInGaN layer may be used instead of the AlGaN layer 22 to reduce the lattice mismatch with the InGaN layer 21. Alternatively, a GaN layer 24 may be inserted between the InGaN layer 21 and the AlGaN layer 22 as shown in FIG. 3. The GaN layer 24 may be formed of an undoped layer or a Si doped layer.
상기 초격자층(20) 상에 다중양자우물 구조의 활성층(30)이 위치한다. 상기 활성층(30)은, 도 4에 잘 도시된 바와 같이, 장벽층(31a, 31b) 및 우물층(33n, 33, 33p)이 교대로 적층된 구조를 갖는다. 여기서, 33n은, 초격자층(20) 또는 제1 반도체층(13)에 가장 가까운 우물층(제1 우물층)을 나타내고, 33p는 전자 블록층(41) 또는 p형 콘택층(23)에 가장 가까운 우물층(제n 우물층)은 나타낸다. 한편, 도 5는 상기 활성층(30)의 에너지 밴드를 나타낸다.The active layer 30 of the multi-quantum well structure is positioned on the superlattice layer 20. As illustrated in FIG. 4, the active layer 30 has a structure in which barrier layers 31a and 31b and well layers 33n, 33, and 33p are alternately stacked. Here, 33n represents the well layer (first well layer) closest to the superlattice layer 20 or the first semiconductor layer 13, and 33p represents the electron block layer 41 or the p-type contact layer 23. The nearest well layer (nth well layer) is shown. 5 illustrates an energy band of the active layer 30.
도 4 및 도 5를 참조하면, 상기 우물층(33n)과 우물층(33p) 사이에 (n-1)개의 복수의 장벽층들(31a, 31b) 및 (n-2)개의 복수의 우물층들(33)이 서로 교대로 적층되어 있다. 장벽층들(31a)은 이들 (n-1)개의 복수의 장벽층들(31a 31b)의 평균 두께보다 더 두꺼운 두께를 가지며, 장벽층들(31b)은 상기 평균 두께보다 더 얇은 두께를 갖는다. 또한, 도시한 바와 같이, 장벽층들(31a)이 제1 우물층(33n)에 가깝게 배치되고, 장벽층들(31b)이 제n 우물층(33p)에 가깝게 배치된다. 일반적으로 5개의 우물층들(33n, 33, 33p)이 사용되나, 이에 한정되는 것은 아니며, 더 많은 수의 우물층들이 사용될 수 있다. 우물층들을 많이 형성할수록 전류 밀도 증가에 따라 발생되는 효율 감소, 즉 드룹(droop) 현상을 완화할 수 있다.4 and 5, a plurality of (n-1) barrier layers 31a and 31b and a plurality of (n-2) well layers are formed between the well layer 33n and the well layer 33p. The fields 33 are stacked alternately with each other. The barrier layers 31a have a thickness thicker than the average thickness of these (n-1) plurality of barrier layers 31a 31b, and the barrier layers 31b have a thickness thinner than the average thickness. Further, as shown, the barrier layers 31a are disposed close to the first well layer 33n and the barrier layers 31b are disposed close to the nth well layer 33p. In general, five well layers 33n, 33, 33p are used, but not limited thereto, and a larger number of well layers may be used. As the well layers are formed, the efficiency decrease caused by the increase of the current density, that is, the droop phenomenon may be alleviated.
나아가, 장벽층(31a)이 초격자층(20)의 최상부층에 접하여 위치할 수 있다. 즉, 초격자층(20)과 제1 우물층(33n) 사이에 장벽층(31a)이 위치할 수 있다. 또한, 제n 우물층(33p) 상에 장벽층(35)이 위치할 수 있다. 장벽층(35)은 장벽층(31a)에 비해 상대적으로 더 두꺼운 두께를 가질 수 있다.In addition, the barrier layer 31a may be positioned in contact with the uppermost layer of the superlattice layer 20. That is, the barrier layer 31a may be located between the superlattice layer 20 and the first well layer 33n. In addition, the barrier layer 35 may be positioned on the nth well layer 33p. The barrier layer 35 may have a relatively thicker thickness than the barrier layer 31a.
제n 우물층(33p)에 가까운 장벽층들(31b)의 두께를 상대적으로 얇게 함으로써 활성층(30)의 저항 성분을 감소시키고 또한 제2 반도체층(43)에서 주입된 정공을 활성층(30) 내의 우물층들(33)에 분산시킬 수 있으며, 이에 따라 발광 다이오드의 순방향 전압을 낮출 수 있다. 또한, 장벽층(35)의 두께를 상대적으로 두껍게 함으로써, 활성층(30), 특히 우물층들(33n, 33, 33p)을 성장시키는 동안 생성된 결정 결함을 치유하여 그 위에 형성되는 에피층들의 결정질을 개선할 수 있다. 다만, 상기 장벽층들(31a)의 개수보다 장벽층들(31b)의 개수를 더 많이 형성할 경우, 활성층(30) 내에 결함 밀도가 증가하여 발광 효율이 감소될 수 있다. 따라서, 상기 장벽층들(31a)의 개수를 장벽층들(31b)의 개수보다 더 많이 형성하는 것이 바람직하다.A relatively thin thickness of the barrier layers 31b close to the nth well layer 33p reduces the resistive component of the active layer 30 and also injects holes injected from the second semiconductor layer 43 into the active layer 30. It is possible to disperse the well layers 33, thereby lowering the forward voltage of the light emitting diode. In addition, by relatively thickening the thickness of the barrier layer 35, the crystallization of epitaxial layers formed thereon to heal crystal defects generated during the growth of the active layer 30, especially the well layers 33n, 33, 33p. Can be improved. However, when the number of the barrier layers 31b is greater than the number of the barrier layers 31a, the defect density may increase in the active layer 30, thereby reducing the light emission efficiency. Therefore, it is preferable to form the number of the barrier layers 31a more than the number of the barrier layers 31b.
한편, 상기 우물층들(33n, 33, 33p)은 서로 거의 동일한 두께를 가질 수 있으며, 이에 따라 반치폭이 매우 작은 광을 방출할 수 있다. 이와 달리, 우물층들(33n, 33, 33p)의 두께를 서로 다르게 조절하여 상대적으로 넓은 반치폭을 갖는 광을 방출할 수도 있다. 나아가, 상기 장벽층들(31a) 사이에 위치하는 우물층(33)에 비해 장벽층들(31b) 사이에 위치하는 우물층(33)의 두께를 상대적으로 얇게 함으로써 결정 결함이 생성되는 것을 방지할 수 있다. 예컨대, 상기 우물층들(33n, 33, 33p)의 두께는 예컨대, 10 내지 30Å 범위 내이고, 상기 장벽층들(31a)의 두께는 50 내지 70Å 범위 내이고, 상기 장벽층들(31b)의 두께는 30 내지 50Å 범위 내일 수 있다.On the other hand, the well layers 33n, 33, 33p may have almost the same thickness as each other, thereby emitting light having a very small half width. Alternatively, the thicknesses of the well layers 33n, 33, and 33p may be adjusted differently to emit light having a relatively wide half width. Furthermore, by making the thickness of the well layer 33 positioned between the barrier layers 31b relatively thin compared to the well layer 33 positioned between the barrier layers 31a, it is possible to prevent the formation of crystal defects. Can be. For example, the thickness of the well layers 33n, 33, 33p is, for example, in the range of 10 to 30 kPa, the thickness of the barrier layers 31a is in the range of 50 to 70 kPa, and the thickness of the barrier layers 31b. The thickness may be in the range of 30 to 50 mm 3.
또한, 상기 우물층들(33n, 33, 33p)은 근자외선 또는 청색 영역의 광을 방출하는 질화갈륨계 층으로 형성될 수 있다. 예컨대, 상기 우물층들(33n, 33, 33p)은 InGaN으로 형성될 수 있드며, In 조성비는 요구되는 파장에 따라 조절된다.In addition, the well layers 33n, 33, 33p may be formed of a gallium nitride based layer that emits light in the near ultraviolet or blue region. For example, the well layers 33n, 33, 33p may be formed of InGaN, and the In composition ratio is adjusted according to a required wavelength.
한편, 상기 장벽층들(31a, 31b)은 전자와 정공을 우물층들(33n, 33, 33p) 내에 가두기 위해 상기 우물층들(33n, 33, 33p)보다 넓은 밴드갭을 갖는 질화갈륨계 층으로 형성된다. 예컨대, 상기 장벽층들(31a, 31b)은 GaN, AlGaN 또는 AlInGaN으로 형성될 수 있다. 특히, 상기 장벽층들(31a, 31b)은 Al을 함유하는 질화갈륨계 층으로 형성되어 밴드갭을 더욱 증대시킬 수 있다. 상기 장벽층들(31a, 31b) 내의 Al의 조성비는 0보다 크고 0.1보다 작은 것이 바람직하며, 특히, 0.02 내지 0.05일 수 있다. Al 조성비를 상기 범위 내로 제한함으로써 광 출력을 증가시킬 수 있다.On the other hand, the barrier layers 31a and 31b are gallium nitride based layers having a wider bandgap than the well layers 33n, 33, 33p to trap electrons and holes in the well layers 33n, 33, 33p. Is formed. For example, the barrier layers 31a and 31b may be formed of GaN, AlGaN or AlInGaN. In particular, the barrier layers 31a and 31b may be formed of a gallium nitride based layer containing Al to further increase the band gap. The composition ratio of Al in the barrier layers 31a and 31b is preferably greater than 0 and less than 0.1, and in particular, may be 0.02 to 0.05. The light output can be increased by limiting the Al composition ratio within the above range.
덧붙여, 상기 각 우물층(33n, 33, 33p)과 그 위에 위치하는 장벽층들(31a, 31b) 사이에는 도시하지는 않았지만, 캡층이 형성될 수 있다. 캡층은, 장벽층(31a, 31b)을 성장시키기 위해 챔버 온도를 올리는 동안 우물층이 손상되는 것을 방지하기 위해 형성된다. 예컨대, 상기 우물층들(33n, 33, 33p)은 약 780℃의 온도에서 성장될 수 있으며, 상기 장벽층들(31a, 31b)은 약 800℃의 온도에서 성장될 수 있다. In addition, a cap layer may be formed between the well layers 33n, 33, 33p and the barrier layers 31a and 31b disposed thereon. The cap layer is formed to prevent the well layer from being damaged while raising the chamber temperature to grow the barrier layers 31a and 31b. For example, the well layers 33n, 33, 33p may be grown at a temperature of about 780 ° C, and the barrier layers 31a, 31b may be grown at a temperature of about 800 ° C.
상기 전자 블록층(41)은 활성층(30) 상에 위치하며, AlInGaN으로 형성된다. 상기 전자 블록층(41)은 전자가 제2 반도체층(43)으로 이동하는 것을 차단하여 발광 효율을 개선한다. 상기 전자 블록층(41)의 두께는 활성층(30) 내 우물층들의 두께의 합과 동일하거나 그보다 작게 형성될 수 있다.The electron block layer 41 is positioned on the active layer 30 and is formed of AlInGaN. The electron block layer 41 prevents electrons from moving to the second semiconductor layer 43 to improve luminous efficiency. The thickness of the electron block layer 41 may be formed to be equal to or smaller than the sum of the thicknesses of the well layers in the active layer 30.
종래 전자 블록층(41)은 일반적으로 AlGaN으로 형성되어 왔다. 그러나, AlGaN은 InGaN과 격자 상수 차이가 크기 때문에 활성층(30)에 더 많은 압축 스트레스를 인가한다. 또한, 제1 반도체층(13)의 두께가 증가함에 따라 활성층(30)에 추가의 압축 스트레스가 발생되며, 전자 블록층(41)에 의한 압축 스트레스가 더해진다.The conventional electron block layer 41 has generally been formed of AlGaN. However, since AlGaN has a large lattice constant difference from InGaN, more compressive stress is applied to the active layer 30. In addition, as the thickness of the first semiconductor layer 13 increases, additional compressive stress is generated in the active layer 30, and compressive stress by the electron block layer 41 is added.
본 실시예에 따르면, 상기 전자블록층(41)을 AlInGaN으로 형성함으로써 AlGaN에 비해 활성층(30)에 인가되는 압축 스트레스를 완화할 수 있다. 이에 따라, AlInGan 전자 블록층(41)을 채택함으로써, 종래 AlGaN을 사용하는 경우에 비해 제1 반도체층(13)의 두께를 더 증가시킬 수 있다.According to the present embodiment, the electron block layer 41 is formed of AlInGaN to reduce the compressive stress applied to the active layer 30 compared to AlGaN. Accordingly, by adopting the AlInGan electron block layer 41, the thickness of the first semiconductor layer 13 can be further increased as compared with the case of using AlGaN.
다시 도 1을 참조하면, 상기 제2 반도체층(43)은 Mg을 도핑한 GaN로 형성될 수 있다. 제2 반도체층(43)은 전자 블록층(41) 상에 위치한다. 한편, 제2 반도체층(43) 상에 ITO나 ZnO와 같은 투명 도전층(45)이 형성되어 제2 반도체층(43)에 오믹 콘택할 수 있다. 제2 전극(49)이 제2 반도체층(43)에 전기적으로 접속된다. 제2 전극(49)은 투명 도전층(45)을 통해 제2 반도체층(43)에 접속될 수 있다.Referring back to FIG. 1, the second semiconductor layer 43 may be formed of GaN doped with Mg. The second semiconductor layer 43 is located on the electron block layer 41. On the other hand, a transparent conductive layer 45 such as ITO or ZnO is formed on the second semiconductor layer 43 to make ohmic contact with the second semiconductor layer 43. The second electrode 49 is electrically connected to the second semiconductor layer 43. The second electrode 49 may be connected to the second semiconductor layer 43 through the transparent conductive layer 45.
한편, 제2 반도체층(43), 전자 블록층(41), 활성층(30) 및 초격자층(20)의 일부를 식각 공정으로 제거하여 제1 반도체층(13)이 노출될 수 있다. 제1 전극(47)은 상기 노출된 제1 반도체층(13) 상에 형성된다.Meanwhile, the first semiconductor layer 13 may be exposed by removing a portion of the second semiconductor layer 43, the electron block layer 41, the active layer 30, and the superlattice layer 20 by an etching process. The first electrode 47 is formed on the exposed first semiconductor layer 13.
본 실시예에 있어서, 상기 질화갈륨 기판(11) 상에 성장되는 에피층들(13 ~ 43)은 MOCVD 기술을 이용하여 형성될 수 있다. 이때, Al, Ga 및 In의 소스로는 TMAl, TMGa 및 TMIn이 각각 사용될 수 있으며, N의 소스로는 NH3가 사용될 수 있다. 또한, n형 불순물인 Si의 소스로는 SiH4가 사용될 수 있고, p형 불순물인 Mg의 소스로는 Cp2Mg가 사용될 수 있다.In the present embodiment, the epitaxial layers 13 to 43 grown on the gallium nitride substrate 11 may be formed using MOCVD. In this case, TMAl, TMGa, and TMIn may be used as the sources of Al, Ga, and In, and NH 3 may be used as the source of N. In addition, SiH 4 may be used as a source of Si which is an n-type impurity, and Cp 2 Mg may be used as a source of Mg that is a p-type impurity.
도 6은 질화갈륨 기판 상에 성장되는 에피층들에 의해 발생되는 스트레스 변화를 설명하기 위한 개략적인 단면도들이다. 여기서, 도 6(a)는 질화갈륨 기판(11)의 초기 상태를 설명하기 위한 단면도이고, 도 6(b)는 질화갈륨 기판(11) 상에 제1 반도체층(13)으로서 GaN층 성장 후의 상태를 설명하기 위한 단면도이고, 도 6(c)는 제1 반도체층(13) 상에 초격자층(20) 및 활성층(30) 성장 후의 상태를 설명하기 위한 단면도이고, 도 6(d)는 전자 블록층(41) 성장 후의 상태를 설명하기 위한 단면도이다.6 is a schematic cross-sectional view for explaining a change in stress caused by epitaxial layers grown on a gallium nitride substrate. 6 (a) is a cross-sectional view for explaining the initial state of the gallium nitride substrate 11, and FIG. 6 (b) shows the GaN layer grown on the gallium nitride substrate 11 as the first semiconductor layer 13. 6 (c) is a cross-sectional view for describing a state after growth of the superlattice layer 20 and the active layer 30 on the first semiconductor layer 13, and FIG. It is sectional drawing for demonstrating the state after growth of the electron block layer 41. FIG.
도 6(a)에 도시되듯이, 질화갈륨 기판(11)은 단일 층으로서 외부에서 인가되는 스트레스가 없다. 따라서, 질화갈륨 기판(11)은 기판 휨이 없는 것으로 도시하였다.As shown in Fig. 6A, the gallium nitride substrate 11 is a single layer and there is no stress applied from the outside. Thus, the gallium nitride substrate 11 is shown as having no substrate warpage.
도 6(b)에 도시되듯이, 상기 질화갈륨 기판(11) 상에 제1 반도체층(13)으로서 n형 GaN층이 성장될 경우, 동일한 GaN층으로 형성되어 있지만 상기 n형 GaN층은 n형 불순물 도핑 및 결정 결함 등에 기인하여 상기 질화갈륨 기판(11)에 의해 인장 스트레스를 받는다. 따라서, 상기 n형 GaN층(13)은 인장 스트레인이 발생된다.As shown in FIG. 6B, when the n-type GaN layer is grown as the first semiconductor layer 13 on the gallium nitride substrate 11, the n-type GaN layer is formed of the same GaN layer. The gallium nitride substrate 11 is subjected to tensile stress due to the type impurity doping and crystal defects. Accordingly, the n-type GaN layer 13 generates tensile strain.
도 6(c)에 도시되듯이, 초격자층(20) 및 활성층(30)은 GaN층(13)에 비해 상대적으로 큰 격자 상수를 갖기 때문에 상기 GaN층(13)에 의해 압축 스트레스를 받는다. 특히, 상기 초격자층(20) 및 활성층(30)은 InGaN을 포함하기 때문에 상기 GaN층(13) 및 질화갈륨 기판(11)에 비해 상대적으로 큰 격자 상수를 가지려는 경향을 갖는다. 이에 따라, 질화갈륨 기판(11) 및 GaN층(13)에 의해 활성층(30)에 더 큰 압축 스트레스가 인가된다.As shown in FIG. 6C, the superlattice layer 20 and the active layer 30 are subjected to compressive stress by the GaN layer 13 because they have a relatively large lattice constant compared to the GaN layer 13. In particular, since the superlattice layer 20 and the active layer 30 include InGaN, the superlattice layer 20 and the active layer 30 tend to have a relatively large lattice constant compared to the GaN layer 13 and the gallium nitride substrate 11. Accordingly, greater compressive stress is applied to the active layer 30 by the gallium nitride substrate 11 and the GaN layer 13.
도 6(d)에 도시되듯이, 전자 블록층(41)은 일반적으로 Al을 함유하며, 따라서 GaN층(13)에 비해 더 작은 격자 상수를 갖는다. 따라서, 상기 전자 블록층(41)은 활성층(30)에 압축 스트레스를 인가한다.As shown in FIG. 6 (d), the electron block layer 41 generally contains Al, and thus has a smaller lattice constant than the GaN layer 13. Therefore, the electron block layer 41 applies compressive stress to the active layer 30.
즉, 상기 활성층(30)에는 기판(11), 제1 반도체층(13) 및 전자 블록층(41)에 의해 압축 스트레스가 인가되어 압축 스트레인이 발생된다. 더욱이, 제1 반도체층(13) 두께를 증가시킴에 따라 압축 스트레인은 더욱 증가된다. 이러한 압축 스트레인은 우물층에 인가되는 압전 분극을 더 증가시켜 발광 효율을 감소시킬 수 있다.That is, compressive stress is applied to the active layer 30 by the substrate 11, the first semiconductor layer 13, and the electron block layer 41 to generate a compressive strain. Moreover, as the thickness of the first semiconductor layer 13 is increased, the compressive strain is further increased. Such a compressive strain may further increase the piezoelectric polarization applied to the well layer to reduce the luminous efficiency.
따라서, 상기 전자 블록층(41)을 AlGaN보다 격자 상수가 큰 AlInGaN으로 형성함으로써 활성층(30)에 인가되는 압축 스트레스를 완화할 수 있다.Accordingly, the compressive stress applied to the active layer 30 can be alleviated by forming the electron block layer 41 made of AlInGaN having a larger lattice constant than AlGaN.
(실험예 1)Experimental Example 1
도 7은 질화갈륨 기판 사용에 따른 광 출력 증가를 설명하기 위한 그래프이다. 여기서, 본원 발명의 실시예로서, c면 질화갈륨 기판을 성장 기판으로 사용하고 그 위에 차례로 에피층들을 성장시켜 발광 다이오드를 형성하였다. 여기서 초격자층(20)은 InGaN/GaN을 20주기 반복 적층하여 형성하였으며, 우물층은 근자외선을 방출하는 InGaN층으로 형성하였고, 장벽층은 GaN으로 형성하였다. 제1 반도체층(13)은 2um로 하였다. 비교예로서, 사파이어 기판을 성장 기판으로 사용하여 사파이어 기판 상에 근자외선을 방출하는 발광 다이오드를 형성하였다. 여기서는, 성장 기판의 차이에 따른 광 출력 변화를 확인하기 위해 장벽층들 및 우물층들의 두께는 비교예와 실시예에서 서로 동일하게 형성하였다.7 is a graph for explaining the increase in light output according to the use of gallium nitride substrate. Here, as an embodiment of the present invention, a c-plane gallium nitride substrate was used as a growth substrate, and epitaxial layers were grown thereon to form a light emitting diode. The superlattice layer 20 was formed by repeatedly stacking InGaN / GaN for 20 cycles, the well layer was formed of an InGaN layer emitting near ultraviolet rays, and the barrier layer was formed of GaN. The first semiconductor layer 13 was 2 um. As a comparative example, a sapphire substrate was used as a growth substrate to form a light emitting diode emitting near ultraviolet rays on the sapphire substrate. Here, the thicknesses of the barrier layers and the well layers are the same in the comparative example and the example in order to confirm the light output change according to the difference of the growth substrate.
도 7을 참조하면, 질화갈륨 기판을 사용한 경우, 사파이어 기판을 사용한 경우에 비해 30% 이상의 광 출력이 증가되는 것을 확인할 수 있다. 성장 기판 차이에 따른 광 출력 변화는 에피층 특히 활성층(30) 내의 전위 밀도 차이에 의해 발생하는 것으로 판단된다. Referring to FIG. 7, it can be seen that when the gallium nitride substrate is used, the light output is increased by 30% or more compared with the case where the sapphire substrate is used. The change in the light output according to the growth substrate difference is determined by the difference in dislocation density in the epi layer, particularly in the active layer 30.
(실험예 2)Experimental Example 2
도 8은 제1 반도체층의 두께에 따른 광 출력 증가를 설명하기 위한 그래프이다. 여기서, c면 성장면을 갖는 질화갈륨 기판 상에 제1 반도체층(13)으로서 GaN층을 형성하되, 제1 반도체층의 두께를 2um, 3.5um, 5um 및 10um로 서로 다르게 하여 발광 다이오드를 제작하였다. 그리고, 2um 두께의 제1 반도체층(13)을 갖는 발광 다이오드를 기준으로 상대 광 출력을 도 8에 나타내었다. 초격자층(20), 활성층(30), 전자 블록층(41) 및 제2 반도체층(43)은 모두 동일하게 형성하였다.8 is a graph illustrating an increase in light output according to a thickness of a first semiconductor layer. Here, a GaN layer is formed as a first semiconductor layer 13 on a gallium nitride substrate having a c-plane growth surface, and the light emitting diode is manufactured by varying the thickness of the first semiconductor layer to 2um, 3.5um, 5um, and 10um. It was. The relative light output is shown in FIG. 8 based on the light emitting diode having the first semiconductor layer 13 having a thickness of 2 μm. The superlattice layer 20, the active layer 30, the electron block layer 41, and the second semiconductor layer 43 were all formed in the same manner.
도 8을 참조하면, 제1 반도체층(13)의 두께를 증가함에 따라 광 출력이 증가하는 것을 알 수 있다. 특히, 제1 반도체층(13)의 두께가 5um를 초과함에 따라 광 출력이 더욱 증가하는 것을 확인할 수 있다.Referring to FIG. 8, it can be seen that the light output increases as the thickness of the first semiconductor layer 13 increases. In particular, as the thickness of the first semiconductor layer 13 exceeds 5um, it can be seen that the light output further increases.
이상에서, 본 발명의 다양한 실시예들 및 특징들에 대해 설명하였지만, 본 발명은 위에서 설명한 실시예들 및 특징들에 한정되는 것은 아니며, 본 발명의 사상을 벗어나지 않는 범위 내에서 다양하게 변형될 수 있다.In the above, various embodiments and features of the present invention have been described, but the present invention is not limited to the embodiments and features described above, and various modifications may be made without departing from the spirit of the present invention. have.

Claims (9)

  1. 질화갈륨 기판;Gallium nitride substrates;
    상기 질화갈륨 기판 상에 위치하는 질화갈륨계 제1 반도체층;A gallium nitride based first semiconductor layer on the gallium nitride substrate;
    상기 제1 반도체층 상부에 위치하는 질화갈륨계 제2 반도체층;A gallium nitride based second semiconductor layer positioned on the first semiconductor layer;
    상기 제1 반도체층과 상기 제2 반도체층 사이에 위치하는 다중양자우물 구조의 활성층; 및An active layer having a multi-quantum well structure positioned between the first semiconductor layer and the second semiconductor layer; And
    상기 활성층과 상기 제2 반도체층 사이에 위치하는 질화갈륨계 전자 블록층을 포함하고,A gallium nitride-based electron block layer positioned between the active layer and the second semiconductor layer,
    상기 제1 반도체층은 5um 내지 15um 범위 내의 두께를 갖고,The first semiconductor layer has a thickness in the range of 5um to 15um,
    상기 전자 블록층은 알루미늄과 인듐을 함유하는 4성분계 질화갈륨계 반도체층인 발광 다이오드.The electron blocking layer is a light emitting diode comprising a gallium nitride-based semiconductor layer containing aluminum and indium.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 제1 반도체층은 단일의 GaN층인 발광 다이오드.The first semiconductor layer is a light emitting diode of a single GaN layer.
  3. 청구항 1에 있어서,The method according to claim 1,
    상기 제1 반도체층에 콘택하는 제1 전극; 및A first electrode contacting the first semiconductor layer; And
    상기 제2 반도체층에 전기적으로 접속된 제2 전극을 더 포함하는 발광 다이오드.And a second electrode electrically connected to the second semiconductor layer.
  4. 청구항 1에 있어서,The method according to claim 1,
    상기 제1 반도체층과 상기 활성층 사이에 위치하는 다층 구조의 초격자층을 더 포함하는 발광 다이오드.The light emitting diode of claim 1, further comprising a superlattice layer having a multilayer structure positioned between the first semiconductor layer and the active layer.
  5. 청구항 4에 있어서,The method according to claim 4,
    상기 초격자층은 InGaN층, AlGaN층 및 GaN층을 복수 주기로 반복 적층한 구조를 갖는 발광 다이오드.The superlattice layer has a structure in which an InGaN layer, an AlGaN layer, and a GaN layer are repeatedly stacked in a plurality of cycles.
  6. 청구항 5에 있어서, 상기 다층 구조의 초격자층은 각 주기 내에서 InGaN층과 AlGaN층 사이에 GaN층을 더 포함하는 발광 다이오드.The light emitting diode of claim 5, wherein the multilayered superlattice layer further comprises a GaN layer between the InGaN layer and the AlGaN layer in each period.
  7. 청구항 1에 있어서,The method according to claim 1,
    상기 활성층은 장벽층과 우물층을 포함하고,The active layer comprises a barrier layer and a well layer,
    상기 우물층은 InGaN으로 형성된 발광 다이오드.The well layer is a light emitting diode formed of InGaN.
  8. 청구항 7에 있어서,The method according to claim 7,
    상기 활성층 내의 장벽층들은 AlGaN 또는 AlInGaN으로 형성된 발광 다이오드.A light emitting diode in which the barrier layers in the active layer are formed of AlGaN or AlInGaN.
  9. 청구항 7에 있어서,The method according to claim 7,
    상기 전자블록층의 두께는 상기 활성층 내의 우물층들의 두께의 전체 합과 동일하거나 그 보다 더 작은 발광 다이오드.The thickness of the electron blocking layer is equal to or less than the total sum of the thicknesses of the well layers in the active layer.
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