WO2013140621A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2013140621A1
WO2013140621A1 PCT/JP2012/057589 JP2012057589W WO2013140621A1 WO 2013140621 A1 WO2013140621 A1 WO 2013140621A1 JP 2012057589 W JP2012057589 W JP 2012057589W WO 2013140621 A1 WO2013140621 A1 WO 2013140621A1
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layer
insulating film
thickness
semiconductor device
semiconductor layer
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PCT/JP2012/057589
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French (fr)
Japanese (ja)
Inventor
大輔 新井
剛 可知
義典 星野
田畑　剛
靖之 斉藤
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ルネサスエレクトロニクス株式会社
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Priority to PCT/JP2012/057589 priority Critical patent/WO2013140621A1/en
Publication of WO2013140621A1 publication Critical patent/WO2013140621A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0839—Cathode regions of thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a semiconductor device including a planar gate IGBT (Insulated Gate Bipolar Transistor) and a technology effective when applied to the manufacturing thereof.
  • IGBT Insulated Gate Bipolar Transistor
  • Patent Document 1 discloses a base layer, a buried insulating film having an opening, a surface semiconductor layer connected to the base layer under the opening, and a p-type channel formed in the surface semiconductor layer.
  • An IGBT having a formation layer, an n + -type source layer, a p + -type emitter layer, a gate electrode formed on a surface semiconductor layer via a gate insulating film, an n + -type buffer layer, a p-type collector layer, and the like is disclosed. ing. Further, it is described that the thickness of the surface semiconductor layer is 20 nm to 100 nm.
  • a surface semiconductor layer is formed on the main surface (surface) of a base layer made of single crystal silicon by an epitaxial method through a buried insulating film, and a source layer, a channel layer, And an emitter layer (channel contact layer) is formed.
  • the base layer and the surface semiconductor layer have a structure connected through an opening (spaced portion) formed in the buried insulating film.
  • a plurality of active regions are defined on the main surface of the base layer by an insulating film thicker than the buried insulating film, and a surface semiconductor layer is formed in each of the plurality of active regions.
  • the thickness of the surface semiconductor layer is set to 100 nm or less, more preferably in the range of 20 nm to 40 nm in order to reduce the steady loss, turn-off time, and turn-off loss of the IGBT (see the above-mentioned Patent Document 1). .
  • the thickness from the upper surface of the buried insulating film at the position corresponding to the first opening of the buried insulating film to the upper surface of the surface semiconductor layer is equal to the buried insulation at the position corresponding to the end of the gate electrode in contact with the sidewall. It is thinner than the thickness from the upper surface of the film to the upper surface of the surface semiconductor layer.
  • the present invention is a method for manufacturing a semiconductor device including an IGBT element.
  • An insulating film including a thin film portion having a first thickness and a thick film portion surrounding the thin film portion and having a second thickness thicker than the first thickness is formed on the main surface of the substrate.
  • a first opening reaching the substrate is formed in the thin film portion.
  • the surface semiconductor layer is formed on the thin film portion of the insulating film by embedding the first opening.
  • the thickness from the main surface of the substrate to the upper surface of the surface semiconductor layer is surrounded by the thick film portion of the insulating film.
  • the surface semiconductor layer is formed so as to be the thinnest at the center of the region and gradually thicker as it approaches the thick film portion of the insulating film.
  • the thickness from the upper surface of the insulating film to the upper surface of the surface semiconductor layer is thin at the center of the region surrounded by the thick film portion of the insulating film, and gradually increases as it approaches the thick film portion of the insulating film.
  • a surface semiconductor layer is formed.
  • the thickness from the upper surface of the base layer to the upper surface of the surface semiconductor layer located under the gate electrode reaches the second opening formed in a part of the interlayer insulating film covering the gate electrode from the upper surface of the base layer. Since the thickness of the surface semiconductor layer located in the region is thinner than the upper surface, the characteristics of the IGBT element can be improved. In other words, the thickness from the upper surface of the buried insulating film at the position corresponding to the first opening of the buried insulating film to the upper surface of the surface semiconductor layer is from the upper surface of the buried insulating film at the position corresponding to the end of the gate electrode. Since the thickness is smaller than the thickness up to the upper surface of the surface semiconductor layer, the characteristics of the IGBT element can be improved.
  • the thickness from the upper surface of the n-type base layer to the upper surface of the surface semiconductor layer located in the region reached by the second opening formed in a part of the interlayer insulating film covering the gate electrode is the thickness of the n-type base layer It is formed thicker than the thickness from the upper surface to the upper surface of the surface semiconductor layer located under the gate electrode.
  • the thickness from the upper surface of the insulating film to the upper surface of the surface semiconductor layer is thin at the center of the region surrounded by the thick film portion of the insulating film, and gradually increases as it approaches the thick film portion of the insulating film.
  • a surface semiconductor layer is formed. Therefore, the manufacturing yield of semiconductor devices including IGBT can be improved.
  • FIG. 2 is a plan view of a main part of a semiconductor chip forming an IGBT according to the present embodiment (an active part is a main part plan view showing an enlarged part of a region where an IGBT element is formed), and shows a layout of the IGBT element; It is a principal part top view to explain.
  • FIG. 2 is a main part plan view for explaining in detail a layout of an IGBT element by further enlarging only a region where the IGBT element of FIG. 1 is formed; FIG.
  • FIG. 6 is a plan view of a main part of a semiconductor chip forming an IGBT according to the present embodiment (an active part is a main part plan view showing an enlarged part of a region where an IGBT element is formed), and shows a layout of the wiring of the IGBT; It is a principal part top view to explain.
  • FIG. 3 is an essential part cross-sectional view showing an active part and an outer peripheral part of a semiconductor chip forming an IGBT according to the present embodiment (the active part is an essential part cross-sectional view corresponding to a cross section along line AA ′ shown in FIG. 2); .
  • FIG. 3 is an essential part cross-sectional view (a main part cross-sectional view corresponding to a cross section taken along the line BB ′ shown in FIG.
  • FIG. 2 shows an enlarged part of the IGBT element according to the present embodiment.
  • A is a schematic diagram when the thickness of a channel layer is 40 nm or less
  • (b) is a schematic diagram when the thickness of a channel layer is thicker than 40 nm (for example, 100 nm).
  • Ic collector current
  • Vce collector-emitter voltage
  • FIG. 2 is an essential part cross-sectional view showing an enlarged part of an active part of a semiconductor chip during a manufacturing process of a semiconductor device including an IGBT according to the present embodiment (main part corresponding to a cross section taken along line AA ′ shown in FIG. 2);
  • FIG. FIG. 9 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 8;
  • FIG. 10 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 9;
  • FIG. 11 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 10;
  • FIG. 11 is an essential part plan view illustrating a part of the active portion of the semiconductor chip in the process of manufacturing the semiconductor device, enlarged from FIG. 10;
  • FIG. 13 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 11 and FIG. 12;
  • FIG. 13 is a principal part plan view of the same place as in FIG. 12 in the process of manufacturing the semiconductor device, following FIG. 11 and FIG. 12;
  • FIG. 15 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 13 and FIG. 14;
  • FIG. 15 is a plan view of main parts of the same portions as those in FIG. 12 during the manufacturing process of the semiconductor device, following FIGS.
  • FIG. 17 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 15 and FIG. 16;
  • FIG. 18 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 17;
  • FIG. 18 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 17;
  • FIG. 20 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 18 and FIG. 19;
  • FIG. 20 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 18 and FIG. 19;
  • FIG. 20 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 18 and FIG. 19;
  • FIG. 18 and FIG. 19 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of
  • FIG. 22 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 20 and FIG. 21;
  • FIG. 23 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 22;
  • FIG. 24 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 23;
  • FIG. 24 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 23;
  • FIG. 26 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 24 and FIG. 25;
  • FIG. 27 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 26;
  • FIG. 28 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 27;
  • FIG. 29 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 28;
  • FIG. 30 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 29;
  • FIG. 30 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 29;
  • FIG. 29 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 26;
  • FIG. 28 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following
  • FIG. 32 is a main-portion cross-sectional view of the same portion as shown in FIG. 8 in the manufacturing process of the semiconductor device, which is subsequent to FIGS. 30 and 31;
  • FIG. 33 is a plan view of main parts of the same portions as those in FIG. 12 during the manufacturing process of the semiconductor device, following FIGS. 30 and 31;
  • FIG. 34 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 32 and FIG. 33;
  • FIG. 35 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 34;
  • FIG. 36 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 35;
  • FIG. 35 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 35;
  • FIG. 35 is an essential part cross-sectional view of the same place as in
  • FIG. 37 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 36;
  • FIG. 38 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 37;
  • FIG. 38 is a principal part plan view of the same place as in FIG. 12 in the process of manufacturing the semiconductor device, following FIG. 37;
  • FIG. 40 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 38 and FIG. 39;
  • FIG. 40 is a principal part plan view of the same point in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 38 and FIG. 39;
  • FIG. 42 is a main-portion cross-sectional view of the same portion as shown in FIG. 8 in the manufacturing process of the semiconductor device, which is subsequent to FIGS. 40 and 41;
  • the number of elements when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.
  • the constituent elements including element steps and the like
  • the shapes, positional relationships, etc. of the components, etc. when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
  • the specified material is a major material, and it is a sub-element, additive, unless otherwise specified or unless otherwise specified in principle or circumstances. However, this does not exclude added elements.
  • the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (eg, SiGe) having silicon as a main element, and the like.
  • SiGe binary or ternary alloy
  • silicon nitride, silicon nitride, or silicon nitride not only Si 3 N 4 but also silicon nitride is used and includes an insulating film having a similar composition. .
  • FIG. 1 is a plan view of a main part of a semiconductor chip forming an IGBT (an active part is an enlarged plan view of a main part showing a part of a region where an IGBT element is formed) and describes the layout of the IGBT element. It is a principal part top view to do.
  • FIG. 2 is a plan view of an essential part for explaining in detail the layout of the IGBT element by further enlarging only the region where the IGBT element is formed.
  • FIG. 3 is a plan view of a main part of a semiconductor chip forming the IGBT (the active part is a main part plan view showing a part of a region where an IGBT element is formed), and the layout of the IGBT wiring is described. It is a principal part top view to do.
  • FIG. 4 is a principal part sectional view showing an active part and an outer peripheral part of the semiconductor chip forming the IGBT (the active part is a principal part sectional view corresponding to a section taken along the line AA ′ shown in FIG. 2).
  • FIG. 5 is an essential part cross-sectional view showing a part of the IGBT element in an enlarged manner (main part cross-sectional view corresponding to the cross section along the line BB ′ shown in FIG. 2).
  • FIG. 6A and 6B are schematic diagrams for explaining a state in which the channel layer of the IGBT element is inverted.
  • FIG. 6A is a schematic diagram when the thickness of the channel layer is 40 nm or less
  • FIG. 6B is a schematic diagram when the thickness of the channel layer is 40 nm. It is a schematic diagram when it is thicker (for example, 100 nm).
  • FIG. 7 is a graph showing the relationship between the collector current (Ic) of the IGBT element and the collector-emitter voltage (Vce).
  • an IGBT element is formed in the active portion of the semiconductor chip 1.
  • This IGBT element is made of n ⁇ type single crystal silicon via a buried insulating film (thin film portion) 3 on the main surface (surface) of the base layer 2 made of n ⁇ type single crystal silicon, for example.
  • a plurality of surface semiconductor layers 4 are formed, and the base layer 2 and the surface semiconductor layer 4 are connected through a first opening (spaced portion) 5 formed in the buried insulating film 3.
  • a plurality of active regions AC are defined on the main surface of the base layer 2 by a plurality of insulating films (thick film portions) 6 thicker than the buried insulating film 3, and the surface semiconductor layer is formed in each of the plurality of active regions AC. 4 is formed.
  • the thickness of the base layer 2 is, for example, 70 ⁇ m to 100 ⁇ m, which is determined according to the breakdown voltage of the IGBT, and is 60 ⁇ m to 100 ⁇ m when the breakdown voltage is 600V, and 120 ⁇ m to 150 ⁇ m when the breakdown voltage is 1200V. Can be exemplified.
  • the thickness (first thickness) of the buried insulating film 3 is, for example, 100 nm to 450 nm
  • the thickness (second thickness) of the insulating film 6 is thicker than 300 nm, for example, 550 nm to 650 nm.
  • the buried insulating film 3 and the insulating film 6 are desirably formed thin in order to extend the depletion layer deeply to the base layer 2 under the buried insulating film 3 and the insulating film 6 to obtain a high breakdown voltage.
  • the buried insulating film 3 and the insulating film 6 are thin, there is a risk of penetrating the buried insulating film 3 and the insulating film 6 when the second opening is formed in the interlayer insulating film, as will be described later. There is sex. Therefore, the buried insulating film 3 and the insulating film 6 are also required to have a thickness for avoiding penetration. Therefore, the thicknesses of the buried insulating film 3 and the insulating film 6 are determined by a trade-off between the breakdown voltage and the processing margin. In the present embodiment, the above numerical values are shown as an example of the thicknesses of the buried insulating film 3 and the insulating film 6. However, the present invention is not limited thereto, and various changes can be made without departing from the scope of the invention. Needless to say.
  • the active region AC in which the IGBT element is formed has a long side in the first direction (the b direction in FIGS. 1 and 2) in a top view, and a second direction (FIGS. 1 and 2) orthogonal to the first direction. This is a region having a short side in the c direction).
  • the active region AC is a pattern having a certain width in the second direction (width indicated by a symbol W in FIG. 1) in the top view and extending in a strip shape in the first direction, and includes a plurality of active regions AC. Are arranged in stripes. Actually, for example, about 700 active regions AC are formed apart from each other along the second direction, but for convenience, only 16 active regions AC are shown in an enlarged manner in FIG. ing.
  • the width (W) along the second direction of the active region AC is, for example, 3 ⁇ m or more, and a typical value may be 7 ⁇ m to 8 ⁇ m. Further, the interval between two active regions AC adjacent to each other in the second direction (the interval indicated by symbol S in FIG. 1), that is, the width of the insulating film 6 along the second direction is along the second direction of the active region AC. It is shorter than the width (W).
  • the surface semiconductor layer 4 on the buried insulating film 3 includes a p-type channel layer 7, an n-type source layer 8 including an n + -type source layer 8 a and an n ⁇ -type source layer 8 b, and p ++ -type emitter layers 9 a and p A p-type emitter layer (p-type channel contact layer) 9 including a + -type emitter layer 9b is formed.
  • the impurity concentration in the n + -type source layer 8a is higher than the impurity concentration in the n ⁇ -type source layer 8b, and is on the p-type channel layer 7 side (between the p-type channel layer 7 and the n + -type source layer 8a).
  • the impurity concentration in the p ++ type emitter layer 9 a is higher than the impurity concentration in the p + type emitter layer 9 b
  • the impurity concentration in the p + type emitter layer 9 b is higher than the impurity concentration in the p type channel layer 7.
  • the p + emitter layer 9b is formed on the p type channel layer 7 side (between the p type channel layer 7 and the p + + type emitter layer 9a).
  • the n-type source layer 8 and the p emitter layer 9 are formed side by side along the first direction in a top view, but cannot be formed in the same cross section. Therefore, the n-type source layer 8 and the p-type emitter layer 9 are alternately arranged in the first direction in one pattern extending in a band shape between the gate electrode 11 and the insulating film 6 in a top view. ing. Further, the breakdown area is increased by making the plane area of the n-type source layer 8 smaller than the plane area of the p-type emitter layer 9.
  • the p-type channel layer 7 is formed between the gate electrode 11 and the buried insulating film 3. Further, since the p-type channel layer 7 is connected to the p-type emitter layer 9 and the potential is fixed, it is possible to prevent deterioration of characteristics due to formation of a parasitic MOS (Metal Oxide Semiconductor).
  • MOS Metal Oxide Semiconductor
  • Sidewalls SW are formed on the side surfaces of the gate electrode 11.
  • high concentration impurities are ion-implanted into the surface conductor layer 4 below the side surface of the gate electrode 11 using the gate electrode 11 as a mask
  • crystal defects are generated in the surface conductor layer 4 below the side surface of the gate electrode 11 by the subsequent heat treatment. There was concern. Therefore, a sidewall SW is formed on the side surface of the gate electrode 11, and high concentration impurities are ion-implanted into the surface conductor layer 4 below the end of the sidewall SW using the sidewall SW as a mask. Crystal defects are prevented from occurring in the surface semiconductor layer 4.
  • the n ⁇ -type source layer 8b is formed on the surface conductor layer 4 near the side surface of the gate electrode 11, and the n + -type source layer 8a is formed on the surface conductor layer 4 near the edge of the sidewall SW.
  • a plurality of p-type field limiting rings (Field Limiting Ring) 12 are formed on the outer peripheral portion of the semiconductor chip 1 so as to surround the active portion in a top view, and further surround the plurality of p-type field limiting rings 12.
  • an n-type guard ring (channel stopper) 13 is formed.
  • the p-type field limiting ring 12 is formed by introducing a p-type impurity into the base layer 2.
  • the p-type field limiting ring 12 is a p + -type semiconductor layer 26 into which an impurity indicating p-type is introduced through the first opening 5 formed in the buried insulating film 3 (similar to the surface semiconductor layer 4 described above). And has a structure connected to an impurity concentration similar to that in the p + -type emitter layer 9b), and the voltage is fixed by the field limiting ring electrode 12A.
  • FIG. 1 shows an example in which two p-type field limiting rings 12 are formed, a larger number may be formed.
  • the n-type guard ring 13 formed so as to surround the plurality of p-type field limiting rings 12 has a function of protecting the IGBT elements in the semiconductor chip 1 after the semiconductor chip 1 is separated from the semiconductor wafer.
  • the n-type guard ring 13 is formed in the same manner as the surface semiconductor layer 4 and has an n-type impurity introduced therein, and the voltage is fixed by the guard ring electrode 13A.
  • the n-type guard ring 13 has an impurity concentration comparable to the impurity concentration in the n + -type source layer 8a.
  • an interlayer insulating film 14 is formed on the active part and the outer peripheral part of the semiconductor chip 1 so as to cover the IGBT element, the p-type field limiting ring 12 and the n-type guard ring 13.
  • the interlayer insulating film 14 is configured by a laminated film in which a nitride film 32, a silicon oxide film 33, a BPSG (Boron-Phospho Silicate Glass) film 34, and a PSG (Phospho Silicate Glass) film 35 are sequentially deposited from the bottom. .
  • an n-type source layer 8 and a p-type emitter layer 9, a gate electrode 11, a p + -type semiconductor layer 26, and a second opening 15 reaching the n-type guard ring 13 are formed.
  • a source pad (source electrode) 16 electrically connected to the n-type source layer 8 and the p-type emitter layer 9 on the interlayer insulating film 14, and the gate electrode 11 Gate pads 17 that are electrically connected to each other are formed apart from each other. Further, a field limiting ring electrode 12A electrically connected to the p + -type semiconductor layer 26 and a guard ring electrode 13A electrically connected to the n-type guard ring 13 are formed apart from each other. These source pads 16 and the like are made of, for example, Al (aluminum). Further, around the active portion (region between the region where the IGBT element is formed and the outer peripheral portion), a source leading electrode 16A is formed continuously with the source pad 16.
  • the source routing electrode 16A is connected to a p ++ type emitter layer (not shown) formed around the active portion through a second opening (not shown) formed in the interlayer insulating film 14 below the source leading electrode 16A.
  • strip-shaped gate fingers 17A extending in the second direction are formed at both ends of the central portion of the active portion and both ends of the active portion in the first direction (the b direction in FIG. 3).
  • the gate finger 17 ⁇ / b> A is electrically connected to the gate electrode 11 through the second opening 15 formed in the interlayer insulating film 14 thereunder, and is formed continuously with the gate pad 17.
  • a polyimide film is formed so as to cover the source pad 16 and the like, and a part of the surface of the source pad 16 and a part of the surface of the gate pad 17 are exposed on the polyimide film.
  • An opening is formed. These openings serve as bonding pads for connecting a bonding wire for electrically connecting the outside of the semiconductor chip 1 to the source pad 16 and the gate pad 17. If necessary, an opening for exposing a part of the surface of the guard ring electrode 13A may be formed in the polyimide film.
  • an n + -type buffer layer 18, a p-type collector layer 19, and a collector electrode 20 are formed in order from the base layer 2.
  • the specific resistance of the p-type collector layer 19 increases due to the low impurity concentration. Therefore, in order to reduce the series resistance component of the p-type collector layer 19, it is required to form it thinly, and the thickness is preferably, for example, 5 ⁇ m or less.
  • the thickness of the p-type collector layer 19 is, for example, 1 ⁇ m or less. It is preferable to do.
  • the collector electrode 20 can be formed from the following metal film (1), (2), or (3).
  • the semiconductor chip 1 is illustrated as a rectangle for convenience of illustration, but actually, the length along the first direction (b direction) of the semiconductor chip 1 is 1 cm.
  • the length along the second direction (c direction) is 1 cm.
  • the distance from the chip end along the first direction (b direction) of the semiconductor chip 1 to the active part (active region AC) is 200 ⁇ m to 300 ⁇ m, and the chip along the second direction (c direction) of the semiconductor chip 1.
  • the distance from the end portion to the active portion (active region AC) is 200 ⁇ m to 300 ⁇ m. That is, the outer peripheral portion of the semiconductor chip 1 is disposed on the four sides of the semiconductor chip 1 over 200 ⁇ m to 300 ⁇ m. Therefore, in FIG. 4, the active portion and the outer peripheral portion are continuously described for easy understanding, but the width of the outer peripheral portion in FIG. 4 is 200 ⁇ m to 300 ⁇ m.
  • the technical feature of the present invention resides in the thickness of the surface semiconductor layer 4 formed in each of the plurality of active regions AC.
  • the thickness of the surface semiconductor layer 4 on which the p-type channel layer 7, the n-type source layer 8, and the p-type emitter layer 9 are formed is not constant.
  • the surface semiconductor layer 4 is formed so that the thickness up to the upper surface of 4 is the thinnest at the center of the active region AC and gradually increases as it approaches the insulating film 6. That is, in the cross section of the active region AC along the second direction, the thickness (L1) from the upper surface of the base layer 2 to the upper surface of the surface semiconductor layer 4 located under the gate electrode 11 is the upper surface of the base layer 2.
  • the thickness (L3) from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 at the position corresponding to the first opening 5 of the buried insulating film 3 is the thickness of the gate electrode 11 in contact with the sidewall SW. It is formed thinner than the thickness (L4) from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 at a position corresponding to the end (L3 ⁇ L4).
  • the thickness from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 (a region where part of the p-type channel layer 7 and the p + -type emitter layer 9b is formed) located under the gate electrode 11 is It is set in consideration of the steady loss, turn-off time, and turn-off loss of the IGBT. For example, 300 nm or less is considered to be an appropriate range (which is not limited to this range depending on other conditions). Further, a range suitable for mass production is considered to be 100 nm or less, but a range of 20 nm to 40 nm is considered most preferable.
  • the thickness (L2) from the upper surface of the base layer 2 to the upper surface of the surface semiconductor layer 4 located in the region where the second opening 15 is formed prevents penetration of the second opening 15.
  • the source pad 16 is formed to be thicker than 300 nm, for example.
  • the thickness of the surface semiconductor layer 4 located below the gate electrode 11 from the upper surface of the buried insulating film 3 is more desirably set in the range of 20 nm to 40 nm will be described with reference to FIGS.
  • the thickness of the p-type channel layer 7 (surface semiconductor layer 4) under the gate electrode 11 is larger than 40 nm (for example, 100 nm)
  • the p-type channel layer 7 is entirely Since the inversion does not occur, holes flow through the p-type channel layer 7 and the amount of accumulated charges decreases.
  • the p-type channel layer 7 As shown in FIG. 7, when compared with the same collector current (Ic), the p-type channel layer 7 (surface semiconductor layer 4) has a thickness of 40 nm when the p-type channel layer 7 (surface semiconductor layer 4) has a thickness of 40 nm. It can be seen that the collector-emitter voltage (Vce) is lower and the on-voltage is lower than when the thickness of the transistor is 100 nm.
  • the thickness of the p-type channel layer 7 (surface semiconductor layer 4) is 10 nm to 15 nm, the thickness of the inversion layer formed in the p-type channel layer 7 becomes too thin, and resistance to the flow of electrons. Therefore, it becomes difficult for the electronic current to flow. From the above, it is considered that the thickness of the surface semiconductor layer 4 located below the gate electrode 11 from the upper surface of the buried insulating film 3 is desirably set in the range of 20 nm to 40 nm.
  • the thickness of the surface semiconductor layer 4 formed in each of the plurality of active regions AC gradually increases as the insulating film 6 is approached not only in the second direction but also in the first direction. Therefore, of the surface semiconductor layer 4 located under the gate electrode 11, the thickness of the surface semiconductor layer 4 located at both ends in the first direction of the active region AC is the region where the second opening 15 is formed ( The thickness of the surface semiconductor layer 4 in the region to which the source pad 16 is connected is substantially the same. However, the surface semiconductor layer 4 is located at both ends in the first direction and has a thickness substantially equal to the thickness of the surface semiconductor layer 4 in the region where the second opening 15 is formed (the region to which the source pad 16 is connected). Since the area is extremely small as compared with the entire area of the surface semiconductor layer 4 located under the gate electrode 11, the surface semiconductor layers 4 located at both ends in the first direction of the active region AC have the operating characteristics of the IGBT. Has little effect.
  • FIG. 42 is a principal part sectional view showing a part of the active part of the semiconductor chip in an enlarged manner (a principal part sectional view corresponding to the section along the line AA ′ shown in FIG. 2).
  • FIG. 16, FIG. 16, FIG. 19, FIG. 21, FIG. 25, FIG. 31, FIG. 33, FIGS. 35, 39, and 41 are enlarged plan views showing a part of the active portion of the semiconductor chip.
  • a high-resistance semiconductor substrate (hereinafter simply referred to as a substrate) 2A made of n ⁇ -type single crystal silicon is prepared.
  • the types of crystals forming the substrate 2A include FZ (Float Zoning) crystals manufactured by the floating zone method, CZ (Czochralski) crystals manufactured by the Czochralski method (pulling method), or MCZ (Magnetic Field Applied). Czochralski) crystals are preferred.
  • the surface oxide film 21 is formed on the main surface (surface) of the substrate 2A by subjecting the substrate 2A to thermal oxidation.
  • a p-type impurity for example, B (boron)
  • B boron
  • a p-type impurity for example, B (boron)
  • a photoresist film patterned by photolithography as a mask.
  • a plurality of p-type wells 23 are formed.
  • the substrate 2A is subjected to a thermal oxidation process to form a surface oxide film (not shown) on the main surface of the substrate 2A.
  • CVD on the surface oxide film
  • An oxide film (not shown) is deposited by a chemical vapor deposition method to form the surface oxide film and the insulating film 6 including the oxide film.
  • the thickness of the insulating film 6 is, for example, 300 nm to 650 nm.
  • an active region for example, a source layer, a channel layer, and an emitter layer (channel contact) is formed by isotropic wet etching using a photoresist film patterned by photolithography as a mask.
  • the insulating film 6 in a region to be a region where the layer) is formed is etched by, for example, about 200 nm.
  • the active region AC is defined on the main surface of the substrate 2A by the thick film portion of the insulating film 6 that has not been etched.
  • the region where the IGBT element of the active portion is formed, the region where the thick film portion of the insulating film 6 is formed and the region where the thin film portion of the insulating film 6 is formed are alternately striped. line up.
  • a thin film portion of the insulating film 6 is also formed in a region where the p + -type semiconductor layer 26 is formed later and in a region where the n-type guard ring 13 is formed later (see FIGS. 1 and 4).
  • the active region AC in which the IGBT element is formed has a long side in the first direction (the direction in which the gate electrode 11 extends) in the top view and a short side in the second direction orthogonal to the first direction. It is an area.
  • the width (W) along the second direction of the active region AC is, for example, 3 ⁇ m or more, and a typical value may be 7 ⁇ m to 8 ⁇ m. Further, the interval (S) between two active regions AC adjacent in the second direction is formed shorter than the width (W) along the second direction of the active region AC.
  • isotropic wet etching is used for etching the insulating film 6 described above. This is because the isotropic wet etching can etch the insulating film 6 with higher controllability than the dry etching, and can suppress variations in the thickness of the thin film portion of the insulating film 6. As will be described later, the thin film portion of the insulating film 6 constitutes the buried insulating film 3. However, the formation of the buried insulating film 3 having a uniform thickness makes it possible to change the characteristics of the IGBT due to variations in hole current. Can be suppressed. In practice, the corners of the active region AC are rounded, but for convenience, the corners of the active region AC are shown as straight lines.
  • a portion of the thin film portion of the insulating film 6 is etched using a photoresist film patterned by photolithography as a mask, so that the first opening (separating portion) 5 is formed.
  • the buried insulating film 3 which is a thin film portion of the insulating film 6 having the first opening 5 can be formed.
  • the surface of the substrate 2 ⁇ / b> A is exposed at the bottom surface of the first opening 5.
  • the first opening 5 is also formed in the thin film portion of the insulating film 6 in the region where the p + type semiconductor layer 26 will be formed later and the region where the n type guard ring 13 will be formed later (FIG. 1). And FIG. 4).
  • an n ⁇ -type single crystal whose specific resistance is substantially the same as that of the substrate 2A so that the silicon crystal continues from the first opening 5 of the buried insulating film 3 at the lattice level.
  • a silicon film 4A is formed by an epitaxial method. At this time, in order to prevent polycrystalline silicon from being deposited on the surface of the buried insulating film 3, the epitaxial film forming conditions having selectivity are set.
  • a means for supplying a mixed gas of SiHCl 3 (trichlorosilane) and HCl (hydrochloric acid) into the furnace using a carrier gas whose main component is H 2 (hydrogen) gas A means for supplying a mixed gas of SiH 2 Cl 2 (dichlorosilane) and HCl (hydrochloric acid) into the furnace using a carrier gas whose main component is H 2 (hydrogen) gas can be exemplified.
  • HCl gas has a light etching property with respect to the silicon crystal and can prevent the deposition of polycrystalline silicon on the buried insulating film 3.
  • the etching force of HCl gas is not strong enough to prevent the epitaxial film formation of crystalline silicon formed continuously from the crystal (substrate 2A) under the first opening 5, the first opening The selective epitaxial film formation from 5 becomes possible.
  • the n ⁇ -type single crystal silicon film 4A is polished by CMP (Chemical Mechanical Polishing) using the thick film portion of the insulating film 6 as a stopper (polishing end point) to form the active region AC.
  • the surface semiconductor layer 4 is formed.
  • the n ⁇ -type single crystal silicon film 4A is polished using polishing conditions in which so-called dishing (a phenomenon in which the central portion of the pattern is recessed in a dish shape) occurs.
  • the thickness from the main surface of the substrate 2A to the upper surface of the surface semiconductor layer 4 is the thinnest in the central portion of the active region AC surrounded by the thick film portion of the insulating film 6, and the thick film portion of the insulating film 6
  • the surface semiconductor layer 4 is formed so as to gradually increase as it approaches.
  • the thickness from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 located below the gate electrode 11 to be formed later is determined by the steady loss, turn-off time, and turn-off loss of the IGBT as described above. In order to reduce the thickness, it is formed to be 300 nm or less, or 100 nm or less, and more desirably in the range of 20 nm to 40 nm. In contrast, the thickness from the main surface of the substrate 2A to the upper surface of the surface semiconductor layer 4 in the region to which the source pad 16 to be formed later is connected (the total thickness of the buried insulating film 3 and the surface semiconductor layer 4). ) Is formed to be thicker than 300 nm, for example, in order to prevent the penetration of the second opening 15 to be formed later and to obtain a good connection between the source pad 16 and the surface semiconductor layer 4 to be formed later. Is done.
  • the appropriate thickness of the surface semiconductor layer 4 has been described above.
  • the surface of the surface semiconductor layer 4 is sacrificed in the process of forming the gate insulating film 10 by a predetermined thickness in a later process. Therefore, in this step, it is necessary to define the thickness of the surface semiconductor layer 4 in consideration of the thickness (including the thickness of the gate insulating film 10 itself) that is sacrificed in the step of forming the gate insulating film 10. There is. That is, in the step of forming the gate insulating film 10, before the gate insulating film 10 itself is formed, a sacrificial oxide film is formed on the surface of the surface semiconductor layer 4 by thermal oxidation in order to ion-implant impurities into the surface semiconductor layer 4.
  • the gate insulating film 10 is formed again on the surface of the surface semiconductor layer 4 by thermal oxidation treatment of the substrate 2A. That is, in consideration of the loss of the thickness of the surface semiconductor layer 4 by the thickness of the sacrificial oxide film and the gate insulating film 10, the thickness of the surface semiconductor layer 4 remaining after the CMP process must be specified. Don't be.
  • the gate insulating film of the IGBT is composed of a laminated film of an oxide film having a thickness of 10 nm formed by a thermal oxidation method and an oxide film having a thickness of 90 nm formed by a CVD method, a sacrificial oxide film and If the thickness of the gate insulating film 10 is 5 nm, in order to obtain the surface semiconductor layer 4 having a thickness of 20 nm to 40 nm after the gate insulating film 10 is formed, the thickness of the surface semiconductor layer 4 remaining after the CMP process is obtained. The thickness needs to be 30 nm to 50 nm.
  • the thickness of the surface semiconductor layer 4 remaining after the CMP process is determined by a step due to the insulating film 6, the thickness of the surface semiconductor layer 4 remaining after the CMP process is set to such a value. Needless to say, the buried insulating film 3 must be formed.
  • the p-type semiconductor layer 25 is formed by introducing a p-type impurity (for example, B (boron)) into the region to be the channel under the gate electrode 11 formed on the both sides of the gate electrode 11 by ion implantation.
  • a p-type impurity for example, B (boron)
  • the reason why the p-type semiconductor layer 25 is formed on the surface semiconductor layer 4 on which the IGBT element is formed before the gate electrode 11 is formed is as follows. That is, after the gate electrode 11 is formed and a gate electrode 11 is used as a mask and a p-type impurity is introduced into the surface semiconductor layer 4, in order to diffuse the impurity to a region to be a channel below the gate electrode 11, a high temperature is required. In addition, a long heat treatment is required. However, stress is applied to the thin film portion (embedded insulating film 3) of the insulating film 6 by this heat treatment and distortion occurs, resulting in a focus shift or a crystal defect in the photolithography technique. In order to avoid such a problem, the p-type semiconductor layer 25 is formed in the surface semiconductor layer 4 before the gate electrode 11 is formed in the active portion.
  • a part of the p-type semiconductor layer 25 is formed in the active portion using a photoresist film patterned by photolithography as a mask.
  • a p + -type emitter layer 9b is formed by introducing a p-type impurity (for example, B (boron)) into the region) by ion implantation.
  • a p-type impurity for example, B (boron)
  • the outer peripheral portion, impurities imparting p-type surface semiconductor layer 4 on the p-type field limiting rings 12 is introduced by ion implantation to form the p + -type semiconductor layer 26 (See FIG. 4).
  • the surface semiconductor layer 4 (the p-type semiconductor layer 25 and the p + -type emitter layer 9b in the active part and the p + -type semiconductor layer in the outer peripheral part) 26), a lower oxide film (not shown) is formed, and then an upper oxide film (not shown) is deposited on the lower oxide film by a CVD method to form a lower oxide film and an upper oxide film.
  • a gate insulating film 10 including a film is formed.
  • the thickness of the lower oxide film is, for example, 10 nm
  • the thickness of the upper oxide film is, for example, 90 nm.
  • a polycrystalline silicon film 27 is deposited on the main surface of the substrate 2A, and then a tungsten silicide layer 28 is formed on the polycrystalline silicon film 27.
  • the tungsten silicide layer 28 is formed in order to reduce the height of the gate electrode 11 and not increase the resistance of the gate electrode 11.
  • the tungsten silicide layer 28 and the polycrystalline silicon film 27 are sequentially patterned by etching using a photoresist film patterned by photolithography as a mask.
  • the gate electrode 11 which is a laminated film of the polycrystalline silicon film 27 and the tungsten silicide layer 28 can be formed.
  • a sacrificial oxide film 24 is formed on the exposed surface of the surface semiconductor layer 4 by subjecting the substrate 2A to thermal oxidation.
  • an n-type impurity for example, As (arsenic)
  • As (arsenic) is ionized in the p-type semiconductor layer 25 on both sides of the gate electrode 11 using a photoresist film patterned by photolithography as a mask.
  • the n ⁇ type source layer 8b is formed in a predetermined region by introducing by an implantation method.
  • the implantation energy and implantation amount of ion implantation are relatively low. Is set.
  • a silicon oxide film 30 is deposited on the main surface of the substrate 2A.
  • the silicon oxide film 30 is anisotropically dry-etched to form a sidewall SW that is to be the silicon oxide film 30 on the side surface of the gate electrode 11.
  • the n ⁇ type source layer 8b on both sides of the gate electrode 11 in the active part has an n-type impurity (for example, As (arsenic)) is introduced by ion implantation to form an n + type source layer 8a having an impurity concentration higher than that of the n ⁇ type source layer 8b.
  • the n - type source layer 8 including the n ⁇ -type source layer 8b and the n + -type source layer 8a is formed.
  • an n-type impurity for example, As (arsenic)
  • n-type guard ring channel stopper 13
  • FIG. 30 shows a mode in which the n + -type source layer 8a is formed from the upper surface of the surface semiconductor layer 4 to the lower surface in contact with the buried insulating film 3, but it is formed only on the upper surface side of the surface semiconductor layer 4. May be.
  • a p-type impurity (for example, in the p + -type emitter layer 9b on both sides of the gate electrode 11 of the active portion) is masked using a photoresist film patterned by photolithography as a mask.
  • B boron
  • B boron
  • a p-type emitter layer (p-type channel contact layer) 9 including the p + -type emitter layer 9b and the p + + type emitter layer 9a is formed.
  • FIG. 32 shows an embodiment in which the p ++ type emitter layer 9a is formed from the upper surface of the surface semiconductor layer 4 to the lower surface in contact with the buried insulating film 3, but it is formed only on the upper surface side of the surface semiconductor layer 4. May be.
  • the implantation amount is larger than that of the impurity ion implantation forming the n ⁇ -type source layer 8b.
  • the ion implantation of the impurity forming the p ++ type emitter layer 9a has a larger implantation amount than the ion implantation of the impurity forming the p + type emitter layer 9b.
  • Crystal defects can be prevented from occurring in the layer 4 and the gate insulating film 10. Further, even if crystal defects occur in the surface semiconductor layer 4 below the end portion of the sidewall SW, it is far from the side surface of the gate electrode 11 and therefore hardly affects the operation characteristics of the IGBT.
  • the n-type source layer 8 and the p-type emitter layer 9 are alternately arranged in one pattern extending in a strip shape between the gate electrode 11 and the thick film portion of the insulating film 6 in a top view. It will be. Further, the p-type semiconductor layer 25 under the gate electrode 11 where the n-type source layer 8 or the p-type emitter layer 9 is not formed constitutes the p-type channel layer 7.
  • the IGBT element according to the present embodiment can be formed through the above steps.
  • a nitride film 32 is formed on the main surface of the substrate 2A.
  • the nitride film 32 is, for example, a silicon nitride film, and the thickness thereof is, for example, 50 nm to 70 nm.
  • the nitride film 32 is etched using a photoresist film patterned by the photolithography technique as a mask to form a third opening 31 reaching the gate electrode 11.
  • a silicon oxide film 33 and a BPSG (Boron-PSG) film 34 are sequentially deposited on the main surface of the substrate 2A.
  • the thickness of the silicon oxide film 33 is, for example, 150 nm
  • the thickness of the BPSG film 34 is, for example, 400 nm to 500 nm.
  • heat treatment is performed on the substrate 2A.
  • the PSG film 35 is deposited on the BPSG film 34 to form the interlayer insulating film 14 including the nitride film 32, the silicon oxide film 33, the BGSP film 34, and the PSG film 35. .
  • the thickness of the PSG film 35 is, for example, 300 nm.
  • heat treatment is performed on the substrate 2A.
  • the interlayer insulating film 14 is etched, and in the active portion, each of the n + type source layer 8a and the p ++ type emitter layer 9a of the IGBT element and the gate electrode 11 is formed.
  • a second opening 15 is formed. In the outer peripheral portion, second openings 15 reaching the p + type semiconductor layer 26 and the n type guard ring 13 are formed (see FIGS. 3 and 4).
  • the PSG film 35, the BPSG film 34, and the silicon oxide film 33 are formed using a photoresist film patterned by photolithography as a mask and the nitride film 32 as an etching stopper. Are sequentially etched.
  • the third opening 31 is formed in a part of the nitride film 32 on the gate electrode 11 in the process described with reference to FIG. 35 described above, the tungsten silicide constituting the upper part of the gate electrode 11 is formed. A portion of layer 28 is exposed.
  • the nitride film 32 is etched using the photoresist film as a mask.
  • the etching of the PSG film 35, the BPSG film 34, and the silicon oxide film 33 in the nitride film 32 is once stopped, and then the nitride film 32 is etched to form the second opening 15. Therefore, the surface semiconductor layer 4 on which the n + -type source layer 8a and the p + + -type emitter layer 9a are formed, and the overetching amount of the thick film portion of the insulating film 6 (in the outer peripheral portion, the p + -type semiconductor layer 26 and the n-type The amount of overetching of the surface semiconductor layer 4 on which the guard ring 13 is formed (see FIGS. 3 and 4) can be made small.
  • the thickness from the main surface of the substrate 2A to the upper surface of the surface semiconductor layer 4 in the region where the second opening 15 is formed is, for example, It is formed thicker than 300 nm.
  • the second opening 15 extends through the n + -type source layer 8a and the p + + -type emitter layer 9a (in the outer periphery, the p + -type semiconductor layer 26 and the n-type guard ring 13 (see FIGS. 3 and 4)). Does not reach the substrate 2A.
  • the nitride film 32 is removed in advance. This is to avoid poor connection between the gate electrode 11 and the gate finger. That is, if an oxide film is formed between the tungsten silicide layer 28 and the nitride film 32 constituting the upper portion of the gate electrode 11, the second opening 15 is formed (after the nitride film 32 is removed). The oxide film may remain without being removed. If the oxide film remains, the contact resistance between the tungsten silicide layer 28 and the metal film constituting the gate finger increases. In order to prevent this, the nitride film 32 in the region where the second opening 15 connecting the gate electrode 11 and the gate finger to be formed later is formed is removed in advance.
  • the remaining oxide film can be removed by etching after the second opening 15 is formed (after the nitride film 32 is removed). However, at the same time, the thick film portion of the insulating film 6 is also etched, and the thickness of the thick film portion of the insulating film 6 cannot be maintained at a predetermined thickness.
  • an Al (aluminum) film is deposited on the main surface of the substrate 2A, for example, by sputtering.
  • the Al (aluminum) film is etched using a photoresist film patterned by photolithography as a mask, and the source pad is electrically connected to the n + type source layer 8a and the p + + type emitter layer 9a of the IGBT element.
  • (Source electrode) 16 is formed.
  • the following is formed.
  • the surface is formed on the main surface of the substrate 2A.
  • a polyimide film is deposited as a protective film.
  • openings reaching the source pad 16, the gate pad 17, the field limiting ring electrode 12A, and the guard ring electrode 13A are formed in the polyimide film. These openings divide the substrate 2A into individual semiconductor chips 1, and after the semiconductor chip 1 is mounted on the die pad of the lead frame, the source pads 16, the gate pads 17, and the field limiting ring electrodes 12A using bonding wires. And the guard ring electrode 13A are formed to be electrically connected to the corresponding leads.
  • a reinforcing material such as a foam double-sided tape or a glass reinforcing plate is attached to the main surface of the substrate 2A, and then the back surface of the substrate 2A is ground to form a base layer. 2 is formed.
  • the thickness of the base layer 2 is determined in accordance with the breakdown voltage of the IGBT.
  • the substrate is 60 ⁇ m to 100 ⁇ m when the breakdown voltage is 600V, and 120 ⁇ m to 150 ⁇ m when the breakdown voltage is 1200V. Grind the back of 2A. Since the reinforcing material is affixed to the main surface side of the substrate 2A, it is possible to prevent the substrate 2A from warping or drooping.
  • an n-type impurity for example, P (phosphorus)
  • a p-type impurity for example, B (boron)
  • an ion implantation method for example, using a laser annealing method.
  • an n + -type buffer layer 18 and a p-type collector layer 19 are formed.
  • the collector electrode 20 is formed by laminating an Al (aluminum) film, a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film in order from the p-type collector layer 19 by, for example, sputtering or vapor deposition. Can be formed.
  • the collector electrode 20 in which the Ni (nickel) film, the Ti (titanium) film, the Ni (nickel) film, and the Au (gold) film are stacked in order from the closest to the p-type collector layer 19 or the p-type collector layer 19
  • the collector electrode 20 may be formed by stacking a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film in order. Thereafter, the reinforcing material is removed.
  • the substrate 2A is cut into individual semiconductor chips 1 by cutting along the divided regions (dicing lines). Subsequently, after preparing a lead frame and mounting the singulated semiconductor chip 1 on a die pad of the lead frame, the source pad 16, the gate pad 17, the field limiting ring electrode 12A, and the guard using bonding wires Each of the ring electrodes 13A is electrically connected to the corresponding lead. Thereafter, the semiconductor chip 1, the lead frame, and the bonding wires are sealed with a sealing resin to manufacture the semiconductor device according to this embodiment.
  • the thickness from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 located under the gate electrode 11 is, for example, 300 nm or less, 100 nm or less, more preferably 20 nm.
  • the steady loss, turn-off time, and turn-off loss of the IGBT can be reduced.
  • the thickness from the upper surface of the base layer 2 to the upper surface of the surface semiconductor layer 4 in the region where the second opening 15 is formed (the region where the source pad 16 is connected) is formed to be thicker than 300 nm, for example. Yes.
  • the second opening 15 is formed in the interlayer insulating film 14 formed on the surface semiconductor layer 4, the second opening 15 is prevented from penetrating even if overetching is performed in order to avoid an opening defect. be able to. Thereby, since the source pad 16 and the base layer 2 are not connected, the malfunction of IBGT can be prevented.
  • the present invention can be applied to semiconductor devices employed in various inverters such as motor drive inverters in railway vehicles and hybrid cars, for example.

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Abstract

A surface semiconductor layer (4), on which a p-channel layer (7), an n-channel layer (8), and p-type emitter layer (9) are formed, is formed on a plurality of active areas. The thickness from the top surface of the base layer (2) to the top surface of the surface semiconductor layer (4) positioned below a gate electrode (11) is less than the thickness from the top surface of the base layer (2) to the top surface of the surface semiconductor layer (4) in the area in which a second opening part (15) is formed.

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置およびその製造技術に関し、特に、プレーナゲート型ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ：Insulated Gate Bipolar Transistor）を含む半導体装置およびその製造に適用して有効な技術に関するものである。 The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a semiconductor device including a planar gate IGBT (Insulated Gate Bipolar Transistor) and a technology effective when applied to the manufacturing thereof.
　例えば特開２０１０－６２２６２号公報（特許文献１）には、ベース層、開口部を備えた埋め込み絶縁膜、開口部下でベース層と接続する表面半導体層、表面半導体層に形成されたｐ型チャネル形成層とｎ＋型ソース層とｐ＋型エミッタ層、表面半導体層上にゲート絶縁膜を介して形成されたゲート電極、ｎ＋型バッファ層、およびｐ型コレクタ層等を有するＩＧＢＴが開示されている。そして、上記表面半導体層の厚さは、２０ｎｍ～１００ｎｍとする内容が記載されている。 For example, Japanese Patent Laying-Open No. 2010-62262 (Patent Document 1) discloses a base layer, a buried insulating film having an opening, a surface semiconductor layer connected to the base layer under the opening, and a p-type channel formed in the surface semiconductor layer. An IGBT having a formation layer, an n + -type source layer, a p + -type emitter layer, a gate electrode formed on a surface semiconductor layer via a gate insulating film, an n + -type buffer layer, a p-type collector layer, and the like is disclosed. ing. Further, it is described that the thickness of the surface semiconductor layer is 20 nm to 100 nm.
特開２０１０－６２２６２号公報JP 2010-62262 A
　ＩＧＢＴは、表面半導体層が、単結晶シリコンとされるベース層の主面（表面）上に、埋め込み絶縁膜を介してエピタキシャル法により形成されており、この表面半導体層にソース層、チャネル層、およびエミッタ層（チャネルコンタクト層）が形成される。ベース層と表面半導体層とは、埋め込み絶縁膜に形成された開口部（離間部）を通じて接続した構造となっている。また、埋め込み絶縁膜よりも厚い絶縁膜によってベース層の主面上では複数の活性領域が規定され、それらの複数の活性領域の各々に表面半導体層が形成されている。上記表面半導体層の厚さは、ＩＧＢＴの定常損失、ターンオフ時間、およびターンオフ損失を低減するために、１００ｎｍ以下、より望ましくは２０ｎｍ～４０ｎｍの範囲に設定されている（前述の特許文献１参照）。 In the IGBT, a surface semiconductor layer is formed on the main surface (surface) of a base layer made of single crystal silicon by an epitaxial method through a buried insulating film, and a source layer, a channel layer, And an emitter layer (channel contact layer) is formed. The base layer and the surface semiconductor layer have a structure connected through an opening (spaced portion) formed in the buried insulating film. A plurality of active regions are defined on the main surface of the base layer by an insulating film thicker than the buried insulating film, and a surface semiconductor layer is formed in each of the plurality of active regions. The thickness of the surface semiconductor layer is set to 100 nm or less, more preferably in the range of 20 nm to 40 nm in order to reduce the steady loss, turn-off time, and turn-off loss of the IGBT (see the above-mentioned Patent Document 1). .
　ところで、表面半導体層に電気的に接続するソースパッド（ソース電極）を形成する際には、まず、表面半導体層上に層間絶縁膜を形成し、この層間絶縁膜に表面半導体層に達する開口部を形成した後に、ソースパッドが形成される。しかしながら、耐圧を考慮すると、層間絶縁膜の厚さは、例えば６００ｎｍ程度必要であるが、表面半導体層の厚さは、例えば２０ｎｍ～１００ｎｍである。そのため、上記開口部の開口不良を回避するためにオーバエッチングを行うと、表面半導体層（ソース層およびエミッタ層）を貫通し、さらにその下の埋め込み絶縁膜を貫通して、開口部がベース層に達する場合がある。開口部がベース層に達すると、その開口部の内部に埋め込まれるソースパッドとベース層とが電気的に接続してＩＢＧＴの動作不良が生じ、その結果、ＩＧＢＴを含む半導体装置の製造歩留りが低下するという問題が生じる。 By the way, when forming a source pad (source electrode) electrically connected to the surface semiconductor layer, first, an interlayer insulating film is formed on the surface semiconductor layer, and an opening reaching the surface semiconductor layer in the interlayer insulating film. After forming, a source pad is formed. However, considering the breakdown voltage, the thickness of the interlayer insulating film needs to be about 600 nm, for example, while the thickness of the surface semiconductor layer is, for example, 20 nm to 100 nm. For this reason, when over-etching is performed to avoid an opening defect in the opening, the surface semiconductor layer (source layer and emitter layer) penetrates, and the buried insulating film below the surface semiconductor layer penetrates. May be reached. When the opening reaches the base layer, the source pad embedded in the opening and the base layer are electrically connected to each other to cause an operation failure of the IBGT, resulting in a decrease in manufacturing yield of the semiconductor device including the IGBT. Problem arises.
　本発明の目的は、ＩＧＢＴを含む半導体装置の特性を向上させることのできる技術を提供することにある。 An object of the present invention is to provide a technique capable of improving the characteristics of a semiconductor device including an IGBT.
　本発明の他の目的は、ＩＧＢＴを含む半導体装置の製造歩留りを向上させることのできる技術を提供することにある。 Another object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device including an IGBT.
　本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　本発明は、ＩＧＢＴの素子を含む半導体装置である。ＩＧＢＴの素子が形成される活性領域は、上面視において第１方向に長辺を有し、第１方向と直交する第２方向に短辺を有する領域である。そして、第２方向に沿った活性領域の断面において、ベース層の上面から、ゲート電極の下に位置する表面半導体層の上面までの厚さが、ベース層の上面から、ゲート電極を覆う層間絶縁膜の一部に形成された第２開口部が達する領域に位置する表面半導体層の上面までの厚さよりも薄いものである。言い換えるならば、埋め込み絶縁膜の第１開口部に対応する位置における埋め込み絶縁膜の上面から表面半導体層の上面までの厚さは、サイドウォールと接するゲート電極の端部に対応する位置における埋め込み絶縁膜の上面から表面半導体層の上面までの厚さよりも薄いものである。 The present invention is a semiconductor device including an IGBT element. The active region in which the IGBT element is formed is a region having a long side in the first direction and a short side in the second direction orthogonal to the first direction when viewed from above. Then, in the cross section of the active region along the second direction, the thickness from the upper surface of the base layer to the upper surface of the surface semiconductor layer located under the gate electrode is the interlayer insulation covering the gate electrode from the upper surface of the base layer The thickness is smaller than the thickness up to the upper surface of the surface semiconductor layer located in the region reached by the second opening formed in a part of the film. In other words, the thickness from the upper surface of the buried insulating film at the position corresponding to the first opening of the buried insulating film to the upper surface of the surface semiconductor layer is equal to the buried insulation at the position corresponding to the end of the gate electrode in contact with the sidewall. It is thinner than the thickness from the upper surface of the film to the upper surface of the surface semiconductor layer.
　また、本発明は、ＩＧＢＴの素子を備える半導体装置の製造方法である。基板の主面上に、第１厚さを有する薄膜部と、薄膜部を囲み、第１厚さよりも厚い第２厚さを有する厚膜部とを含む絶縁膜を形成した後、絶縁膜の薄膜部に基板に達する第１開口部を形成する。その後、絶縁膜の薄膜部上に表面半導体層を、第１開口部を埋め込んで形成するが、基板の主面から表面半導体層の上面までの厚さは、絶縁膜の厚膜部に囲まれた領域の中央部において最も薄く、絶縁膜の厚膜部に近づくに従い徐々に厚くなるように、表面半導体層は形成される。言い換えるならば、絶縁膜の上面から表面半導体層の上面までの厚さは、絶縁膜の厚膜部に囲まれた領域の中央部において薄く、絶縁膜の厚膜部に近づくに従い徐々に厚くなるように、表面半導体層が形成される。 Further, the present invention is a method for manufacturing a semiconductor device including an IGBT element. An insulating film including a thin film portion having a first thickness and a thick film portion surrounding the thin film portion and having a second thickness thicker than the first thickness is formed on the main surface of the substrate. A first opening reaching the substrate is formed in the thin film portion. Thereafter, the surface semiconductor layer is formed on the thin film portion of the insulating film by embedding the first opening. The thickness from the main surface of the substrate to the upper surface of the surface semiconductor layer is surrounded by the thick film portion of the insulating film. The surface semiconductor layer is formed so as to be the thinnest at the center of the region and gradually thicker as it approaches the thick film portion of the insulating film. In other words, the thickness from the upper surface of the insulating film to the upper surface of the surface semiconductor layer is thin at the center of the region surrounded by the thick film portion of the insulating film, and gradually increases as it approaches the thick film portion of the insulating film. Thus, a surface semiconductor layer is formed.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　ベース層の上面から、ゲート電極の下に位置する表面半導体層の上面までの厚さは、ベース層の上面から、ゲート電極を覆う層間絶縁膜の一部に形成された第２開口部が達する領域に位置する表面半導体層の上面までの厚さよりも薄いので、ＩＧＢＴの素子の特性を向上できる。言い換えるならば、埋め込み絶縁膜の第１開口部に対応する位置における埋め込み絶縁膜の上面から表面半導体層の上面までの厚さは、ゲート電極の端部に対応する位置における埋め込み絶縁膜の上面から表面半導体層の上面までの厚さよりも薄いので、ＩＧＢＴの素子の特性を向上できる。 The thickness from the upper surface of the base layer to the upper surface of the surface semiconductor layer located under the gate electrode reaches the second opening formed in a part of the interlayer insulating film covering the gate electrode from the upper surface of the base layer. Since the thickness of the surface semiconductor layer located in the region is thinner than the upper surface, the characteristics of the IGBT element can be improved. In other words, the thickness from the upper surface of the buried insulating film at the position corresponding to the first opening of the buried insulating film to the upper surface of the surface semiconductor layer is from the upper surface of the buried insulating film at the position corresponding to the end of the gate electrode. Since the thickness is smaller than the thickness up to the upper surface of the surface semiconductor layer, the characteristics of the IGBT element can be improved.
　また、ｎ型ベース層の上面から、ゲート電極を覆う層間絶縁膜の一部に形成された第２開口部が達する領域に位置する表面半導体層の上面までの厚さは、ｎ型ベース層の上面から、ゲート電極の下に位置する表面半導体層の上面までの厚さよりも厚く形成される。層間絶縁膜に第２開口部を形成する際、第２開口部の開口不良を回避するため、ある程度のオーバーエッチングを行った場合であっても、第２開口部が表面半導体層または埋め込み絶縁膜を貫通することを防止できる。そのため、ＩＧＢＴを含む半導体装置の製造歩留りを向上させることができる。言い換えるならば、絶縁膜の上面から表面半導体層の上面までの厚さは、絶縁膜の厚膜部に囲まれた領域の中央部において薄く、絶縁膜の厚膜部に近づくに従い徐々に厚くなるように、表面半導体層が形成される。そのため、ＩＧＢＴを含む半導体装置の製造歩留りを向上させることができる。 In addition, the thickness from the upper surface of the n-type base layer to the upper surface of the surface semiconductor layer located in the region reached by the second opening formed in a part of the interlayer insulating film covering the gate electrode is the thickness of the n-type base layer It is formed thicker than the thickness from the upper surface to the upper surface of the surface semiconductor layer located under the gate electrode. When the second opening is formed in the interlayer insulating film, even if a certain degree of over-etching is performed in order to avoid an opening defect in the second opening, the second opening is a surface semiconductor layer or a buried insulating film. Can be prevented. Therefore, the manufacturing yield of semiconductor devices including IGBT can be improved. In other words, the thickness from the upper surface of the insulating film to the upper surface of the surface semiconductor layer is thin at the center of the region surrounded by the thick film portion of the insulating film, and gradually increases as it approaches the thick film portion of the insulating film. Thus, a surface semiconductor layer is formed. Therefore, the manufacturing yield of semiconductor devices including IGBT can be improved.
本実施例によるＩＧＢＴを形成する半導体チップの要部平面図（活性部は、ＩＧＢＴの素子が形成される領域の一部を拡大して示す要部平面図）であり、ＩＧＢＴの素子のレイアウトを説明する要部平面図である。FIG. 2 is a plan view of a main part of a semiconductor chip forming an IGBT according to the present embodiment (an active part is a main part plan view showing an enlarged part of a region where an IGBT element is formed), and shows a layout of the IGBT element; It is a principal part top view to explain. 図１のＩＧＢＴの素子が形成される領域のみをさらに拡大して、ＩＧＢＴの素子のレイアウトを詳細に説明する要部平面図である。FIG. 2 is a main part plan view for explaining in detail a layout of an IGBT element by further enlarging only a region where the IGBT element of FIG. 1 is formed; 本実施例によるＩＧＢＴを形成する半導体チップの要部平面図（活性部は、ＩＧＢＴの素子が形成される領域の一部を拡大して示す要部平面図）であり、ＩＧＢＴの配線のレイアウトを説明する要部平面図である。FIG. 6 is a plan view of a main part of a semiconductor chip forming an IGBT according to the present embodiment (an active part is a main part plan view showing an enlarged part of a region where an IGBT element is formed), and shows a layout of the wiring of the IGBT; It is a principal part top view to explain. 本実施例によるＩＧＢＴを形成する半導体チップの活性部および外周部を示す要部断面図（活性部は、図２に示すＡ－Ａ′線に沿った断面に該当する要部断面図）である。FIG. 3 is an essential part cross-sectional view showing an active part and an outer peripheral part of a semiconductor chip forming an IGBT according to the present embodiment (the active part is an essential part cross-sectional view corresponding to a cross section along line AA ′ shown in FIG. 2); . 本実施例によるＩＧＢＴの素子の一部を拡大して示す要部断面図（図２に示すＢ－Ｂ′線に沿った断面に該当する要部断面図）である。FIG. 3 is an essential part cross-sectional view (a main part cross-sectional view corresponding to a cross section taken along the line BB ′ shown in FIG. 2) showing an enlarged part of the IGBT element according to the present embodiment. 本実施例によるＩＧＢＴの素子のチャネル層が反転した状態を説明する模式図である。（ａ）はチャネル層の厚さが４０ｎｍ以下の場合の模式図、（ｂ）はチャネル層の厚さが４０ｎｍよりも厚い場合（例えば１００ｎｍ）の模式図である。It is a schematic diagram explaining the state where the channel layer of the element of IGBT by a present Example was reversed. (A) is a schematic diagram when the thickness of a channel layer is 40 nm or less, (b) is a schematic diagram when the thickness of a channel layer is thicker than 40 nm (for example, 100 nm). 本実施例によるＩＧＢＴの素子のコレクタ電流（Ｉｃ）とコレクタ・エミッタ電圧（Ｖｃｅ）との関係を示すグラフ図である。It is a graph which shows the relationship between the collector current (Ic) of the element of IGBT by a present Example, and collector-emitter voltage (Vce). 本実施例によるＩＧＢＴを含む半導体装置の製造工程中の半導体チップの活性部の一部を拡大して示す要部断面図（図２に示すＡ－Ａ′線に沿った断面に該当する要部断面図）である。FIG. 2 is an essential part cross-sectional view showing an enlarged part of an active part of a semiconductor chip during a manufacturing process of a semiconductor device including an IGBT according to the present embodiment (main part corresponding to a cross section taken along line AA ′ shown in FIG. 2); FIG. 図８に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 9 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 8; 図９に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 10 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 9; 図１０に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 11 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 10; 図１０に続く、半導体装置の製造工程中の半導体チップの活性部の一部を拡大して示す要部平面図である。FIG. 11 is an essential part plan view illustrating a part of the active portion of the semiconductor chip in the process of manufacturing the semiconductor device, enlarged from FIG. 10; 図１１および図１２に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 13 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 11 and FIG. 12; 図１１および図１２に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 13 is a principal part plan view of the same place as in FIG. 12 in the process of manufacturing the semiconductor device, following FIG. 11 and FIG. 12; 図１３および図１４に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 15 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 13 and FIG. 14; 図１３および図１４に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 15 is a plan view of main parts of the same portions as those in FIG. 12 during the manufacturing process of the semiconductor device, following FIGS. 13 and 14; 図１５および図１６に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 17 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 15 and FIG. 16; 図１７に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 18 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 17; 図１７に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 18 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 17; 図１８および図１９に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 20 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 18 and FIG. 19; 図１８および図１９に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 20 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 18 and FIG. 19; 図２０および図２１に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 22 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 20 and FIG. 21; 図２２に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 23 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 22; 図２３に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 24 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 23; 図２３に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 24 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 23; 図２４および図２５に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 26 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 24 and FIG. 25; 図２６に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 27 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 26; 図２７に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 28 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 27; 図２８に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 29 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 28; 図２９に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 30 is an essential part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 29; 図２９に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 30 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 29; 図３０および図３１に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 32 is a main-portion cross-sectional view of the same portion as shown in FIG. 8 in the manufacturing process of the semiconductor device, which is subsequent to FIGS. 30 and 31; 図３０および図３１に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 33 is a plan view of main parts of the same portions as those in FIG. 12 during the manufacturing process of the semiconductor device, following FIGS. 30 and 31; 図３２および図３３に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 34 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 32 and FIG. 33; 図３４に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 35 is an essential part plan view of the same place in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 34; 図３５に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 36 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 35; 図３６に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 37 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 36; 図３７に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 38 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 37; 図３７に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 38 is a principal part plan view of the same place as in FIG. 12 in the process of manufacturing the semiconductor device, following FIG. 37; 図３８および図３９に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 40 is a principal part cross-sectional view of the same place as in FIG. 8 in the process of manufacturing the semiconductor device, following FIG. 38 and FIG. 39; 図３８および図３９に続く、半導体装置の製造工程中の図１２と同じ個所の要部平面図である。FIG. 40 is a principal part plan view of the same point in FIG. 12 during the manufacturing process of the semiconductor device, following FIG. 38 and FIG. 39; 図４０および図４１に続く、半導体装置の製造工程中の図８と同じ個所の要部断面図である。FIG. 42 is a main-portion cross-sectional view of the same portion as shown in FIG. 8 in the manufacturing process of the semiconductor device, which is subsequent to FIGS. 40 and 41;
　以下の実施の形態において、便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。 In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.
　また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。 Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
　また、材料等について言及するときは、特にそうでない旨明記したとき、または、原理的または状況的にそうでないときを除く、特定した材料は主要な材料であって、副次的要素、添加物、添加要素等を排除するものではない。例えばシリコン部材は特に明示した場合等を除き、純粋なシリコンの場合だけでなく、添加不純物、シリコンを主要な要素とする２元、３元等の合金（例えばＳｉＧｅ）等を含むものとする。また、以下の実施の形態において、窒化シリコン、窒化ケイ素またはシリコンナイトライドというときは、Ｓｉ３Ｎ４は勿論であるが、それのみではなく、シリコンの窒化物で類似組成の絶縁膜を含むものとする。 In addition, when referring to materials, etc., the specified material is a major material, and it is a sub-element, additive, unless otherwise specified or unless otherwise specified in principle or circumstances. However, this does not exclude added elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (eg, SiGe) having silicon as a main element, and the like. In the following embodiments, when referring to silicon nitride, silicon nitride, or silicon nitride, not only Si 3 N 4 but also silicon nitride is used and includes an insulating film having a similar composition. .
　また、以下の実施の形態で用いる図面においては、平面図であっても図面を見易くするためにハッチングを付す場合もある。また、以下の実施の形態を説明するための全図において、同一機能を有するものは原則として同一の符号を付し、その繰り返しの説明は省略する。以下、本発明の実施の形態を図面に基づいて詳細に説明する。 Also, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　≪半導体装置≫
　本実施例によるプレーナゲート型ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ：Insulated Gate Bipolar Transistor）を含む半導体装置について図１～図７を用いて説明する。図１はＩＧＢＴを形成する半導体チップの要部平面図（活性部は、ＩＧＢＴの素子が形成される領域の一部を拡大して示す要部平面図）であり、ＩＧＢＴの素子のレイアウトを説明する要部平面図である。図２はＩＧＢＴの素子が形成される領域のみをさらに拡大して、ＩＧＢＴの素子のレイアウトを詳細に説明する要部平面図である。図３はＩＧＢＴを形成する半導体チップの要部平面図（活性部は、ＩＧＢＴの素子が形成される領域の一部を拡大して示す要部平面図）であり、ＩＧＢＴの配線のレイアウトを説明する要部平面図である。図４はＩＧＢＴを形成する半導体チップの活性部および外周部を示す要部断面図（活性部は、図２に示すＡ－Ａ′線に沿った断面に該当する要部断面図）である。図５はＩＧＢＴの素子の一部を拡大して示す要部断面図（図２に示すＢ－Ｂ′線に沿った断面に該当する要部断面図）である。図６はＩＧＢＴの素子のチャネル層が反転した状態を説明する模式図であり、（ａ）はチャネル層の厚さが４０ｎｍ以下の場合の模式図、（ｂ）はチャネル層の厚さが４０ｎｍよりも厚い場合（例えば１００ｎｍ）の模式図である。図７はＩＧＢＴの素子のコレクタ電流（Ｉｃ）とコレクタ・エミッタ電圧（Ｖｃｅ）との関係を示すグラフ図である。 ≪Semiconductor device≫
A semiconductor device including a planar gate IGBT (Insulated Gate Bipolar Transistor) according to this embodiment will be described with reference to FIGS. FIG. 1 is a plan view of a main part of a semiconductor chip forming an IGBT (an active part is an enlarged plan view of a main part showing a part of a region where an IGBT element is formed) and describes the layout of the IGBT element. It is a principal part top view to do. FIG. 2 is a plan view of an essential part for explaining in detail the layout of the IGBT element by further enlarging only the region where the IGBT element is formed. FIG. 3 is a plan view of a main part of a semiconductor chip forming the IGBT (the active part is a main part plan view showing a part of a region where an IGBT element is formed), and the layout of the IGBT wiring is described. It is a principal part top view to do. FIG. 4 is a principal part sectional view showing an active part and an outer peripheral part of the semiconductor chip forming the IGBT (the active part is a principal part sectional view corresponding to a section taken along the line AA ′ shown in FIG. 2). FIG. 5 is an essential part cross-sectional view showing a part of the IGBT element in an enlarged manner (main part cross-sectional view corresponding to the cross section along the line BB ′ shown in FIG. 2). 6A and 6B are schematic diagrams for explaining a state in which the channel layer of the IGBT element is inverted. FIG. 6A is a schematic diagram when the thickness of the channel layer is 40 nm or less, and FIG. 6B is a schematic diagram when the thickness of the channel layer is 40 nm. It is a schematic diagram when it is thicker (for example, 100 nm). FIG. 7 is a graph showing the relationship between the collector current (Ic) of the IGBT element and the collector-emitter voltage (Vce).
　図１、図２、図３、および図４に示すように、半導体チップ１の活性部には、ＩＧＢＴの素子が形成されている。このＩＧＢＴの素子は、例えばｎ－型の単結晶シリコンとされるベース層２の主面（表面）上に、埋め込み絶縁膜（薄膜部）３を介して、ｎ－型の単結晶シリコンとされる複数の表面半導体層４が形成され、ベース層２と表面半導体層４とは、埋め込み絶縁膜３に形成された第１開口部（離間部）５を通じて接続した構造となっている。また、上記埋め込み絶縁膜３よりも厚い複数の絶縁膜（厚膜部）６によってベース層２の主面上では複数の活性領域ＡＣが規定され、複数の活性領域ＡＣの各々に上記表面半導体層４が形成されている。 As shown in FIGS. 1, 2, 3, and 4, an IGBT element is formed in the active portion of the semiconductor chip 1. This IGBT element is made of n − type single crystal silicon via a buried insulating film (thin film portion) 3 on the main surface (surface) of the base layer 2 made of n − type single crystal silicon, for example. A plurality of surface semiconductor layers 4 are formed, and the base layer 2 and the surface semiconductor layer 4 are connected through a first opening (spaced portion) 5 formed in the buried insulating film 3. A plurality of active regions AC are defined on the main surface of the base layer 2 by a plurality of insulating films (thick film portions) 6 thicker than the buried insulating film 3, and the surface semiconductor layer is formed in each of the plurality of active regions AC. 4 is formed.
　ベース層２の厚さは、例えば７０μｍ～１００μｍであるが、これはＩＧＢＴの耐圧に合わせて決定されるものであり、耐圧６００Ｖであれば６０μｍ～１００μｍとし、耐圧１２００Ｖであれば１２０μｍ～１５０μｍとすることを例示できる。 The thickness of the base layer 2 is, for example, 70 μm to 100 μm, which is determined according to the breakdown voltage of the IGBT, and is 60 μm to 100 μm when the breakdown voltage is 600V, and 120 μm to 150 μm when the breakdown voltage is 1200V. Can be exemplified.
　また、埋め込み絶縁膜３の厚さ（第１厚さ）は、例えば１００ｎｍ～４５０ｎｍであり、絶縁膜６の厚さ（第２厚さ）は３００ｎｍよりも厚く、例えば５５０ｎｍ～６５０ｎｍである。埋め込み絶縁膜３および絶縁膜６は、埋め込み絶縁膜３および絶縁膜６の下のベース層２に空乏層を深く延ばして高耐圧を得るために、薄く形成されることが望ましい。一方で、埋め込み絶縁膜３および絶縁膜６の厚さが薄いと、後に説明するように、層間絶縁膜に第２開口部を形成する際に、埋め込み絶縁膜３および絶縁膜６を貫通する危険性がある。そのため、埋め込み絶縁膜３および絶縁膜６には、貫通を回避するための厚さも必要とされる。従って、埋め込み絶縁膜３および絶縁膜６の厚さは、耐圧と加工マージンとのトレードオフから決まる。本実施例では、埋め込み絶縁膜３および絶縁膜６の厚さの一例として、上記数値を示したが、これらに限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 Further, the thickness (first thickness) of the buried insulating film 3 is, for example, 100 nm to 450 nm, and the thickness (second thickness) of the insulating film 6 is thicker than 300 nm, for example, 550 nm to 650 nm. The buried insulating film 3 and the insulating film 6 are desirably formed thin in order to extend the depletion layer deeply to the base layer 2 under the buried insulating film 3 and the insulating film 6 to obtain a high breakdown voltage. On the other hand, if the buried insulating film 3 and the insulating film 6 are thin, there is a risk of penetrating the buried insulating film 3 and the insulating film 6 when the second opening is formed in the interlayer insulating film, as will be described later. There is sex. Therefore, the buried insulating film 3 and the insulating film 6 are also required to have a thickness for avoiding penetration. Therefore, the thicknesses of the buried insulating film 3 and the insulating film 6 are determined by a trade-off between the breakdown voltage and the processing margin. In the present embodiment, the above numerical values are shown as an example of the thicknesses of the buried insulating film 3 and the insulating film 6. However, the present invention is not limited thereto, and various changes can be made without departing from the scope of the invention. Needless to say.
　ＩＧＢＴの素子が形成される活性領域ＡＣは、上面視において第１方向（図１および図２のｂ方向）に長辺を有し、第１方向と直交する第２方向（図１および図２のｃ方向）に短辺を有した領域である。また、活性領域ＡＣは、上面視において第２方向に一定の幅（図１に符号Ｗで示す幅）を有して、第１方向に帯状に延在するパターンであり、複数の活性領域ＡＣはストライプ状に配置されている。なお、実際には、例えば７００程度の活性領域ＡＣが第２方向に沿って互いに離間して形成されているが、便宜上、図１には、１６個の活性領域ＡＣのみを拡大して記載している。 The active region AC in which the IGBT element is formed has a long side in the first direction (the b direction in FIGS. 1 and 2) in a top view, and a second direction (FIGS. 1 and 2) orthogonal to the first direction. This is a region having a short side in the c direction). The active region AC is a pattern having a certain width in the second direction (width indicated by a symbol W in FIG. 1) in the top view and extending in a strip shape in the first direction, and includes a plurality of active regions AC. Are arranged in stripes. Actually, for example, about 700 active regions AC are formed apart from each other along the second direction, but for convenience, only 16 active regions AC are shown in an enlarged manner in FIG. ing.
　また、活性領域ＡＣの第２方向に沿った幅（Ｗ）は、例えば３μｍ以上であり、代表的な値としては７μｍ～８μｍを例示することができる。また、第２方向に隣り合う２つの活性領域ＡＣの間隔（図１に符号Ｓで示す間隔）、すなわち、第２方向に沿った絶縁膜６の幅は、活性領域ＡＣの第２方向に沿った幅（Ｗ）よりも短く形成されている。 Further, the width (W) along the second direction of the active region AC is, for example, 3 μm or more, and a typical value may be 7 μm to 8 μm. Further, the interval between two active regions AC adjacent to each other in the second direction (the interval indicated by symbol S in FIG. 1), that is, the width of the insulating film 6 along the second direction is along the second direction of the active region AC. It is shorter than the width (W).
　埋め込み絶縁膜３上の表面半導体層４には、ｐ型チャネル層７、ｎ＋型ソース層８ａとｎ－型ソース層８ｂとを含むｎ型ソース層８、およびｐ＋＋型エミッタ層９ａとｐ＋型エミッタ層９ｂとを含むｐ型エミッタ層（ｐ型チャネルコンタクト層）９が形成されている。ｎ＋型ソース層８ａ中の不純物濃度はｎ－型ソース層８ｂ中の不純物濃度よりも高くなっており、ｐ型チャネル層７側（ｐ型チャネル層７とｎ＋型ソース層８ａとの間）にｎ－型ソース層８ｂが形成されている。また、ｐ＋＋型エミッタ層９ａ中の不純物濃度はｐ＋型エミッタ層９ｂ中の不純物濃度よりも高く、ｐ＋型エミッタ層９ｂ中の不純物濃度はｐ型チャネル層７中の不純物濃度よりも高くなっており、ｐ型チャネル層７側（ｐ型チャネル層７とｐ＋＋型エミッタ層９ａとの間）にｐ＋エミッタ層９ｂが形成されている。 The surface semiconductor layer 4 on the buried insulating film 3 includes a p-type channel layer 7, an n-type source layer 8 including an n + -type source layer 8 a and an n − -type source layer 8 b, and p ++ -type emitter layers 9 a and p A p-type emitter layer (p-type channel contact layer) 9 including a + -type emitter layer 9b is formed. The impurity concentration in the n + -type source layer 8a is higher than the impurity concentration in the n − -type source layer 8b, and is on the p-type channel layer 7 side (between the p-type channel layer 7 and the n + -type source layer 8a). ) Is formed with an n − -type source layer 8b. Further, the impurity concentration in the p ++ type emitter layer 9 a is higher than the impurity concentration in the p + type emitter layer 9 b, and the impurity concentration in the p + type emitter layer 9 b is higher than the impurity concentration in the p type channel layer 7. The p + emitter layer 9b is formed on the p type channel layer 7 side (between the p type channel layer 7 and the p + + type emitter layer 9a).
　各表面半導体層４上には、ゲート絶縁膜１０を介してゲート電極１１が形成（パターニング）されている。ゲート電極１１は、上面視において第１方向に帯状に延在するパターンであり、複数のゲート電極１１はストライプ状に配置されている。ゲート電極１１は、例えば下から順に多結晶シリコン膜２７およびタングステンシリサイド層２８が堆積された積層膜によって構成される。 A gate electrode 11 is formed (patterned) on each surface semiconductor layer 4 via a gate insulating film 10. The gate electrode 11 is a pattern extending in a strip shape in the first direction when viewed from above, and the plurality of gate electrodes 11 are arranged in stripes. The gate electrode 11 is constituted by, for example, a laminated film in which a polycrystalline silicon film 27 and a tungsten silicide layer 28 are deposited in order from the bottom.
　上記ｎ型ソース層８および上記ｐエミッタ層９は、上面視において第１方向に沿って並べて形成されるが、同一断面の中に形成することは不可能である。そのため、上面視においてゲート電極１１と絶縁膜６との間の帯状に延在する１本のパターンの中で、ｎ型ソース層８とｐ型エミッタ層９とが第１方向に交互に配置されている。また、ｎ型ソース層８の平面面積を、ｐ型エミッタ層９の平面面積よりも小さくすることによって破壊耐量を高くしている。上記ｐ型チャネル層７は、ゲート電極１１と埋め込み絶縁膜３との間に形成されている。また、ｐ型チャネル層７はｐ型エミッタ層９と接続して、電位が固定されているので、寄生ＭＯＳ（Metal Oxide Semiconductor）が形成されることによる特性劣化を防止することができる。 The n-type source layer 8 and the p emitter layer 9 are formed side by side along the first direction in a top view, but cannot be formed in the same cross section. Therefore, the n-type source layer 8 and the p-type emitter layer 9 are alternately arranged in the first direction in one pattern extending in a band shape between the gate electrode 11 and the insulating film 6 in a top view. ing. Further, the breakdown area is increased by making the plane area of the n-type source layer 8 smaller than the plane area of the p-type emitter layer 9. The p-type channel layer 7 is formed between the gate electrode 11 and the buried insulating film 3. Further, since the p-type channel layer 7 is connected to the p-type emitter layer 9 and the potential is fixed, it is possible to prevent deterioration of characteristics due to formation of a parasitic MOS (Metal Oxide Semiconductor).
　ゲート電極１１の側面には、サイドウォールＳＷが形成されている。ゲート電極１１をマスクとしてゲート電極１１の側面下の表面導体層４に高濃度の不純物をイオン注入すると、その後の熱処理によって、ゲート電極１１の側面下の表面導体層４に結晶欠陥が発生することが懸念された。そこで、ゲート電極１１の側面にサイドウォールＳＷを形成し、サイドウォールＳＷをマスクとしてサイドウォールＳＷの端部下の表面導体層４に高濃度不純物をイオン注入することにより、ゲート電極１１の側面下の表面半導体層４に結晶欠陥が発生するのを防止している。すなわち、ゲート電極１１の側面下近傍の表面導体層４にはｎ－型ソース層８ｂを形成し、サイドウォールＳＷの端部下近傍の表面導体層４にはｎ＋型ソース層８ａを形成する。同様に、ゲート電極１１の側面下近傍の表面導体層４にはｐ＋型エミッタ層９ｂを形成し、サイドウォールＳＷの端部下近傍の表面導体層４にはｐ＋＋型エミッタ層９ａを形成する。 Sidewalls SW are formed on the side surfaces of the gate electrode 11. When high concentration impurities are ion-implanted into the surface conductor layer 4 below the side surface of the gate electrode 11 using the gate electrode 11 as a mask, crystal defects are generated in the surface conductor layer 4 below the side surface of the gate electrode 11 by the subsequent heat treatment. There was concern. Therefore, a sidewall SW is formed on the side surface of the gate electrode 11, and high concentration impurities are ion-implanted into the surface conductor layer 4 below the end of the sidewall SW using the sidewall SW as a mask. Crystal defects are prevented from occurring in the surface semiconductor layer 4. That is, the n − -type source layer 8b is formed on the surface conductor layer 4 near the side surface of the gate electrode 11, and the n + -type source layer 8a is formed on the surface conductor layer 4 near the edge of the sidewall SW. Similarly, the surface conductor layer 4 side under the vicinity of the gate electrode 11 to form a p + -type emitter layer 9b, the surface conductor layer 4 below the end near the sidewall SW forming the p ++ type emitter layer 9a .
　活性部の複数の厚い絶縁膜６下のベース層２内には、ｐ型ウェル２３が形成されている。ｐ型チャネル層７とベース層２とのｐｎ接合部からベース層２へ空乏層が拡がることにより接合耐圧を保たせているが、補助的にｐ型ウェル２３を設けることにより、さらに接合耐圧を上げることが可能となる。 A p-type well 23 is formed in the base layer 2 below the plurality of thick insulating films 6 in the active portion. Although the depletion layer extends from the pn junction between the p-type channel layer 7 and the base layer 2 to the base layer 2, the junction breakdown voltage is maintained. However, by additionally providing the p-type well 23, the junction breakdown voltage is further reduced. It is possible to raise.
　半導体チップ１の外周部には、上面視において上記活性部を囲むように複数のｐ型フィールドリミッティングリング（Field Limiting Ring）１２が形成され、さらにそれら複数のｐ型フィールドリミッティングリング１２を囲むようにｎ型ガードリング（チャネルストッパ）１３が形成されている。 A plurality of p-type field limiting rings (Field Limiting Ring) 12 are formed on the outer peripheral portion of the semiconductor chip 1 so as to surround the active portion in a top view, and further surround the plurality of p-type field limiting rings 12. Thus, an n-type guard ring (channel stopper) 13 is formed.
　ｐ型フィールドリミッティングリング１２は、ベース層２内にｐ型を示す不純物が導入されて形成されている。また、ｐ型フィールドリミッティングリング１２は、埋め込み絶縁膜３に形成された第１開口部５を通じて、ｐ型を示す不純物が導入されたｐ＋型半導体層２６（上記表面半導体層４と同様に形成されて、ｐ＋型エミッタ層９ｂ中の不純物濃度と同程度の不純物濃度を有する）と接続した構造となっており、フィールドリミッティングリング電極１２Ａによって電圧が固定されている。図１では、２本のｐ型フィールドリミッティングリング１２が形成されている例を図示しているが、さらに多数形成してもよい。上記のような複数本のｐ型フィールドリミッティングリング１２を形成することにより、電界が複数本のｐ型フィールドリミッティングリング１２によって分担されるので、本実施例によるＩＧＢＴを高耐圧とすることが可能となる。 The p-type field limiting ring 12 is formed by introducing a p-type impurity into the base layer 2. In addition, the p-type field limiting ring 12 is a p + -type semiconductor layer 26 into which an impurity indicating p-type is introduced through the first opening 5 formed in the buried insulating film 3 (similar to the surface semiconductor layer 4 described above). And has a structure connected to an impurity concentration similar to that in the p + -type emitter layer 9b), and the voltage is fixed by the field limiting ring electrode 12A. Although FIG. 1 shows an example in which two p-type field limiting rings 12 are formed, a larger number may be formed. By forming the plurality of p-type field limiting rings 12 as described above, the electric field is shared by the plurality of p-type field limiting rings 12, so that the IGBT according to this embodiment can have a high breakdown voltage. It becomes possible.
　複数のｐ型フィールドリミッティングリング１２を取り囲むように形成されたｎ型ガードリング１３は、半導体ウエハから半導体チップ１が個片化された後で半導体チップ１中のＩＧＢＴの素子を保護する機能を有する。ｎ型ガードリング１３は、上記表面半導体層４と同様に形成され、ｎ型を示す不純物が導入された構造となっており、ガードリング電極１３Ａによって電圧が固定されている。ｎ型ガードリング１３は、ｎ＋型ソース層８ａ中の不純物濃度と同程度の不純物濃度を有する。 The n-type guard ring 13 formed so as to surround the plurality of p-type field limiting rings 12 has a function of protecting the IGBT elements in the semiconductor chip 1 after the semiconductor chip 1 is separated from the semiconductor wafer. Have. The n-type guard ring 13 is formed in the same manner as the surface semiconductor layer 4 and has an n-type impurity introduced therein, and the voltage is fixed by the guard ring electrode 13A. The n-type guard ring 13 has an impurity concentration comparable to the impurity concentration in the n + -type source layer 8a.
　さらに、半導体チップ１の活性部および外周部には、ＩＧＢＴの素子、ｐ型フィールドリミッティングリング１２、およびｎ型ガードリング１３を覆うように層間絶縁膜１４が形成されている。層間絶縁膜１４は、例えば下から順に窒化膜３２、酸化シリコン膜３３、ＢＰＳＧ（Boron-Phospho Silicate Glass）膜３４、およびＰＳＧ（Phospho Silicate Glass）膜３５が順次堆積された積層膜によって構成される。この層間絶縁膜１４には、ｎ型ソース層８およびｐ型エミッタ層９、ゲート電極１１、ｐ＋型半導体層２６、ならびにｎ型ガードリング１３に達する第２開口部１５がそれぞれ形成されている。 Further, an interlayer insulating film 14 is formed on the active part and the outer peripheral part of the semiconductor chip 1 so as to cover the IGBT element, the p-type field limiting ring 12 and the n-type guard ring 13. For example, the interlayer insulating film 14 is configured by a laminated film in which a nitride film 32, a silicon oxide film 33, a BPSG (Boron-Phospho Silicate Glass) film 34, and a PSG (Phospho Silicate Glass) film 35 are sequentially deposited from the bottom. . In the interlayer insulating film 14, an n-type source layer 8 and a p-type emitter layer 9, a gate electrode 11, a p + -type semiconductor layer 26, and a second opening 15 reaching the n-type guard ring 13 are formed. .
　これら第２開口部１５が形成された状況下で、層間絶縁膜１４上にはｎ型ソース層８およびｐ型エミッタ層９と電気的に接続するソースパッド（ソース電極）１６と、ゲート電極１１と電気的に接続するゲートパッド１７とが、互いに離間して形成される。さらに、ｐ＋型半導体層２６と電気的に接続するフィールドリミッティングリング電極１２Ａと、ｎ型ガードリング１３と電気的に接続するガードリング電極１３Ａとが、互いに離間して形成されている。これらソースパッド１６等は、例えばＡｌ（アルミニウム）等から形成されている。また、活性部の周囲（ＩＧＢＴの素子が形成された領域と外周部との間の領域）には、ソースパッド１６と連続してソース引き回し電極１６Ａが形成されている。ソース引き回し電極１６Ａは、その下の層間絶縁膜１４に形成された第２開口部（図示は省略）を通じて活性部の周囲に形成されたｐ＋＋型エミッタ層（図示は省略）と接続している。また、活性部の中央部および活性部の第１方向（図３のｂ方向）の両端部には、第２方向に延在する帯状のゲートフィンガー１７Ａが形成されている。ゲートフィンガー１７Ａは、その下の層間絶縁膜１４に形成された第２開口部１５を通じてゲート電極１１と電気的に接続し、ゲートパッド１７と連続して形成されている。 Under the condition that these second openings 15 are formed, a source pad (source electrode) 16 electrically connected to the n-type source layer 8 and the p-type emitter layer 9 on the interlayer insulating film 14, and the gate electrode 11 Gate pads 17 that are electrically connected to each other are formed apart from each other. Further, a field limiting ring electrode 12A electrically connected to the p + -type semiconductor layer 26 and a guard ring electrode 13A electrically connected to the n-type guard ring 13 are formed apart from each other. These source pads 16 and the like are made of, for example, Al (aluminum). Further, around the active portion (region between the region where the IGBT element is formed and the outer peripheral portion), a source leading electrode 16A is formed continuously with the source pad 16. The source routing electrode 16A is connected to a p ++ type emitter layer (not shown) formed around the active portion through a second opening (not shown) formed in the interlayer insulating film 14 below the source leading electrode 16A. . In addition, strip-shaped gate fingers 17A extending in the second direction are formed at both ends of the central portion of the active portion and both ends of the active portion in the first direction (the b direction in FIG. 3). The gate finger 17 </ b> A is electrically connected to the gate electrode 11 through the second opening 15 formed in the interlayer insulating film 14 thereunder, and is formed continuously with the gate pad 17.
　さらに、図示は省略するが、ソースパッド１６等を覆うようにポリイミド膜が形成されており、そのポリイミド膜には、ソースパッド１６の一部の表面およびゲートパッド１７の一部の表面をそれぞれ露出する開口部が形成されている。これら開口部は、半導体チップ１の外部と、ソースパッド１６およびゲートパッド１７とを電気的に接続するためのボンディングワイヤを接続するためのボンディングパッドとなる。なお、必要に応じては、ガードリング電極１３Ａの一部の表面を露出する開口部を上記ポリイミド膜に形成することもある。 Further, although not shown, a polyimide film is formed so as to cover the source pad 16 and the like, and a part of the surface of the source pad 16 and a part of the surface of the gate pad 17 are exposed on the polyimide film. An opening is formed. These openings serve as bonding pads for connecting a bonding wire for electrically connecting the outside of the semiconductor chip 1 to the source pad 16 and the gate pad 17. If necessary, an opening for exposing a part of the surface of the guard ring electrode 13A may be formed in the polyimide film.
　ベース層２の裏面には、ベース層２に近い順からｎ＋型バッファ層１８、ｐ型コレクタ層１９、およびコレクタ電極２０が形成されている。スイッチング速度を速くし、スイッチング損失を減らすためには、裏面からの正孔注入量を減らすことが望ましく、ｐ型コレクタ層１９に導入されているｐ型を示す不純物の濃度を低くする必要がある。しかし、不純物濃度が低いことに起因してｐ型コレクタ層１９の比抵抗は高くなる。そのため、ｐ型コレクタ層１９が有する直列抵抗成分を下げるために薄く形成することが求められ、その厚さは、例えば５μｍ以下とすることが好ましい。さらに、ｐ型コレクタ層１９に導入されているｐ型を示す不純物であるＢ（ホウ素）の拡散係数が小さいことを考慮した場合には、ｐ型コレクタ層１９の厚さは、例えば１μｍ以下とすることが好ましい。 On the back surface of the base layer 2, an n + -type buffer layer 18, a p-type collector layer 19, and a collector electrode 20 are formed in order from the base layer 2. In order to increase the switching speed and reduce the switching loss, it is desirable to reduce the amount of holes injected from the back surface, and it is necessary to reduce the concentration of the p-type impurity introduced into the p-type collector layer 19. . However, the specific resistance of the p-type collector layer 19 increases due to the low impurity concentration. Therefore, in order to reduce the series resistance component of the p-type collector layer 19, it is required to form it thinly, and the thickness is preferably, for example, 5 μm or less. Further, considering that the diffusion coefficient of B (boron), which is an impurity indicating p-type introduced into the p-type collector layer 19, is small, the thickness of the p-type collector layer 19 is, for example, 1 μm or less. It is preferable to do.
　コレクタ電極２０は、以下の（１）、（２）、または（３）の金属膜から形成することができる。 The collector electrode 20 can be formed from the following metal film (1), (2), or (3).
　（１）ｐ型コレクタ層１９に近い順からＡｌ（アルミニウム）膜、Ｔｉ（チタン）膜、Ｎｉ（ニッケル）膜、およびＡｕ（金）膜を積層した金属膜。 (1) A metal film in which an Al (aluminum) film, a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film are stacked in order from the p-type collector layer 19.
　（２）ｐ型コレクタ層１９に近い順からＮｉ（ニッケル）膜、Ｔｉ（チタン）膜、Ｎｉ（ニッケル）膜、およびＡｕ（金）膜を積層した金属膜。 (2) A metal film in which a Ni (nickel) film, a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film are stacked in order from the p-type collector layer 19.
　（３）ｐ型コレクタ層１９に近い順からＴｉ（チタン）膜、Ｎｉ（ニッケル）膜、およびＡｕ（金）膜積層した金属膜。 (3) A metal film in which a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film are stacked in order from the p-type collector layer 19.
　なお、図１においては、図面を便宜上、半導体チップ１を長方形として記載しているが、実際には、半導体チップ１の第１方向（ｂ方向）に沿う長さは１ｃｍとされ、半導体チップ１の第２方向（ｃ方向）に沿う長さは１ｃｍとされる。また、半導体チップ１の第１方向（ｂ方向）に沿うチップ端部から活性部（活性領域ＡＣ）までの距離は２００μｍ～３００μｍとされ、半導体チップ１の第２方向（ｃ方向）に沿うチップ端部から活性部（活性領域ＡＣ）までの距離は２００μｍ～３００μｍとされる。すなわち、半導体チップ１の外周部は、半導体チップ１の４辺に、２００μｍ～３００μｍにわたって配置される。従って、図４では、理解を容易化するために、活性部と外周部とを連続的に記載しているが、図４の外周部の幅は、２００μｍ～３００μｍとされている。 In FIG. 1, the semiconductor chip 1 is illustrated as a rectangle for convenience of illustration, but actually, the length along the first direction (b direction) of the semiconductor chip 1 is 1 cm. The length along the second direction (c direction) is 1 cm. Further, the distance from the chip end along the first direction (b direction) of the semiconductor chip 1 to the active part (active region AC) is 200 μm to 300 μm, and the chip along the second direction (c direction) of the semiconductor chip 1. The distance from the end portion to the active portion (active region AC) is 200 μm to 300 μm. That is, the outer peripheral portion of the semiconductor chip 1 is disposed on the four sides of the semiconductor chip 1 over 200 μm to 300 μm. Therefore, in FIG. 4, the active portion and the outer peripheral portion are continuously described for easy understanding, but the width of the outer peripheral portion in FIG. 4 is 200 μm to 300 μm.
　本発明の技術的特徴は、複数の活性領域ＡＣの各々に形成された表面半導体層４の厚さにある。図５に示すように、ｐ型チャネル層７、ｎ型ソース層８、およびｐ型エミッタ層９が形成された表面半導体層４の厚さは一定ではなく、ベース層２の上面から表面半導体層４の上面までの厚さは、活性領域ＡＣの中央部において最も薄く、絶縁膜６に近づくに従い徐々に厚くなるように、表面半導体層４は形成されている。すなわち、第２方向に沿った活性領域ＡＣの断面において、ベース層２の上面から、ゲート電極１１の下に位置する表面半導体層４の上面までの厚さ（Ｌ１）が、ベース層２の上面から、第２開口部１５が形成された領域に位置する表面半導体層４の上面までの厚さ（Ｌ２）よりも薄く形成されている。言い換えるならば、埋め込み絶縁膜３の第１開口部５に対応する位置における埋め込み絶縁膜３の上面から表面半導体層４の上面までの厚さ（Ｌ３）は、サイドウォールＳＷに接するゲート電極１１の端部に対応する位置における埋め込み絶縁膜３の上面から表面半導体層４の上面までの厚さ（Ｌ４）よりも薄く（Ｌ３＜Ｌ４）形成される。 The technical feature of the present invention resides in the thickness of the surface semiconductor layer 4 formed in each of the plurality of active regions AC. As shown in FIG. 5, the thickness of the surface semiconductor layer 4 on which the p-type channel layer 7, the n-type source layer 8, and the p-type emitter layer 9 are formed is not constant. The surface semiconductor layer 4 is formed so that the thickness up to the upper surface of 4 is the thinnest at the center of the active region AC and gradually increases as it approaches the insulating film 6. That is, in the cross section of the active region AC along the second direction, the thickness (L1) from the upper surface of the base layer 2 to the upper surface of the surface semiconductor layer 4 located under the gate electrode 11 is the upper surface of the base layer 2. To a thickness (L2) from the surface semiconductor layer 4 located in the region where the second opening 15 is formed to the upper surface. In other words, the thickness (L3) from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 at the position corresponding to the first opening 5 of the buried insulating film 3 is the thickness of the gate electrode 11 in contact with the sidewall SW. It is formed thinner than the thickness (L4) from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 at a position corresponding to the end (L3 <L4).
　埋め込み絶縁膜３の上面から、ゲート電極１１の下に位置する表面半導体層４（ｐ型チャネル層７およびｐ＋型エミッタ層９ｂの一部が形成された領域）の上面までの厚さは、ＩＧＢＴの定常損失、ターンオフ時間、およびターンオフ損失を考慮して設定されており、例えば３００ｎｍ以下が適切な範囲と考えられる（他の条件によってはこの範囲に限定されないことはもとよりである）。また、量産に適した範囲としては１００ｎｍ以下が考えられるが、さらに２０ｎｍ～４０ｎｍの範囲が最も好適と考えられる。 The thickness from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 (a region where part of the p-type channel layer 7 and the p + -type emitter layer 9b is formed) located under the gate electrode 11 is It is set in consideration of the steady loss, turn-off time, and turn-off loss of the IGBT. For example, 300 nm or less is considered to be an appropriate range (which is not limited to this range depending on other conditions). Further, a range suitable for mass production is considered to be 100 nm or less, but a range of 20 nm to 40 nm is considered most preferable.
　これに対し、ベース層２の上面から、第２開口部１５が形成された領域に位置する表面半導体層４の上面までの厚さ（Ｌ２）は、第２開口部１５の突き抜けを防止して、ソースパッド１６と表面半導体層４との良好な接続を得るために、例えば３００ｎｍよりも厚く形成されている。 In contrast, the thickness (L2) from the upper surface of the base layer 2 to the upper surface of the surface semiconductor layer 4 located in the region where the second opening 15 is formed prevents penetration of the second opening 15. In order to obtain a good connection between the source pad 16 and the surface semiconductor layer 4, the source pad 16 is formed to be thicker than 300 nm, for example.
　埋め込み絶縁膜３の上面から、ゲート電極１１の下に位置する表面半導体層４の厚さを、より望ましくは２０ｎｍ～４０ｎｍの範囲に設定する理由について、図６および図７を用いて説明する。 The reason why the thickness of the surface semiconductor layer 4 located below the gate electrode 11 from the upper surface of the buried insulating film 3 is more desirably set in the range of 20 nm to 40 nm will be described with reference to FIGS.
　図６（ａ）に示すように、ゲート電極１１に、例えば＋１５Ｖのゲート電圧を加えると、ｐ型チャネル層７に電子が集まり反転層が形成されてｐ型チャネル層７はｎ型の導電性を有する。ゲート電極１１下のｐ型チャネル層７（表面半導体層４）の厚さが４０ｎｍ以下の場合は、ｐ型チャネル層７が全て反転するため、正孔は流れることができずに蓄積されて、蓄積電荷量が増加する。その結果、電子がクーロン力により引っ張られて電子電流は増加し、正孔電流は減少する。 As shown in FIG. 6A, when a gate voltage of, for example, +15 V is applied to the gate electrode 11, electrons are collected in the p-type channel layer 7 to form an inversion layer, and the p-type channel layer 7 has n-type conductivity. Have When the thickness of the p-type channel layer 7 (surface semiconductor layer 4) under the gate electrode 11 is 40 nm or less, all the p-type channel layer 7 is inverted, so that holes cannot flow and are accumulated, The amount of stored charge increases. As a result, electrons are pulled by the Coulomb force, the electron current increases, and the hole current decreases.
　一方、図６（ｂ）に示すように、ゲート電極１１下のｐ型チャネル層７（表面半導体層４）の厚さが４０ｎｍよりも厚い場合（例えば１００ｎｍ）は、ｐ型チャネル層７が全て反転しないため、正孔がｐ型チャネル層７を流れて蓄積電荷量が減少する。 On the other hand, as shown in FIG. 6B, when the thickness of the p-type channel layer 7 (surface semiconductor layer 4) under the gate electrode 11 is larger than 40 nm (for example, 100 nm), the p-type channel layer 7 is entirely Since the inversion does not occur, holes flow through the p-type channel layer 7 and the amount of accumulated charges decreases.
　図７に示すように、同じコレクタ電流（Ｉｃ）で比べると、ｐ型チャネル層７（表面半導体層４）の厚さが４０ｎｍの場合の方が、ｐ型チャネル層７（表面半導体層４）の厚さが１００ｎｍの場合よりもコレクタ・エミッタ電圧（Ｖｃｅ）は低くなり、オン電圧が低くなることが分かる。 As shown in FIG. 7, when compared with the same collector current (Ic), the p-type channel layer 7 (surface semiconductor layer 4) has a thickness of 40 nm when the p-type channel layer 7 (surface semiconductor layer 4) has a thickness of 40 nm. It can be seen that the collector-emitter voltage (Vce) is lower and the on-voltage is lower than when the thickness of the transistor is 100 nm.
　しかし、ｐ型チャネル層７（表面半導体層４）の厚さが１０ｎｍ～１５ｎｍになると、ｐ型チャネル層７に形成される反転層の厚さが薄くなりすぎて、電子の流れに対して抵抗を持つため、電子電流が流れにくくなる。以上のことから、埋め込み絶縁膜３の上面から、ゲート電極１１の下に位置する表面半導体層４の厚さは２０ｎｍ～４０ｎｍの範囲に設定することが望ましいと考えられる。 However, when the thickness of the p-type channel layer 7 (surface semiconductor layer 4) is 10 nm to 15 nm, the thickness of the inversion layer formed in the p-type channel layer 7 becomes too thin, and resistance to the flow of electrons. Therefore, it becomes difficult for the electronic current to flow. From the above, it is considered that the thickness of the surface semiconductor layer 4 located below the gate electrode 11 from the upper surface of the buried insulating film 3 is desirably set in the range of 20 nm to 40 nm.
　ところで、複数の活性領域ＡＣの各々に形成された表面半導体層４の厚さは、第２方向のみでなく第１方向においても絶縁膜６に近づくに従い徐々に厚くなる。そのため、ゲート電極１１の下に位置する表面半導体層４のうち、活性領域ＡＣの第１方向の両端部に位置する表面半導体層４の厚さは、第２開口部１５が形成される領域（ソースパッド１６が接続される領域）の表面半導体層４の厚さとほぼ同じ厚さとなる。しかし、第１方向の両端部に位置し、第２開口部１５が形成される領域（ソースパッド１６が接続される領域）の表面半導体層４の厚さとほぼ同じ厚さとなる表面半導体層４の面積は、ゲート電極１１の下に位置する表面半導体層４全体の面積に比べて極めて小さいことから、活性領域ＡＣの第１方向の両端部に位置する表面半導体層４は、ＩＧＢＴの動作特性にはほとんど影響を及ぼさない。 Incidentally, the thickness of the surface semiconductor layer 4 formed in each of the plurality of active regions AC gradually increases as the insulating film 6 is approached not only in the second direction but also in the first direction. Therefore, of the surface semiconductor layer 4 located under the gate electrode 11, the thickness of the surface semiconductor layer 4 located at both ends in the first direction of the active region AC is the region where the second opening 15 is formed ( The thickness of the surface semiconductor layer 4 in the region to which the source pad 16 is connected is substantially the same. However, the surface semiconductor layer 4 is located at both ends in the first direction and has a thickness substantially equal to the thickness of the surface semiconductor layer 4 in the region where the second opening 15 is formed (the region to which the source pad 16 is connected). Since the area is extremely small as compared with the entire area of the surface semiconductor layer 4 located under the gate electrode 11, the surface semiconductor layers 4 located at both ends in the first direction of the active region AC have the operating characteristics of the IGBT. Has little effect.
　≪半導体装置の製造方法≫
　本実施例によるＩＧＢＴを含む半導体装置の製造方法について図８～図４２を用いて工程順に説明する。図８～図１１、図１３、図１５、図１７、図１８、図２０、図２２～図２４、図２６～図３０、図３２、および図３４、図３６～図３８、図４０、および図４２は半導体チップの活性部の一部を拡大して示す要部断面図（前述の図２に示すＡ－Ａ′線に沿った断面に該当する要部断面図）である。図１２、図１４、図１６、図１９、図２１、図２５、図３１、図３３、図３５、図３９、および図４１は半導体チップの活性部の一部を拡大して示す要部平面図である。 ≪Semiconductor device manufacturing method≫
A method for manufacturing a semiconductor device including an IGBT according to this embodiment will be described in the order of steps with reference to FIGS. 8 to 11, 13, 15, 15, 17, 18, 20, 22 to 24, 26 to 30, 32, and 34, 36 to 38, 40, and FIG. 42 is a principal part sectional view showing a part of the active part of the semiconductor chip in an enlarged manner (a principal part sectional view corresponding to the section along the line AA ′ shown in FIG. 2). 12, FIG. 16, FIG. 16, FIG. 19, FIG. 21, FIG. 25, FIG. 31, FIG. 33, FIGS. 35, 39, and 41 are enlarged plan views showing a part of the active portion of the semiconductor chip. FIG.
　まず、図８に示すように、ｎ－型の単結晶シリコンとされる高抵抗の半導体基板（以下、単に基板と記す）２Ａを用意する。基板２Ａを形成する結晶の種類としては、フローティングゾーン法で製造されたＦＺ（Float Zoning）結晶、またはチョクラルスキー法（引き上げ法）で製造されたＣＺ（Czochralski）結晶、またはＭＣＺ（Magnetic Field Applied Czochralski）結晶が望ましい。 First, as shown in FIG. 8, a high-resistance semiconductor substrate (hereinafter simply referred to as a substrate) 2A made of n − -type single crystal silicon is prepared. The types of crystals forming the substrate 2A include FZ (Float Zoning) crystals manufactured by the floating zone method, CZ (Czochralski) crystals manufactured by the Czochralski method (pulling method), or MCZ (Magnetic Field Applied). Czochralski) crystals are preferred.
　次に、基板２Ａに熱酸化処理を施すことによって、基板２Ａの主面（表面）に表面酸化膜２１を形成する。 Next, the surface oxide film 21 is formed on the main surface (surface) of the substrate 2A by subjecting the substrate 2A to thermal oxidation.
　次に、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして、基板２Ａの主面の外周部にｐ型を示す不純物（例えばＢ（ホウ素））をイオン注入法により導入し、複数のｐ型フィールドリミッティングリング１２を形成する（図１および図４参照）。 Next, a p-type impurity (for example, B (boron)) is introduced into the outer peripheral portion of the main surface of the substrate 2A by an ion implantation method using a photoresist film patterned by a photolithography technique as a mask, and a plurality of p-types are introduced. A field limiting ring 12 is formed (see FIGS. 1 and 4).
　次に、図９に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして、基板２Ａの主面の活性部にｐ型を示す不純物（例えばＢ（ホウ素））をイオン注入法により導入し、複数のｐ型ウェル２３を形成する。 Next, as shown in FIG. 9, a p-type impurity (for example, B (boron)) is ion-implanted into the active portion of the main surface of the substrate 2A using a photoresist film patterned by photolithography as a mask. Introducing, a plurality of p-type wells 23 are formed.
　次に、図１０に示すように、基板２Ａに熱酸化処理を施すことによって、基板２Ａの主面に表面酸化膜（図示は省略）を形成し、続いて、この表面酸化膜上にＣＶＤ（Chemical Vapor Deposition）法により酸化膜（図示は省略）を堆積して、上記表面酸化膜および上記酸化膜を含む絶縁膜６を形成する。絶縁膜６の厚さは、例えば３００ｎｍ～６５０ｎｍである。 Next, as shown in FIG. 10, the substrate 2A is subjected to a thermal oxidation process to form a surface oxide film (not shown) on the main surface of the substrate 2A. Subsequently, CVD (on the surface oxide film) An oxide film (not shown) is deposited by a chemical vapor deposition method to form the surface oxide film and the insulating film 6 including the oxide film. The thickness of the insulating film 6 is, for example, 300 nm to 650 nm.
　次に、図１１および図１２に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとした等方性ウエットエッチングにより、活性領域（例えばソース層、チャネル層、およびエミッタ層（チャネルコンタクト層）が形成される領域）となる領域の絶縁膜６を、例えば２００ｎｍ程度エッチングする。これにより、エッチングされなかった絶縁膜６の厚膜部によって基板２Ａの主面では活性領域ＡＣが規定される。本実施例では、活性部のＩＧＢＴの素子が形成される領域では、絶縁膜６の厚膜部が形成された領域と、絶縁膜６の薄膜部が形成された領域とが交互にストライプ状に並ぶ。同時に、外周部では、後にｐ＋型半導体層２６が形成される領域および後にｎ型ガードリング１３が形成される領域にも絶縁膜６の薄膜部を形成する（図１および図４参照）。 Next, as shown in FIGS. 11 and 12, an active region (for example, a source layer, a channel layer, and an emitter layer (channel contact) is formed by isotropic wet etching using a photoresist film patterned by photolithography as a mask. The insulating film 6 in a region to be a region where the layer) is formed is etched by, for example, about 200 nm. Thus, the active region AC is defined on the main surface of the substrate 2A by the thick film portion of the insulating film 6 that has not been etched. In this embodiment, in the region where the IGBT element of the active portion is formed, the region where the thick film portion of the insulating film 6 is formed and the region where the thin film portion of the insulating film 6 is formed are alternately striped. line up. At the same time, in the outer peripheral portion, a thin film portion of the insulating film 6 is also formed in a region where the p + -type semiconductor layer 26 is formed later and in a region where the n-type guard ring 13 is formed later (see FIGS. 1 and 4).
　ＩＧＢＴの素子が形成される活性領域ＡＣは、上面視において第１方向（ゲート電極１１が延在する方向）に長辺を有し、第１方向と直交する第２方向に短辺を有した領域である。活性領域ＡＣの第２方向に沿った幅（Ｗ）は、例えば３μｍ以上であり、代表的な値としては７μｍ～８μｍを例示することができる。また、第２方向に隣り合う２つの活性領域ＡＣの間隔（Ｓ）は、活性領域ＡＣの第２方向に沿った幅（Ｗ）よりも短く形成されている。 The active region AC in which the IGBT element is formed has a long side in the first direction (the direction in which the gate electrode 11 extends) in the top view and a short side in the second direction orthogonal to the first direction. It is an area. The width (W) along the second direction of the active region AC is, for example, 3 μm or more, and a typical value may be 7 μm to 8 μm. Further, the interval (S) between two active regions AC adjacent in the second direction is formed shorter than the width (W) along the second direction of the active region AC.
　また、本実施例では、上述の絶縁膜６のエッチングに等方性ウエットエッチングを用いている。これは、等方性ウエットエッチングはドライエッチングよりも絶縁膜６を制御性よくエッチングできるので、絶縁膜６の薄膜部の厚さのばらつきを抑えることができるからである。後述するように、絶縁膜６の薄膜部は埋め込み絶縁膜３を構成するが、均一な厚さを有する埋め込み絶縁膜３が形成されることにより、正孔電流のばらつきに起因するＩＧＢＴの特性変動を抑えることができる。なお、実際には、活性領域ＡＣの角部は丸くなるが、便宜上、活性領域ＡＣの角部は直線で記載している。 In this embodiment, isotropic wet etching is used for etching the insulating film 6 described above. This is because the isotropic wet etching can etch the insulating film 6 with higher controllability than the dry etching, and can suppress variations in the thickness of the thin film portion of the insulating film 6. As will be described later, the thin film portion of the insulating film 6 constitutes the buried insulating film 3. However, the formation of the buried insulating film 3 having a uniform thickness makes it possible to change the characteristics of the IGBT due to variations in hole current. Can be suppressed. In practice, the corners of the active region AC are rounded, but for convenience, the corners of the active region AC are shown as straight lines.
　次に、図１３および図１４に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして絶縁膜６の薄膜部の一部をエッチングして、第１開口部（離間部）５を形成する。これにより、第１開口部５を備えた絶縁膜６の薄膜部とされる埋め込み絶縁膜３を形成することができる。このとき、第１開口部５の底面には基板２Ａの表面が露出する。同時に、外周部では、後にｐ＋型半導体層２６が形成される領域および後にｎ型ガードリング１３が形成される領域の絶縁膜６の薄膜部にも第１開口部５を形成する（図１および図４参照）。 Next, as shown in FIGS. 13 and 14, a portion of the thin film portion of the insulating film 6 is etched using a photoresist film patterned by photolithography as a mask, so that the first opening (separating portion) 5 is formed. Form. Thereby, the buried insulating film 3 which is a thin film portion of the insulating film 6 having the first opening 5 can be formed. At this time, the surface of the substrate 2 </ b> A is exposed at the bottom surface of the first opening 5. At the same time, in the outer peripheral portion, the first opening 5 is also formed in the thin film portion of the insulating film 6 in the region where the p + type semiconductor layer 26 will be formed later and the region where the n type guard ring 13 will be formed later (FIG. 1). And FIG. 4).
　次に、図１５および図１６に示すように、埋め込み絶縁膜３の第１開口部５からシリコン結晶が格子レベルで連続するように、比抵抗が基板２Ａとほぼ同じであるｎ－型単結晶シリコン膜４Ａをエピタキシャル法により成膜する。この時、埋め込み絶縁膜３の表面に多結晶シリコンが堆積しないようにするために、選択性を有するエピタキシャル成膜条件とする。すなわち、基板２Ａをエピタキシャル炉に導入してから、主成分がＨ２（水素）ガスのキャリアガスを用い、ＳｉＨＣｌ３（トリクロロシラン）およびＨＣｌ（塩酸）の混合ガスを炉内に供給する手段や、主成分がＨ２（水素）ガスのキャリアガスを用い、ＳｉＨ２Ｃｌ２（ジクロロシラン）およびＨＣｌ（塩酸）の混合ガスを炉内に供給する手段を例示することができる。エピタキシャル炉内に導入するガスのうち、ＨＣｌガスは、シリコン結晶に対して軽いエッチング性を有しており、埋め込み絶縁膜３上に多結晶シリコンが堆積してしまうことを阻止することができる。しかし、ＨＣｌガスのエッチング力は、第１開口部５下の結晶（基板２Ａ）から連続して成膜される結晶シリコンのエピタキシャル成膜を阻止するほどの強いエッチング力ではないので、第１開口部５からの選択エピタキシャル成膜が可能となる。 Next, as shown in FIGS. 15 and 16, an n − -type single crystal whose specific resistance is substantially the same as that of the substrate 2A so that the silicon crystal continues from the first opening 5 of the buried insulating film 3 at the lattice level. A silicon film 4A is formed by an epitaxial method. At this time, in order to prevent polycrystalline silicon from being deposited on the surface of the buried insulating film 3, the epitaxial film forming conditions having selectivity are set. That is, after introducing the substrate 2A into the epitaxial furnace, a means for supplying a mixed gas of SiHCl 3 (trichlorosilane) and HCl (hydrochloric acid) into the furnace using a carrier gas whose main component is H 2 (hydrogen) gas, A means for supplying a mixed gas of SiH 2 Cl 2 (dichlorosilane) and HCl (hydrochloric acid) into the furnace using a carrier gas whose main component is H 2 (hydrogen) gas can be exemplified. Of the gases introduced into the epitaxial furnace, HCl gas has a light etching property with respect to the silicon crystal and can prevent the deposition of polycrystalline silicon on the buried insulating film 3. However, since the etching force of HCl gas is not strong enough to prevent the epitaxial film formation of crystalline silicon formed continuously from the crystal (substrate 2A) under the first opening 5, the first opening The selective epitaxial film formation from 5 becomes possible.
　次に、図１７に示すように、絶縁膜６の厚膜部をストッパ（研磨終点）としたＣＭＰ（Chemical Mechanical Polishing）法によりｎ－型単結晶シリコン膜４Ａを研磨して、活性領域ＡＣに表面半導体層４を形成する。ここで、いわゆるディッシング（Dishing：パターンの中央部が皿状に窪む現象）が生じる研磨条件を用いてｎ－型単結晶シリコン膜４Ａを研磨する。これにより、基板２Ａの主面から表面半導体層４の上面までの厚さが、絶縁膜６の厚膜部に囲まれた活性領域ＡＣの中央部において最も薄く、絶縁膜６の厚膜部に近づくに従い徐々に厚くなるように、表面半導体層４は形成される。 Next, as shown in FIG. 17, the n − -type single crystal silicon film 4A is polished by CMP (Chemical Mechanical Polishing) using the thick film portion of the insulating film 6 as a stopper (polishing end point) to form the active region AC. The surface semiconductor layer 4 is formed. Here, the n − -type single crystal silicon film 4A is polished using polishing conditions in which so-called dishing (a phenomenon in which the central portion of the pattern is recessed in a dish shape) occurs. As a result, the thickness from the main surface of the substrate 2A to the upper surface of the surface semiconductor layer 4 is the thinnest in the central portion of the active region AC surrounded by the thick film portion of the insulating film 6, and the thick film portion of the insulating film 6 The surface semiconductor layer 4 is formed so as to gradually increase as it approaches.
　すなわち、埋め込み絶縁膜３の上面から、後に形成されるゲート電極１１の下に位置する表面半導体層４の上面までの厚さは、前述したように、ＩＧＢＴの定常損失、ターンオフ時間、およびターンオフ損失を低減するために、３００ｎｍ以下、または１００ｎｍ以下、より望ましくは２０ｎｍ～４０ｎｍの範囲となるように形成される。これに対し、基板２Ａの主面から、後に形成されるソースパッド１６が接続される領域の表面半導体層４の上面までの厚さ（埋め込み絶縁膜３と表面半導体層４との合計の厚さ）は、後に形成される第２開口部１５の突き抜けを防止して、後に形成されるソースパッド１６と表面半導体層４との良好な接続を得るために、例えば３００ｎｍよりも厚くなるように形成される。 That is, the thickness from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 located below the gate electrode 11 to be formed later is determined by the steady loss, turn-off time, and turn-off loss of the IGBT as described above. In order to reduce the thickness, it is formed to be 300 nm or less, or 100 nm or less, and more desirably in the range of 20 nm to 40 nm. In contrast, the thickness from the main surface of the substrate 2A to the upper surface of the surface semiconductor layer 4 in the region to which the source pad 16 to be formed later is connected (the total thickness of the buried insulating film 3 and the surface semiconductor layer 4). ) Is formed to be thicker than 300 nm, for example, in order to prevent the penetration of the second opening 15 to be formed later and to obtain a good connection between the source pad 16 and the surface semiconductor layer 4 to be formed later. Is done.
　本実施例において、表面半導体層４の適切な厚さを前述したが、後の工程で表面半導体層４の表面は、所定の厚さだけゲート絶縁膜１０の形成工程で犠牲となってしまうことから、本工程では、そのゲート絶縁膜１０の形成工程で犠牲となってしまう厚さ分（ゲート絶縁膜１０の厚さ自体も含む）を考慮して表面半導体層４の厚さを規定する必要がある。すなわち、ゲート絶縁膜１０の形成工程では、ゲート絶縁膜１０自体を形成する前に、表面半導体層４に不純物をイオン注入するために、熱酸化法によって表面半導体層４の表面に犠牲酸化膜を形成し、その犠牲酸化膜を除去した後で改めて基板２Ａの熱酸化処理によって表面半導体層４の表面にゲート絶縁膜１０を形成する。つまり、犠牲酸化膜およびゲート絶縁膜１０の厚さ分だけ表面半導体層４の厚さが失われてしまうことを考慮して、上記ＣＭＰ工程後に残る表面半導体層４の厚さを規定しなければならない。 In the present embodiment, the appropriate thickness of the surface semiconductor layer 4 has been described above. However, the surface of the surface semiconductor layer 4 is sacrificed in the process of forming the gate insulating film 10 by a predetermined thickness in a later process. Therefore, in this step, it is necessary to define the thickness of the surface semiconductor layer 4 in consideration of the thickness (including the thickness of the gate insulating film 10 itself) that is sacrificed in the step of forming the gate insulating film 10. There is. That is, in the step of forming the gate insulating film 10, before the gate insulating film 10 itself is formed, a sacrificial oxide film is formed on the surface of the surface semiconductor layer 4 by thermal oxidation in order to ion-implant impurities into the surface semiconductor layer 4. After the formation and removal of the sacrificial oxide film, the gate insulating film 10 is formed again on the surface of the surface semiconductor layer 4 by thermal oxidation treatment of the substrate 2A. That is, in consideration of the loss of the thickness of the surface semiconductor layer 4 by the thickness of the sacrificial oxide film and the gate insulating film 10, the thickness of the surface semiconductor layer 4 remaining after the CMP process must be specified. Don't be.
　例えばＩＧＢＴのゲート絶縁膜を、熱酸化法により形成される１０ｎｍの厚さの酸化膜と、ＣＶＤ法により形成される９０ｎｍの厚さの酸化膜との積層膜により構成した場合、犠牲酸化膜およびゲート絶縁膜１０の厚さ分をそれぞれ５ｎｍとすると、ゲート絶縁膜１０を形成した後に２０ｎｍ～４０ｎｍの厚さの表面半導体層４を得るためには、そのＣＭＰ工程後に残る表面半導体層４の厚さを、３０ｎｍ～５０ｎｍとする必要がある。また、このＣＭＰ工程後に残る表面半導体層４の厚さは、絶縁膜６による段差で決定されるものであるから、ＣＭＰ工程後に残る表面半導体層４の厚さがそのような値となるように埋め込み絶縁膜３を形成しなければならないことは言うまでもない。 For example, when the gate insulating film of the IGBT is composed of a laminated film of an oxide film having a thickness of 10 nm formed by a thermal oxidation method and an oxide film having a thickness of 90 nm formed by a CVD method, a sacrificial oxide film and If the thickness of the gate insulating film 10 is 5 nm, in order to obtain the surface semiconductor layer 4 having a thickness of 20 nm to 40 nm after the gate insulating film 10 is formed, the thickness of the surface semiconductor layer 4 remaining after the CMP process is obtained. The thickness needs to be 30 nm to 50 nm. In addition, since the thickness of the surface semiconductor layer 4 remaining after the CMP process is determined by a step due to the insulating film 6, the thickness of the surface semiconductor layer 4 remaining after the CMP process is set to such a value. Needless to say, the buried insulating film 3 must be formed.
　次に、図１８および図１９に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして、活性領域では、ＩＧＢＴの素子が形成される表面半導体層４の一部領域（後の工程で形成されるゲート電極１１下のチャネルとなる領域とその両側）にｐ型を示す不純物（例えばＢ（ホウ素））をイオン注入法により導入して、ｐ型半導体層２５を形成する。 Next, as shown in FIGS. 18 and 19, a partial region of the surface semiconductor layer 4 in which an IGBT element is formed (later process) in the active region using a photoresist film patterned by a photolithography technique as a mask. The p-type semiconductor layer 25 is formed by introducing a p-type impurity (for example, B (boron)) into the region to be the channel under the gate electrode 11 formed on the both sides of the gate electrode 11 by ion implantation.
　ゲート電極１１を形成する前に、ＩＧＢＴの素子が形成される表面半導体層４にｐ型半導体層２５を形成するのは、以下の理由による。すなわち、ゲート電極１１を形成した後に、ゲート電極１１をマスクとして表面半導体層４にｐ型を示す不純物を導入すると、その不純物をゲート電極１１下のチャネルとなる領域まで拡散させるためには、高温かつ長時間の熱処理が必要となる。しかし、この熱処理により絶縁膜６の薄膜部（埋め込み絶縁膜３）に応力がかかり、歪みが生じるため、フォトリソグラフィ技術におけるフォーカスの合わせずれ、または結晶欠陥が発生する。このような問題を回避するために、活性部にゲート電極１１を形成する前に、表面半導体層４にｐ型半導体層２５を形成している。 The reason why the p-type semiconductor layer 25 is formed on the surface semiconductor layer 4 on which the IGBT element is formed before the gate electrode 11 is formed is as follows. That is, after the gate electrode 11 is formed and a gate electrode 11 is used as a mask and a p-type impurity is introduced into the surface semiconductor layer 4, in order to diffuse the impurity to a region to be a channel below the gate electrode 11, a high temperature is required. In addition, a long heat treatment is required. However, stress is applied to the thin film portion (embedded insulating film 3) of the insulating film 6 by this heat treatment and distortion occurs, resulting in a focus shift or a crystal defect in the photolithography technique. In order to avoid such a problem, the p-type semiconductor layer 25 is formed in the surface semiconductor layer 4 before the gate electrode 11 is formed in the active portion.
　次に、図２０および図２１に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして、活性部では、ｐ型半導体層２５の一部領域（エミッタ層（チャネルコンタクト層）となる領域）にｐ型を示す不純物（例えばＢ（ホウ素））をイオン注入法により導入して、ｐ＋型エミッタ層９ｂを形成する。同時に、外周部では、ｐ型フィールドリミッティングリング１２上の表面半導体層４にｐ型を示す不純物（例えばＢ（ホウ素））をイオン注入法により導入して、ｐ＋型半導体層２６を形成する（図４参照）。 Next, as shown in FIGS. 20 and 21, a part of the p-type semiconductor layer 25 (emitter layer (channel contact layer)) is formed in the active portion using a photoresist film patterned by photolithography as a mask. A p + -type emitter layer 9b is formed by introducing a p-type impurity (for example, B (boron)) into the region) by ion implantation. At the same time, the outer peripheral portion, impurities imparting p-type surface semiconductor layer 4 on the p-type field limiting rings 12 (for example, B (boron)) is introduced by ion implantation to form the p + -type semiconductor layer 26 (See FIG. 4).
　ここでは、ＩＧＢＴの素子が形成される領域では、ｐ＋型エミッタ層９ｂの内側にｐ型半導体層２５を残しているが、ｐ型半導体層２５の全てにｐ＋型エミッタ層９ｂを形成してもよい。 Here, in a region where elements of the IGBT is formed, but leaving the p-type semiconductor layer 25 on the inner side of the p + -type emitter layer 9b, the p + -type emitter layer 9b is formed on all the p-type semiconductor layer 25 May be.
　次に、図２２に示すように、基板２Ａに熱酸化処理を施すことによって、表面半導体層４（活性部のｐ型半導体層２５およびｐ＋型エミッタ層９ｂならびに外周部のｐ＋型半導体層２６も含む）の表面に下層酸化膜（図示は省略）を形成し、続いて、この下層酸化膜上にＣＶＤ法により上層酸化膜（図示は省略）を堆積して、下層酸化膜および上層酸化膜を含むゲート絶縁膜１０を形成する。下層酸化膜の厚さは、例えば１０ｎｍであり、上層酸化膜の厚さは、例えば９０ｎｍである。 Next, as shown in FIG. 22, by subjecting the substrate 2A to thermal oxidation treatment, the surface semiconductor layer 4 (the p-type semiconductor layer 25 and the p + -type emitter layer 9b in the active part and the p + -type semiconductor layer in the outer peripheral part) 26), a lower oxide film (not shown) is formed, and then an upper oxide film (not shown) is deposited on the lower oxide film by a CVD method to form a lower oxide film and an upper oxide film. A gate insulating film 10 including a film is formed. The thickness of the lower oxide film is, for example, 10 nm, and the thickness of the upper oxide film is, for example, 90 nm.
　次に、図２３に示すように、基板２Ａの主面上に多結晶シリコン膜２７を堆積し、続いて、多結晶シリコン膜２７上にタングステンシリサイド層２８を形成する。タングステンシリサイド層２８を形成するのは、ゲート電極１１の高さを低くして、かつゲート電極１１の抵抗を増加させないためである。 Next, as shown in FIG. 23, a polycrystalline silicon film 27 is deposited on the main surface of the substrate 2A, and then a tungsten silicide layer 28 is formed on the polycrystalline silicon film 27. The tungsten silicide layer 28 is formed in order to reduce the height of the gate electrode 11 and not increase the resistance of the gate electrode 11.
　次に、図２４および図２５に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとしたエッチングにより、タングステンシリサイド層２８および多結晶シリコン膜２７を順次パターニングする。これにより、多結晶シリコン膜２７とタングステンシリサイド層２８との積層膜とされるゲート電極１１を形成することができる。 Next, as shown in FIGS. 24 and 25, the tungsten silicide layer 28 and the polycrystalline silicon film 27 are sequentially patterned by etching using a photoresist film patterned by photolithography as a mask. Thereby, the gate electrode 11 which is a laminated film of the polycrystalline silicon film 27 and the tungsten silicide layer 28 can be formed.
　次に、図２６に示すように、基板２Ａに熱酸化処理を施すことによって、露出した表面半導体層４の表面に犠牲酸化膜２４を形成する。 Next, as shown in FIG. 26, a sacrificial oxide film 24 is formed on the exposed surface of the surface semiconductor layer 4 by subjecting the substrate 2A to thermal oxidation.
　次に、図２７に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして、ゲート電極１１の両側のｐ型半導体層２５にｎ型を示す不純物（例えばＡｓ（ヒ素））をイオン注入法により導入して、所定の領域にｎ－型ソース層８ｂを形成する。このｎ型を示す不純物の導入により、ゲート電極１１の側面下の表面半導体層４およびゲート絶縁膜１０に結晶欠陥が生じるのを防止するため、イオン注入の注入エネルギーおよび注入量は相対的に低く設定される。 Next, as shown in FIG. 27, an n-type impurity (for example, As (arsenic)) is ionized in the p-type semiconductor layer 25 on both sides of the gate electrode 11 using a photoresist film patterned by photolithography as a mask. The n − type source layer 8b is formed in a predetermined region by introducing by an implantation method. In order to prevent crystal defects from being generated in the surface semiconductor layer 4 and the gate insulating film 10 below the side surface of the gate electrode 11 by the introduction of the n-type impurity, the implantation energy and implantation amount of ion implantation are relatively low. Is set.
　次に、図２８に示すように、基板２Ａの主面上に酸化シリコン膜３０を堆積する。 Next, as shown in FIG. 28, a silicon oxide film 30 is deposited on the main surface of the substrate 2A.
　次に、図２９に示すように、酸化シリコン膜３０を異方性ドライエッチングして、ゲート電極１１の側面に酸化シリコン膜３０とされるサイドウォールＳＷを形成する。 Next, as shown in FIG. 29, the silicon oxide film 30 is anisotropically dry-etched to form a sidewall SW that is to be the silicon oxide film 30 on the side surface of the gate electrode 11.
　次に、図３０および図３１に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして、活性部では、ゲート電極１１の両側のｎ－型ソース層８ｂにｎ型を示す不純物（例えばＡｓ（ヒ素））をイオン注入法により導入して、ｎ－型ソース層８ｂよりも不純物濃度の高いｎ＋型ソース層８ａを形成する。これにより、ｎ－型ソース層８ｂとｎ＋型ソース層８ａとを含むｎ型ソース層８を形成する。同時に、外周部では、表面半導体層４にｎ型を示す不純物（例えばＡｓ（ヒ素））をイオン注入法により導入して、ｎ型ガードリング（チャネルストッパ）１３を形成する（図１および図４参照）。図３０には、ｎ＋型ソース層８ａが、表面半導体層４の上面から埋め込み絶縁膜３と接する下面まで形成されている態様を示しているが、表面半導体層４の上面側のみに形成してもよい。 Next, as shown in FIGS. 30 and 31, using the photoresist film patterned by the photolithography technique as a mask, the n − type source layer 8b on both sides of the gate electrode 11 in the active part has an n-type impurity ( For example, As (arsenic)) is introduced by ion implantation to form an n + type source layer 8a having an impurity concentration higher than that of the n − type source layer 8b. Thereby, the n - type source layer 8 including the n − -type source layer 8b and the n + -type source layer 8a is formed. At the same time, in the outer peripheral portion, an n-type impurity (for example, As (arsenic)) is introduced into the surface semiconductor layer 4 by ion implantation to form an n-type guard ring (channel stopper) 13 (FIGS. 1 and 4). reference). FIG. 30 shows a mode in which the n + -type source layer 8a is formed from the upper surface of the surface semiconductor layer 4 to the lower surface in contact with the buried insulating film 3, but it is formed only on the upper surface side of the surface semiconductor layer 4. May be.
　次に、図３２および図３３に示すように、フォトリソグラフィ技術によってパターニングされたフォトレジスト膜をマスクとして、活性部のゲート電極１１の両側のｐ＋型エミッタ層９ｂにｐ型を示す不純物（例えばＢ（ホウ素））をイオン注入法により導入して、ｐ＋型エミッタ層９ｂよりも不純物濃度の高いｐ＋＋型エミッタ層９ａを形成する。これにより、ｐ＋型エミッタ層９ｂとｐ＋＋型エミッタ層９ａとを含むｐ型エミッタ層（ｐ型チャネルコンタクト層）９を形成する。図３２には、ｐ＋＋型エミッタ層９ａが、表面半導体層４の上面から埋め込み絶縁膜３と接する下面まで形成されている態様を示しているが、表面半導体層４の上面側のみに形成してもよい。 Next, as shown in FIGS. 32 and 33, a p-type impurity (for example, in the p + -type emitter layer 9b on both sides of the gate electrode 11 of the active portion) is masked using a photoresist film patterned by photolithography as a mask. B (boron)) is introduced by an ion implantation method to form a p ++ type emitter layer 9a having an impurity concentration higher than that of the p + type emitter layer 9b. Thereby, a p-type emitter layer (p-type channel contact layer) 9 including the p + -type emitter layer 9b and the p + + type emitter layer 9a is formed. FIG. 32 shows an embodiment in which the p ++ type emitter layer 9a is formed from the upper surface of the surface semiconductor layer 4 to the lower surface in contact with the buried insulating film 3, but it is formed only on the upper surface side of the surface semiconductor layer 4. May be.
　ｎ＋型ソース層８ａを形成する不純物のイオン注入では、ｎ－型ソース層８ｂを形成する不純物のイオン注入よりも注入量を多くしている。また、ｐ＋＋型エミッタ層９ａを形成する不純物のイオン注入では、ｐ＋型エミッタ層９ｂを形成する不純物のイオン注入よりも注入量を多くしている。このように、高濃度の不純物が導入されても、ゲート電極１１の側面からサイドウォールＳＷのサイドウォール長分の距離を離れて不純物がイオン注入されるので、ゲート電極１１の側面下の表面半導体層４およびゲート絶縁膜１０に結晶欠陥が生じるのを防止することができる。また、サイドウォールＳＷの端部下の表面半導体層４に結晶欠陥が生じても、ゲート電極１１の側面から離れているので、ＩＧＢＴの動作特性へはほとんど影響を及ぼさない。 In the ion implantation of the impurity forming the n + -type source layer 8a, the implantation amount is larger than that of the impurity ion implantation forming the n − -type source layer 8b. Further, the ion implantation of the impurity forming the p ++ type emitter layer 9a has a larger implantation amount than the ion implantation of the impurity forming the p + type emitter layer 9b. Thus, even if a high concentration of impurities is introduced, the impurities are ion-implanted from the side surface of the gate electrode 11 at a distance corresponding to the side wall length of the side wall SW, so that the surface semiconductor below the side surface of the gate electrode 11 is implanted. Crystal defects can be prevented from occurring in the layer 4 and the gate insulating film 10. Further, even if crystal defects occur in the surface semiconductor layer 4 below the end portion of the sidewall SW, it is far from the side surface of the gate electrode 11 and therefore hardly affects the operation characteristics of the IGBT.
　ところで、ＩＧＢＴの素子が形成される領域では、ｎ型ソース層８およびｐ型エミッタ層９は同一断面の中に形成することは不可能である。そのため、上面視においてゲート電極１１と絶縁膜６の厚膜部との間の帯状に延在する１本のパターンの中でｎ型ソース層８とｐ型エミッタ層９とは交互に配置されることになる。また、ｎ型ソース層８またはｐ型エミッタ層９が形成されなかったゲート電極１１下のｐ型半導体層２５は、ｐ型チャネル層７を構成することになる。 By the way, in the region where the IGBT element is formed, it is impossible to form the n-type source layer 8 and the p-type emitter layer 9 in the same cross section. Therefore, the n-type source layer 8 and the p-type emitter layer 9 are alternately arranged in one pattern extending in a strip shape between the gate electrode 11 and the thick film portion of the insulating film 6 in a top view. It will be. Further, the p-type semiconductor layer 25 under the gate electrode 11 where the n-type source layer 8 or the p-type emitter layer 9 is not formed constitutes the p-type channel layer 7.
　ここまでの工程により、本実施例によるＩＧＢＴの素子を形成することができる。 The IGBT element according to the present embodiment can be formed through the above steps.
　次に、図３４に示すように、基板２Ａの主面上に窒化膜３２を形成する。窒化膜３２は、例えば窒化シリコン膜であり、その厚さは、例えば５０ｎｍ～７０ｎｍである。 Next, as shown in FIG. 34, a nitride film 32 is formed on the main surface of the substrate 2A. The nitride film 32 is, for example, a silicon nitride film, and the thickness thereof is, for example, 50 nm to 70 nm.
　次に、図３５に示すように、フォトリソグラフィ技術によりパターニングされたフォトレジスト膜をマスクとして窒化膜３２をエッチングし、ゲート電極１１に達する第３開口部３１を形成する。 Next, as shown in FIG. 35, the nitride film 32 is etched using a photoresist film patterned by the photolithography technique as a mask to form a third opening 31 reaching the gate electrode 11.
　次に、図３６に示すように、基板２Ａの主面上に酸化シリコン膜３３およびＢＰＳＧ（Boron-ＰＳＧ）膜３４を順次堆積する。酸化シリコン膜３３の厚さは、例えば１５０ｎｍ、ＢＰＳＧ膜３４の厚さは、例えば４００ｎｍ～５００ｎｍである。その後、基板２Ａに対して熱処理を施す。この熱処理により、外周部では、ｐ型フィールドリミッティングリング１２上の表面半導体層４に形成されたｐ＋型半導体層２６中の不純物が拡散して、ｐ型フィールドリミッティングリング１２とｐ＋型半導体層２６との間の表面半導体層４（第１開口部５）にも不純物が導入されて、両者は低抵抗で接続される。同様に、ｎ型ガードリング１３中の不純物が拡散して、ｎ型ガードリング１３と基板２Ａとの間の表面半導体層４（第１開口部５）にも不純物が導入されて、両者は低抵抗で接続される（図３および図４参照）。 Next, as shown in FIG. 36, a silicon oxide film 33 and a BPSG (Boron-PSG) film 34 are sequentially deposited on the main surface of the substrate 2A. The thickness of the silicon oxide film 33 is, for example, 150 nm, and the thickness of the BPSG film 34 is, for example, 400 nm to 500 nm. Thereafter, heat treatment is performed on the substrate 2A. By this heat treatment, the outer peripheral portion, and an impurity diffusion of p-type field limiting ring in p + -type semiconductor layer 26 formed on the surface semiconductor layer 4 on 12, p-type field limiting ring 12 and the p + -type Impurities are also introduced into the surface semiconductor layer 4 (first opening 5) between the semiconductor layer 26 and the two are connected with low resistance. Similarly, impurities in the n-type guard ring 13 are diffused, and impurities are also introduced into the surface semiconductor layer 4 (first opening 5) between the n-type guard ring 13 and the substrate 2A. The resistors are connected (see FIGS. 3 and 4).
　次に、図３７に示すように、ＢＰＳＧ膜３４上にＰＳＧ膜３５を堆積することにより、窒化膜３２、酸化シリコン膜３３、ＢＧＳＰ膜３４、およびＰＳＧ膜３５を含む層間絶縁膜１４を形成する。ＰＳＧ膜３５の厚さは、例えば３００ｎｍである。その後、基板２Ａに対して熱処理を施す。 Next, as shown in FIG. 37, the PSG film 35 is deposited on the BPSG film 34 to form the interlayer insulating film 14 including the nitride film 32, the silicon oxide film 33, the BGSP film 34, and the PSG film 35. . The thickness of the PSG film 35 is, for example, 300 nm. Thereafter, heat treatment is performed on the substrate 2A.
　次に、図３８および図３９に示すように、層間絶縁膜１４をエッチングして、活性部では、ＩＧＢＴの素子のｎ＋型ソース層８ａおよびｐ＋＋型エミッタ層９ａ、ならびにゲート電極１１のそれぞれに達する第２開口部１５を形成する。また、外周部では、ｐ＋型半導体層２６およびｎ型ガードリング１３のそれぞれに達する第２開口部１５を形成する（図３および図４参照）。 Next, as shown in FIGS. 38 and 39, the interlayer insulating film 14 is etched, and in the active portion, each of the n + type source layer 8a and the p ++ type emitter layer 9a of the IGBT element and the gate electrode 11 is formed. A second opening 15 is formed. In the outer peripheral portion, second openings 15 reaching the p + type semiconductor layer 26 and the n type guard ring 13 are formed (see FIGS. 3 and 4).
　この第２開口部１５を形成する際には、まず、フォトリソグラフィ技術によりパターニングされたフォトレジスト膜をマスクとし、窒化膜３２をエッチングストッパとして、ＰＳＧ膜３５、ＢＰＳＧ膜３４、および酸化シリコン膜３３を順次エッチングする。このとき、ゲート電極１１上の窒化膜３２の一部に、前述の図３５を用いて説明した工程において、第３開口部３１が形成されているので、ゲート電極１１の上部を構成するタングステンシリサイド層２８の一部が露出する。続いて、上記フォトレジスト膜をマスクとして、窒化膜３２をエッチングする。 In forming the second opening 15, first, the PSG film 35, the BPSG film 34, and the silicon oxide film 33 are formed using a photoresist film patterned by photolithography as a mask and the nitride film 32 as an etching stopper. Are sequentially etched. At this time, since the third opening 31 is formed in a part of the nitride film 32 on the gate electrode 11 in the process described with reference to FIG. 35 described above, the tungsten silicide constituting the upper part of the gate electrode 11 is formed. A portion of layer 28 is exposed. Subsequently, the nitride film 32 is etched using the photoresist film as a mask.
　このように、一旦、窒化膜３２においてＰＳＧ膜３５、ＢＰＳＧ膜３４、および酸化シリコン膜３３のエッチングを止めて、その後、窒化膜３２をエッチングして第２開口部１５を形成している。そのため、ｎ＋型ソース層８ａおよびｐ＋＋型エミッタ層９ａが形成された表面半導体層４、ならびに絶縁膜６の厚膜部のオーバエッチング量（外周部では、ｐ＋型半導体層２６およびｎ型ガードリング１３が形成された表面半導体層４のオーバエッチング量（図３および図４参照））を僅かとすることができる。また、基板２Ａの主面から、第２開口部１５が形成される領域の表面半導体層４の上面までの厚さ（埋め込み絶縁膜３と表面半導体層４との合計の厚さ）は、例えば３００ｎｍよりも厚く形成されている。 As described above, the etching of the PSG film 35, the BPSG film 34, and the silicon oxide film 33 in the nitride film 32 is once stopped, and then the nitride film 32 is etched to form the second opening 15. Therefore, the surface semiconductor layer 4 on which the n + -type source layer 8a and the p + + -type emitter layer 9a are formed, and the overetching amount of the thick film portion of the insulating film 6 (in the outer peripheral portion, the p + -type semiconductor layer 26 and the n-type The amount of overetching of the surface semiconductor layer 4 on which the guard ring 13 is formed (see FIGS. 3 and 4) can be made small. The thickness from the main surface of the substrate 2A to the upper surface of the surface semiconductor layer 4 in the region where the second opening 15 is formed (total thickness of the buried insulating film 3 and the surface semiconductor layer 4) is, for example, It is formed thicker than 300 nm.
　従って、ｎ＋型ソース層８ａおよびｐ＋＋型エミッタ層９ａ（外周部では、ｐ＋型半導体層２６およびｎ型ガードリング１３（図３および図４参照））を突き抜けて、第２開口部１５が基板２Ａに達することがない。 Therefore, the second opening 15 extends through the n + -type source layer 8a and the p + + -type emitter layer 9a (in the outer periphery, the p + -type semiconductor layer 26 and the n-type guard ring 13 (see FIGS. 3 and 4)). Does not reach the substrate 2A.
　一方、ゲート電極１１と後に形成されるゲートフィンガー（図３に符号１７Ａで示すゲートフィンガー）とを接続する第２開口部１５が形成される領域では、予め窒化膜３２が除去されている。これは、ゲート電極１１とゲートフィンガーとの接続不良を回避するためである。すなわち、ゲート電極１１の上部を構成するタングステンシリサイド層２８と窒化膜３２との間に酸化膜が形成されていると、第２開口部１５を形成した後（窒化膜３２を除去した後）も、上記酸化膜が除去できずに残存することがある。上記酸化膜が残存していると、タングステンシリサイド層２８とゲートフィンガーを構成する金属膜との接触抵抗が増加する。これを防ぐために、ゲート電極１１と後に形成されるゲートフィンガーとを接続する第２開口部１５が形成される領域の窒化膜３２を予め除去しておく。 On the other hand, in the region where the second opening 15 that connects the gate electrode 11 and the gate finger formed later (a gate finger indicated by reference numeral 17A in FIG. 3) is formed, the nitride film 32 is removed in advance. This is to avoid poor connection between the gate electrode 11 and the gate finger. That is, if an oxide film is formed between the tungsten silicide layer 28 and the nitride film 32 constituting the upper portion of the gate electrode 11, the second opening 15 is formed (after the nitride film 32 is removed). The oxide film may remain without being removed. If the oxide film remains, the contact resistance between the tungsten silicide layer 28 and the metal film constituting the gate finger increases. In order to prevent this, the nitride film 32 in the region where the second opening 15 connecting the gate electrode 11 and the gate finger to be formed later is formed is removed in advance.
　なお、この残存した酸化膜を、第２開口部１５を形成した後（窒化膜３２を除去した後）にエッチングにより除去することは可能である。しかし、同時に絶縁膜６の厚膜部もエッチングされて、絶縁膜６の厚膜部の厚さを所定の厚さに維持することができなくなる。 The remaining oxide film can be removed by etching after the second opening 15 is formed (after the nitride film 32 is removed). However, at the same time, the thick film portion of the insulating film 6 is also etched, and the thickness of the thick film portion of the insulating film 6 cannot be maintained at a predetermined thickness.
　次に、図４０および図４１に示すように、例えばスパッタリング法により基板２Ａの主面上にＡｌ（アルミニウム）膜を堆積する。次いで、フォトリソグラフィ技術によりパターニングされたフォトレジスト膜をマスクとしてそのＡｌ（アルミニウム）膜をエッチングし、ＩＧＢＴの素子のｎ＋型ソース層８ａおよびｐ＋＋型エミッタ層９ａと電気的に接続するソースパッド（ソース電極）１６を形成する。同時に、前述の図３および図４に示したように、以下が形成される。 Next, as shown in FIGS. 40 and 41, an Al (aluminum) film is deposited on the main surface of the substrate 2A, for example, by sputtering. Next, the Al (aluminum) film is etched using a photoresist film patterned by photolithography as a mask, and the source pad is electrically connected to the n + type source layer 8a and the p + + type emitter layer 9a of the IGBT element. (Source electrode) 16 is formed. At the same time, as shown in FIGS. 3 and 4 described above, the following is formed.
　１）ソースパッド１６と電気的に接続しソースパッド１６と連続したパターンを有するソース引き回し電極１６Ａ、
　２）ゲート電極１１と電気的に接続するゲートパッド１７、
　３）ゲート電極１１と電気的に接続しゲートパッド１７と連続したパターンを有するゲートフィンガー１７Ａ、
　４）ｐ型フィールドリミッティングリング１２とｐ＋型半導体層２６を介して電気的に接続するフィールドリミッティングリング電極１２Ａ、および、
　５）ｎ型ガードリング１３と電気的に接続するガードリング電極１３Ａ。 1) A source lead electrode 16A electrically connected to the source pad 16 and having a pattern continuous with the source pad 16;
2) a gate pad 17 electrically connected to the gate electrode 11;
3) A gate finger 17A that is electrically connected to the gate electrode 11 and has a continuous pattern with the gate pad 17.
4) A field limiting ring electrode 12A electrically connected to the p-type field limiting ring 12 via the p + -type semiconductor layer 26, and
5) A guard ring electrode 13A electrically connected to the n-type guard ring 13.
　さらに、図示は省略するが、ソースパッド１６、ソース引き回し電極１６Ａ、ゲートパッド１７、ゲートフィンガー１７Ａ、フィールドリミッティングリング電極１２Ａ、およびガードリング電極１３Ａを形成した後、基板２Ａの主面上に表面保護膜としてポリイミド膜を堆積する。続いて、このポリイミド膜に、ソースパッド１６、ゲートパッド１７、フィールドリミッティングリング電極１２Ａ、およびガードリング電極１３Ａのそれぞれに達する開口部を形成する。これら開口部は、基板２Ａを個々の半導体チップ１へ分割し、半導体チップ１をリードフレームのダイパッドに搭載した後で、ボンディングワイヤを用いてソースパッド１６、ゲートパッド１７、フィールドリミッティングリング電極１２Ａ、およびガードリング電極１３Ａのそれぞれを対応するリードと電気的に接続するために形成するものである。 Furthermore, although illustration is omitted, after the source pad 16, the source routing electrode 16A, the gate pad 17, the gate finger 17A, the field limiting ring electrode 12A, and the guard ring electrode 13A are formed, the surface is formed on the main surface of the substrate 2A. A polyimide film is deposited as a protective film. Subsequently, openings reaching the source pad 16, the gate pad 17, the field limiting ring electrode 12A, and the guard ring electrode 13A are formed in the polyimide film. These openings divide the substrate 2A into individual semiconductor chips 1, and after the semiconductor chip 1 is mounted on the die pad of the lead frame, the source pads 16, the gate pads 17, and the field limiting ring electrodes 12A using bonding wires. And the guard ring electrode 13A are formed to be electrically connected to the corresponding leads.
　次に、図４２に示すように、基板２Ａの主面上に発泡性両面テープまたはガラス補強板などの補強材（図示は省略）を貼り付けた後、基板２Ａの裏面を研削し、ベース層２を形成する。前述したように、ベース層２の厚さは、ＩＧＢＴの耐圧に合わせて決定するものであり、耐圧６００Ｖであれば６０μｍ～１００μｍとなるまで、また耐圧１２００Ｖであれば１２０μｍ～１５０μｍとなるまで基板２Ａの裏面を研削する。基板２Ａの主面側に補強材を貼り付けているので、基板２Ａの反りや垂れ下がりを防止することができる。 Next, as shown in FIG. 42, a reinforcing material (not shown) such as a foam double-sided tape or a glass reinforcing plate is attached to the main surface of the substrate 2A, and then the back surface of the substrate 2A is ground to form a base layer. 2 is formed. As described above, the thickness of the base layer 2 is determined in accordance with the breakdown voltage of the IGBT. The substrate is 60 μm to 100 μm when the breakdown voltage is 600V, and 120 μm to 150 μm when the breakdown voltage is 1200V. Grind the back of 2A. Since the reinforcing material is affixed to the main surface side of the substrate 2A, it is possible to prevent the substrate 2A from warping or drooping.
　次に、ベース層２の裏面にｎ型を示す不純物（例えばＰ（リン））およびｐ型を示す不純物（例えばＢ（ホウ素））を順次イオン注入法により導入し、例えばレーザーアニール法を用いて上記不純物を活性化することにより、ｎ＋型バッファ層１８およびｐ型コレクタ層１９を形成する。 Next, an n-type impurity (for example, P (phosphorus)) and a p-type impurity (for example, B (boron)) are sequentially introduced into the back surface of the base layer 2 by an ion implantation method, for example, using a laser annealing method. By activating the impurities, an n + -type buffer layer 18 and a p-type collector layer 19 are formed.
　次に、ｐ型コレクタ層１９と電気的に接続するコレクタ電極２０を形成する。このコレクタ電極２０は、たとえばスパッタリング法または蒸着法により、ｐ型コレクタ層１９に近い順からＡｌ（アルミニウム）膜、Ｔｉ（チタン）膜、Ｎｉ（ニッケル）膜、およびＡｕ（金）膜を積層することで形成することができる。また、ｐ型コレクタ層１９に近い順からＮｉ（ニッケル）膜、Ｔｉ（チタン）膜、Ｎｉ（ニッケル）膜、およびＡｕ（金）膜を積層したコレクタ電極２０、もしくはｐ型コレクタ層１９に近い順からＴｉ（チタン）膜、Ｎｉ（ニッケル）膜、およびＡｕ（金）膜を積層したコレクタ電極２０としてもよい。その後、補強材を除去する。 Next, a collector electrode 20 that is electrically connected to the p-type collector layer 19 is formed. The collector electrode 20 is formed by laminating an Al (aluminum) film, a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film in order from the p-type collector layer 19 by, for example, sputtering or vapor deposition. Can be formed. Further, the collector electrode 20 in which the Ni (nickel) film, the Ti (titanium) film, the Ni (nickel) film, and the Au (gold) film are stacked in order from the closest to the p-type collector layer 19 or the p-type collector layer 19 The collector electrode 20 may be formed by stacking a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film in order. Thereafter, the reinforcing material is removed.
　次に、基板２Ａを分割領域（ダイシングライン）に沿って切断することにより、個々の半導体チップ１へ個片化する。続いて、リードフレームを用意し、個片化された半導体チップ１をリードフレームのダイパッドに搭載した後で、ボンディングワイヤを用いてソースパッド１６、ゲートパッド１７、フィールドリミッティングリング電極１２Ａ、およびガードリング電極１３Ａのそれぞれを対応するリードと電気的に接続する。その後、封止用樹脂で半導体チップ１、リードフレーム、およびボンディングワイヤを封止して、本実施例による半導体装置を製造する。 Next, the substrate 2A is cut into individual semiconductor chips 1 by cutting along the divided regions (dicing lines). Subsequently, after preparing a lead frame and mounting the singulated semiconductor chip 1 on a die pad of the lead frame, the source pad 16, the gate pad 17, the field limiting ring electrode 12A, and the guard using bonding wires Each of the ring electrodes 13A is electrically connected to the corresponding lead. Thereafter, the semiconductor chip 1, the lead frame, and the bonding wires are sealed with a sealing resin to manufacture the semiconductor device according to this embodiment.
　このように、本実施例によれば、埋め込み絶縁膜３の上面から、ゲート電極１１の下に位置する表面半導体層４の上面までの厚さを、例えば３００ｎｍ以下、１００ｎｍ以下、より望ましくは２０ｎｍ～４０ｎｍの範囲に設定することにより、ＩＧＢＴの定常損失、ターンオフ時間、およびターンオフ損失を低減することができる。一方、ベース層２の上面から、第２開口部１５が形成される領域（ソースパッド１６が接続される領域）の表面半導体層４の上面までの厚さは、例えば３００ｎｍよりも厚く形成されている。従って、表面半導体層４上に形成された層間絶縁膜１４に第２開口部１５を形成する際、開口不良を回避するためにオーバエッチングを行っても、第２開口部１５の突き抜けを防止することができる。これにより、ソースパッド１６とベース層２とは接続しないので、ＩＢＧＴの動作不良を防止することができる。 Thus, according to the present embodiment, the thickness from the upper surface of the buried insulating film 3 to the upper surface of the surface semiconductor layer 4 located under the gate electrode 11 is, for example, 300 nm or less, 100 nm or less, more preferably 20 nm. By setting in the range of ˜40 nm, the steady loss, turn-off time, and turn-off loss of the IGBT can be reduced. On the other hand, the thickness from the upper surface of the base layer 2 to the upper surface of the surface semiconductor layer 4 in the region where the second opening 15 is formed (the region where the source pad 16 is connected) is formed to be thicker than 300 nm, for example. Yes. Therefore, when the second opening 15 is formed in the interlayer insulating film 14 formed on the surface semiconductor layer 4, the second opening 15 is prevented from penetrating even if overetching is performed in order to avoid an opening defect. be able to. Thereby, since the source pad 16 and the base layer 2 are not connected, the malfunction of IBGT can be prevented.
　以上、本発明者らによってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　本発明は、例えば鉄道車両およびハイブリッドカーにおけるモータードライブ用インバータ等の種々のインバータに採用される半導体装置に適用することができる。 The present invention can be applied to semiconductor devices employed in various inverters such as motor drive inverters in railway vehicles and hybrid cars, for example.
１　半導体チップ
２　ベース層
２Ａ　半導体基板
３　埋め込み絶縁膜
４　表面半導体層
４Ａ　ｎ－型単結晶シリコン膜
５　第１開口部
６　絶縁膜（厚膜部）
７　ｐ型チャネル層
８　ｎ型ソース層
８ａ　ｎ＋型ソース層
８ｂ　ｎ－型ソース層
９　ｐ型エミッタ層（ｐ型チャネルコンタクト層）
９ａ　ｐ＋＋型エミッタ層
９ｂ　ｐ＋型エミッタ層
１０　ゲート絶縁膜
１１　ゲート電極
１２　ｐ型フィールドリミッティングリング
１２Ａ　フィールドリミッティングリング電極
１３　ｎ型ガードリング（チャネルストッパ）
１３Ａ　ガードリング電極
１４　層間絶縁膜
１５　第２開口部
１６　ソースパッド（ソース電極）
１６Ａ　ソース引き回し電極
１７　ゲートパッド
１７Ａ　ゲートフィンガー
１８　ｎ＋型バッファ層
１９　ｐ型コレクタ層
２０　コレクタ電極
２１　表面酸化膜
２３　ｐ型ウェル
２４　犠牲酸化膜
２５　ｐ型半導体層
２６　ｐ＋型半導体層
２７　多結晶シリコン膜
２８　タングステンシリサイド層
３０　酸化シリコン膜
３１　第３開口部
３２　窒化膜
３３　酸化シリコン膜
３４　ＢＰＳＧ膜
３５　ＰＳＧ膜
ＡＣ　活性領域
ＳＷ　サイドウォール DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Base layer 2A Semiconductor substrate 3 Embedded insulating film 4 Surface semiconductor layer 4A n − type single crystal silicon film 5 First opening 6 Insulating film (thick film part)
7 p-type channel layer 8 n-type source layer 8a n + -type source layer 8b n - -type source layer 9 p-type emitter layer (p-type channel contact layer)
9a p ++ type emitter layer 9b p + type emitter layer 10 Gate insulating film 11 Gate electrode 12 p type field limiting ring 12A field limiting ring electrode 13 n type guard ring (channel stopper)
13A guard ring electrode 14 interlayer insulating film 15 second opening 16 source pad (source electrode)
16A source routing electrode 17 gate pad 17A gate finger 18 n + type buffer layer 19 p type collector layer 20 collector electrode 21 surface oxide film 23 p type well 24 sacrificial oxide film 25 p type semiconductor layer 26 p + type semiconductor layer 27 polycrystalline Silicon film 28 Tungsten silicide layer 30 Silicon oxide film 31 Third opening 32 Nitride film 33 Silicon oxide film 34 BPSG film 35 PSG film AC Active region SW Side wall

Claims (21)

  1. 　ＩＧＢＴの素子を含む半導体装置であって、
    　第１導電型を示す前記ＩＧＢＴのコレクタ層と、
    　前記コレクタ層の上面に形成された、前記第１導電型と異なる第２導電型を示す前記ＩＧＢＴのバッファ層と、
    　前記バッファ層上に形成された、前記第２導電型を示す前記ＩＧＢＴのベース層と、
    　前記ベース層上に形成された、第１厚さを有する埋め込み絶縁膜と、
    　前記埋め込み絶縁膜に形成された第１開口部と、
    　前記埋め込み絶縁膜の周囲に形成され、前記第１厚さよりも厚い第２厚さを有し、活性領域を規定する絶縁膜と、
    　前記活性領域において、前記埋め込み絶縁膜上に形成された表面半導体層と、
    　前記表面半導体層内に形成された、前記第１導電型を示す前記ＩＧＢＴのチャネル層と、
    　前記表面半導体層内にて、前記チャネル層と接するように形成され、前記チャネル層よりも高濃度の前記第１導電型を示す前記ＩＧＢＴのエミッタ層と、
    　前記表面半導体層内に形成された、前記第２導電型を示す前記ＩＧＢＴのソース層と、
    　前記表面半導体層上の一部に形成された、前記ＩＧＢＴのゲート絶縁膜と、
    　前記ゲート絶縁膜上に形成された、前記ＩＧＢＴのゲート電極と、
    　前記ゲート電極および前記表面半導体層を覆うように形成された層間絶縁膜と、
    　前記層間絶縁膜に形成され、前記エミッタ層および前記ソース層に達する第２開口部と、
    　前記第２開口部を通じて前記エミッタ層および前記ソース層と電気的に接続された、前記ＩＧＢＴのソース電極と、
    　前記コレクタ層の上面と反対側の面に形成され、前記コレクタ層と電気的に接続された、前記ＩＧＢＴのコレクタ電極と、
    を有し、
    　前記活性領域は、上面視において第１方向に長辺を有し、前記第１方向と直交する第２方向に短辺を有する領域であり、
    　前記第２方向に沿った前記活性領域の断面において、
    　前記ベース層の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さが、前記ベース層の上面から、前記第２開口部が形成された領域に位置する前記表面半導体層の上面までの厚さよりも薄いことを特徴とする半導体装置。     A semiconductor device including an IGBT element,
    A collector layer of the IGBT exhibiting a first conductivity type;
    A buffer layer of the IGBT having a second conductivity type different from the first conductivity type, formed on an upper surface of the collector layer;
    A base layer of the IGBT having the second conductivity type formed on the buffer layer;
    A buried insulating film having a first thickness formed on the base layer;
    A first opening formed in the buried insulating film;
    An insulating film formed around the buried insulating film, having a second thickness greater than the first thickness, and defining an active region;
    A surface semiconductor layer formed on the buried insulating film in the active region;
    A channel layer of the IGBT having the first conductivity type formed in the surface semiconductor layer;
    An emitter layer of the IGBT formed in contact with the channel layer in the surface semiconductor layer and exhibiting the first conductivity type having a higher concentration than the channel layer;
    A source layer of the IGBT having the second conductivity type formed in the surface semiconductor layer;
    A gate insulating film of the IGBT formed in a part on the surface semiconductor layer;
    A gate electrode of the IGBT formed on the gate insulating film;
    An interlayer insulating film formed to cover the gate electrode and the surface semiconductor layer;
    A second opening formed in the interlayer insulating film and reaching the emitter layer and the source layer;
    A source electrode of the IGBT electrically connected to the emitter layer and the source layer through the second opening;
    A collector electrode of the IGBT formed on a surface opposite to the upper surface of the collector layer and electrically connected to the collector layer;
    Have
    The active region is a region having a long side in a first direction in a top view and a short side in a second direction orthogonal to the first direction;
    In a cross section of the active region along the second direction,
    The surface semiconductor in which the thickness from the upper surface of the base layer to the upper surface of the surface semiconductor layer located under the gate electrode is located in a region where the second opening is formed from the upper surface of the base layer A semiconductor device characterized by being thinner than the thickness up to the upper surface of the layer.
  2. 　請求項１記載の半導体装置において、
    　前記埋め込み絶縁膜の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さは、３００ｎｍ以下であることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A thickness of the semiconductor device, wherein the thickness from the upper surface of the buried insulating film to the upper surface of the surface semiconductor layer located under the gate electrode is 300 nm or less.
  3. 　請求項１記載の半導体装置において、
    　前記埋め込み絶縁膜の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さは、１００ｎｍ以下であることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A thickness of the semiconductor device, wherein the thickness from the upper surface of the buried insulating film to the upper surface of the surface semiconductor layer located under the gate electrode is 100 nm or less.
  4. 　請求項１記載の半導体装置において、
    　前記埋め込み絶縁膜の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さは、２０ｎｍ～４０ｎｍであることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device characterized in that the thickness from the upper surface of the buried insulating film to the upper surface of the surface semiconductor layer located under the gate electrode is 20 nm to 40 nm.
  5. 　請求項１記載の半導体装置において、
    　前記活性領域を規定する前記絶縁膜の前記第２厚さは、３００ｎｍよりも厚いことを特徴とする半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device according to claim 1, wherein the second thickness of the insulating film defining the active region is greater than 300 nm.
  6. 　請求項１記載の半導体装置において、
    　前記活性領域の前記第２方向の幅は、前記第２方向に隣り合う前記活性領域の間隔よりも広いことを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A width of the active region in the second direction is wider than an interval between the active regions adjacent to each other in the second direction.
  7. 　請求項６記載の半導体装置において、
    　前記活性領域の前記第２方向の幅は３μｍ以上であることを特徴とする半導体装置。     The semiconductor device according to claim 6.
    A width of the active region in the second direction is 3 μm or more.
  8. 　絶縁ゲート型バイポーラトランジスタの素子を含む半導体装置であって、
    　前記絶縁ゲート型バイポーラトランジスタの素子が形成される活性領域は、上面視において第１方向に長辺を有し、前記第１方向と直交する第２方向に短辺を有する領域とされ、
    　前記第２方向に沿った前記活性領域の断面において、ベース層の上面から、ゲート電極の下に位置する表面半導体層の上面までの厚さが、前記ベース層の上面から、前記ゲート電極を覆う層間絶縁膜の一部に形成された第２開口部が達する領域に位置する表面半導体層の上面までの厚さよりも薄いことを特徴とする半導体装置。     A semiconductor device including an element of an insulated gate bipolar transistor,
    The active region in which the element of the insulated gate bipolar transistor is formed is a region having a long side in the first direction and a short side in the second direction orthogonal to the first direction when viewed from above.
    In the cross section of the active region along the second direction, the thickness from the upper surface of the base layer to the upper surface of the surface semiconductor layer located under the gate electrode covers the gate electrode from the upper surface of the base layer. A semiconductor device characterized in that the thickness is smaller than the thickness up to the upper surface of a surface semiconductor layer located in a region reached by a second opening formed in a part of an interlayer insulating film.
  9. 　絶縁ゲート型バイポーラトランジスタの素子を含む半導体装置であって、
    　前記絶縁ゲート型バイポーラトランジスタの素子が形成される活性領域は、上面視において第１方向に長辺を有し、前記第１方向と直交する第２方向に短辺を有する領域とされ、
    　前記第２方向に沿った前記活性領域の断面において、埋め込み絶縁膜の第１開口部に対応する位置における前記埋め込み絶縁膜の上面から表面半導体層の上面までの厚さは、ゲート電極の端部に対応する位置における前記埋め込み絶縁膜の上面から前記表面半導体層の上面までの厚さよりも薄いことを特徴とする半導体装置。     A semiconductor device including an element of an insulated gate bipolar transistor,
    The active region in which the element of the insulated gate bipolar transistor is formed is a region having a long side in the first direction and a short side in the second direction orthogonal to the first direction when viewed from above.
    In the cross section of the active region along the second direction, the thickness from the upper surface of the buried insulating film to the upper surface of the surface semiconductor layer at the position corresponding to the first opening of the buried insulating film is the end of the gate electrode And a thickness from the upper surface of the buried insulating film to the upper surface of the surface semiconductor layer at a position corresponding to.
  10. 　以下の工程を含むＩＧＢＴの素子を備える半導体装置の製造方法：
    （ａ）前記ＩＧＢＴのベース層となる第２導電型を示す基板を準備する工程；
    （ｂ）前記基板の主面上に、第１厚さを有する薄膜部と前記第１厚さよりも厚い第２厚さを有する厚膜部とを含む絶縁膜を形成する工程；
    （ｃ）前記絶縁膜の前記薄膜部に、前記基板に達する第１開口部を形成する工程；
    （ｄ）前記絶縁膜の前記薄膜部上に、前記第２導電型を示す表面半導体層を、前記第１開口部を埋め込んで形成する工程；
    （ｅ）前記表面半導体層内の所定の領域に、前記第２導電型と異なる第１導電型を示す前記ＩＧＢＴのチャネル層を形成する工程；
    （ｆ）前記チャネル層内の所定の領域に、前記チャネル層よりも高濃度の前記第１導電型を示す前記ＩＧＢＴの第１エミッタ層を形成する工程；
    （ｇ）前記工程（ｆ）の後、前記表面半導体層上に、前記ＩＧＢＴのゲート絶縁膜を形成する工程；
    （ｈ）前記ゲート絶縁膜上に、前記ＩＧＢＴのゲート電極を形成する工程；
    （ｉ）前記表面半導体層内に前記第２導電型を示す不純物を導入して、前記ゲート電極の両側の前記表面半導体層の前記第１エミッタ層が形成されていない領域に、前記ＩＧＢＴの第１ソース層を形成する工程；
    （ｊ）前記ゲート電極の側面にサイドウォールを形成する工程；
    （ｋ）前記表面半導体層内に前記第１導電型を示す不純物を導入して、前記サイドウォールの両側の前記表面半導体層の前記第１エミッタ層が形成されている領域に、前記第１エミッタ層よりも高濃度の前記ＩＧＢＴの第２エミッタ層を形成し、
    　前記表面半導体層内に前記第２導電型を示す不純物を導入して、前記サイドウォールの両側の前記表面半導体層の前記第１ソース層が形成されている領域に、前記第１ソース層よりも高濃度の前記ＩＧＢＴの第２ソース層を形成する工程；
    （ｌ）前記工程（ｋ）の後、前記基板の前記主面側に、窒化膜を形成する工程；
    （ｍ）前記ゲート電極上の前記窒化膜に、第３開口部を形成する工程；
    （ｎ）前記工程（ｍ）の後、前記基板の前記主面側に、層間絶縁膜を形成する工程；
    （ｏ）前記第３開口部が形成された領域の前記層間絶縁膜、ならびに前記第２エミッタ層上および前記第２ソース層上の前記層間絶縁膜および前記窒化膜をエッチングして、前記ゲート電極、ならびに前記第２エミッタ層および前記第２ソース層に達する第２開口部をそれぞれ形成する工程；
    （ｐ）前記第２エミッタ層および前記第２ソース層と電気的に接続する前記ＩＧＢＴのソース電極、ならびに前記ゲート電極と電気的に接続するゲートパッドを形成する工程；
    （ｑ）前記基板を前記主面と反対側の裏面から薄くして、前記ＩＧＢＴの前記ベース層を形成する工程；
    （ｒ）前記工程（ｑ）の後、前記基板の前記裏面側に前記第２導電型を示す前記ＩＧＢＴのバッファ層を形成する工程；
    （ｓ）前記工程（ｒ）の後、前記基板の前記裏面側に前記第１導電型を示す前記ＩＧＢＴのコレクタ層を形成する工程；
    （ｔ）前記コレクタ層と電気的に接続する前記ＩＧＢＴのコレクタ電極を形成する工程、
    　ここで、前記工程（ｄ）において、前記基板の前記主面から、前記表面半導体層の上面までの厚さが、前記絶縁膜の前記厚膜部に囲まれた領域の中央部において最も薄く、前記絶縁膜の前記厚膜部に近づくに従い徐々に厚くなるように、前記表面半導体層は形成される。     Method for manufacturing a semiconductor device including an IGBT element including the following steps:
    (A) a step of preparing a substrate having a second conductivity type which becomes a base layer of the IGBT;
    (B) forming an insulating film including a thin film portion having a first thickness and a thick film portion having a second thickness greater than the first thickness on a main surface of the substrate;
    (C) forming a first opening reaching the substrate in the thin film portion of the insulating film;
    (D) forming a surface semiconductor layer having the second conductivity type on the thin film portion of the insulating film by embedding the first opening;
    (E) forming a channel layer of the IGBT having a first conductivity type different from the second conductivity type in a predetermined region in the surface semiconductor layer;
    (F) forming a first emitter layer of the IGBT exhibiting the first conductivity type at a higher concentration than the channel layer in a predetermined region in the channel layer;
    (G) After the step (f), forming a gate insulating film of the IGBT on the surface semiconductor layer;
    (H) forming a gate electrode of the IGBT on the gate insulating film;
    (I) Impurities of the second conductivity type are introduced into the surface semiconductor layer, and the first emitter layer of the IGBT is formed in a region of the surface semiconductor layer on both sides of the gate electrode where the first emitter layer is not formed. Forming one source layer;
    (J) forming a sidewall on a side surface of the gate electrode;
    (K) An impurity having the first conductivity type is introduced into the surface semiconductor layer, and the first emitter is formed in a region where the first emitter layer of the surface semiconductor layer on both sides of the sidewall is formed. Forming a second emitter layer of the IGBT having a higher concentration than the layer;
    An impurity having the second conductivity type is introduced into the surface semiconductor layer, and the first source layer is formed in a region where the first source layer of the surface semiconductor layer on both sides of the sidewall is formed. Forming a high concentration second source layer of the IGBT;
    (L) After the step (k), forming a nitride film on the main surface side of the substrate;
    (M) forming a third opening in the nitride film on the gate electrode;
    (N) After the step (m), a step of forming an interlayer insulating film on the main surface side of the substrate;
    (O) etching the interlayer insulating film in the region where the third opening is formed, and the interlayer insulating film and the nitride film on the second emitter layer and the second source layer, to thereby form the gate electrode And forming second openings respectively reaching the second emitter layer and the second source layer;
    (P) forming a source electrode of the IGBT electrically connected to the second emitter layer and the second source layer, and a gate pad electrically connected to the gate electrode;
    (Q) forming the base layer of the IGBT by thinning the substrate from the back surface opposite to the main surface;
    (R) After the step (q), forming a buffer layer of the IGBT showing the second conductivity type on the back side of the substrate;
    (S) After the step (r), a step of forming a collector layer of the IGBT showing the first conductivity type on the back surface side of the substrate;
    (T) forming a collector electrode of the IGBT electrically connected to the collector layer;
    Here, in the step (d), the thickness from the main surface of the substrate to the upper surface of the surface semiconductor layer is the thinnest in the central portion of the region surrounded by the thick film portion of the insulating film, The surface semiconductor layer is formed so as to gradually increase as it approaches the thick film portion of the insulating film.
  11. 　請求項１０記載の半導体装置の製造方法において、
    　前記絶縁膜の前記厚膜部に囲まれた領域は、上面視において第１方向に長辺を有し、前記第１方向と直交する第２方向に短辺を有し、
    　前記第２方向に沿った、前記絶縁膜の前記厚膜部に囲まれた領域の断面において、
    　前記ベース層の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さが、前記ベース層の上面から、前記第２開口部が形成された領域に位置する前記表面半導体層の上面までの厚さよりも薄くなるように、前記表面半導体層が形成されることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 10.
    The region surrounded by the thick film portion of the insulating film has a long side in the first direction in a top view, and a short side in a second direction orthogonal to the first direction,
    In a cross section of the region surrounded by the thick film portion of the insulating film along the second direction,
    The surface semiconductor in which the thickness from the upper surface of the base layer to the upper surface of the surface semiconductor layer located under the gate electrode is located in a region where the second opening is formed from the upper surface of the base layer A method of manufacturing a semiconductor device, wherein the surface semiconductor layer is formed so as to be thinner than a thickness up to an upper surface of the layer.
  12. 　請求項１１記載の半導体装置の製造方法において、
    　前記絶縁膜の前記薄膜部の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さは、３００ｎｍ以下であることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 11.
    A method of manufacturing a semiconductor device, wherein a thickness from an upper surface of the thin film portion of the insulating film to an upper surface of the surface semiconductor layer located under the gate electrode is 300 nm or less.
  13. 　請求項１１記載の半導体装置の製造方法において、
    　前記絶縁膜の前記薄膜部の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さは、１００ｎｍ以下であることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 11.
    A method of manufacturing a semiconductor device, wherein a thickness from an upper surface of the thin film portion of the insulating film to an upper surface of the surface semiconductor layer located under the gate electrode is 100 nm or less.
  14. 　請求項１１記載の半導体装置の製造方法において、
    　前記絶縁膜の前記薄膜部の上面から、前記ゲート電極の下に位置する前記表面半導体層の上面までの厚さは、２０ｎｍ～４０ｎｍの範囲であることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 11.
    A method of manufacturing a semiconductor device, wherein a thickness from an upper surface of the thin film portion of the insulating film to an upper surface of the surface semiconductor layer located under the gate electrode is in a range of 20 nm to 40 nm.
  15. 　請求項１０記載の半導体装置の製造方法において、
    　前記絶縁膜の前記厚膜部の前記第２厚さは、３００ｎｍよりも厚いことを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 10.
    The method of manufacturing a semiconductor device, wherein the second thickness of the thick film portion of the insulating film is greater than 300 nm.
  16. 　請求項１０記載の半導体装置の製造方法において、
    　前記窒化膜の厚さは、５０ｎｍ～７０ｎｍであることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 10.
    A method of manufacturing a semiconductor device, wherein the nitride film has a thickness of 50 nm to 70 nm.
  17. 　請求項１０記載の半導体装置の製造方法において、さらに、前記工程（ｂ）は、以下の工程を含む：
    （ｂ１）前記基板の前記主面上に、前記第２厚さを有する前記絶縁膜を形成する工程；
    （ｂ２）前記厚膜部を形成する領域にレジストパターンを形成する工程；
    （ｂ３）前記レジストパターンをマスクとした等方性ウエットエッチングにより、前記絶縁膜に前記第１厚さを有する前記薄膜部を形成する工程。     11. The method for manufacturing a semiconductor device according to claim 10, wherein the step (b) further includes the following steps:
    (B1) forming the insulating film having the second thickness on the main surface of the substrate;
    (B2) forming a resist pattern in a region where the thick film portion is to be formed;
    (B3) A step of forming the thin film portion having the first thickness on the insulating film by isotropic wet etching using the resist pattern as a mask.
  18. 　請求項１０記載の半導体装置の製造方法において、さらに、前記工程（ｄ）は、以下の工程を含む：
    （ｄ１）前記絶縁膜の前記薄膜部上に、前記絶縁膜の前記厚膜部の前記第２厚さよりも厚い前記第２導電型を示す導電膜を形成する工程；
    （ｄ２）前記導電膜をＣＭＰ法により研磨して、前記絶縁膜の前記薄膜部上に前記表面半導体層を形成する工程。     The method of manufacturing a semiconductor device according to claim 10, wherein the step (d) further includes the following steps:
    (D1) forming a conductive film having the second conductivity type, which is thicker than the second thickness of the thick film portion of the insulating film, on the thin film portion of the insulating film;
    (D2) A step of polishing the conductive film by a CMP method to form the surface semiconductor layer on the thin film portion of the insulating film.
  19. 　請求項１８記載の半導体装置の製造方法において、
    　前記導電膜は、エピタキシャル法により形成されることを特徴とする半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 18.
    The method for manufacturing a semiconductor device, wherein the conductive film is formed by an epitaxial method.
  20. 　以下の工程を含む絶縁ゲート型バイポーラトランジスタの素子を備える半導体装置の製造方法：
    （ａ）基板の主面上に、第１厚さを有する薄膜部と、前記第１厚さよりも厚い第２厚さを有する厚膜部とを含む絶縁膜を形成する工程；
    （ｂ）前記絶縁膜の前記薄膜部に前記基板に達する第１開口部を形成する工程；
    （ｃ）前記工程（ｂ）の後、前記絶縁膜の前記薄膜部上に表面半導体層を、前記第１開口部を埋め込んで形成する工程、
    　ここで、前記基板の主面から前記表面半導体層の上面までの厚さは、前記絶縁膜の前記厚膜部に囲まれた領域の中央部において薄く、前記絶縁膜の前記厚膜部に近づくに従い徐々に厚くなる。     Method for manufacturing a semiconductor device comprising an element of an insulated gate bipolar transistor including the following steps:
    (A) forming an insulating film including a thin film portion having a first thickness and a thick film portion having a second thickness greater than the first thickness on a main surface of the substrate;
    (B) forming a first opening reaching the substrate in the thin film portion of the insulating film;
    (C) After the step (b), forming a surface semiconductor layer on the thin film portion of the insulating film by embedding the first opening,
    Here, the thickness from the main surface of the substrate to the upper surface of the surface semiconductor layer is thin in the central portion of the region surrounded by the thick film portion of the insulating film and approaches the thick film portion of the insulating film. It becomes thicker gradually.
  21. 　以下の工程を含む絶縁ゲート型バイポーラトランジスタの素子を備える半導体装置の製造方法：
    （ａ）基板の主面上に、第１厚さを有する薄膜部と、前記第１厚さよりも厚い第２厚さを有する厚膜部とを含む絶縁膜を形成する工程；
    （ｂ）前記絶縁膜の前記薄膜部に前記基板に達する第１開口部を形成する工程；
    （ｃ）前記工程（ｂ）の後、前記絶縁膜の前記薄膜部上に表面半導体層を、前記第１開口部を埋め込んで形成する工程、
    　ここで、前記絶縁膜の上面から前記表面半導体層の上面までの厚さは、前記絶縁膜の厚膜部に囲まれた領域の中央部において薄く、前記絶縁膜の前記厚膜部に近づくに従い徐々に厚くなるように、前記表面半導体層が形成される。     Method for manufacturing a semiconductor device comprising an element of an insulated gate bipolar transistor including the following steps:
    (A) forming an insulating film including a thin film portion having a first thickness and a thick film portion having a second thickness greater than the first thickness on a main surface of the substrate;
    (B) forming a first opening reaching the substrate in the thin film portion of the insulating film;
    (C) After the step (b), forming a surface semiconductor layer on the thin film portion of the insulating film by embedding the first opening,
    Here, the thickness from the upper surface of the insulating film to the upper surface of the surface semiconductor layer is thin at the center of the region surrounded by the thick film portion of the insulating film, and as the thickness approaches the thick film portion of the insulating film The surface semiconductor layer is formed so as to gradually increase in thickness.
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JP2010062262A (en) * 2008-09-02 2010-03-18 Renesas Technology Corp Semiconductor device and manufacturing method of same

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Publication number Priority date Publication date Assignee Title
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