WO2013132937A1 - Method for manufacturing thin film transistor and method for manufacturing display device - Google Patents

Method for manufacturing thin film transistor and method for manufacturing display device Download PDF

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WO2013132937A1
WO2013132937A1 PCT/JP2013/052487 JP2013052487W WO2013132937A1 WO 2013132937 A1 WO2013132937 A1 WO 2013132937A1 JP 2013052487 W JP2013052487 W JP 2013052487W WO 2013132937 A1 WO2013132937 A1 WO 2013132937A1
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manufacturing
thin film
film transistor
substrate
surface wave
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French (fr)
Japanese (ja)
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東　和文
智子 上野
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株式会社 島津製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/511—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using microwave discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • the present invention relates to a method for manufacturing a thin film transistor and a method for manufacturing a display device.
  • TFT Thin Film Transistor
  • the performance improvement of a thin film transistor has been an issue due to the demand for further performance improvement.
  • the mobility (mobility) is less than 1 cm / V / s.
  • TFTs using polysilicon are used for higher performance.
  • a TFT using an oxide semiconductor such as amorphous IGZO (InGaZnOx) is being put to practical use as an alternative technique.
  • Patent Document 1 In the case of an oxide semiconductor, there is a problem that it deteriorates in a reducing atmosphere during the process.
  • an iridium-based material is used for the source and drain electrodes in order to avoid deterioration in a reducing atmosphere. This is aimed at preventing the diffusion of reducing atoms, molecules and oxygen.
  • Non-Patent Document 1 discloses a top gate type TFT using amorphous IGZO.
  • a SiO2 film formed by a reactive sputtering method using oxygen is used as a gate insulating film.
  • Patent Document 1 a gate insulating film that covers the oxide semiconductor film is formed before the source / drain electrodes are formed. Therefore, the oxide semiconductor film may be reduced in the step of forming the gate insulating film.
  • the electron mobility between a metal atom and an oxygen atom is important.
  • the oxide semiconductor film is reduced in a reducing atmosphere and the composition changes, there is a problem that the mobility of the TFT deteriorates.
  • Non-Patent Document 1 there is a problem of plasma damage to the base when a gate insulating film is formed over the oxide semiconductor film by a sputtering method.
  • a film formed by sputtering generally has a columnar structure, it is difficult to improve characteristics such as voltage resistance.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a thin film transistor capable of obtaining a high-performance oxide semiconductor thin film transistor, and a method for manufacturing a display device using the same.
  • the gate insulating film is formed by the surface wave plasma CVD method, deterioration due to reduction of the oxide semiconductor film can be reduced. Thereby, a high-performance thin film transistor can be obtained.
  • the gate insulating film is formed in a state where the distance between the substrate and the dielectric is 150 mm or more, the concentration of hydrogen radicals in the vicinity of the substrate can be suppressed, so that the oxide semiconductor Reduction of the membrane can be prevented.
  • a microwave propagates through a slot antenna to a dielectric window and becomes a surface wave that forms a standing wave on the surface of the dielectric window. Therefore, reduction of the oxide semiconductor film can be prevented.
  • an IGZO film can be used as the oxide semiconductor film, and a silicon oxide film can be used as the gate insulating film. Furthermore, the above-described method for manufacturing a thin film transistor is suitable for a method for manufacturing a TFT array substrate for a display device.
  • An object of the present invention is to provide a method for manufacturing a thin film transistor capable of obtaining a high-performance oxide semiconductor thin film transistor, and a method for manufacturing a display device using the same.
  • FIG. 5 is a graph showing the emission intensity of hydrogen when the distance between the dielectric window and the substrate is changed in the surface wave plasma CVD apparatus. It is a graph which shows the light emission intensity
  • the thin film transistor according to this embodiment is a thin film transistor using an oxide semiconductor film as an active layer.
  • a cross-sectional structure of this thin film transistor is shown in FIG.
  • the TFT shown in FIG. 1 is, for example, a TFT of a TFT array substrate used in a display device such as a liquid crystal or an organic EL.
  • an insulating film 2 serving as a base of a TFT is formed on the substrate 1.
  • a transparent glass substrate can be used as the substrate 1, and a SiO 2 film can be used as the insulating film 2.
  • the insulating film 2 can be formed by, for example, a plasma CVD method, a sputtering method, or the like, and the film forming method is not particularly limited.
  • source / drain electrodes 3 are formed on the insulating film 2.
  • a metal film such as Mo is formed by sputtering.
  • resist coating, exposure, development, etching, resist removal, and the like are performed, and the metal film is patterned to form the source / drain electrodes 3.
  • the source / drain electrodes 3 may be formed by other materials and methods. Further, in this step, wirings to the source / drain electrodes 3 may be formed.
  • the semiconductor layer 4 is formed on the source / drain electrodes 3.
  • the semiconductor layer 4 is formed of an amorphous oxide film.
  • an ⁇ -IGZO film can be used.
  • an ⁇ -IGZO film is formed by reactive sputtering using an Ar / O 2 mixed gas. Then, resist coating, exposure, development, etching, resist removal, and the like are performed to pattern the ⁇ -IGZO film. Thereby, an island-like semiconductor layer 4 extending from the source electrode 3 to the drain electrode 3 is formed.
  • a gate insulating film 5 is formed so as to cover the semiconductor layer 4.
  • the gate insulating film 5 is formed by forming a SiO 2 film on the entire substrate 1 using a surface wave plasma CVD (Chemical Vapor Deposition) apparatus.
  • a gate insulating film 5 is formed on the entire surface of the substrate 1 using a surface wave plasma CVD method using SiH4 and N2O as source gases.
  • a gate electrode 6 is formed on the gate insulating film 5.
  • an ITO (Indium Tin Oxide) film using a reactive sputtering method using an O2 / Ar mixed gas is formed.
  • the ITO film is patterned by performing resist coating, exposure, development, etching, resist removal, and the like. Thereby, the gate electrode 6 can be formed on the gate insulating film 5.
  • the gate electrode 6 is disposed so as to face the semiconductor layer 4 with the gate insulating film 5 interposed therebetween.
  • a top gate type thin film transistor can be manufactured. For example, when a predetermined gate voltage is supplied to the gate electrode 6, a channel is formed in the semiconductor layer 4. Such thin film transistors are formed in an array on the substrate 1 to manufacture a thin film transistor array substrate.
  • This TFT array substrate can be used as an active matrix substrate for a display device such as liquid crystal or organic EL.
  • the gate insulating film 5 can be formed without reducing or deteriorating the semiconductor layer 4 made of the underlying amorphous IGZO film. Therefore, a high-performance thin film transistor can be manufactured.
  • the composition of the ⁇ -IGZO active layer of the thin film transistor thus obtained was evaluated by fluorescent X-rays, it was confirmed that it was almost the same composition as InGaZnO 4 which was the composition before the formation of the gate insulating film 5 and was not reduced. .
  • FIG. 2 is a front view showing a schematic configuration of the surface wave plasma CVD apparatus.
  • FIG. 3 is a side view showing a schematic configuration of the surface wave plasma CVD apparatus.
  • FIG. 4 is a top view showing a schematic configuration of the surface wave plasma CVD apparatus. 2 to 4 show an example of the device configuration, and dimensions and arrangement of slot antennas are simplified.
  • the surface wave plasma CVD apparatus includes a chamber 11 serving as a reaction chamber.
  • the chamber 11 is provided with an exhaust port 11a.
  • a vacuum pump (not shown) connected to the exhaust port 11a exhausts the chamber 11.
  • gas inlets 14 and 15 are provided on the side wall of the chamber 11.
  • Ar gas is introduced from the gas inlet 14, and SiH 4 gas and N 2 O gas source gases are introduced from the gas inlet 15.
  • the inside of the chamber 11 is controlled to have a predetermined process pressure.
  • the gas introduced into the chamber 11 and the flow rate thereof are not particularly limited.
  • TEOS tetraethoxysilane
  • a stage 17 that can be moved up and down is installed. Then, the substrate 1 on which the semiconductor layer 4 (not shown in FIG. 2) is formed is placed on the stage 17. Note that a heater may be provided on the stage 17 to heat the substrate 1 to an appropriate process temperature.
  • a waveguide 12 through which microwaves propagate is attached above the chamber 11. In the waveguide 12, the microwave propagates from the left side to the right side in FIGS. 2 and 4. The space in the waveguide 12 is at atmospheric pressure.
  • a slot antenna 16 is formed on the upper wall of the chamber 11. The slot antenna 16 is opened in a slit shape, for example. The plurality of slot antennas 16 are arranged in an array. The microwave that has propagated through the waveguide 12 is supplied into the chamber 11 through the slot antenna 16. Furthermore, a dielectric window 13 is installed under the slot antenna 16. The dielectric window 13 is an alumina flat plate, for example, and is provided to separate the space in the waveguide 12 and the space in the chamber 11.
  • the width of the dielectric window 13 is wider than that of the waveguide 12 in a direction (left-right direction in FIG. 3) orthogonal to the microwave traveling direction (left-right direction in FIG. 2). Then, the microwave is introduced into the chamber 11 through the dielectric window 13 and becomes a surface wave that propagates along the surface of the dielectric window 13. More specifically, the microwave propagates through the slot antenna 16 to the dielectric window 13, generates a standing wave on the surface of the dielectric window 13, and becomes a surface wave propagating along the surface of the dielectric window 13. . In the direction orthogonal to the traveling direction of the microwave, the surface wave is formed to be wider than the waveguide 12 on the surface of the dielectric window 13.
  • the number, shape, size, and the like of the slot antenna 16 are not particularly limited.
  • Ar gas introduced from the gas inlet 14 is excited by surface waves along the surface of the dielectric window 13. Thereby, surface wave plasma is generated near the dielectric window 13 of the chamber 11. Thereby, the source gas (SiH 4, N 2 O) introduced from the gas inlet 15 is dissociated, and silicon oxide is deposited on the substrate 1. In this way, the gate insulating film 5 is formed on the semiconductor layer 4 made of the InGaZnO 4 film.
  • the distance (Gap) between the substrate 1 and the dielectric window 13 can be adjusted by moving the stage 17 up and down.
  • the surface wave plasma CVD method a microwave is propagated along the surface of the dielectric window 13 in a surface wave mode. For this reason, plasma exists only in a very thin region near the dielectric window 13 and does not exist in the vicinity of the substrate 1. Thereby, the hydrogen radical concentration in the vicinity of the substrate 1 can be suppressed.
  • the semiconductor layer 4 can be prevented from being reduced by hydrogen radicals. Therefore, deterioration of the semiconductor layer 4 can be prevented, and a high-performance oxide semiconductor thin film transistor can be formed.
  • the gap between the substrate 1 and the dielectric window 13 is preferably 250 mm or less.
  • a TFT having excellent pressure resistance can be manufactured. Further, in the parallel plate type plasma CVD apparatus, plasma is present almost entirely between the parallel plates. Therefore, the hydrogen radical concentration in the vicinity of the substrate 1 is increased, and the semiconductor layer 4 is reduced. Therefore, a high performance thin film transistor can be manufactured by forming the gate insulating film 5 using the surface wave plasma CVD apparatus as in the manufacturing method according to the present embodiment.
  • FIG. 5 shows the measurement results obtained by measuring the emission intensity ratio of H ⁇ with respect to argon, which is a tracer gas, using the actinometry method.
  • FIG. 5 is a graph showing the results of measuring the emission intensity ratio (H ⁇ / Ar) while changing the dielectric window 13, the substrate 1, and the gap. Since the emission intensity ratio is proportional to the hydrogen radical concentration, it can be seen that when the gap is changed from 100 mm to 300 mm, the hydrogen radical concentration rapidly decreases as the gap becomes wider until the gap is near 150 mm. Therefore, the hydrogen radical concentration can be made sufficiently low by setting Gap to 150 mm or more. That is, by setting the gap to 150 mm or more, damage to the substrate 1 due to hydrogen radicals can be reduced.
  • FIGS. 6 and 7 show the measurement results obtained by the actinometry method when the process conditions are changed.
  • FIG. 6 shows the measurement result when the power of the supplied microwave is changed
  • FIG. 7 shows the measurement result when the flow rate of the supplied gas is changed. 6 and 7, the horizontal axis is Gap (mm), and the vertical axis is the emission intensity ratio of H ⁇ to Ar.
  • the process pressure (10 Pa) is the common condition, and the microwave power is changed to 0.7 kW, 1.4 kW, 2.1 kW, and 2.8 kW.
  • the hydrogen radicals decrease as the gap becomes wider.
  • the gap is 150 mm or more, more preferably 200 mm or more
  • the hydrogen radical concentration is sufficiently low. Therefore, damage caused by hydrogen radicals can be reduced by setting the gap to 150 mm or more, more preferably 200 mm or more.
  • the SiH 4 and NH 3 gas flow rates are changed, the hydrogen radical concentration decreases as the gap becomes wider. Therefore, when Gap is 150 mm or more, more preferably 200 mm or more, damage due to hydrogen radicals can be reduced.
  • the gap is set to 150 mm or more, more preferably 200 mm or more.
  • the gap is set to 150 mm or more, more preferably 200 mm or more.
  • an SiO 2 film is formed on the substrate 1 on which amorphous IGZO is formed by surface wave plasma CVD using SiH 4 and N 2 O gas as raw materials.
  • the oxide semiconductor thin film transistor thus obtained has higher mobility than an amorphous silicon semiconductor, and the manufacturing process is less complicated than a polycrystalline silicon semiconductor. Therefore, the oxide semiconductor thin film transistor is suitable for a display device such as a liquid crystal or an organic EL. Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.
  • the present invention is applicable to a method for manufacturing a thin film transistor capable of obtaining a high-performance oxide semiconductor thin film transistor, and a method for manufacturing a display device using the same.

Abstract

Provided are a method for manufacturing thin film transistors with which a high efficiency oxide semiconductor thin film transistor can be obtained and a method for manufacturing display devices using the same. The method for manufacturing thin film transistors relating to one aspect of the invention is provided with a step for forming, on a substrate (1), a semiconductor layer (4) which is the oxide semiconductor film, and a step for forming, on the semiconductor layer (4), a gate insulator film (5) using a surface wave plasma CVD method. Further, with the surface wave plasma CVD method, it is preferable to separate the substrate (1) and a dielectric body by a gap of at least 150 mm.

Description

薄膜トランジスタの製造方法、及び表示装置の製造方法Thin film transistor manufacturing method and display device manufacturing method
　本発明は、薄膜トランジスタの製造方法、及び表示装置の製造方法に関する。 The present invention relates to a method for manufacturing a thin film transistor and a method for manufacturing a display device.
　液晶や有機ＥＬ等の表示装置では、これまで以上の性能向上の要求から、薄膜トランジスタ（ＴＦＴ：Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ）の性能向上が課題となっている。非晶質（アモルファス）シリコンを用いたＴＦＴでは、易動度（移動度）が１ｃｍ／Ｖ／ｓに満たない。このため、ポリシリコンを用いたＴＦＴが高性能化のために利用されている。しかしながら、ポリシリコンを用いるプロセスは低コスト化が難しいため、これに代わる技術として、非晶質ＩＧＺＯ（ＩｎＧａＺｎＯｘ）等の酸化物半導体を用いるＴＦＴが実用化されつつある。 In a display device such as a liquid crystal display or an organic EL display, the performance improvement of a thin film transistor (TFT: Thin Film Transistor) has been an issue due to the demand for further performance improvement. In a TFT using amorphous silicon, the mobility (mobility) is less than 1 cm / V / s. For this reason, TFTs using polysilicon are used for higher performance. However, since it is difficult to reduce the cost of a process using polysilicon, a TFT using an oxide semiconductor such as amorphous IGZO (InGaZnOx) is being put to practical use as an alternative technique.
　酸化物半導体の場合、プロセス中に還元雰囲気化で劣化するという問題がある。例えば、特許文献１では、還元雰囲気化の劣化を避けるために、ソース、ドレイン電極にイリジウム系材料を用いている。こうすることで、還元性の原子、分子、酸素の拡散防止を狙っている。 In the case of an oxide semiconductor, there is a problem that it deteriorates in a reducing atmosphere during the process. For example, in Patent Document 1, an iridium-based material is used for the source and drain electrodes in order to avoid deterioration in a reducing atmosphere. This is aimed at preventing the diffusion of reducing atoms, molecules and oxygen.
　また、非特許文献１には、非晶質ＩＧＺＯを用いたトップゲート型のＴＦＴが開示されている。非特許文献１では、酸素を用いた反応性スパッタリング法によって形成したＳｉＯ２膜をゲート絶縁膜として用いている。 Further, Non-Patent Document 1 discloses a top gate type TFT using amorphous IGZO. In Non-Patent Document 1, a SiO2 film formed by a reactive sputtering method using oxygen is used as a gate insulating film.
特開２０１０－２７２６６３号公報JP 2010-272663 A
　しかしながら、特許文献１では、ソース・ドレイン電極を形成する前に、酸化物半導体膜を覆うゲート絶縁膜を成膜している。従って、ゲート絶縁膜の形成工程で、酸化物半導体膜が還元されてしまうおそれがある。酸化物半導体では、金属原子と酸素原子の間の電子移動度が重要である。例えば、還元雰囲気下で酸化物半導体膜が還元されて、組成が変化してしまうと、ＴＦＴの易動度が劣化してしまうという問題がある。また、非特許文献１では、酸化物半導体膜上に、スパッタリング法を用いてゲート絶縁膜を成膜した場合、下地へのプラズマダメージの問題がある。また、スパッタリング法で成膜された膜は、一般的に、柱状構造となるため、耐電圧性等の特性を高くすることが困難である。 However, in Patent Document 1, a gate insulating film that covers the oxide semiconductor film is formed before the source / drain electrodes are formed. Therefore, the oxide semiconductor film may be reduced in the step of forming the gate insulating film. In an oxide semiconductor, the electron mobility between a metal atom and an oxygen atom is important. For example, when the oxide semiconductor film is reduced in a reducing atmosphere and the composition changes, there is a problem that the mobility of the TFT deteriorates. In Non-Patent Document 1, there is a problem of plasma damage to the base when a gate insulating film is formed over the oxide semiconductor film by a sputtering method. In addition, since a film formed by sputtering generally has a columnar structure, it is difficult to improve characteristics such as voltage resistance.
　本発明は、上記の問題点に鑑みてなされたものであり、高性能の酸化物半導体薄膜トランジスタを得ることができる薄膜トランジスタの製造方法、及びそれを用いた表示装置の製造方法を提供することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a thin film transistor capable of obtaining a high-performance oxide semiconductor thin film transistor, and a method for manufacturing a display device using the same. And
　本発明の第１の態様に係る薄膜トランジスタの製造方法によれば、表面波プラズマＣＶＤ法によって、ゲート絶縁膜を形成しているため、酸化物半導体膜の還元による劣化を低減することができる。これにより、高性能な薄膜トランジスタを得ることができる。 According to the method for manufacturing a thin film transistor according to the first aspect of the present invention, since the gate insulating film is formed by the surface wave plasma CVD method, deterioration due to reduction of the oxide semiconductor film can be reduced. Thereby, a high-performance thin film transistor can be obtained.
　上記の製造方法において、基板と誘電体との距離を１５０ｍｍ以上とした状態で、ゲート絶縁膜を成膜することで、基板の近傍での水素ラジカル濃度を抑制することができるため、酸化物半導体膜の還元を防ぐことができる。 In the above manufacturing method, since the gate insulating film is formed in a state where the distance between the substrate and the dielectric is 150 mm or more, the concentration of hydrogen radicals in the vicinity of the substrate can be suppressed, so that the oxide semiconductor Reduction of the membrane can be prevented.
　上記の製造方法において、前記表面波プラズマＣＶＤ法では、スロットアンテナを通して誘電体窓にマイクロ波が伝播し、前記誘電体窓の表面で定在波が形成する表面波となることで、基板の近傍での水素ラジカル濃度を抑制することができるため、酸化物半導体膜の還元を防ぐことができる。 In the manufacturing method described above, in the surface wave plasma CVD method, a microwave propagates through a slot antenna to a dielectric window and becomes a surface wave that forms a standing wave on the surface of the dielectric window. Therefore, reduction of the oxide semiconductor film can be prevented.
　上記の製造方法の好適な実施形態として、酸化物半導体膜としてＩＧＺＯ膜を用いることができ、ゲート絶縁膜として酸化ケイ素膜を用いることができる。さらに、上記の薄膜トランジスタの製造方法は、表示装置用のＴＦＴアレイ基板の製造方法に好適である。 As a preferred embodiment of the above manufacturing method, an IGZO film can be used as the oxide semiconductor film, and a silicon oxide film can be used as the gate insulating film. Furthermore, the above-described method for manufacturing a thin film transistor is suitable for a method for manufacturing a TFT array substrate for a display device.
　本発明によれば、高性能の酸化物半導体薄膜トランジスタを得ることができる薄膜トランジスタの製造方法、及びそれを用いた表示装置の製造方法を提供することを目的とする。 An object of the present invention is to provide a method for manufacturing a thin film transistor capable of obtaining a high-performance oxide semiconductor thin film transistor, and a method for manufacturing a display device using the same.
本実施の形態に係る薄膜トランジスタの断面構造を示す図である。It is a figure which shows the cross-section of the thin-film transistor which concerns on this Embodiment. ゲート絶縁膜を成膜する表面波プラズマＣＶＤ装置の構成を模式的に示す正面図である。It is a front view which shows typically the structure of the surface wave plasma CVD apparatus which forms a gate insulating film. ゲート絶縁膜を成膜する表面波プラズマＣＶＤ装置の構成を模式的に示す側面図である。It is a side view which shows typically the structure of the surface wave plasma CVD apparatus which forms a gate insulating film. ゲート絶縁膜を成膜する表面波プラズマＣＶＤ装置の構成を模式的に示す上面図である。It is a top view which shows typically the structure of the surface wave plasma CVD apparatus which forms a gate insulating film. 表面波プラズマＣＶＤ装置において、誘電体窓と基板間距離を変化させた時の水素の発光強度を示すグラフである。5 is a graph showing the emission intensity of hydrogen when the distance between the dielectric window and the substrate is changed in the surface wave plasma CVD apparatus. 表面波プラズマＣＶＤ装置において、マイクロ波パワーを変えた時の水素の発光強度を示すグラフである。It is a graph which shows the light emission intensity | strength of hydrogen when a microwave power is changed in a surface wave plasma CVD apparatus. 表面波プラズマＣＶＤ装置において、ガス流量を変えた時の水素の発光強度を示すグラフである。It is a graph which shows the emitted light intensity of hydrogen when a gas flow rate is changed in a surface wave plasma CVD apparatus.
　本実施の形態に係る薄膜トランジスタは、酸化物半導体膜を活性層として用いた薄膜トランジスタである。この薄膜トランジスタの断面構成を図１に示す。以下、図１を参照して、薄膜トランジスタの製造方法について説明する。図１に示すＴＦＴは、例えば、液晶や有機ＥＬ等の表示装置に用いられるＴＦＴアレイ基板のＴＦＴである。 The thin film transistor according to this embodiment is a thin film transistor using an oxide semiconductor film as an active layer. A cross-sectional structure of this thin film transistor is shown in FIG. Hereinafter, a method of manufacturing a thin film transistor will be described with reference to FIG. The TFT shown in FIG. 1 is, for example, a TFT of a TFT array substrate used in a display device such as a liquid crystal or an organic EL.
　まず、基板１の上に、ＴＦＴの下地となる絶縁膜２を形成する。基板１としては、例えば、透明なガラス基板を用いることでき、絶縁膜２としては、ＳｉＯ２膜を用いることができる。絶縁膜２は、例えば、プラズマＣＶＤ法、スパッタリング法等で形成することができ、特に成膜法は限定されるものではない。次に、絶縁膜２の上に、ソース・ドレイン電極３を形成する。例えば、スパッタリング法でＭｏ等の金属膜を形成する。そして、レジスト塗布、露光、現像、エッチング、レジスト除去などを行い、金属膜をパターニングすることで、ソース・ドレイン電極３が形成される。もちろん、これ以外の、材料、方法で、ソース・ドレイン電極３を形成してもよい。さらには、この工程で、ソース・ドレイン電極３への配線等を形成してもよい。 First, an insulating film 2 serving as a base of a TFT is formed on the substrate 1. For example, a transparent glass substrate can be used as the substrate 1, and a SiO 2 film can be used as the insulating film 2. The insulating film 2 can be formed by, for example, a plasma CVD method, a sputtering method, or the like, and the film forming method is not particularly limited. Next, source / drain electrodes 3 are formed on the insulating film 2. For example, a metal film such as Mo is formed by sputtering. Then, resist coating, exposure, development, etching, resist removal, and the like are performed, and the metal film is patterned to form the source / drain electrodes 3. Of course, the source / drain electrodes 3 may be formed by other materials and methods. Further, in this step, wirings to the source / drain electrodes 3 may be formed.
　次に、ソース・ドレイン電極３の上に、半導体層４を形成する。半導体層４は、非晶質酸化物膜によって形成され、具体的には、α－ＩＧＺＯ膜を用いることができる。例えば、Ａｒ／Ｏ２混合ガスを用いた反応性スパッタリングにより、α－ＩＧＺＯ膜を成膜する。そして、レジスト塗布、露光、現像、エッチング、レジスト除去などを行い、α－ＩＧＺＯ膜をパターニングする。これにより、ソース電極３上からドレイン電極３上に渡って延在する島状の半導体層４が形成される。 Next, the semiconductor layer 4 is formed on the source / drain electrodes 3. The semiconductor layer 4 is formed of an amorphous oxide film. Specifically, an α-IGZO film can be used. For example, an α-IGZO film is formed by reactive sputtering using an Ar / O 2 mixed gas. Then, resist coating, exposure, development, etching, resist removal, and the like are performed to pattern the α-IGZO film. Thereby, an island-like semiconductor layer 4 extending from the source electrode 3 to the drain electrode 3 is formed.
　次に、半導体層４を覆うようにゲート絶縁膜５を形成する。ここでは、表面波プラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）装置を用いて基板１の全体にＳｉＯ２膜を成膜することで、ゲート絶縁膜５が形成される。ＳｉＨ４とＮ２Ｏを原料ガスとした表面波プラズマＣＶＤ法を用いて、基板１全面にゲート絶縁膜５を形成する。そして、ゲート絶縁膜５の上から、ゲート電極６を形成する。例えば、Ｏ２／Ａｒ混合ガスを用いた反応性スパッタリング法を用いたＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）膜を成膜する。そして、レジスト塗布、露光、現像、エッチング、レジスト除去等を行うことで、ＩＴＯ膜をパターニングする。これにより、ゲート絶縁膜５上に、ゲート電極６を形成することができる。ゲート電極６は、ゲート絶縁膜５を介して、半導体層４と対向するよう配置される。 Next, a gate insulating film 5 is formed so as to cover the semiconductor layer 4. Here, the gate insulating film 5 is formed by forming a SiO 2 film on the entire substrate 1 using a surface wave plasma CVD (Chemical Vapor Deposition) apparatus. A gate insulating film 5 is formed on the entire surface of the substrate 1 using a surface wave plasma CVD method using SiH4 and N2O as source gases. Then, a gate electrode 6 is formed on the gate insulating film 5. For example, an ITO (Indium Tin Oxide) film using a reactive sputtering method using an O2 / Ar mixed gas is formed. Then, the ITO film is patterned by performing resist coating, exposure, development, etching, resist removal, and the like. Thereby, the gate electrode 6 can be formed on the gate insulating film 5. The gate electrode 6 is disposed so as to face the semiconductor layer 4 with the gate insulating film 5 interposed therebetween.
　このようにすることで、トップゲート型の薄膜トランジスタを製造することができる。例えば、ゲート電極６に所定のゲート電圧を供給すると、半導体層４にチャネルが形成される。このような薄膜トランジスタを基板１上にアレイ状に形成して、薄膜トランジスタアレイ基板を製造する。このＴＦＴアレイ基板を液晶や有機ＥＬ等の表示装置のアクティブマトリクス基板として用いることができる。 In this way, a top gate type thin film transistor can be manufactured. For example, when a predetermined gate voltage is supplied to the gate electrode 6, a channel is formed in the semiconductor layer 4. Such thin film transistors are formed in an array on the substrate 1 to manufacture a thin film transistor array substrate. This TFT array substrate can be used as an active matrix substrate for a display device such as liquid crystal or organic EL.
　本実施の形態では、表面波プラズマＣＶＤ法を用いているため、下地の非晶質ＩＧＺＯ膜から成る半導体層４を還元・劣化させることなく、ゲート絶縁膜５を形成することができる。よって、高性能の薄膜トランジスタを製造することができる。こうして得られた薄膜トランジスタのα－ＩＧＺＯ活性層の組成を蛍光Ｘ線により評価したところ、ゲート絶縁膜５の形成前の組成であるＩｎＧａＺｎＯ４とほぼ同じ組成であり、還元されていないことが確認できた。 In this embodiment, since the surface wave plasma CVD method is used, the gate insulating film 5 can be formed without reducing or deteriorating the semiconductor layer 4 made of the underlying amorphous IGZO film. Therefore, a high-performance thin film transistor can be manufactured. When the composition of the α-IGZO active layer of the thin film transistor thus obtained was evaluated by fluorescent X-rays, it was confirmed that it was almost the same composition as InGaZnO 4 which was the composition before the formation of the gate insulating film 5 and was not reduced. .
　次に、ゲート絶縁膜５の成膜方法について、詳細に説明する。本実施の形態では、表面波プラズマＣＶＤ法を用いて、ゲート絶縁膜５を成膜している。この表面波プラズマＣＶＤ装置について、図２～図４を用いて説明する。図２は、表面波プラズマＣＶＤ装置の概略構成を示す正面図である。図３は、表面波プラズマＣＶＤ装置の概略構成を示す側面図である。図４は、表面波プラズマＣＶＤ装置の概略構成を示す上面図である。なお、図２～図４は、装置構成の一例であり、寸法やスロットアンテナの配置などは簡略化されている。 Next, a method for forming the gate insulating film 5 will be described in detail. In this embodiment, the gate insulating film 5 is formed using a surface wave plasma CVD method. This surface wave plasma CVD apparatus will be described with reference to FIGS. FIG. 2 is a front view showing a schematic configuration of the surface wave plasma CVD apparatus. FIG. 3 is a side view showing a schematic configuration of the surface wave plasma CVD apparatus. FIG. 4 is a top view showing a schematic configuration of the surface wave plasma CVD apparatus. 2 to 4 show an example of the device configuration, and dimensions and arrangement of slot antennas are simplified.
　表面波プラズマＣＶＤ装置には、反応室となるチャンバー１１を備えている。チャンバー１１には、排気口１１ａが設けられている。そして、排気口１１ａに接続された真空ポンプ（不図示）が、チャンバー１１を排気している。さらに、チャンバー１１の側壁には、ガス導入口１４、１５が設けられている。ガス導入口１４からはＡｒガスが導入され、ガス導入口１５からは、ＳｉＨ４ガス、及びＮ２Ｏガスの原料ガスが導入される。ガス導入口１４、１５から導入されるガスを、排気口１１ａから排気することで、チャンバー１１内が所定のプロセス圧力になるように制御される。もちろん、チャンバー１１内に導入されるガス、及びその流量については、特に限定されるものではない。例えば、テトラエトキシシラン（ＴＥＯＳ）を原料ガスとして用いてもよい。 The surface wave plasma CVD apparatus includes a chamber 11 serving as a reaction chamber. The chamber 11 is provided with an exhaust port 11a. A vacuum pump (not shown) connected to the exhaust port 11a exhausts the chamber 11. Further, gas inlets 14 and 15 are provided on the side wall of the chamber 11. Ar gas is introduced from the gas inlet 14, and SiH 4 gas and N 2 O gas source gases are introduced from the gas inlet 15. By exhausting the gas introduced from the gas inlets 14 and 15 from the exhaust port 11a, the inside of the chamber 11 is controlled to have a predetermined process pressure. Of course, the gas introduced into the chamber 11 and the flow rate thereof are not particularly limited. For example, tetraethoxysilane (TEOS) may be used as the source gas.
　チャンバー１１内には、昇降可能なステージ１７が設置されている。そして、ステージ１７上に、半導体層４（図２では図示せず）が形成された基板１を載置する。なお、ステージ１７にヒータを設け、基板１を適切なプロセス温度に加熱してもよい。チャンバー１１の上方には、マイクロ波が伝播する導波管１２が取り付けられている。導波管１２において、マイクロ波は、図２、及び図４において、左側から右側に伝播する。導波管１２内の空間は、大気圧となっている。チャンバー１１の上壁には、スロットアンテナ１６が形成されている。スロットアンテナ１６は、例えば、スリット状に開口している。そして、複数のスロットアンテナ１６はアレイ状にされている。このスロットアンテナ１６を介して、導波管１２を伝播してきたマイクロ波がチャンバー１１内に供給される。さらに、スロットアンテナ１６の下には、誘電体窓１３が設置されている。誘電体窓１３は、例えば、アルミナの平板であり、導波管１２内の空間とチャンバー１１内の空間とを隔てるために設けられている。 In the chamber 11, a stage 17 that can be moved up and down is installed. Then, the substrate 1 on which the semiconductor layer 4 (not shown in FIG. 2) is formed is placed on the stage 17. Note that a heater may be provided on the stage 17 to heat the substrate 1 to an appropriate process temperature. A waveguide 12 through which microwaves propagate is attached above the chamber 11. In the waveguide 12, the microwave propagates from the left side to the right side in FIGS. 2 and 4. The space in the waveguide 12 is at atmospheric pressure. A slot antenna 16 is formed on the upper wall of the chamber 11. The slot antenna 16 is opened in a slit shape, for example. The plurality of slot antennas 16 are arranged in an array. The microwave that has propagated through the waveguide 12 is supplied into the chamber 11 through the slot antenna 16. Furthermore, a dielectric window 13 is installed under the slot antenna 16. The dielectric window 13 is an alumina flat plate, for example, and is provided to separate the space in the waveguide 12 and the space in the chamber 11.
　マイクロ波の進行方向（図２の左右方向）と直交する方向（図３の左右方向）において、誘電体窓１３の幅は、導波管１２よりも広くなっている。そして、マイクロ波は、誘電体窓１３を介してチャンバー１１に導入され、誘電体窓１３の表面に沿って伝播する表面波となる。より具体的には、スロットアンテナ１６を通して誘電体窓１３にマイクロ波が伝播し、誘電体窓１３の表面で定在波を生じて、誘電体窓１３の表面に沿って伝播する表面波となる。マイクロ波の進行方向と直交する方向において、誘電体窓１３の表面では、表面波が導波管１２よりも広がって形成される。なお、スロットアンテナ１６の数、形状、大きさ等については特に限定されるものではない。 The width of the dielectric window 13 is wider than that of the waveguide 12 in a direction (left-right direction in FIG. 3) orthogonal to the microwave traveling direction (left-right direction in FIG. 2). Then, the microwave is introduced into the chamber 11 through the dielectric window 13 and becomes a surface wave that propagates along the surface of the dielectric window 13. More specifically, the microwave propagates through the slot antenna 16 to the dielectric window 13, generates a standing wave on the surface of the dielectric window 13, and becomes a surface wave propagating along the surface of the dielectric window 13. . In the direction orthogonal to the traveling direction of the microwave, the surface wave is formed to be wider than the waveguide 12 on the surface of the dielectric window 13. The number, shape, size, and the like of the slot antenna 16 are not particularly limited.
　ガス導入口１４から導入されたＡｒガスが、誘電体窓１３の表面に沿った表面波によって励起される。これにより、チャンバー１１の誘電体窓１３の近傍には、表面波プラズマが生成される。これにより、ガス導入口１５から導入された原料ガス（ＳｉＨ４、Ｎ２Ｏ）が解離され、酸化ケイ素が基板１に堆積される。このようにして、ＩｎＧａＺｎＯ４膜からなる半導体層４上にゲート絶縁膜５が成膜される。なお、ステージ１７を昇降することで、基板１と誘電体窓１３との距離（Ｇａｐ）が調整可能になっている。 Ar gas introduced from the gas inlet 14 is excited by surface waves along the surface of the dielectric window 13. Thereby, surface wave plasma is generated near the dielectric window 13 of the chamber 11. Thereby, the source gas (SiH 4, N 2 O) introduced from the gas inlet 15 is dissociated, and silicon oxide is deposited on the substrate 1. In this way, the gate insulating film 5 is formed on the semiconductor layer 4 made of the InGaZnO 4 film. The distance (Gap) between the substrate 1 and the dielectric window 13 can be adjusted by moving the stage 17 up and down.
　半導体層４を劣化させることなく、プラズマＣＶＤ法を用いて、ゲート絶縁膜５を形成するためには、ゲート絶縁膜５の形成プロセスの際に、基板１の近傍での水素ラジカルを大幅に削減することが重要である。本件出願の発明者らは表面波プラズマＣＶＤ装置を用いた絶縁膜形成を行ってきた結果、基板１を誘電体窓１３から１５０ｍｍ以上離しても、十分な電子密度の条件下で、高速成膜が可能であることを確認している。さらに、発明者らは、水素ラジカルの寿命は、シランが分解されて生じる前駆体（ＳｉＨｘ）よりも短く、誘電体窓１３から基板１を離すことで、水素ラジカル濃度の低い環境下で成膜できることを見出している。 In order to form the gate insulating film 5 using the plasma CVD method without deteriorating the semiconductor layer 4, hydrogen radicals in the vicinity of the substrate 1 are greatly reduced during the formation process of the gate insulating film 5. It is important to. The inventors of the present application have formed an insulating film using a surface wave plasma CVD apparatus. As a result, even if the substrate 1 is separated from the dielectric window 13 by 150 mm or more, high-speed film formation is performed under conditions of sufficient electron density. Confirm that it is possible. Furthermore, the inventors have a life of hydrogen radicals shorter than that of a precursor (SiHx) generated by decomposition of silane, and the substrate 1 is separated from the dielectric window 13 to form a film in an environment with a low hydrogen radical concentration. I find out what I can do.
　表面波プラズマＣＶＤ法では、マイクロ波が誘電体窓１３の表面に沿って伝播する表面波モードとなる。このため、プラズマが誘電体窓１３の付近のごく薄い領域にのみ存在し、基板１の近傍には存在しなくなる。これにより、基板１の近傍における水素ラジカル濃度を抑制することができる。水素ラジカルによって半導体層４が還元されるのを防ぐことができる。よって、半導体層４の劣化を防ぐことができ、高性能な酸化物半導体薄膜トランジスタを形成することができる。また、成膜速度の低下を防ぐために、基板１と誘電体窓１３との間のＧａｐを２５０ｍｍ以下とすることが好ましい。 In the surface wave plasma CVD method, a microwave is propagated along the surface of the dielectric window 13 in a surface wave mode. For this reason, plasma exists only in a very thin region near the dielectric window 13 and does not exist in the vicinity of the substrate 1. Thereby, the hydrogen radical concentration in the vicinity of the substrate 1 can be suppressed. The semiconductor layer 4 can be prevented from being reduced by hydrogen radicals. Therefore, deterioration of the semiconductor layer 4 can be prevented, and a high-performance oxide semiconductor thin film transistor can be formed. In order to prevent the film formation rate from decreasing, the gap between the substrate 1 and the dielectric window 13 is preferably 250 mm or less.
　ゲート絶縁膜５の形成に、スパッタリング法を用いていないため、耐圧性の優れたＴＦＴを製造することができる。また、平行平板型のプラズマＣＶＤ装置では、平行平板間のほぼ全体にプラズマが存在してしまう。従って、基板１の近傍での水素ラジカル濃度が高くなり、半導体層４が還元されてしまう。よって、本実施形態にかかる製造方法のように、表面波プラズマＣＶＤ装置を用いて、ゲート絶縁膜５を成膜することで、高性能の薄膜トランジスタを製造することができる。 Since the sputtering method is not used for forming the gate insulating film 5, a TFT having excellent pressure resistance can be manufactured. Further, in the parallel plate type plasma CVD apparatus, plasma is present almost entirely between the parallel plates. Therefore, the hydrogen radical concentration in the vicinity of the substrate 1 is increased, and the semiconductor layer 4 is reduced. Therefore, a high performance thin film transistor can be manufactured by forming the gate insulating film 5 using the surface wave plasma CVD apparatus as in the manufacturing method according to the present embodiment.
　アクチノメトリ法を用いて、トレーサガスであるアルゴンに対するＨαの発光強度比を測定した測定結果を図５に示す。図５は、誘電体窓１３と基板１とＧａｐを変えて、発光強度比（Ｈα／Ａｒ）を測定した結果を示すグラフである。この発光強度比と水素ラジカル濃度は比例することから、Ｇａｐを１００ｍｍから３００ｍｍに変えた場合、Ｇａｐが１５０ｍｍ付近までは、Ｇａｐが広くなるにつれて急激に水素ラジカル濃度が減少することが分かる。従って、Ｇａｐを１５０ｍｍ以上にすることで、水素ラジカル濃度が十分に低い状態とすることができる。すなわち、Ｇａｐを１５０ｍｍ以上にすることで、水素ラジカルによる基板１へのダメージを軽減することができる。 FIG. 5 shows the measurement results obtained by measuring the emission intensity ratio of Hα with respect to argon, which is a tracer gas, using the actinometry method. FIG. 5 is a graph showing the results of measuring the emission intensity ratio (Hα / Ar) while changing the dielectric window 13, the substrate 1, and the gap. Since the emission intensity ratio is proportional to the hydrogen radical concentration, it can be seen that when the gap is changed from 100 mm to 300 mm, the hydrogen radical concentration rapidly decreases as the gap becomes wider until the gap is near 150 mm. Therefore, the hydrogen radical concentration can be made sufficiently low by setting Gap to 150 mm or more. That is, by setting the gap to 150 mm or more, damage to the substrate 1 due to hydrogen radicals can be reduced.
　さらに、本件出願の発明者は、種々の実験を行い、基板１へのダメージの観点から、Ｇａｐを１５０ｍｍ以上とすることが好ましく、さらに２００ｍｍ以上とより好ましいことを見出した。本件出願の発明者が行った実験例について、以下に説明する。図６、７にプロセス条件を変えた時のアクチノメトリ法による測定結果を示す。図６は、供給するマイクロ波のパワーを変えた時の測定結果を示しており、図７は、供給するガスの流量を変えた時の測定結果を示している。図６、７において、横軸は、Ｇａｐ（ｍｍ）であり、縦軸は、Ａｒに対するＨαの発光強度比である。 Furthermore, the inventor of the present application has conducted various experiments and found that the gap is preferably 150 mm or more and more preferably 200 mm or more from the viewpoint of damage to the substrate 1. Experimental examples conducted by the inventors of the present application will be described below. FIGS. 6 and 7 show the measurement results obtained by the actinometry method when the process conditions are changed. FIG. 6 shows the measurement result when the power of the supplied microwave is changed, and FIG. 7 shows the measurement result when the flow rate of the supplied gas is changed. 6 and 7, the horizontal axis is Gap (mm), and the vertical axis is the emission intensity ratio of Hα to Ar.
　図６では、ＳｉＨ４のガス流量（３５ｓｃｃｍ＝５．９１×１０‐３Ｐａ・ｍ３／ｓｅｃ）、ＮＨ３のガス流量（２５０ｓｃｃｍ＝４．２２×１０‐１Ｐａ・ｍ３／ｓｅｃ）、Ａｒのガス流量（１７５ｓｃｃｍ＝２．９６２×１０‐１Ｐａ・ｍ３／ｓｅｃ）、プロセス圧力（１０Ｐａ）を共通の条件として、マイクロ波パワーを０．７ｋＷ，１．４ｋＷ、２．１ｋＷ、２．８ｋＷと変えている。図６に示すように、マイクロ波パワーを変えていったとしても、Ｇａｐが広くなるほど、水素ラジカルが減少していく。そして、Ｇａｐを１５０ｍｍ以上、さらに好ましくは２００ｍｍ以上とすると、水素ラジカル濃度が十分に低くなる。よって、Ｇａｐを、１５０ｍｍ以上、より好ましくは２００ｍｍ以上とすることで、水素ラジカルによるダメージを軽減することができる。 In FIG. 6, the gas flow rate of SiH4 (35 sccm = 5.91 × 10 −3 Pa · m 3 / sec), the gas flow rate of NH 3 (250 sccm = 4.22 × 10 −1 Pa · m 3 / sec), the gas flow rate of Ar (175 sccm). = 2.962 × 10 −1 Pa · m 3 / sec), the process pressure (10 Pa) is the common condition, and the microwave power is changed to 0.7 kW, 1.4 kW, 2.1 kW, and 2.8 kW. As shown in FIG. 6, even when the microwave power is changed, the hydrogen radicals decrease as the gap becomes wider. When the gap is 150 mm or more, more preferably 200 mm or more, the hydrogen radical concentration is sufficiently low. Therefore, damage caused by hydrogen radicals can be reduced by setting the gap to 150 mm or more, more preferably 200 mm or more.
　図７では、Ａｒのガス流量（１７５ｓｃｃｍ＝２．９６×１０‐１Ｐａ・ｍ３／ｓｅｃ）、プロセス圧力（１０Ｐａ）、マイクロ波パワーを１．４ｋＷと共通の条件として、ＳｉＨ４のガス流量とＮＨ３のガス流量条件を変えていった時の測定結果を示している。具体的には、ガス流量の基準ｓｔｄをＳｉＨ４：３５ｓｃｃｍ＝５．９１×１０‐３Ｐａ・ｍ３／ｓｅｃ、ＮＨ３：２５０ｓｃｃｍ＝４．２２×１０‐１Ｐａ・ｍ３／ｓｅｃとして、ＳｉＨ４、及びＮＨ３のガス流量を条件２（Ｓｉ：７０ｓｃｃｍ＝１．１８×１０‐２Ｐａ・ｍ３／ｓｅｃ、ＮＨ３：５００ｓｃｃｍ＝８．４４×１０‐１Ｐａ・ｍ３／ｓｅｃ）、条件３（Ｓｉ：１４０ｓｃｃｍ＝２．３６×１０‐２Ｐａ・ｍ３／ｓｅｃ、ＮＨ３：１０００ｓｃｃｍ＝１．６９Ｐａ・ｍ３／ｓｅｃ）、条件４（Ｓｉ：２８０ｓｃｃｍ＝４．７３×１０‐２Ｐａ・ｍ３／ｓｅｃ、ＮＨ３：２０００ｓｃｃｍ＝３．３８Ｐａ・ｍ３／ｓｅｃ）と変えている。このように、ＳｉＨ４、及びＮＨ３ガス流量を変えていったとしても、Ｇａｐが広くなるほど、水素ラジカル濃度が減少していく。よって、Ｇａｐが１５０ｍｍ以上、より好ましくは２００ｍｍ以上とすることで、水素ラジカルによるダメージを軽減することができる。 In FIG. 7, assuming that the Ar gas flow rate (175 sccm = 2.96 × 10 −1 Pa · m 3 / sec), the process pressure (10 Pa), and the microwave power are 1.4 kW, the gas flow rate of SiH 4 and NH 3 are the same. The measurement result when changing the gas flow rate condition is shown. Specifically, the gas flow rate standard std is SiH4: 35 sccm = 5.91 × 10 −3 Pa · m 3 / sec, NH 3: 250 sccm = 4.22 × 10 −1 Pa · m 3 / sec, and SiH 4 and NH 3 gas. The flow rate is condition 2 (Si: 70 sccm = 1.18 × 10 −2 Pa · m 3 / sec, NH 3: 500 sccm = 8.44 × 10 −1 Pa · m 3 / sec), condition 3 (Si: 140 sccm = 2.36 × 10 −2 Pa · m 3 / sec, NH 3: 1000 sccm = 1.69 Pa · m 3 / sec, Condition 4 (Si: 280 sccm = 4.73 × 10 −2 Pa · m 3 / sec, NH 3: 2000 sccm = 3.38 Pa · m 3 / sec) ). Thus, even if the SiH 4 and NH 3 gas flow rates are changed, the hydrogen radical concentration decreases as the gap becomes wider. Therefore, when Gap is 150 mm or more, more preferably 200 mm or more, damage due to hydrogen radicals can be reduced.
　このようにガス流量やマイクロ波パワーによらず、Ｇａｐを１５０ｍｍ以上、より好ましくは２００ｍｍ以上とすることで、水素ラジカルによる基板１へのダメージを軽減することができる。また、本件出願の発明者は、その他の種々の実験を行った結果、装置構成やプロセス条件によって、表面波プラズマの状態に大きな違いはなく、Ｇａｐを１５０ｍｍ以上、より好ましくは２００ｍｍ以上とすることで、水素ラジカルによる基板１へのダメージを軽減することができることを見出した。このようにすることで、特性の優れた酸化物半導体薄膜トランジスタを製造することができる。 Thus, regardless of the gas flow rate or the microwave power, by setting the gap to 150 mm or more, more preferably 200 mm or more, damage to the substrate 1 due to hydrogen radicals can be reduced. In addition, as a result of conducting various other experiments, the inventors of the present application have no significant difference in the state of surface wave plasma depending on the apparatus configuration and process conditions, and the gap is set to 150 mm or more, more preferably 200 mm or more. Thus, it was found that damage to the substrate 1 by hydrogen radicals can be reduced. Thus, an oxide semiconductor thin film transistor with excellent characteristics can be manufactured.
　上記したように、非晶質ＩＧＺＯを形成した基板１の上に、ＳｉＨ４、Ｎ２Ｏガスを原料とする表面波プラズマＣＶＤ法でＳｉＯ２膜を形成する。この際に、誘電体窓１３から基板１までの距離が１５０ｍｍ以上となるＧａｐ位置で、成膜することが望ましい。こうすることで、水素ラジカルによって、ＩＧＺＯ膜が還元されるのを防ぐことができる。よって、高性能の酸化物半導体薄膜トランジスタを得ることができる。こうして得られた酸化物半導体薄膜トランジスタはアモルファスシリコン半導体に比べて易動度が高く、また製造工程が多結晶シリコン半導体に比べて複雑でないため、液晶や有機ＥＬ等の表示装置に好適である。尚、本発明は上記実施の形態に限られるものではなく、趣旨を逸脱しない範囲で適宜変更することが可能なものである。 As described above, an SiO 2 film is formed on the substrate 1 on which amorphous IGZO is formed by surface wave plasma CVD using SiH 4 and N 2 O gas as raw materials. At this time, it is desirable to form a film at a gap position where the distance from the dielectric window 13 to the substrate 1 is 150 mm or more. By doing so, it is possible to prevent the IGZO film from being reduced by hydrogen radicals. Therefore, a high-performance oxide semiconductor thin film transistor can be obtained. The oxide semiconductor thin film transistor thus obtained has higher mobility than an amorphous silicon semiconductor, and the manufacturing process is less complicated than a polycrystalline silicon semiconductor. Therefore, the oxide semiconductor thin film transistor is suitable for a display device such as a liquid crystal or an organic EL. Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.
　本発明は、高性能の酸化物半導体薄膜トランジスタを得ることができる薄膜トランジスタの製造方法、及びそれを用いた表示装置の製造方法に利用可能である。 The present invention is applicable to a method for manufacturing a thin film transistor capable of obtaining a high-performance oxide semiconductor thin film transistor, and a method for manufacturing a display device using the same.
　１　基板
　２　絶縁膜
　３　ソース・ドレイン電極
　４　半導体層
　５　ゲート絶縁膜
　６　ゲート電極
　１１　チャンバー
　１１ａ　排気口
　１２　導波管
　１３　誘電体窓
　１４　ガス導入口
　１５　ガス導入口
　１６　スロットアンテナ
　１７　ステージ DESCRIPTION OF SYMBOLS 1 Substrate 2 Insulating film 3 Source / drain electrode 4 Semiconductor layer 5 Gate insulating film 6 Gate electrode 11 Chamber 11a Exhaust port 12 Waveguide 13 Dielectric window 14 Gas inlet 15 Gas inlet 16 Slot antenna 17 Stage

Claims (6)

  1. 　基板上に、酸化物半導体膜を形成するステップと、
    　前記酸化物半導体膜の上に、表面波プラズマＣＶＤ法を用いて、ゲート絶縁膜を形成するステップと、を備えた薄膜トランジスタの製造方法。     Forming an oxide semiconductor film over the substrate;
    Forming a gate insulating film on the oxide semiconductor film by using a surface wave plasma CVD method.
  2. 　前記表面波プラズマＣＶＤ法では、基板と誘電体との距離を１５０ｍｍ以上とした状態で、ゲート絶縁膜を成膜していることを特徴とする請求項１に記載の薄膜トランジスタの製造方法。 2. The method of manufacturing a thin film transistor according to claim 1, wherein in the surface wave plasma CVD method, the gate insulating film is formed in a state where the distance between the substrate and the dielectric is 150 mm or more.
  3. 　前記表面波プラズマＣＶＤ法では、スロットアンテナを通して誘電体窓にマイクロ波が伝播し、前記誘電体窓の表面で定在波が形成する表面波となることを特徴とする請求項１、又は２に記載の薄膜トランジスタの製造方法。 3. The surface wave plasma CVD method according to claim 1, wherein a microwave propagates to a dielectric window through a slot antenna to form a surface wave that forms a standing wave on the surface of the dielectric window. The manufacturing method of the thin-film transistor of description.
  4. 　前記ゲート絶縁膜が、酸化ケイ素膜であることを特徴とする請求項１～３のいずれか１項に記載の薄膜トランジスタの製造方法。 The method of manufacturing a thin film transistor according to any one of claims 1 to 3, wherein the gate insulating film is a silicon oxide film.
  5. 　前記酸化物半導体膜が、ＩＧＺＯ膜であることを特徴とする請求項１～４のいずれか１項に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to any one of claims 1 to 4, wherein the oxide semiconductor film is an IGZO film.
  6. 　請求項１～５のいずれか１項に記載の薄膜トランジスタの製造方法を用いて、前記薄膜トランジスタをアレイ状に形成するステップを有する表示装置の製造方法。 A method for manufacturing a display device comprising a step of forming the thin film transistors in an array using the method for manufacturing thin film transistors according to any one of claims 1 to 5.
PCT/JP2013/052487 2012-03-08 2013-02-04 Method for manufacturing thin film transistor and method for manufacturing display device WO2013132937A1 (en)

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