WO2013129216A1 - Display device and method for driving same - Google Patents

Display device and method for driving same Download PDF

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Publication number
WO2013129216A1
WO2013129216A1 PCT/JP2013/054279 JP2013054279W WO2013129216A1 WO 2013129216 A1 WO2013129216 A1 WO 2013129216A1 JP 2013054279 W JP2013054279 W JP 2013054279W WO 2013129216 A1 WO2013129216 A1 WO 2013129216A1
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Prior art keywords
pixel
display device
light emitting
data
circuit
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PCT/JP2013/054279
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French (fr)
Japanese (ja)
Inventor
宣孝 岸
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シャープ株式会社
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Publication of WO2013129216A1 publication Critical patent/WO2013129216A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to a display device, and more particularly, to an active matrix display device such as an organic EL display and a driving method thereof.
  • An organic EL (Electro Luminescence) display is known as a thin, high image quality, low power consumption display device.
  • the organic EL display includes a plurality of pixel circuits including an organic EL element, a driving transistor, and a control transistor.
  • a transistor in the pixel circuit a thin film transistor (hereinafter referred to as TFT) is used.
  • the characteristics (threshold voltage and mobility) of the driving transistor in the pixel circuit vary. For this reason, even if the same data potential is written in the pixel circuit, the amount of current flowing through the organic EL element varies. Since the luminance of the organic EL element changes in accordance with the amount of current flowing through the organic EL element, if the amount of current flowing through the organic EL element varies, uneven luminance occurs on the display screen. Therefore, in order to perform high-quality display on the organic EL display, it is necessary to compensate for the characteristics of the driving transistor.
  • FIG. 18 is a circuit diagram of a pixel circuit of an organic EL display described in Patent Document 1.
  • a pixel circuit 70 shown in FIG. 18 includes six TFTs 71 to 76, a capacitor 77, and an organic EL element 78.
  • the pixel circuit 70 has a function of compensating the threshold voltage of the TFT 71 (driving transistor).
  • one color pixel is composed of three sub-pixels.
  • 18 TFTs and three capacitors are required for one color pixel.
  • the number of elements in the pixel circuit is increased, the yield of the display panel is lowered, and there is a problem that a high-definition display panel cannot be realized.
  • FIG. 19 is a diagram showing a configuration of an organic EL display described in Patent Document 3. As shown in FIG. In the organic EL display shown in FIG. 19, one pixel circuit 80 is provided corresponding to two organic EL elements 81a and 81b adjacent in the vertical direction. The TFTs 82a and 82b are selectively turned on, and the organic EL elements 81a and 81b selectively emit light.
  • FIG. 20 is a circuit diagram of a pixel circuit of an organic EL display described in Patent Document 4. A pixel circuit 90 shown in FIG.
  • the 20 includes one TFT 91 (driving transistor) and one compensation circuit 92 corresponding to the three organic EL elements 94r, 94g, and 94b.
  • the TFTs 93r, 93g, 93b are selectively turned on, and the three organic EL elements 94r, 94g, 94b selectively emit light.
  • Japanese Unexamined Patent Publication No. 2005-31630 Japanese Unexamined Patent Publication No. 2003-202833 Japanese Unexamined Patent Publication No. 2003-122306 Japanese Unexamined Patent Publication No. 2005-165266 Japanese Unexamined Patent Publication No. 2007-128019 Japanese Unexamined Patent Publication No. 2008-268437 Japanese Unexamined Patent Publication No. 2010-122461
  • the conventional organic EL display in which elements are shared among a plurality of sub-pixels has a problem that the scanning speed is increased.
  • the organic EL display described in Patent Document 4 one frame period is divided into three subframe periods, and writing to the organic EL element 94r, writing to the organic EL element 94g, and organic One of writing to the EL element 94b is performed. For this reason, the scanning speed is three times that when elements are not shared.
  • the organic EL display described in Patent Document 3 since the elements are shared between two vertically adjacent sub-pixels, there is a problem that the shared portion becomes vertically long and the layout becomes difficult.
  • an object of the present invention is to provide a display device in which the number of elements in a pixel circuit is reduced by sharing elements among a plurality of sub-pixels while suppressing an increase in scanning speed.
  • a first aspect of the present invention is an active matrix display device, A plurality of pixel circuits arranged in a row direction and a column direction; A plurality of scanning lines and a plurality of control lines extending in the row direction; A plurality of data lines extending in the column direction; A scanning line driving circuit for driving the scanning line and the control line; A data line driving circuit for driving the data line,
  • Each of the pixel circuits is A plurality of light emitting elements;
  • a light-emitting element drive unit that includes one drive transistor, and causes a current that has passed through the drive transistor to flow to any one of the plurality of light-emitting elements based on the potential of the control line,
  • the scanning line driving circuit and the data line driving circuit write data potentials to the plurality of pixel circuits in each of the subframe periods obtained by dividing one frame period, and the driving transistor is set in each subframe period. Switch the path of the current that passed, The scan line driver circuit and the data line driver circuit write the data potentials in parallel to the pixel circuit
  • the scanning lines are provided one by one corresponding to a first number of rows of two or more of the pixel circuits
  • the data lines are provided by the first number corresponding to the columns of the pixel circuit
  • the scanning line driving circuit sequentially selects the pixel circuits in the first number of rows by sequentially selecting the scanning lines one by one
  • the data line driving circuit applies a data potential to be written to the pixel circuit selected by the scanning line driving circuit to the data line.
  • Each of the pixel circuits includes a second number of light emitting elements of 2 or more,
  • the scanning line driving circuit and the data line driving circuit divide one frame period into the second number of subframe periods.
  • the plurality of light emitting elements included in the pixel circuit are arranged in a row direction in a display screen, and correspond to a plurality of subpixels constituting one color pixel.
  • Each of the pixel circuits includes one light emitting element that emits red light, one light emitting element that emits green light, and one light emitting element that emits blue light.
  • the plurality of light emitting elements included in the pixel circuit correspond to a plurality of subpixels arranged in a row direction in a display screen and constituting a plurality of adjacent color pixels.
  • a seventh aspect of the present invention is the sixth aspect of the present invention.
  • Each of the pixel circuits includes a plurality of light emitting elements that emit red light, light emitting elements that emit green light, and light emitting elements that emit blue light.
  • the plurality of light emitting elements included in the pixel circuit correspond to sub-pixels of the same color included in the plurality of color pixels arranged in the column direction in the display screen.
  • a ninth aspect of the present invention is the eighth aspect of the present invention,
  • the pixel circuit is any one of a pixel circuit including a light emitting element that emits red light, a pixel circuit including a light emitting element that emits green light, and a pixel circuit including a light emitting element that emits blue light.
  • the first number is equal to the second number.
  • An eleventh aspect of the present invention is the third aspect of the present invention, The first number is smaller than the second number.
  • a twelfth aspect of the present invention is the third aspect of the present invention, The first number is larger than the second number.
  • a thirteenth aspect of the present invention is the third aspect of the present invention.
  • the light emitting element driving unit includes a switch element having a control terminal connected to the control line different from each other between the driving transistor and the light emitting element.
  • a fourteenth aspect of the present invention a plurality of scanning lines and a plurality of control lines extending in the row direction, a plurality of data lines extending in the column direction, each passing through a plurality of light emitting elements and a driving transistor.
  • a driving method of an active matrix display device including a plurality of pixel circuits arranged in a row direction and a column direction, and a light emitting element driving unit that causes a current to flow to any of the plurality of light emitting elements, Writing data potentials to the plurality of pixel circuits in each of the sub-frame periods obtained by dividing one frame period by driving the scanning lines and the data lines; Switching the path of the current that has passed through the driving transistor every subframe period by driving the control line, and The step of writing the data potential is characterized in that the data potential is written in parallel to a plurality of rows of pixel circuits.
  • a plurality of light emitting element driving units that allow a current that has passed through the driving transistor to flow to any one of the plurality of light emitting elements are provided corresponding to the plurality of light emitting elements.
  • the elements can be shared among the sub-pixels, and the number of elements in the pixel circuit can be reduced.
  • an increase in scanning speed can be suppressed by writing data potentials in parallel to pixel circuits in a plurality of rows. Therefore, it is possible to reduce the number of elements in the pixel circuit by sharing elements among the plurality of sub-pixels while suppressing an increase in scanning speed.
  • the scanning speed can be reduced to 1 / p compared to the case where writing is performed row by row to the pixel circuit.
  • the elements are shared among the q sub pixels, and the pixels are compared with the case where the elements are not shared.
  • the number of elements in the circuit can be reduced to about 1 / q.
  • the scanning speed is increased q times. Therefore, by writing data potentials in parallel to the pixel circuit in the p row, the scanning speed is (q / p) times as compared with the case where writing is performed row by row in the pixel circuit without sharing the elements. Can be suppressed.
  • elements can be shared among a plurality of sub-pixels constituting one color pixel, and the number of elements in the pixel circuit can be reduced.
  • elements can be shared among a plurality of sub-pixels constituting a plurality of color pixels, and the number of elements in the pixel circuit can be reduced.
  • elements can be shared among a plurality of sub-pixels corresponding to the same color, and the number of elements in the pixel circuit can be reduced.
  • the elements are shared among the q sub-pixels without changing the scanning speed.
  • the number of elements can be reduced.
  • the eleventh aspect of the present invention when the first number p is smaller than the second number q, the increase in the scanning speed is suppressed to (q / p) times, and between the q sub-pixels.
  • the number of elements in the pixel circuit can be reduced by sharing the elements.
  • the scanning speed is reduced by a factor of (q / p), and the element between q sub-pixels is reduced. And the number of elements in the pixel circuit can be reduced.
  • a switch element is provided between the drive transistor and each light-emitting element, and the control terminal of the switch element is connected to different control lines, whereby the current passed through the drive transistor is It is possible to easily configure a light emitting element driving unit that flows to any one of the plurality of light emitting elements.
  • FIG. 2 is a diagram showing an arrangement of sub-pixels in a display screen in the display device shown in FIG. 1. It is a figure which shows the connection form of the pixel circuit contained in the display apparatus shown in FIG.
  • FIG. 2 is a circuit diagram of a pixel circuit included in the display device shown in FIG. 1.
  • FIG. 2 is a diagram illustrating an operation of a pixel circuit in each row included in the display device illustrated in FIG. 1.
  • 2 is a timing chart of a pixel circuit included in the display device shown in FIG.
  • FIG. 13 is a circuit diagram of a pixel circuit included in the display device shown in FIG. 12.
  • FIG. 15 is a circuit diagram of a pixel circuit included in the display device shown in FIG. 14. 15 is a timing chart of a pixel circuit included in the display device shown in FIG. It is a circuit diagram of the pixel circuit of the conventional organic EL display. It is a block diagram which shows the structure of the conventional organic EL display. It is a circuit diagram of the pixel circuit of the conventional organic EL display.
  • FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention.
  • a display device 100 illustrated in FIG. 1 is an active matrix organic EL display including a display control circuit 1, a scanning line driving circuit 2, a data line driving circuit 3, and (m ⁇ n) pixel circuits 10. .
  • m is an integer of 2 or more
  • n is a multiple of 3
  • i is any number of 1, 4,..., N-5, n-2
  • j is an integer of 1 to m.
  • the display device 100 is provided with (n / 3) scanning lines Gi, (5n / 3) control lines GINIi, EMi, EMRi, EMGi, EMBi, and 3m data lines S1j, S2j, S3j. It is done.
  • (N / 3) scanning lines and (5n / 3) control lines are arranged in parallel to each other.
  • the 3m data lines are arranged in parallel to each other so as to be orthogonal to the scanning lines and the control lines.
  • the extending direction (horizontal direction in the figure) of the scanning line and the control line is referred to as the row direction
  • the extending direction of the data line vertical direction in the figure
  • the pixel circuit 10 is provided corresponding to the intersection of the scanning line and the data line.
  • the pixel circuits 10 are arranged two-dimensionally in the row direction and the column direction. Note that in the block diagram illustrating the structure of the display device, three pixel circuits adjacent in the column direction are represented by one rectangle.
  • the display control circuit 1 outputs control signals to the scanning line driving circuit 2 and the data line driving circuit 3. More specifically, the display control circuit 1 outputs a timing signal OE, a start pulse YI, and a clock YCK to the scanning line driving circuit 2, and a start pulse SP, a clock CLK, a data signal to the data line driving circuit 3. DA and latch pulse LP are output.
  • the scanning line driving circuit 2 drives the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi. More specifically, the scanning line driving circuit 2 includes a shift register circuit, a logical operation circuit, and a buffer (all not shown).
  • the shift register circuit sequentially transfers the start pulse YI in synchronization with the clock YCK.
  • the logical operation circuit performs a logical operation between the pulse output from each stage of the shift register circuit and the timing signal OE. The output of the logical operation circuit is given to the corresponding scanning line and control line via the buffer.
  • the data line driving circuit 3 drives the data lines S1j, S2j, S3j. More specifically, the data line driving circuit 3 includes an m-bit shift register 4, a register 5, a latch circuit 6, and 3m D / A converters 7.
  • the shift register 4 has a configuration in which m registers are connected in multiple stages, transfers the start pulse SP supplied to the first stage register in synchronization with the clock CLK, and outputs a timing pulse DLP from each stage register.
  • the data signal DA for three subpixels is supplied to the register 5 in accordance with the output timing of the timing pulse DLP.
  • the register 5 stores the data signal DA according to the timing pulse DLP.
  • the display control circuit 1 When the data signals DA for three rows are stored in the register 5, the display control circuit 1 outputs a latch pulse LP to the latch circuit 6. When receiving the latch pulse LP, the latch circuit 6 holds the data signal DA stored in the register 5.
  • the 3m D / A converters 7 are provided corresponding to the 3m data lines. The D / A converter 7 applies a data potential corresponding to the data signal DA held in the latch circuit 6 to the corresponding data line.
  • FIG. 2 is a diagram showing the arrangement of sub-pixels in the display screen of the display device 100. As shown in FIG. FIG. 2 shows a configuration of three color pixels adjacent in the column direction in the display screen. The display device 100 performs color display using RGB three colors. For this reason, one color pixel (portion surrounded by a thick line) is composed of three sub-pixels (R sub-pixel displaying red, G sub-pixel displaying green, and B sub-pixels that display blue).
  • FIG. 3 is a diagram showing a connection form of the pixel circuit 10.
  • FIG. 3 shows a connection form of three pixel circuits 10 adjacent in the column direction.
  • the pixel circuit 10 corresponds to the color pixel shown in FIG.
  • the three pixel circuits 10 are provided in the vicinity of the intersection of the scanning line Gi and the three data lines S1j, S2j, and S3j. All of the three pixel circuits 10 are connected to the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi.
  • the three pixel circuits 10 are connected to data lines S1j, S2j, and S3j, respectively.
  • the pixel circuit 10 connected to the data line S1j corresponds to the color pixel in the i-th row and the j-th column.
  • the pixel circuit 10 connected to the data line S2j corresponds to the color pixel of the (i + 1) th row and the jth column.
  • the pixel circuit 10 connected to the data line S3j corresponds to the color pixel in the (i + 2) th row and the jth column.
  • the pixel circuit 10 corresponding to the color pixel in the i-th row and the j-th column is referred to as a pixel circuit Aij.
  • Each of the three pixel circuits 10 includes three organic EL elements and a light emitting element driving unit.
  • the light emitting element driving unit has one driving transistor, and the current that has passed through the driving transistor flows to one of the three organic EL elements based on the potentials of the control lines EMRi, EMGi, and EMBi.
  • FIG. 4 is a circuit diagram of the pixel circuit 10.
  • the pixel circuit 10 includes eight TFTs 11 to 15, 16r, 16g, and 16b, a capacitor 17, and three organic EL elements 18r, 18g, and 18b.
  • the organic EL elements 18r, 18g, and 18b are light emitting elements that emit red, green, and blue light, respectively.
  • Each of the eight TFTs is a P-type transistor, and the TFT 11 functions as a driving transistor.
  • the TFTs 11 to 15, 16r, 16g, and 16b and the capacitor 17 function as a light emitting element driving unit.
  • the pixel circuit 10 includes a wiring having an initialization potential Vini, a wiring having a power supply potential ELVDD, and a power supply potential ELVSS. Is connected to an electrode having The pixel circuit 10 is a modification of the pixel circuit described in FIG.
  • the power supply potential ELVDD is applied to the source of the TFT 13 and one electrode of the capacitor 17, and the source of the TFT 15 is connected to the data line S1j.
  • the drains of the TFTs 13 and 15 are connected to the source of the TFT 11.
  • the drain of the TFT 11 is connected to the sources of the TFTs 12, 16r, 16g, and 16b.
  • An initialization potential Vini is applied to the drain of the TFT 14.
  • the drain of the TFT 12, the source of the TFT 14, and the other electrode of the capacitor 17 are connected to the gate of the TFT 11.
  • the drains of the TFTs 16r, 16g, and 16b are connected to the anodes of the organic EL elements 18r, 18g, and 18b, respectively.
  • a power supply potential ELVSS is applied to the cathodes of the organic EL elements 18r, 18g, and 18b.
  • the gates of the TFTs 12 and 15 are connected to the scanning line Gi, the gate of the TFT 13 is connected to the control line EMi, and the gate of the TFT 14 is connected to the control line GINIi.
  • the gates of the TFTs 16r, 16g, and 16b are connected to control lines EMRi, EMGi, and EMBi, respectively.
  • the TFTs 16r, 16g, and 16b switch elements
  • the TFT 11 drive transistor
  • the organic EL elements 18r, 18g, and 18b the gates of the TFTs 16r, 16g, and 16b are connected to different control lines EMRi, EMGi, and EMBi.
  • the pixel circuit 10 shown in FIG. 4 is a pixel circuit Aij corresponding to the color pixel in the i-th row and the j-th column.
  • the pixel circuit Ai + 1j corresponding to the color pixel in the (i + 1) th row and the jth column and the pixel circuit Ai + 2j corresponding to the color pixel in the (i + 2) th row and the jth column also have the configuration shown in FIG.
  • the source of the TFT 15 is connected to the data line S2j
  • the source of the TFT 15 is connected to the data line S3j.
  • FIG. 5 is a diagram illustrating the operation of the pixel circuits 10 in each row.
  • one frame period is divided into three subframe periods (R subframe period, G subframe period, and B subframe period).
  • the scanning line driving circuit 2 and the data line driving circuit 3 write data potentials to (m ⁇ n) pixel circuits 10 in each of the subframe periods obtained by dividing one frame period, and each subframe period
  • the path of the current passing through the TFT 11 driving transistor
  • the scanning line driving circuit 2 and the data line driving circuit 3 perform initialization, threshold value detection, and data potential writing on the pixel circuits 10 in three rows in parallel.
  • (M ⁇ n) pixel circuits 10 are divided into (n / 3) groups by three rows.
  • the pixel circuits in the first to third rows are in the first group
  • the pixel circuits in the fourth to sixth rows are in the second group
  • the pixel circuits in the (n ⁇ 2) -th to n-th rows are in the first group.
  • Classified into (n / 3) groups For the first group of pixel circuits, an R subframe period, a G subframe period, and a B subframe period are sequentially set from the beginning of one frame period. At the beginning of each subframe period, initialization, threshold compensation, and data potential writing are performed on the first group of pixel circuits.
  • the organic EL elements 18r in the first group of pixel circuits emit light in the remainder of the R subframe period.
  • the organic EL elements 18g in the first group of pixel circuits emit light in the remainder of the G subframe period.
  • the organic EL elements 18b in the first group of pixel circuits emit light in the remaining part of the B subframe period.
  • the R subframe period and the G subframe period And B subframe periods are set in order.
  • initialization, threshold compensation, and data potential writing are performed on the pixel circuits of the kth group.
  • the organic EL elements 18r in the k-th group of pixel circuits emit light in the remainder of the R subframe period.
  • the organic EL elements 18g in the k-th group of pixel circuits emit light in the remainder of the G subframe period.
  • the organic EL elements 18b in the k-th group of pixel circuits emit light in the remainder of the B subframe period.
  • one scanning line Gi is provided corresponding to each of the three rows of pixel circuits 10, and the data lines S1j, S2j, and S3j are pixel circuits. Three are provided corresponding to each of the ten columns.
  • the scanning line driving circuit 2 sequentially selects the pixel circuits 10 in three rows by sequentially selecting the scanning lines Gi one by one.
  • the data line driving circuit 3 applies data potentials to be written to the three rows of pixel circuits 10 selected by the scanning line driving circuit 2 to the data lines S1j, S2j, and S3j.
  • the pixel circuit 10 includes three organic EL elements, and the scanning line driving circuit 2 and the data line driving circuit 3 divide one frame period into three subframe periods.
  • FIG. 6 is a timing chart of the pixel circuit 10.
  • FIG. 6 shows changes in potentials of nine signal lines connected to three pixel circuits Aij, Ai + 1j, and Ai + 2j adjacent in the column direction.
  • a period in which the potential of the scanning line Gi is at a low level is referred to as a selection period of the scanning line Gi
  • a period in which the potentials of the control lines EMRi, EMGi, and EMBi are at a low level are R emission period, G emission period, and This is called the B light emission period.
  • the operation of the pixel circuit Aij will be described with reference to FIG.
  • the potentials of the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi are at a high level. For this reason, the TFTs 12 to 15, 16r, 16g, and 16b are all turned off.
  • the potential of the control line GINIi changes to a low level. For this reason, the TFT 14 is turned on. As a result, the gate potential of the TFT 11 is initialized to Vini.
  • the potential of the control line GINIi changes to a high level, and the potential of the scanning line Gi changes to a low level. For this reason, the TFT 14 is turned off, and the TFTs 12 and 15 are turned on.
  • the data potential VRij is applied to the data line S1j. For this reason, the source potential of the TFT 11 becomes VRij, and the TFT 11 is turned on.
  • the threshold voltage of the TFT 11 is Vth
  • the gate potential of the TFT 11 rises to (VRij ⁇ Vth).
  • the potential of the scanning line Gi changes to a high level. For this reason, the TFTs 12 and 15 are turned off. At this time, the potential difference (ELVDD ⁇ VRij + Vth) is held in the capacitor 17.
  • the current Ir shown in the equation (2) changes according to the data potential VRij, but does not depend on the threshold voltage Vth of the TFT 11. Therefore, even when the threshold voltage Vth varies or when the threshold voltage Vth changes over time, a current that does not depend on the threshold voltage Vth is caused to flow through the organic EL element 18r, and the organic EL element 18r emits light with a desired luminance. Can be made.
  • the pixel circuit Aij operates in the same manner as in the R subframe period.
  • the data potential VGij is applied to the data line S1j during the selection period of the scanning line Gi within the G subframe period, and the organic EL element 18g emits light with luminance corresponding to the data potential VGij during the G light emission period.
  • the data potential VBij is applied to the data line S1j during the selection period of the scanning line Gi within the B subframe period, and the organic EL element 18b emits light with luminance corresponding to the data potential VBij during the B light emission period.
  • the pixel circuits Ai + 1j and Ai + 2j operate in the same manner as the pixel circuit Aij in parallel with the pixel circuit Aij.
  • the data potentials VRi + 1j and VRi + 2j are applied to the data lines S2j and S3j, respectively.
  • the organic EL element 18r in the pixel circuit Ai + 1j emits light with a luminance corresponding to the data potential VRi + 1j
  • the organic EL element 18r in the pixel circuit Ai + 2j emits light with a luminance corresponding to the data potential VRi + 2j.
  • the data potentials VGi + 1j and VGi + 2j are applied to the data lines S2j and S3j, respectively.
  • the organic EL element 18g in the pixel circuit Ai + 1j emits light with a luminance corresponding to the data potential VGi + 1j
  • the organic EL element 18g in the pixel circuit Ai + 2j emits light with a luminance corresponding to the data potential VGi + 2j.
  • the data potentials VBi + 1j and VBi + 2j are applied to the data lines S2j and S3j, respectively.
  • the organic EL element 18b in the pixel circuit Ai + 1j emits light with a luminance corresponding to the data potential VBi + 1j
  • the organic EL element 18b in the pixel circuit Ai + 2j emits light with a luminance corresponding to the data potential VBi + 2j.
  • the display device 100 according to the present embodiment is compared with the display device described in Patent Document 1 (hereinafter referred to as a conventional display device).
  • a conventional display device performs color display using three colors of RGB, and the conventional display device handles the scan signals scan [n] and scan [n ⁇ 1] as two signals. It was decided.
  • the display device 100 by providing one light-emitting element driving unit corresponding to three organic EL elements, the elements are shared among the plurality of sub-pixels, and the number of elements in the pixel circuit is reduced. Can be reduced.
  • the display device 100 requires six scanning lines and three control lines and three data lines for three color pixels.
  • the number of scanning lines can be reduced as compared with the conventional display device.
  • the display device 100 writes the data potential to each pixel circuit 10 three times in one frame period. For this reason, in the display device 100, the number of data potentials written per frame period is three times that of a conventional display device. However, the display device 100 writes data potentials in parallel to the pixel circuits 10 in three rows. Therefore, the scanning speed of the display device 100 is the same as that of the conventional display device. However, in the display device 100, the length of the light emission period is 1/3 that of the conventional display device.
  • the display device 100 includes (m ⁇ n) pixel circuits 10, (n / 3) scanning lines, (5n / 3) control lines, 3m lines.
  • a data line, a scanning line driving circuit 2 and a data line driving circuit 3 are provided.
  • the pixel circuit 10 includes three light emitting elements (organic EL elements) and a light emitting element driving unit that causes a current that has passed through the driving transistor (TFT 11) to flow to one of the three light emitting elements based on the potential of the control line. .
  • the scanning line driving circuit 2 and the data line driving circuit 3 write data potentials to the (m ⁇ n) pixel circuits 10 in each subframe period obtained by dividing one frame period into three, and each subframe period.
  • the path of the current that has passed through the driving transistor is switched.
  • the scanning line driving circuit 2 and the data line driving circuit 3 write data potentials in parallel to the pixel circuits in three rows.
  • One scanning line is provided corresponding to each pixel circuit 10 in three rows, and three data lines are provided corresponding to each column of the pixel circuits 10.
  • the scanning line driving circuit 2 sequentially selects the pixel circuits 10 in three rows by sequentially selecting the scanning lines one by one.
  • the data line driving circuit 3 applies a data potential to be written to the three rows of pixel circuits 10 selected by the scanning line driving circuit 2 to the data lines.
  • the elements can be shared among the plurality of subpixels, and the number of elements in the pixel circuit can be reduced.
  • writing data potentials in parallel to a plurality of pixel circuits can suppress an increase in scanning speed. Therefore, it is possible to provide a display device in which the number of elements in the pixel circuit is reduced by sharing elements among a plurality of sub-pixels while suppressing an increase in scanning speed.
  • the scanning speed can be reduced to 1 / p (here, 1/3) as compared with the case where writing is performed row by row to the pixel circuit.
  • the elements are shared among the q subpixels, and compared with the case where the elements are not shared, in the pixel circuit.
  • the number of elements can be reduced to about (1 / q).
  • the number of TFTs required for one color pixel can be reduced to 4/9 compared with the conventional display device.
  • the scanning speed is increased q times.
  • the scanning speed is (q / p) times as compared with the case where writing is performed row by row in the pixel circuit without sharing the elements. Can be suppressed. Since p and q are equal in the display device 100, the number of elements in the pixel circuit can be reduced by sharing elements among the three sub-pixels without changing the scanning speed.
  • the pixel circuit 10 includes one light emitting element that emits red light, one light emitting element that emits green light, and one light emitting element that emits blue light. These three light emitting elements are aligned in the row direction in the display screen, and correspond to three sub-pixels constituting one color pixel. In this manner, elements can be shared among a plurality of sub-pixels constituting one color pixel, and the number of elements in the pixel circuit can be reduced.
  • the display device according to the first modification includes (m ⁇ n / 2) pixel circuits including six organic EL elements.
  • the display device according to the first modification includes (n / 3) scanning lines Gi, (8n / 3) control lines GINIi, EMi, EMR1i, EMG1i, EMB1i, EMR2i, EMG2i, EMB2i, and 3m. Two data lines S1j, S2j, S3j are provided.
  • FIG. 7 is a diagram illustrating a connection form of pixel circuits in the display device according to the first modification.
  • FIG. 7 shows a connection form of three pixel circuits 20 adjacent in the column direction.
  • the pixel circuit 20 corresponds to two color pixels adjacent in the row direction. All of the three pixel circuits 20 are connected to the scanning line Gi and the control lines GINIi, EMi, EMR1i, EMG1i, EMB1i, EMR2i, EMG2i, and EMB2i.
  • the three pixel circuits 20 are connected to data lines S1j, S2j, and S3j, respectively.
  • the pixel circuit 10 connected to the data line S1j corresponds to the color pixel in the i-th row and j-th column and the color pixel in the i-th row (j + 1) -th column.
  • the pixel circuit 10 connected to the data line S2j corresponds to the color pixel in the (i + 1) th row and the jth column and the color pixel in the (i + 1) th row and the (j + 1) th column.
  • the pixel circuit 10 connected to the data line S3j corresponds to the color pixel of the (i + 2) th row and the jth column and the color pixel of the (i + 2) th row and the (j + 1) th column.
  • FIG. 8 is a circuit diagram of the pixel circuit 20.
  • the pixel circuit 20 is obtained by adding TFTs 21r, 21g, and 21b and organic EL elements 22r, 22g, and 22b to the pixel circuit 10 (FIG. 4).
  • the TFTs 21r, 21g, and 21b and the organic EL elements 22r, 22g, and 22b are connected in the same form as the TFT 16r and the organic EL element 18r.
  • the gates of the TFTs 16r, 16g, 16b, 21r, 21g, and 21b are connected to control lines EMR1i, EMG1i, EMB1i, EMR2i, EMG2i, and EMB2i, respectively.
  • one frame period is divided into six subframe periods.
  • the scanning line driving circuit and the data line driving circuit perform initialization, threshold value detection, and writing for the pixel circuits in three rows in parallel.
  • the number of data lines can be reduced to 1 ⁇ 2 compared to the case where the elements are not shared.
  • the length of the light emission period is 1/6 of one frame period, and the scanning speed is doubled compared to the case where the elements are not shared.
  • the increase in scanning speed is suppressed to (q / p) times (here, 2 times), while the elements are shared among the q sub-pixels, and within the pixel circuit.
  • the number of elements can be reduced.
  • the pixel circuit 20 includes two light emitting elements that emit red light, two light emitting elements that emit green light, and two light emitting elements that emit blue light. These six light emitting elements are aligned in the row direction in the display screen and correspond to six sub-pixels constituting two color pixels. In this manner, elements can be shared among a plurality of sub-pixels constituting a plurality of color pixels, and the number of elements in the pixel circuit can be reduced.
  • the display device performs initialization, threshold value detection, and writing for the pixel circuits in six rows in parallel.
  • the display device according to the second modification includes (n / 6) scanning lines Gi (in this modification, i is one of 1, 7,..., N-11, n-5). Number), (5n / 6) control lines GINIi, EMi, EMRi, EMGi, EMBi, and 6m data lines S1j, S2j, S3j, S4j, S5j, S6j.
  • FIG. 9 is a diagram illustrating a connection form of pixel circuits in the display device according to the second modification.
  • FIG. 9 shows a connection form of six pixel circuits 10 adjacent in the column direction.
  • Each of the six pixel circuits 10 is connected to the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi.
  • the six pixel circuits 10 are connected to the data lines S1j to S6j, respectively.
  • the pixel circuit 10 connected to the data line S1j corresponds to the color pixel in the i-th row and the j-th column.
  • the pixel circuit 10 connected to the data line S2j corresponds to the color pixel of the (i + 1) th row and the jth column.
  • the pixel circuit 10 connected to the data line S3j corresponds to the color pixel in the (i + 2) th row and the jth column.
  • the pixel circuit 10 connected to the data line S4j corresponds to the color pixel in the (i + 3) th row and the jth column.
  • the pixel circuit 10 connected to the data line S5j corresponds to the color pixel in the (i + 4) th row and the jth column.
  • the pixel circuit 10 connected to the data line S6j corresponds to the color pixel in the (i + 5) th row and the jth column.
  • one frame period is divided into three subframe periods.
  • the scanning line driving circuit and the data line driving circuit perform initialization, threshold value detection, and writing for the pixel circuits in six rows in parallel.
  • the number of data lines is doubled compared to the case where the elements are not shared.
  • the scanning speed is 1 ⁇ 2 compared to the case where the elements are not shared.
  • the length of the light emission period can be extended without changing the scanning speed as compared with the case where the elements are not shared.
  • the value of p (here, 6) is changed to the value of q.
  • the pixel size is larger than (here, 3)
  • the pixel is shared between the q sub-pixels while reducing the increase in scanning speed by (q / p) times (here, 1/2 times).
  • the number of elements in the circuit can be reduced.
  • the display device causes a plurality of light emitting elements to emit light in each subframe period.
  • the organic EL elements 18r in the pixel circuits 10 in the first to third rows and the fourth to fourth subframe periods are used.
  • the organic EL elements 18g in the pixel circuits 10 in the six rows and the organic EL elements 18b in the pixel circuits in the seventh to ninth rows emit light.
  • the organic EL elements 18r in the 9-row pixel circuits emit light.
  • the organic EL elements 18b in the pixel circuits 10 in the first to third rows the organic EL elements 18r in the pixel circuits 10 in the fourth to sixth rows, and the seventh to sixth rows.
  • the organic EL elements 18g in the 9-row pixel circuits emit light. According to the display device according to the third modification, it is possible to prevent the emission color from being biased to a specific color in each subframe period, and to reduce flickering of the display screen and color breakup during moving image display.
  • the display device according to the second embodiment of the present invention has the same configuration (FIG. 1) as that of the first embodiment, and includes the same pixel circuit 10 (FIG. 4).
  • the arrangement of the sub-pixels in the display screen in the display device according to the present embodiment is the same as that in the first embodiment (FIG. 2).
  • This embodiment is different from the first embodiment in which sub-pixel the organic EL element in the pixel circuit corresponds to.
  • differences from the first embodiment will be described.
  • FIG. 10 is a diagram showing a connection form of the pixel circuit 10 in the display device according to the second embodiment.
  • the connection form of the three pixel circuits 10 shown in FIG. 10 is the same as that of the first embodiment (FIG. 3).
  • the three organic EL elements included in the pixel circuit 10 emit light in the same color, and the same color sub-pixels included in the three color pixels arranged in the column direction in the display screen. Correspond.
  • each of the three organic EL elements in the pixel circuit 10 connected to the data line S1j emits red light, and the i-th row, the j-th column, the (i + 1) -th row, the j-th column, and the ( i + 2) Corresponds to three R sub-pixels included in the color pixel in the row and column j.
  • All the three organic EL elements in the pixel circuit 10 connected to the data line S2j emit green light and correspond to the three G sub-pixels included in the three color pixels.
  • All the three organic EL elements in the pixel circuit 10 connected to the data line S3j emit blue light and correspond to the three B sub-pixels included in the three color pixels.
  • the three organic EL elements included in the pixel circuit 10 may be disposed at a position away from the light emitting element driving unit. As shown in FIG. 10, the light emitting element driving units are arranged side by side in the column direction. Three organic EL elements included in the pixel circuit 10 are also arranged in the column direction (see FIG. 2). In the case where the organic EL element is disposed at a position away from the light emitting element driving unit, wiring drawn from the light emitting element driving unit is connected to the organic EL element.
  • (m ⁇ n) color pixels are divided into three columns, and those in the first column, fourth column,... Are in the first color pixel, second column, fifth column,. Those in the second color pixel, third column, sixth column,... Are referred to as third color pixels.
  • one frame period is divided into first to third subframe periods. The first color pixel emits light in the first subframe period, the second color pixel emits light in the second subframe period, and the third color pixel emits light in the third subframe period.
  • the display device according to the second embodiment performs initialization, threshold value detection, and writing on the pixel circuits in three rows in parallel.
  • FIG. 11 is a timing chart of the pixel circuit 10 in the display device according to the second embodiment.
  • data potentials VRij, VGij, and VBij are applied to the data lines S1j, S2j, and S3j, respectively, during the selection period of the scanning line Gi within the first subframe period.
  • the three pixel circuits 10 emit light with luminance corresponding to the data potentials VRij, VGij, and VBij, respectively.
  • the data potentials VRi + 1j, VGi + 1j, and VBi + 1j are applied to the data lines S1j, S2j, and S3j, respectively.
  • the three pixel circuits 10 emit light with luminance corresponding to the data potentials VRi + 1j, VGi + 1j, and VBi + 1j, respectively.
  • the data potentials VRi + 2j, VGi + 2j, and VBi + 2j are applied to the data lines S1j, S2j, and S3j, respectively.
  • the three pixel circuits 10 emit light with luminance corresponding to the data potentials VRi + 2j, VGi + 2j, and VBi + 2j, respectively.
  • the data line driving circuit 3 uses the data potentials VRij, VRi + 1j, VRi + 2j with respect to the data lines S1j, S2j, S3j in the selection period of the scanning line Gi in the R subframe period. Apply. As described above, the data line driving circuit 3 of the display device 100 needs to output three data potentials corresponding to the sub-pixels of the same color included in different color pixels in parallel.
  • the data line driving circuit has the data potentials VRij, VGij with respect to the data lines S1j, S2j, S3j in the selection period of the scanning line Gi in the first subframe period. , VBij is applied.
  • the data line driving circuit of the display device according to the present embodiment may output three data potentials corresponding to the three sub-pixels included in one color pixel in parallel. Therefore, the display control circuit 1 can easily rearrange the data signals DA.
  • the output order of data potentials from the data line driving circuit matches the output order of interlaced video data. Therefore, the memory for rearranging the data signals DA can be deleted, or the amount of memory can be reduced.
  • the pixel circuit 10 is any one of a pixel circuit including a light emitting element that emits red light, a pixel circuit including a light emitting element that emits green light, and a pixel circuit including a light emitting element that emits blue light. is there.
  • the three light emitting elements included in the pixel circuit 10 correspond to sub-pixels of the same color included in the three color pixels arranged in the column direction in the display screen. In this way, elements can be supplied between a plurality of subpixels corresponding to the same color, and the number of elements in the pixel circuit can be reduced.
  • FIG. 12 is a block diagram showing a configuration of a display device according to the third embodiment of the present invention.
  • (n / 3) control lines EMi are deleted from the display device 100 (FIG. 1) according to the first embodiment, and the scanning line driving circuit 2 and the pixel circuit 10 are respectively connected.
  • the scanning line driving circuit 301 and the pixel circuit 30 are replaced.
  • the same elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
  • the scanning line driving circuit 301 is obtained by deleting the function of driving the control line EMi from the scanning line driving circuit 2.
  • the scanning line driving circuit 301 drives (n / 3) scanning lines Gi and (4n / 3) control lines GINIi, GMRi, GMGi, GMBi.
  • FIG. 13 is a circuit diagram of the pixel circuit 30.
  • a pixel circuit 30 shown in FIG. 13 is obtained by replacing the TFT 13 that is a P-type transistor with a TFT 31 that is an N-type transistor in the pixel circuit 10.
  • the power supply potential ELVDD is applied to the drain of the TFT 31, and the source of the TFT 31 is connected to the source of the TFT 11.
  • the gate of the TFT 31 is connected to the scanning line Gi together with the gates of the TFTs 12 and 15.
  • the control lines EMi can be reduced compared to the display device 100 according to the first embodiment. Therefore, the circuit amount of the scan line driver circuit 301 can be reduced, and the frame area of the display panel can be reduced.
  • the gate of the TFT 14 is connected to the control line GINIi, and the control line GINIi is a signal line different from the scanning line Gi.
  • the gate of the TFT 14 may be connected to the previous scanning line Gi-3. Thereby, (n / 3) control lines GINIi can be reduced.
  • FIG. 14 is a block diagram showing a configuration of a display device according to the fourth embodiment of the present invention. 14 replaces the scanning line driving circuit 2 and the pixel circuit 10 with the scanning line driving circuit 401 and the pixel circuit 40, respectively, in the display device 100 (FIG. 1) according to the first embodiment.
  • n / 3) the scanning lines Gi are replaced with (n / 3) scanning lines G1i, and (5n / 3) the control lines GINIi, EMi, EMRi, EMGi, EMBi are replaced with 2n control lines G2i, Substituted by G3i, G4i, G5Ri, G5Gi, G5Bi.
  • the same elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
  • FIG. 15 is a diagram showing a connection form of the pixel circuit 40.
  • FIG. 15 shows a connection form of three pixel circuits 40 adjacent in the column direction. All of the three pixel circuits 40 are connected to the scanning line G1i and the control lines G2i, G3i, G4i, G5Ri, G5Gi, and G5Bi.
  • the three pixel circuits 10 are connected to data lines S1j, S2j, and S3j, respectively.
  • FIG. 16 is a circuit diagram of the pixel circuit 40.
  • the pixel circuit 40 includes eleven TFTs 41 to 45, 46r, 46g, 46b, 47r, 47g, 47b, a capacitor 48, and three organic EL elements 49r, 49g, 49b.
  • the eleven TFTs are all N-type transistors, and the TFT 41 functions as a driving transistor.
  • the TFTs 41 to 45, 46r, 46g, 46b, 47r, 47g, 47b and the capacitor 48 function as a light emitting element driving unit.
  • the pixel circuit 40 is a modification of the pixel circuit described in FIG.
  • the power supply potential ELVDD is applied to the drain of the TFT 45.
  • the source of the TFT 45 is connected to the drains of the TFTs 41 and 43.
  • the source of the TFT 43 is connected to the gate of the TFT 41 and one electrode of the capacitor 48.
  • the source of the TFT 41 is connected to the drains of the TFTs 42, 46r, 46g, and 46b.
  • the source of the TFT 42 is connected to the data line S1j.
  • the sources of the TFTs 46r, 46g, and 46b are connected to the sources of the TFTs 47r, 47g, and 47b and the anodes of the organic EL elements 49r, 49g, and 49b, respectively.
  • a power supply potential ELVSS is applied to the cathodes of the organic EL elements 49r, 49g, and 49b.
  • the other electrode of the capacitor 48 and the drains of the TFTs 47r, 47g, 47b are connected to the source of the TFT 44.
  • An initialization potential Vini is applied to the drain of the TFT 44.
  • the gate of the TFT 42 is connected to the scanning line G1i.
  • the gates of the TFTs 43 to 45 are connected to control lines G3i, G4i, and G2i, respectively.
  • the gates of the TFTs 46r and 47r are connected to the control line G5Ri, the gates of the TFTs 46g and 47g are connected to the control line G5Gi, and the gates of the TFTs 46b and 47b are connected to the control line G5Bi.
  • the pixel circuit 40 shown in FIG. 16 is a pixel circuit Aij corresponding to the color pixel in the i-th row and the j-th column.
  • the pixel circuit Ai + 1j corresponding to the color pixel in the (i + 1) th row and the jth column and the pixel circuit Ai + 2j corresponding to the color pixel in the (i + 2) th row and the jth column also have the configuration shown in FIG.
  • the source of the TFT 42 is connected to the data line S2j
  • the source of the TFT 42 is connected to the data line S3j.
  • the pixel circuit 40 operates at the timing shown in FIG.
  • FIG. 17 is a timing chart of the pixel circuit 40.
  • FIG. 17 shows changes in potentials of ten signal lines connected to three pixel circuits Aij, Ai + 1j, and Ai + 2j adjacent in the column direction.
  • a period in which the potential of the scanning line G1i is at a high level is referred to as a selection period of the scanning line G1i
  • a period in which the potentials of the control lines G5Ri, G5Gi, and G5Bi are at a high level are respectively represented as This is called the B light emission period.
  • the operation of the pixel circuit Aij will be described with reference to FIG.
  • the potentials of the scanning line G1i and the control lines G3i, G4i, G5Ri, G5Gi, and G5Bi are at a low level, and the potential of the control line G2i is at a high level. Therefore, the TFTs 42 to 44, 46r, 46g, 46b, 47r, 47g, and 47b are in the off state, and the TFT 45 is in the on state.
  • the potentials of the scanning line G1i and the control lines G3i, G4i change to high level. Therefore, the TFTs 41 to 44 are turned on.
  • the gate potential of the TFT 41 is initialized to ELVDD, and the potential of the other electrode of the capacitor 48 is initialized to Vini.
  • the data potential VRij is applied to the data line S1j. For this reason, the source potential of the TFT 41 becomes VRij.
  • the potential of the control line G2i changes to a low level. For this reason, the TFT 45 is turned off.
  • the TFT 41 is in the ON state, a current passing through the TFTs 41 and 43 flows, and the gate potential of the TFT 41 decreases.
  • the threshold voltage of the TFT 41 is Vth
  • the gate potential of the TFT 41 falls to (VRij + Vth).
  • the potentials of the scanning line G1i and the control lines G3i, G4i change to a low level. For this reason, the TFTs 42 to 44 are turned off.
  • the capacitor 48 holds a potential difference (VRij + Vth ⁇ Vini).
  • the control lines G2i and G5Ri change to high level.
  • the TFTs 45, 46r, and 47r are turned on. Further, a potential difference (VRij + Vth ⁇ Vini) held in the capacitor 48 is applied between the gate and source of the TFT 41.
  • the current Ir shown in Equation (3) changes according to the data potential VRij, but does not depend on the threshold voltage Vth of the TFT 41. Therefore, even when the threshold voltage Vth varies or when the threshold voltage Vth changes over time, a current that does not depend on the threshold voltage Vth is caused to flow through the organic EL element 49r, and the organic EL element 49r emits light with a desired luminance. Can be made.
  • the potential of the control line G5Ri changes to a low level. For this reason, the TFTs 46r and 47r are turned off.
  • the pixel circuit Aij operates in the same manner as in the R subframe period.
  • the pixel circuits Ai + 1j and Ai + 2j perform the same operation as the pixel circuit Aij in parallel with the pixel circuit Aij.
  • the elements are shared among a plurality of sub-pixels.
  • the number of elements can be reduced.
  • the display device of the present invention it is possible to reduce the number of elements in a pixel circuit by sharing elements among a plurality of sub-pixels while suppressing an increase in scanning speed.
  • the display device of the present invention has a feature that the number of elements in the pixel circuit can be reduced while suppressing an increase in scanning speed, it can be used for an active matrix display device such as an organic EL display.

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Abstract

A pixel circuit (10) includes three organic EL elements and a light-emitting element driving unit which applies the current that has passed through a driving transistor to any one of the three organic EL elements. A scan line (Gi) is provided corresponding to three-row pixel circuits (10), and three data lines (S1j, S2j, S3j) are provided corresponding to each column of the pixel circuits (10). A scan line driving circuit and a data line driving circuit write data potential in parallel into the three-row pixel circuits (10). Thereby, elements are shared among a plurality of sub-pixels and thus the number of elements in a pixel circuit can be reduced while suppressing an increase in the scanning rate.

Description

表示装置およびその駆動方法Display device and driving method thereof
　本発明は、表示装置に関し、より特定的には、有機ＥＬディスプレイなどのアクティブマトリクス型の表示装置およびその駆動方法に関する。 The present invention relates to a display device, and more particularly, to an active matrix display device such as an organic EL display and a driving method thereof.
　薄型、高画質、低消費電力の表示装置として、有機ＥＬ（Electro Luminescence）ディスプレイが知られている。有機ＥＬディスプレイは、有機ＥＬ素子、駆動用トランジスタ、および、制御用トランジスタを含む複数の画素回路を備えている。画素回路内のトランジスタには、薄膜トランジスタ（Thin Film Transistor：以下、ＴＦＴという）が用いられる。 An organic EL (Electro Luminescence) display is known as a thin, high image quality, low power consumption display device. The organic EL display includes a plurality of pixel circuits including an organic EL element, a driving transistor, and a control transistor. As a transistor in the pixel circuit, a thin film transistor (hereinafter referred to as TFT) is used.
　有機ＥＬディスプレイでは、画素回路内の駆動用トランジスタの特性（閾値電圧や移動度）にばらつきが生じる。このため、画素回路に同じデータ電位を書き込んでも、有機ＥＬ素子を流れる電流の量にばらつきが生じる。有機ＥＬ素子の輝度は有機ＥＬ素子を流れる電流の量に応じて変化するので、有機ＥＬ素子を流れる電流の量にばらつきが生じると、表示画面に輝度むらが発生する。したがって、有機ＥＬディスプレイで高画質表示を行うためには、駆動用トランジスタの特性を補償する必要がある。 In the organic EL display, the characteristics (threshold voltage and mobility) of the driving transistor in the pixel circuit vary. For this reason, even if the same data potential is written in the pixel circuit, the amount of current flowing through the organic EL element varies. Since the luminance of the organic EL element changes in accordance with the amount of current flowing through the organic EL element, if the amount of current flowing through the organic EL element varies, uneven luminance occurs on the display screen. Therefore, in order to perform high-quality display on the organic EL display, it is necessary to compensate for the characteristics of the driving transistor.
　駆動用トランジスタの特性を補償する有機ＥＬディスプレイは、従来から各種知られている（例えば、特許文献１、２）。図１８は、特許文献１に記載された有機ＥＬディスプレイの画素回路の回路図である。図１８に示す画素回路７０は、６個のＴＦＴ７１～７６、コンデンサ７７、および、有機ＥＬ素子７８を含んでいる。画素回路７０は、ＴＦＴ７１（駆動用トランジスタ）の閾値電圧を補償する機能を有する。 Various organic EL displays that compensate for the characteristics of driving transistors have been known (for example, Patent Documents 1 and 2). FIG. 18 is a circuit diagram of a pixel circuit of an organic EL display described in Patent Document 1. A pixel circuit 70 shown in FIG. 18 includes six TFTs 71 to 76, a capacitor 77, and an organic EL element 78. The pixel circuit 70 has a function of compensating the threshold voltage of the TFT 71 (driving transistor).
　ＲＧＢ３色を用いてカラー表示を行う有機ＥＬディスプレイでは、１個のカラー画素は３個のサブ画素で構成される。画素回路７０を用いて３色カラー表示を行う有機ＥＬディスプレイを構成する場合、１個のカラー画素について１８個のＴＦＴと３個のコンデンサが必要になる。このように画素回路内の素子数が多くなると、表示パネルの歩留まりが低下し、高精細の表示パネルを実現できなくなるという問題が生じる。 In an organic EL display that performs color display using RGB three colors, one color pixel is composed of three sub-pixels. When an organic EL display that performs three-color display using the pixel circuit 70 is configured, 18 TFTs and three capacitors are required for one color pixel. Thus, when the number of elements in the pixel circuit is increased, the yield of the display panel is lowered, and there is a problem that a high-definition display panel cannot be realized.
　この問題を解決する方法の１つとして、複数のサブ画素間で画素回路内の素子を共有する方法が知られている（例えば、特許文献３～７）。図１９は、特許文献３に記載された有機ＥＬディスプレイの構成を示す図である。図１９に示す有機ＥＬディスプレイでは、上下に隣接する２個の有機ＥＬ素子８１ａ、８１ｂに対応して、１個の画素回路８０が設けられる。ＴＦＴ８２ａ、８２ｂが選択的にオン状態になり、有機ＥＬ素子８１ａ、８１ｂは選択的に発光する。図２０は、特許文献４に記載された有機ＥＬディスプレイの画素回路の回路図である。図２０に示す画素回路９０は、３個の有機ＥＬ素子９４ｒ、９４ｇ、９４ｂに対応して、ＴＦＴ９１（駆動用トランジスタ）と補償回路９２を１個ずつ含んでいる。ＴＦＴ９３ｒ、９３ｇ、９３ｂが選択的にオン状態になり、３個の有機ＥＬ素子９４ｒ、９４ｇ、９４ｂは選択的に発光する。 As one method of solving this problem, a method of sharing elements in a pixel circuit between a plurality of subpixels is known (for example, Patent Documents 3 to 7). FIG. 19 is a diagram showing a configuration of an organic EL display described in Patent Document 3. As shown in FIG. In the organic EL display shown in FIG. 19, one pixel circuit 80 is provided corresponding to two organic EL elements 81a and 81b adjacent in the vertical direction. The TFTs 82a and 82b are selectively turned on, and the organic EL elements 81a and 81b selectively emit light. FIG. 20 is a circuit diagram of a pixel circuit of an organic EL display described in Patent Document 4. A pixel circuit 90 shown in FIG. 20 includes one TFT 91 (driving transistor) and one compensation circuit 92 corresponding to the three organic EL elements 94r, 94g, and 94b. The TFTs 93r, 93g, 93b are selectively turned on, and the three organic EL elements 94r, 94g, 94b selectively emit light.
日本国特開２００５－３１６３０号公報Japanese Unexamined Patent Publication No. 2005-31630 日本国特開２００３－２０２８３３号公報Japanese Unexamined Patent Publication No. 2003-202833 日本国特開２００３－１２２３０６号公報Japanese Unexamined Patent Publication No. 2003-122306 日本国特開２００５－１６５２６６号公報Japanese Unexamined Patent Publication No. 2005-165266 日本国特開２００７－１２８０１９号公報Japanese Unexamined Patent Publication No. 2007-128019 日本国特開２００８－２６８４３７号公報Japanese Unexamined Patent Publication No. 2008-268437 日本国特開２０１０－１２２４６１号公報Japanese Unexamined Patent Publication No. 2010-122461
　しかしながら、複数のサブ画素間で素子を共有する従来の有機ＥＬディスプレイには、走査速度が速くなるという問題がある。例えば、特許文献４に記載された有機ＥＬディスプレイは、１フレーム期間を３個のサブフレーム期間に分割し、各サブフレーム期間において有機ＥＬ素子９４ｒに対する書き込み、有機ＥＬ素子９４ｇに対する書き込み、および、有機ＥＬ素子９４ｂに対する書き込みのいずれかを行う。このため、走査速度は、素子を共有しない場合の３倍になる。また、特許文献３に記載された有機ＥＬディスプレイでは、上下に隣接する２個のサブ画素間で素子を共有するので、共有部分が縦長になり、レイアウトが困難になるという問題も生じる。 However, the conventional organic EL display in which elements are shared among a plurality of sub-pixels has a problem that the scanning speed is increased. For example, in the organic EL display described in Patent Document 4, one frame period is divided into three subframe periods, and writing to the organic EL element 94r, writing to the organic EL element 94g, and organic One of writing to the EL element 94b is performed. For this reason, the scanning speed is three times that when elements are not shared. Further, in the organic EL display described in Patent Document 3, since the elements are shared between two vertically adjacent sub-pixels, there is a problem that the shared portion becomes vertically long and the layout becomes difficult.
　それ故に、本発明は、走査速度の増加を抑制しながら、複数のサブ画素間で素子を共有して画素回路内の素子数を削減した表示装置を提供することを目的とする。 Therefore, an object of the present invention is to provide a display device in which the number of elements in a pixel circuit is reduced by sharing elements among a plurality of sub-pixels while suppressing an increase in scanning speed.
　本発明の第１の局面は、アクティブマトリクス型の表示装置であって、
　行方向および列方向に並んだ複数の画素回路と、
　行方向に伸延する複数の走査線および複数の制御線と、
　列方向に伸延する複数のデータ線と、
　前記走査線および前記制御線を駆動する走査線駆動回路と、
　前記データ線を駆動するデータ線駆動回路とを備え、
　前記画素回路のそれぞれは、
　　複数の発光素子と、
　　１個の駆動用トランジスタを有し、前記駆動用トランジスタを通過した電流を前記制御線の電位に基づき前記複数の発光素子のいずれかに流す発光素子駆動部とを含み、
　前記走査線駆動回路および前記データ線駆動回路は、１フレーム期間を分割して得られたサブフレーム期間のそれぞれにおいて前記複数の画素回路にデータ電位を書き込み、サブフレーム期間ごとに前記駆動用トランジスタを通過した電流の経路を切り替え、
　前記走査線駆動回路および前記データ線駆動回路は、複数行の画素回路に対して前記データ電位を並列に書き込むことを特徴とする。 A first aspect of the present invention is an active matrix display device,
A plurality of pixel circuits arranged in a row direction and a column direction;
A plurality of scanning lines and a plurality of control lines extending in the row direction;
A plurality of data lines extending in the column direction;
A scanning line driving circuit for driving the scanning line and the control line;
A data line driving circuit for driving the data line,
Each of the pixel circuits is
A plurality of light emitting elements;
A light-emitting element drive unit that includes one drive transistor, and causes a current that has passed through the drive transistor to flow to any one of the plurality of light-emitting elements based on the potential of the control line,
The scanning line driving circuit and the data line driving circuit write data potentials to the plurality of pixel circuits in each of the subframe periods obtained by dividing one frame period, and the driving transistor is set in each subframe period. Switch the path of the current that passed,
The scan line driver circuit and the data line driver circuit write the data potentials in parallel to the pixel circuits in a plurality of rows.
　本発明の第２の局面は、本発明の第１の局面において、
　前記走査線は、前記画素回路の２以上の第１の数の行に対応して１本ずつ設けられ、
　前記データ線は、前記画素回路の各列に対応して前記第１の数ずつ設けられ、
　前記走査線駆動回路は、前記走査線を１本ずつ順に選択することにより、前記第１の数の行の画素回路を順に選択し、
　前記データ線駆動回路は、前記走査線駆動回路によって選択された画素回路に書き込むデータ電位を前記データ線に印加することを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
The scanning lines are provided one by one corresponding to a first number of rows of two or more of the pixel circuits,
The data lines are provided by the first number corresponding to the columns of the pixel circuit,
The scanning line driving circuit sequentially selects the pixel circuits in the first number of rows by sequentially selecting the scanning lines one by one,
The data line driving circuit applies a data potential to be written to the pixel circuit selected by the scanning line driving circuit to the data line.
　本発明の第３の局面は、本発明の第２の局面において、
　前記画素回路のそれぞれは、２以上の第２の数の発光素子を含み、
　前記走査線駆動回路および前記データ線駆動回路は、１フレーム期間を前記第２の数のサブフレーム期間に分割することを特徴とする。 According to a third aspect of the present invention, in the second aspect of the present invention,
Each of the pixel circuits includes a second number of light emitting elements of 2 or more,
The scanning line driving circuit and the data line driving circuit divide one frame period into the second number of subframe periods.
　本発明の第４の局面は、本発明の第３の局面において、
　前記画素回路に含まれる前記複数の発光素子は、表示画面内で行方向に並び、１個のカラー画素を構成する複数のサブ画素に対応することを特徴とする。 According to a fourth aspect of the present invention, in the third aspect of the present invention,
The plurality of light emitting elements included in the pixel circuit are arranged in a row direction in a display screen, and correspond to a plurality of subpixels constituting one color pixel.
　本発明の第５の局面は、本発明の第４の局面において、
　前記画素回路のそれぞれは、赤色に発光する発光素子、緑色に発光する発光素子、および、青色に発光する発光素子を１個ずつ含むことを特徴とする。 According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
Each of the pixel circuits includes one light emitting element that emits red light, one light emitting element that emits green light, and one light emitting element that emits blue light.
　本発明の第６の局面は、本発明の第３の局面において、
　前記画素回路に含まれる前記複数の発光素子は、表示画面内で行方向に並び、隣接した複数のカラー画素を構成する複数のサブ画素に対応することを特徴とする。 According to a sixth aspect of the present invention, in the third aspect of the present invention,
The plurality of light emitting elements included in the pixel circuit correspond to a plurality of subpixels arranged in a row direction in a display screen and constituting a plurality of adjacent color pixels.
　本発明の第７の局面は、本発明の第６の局面において、
　前記画素回路のそれぞれは、赤色に発光する発光素子、緑色に発光する発光素子、および、青色に発光する発光素子を複数個ずつ含むことを特徴とする。 A seventh aspect of the present invention is the sixth aspect of the present invention,
Each of the pixel circuits includes a plurality of light emitting elements that emit red light, light emitting elements that emit green light, and light emitting elements that emit blue light.
　本発明の第８の局面は、本発明の第３の局面において、
　前記画素回路に含まれる前記複数の発光素子は、表示画面内で列方向に並んだ複数のカラー画素に含まれる同じ色のサブ画素に対応することを特徴とする。 According to an eighth aspect of the present invention, in the third aspect of the present invention,
The plurality of light emitting elements included in the pixel circuit correspond to sub-pixels of the same color included in the plurality of color pixels arranged in the column direction in the display screen.
　本発明の第９の局面は、本発明の第８の局面において、
　前記画素回路は、赤色に発光する発光素子を含む画素回路、緑色に発光する発光素子を含む画素回路、および、青色に発光する発光素子を含む画素回路のいずれかであることを特徴とする。 A ninth aspect of the present invention is the eighth aspect of the present invention,
The pixel circuit is any one of a pixel circuit including a light emitting element that emits red light, a pixel circuit including a light emitting element that emits green light, and a pixel circuit including a light emitting element that emits blue light.
　本発明の第１０の局面は、本発明の第３の局面において、
　前記第１の数は前記第２の数に等しいことを特徴とする。 According to a tenth aspect of the present invention, in the third aspect of the present invention,
The first number is equal to the second number.
　本発明の第１１の局面は、本発明の第３の局面において、
　前記第１の数は前記第２の数よりも小さいことを特徴とする。 An eleventh aspect of the present invention is the third aspect of the present invention,
The first number is smaller than the second number.
　本発明の第１２の局面は、本発明の第３の局面において、
　前記第１の数は前記第２の数よりも大きいことを特徴とする。 A twelfth aspect of the present invention is the third aspect of the present invention,
The first number is larger than the second number.
　本発明の第１３の局面は、本発明の第３の局面において、
　前記発光素子駆動部は、前記駆動用トランジスタと前記発光素子のそれぞれとの間に、制御端子が互いに異なる前記制御線に接続されたスイッチ素子を含むことを特徴とする。 A thirteenth aspect of the present invention is the third aspect of the present invention,
The light emitting element driving unit includes a switch element having a control terminal connected to the control line different from each other between the driving transistor and the light emitting element.
　本発明の第１４の局面は、行方向に伸延する複数の走査線および複数の制御線と、列方向に伸延する複数のデータ線と、それぞれが複数の発光素子と、駆動用トランジスタを通過した電流を前記複数の発光素子のいずれかに流す発光素子駆動部とを含み、行方向および列方向に並んだ複数の画素回路とを備えたアクティブマトリクス型の表示装置の駆動方法であって、
　前記走査線および前記データ線を駆動することにより、１フレーム期間を分割して得られたサブフレーム期間のそれぞれにおいて前記複数の画素回路にデータ電位を書き込むステップと、
　前記制御線を駆動することにより、サブフレーム期間ごとに前記駆動用トランジスタを通過した電流の経路を切り替えるステップとを備え、
　前記データ電位を書き込むステップは、複数行の画素回路に対して前記データ電位を並列に書き込むことを特徴とする。 In a fourteenth aspect of the present invention, a plurality of scanning lines and a plurality of control lines extending in the row direction, a plurality of data lines extending in the column direction, each passing through a plurality of light emitting elements and a driving transistor. A driving method of an active matrix display device including a plurality of pixel circuits arranged in a row direction and a column direction, and a light emitting element driving unit that causes a current to flow to any of the plurality of light emitting elements,
Writing data potentials to the plurality of pixel circuits in each of the sub-frame periods obtained by dividing one frame period by driving the scanning lines and the data lines;
Switching the path of the current that has passed through the driving transistor every subframe period by driving the control line, and
The step of writing the data potential is characterized in that the data potential is written in parallel to a plurality of rows of pixel circuits.
　本発明の第１または第１４の局面によれば、複数の発光素子に対応して、駆動用トランジスタを通過した電流を複数の発光素子のいずれかに流す発光素子駆動部を設けることにより、複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。また、複数行の画素回路に対してデータ電位を並列に書き込むことにより、走査速度の増加を抑制することができる。したがって、走査速度の増加を抑制しながら、複数のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 According to the first or fourteenth aspect of the present invention, a plurality of light emitting element driving units that allow a current that has passed through the driving transistor to flow to any one of the plurality of light emitting elements are provided corresponding to the plurality of light emitting elements. The elements can be shared among the sub-pixels, and the number of elements in the pixel circuit can be reduced. In addition, an increase in scanning speed can be suppressed by writing data potentials in parallel to pixel circuits in a plurality of rows. Therefore, it is possible to reduce the number of elements in the pixel circuit by sharing elements among the plurality of sub-pixels while suppressing an increase in scanning speed.
　本発明の第２の局面によれば、ｐ行の画素回路に対応して１本の走査線を設け、画素回路の各列に対応してｐ本のデータ線を設けることにより、ｐ行の画素回路に対してデータ電位を並列に書き込むことができる。したがって、画素回路に対して１行ずつ書き込みを行う場合と比べて、走査速度を１／ｐに低減することができる。 According to the second aspect of the present invention, by providing one scanning line corresponding to the pixel circuit of p rows and providing p data lines corresponding to each column of the pixel circuit, Data potentials can be written in parallel to the pixel circuit. Therefore, the scanning speed can be reduced to 1 / p compared to the case where writing is performed row by row to the pixel circuit.
　本発明の第３の局面によれば、ｑ個の発光素子に対応して発光素子駆動部を設けることにより、ｑ個のサブ画素間で素子を共有し、素子を共有しない場合と比べて画素回路内の素子数を最も好ましい場合には約１／ｑに削減することができる。また、特段の工夫を行うことなくｑ個のサブ画素間で素子を共有すると、走査速度がｑ倍になる。そこで、ｐ行の画素回路に対してデータ電位を並列に書き込むことにより、素子を共有せず、画素回路に対して１行ずつ書き込みを行う場合と比べて、走査速度を（ｑ／ｐ）倍に抑制することができる。 According to the third aspect of the present invention, by providing the light emitting element driving unit corresponding to q light emitting elements, the elements are shared among the q sub pixels, and the pixels are compared with the case where the elements are not shared. In the most preferred case, the number of elements in the circuit can be reduced to about 1 / q. In addition, if the elements are shared among the q sub-pixels without special measures, the scanning speed is increased q times. Therefore, by writing data potentials in parallel to the pixel circuit in the p row, the scanning speed is (q / p) times as compared with the case where writing is performed row by row in the pixel circuit without sharing the elements. Can be suppressed.
　本発明の第４または第５の局面によれば、１個のカラー画素を構成する複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。 According to the fourth or fifth aspect of the present invention, elements can be shared among a plurality of sub-pixels constituting one color pixel, and the number of elements in the pixel circuit can be reduced.
　本発明の第６または第７の局面によれば、複数のカラー画素を構成する複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。 According to the sixth or seventh aspect of the present invention, elements can be shared among a plurality of sub-pixels constituting a plurality of color pixels, and the number of elements in the pixel circuit can be reduced.
　本発明の第８または第９の局面によれば、同じ色に対応した複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。 According to the eighth or ninth aspect of the present invention, elements can be shared among a plurality of sub-pixels corresponding to the same color, and the number of elements in the pixel circuit can be reduced.
　本発明の第１０の局面によれば、第１の数ｐと第２の数ｑを等しくした場合、走査速度を変化させずに、ｑ個のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 According to the tenth aspect of the present invention, when the first number p and the second number q are made equal, the elements are shared among the q sub-pixels without changing the scanning speed. The number of elements can be reduced.
　本発明の第１１の局面によれば、第１の数ｐを第２の数ｑよりも小さくした場合、走査速度の増加を（ｑ／ｐ）倍に抑制しながら、ｑ個のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 According to the eleventh aspect of the present invention, when the first number p is smaller than the second number q, the increase in the scanning speed is suppressed to (q / p) times, and between the q sub-pixels. Thus, the number of elements in the pixel circuit can be reduced by sharing the elements.
　本発明の第１２の局面によれば、第１の数ｐを第２の数ｑよりも大きくした場合、走査速度を（ｑ／ｐ）倍に低減させながら、ｑ個のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 According to the twelfth aspect of the present invention, when the first number p is larger than the second number q, the scanning speed is reduced by a factor of (q / p), and the element between q sub-pixels is reduced. And the number of elements in the pixel circuit can be reduced.
　本発明の第１３の局面によれば、駆動用トランジスタと各発光素子の間にスイッチ素子を設け、スイッチ素子の制御端子を互いに異なる制御線に接続することにより、駆動用トランジスタを通過した電流を複数の発光素子のいずれかに流す発光素子駆動部を容易に構成することができる。 According to the thirteenth aspect of the present invention, a switch element is provided between the drive transistor and each light-emitting element, and the control terminal of the switch element is connected to different control lines, whereby the current passed through the drive transistor is It is possible to easily configure a light emitting element driving unit that flows to any one of the plurality of light emitting elements.
本発明の第１の実施形態に係る表示装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display apparatus which concerns on the 1st Embodiment of this invention. 図１に示す表示装置における表示画面内のサブ画素の配置を示す図である。FIG. 2 is a diagram showing an arrangement of sub-pixels in a display screen in the display device shown in FIG. 1. 図１に示す表示装置に含まれる画素回路の接続形態を示す図である。It is a figure which shows the connection form of the pixel circuit contained in the display apparatus shown in FIG. 図１に示す表示装置に含まれる画素回路の回路図である。FIG. 2 is a circuit diagram of a pixel circuit included in the display device shown in FIG. 1. 図１に示す表示装置に含まれる各行の画素回路の動作を示す図である。FIG. 2 is a diagram illustrating an operation of a pixel circuit in each row included in the display device illustrated in FIG. 1. 図１に示す表示装置に含まれる画素回路のタイミングチャートである。2 is a timing chart of a pixel circuit included in the display device shown in FIG. 本発明の第１変形例に係る表示装置に含まれる画素回路の接続形態を示す図である。It is a figure which shows the connection form of the pixel circuit contained in the display apparatus which concerns on the 1st modification of this invention. 本発明の第１変形例に係る表示装置に含まれる画素回路の回路図である。It is a circuit diagram of a pixel circuit included in a display device according to a first modification of the present invention. 本発明の第２変形例に係る表示装置に含まれる画素回路の接続形態を示す図である。It is a figure which shows the connection form of the pixel circuit contained in the display apparatus which concerns on the 2nd modification of this invention. 本発明の第２の実施形態に係る表示装置に含まれる画素回路の接続形態を示す図である。It is a figure which shows the connection form of the pixel circuit contained in the display apparatus which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る表示装置に含まれる画素回路のタイミングチャートである。6 is a timing chart of a pixel circuit included in a display device according to a second embodiment of the present invention. 本発明の第３の実施形態に係る表示装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display apparatus which concerns on the 3rd Embodiment of this invention. 図１２に示す表示装置に含まれる画素回路の回路図である。FIG. 13 is a circuit diagram of a pixel circuit included in the display device shown in FIG. 12. 本発明の第４の実施形態に係る表示装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display apparatus which concerns on the 4th Embodiment of this invention. 図１４に示す表示装置に含まれる画素回路の接続形態を示す図である。It is a figure which shows the connection form of the pixel circuit contained in the display apparatus shown in FIG. 図１４に示す表示装置に含まれる画素回路の回路図である。FIG. 15 is a circuit diagram of a pixel circuit included in the display device shown in FIG. 14. 図１４に示す表示装置に含まれる画素回路のタイミングチャートである。15 is a timing chart of a pixel circuit included in the display device shown in FIG. 従来の有機ＥＬディスプレイの画素回路の回路図である。It is a circuit diagram of the pixel circuit of the conventional organic EL display. 従来の有機ＥＬディスプレイの構成を示すブロック図である。It is a block diagram which shows the structure of the conventional organic EL display. 従来の有機ＥＬディスプレイの画素回路の回路図である。It is a circuit diagram of the pixel circuit of the conventional organic EL display.
　（第１の実施形態）
　図１は、本発明の第１の実施形態に係る表示装置の構成を示すブロック図である。図１に示す表示装置１００は、表示制御回路１、走査線駆動回路２、データ線駆動回路３、および、（ｍ×ｎ）個の画素回路１０を備えたアクティブマトリクス型の有機ＥＬディスプレイである。以下、ｍは２以上の整数、ｎは３の倍数、ｉは１、４、…、ｎ－５、ｎ－２のうちいずれかの数、ｊは１以上ｍ以下の整数であるとする。 (First embodiment)
FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention. A display device 100 illustrated in FIG. 1 is an active matrix organic EL display including a display control circuit 1, a scanning line driving circuit 2, a data line driving circuit 3, and (m × n) pixel circuits 10. . In the following, m is an integer of 2 or more, n is a multiple of 3, i is any number of 1, 4,..., N-5, n-2, and j is an integer of 1 to m.
　表示装置１００には、（ｎ／３）本の走査線Ｇｉ、（５ｎ／３）本の制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉ、および、３ｍ本のデータ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊが設けられる。（ｎ／３）本の走査線と（５ｎ／３）本の制御線は、互いに平行に配置される。３ｍ本のデータ線は、走査線および制御線と直交するように互いに平行に配置される。以下、走査線と制御線の伸延方向（図では横方向）を行方向といい、データ線の伸延方向（図では縦方向）を列方向という。（ｎ／３）本の走査線と３ｍ本のデータ線は、（ｍ×ｎ）箇所で交差する。画素回路１０は、走査線とデータ線の交差点に対応して設けられる。このように画素回路１０は、行方向と列方向に並べて２次元状に配置される。なお、表示装置の構成を示すブロック図では、列方向に隣接した３個の画素回路を１個の長方形で表す。 The display device 100 is provided with (n / 3) scanning lines Gi, (5n / 3) control lines GINIi, EMi, EMRi, EMGi, EMBi, and 3m data lines S1j, S2j, S3j. It is done. (N / 3) scanning lines and (5n / 3) control lines are arranged in parallel to each other. The 3m data lines are arranged in parallel to each other so as to be orthogonal to the scanning lines and the control lines. Hereinafter, the extending direction (horizontal direction in the figure) of the scanning line and the control line is referred to as the row direction, and the extending direction of the data line (vertical direction in the figure) is referred to as the column direction. (N / 3) scanning lines and 3m data lines intersect at (m × n) locations. The pixel circuit 10 is provided corresponding to the intersection of the scanning line and the data line. Thus, the pixel circuits 10 are arranged two-dimensionally in the row direction and the column direction. Note that in the block diagram illustrating the structure of the display device, three pixel circuits adjacent in the column direction are represented by one rectangle.
　表示制御回路１は、走査線駆動回路２とデータ線駆動回路３に対して制御信号を出力する。より詳細には、表示制御回路１は、走査線駆動回路２に対してタイミング信号ＯＥ、スタートパルスＹＩおよびクロックＹＣＫを出力し、データ線駆動回路３に対してスタートパルスＳＰ、クロックＣＬＫ、データ信号ＤＡおよびラッチパルスＬＰを出力する。 The display control circuit 1 outputs control signals to the scanning line driving circuit 2 and the data line driving circuit 3. More specifically, the display control circuit 1 outputs a timing signal OE, a start pulse YI, and a clock YCK to the scanning line driving circuit 2, and a start pulse SP, a clock CLK, a data signal to the data line driving circuit 3. DA and latch pulse LP are output.
　走査線駆動回路２は、走査線Ｇｉと制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉを駆動する。より詳細には、走査線駆動回路２は、シフトレジスタ回路、論理演算回路、および、バッファ（いずれも図示せず）を含んでいる。シフトレジスタ回路は、クロックＹＣＫに同期してスタートパルスＹＩを順次転送する。論理演算回路は、シフトレジスタ回路の各段から出力されたパルスとタイミング信号ＯＥとの間で論理演算を行う。論理演算回路の出力は、バッファを経由して対応する走査線と制御線に与えられる。 The scanning line driving circuit 2 drives the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi. More specifically, the scanning line driving circuit 2 includes a shift register circuit, a logical operation circuit, and a buffer (all not shown). The shift register circuit sequentially transfers the start pulse YI in synchronization with the clock YCK. The logical operation circuit performs a logical operation between the pulse output from each stage of the shift register circuit and the timing signal OE. The output of the logical operation circuit is given to the corresponding scanning line and control line via the buffer.
　データ線駆動回路３は、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊを駆動する。より詳細には、データ線駆動回路３は、ｍビットのシフトレジスタ４、レジスタ５、ラッチ回路６、および、３ｍ個のＤ／Ａ変換器７を含んでいる。シフトレジスタ４は、ｍ個のレジスタを多段接続した構成を有し、初段のレジスタに供給されたスタートパルスＳＰをクロックＣＬＫに同期して転送し、各段のレジスタからタイミングパルスＤＬＰを出力する。タイミングパルスＤＬＰの出力タイミングに合わせて、レジスタ５にはサブ画素３個分のデータ信号ＤＡが供給される。レジスタ５は、タイミングパルスＤＬＰに従い、データ信号ＤＡを記憶する。レジスタ５に３行分のデータ信号ＤＡが記憶されると、表示制御回路１はラッチ回路６に対してラッチパルスＬＰを出力する。ラッチ回路６は、ラッチパルスＬＰを受け取ると、レジスタ５に記憶されたデータ信号ＤＡを保持する。３ｍ個のＤ／Ａ変換器７は、３ｍ本のデータ線のそれぞれに対応して設けられる。Ｄ／Ａ変換器７は、ラッチ回路６に保持されたデータ信号ＤＡに応じたデータ電位を対応するデータ線に印加する。 The data line driving circuit 3 drives the data lines S1j, S2j, S3j. More specifically, the data line driving circuit 3 includes an m-bit shift register 4, a register 5, a latch circuit 6, and 3m D / A converters 7. The shift register 4 has a configuration in which m registers are connected in multiple stages, transfers the start pulse SP supplied to the first stage register in synchronization with the clock CLK, and outputs a timing pulse DLP from each stage register. The data signal DA for three subpixels is supplied to the register 5 in accordance with the output timing of the timing pulse DLP. The register 5 stores the data signal DA according to the timing pulse DLP. When the data signals DA for three rows are stored in the register 5, the display control circuit 1 outputs a latch pulse LP to the latch circuit 6. When receiving the latch pulse LP, the latch circuit 6 holds the data signal DA stored in the register 5. The 3m D / A converters 7 are provided corresponding to the 3m data lines. The D / A converter 7 applies a data potential corresponding to the data signal DA held in the latch circuit 6 to the corresponding data line.
　図２は、表示装置１００における表示画面内のサブ画素の配置を示す図である。図２には、表示画面内で列方向に隣接した３個のカラー画素の構成が記載されている。表示装置１００は、ＲＧＢ３色を用いてカラー表示を行う。このため、１個のカラー画素（太線で囲んだ部分）は、表示画面内で行方向に隣接した３個のサブ画素（赤色を表示するＲサブ画素、緑色を表示するＧサブ画素、および、青色を表示するＢサブ画素）で構成される。 FIG. 2 is a diagram showing the arrangement of sub-pixels in the display screen of the display device 100. As shown in FIG. FIG. 2 shows a configuration of three color pixels adjacent in the column direction in the display screen. The display device 100 performs color display using RGB three colors. For this reason, one color pixel (portion surrounded by a thick line) is composed of three sub-pixels (R sub-pixel displaying red, G sub-pixel displaying green, and B sub-pixels that display blue).
　図３は、画素回路１０の接続形態を示す図である。図３には、列方向に隣接した３個の画素回路１０の接続形態が記載されている。画素回路１０は、図２に示すカラー画素に対応する。図３に示すように、３個の画素回路１０は、走査線Ｇｉと３本のデータ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊの交差点の近傍にそれぞれ設けられる。３個の画素回路１０は、いずれも、走査線Ｇｉと制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉに接続される。また、３個の画素回路１０は、それぞれ、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊに接続される。データ線Ｓ１ｊに接続された画素回路１０は、第ｉ行第ｊ列のカラー画素に対応する。データ線Ｓ２ｊに接続された画素回路１０は、第（ｉ＋１）行第ｊ列のカラー画素に対応する。データ線Ｓ３ｊに接続された画素回路１０は、第（ｉ＋２）行第ｊ列のカラー画素に対応する。以下、第ｉ行第ｊ列のカラー画素に対応した画素回路１０を画素回路Ａｉｊという。３個の画素回路１０は、いずれも、３個の有機ＥＬ素子と発光素子駆動部を含む。発光素子駆動部は、１個の駆動用トランジスタを有し、駆動用トランジスタを通過した電流を制御線ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉの電位に基づき３個の有機ＥＬ素子のいずれかに流す。 FIG. 3 is a diagram showing a connection form of the pixel circuit 10. FIG. 3 shows a connection form of three pixel circuits 10 adjacent in the column direction. The pixel circuit 10 corresponds to the color pixel shown in FIG. As shown in FIG. 3, the three pixel circuits 10 are provided in the vicinity of the intersection of the scanning line Gi and the three data lines S1j, S2j, and S3j. All of the three pixel circuits 10 are connected to the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi. The three pixel circuits 10 are connected to data lines S1j, S2j, and S3j, respectively. The pixel circuit 10 connected to the data line S1j corresponds to the color pixel in the i-th row and the j-th column. The pixel circuit 10 connected to the data line S2j corresponds to the color pixel of the (i + 1) th row and the jth column. The pixel circuit 10 connected to the data line S3j corresponds to the color pixel in the (i + 2) th row and the jth column. Hereinafter, the pixel circuit 10 corresponding to the color pixel in the i-th row and the j-th column is referred to as a pixel circuit Aij. Each of the three pixel circuits 10 includes three organic EL elements and a light emitting element driving unit. The light emitting element driving unit has one driving transistor, and the current that has passed through the driving transistor flows to one of the three organic EL elements based on the potentials of the control lines EMRi, EMGi, and EMBi.
　図４は、画素回路１０の回路図である。画素回路１０は、８個のＴＦＴ１１～１５、１６ｒ、１６ｇ、１６ｂ、コンデンサ１７、および、３個の有機ＥＬ素子１８ｒ、１８ｇ、１８ｂを含んでいる。有機ＥＬ素子１８ｒ、１８ｇ、１８ｂは、それぞれ、赤色、緑色および青色に発光する発光素子である。８個のＴＦＴはいずれもＰ型トランジスタであり、ＴＦＴ１１は駆動用トランジスタとして機能する。ＴＦＴ１１～１５、１６ｒ、１６ｇ、１６ｂとコンデンサ１７は、発光素子駆動部として機能する。画素回路１０は、走査線Ｇｉ、制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉ、および、データ線Ｓ１ｊに加えて、初期化電位Ｖｉｎｉを有する配線、電源電位ＥＬＶＤＤを有する配線、および、電源電位ＥＬＶＳＳを有する電極に接続される。なお、画素回路１０は、特許文献１の図１に記載された画素回路を変形したものである。 FIG. 4 is a circuit diagram of the pixel circuit 10. The pixel circuit 10 includes eight TFTs 11 to 15, 16r, 16g, and 16b, a capacitor 17, and three organic EL elements 18r, 18g, and 18b. The organic EL elements 18r, 18g, and 18b are light emitting elements that emit red, green, and blue light, respectively. Each of the eight TFTs is a P-type transistor, and the TFT 11 functions as a driving transistor. The TFTs 11 to 15, 16r, 16g, and 16b and the capacitor 17 function as a light emitting element driving unit. In addition to the scanning line Gi, the control lines GINIi, EMi, EMRi, EMGi, EMBi, and the data line S1j, the pixel circuit 10 includes a wiring having an initialization potential Vini, a wiring having a power supply potential ELVDD, and a power supply potential ELVSS. Is connected to an electrode having The pixel circuit 10 is a modification of the pixel circuit described in FIG.
　図４に示すように、ＴＦＴ１３のソースとコンデンサ１７の一方の電極には電源電位ＥＬＶＤＤが印加され、ＴＦＴ１５のソースはデータ線Ｓ１ｊに接続される。ＴＦＴ１３、１５のドレインは、ＴＦＴ１１のソースに接続される。ＴＦＴ１１のドレインは、ＴＦＴ１２、１６ｒ、１６ｇ、１６ｂのソースに接続される。ＴＦＴ１４のドレインには初期化電位Ｖｉｎｉが印加される。ＴＦＴ１２のドレイン、ＴＦＴ１４のソース、および、コンデンサ１７の他方の電極は、ＴＦＴ１１のゲートに接続される。ＴＦＴ１６ｒ、１６ｇ、１６ｂのドレインは、それぞれ、有機ＥＬ素子１８ｒ、１８ｇ、１８ｂのアノードに接続される。有機ＥＬ素子１８ｒ、１８ｇ、１８ｂのカソードには、電源電位ＥＬＶＳＳが印加される。ＴＦＴ１２、１５のゲートは走査線Ｇｉに接続され、ＴＦＴ１３のゲートは制御線ＥＭｉに接続され、ＴＦＴ１４のゲートは制御線ＧＩＮＩｉに接続される。ＴＦＴ１６ｒ、１６ｇ、１６ｂのゲートは、それぞれ、制御線ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉに接続される。 As shown in FIG. 4, the power supply potential ELVDD is applied to the source of the TFT 13 and one electrode of the capacitor 17, and the source of the TFT 15 is connected to the data line S1j. The drains of the TFTs 13 and 15 are connected to the source of the TFT 11. The drain of the TFT 11 is connected to the sources of the TFTs 12, 16r, 16g, and 16b. An initialization potential Vini is applied to the drain of the TFT 14. The drain of the TFT 12, the source of the TFT 14, and the other electrode of the capacitor 17 are connected to the gate of the TFT 11. The drains of the TFTs 16r, 16g, and 16b are connected to the anodes of the organic EL elements 18r, 18g, and 18b, respectively. A power supply potential ELVSS is applied to the cathodes of the organic EL elements 18r, 18g, and 18b. The gates of the TFTs 12 and 15 are connected to the scanning line Gi, the gate of the TFT 13 is connected to the control line EMi, and the gate of the TFT 14 is connected to the control line GINIi. The gates of the TFTs 16r, 16g, and 16b are connected to control lines EMRi, EMGi, and EMBi, respectively.
　このようにＴＦＴ１１（駆動用トランジスタ）と有機ＥＬ素子１８ｒ、１８ｇ、１８ｂの間にＴＦＴ１６ｒ、１６ｇ、１６ｂ（スイッチ素子）を設け、ＴＦＴ１６ｒ、１６ｇ、１６ｂのゲートを互いに異なる制御線ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉに接続することにより、ＴＦＴ１１を通過した電流を有機ＥＬ素子１８ｒ、１８ｇ、１８ｂのいずれかに流す発光素子駆動部を容易に構成することができる。 In this way, the TFTs 16r, 16g, and 16b (switch elements) are provided between the TFT 11 (drive transistor) and the organic EL elements 18r, 18g, and 18b, and the gates of the TFTs 16r, 16g, and 16b are connected to different control lines EMRi, EMGi, and EMBi. By connecting to, it is possible to easily configure a light emitting element driving section that allows the current that has passed through the TFT 11 to flow to any one of the organic EL elements 18r, 18g, and 18b.
　図４に示す画素回路１０は、第ｉ行第ｊ列のカラー画素に対応した画素回路Ａｉｊである。第（ｉ＋１）行第ｊ列のカラー画素に対応した画素回路Ａｉ＋１ｊと、第（ｉ＋２）行第ｊ列のカラー画素に対応した画素回路Ａｉ＋２ｊも、図４に示す構成を有する。ただし、画素回路Ａｉ＋１ｊではＴＦＴ１５のソースはデータ線Ｓ２ｊに接続され、画素回路Ａｉ＋２ｊではＴＦＴ１５のソースはデータ線Ｓ３ｊに接続される。 The pixel circuit 10 shown in FIG. 4 is a pixel circuit Aij corresponding to the color pixel in the i-th row and the j-th column. The pixel circuit Ai + 1j corresponding to the color pixel in the (i + 1) th row and the jth column and the pixel circuit Ai + 2j corresponding to the color pixel in the (i + 2) th row and the jth column also have the configuration shown in FIG. However, in the pixel circuit Ai + 1j, the source of the TFT 15 is connected to the data line S2j, and in the pixel circuit Ai + 2j, the source of the TFT 15 is connected to the data line S3j.
　図５は、各行の画素回路１０の動作を示す図である。図５に示すように、表示装置１００では、１フレーム期間は３個のサブフレーム期間（Ｒサブフレーム期間、Ｇサブフレーム期間、および、Ｂサブフレーム期間）に分割される。走査線駆動回路２とデータ線駆動回路３は、１フレーム期間を分割して得られたサブフレーム期間のそれぞれにおいて（ｍ×ｎ）個の画素回路１０にデータ電位を書き込み、サブフレーム期間ごとにＴＦＴ１１（駆動用トランジスタ）を通過した電流の経路を切り替える。また、走査線駆動回路２とデータ線駆動回路３は、３行の画素回路１０に対する初期化、閾値検出、および、データ電位の書き込みを並列に行う。 FIG. 5 is a diagram illustrating the operation of the pixel circuits 10 in each row. As shown in FIG. 5, in display device 100, one frame period is divided into three subframe periods (R subframe period, G subframe period, and B subframe period). The scanning line driving circuit 2 and the data line driving circuit 3 write data potentials to (m × n) pixel circuits 10 in each of the subframe periods obtained by dividing one frame period, and each subframe period The path of the current passing through the TFT 11 (driving transistor) is switched. In addition, the scanning line driving circuit 2 and the data line driving circuit 3 perform initialization, threshold value detection, and data potential writing on the pixel circuits 10 in three rows in parallel.
　（ｍ×ｎ）個の画素回路１０は、３行ずつ（ｎ／３）個のグループに分割される。例えば、第１行～第３行の画素回路は第１グループに、第４行～第６行の画素回路は第２グループに、第（ｎ－２）行～第ｎ行の画素回路は第（ｎ／３）グループに分類される。第１グループの画素回路については、１フレーム期間の先頭から、Ｒサブフレーム期間、Ｇサブフレーム期間、および、Ｂサブフレーム期間が順に設定される。各サブフレーム期間の先頭では、第１グループの画素回路に対する初期化、閾値補償、および、データ電位の書き込みが行われる。第１グループの画素回路内の有機ＥＬ素子１８ｒは、Ｒサブフレーム期間の残部で発光する。第１グループの画素回路内の有機ＥＬ素子１８ｇは、Ｇサブフレーム期間の残部で発光する。第１グループの画素回路内の有機ＥＬ素子１８ｂは、Ｂサブフレーム期間の残部で発光する。 (M × n) pixel circuits 10 are divided into (n / 3) groups by three rows. For example, the pixel circuits in the first to third rows are in the first group, the pixel circuits in the fourth to sixth rows are in the second group, and the pixel circuits in the (n−2) -th to n-th rows are in the first group. Classified into (n / 3) groups. For the first group of pixel circuits, an R subframe period, a G subframe period, and a B subframe period are sequentially set from the beginning of one frame period. At the beginning of each subframe period, initialization, threshold compensation, and data potential writing are performed on the first group of pixel circuits. The organic EL elements 18r in the first group of pixel circuits emit light in the remainder of the R subframe period. The organic EL elements 18g in the first group of pixel circuits emit light in the remainder of the G subframe period. The organic EL elements 18b in the first group of pixel circuits emit light in the remaining part of the B subframe period.
　第ｋグループ（ｋは２以上（ｎ／３）以下の整数）の画素回路については、第（ｋ－１）グループの画素回路に対するデータ電位の書き込み完了後に、Ｒサブフレーム期間、Ｇサブフレーム期間、および、Ｂサブフレーム期間が順に設定される。各サブフレーム期間の先頭では、第ｋグループの画素回路に対する初期化、閾値補償、および、データ電位の書き込みが行われる。第ｋグループの画素回路内の有機ＥＬ素子１８ｒは、Ｒサブフレーム期間の残部で発光する。第ｋグループの画素回路内の有機ＥＬ素子１８ｇは、Ｇサブフレーム期間の残部で発光する。第ｋグループの画素回路内の有機ＥＬ素子１８ｂは、Ｂサブフレーム期間の残部で発光する。 For pixel circuits in the k-th group (k is an integer not less than 2 and not more than (n / 3)), after completion of writing of the data potential to the pixel circuits in the (k−1) -th group, the R subframe period and the G subframe period And B subframe periods are set in order. At the beginning of each subframe period, initialization, threshold compensation, and data potential writing are performed on the pixel circuits of the kth group. The organic EL elements 18r in the k-th group of pixel circuits emit light in the remainder of the R subframe period. The organic EL elements 18g in the k-th group of pixel circuits emit light in the remainder of the G subframe period. The organic EL elements 18b in the k-th group of pixel circuits emit light in the remainder of the B subframe period.
　画素回路１０を図５に示すタイミングで動作させるために、表示装置１００では、走査線Ｇｉは３行の画素回路１０に対応して１本ずつ設けられ、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊは画素回路１０の各列に対応して３本ずつ設けられる。走査線駆動回路２は、走査線Ｇｉを１本ずつ順に選択することにより、３行の画素回路１０を順に選択する。データ線駆動回路３は、走査線駆動回路２によって選択された３行の画素回路１０に書き込むデータ電位をデータ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊに印加する。画素回路１０は３個の有機ＥＬ素子を含み、走査線駆動回路２とデータ線駆動回路３は１フレーム期間を３個のサブフレーム期間に分割する。 In order to operate the pixel circuit 10 at the timing shown in FIG. 5, in the display device 100, one scanning line Gi is provided corresponding to each of the three rows of pixel circuits 10, and the data lines S1j, S2j, and S3j are pixel circuits. Three are provided corresponding to each of the ten columns. The scanning line driving circuit 2 sequentially selects the pixel circuits 10 in three rows by sequentially selecting the scanning lines Gi one by one. The data line driving circuit 3 applies data potentials to be written to the three rows of pixel circuits 10 selected by the scanning line driving circuit 2 to the data lines S1j, S2j, and S3j. The pixel circuit 10 includes three organic EL elements, and the scanning line driving circuit 2 and the data line driving circuit 3 divide one frame period into three subframe periods.
　図６は、画素回路１０のタイミングチャートである。図６には、列方向に隣接する３個の画素回路Ａｉｊ、Ａｉ＋１ｊ、Ａｉ＋２ｊに接続される９本の信号線の電位の変化が記載されている。以下、走査線Ｇｉの電位がローレベルである期間を走査線Ｇｉの選択期間といい、制御線ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉの電位がローレベルである期間を、それぞれ、Ｒ発光期間、Ｇ発光期間およびＢ発光期間という。図６を参照して、画素回路Ａｉｊの動作を説明する。 FIG. 6 is a timing chart of the pixel circuit 10. FIG. 6 shows changes in potentials of nine signal lines connected to three pixel circuits Aij, Ai + 1j, and Ai + 2j adjacent in the column direction. Hereinafter, a period in which the potential of the scanning line Gi is at a low level is referred to as a selection period of the scanning line Gi, and a period in which the potentials of the control lines EMRi, EMGi, and EMBi are at a low level are R emission period, G emission period, and This is called the B light emission period. The operation of the pixel circuit Aij will be described with reference to FIG.
　時刻ｔ１より前では、走査線Ｇｉおよび制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉの電位はハイレベルである。このため、ＴＦＴ１２～１５、１６ｒ、１６ｇ、１６ｂはすべてオフ状態である。時刻ｔ１において、制御線ＧＩＮＩｉの電位がローレベルに変化する。このため、ＴＦＴ１４はオン状態になる。これにより、ＴＦＴ１１のゲート電位はＶｉｎｉに初期化される。 Prior to time t1, the potentials of the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi are at a high level. For this reason, the TFTs 12 to 15, 16r, 16g, and 16b are all turned off. At time t1, the potential of the control line GINIi changes to a low level. For this reason, the TFT 14 is turned on. As a result, the gate potential of the TFT 11 is initialized to Vini.
　時刻ｔ２において、制御線ＧＩＮＩｉの電位はハイレベルに変化し、走査線Ｇｉの電位がローレベルに変化する。このため、ＴＦＴ１４はオフ状態になり、ＴＦＴ１２、１５はオン状態になる。走査線Ｇｉの選択期間では、データ線Ｓ１ｊにデータ電位ＶＲｉｊが印加される。このため、ＴＦＴ１１のソース電位はＶＲｉｊになり、ＴＦＴ１１はオン状態になる。ＴＦＴ１１がオン状態である間、ＴＦＴ１１、１２を通過する電流が流れ、ＴＦＴ１１のゲート電位は上昇する。ＴＦＴ１１の閾値電圧をＶｔｈとすると、ＴＦＴ１１のゲート電位は（ＶＲｉｊ－Ｖｔｈ）まで上昇する。時刻ｔ３において、走査線Ｇｉの電位はハイレベルに変化する。このため、ＴＦＴ１２、１５はオフ状態になる。このときコンデンサ１７には、電位差（ＥＬＶＤＤ－ＶＲｉｊ＋Ｖｔｈ）が保持される。 At time t2, the potential of the control line GINIi changes to a high level, and the potential of the scanning line Gi changes to a low level. For this reason, the TFT 14 is turned off, and the TFTs 12 and 15 are turned on. In the selection period of the scanning line Gi, the data potential VRij is applied to the data line S1j. For this reason, the source potential of the TFT 11 becomes VRij, and the TFT 11 is turned on. While the TFT 11 is in the ON state, a current passing through the TFTs 11 and 12 flows, and the gate potential of the TFT 11 rises. When the threshold voltage of the TFT 11 is Vth, the gate potential of the TFT 11 rises to (VRij−Vth). At time t3, the potential of the scanning line Gi changes to a high level. For this reason, the TFTs 12 and 15 are turned off. At this time, the potential difference (ELVDD−VRij + Vth) is held in the capacitor 17.
　時刻ｔ４において、制御線ＥＭｉ、ＥＭＲｉの電位がローレベルに変化する。Ｒ発光期間では、ＴＦＴ１３、１６ｒがオン状態になる。また、ＴＦＴ１１のゲート－ソース間には、コンデンサ１７に保持された電位差（ＥＬＶＤＤ－ＶＲｉｊ＋Ｖｔｈ）が印加される。Ｒ発光期間にＴＦＴ１１を通過する電流Ｉｒは、ＴＦＴ１１のゲート－ソース間の電位差Ｖｇｓと比例定数ｋを用いて、次式（１）で表される。
　　Ｉｒ＝ｋ（Ｖｇｓ－Ｖｔｈ）2   …（１）
　Ｖｇｓ＝ＥＬＶＤＤ－ＶＲｉｊ＋Ｖｔｈより、次式（２）が導かれる。
　　Ｉｒ＝ｋ（ＥＬＶＤＤ－ＶＲｉｊ）2   …（２） At time t4, the potentials of the control lines EMi and EMRi change to a low level. In the R light emission period, the TFTs 13 and 16r are turned on. Further, a potential difference (ELVDD−VRij + Vth) held in the capacitor 17 is applied between the gate and source of the TFT 11. The current Ir passing through the TFT 11 during the R emission period is expressed by the following equation (1) using the potential difference Vgs between the gate and source of the TFT 11 and the proportionality constant k.
Ir = k (Vgs−Vth) 2 (1)
From Vgs = ELVDD−VRij + Vth, the following equation (2) is derived.
Ir = k (ELVDD−VRij) 2 (2)
　式（２）で示す電流Ｉｒは、データ電位ＶＲｉｊに応じて変化するが、ＴＦＴ１１の閾値電圧Ｖｔｈには依存しない。したがって、閾値電圧Ｖｔｈにばらつきがある場合や、閾値電圧Ｖｔｈが経時的に変化する場合でも、閾値電圧Ｖｔｈに依存しない電流を有機ＥＬ素子１８ｒに流して、有機ＥＬ素子１８ｒを所望の輝度で発光させることができる。 The current Ir shown in the equation (2) changes according to the data potential VRij, but does not depend on the threshold voltage Vth of the TFT 11. Therefore, even when the threshold voltage Vth varies or when the threshold voltage Vth changes over time, a current that does not depend on the threshold voltage Vth is caused to flow through the organic EL element 18r, and the organic EL element 18r emits light with a desired luminance. Can be made.
　時刻ｔ５において、制御線ＥＭｉ、ＥＭＲｉの電位はハイレベルに変化する。このため、ＴＦＴ１３、１６ｒはオフ状態になる。Ｇサブフレーム期間とＢサブフレーム期間において、画素回路ＡｉｊはＲサブフレーム期間と同様に動作する。Ｇサブフレーム期間内の走査線Ｇｉの選択期間ではデータ線Ｓ１ｊにデータ電位ＶＧｉｊが印加され、Ｇ発光期間では有機ＥＬ素子１８ｇがデータ電位ＶＧｉｊに応じた輝度で発光する。Ｂサブフレーム期間内の走査線Ｇｉの選択期間ではデータ線Ｓ１ｊにデータ電位ＶＢｉｊが印加され、Ｂ発光期間では有機ＥＬ素子１８ｂがデータ電位ＶＢｉｊに応じた輝度で発光する。 At time t5, the potentials of the control lines EMi and EMRi change to high level. Therefore, the TFTs 13 and 16r are turned off. In the G subframe period and the B subframe period, the pixel circuit Aij operates in the same manner as in the R subframe period. The data potential VGij is applied to the data line S1j during the selection period of the scanning line Gi within the G subframe period, and the organic EL element 18g emits light with luminance corresponding to the data potential VGij during the G light emission period. The data potential VBij is applied to the data line S1j during the selection period of the scanning line Gi within the B subframe period, and the organic EL element 18b emits light with luminance corresponding to the data potential VBij during the B light emission period.
　画素回路Ａｉ＋１ｊ、Ａｉ＋２ｊは、画素回路Ａｉｊと並列に、画素回路Ａｉｊと同様に動作する。Ｒサブフレーム期間内の走査線Ｇｉの選択期間では、データ線Ｓ２ｊ、Ｓ３ｊにデータ電位ＶＲｉ＋１ｊ、ＶＲｉ＋２ｊがそれぞれ印加される。Ｒ発光期間では、画素回路Ａｉ＋１ｊ内の有機ＥＬ素子１８ｒがデータ電位ＶＲｉ＋１ｊに応じた輝度で発光し、画素回路Ａｉ＋２ｊ内の有機ＥＬ素子１８ｒがデータ電位ＶＲｉ＋２ｊに応じた輝度で発光する。Ｇサブフレーム期間内の走査線Ｇｉの選択期間では、データ線Ｓ２ｊ、Ｓ３ｊにデータ電位ＶＧｉ＋１ｊ、ＶＧｉ＋２ｊがそれぞれ印加される。Ｇ発光期間では、画素回路Ａｉ＋１ｊ内の有機ＥＬ素子１８ｇがデータ電位ＶＧｉ＋１ｊに応じた輝度で発光し、画素回路Ａｉ＋２ｊ内の有機ＥＬ素子１８ｇがデータ電位ＶＧｉ＋２ｊに応じた輝度で発光する。Ｂサブフレーム期間内の走査線Ｇｉの選択期間では、データ線Ｓ２ｊ、Ｓ３ｊにデータ電位ＶＢｉ＋１ｊ、ＶＢｉ＋２ｊがそれぞれ印加される。Ｂ発光期間では、画素回路Ａｉ＋１ｊ内の有機ＥＬ素子１８ｂがデータ電位ＶＢｉ＋１ｊに応じた輝度で発光し、画素回路Ａｉ＋２ｊ内の有機ＥＬ素子１８ｂがデータ電位ＶＢｉ＋２ｊに応じた輝度で発光する。 The pixel circuits Ai + 1j and Ai + 2j operate in the same manner as the pixel circuit Aij in parallel with the pixel circuit Aij. In the selection period of the scanning line Gi in the R subframe period, the data potentials VRi + 1j and VRi + 2j are applied to the data lines S2j and S3j, respectively. In the R light emission period, the organic EL element 18r in the pixel circuit Ai + 1j emits light with a luminance corresponding to the data potential VRi + 1j, and the organic EL element 18r in the pixel circuit Ai + 2j emits light with a luminance corresponding to the data potential VRi + 2j. In the selection period of the scanning line Gi within the G subframe period, the data potentials VGi + 1j and VGi + 2j are applied to the data lines S2j and S3j, respectively. In the G light emission period, the organic EL element 18g in the pixel circuit Ai + 1j emits light with a luminance corresponding to the data potential VGi + 1j, and the organic EL element 18g in the pixel circuit Ai + 2j emits light with a luminance corresponding to the data potential VGi + 2j. In the selection period of the scanning line Gi within the B subframe period, the data potentials VBi + 1j and VBi + 2j are applied to the data lines S2j and S3j, respectively. In the B light emission period, the organic EL element 18b in the pixel circuit Ai + 1j emits light with a luminance corresponding to the data potential VBi + 1j, and the organic EL element 18b in the pixel circuit Ai + 2j emits light with a luminance corresponding to the data potential VBi + 2j.
　以下、本実施形態に係る表示装置１００と、特許文献１に記載された表示装置（以下、従来の表示装置という）とを比較する。ただし、比較を容易に行うために、従来の表示装置はＲＧＢ３色を用いてカラー表示を行い、従来の表示装置では走査信号ｓｃａｎ［ｎ］、ｓｃａｎ［ｎ－１］を２個の信号として扱うこととした。 Hereinafter, the display device 100 according to the present embodiment is compared with the display device described in Patent Document 1 (hereinafter referred to as a conventional display device). However, for easy comparison, the conventional display device performs color display using three colors of RGB, and the conventional display device handles the scan signals scan [n] and scan [n−1] as two signals. It was decided.
　従来の表示装置では、１カラー画素について１８個のＴＦＴと３個のコンデンサが必要になる。これに対して表示装置１００では、１カラー画素について８個のＴＦＴと１個のコンデンサで済む。このように表示装置１００によれば、３個の有機ＥＬ素子に対応して１個の発光素子駆動部を設けることにより、複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。 In the conventional display device, 18 TFTs and 3 capacitors are required for one color pixel. On the other hand, in the display device 100, eight TFTs and one capacitor are sufficient for one color pixel. As described above, according to the display device 100, by providing one light-emitting element driving unit corresponding to three organic EL elements, the elements are shared among the plurality of sub-pixels, and the number of elements in the pixel circuit is reduced. Can be reduced.
　また、従来の表示装置では、１個のカラー画素について走査線と制御線が合わせて３本、データ線が１本必要になる。これに対して表示装置１００では、３個のカラー画素について走査線と制御線が合わせて６本、データ線が３本必要になる。このように表示装置１００によれば、従来の表示装置と比べて走査線の本数を削減することができる。 In addition, in the conventional display device, three color lines and one data line are required for one color pixel in total. On the other hand, the display device 100 requires six scanning lines and three control lines and three data lines for three color pixels. Thus, according to the display device 100, the number of scanning lines can be reduced as compared with the conventional display device.
　表示装置１００は、１フレーム期間に３回、各画素回路１０にデータ電位を書き込む。このため、表示装置１００では、１フレーム期間あたりのデータ電位の書き込み回数は、従来の表示装置の３倍になる。ところが、表示装置１００は、３行の画素回路１０に対してデータ電位を並列に書き込む。したがって、表示装置１００の走査速度は、従来の表示装置と同じになる。ただし、表示装置１００では、発光期間の長さは従来の表示装置の１／３になる。 The display device 100 writes the data potential to each pixel circuit 10 three times in one frame period. For this reason, in the display device 100, the number of data potentials written per frame period is three times that of a conventional display device. However, the display device 100 writes data potentials in parallel to the pixel circuits 10 in three rows. Therefore, the scanning speed of the display device 100 is the same as that of the conventional display device. However, in the display device 100, the length of the light emission period is 1/3 that of the conventional display device.
　以上に示すように、本実施形態に係る表示装置１００は、（ｍ×ｎ）個の画素回路１０、（ｎ／３）本の走査線、（５ｎ／３）本の制御線、３ｍ本のデータ線、走査線駆動回路２、および、データ線駆動回路３を備えている。画素回路１０は、３個の発光素子（有機ＥＬ素子）と、駆動用トランジスタ（ＴＦＴ１１）を通過した電流を制御線の電位に基づき３個の発光素子のいずれかに流す発光素子駆動部を含む。走査線駆動回路２とデータ線駆動回路３は、１フレーム期間を３分割して得られたサブフレーム期間のそれぞれにおいて（ｍ×ｎ）個の画素回路１０にデータ電位を書き込み、サブフレーム期間ごとに駆動用トランジスタを通過した電流の経路を切り替える。走査線駆動回路２とデータ線駆動回路３は、３行の画素回路に対してデータ電位を並列に書き込む。走査線は３行の画素回路１０に対応して１本ずつ設けられ、データ線は画素回路１０の各列に対応して３本ずつ設けられる。走査線駆動回路２は、走査線を１本ずつ順に選択することにより、３行の画素回路１０を順に選択する。データ線駆動回路３は、走査線駆動回路２によって選択された３行の画素回路１０に書き込むデータ電位をデータ線に印加する。 As described above, the display device 100 according to this embodiment includes (m × n) pixel circuits 10, (n / 3) scanning lines, (5n / 3) control lines, 3m lines. A data line, a scanning line driving circuit 2 and a data line driving circuit 3 are provided. The pixel circuit 10 includes three light emitting elements (organic EL elements) and a light emitting element driving unit that causes a current that has passed through the driving transistor (TFT 11) to flow to one of the three light emitting elements based on the potential of the control line. . The scanning line driving circuit 2 and the data line driving circuit 3 write data potentials to the (m × n) pixel circuits 10 in each subframe period obtained by dividing one frame period into three, and each subframe period. The path of the current that has passed through the driving transistor is switched. The scanning line driving circuit 2 and the data line driving circuit 3 write data potentials in parallel to the pixel circuits in three rows. One scanning line is provided corresponding to each pixel circuit 10 in three rows, and three data lines are provided corresponding to each column of the pixel circuits 10. The scanning line driving circuit 2 sequentially selects the pixel circuits 10 in three rows by sequentially selecting the scanning lines one by one. The data line driving circuit 3 applies a data potential to be written to the three rows of pixel circuits 10 selected by the scanning line driving circuit 2 to the data lines.
　このように複数の発光素子に対応して１個の発光素子駆動部を設けることにより、複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。また、複数の画素回路に対してデータ電位を並列に書き込むことにより、走査速度の増加を抑制することができる。したがって、走査速度の増加を抑制しながら、複数のサブ画素間で素子を共有して画素回路内の素子数を削減した表示装置を提供することができる。 Thus, by providing one light emitting element driving unit corresponding to a plurality of light emitting elements, the elements can be shared among the plurality of subpixels, and the number of elements in the pixel circuit can be reduced. In addition, writing data potentials in parallel to a plurality of pixel circuits can suppress an increase in scanning speed. Therefore, it is possible to provide a display device in which the number of elements in the pixel circuit is reduced by sharing elements among a plurality of sub-pixels while suppressing an increase in scanning speed.
　特に、ｐ行（ここでは、３行）の画素回路に対応して１本の走査線を設け、画素回路の各列に対応してｐ本のデータ線を設けることにより、ｐ行の画素回路に対して並列に書き込みを行うことができる。したがって、画素回路に対して１行ずつ書き込みを行う場合と比べて、走査速度を１／ｐ（ここでは、１／３）にすることができる。 In particular, by providing one scanning line corresponding to the pixel circuit of p rows (here, 3 rows) and providing p data lines corresponding to each column of the pixel circuit, the pixel circuit of p rows Can be written in parallel. Therefore, the scanning speed can be reduced to 1 / p (here, 1/3) as compared with the case where writing is performed row by row to the pixel circuit.
　また、ｑ個（ここでは、３個）の発光素子に対応して発光素子駆動部を設けることにより、ｑ個のサブ画素間で素子を共有し、素子を共有しない場合と比べて画素回路内の素子数を最も好ましい場合には約（１／ｑ）に削減することができる。表示装置１００では、１個のカラー画素に必要なＴＦＴの個数を従来の表示装置と比べて４／９に削減することができる。また、特段の工夫を行うことなくｑ個のサブ画素間で素子を共有すると、走査速度がｑ倍になる。そこで、ｐ行の画素回路に対してデータ電位を並列に書き込むことにより、素子を共有せず、画素回路に対して１行ずつ書き込みを行う場合と比べて、走査速度を（ｑ／ｐ）倍に抑制することができる。表示装置１００ではｐとｑが等しいので、走査速度を変化させずに、３個のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 Further, by providing a light emitting element driving unit corresponding to q (here, three) light emitting elements, the elements are shared among the q subpixels, and compared with the case where the elements are not shared, in the pixel circuit. In the most preferable case, the number of elements can be reduced to about (1 / q). In the display device 100, the number of TFTs required for one color pixel can be reduced to 4/9 compared with the conventional display device. In addition, if the elements are shared among the q sub-pixels without special measures, the scanning speed is increased q times. Therefore, by writing data potentials in parallel to the pixel circuit in the p row, the scanning speed is (q / p) times as compared with the case where writing is performed row by row in the pixel circuit without sharing the elements. Can be suppressed. Since p and q are equal in the display device 100, the number of elements in the pixel circuit can be reduced by sharing elements among the three sub-pixels without changing the scanning speed.
　また、画素回路１０は、赤色に発光する発光素子、緑色に発光する発光素子、および、青色に発光する発光素子を１個ずつ含む。これら３個の発光素子は、表示画面内で行方向に並び、１個のカラー画素を構成する３個のサブ画素に対応する。このように１個のカラー画素を構成する複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。 The pixel circuit 10 includes one light emitting element that emits red light, one light emitting element that emits green light, and one light emitting element that emits blue light. These three light emitting elements are aligned in the row direction in the display screen, and correspond to three sub-pixels constituting one color pixel. In this manner, elements can be shared among a plurality of sub-pixels constituting one color pixel, and the number of elements in the pixel circuit can be reduced.
　（第１の実施形態の変形例）
　第１の実施形態に係る表示装置１００については、各種の変形例を構成することができる。第１変形例に係る表示装置は、６個の有機ＥＬ素子を含む画素回路を（ｍ×ｎ／２）個備えている。第１変形例に係る表示装置には、（ｎ／３）本の走査線Ｇｉ、（８ｎ／３）本の制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲ１ｉ、ＥＭＧ１ｉ、ＥＭＢ１ｉ、ＥＭＲ２ｉ、ＥＭＧ２ｉ、ＥＭＢ２ｉ、および、３ｍ本のデータ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊが設けられる。 (Modification of the first embodiment)
Various modifications can be configured for the display device 100 according to the first embodiment. The display device according to the first modification includes (m × n / 2) pixel circuits including six organic EL elements. The display device according to the first modification includes (n / 3) scanning lines Gi, (8n / 3) control lines GINIi, EMi, EMR1i, EMG1i, EMB1i, EMR2i, EMG2i, EMB2i, and 3m. Two data lines S1j, S2j, S3j are provided.
　図７は、第１変形例に係る表示装置における画素回路の接続形態を示す図である。図７には、列方向に隣接した３個の画素回路２０の接続形態が記載されている。画素回路２０は、行方向に隣接する２個のカラー画素に対応する。３個の画素回路２０は、いずれも、走査線Ｇｉと制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲ１ｉ、ＥＭＧ１ｉ、ＥＭＢ１ｉ、ＥＭＲ２ｉ、ＥＭＧ２ｉ、ＥＭＢ２ｉに接続される。また、３個の画素回路２０は、それぞれ、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊに接続される。データ線Ｓ１ｊに接続された画素回路１０は、第ｉ行第ｊ列のカラー画素と第ｉ行第（ｊ＋１）列のカラー画素に対応する。データ線Ｓ２ｊに接続された画素回路１０は、第（ｉ＋１）行第ｊ列のカラー画素と第（ｉ＋１）行第（ｊ＋１）列のカラー画素に対応する。データ線Ｓ３ｊに接続された画素回路１０は、第（ｉ＋２）行第ｊ列のカラー画素と第（ｉ＋２）行第（ｊ＋１）列のカラー画素に対応する。 FIG. 7 is a diagram illustrating a connection form of pixel circuits in the display device according to the first modification. FIG. 7 shows a connection form of three pixel circuits 20 adjacent in the column direction. The pixel circuit 20 corresponds to two color pixels adjacent in the row direction. All of the three pixel circuits 20 are connected to the scanning line Gi and the control lines GINIi, EMi, EMR1i, EMG1i, EMB1i, EMR2i, EMG2i, and EMB2i. The three pixel circuits 20 are connected to data lines S1j, S2j, and S3j, respectively. The pixel circuit 10 connected to the data line S1j corresponds to the color pixel in the i-th row and j-th column and the color pixel in the i-th row (j + 1) -th column. The pixel circuit 10 connected to the data line S2j corresponds to the color pixel in the (i + 1) th row and the jth column and the color pixel in the (i + 1) th row and the (j + 1) th column. The pixel circuit 10 connected to the data line S3j corresponds to the color pixel of the (i + 2) th row and the jth column and the color pixel of the (i + 2) th row and the (j + 1) th column.
　図８は、画素回路２０の回路図である。画素回路２０は、画素回路１０（図４）にＴＦＴ２１ｒ、２１ｇ、２１ｂと有機ＥＬ素子２２ｒ、２２ｇ、２２ｂを追加したものである。ＴＦＴ２１ｒ、２１ｇ、２１ｂと有機ＥＬ素子２２ｒ、２２ｇ、２２ｂは、ＴＦＴ１６ｒおよび有機ＥＬ素子１８ｒと同様の形態に接続される。ＴＦＴ１６ｒ、１６ｇ、１６ｂ、２１ｒ、２１ｇ、２１ｂのゲートは、それぞれ、制御線ＥＭＲ１ｉ、ＥＭＧ１ｉ、ＥＭＢ１ｉ、ＥＭＲ２ｉ、ＥＭＧ２ｉ、ＥＭＢ２ｉに接続される。 FIG. 8 is a circuit diagram of the pixel circuit 20. The pixel circuit 20 is obtained by adding TFTs 21r, 21g, and 21b and organic EL elements 22r, 22g, and 22b to the pixel circuit 10 (FIG. 4). The TFTs 21r, 21g, and 21b and the organic EL elements 22r, 22g, and 22b are connected in the same form as the TFT 16r and the organic EL element 18r. The gates of the TFTs 16r, 16g, 16b, 21r, 21g, and 21b are connected to control lines EMR1i, EMG1i, EMB1i, EMR2i, EMG2i, and EMB2i, respectively.
　第１変形例に係る表示装置では、１フレーム期間は６個のサブフレーム期間に分割される。走査線駆動回路とデータ線駆動回路は、３行の画素回路に対する初期化、閾値検出および書き込みを並列に行う。 In the display device according to the first modification, one frame period is divided into six subframe periods. The scanning line driving circuit and the data line driving circuit perform initialization, threshold value detection, and writing for the pixel circuits in three rows in parallel.
　第１変形例に係る表示装置では、素子を共有しない場合と比べて、データ線の本数を１／２に削減することができる。一方、発光期間の長さは１フレーム期間の１／６になり、走査速度は素子を共有しない場合と比べて２倍になる。このようにｑ個の発光素子に対応して発光素子駆動部を設け、ｐ行の画素回路に対してデータ電位を並列に書き込む表示装置において、ｐの値（ここでは、３）をｑの値（ここでは、６）よりも小さくした場合、走査速度の増加を（ｑ／ｐ）倍（ここでは、２倍）に抑制しながら、ｑ個のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 In the display device according to the first modification, the number of data lines can be reduced to ½ compared to the case where the elements are not shared. On the other hand, the length of the light emission period is 1/6 of one frame period, and the scanning speed is doubled compared to the case where the elements are not shared. Thus, in the display device in which the light emitting element driving unit is provided corresponding to the q light emitting elements and the data potential is written in parallel to the pixel circuit in the p row, the value of p (here, 3) is set to the value of q. If it is smaller than (here, 6), the increase in scanning speed is suppressed to (q / p) times (here, 2 times), while the elements are shared among the q sub-pixels, and within the pixel circuit. The number of elements can be reduced.
　また、画素回路２０は、赤色に発光する発光素子、緑色に発光する発光素子、および、青色に発光する発光素子を２個ずつ含む。これら６個の発光素子は、表示画面内で行方向に並び、２個のカラー画素を構成する６個のサブ画素に対応する。このように複数のカラー画素を構成する複数のサブ画素間で素子を共有し、画素回路内の素子数を削減することができる。 The pixel circuit 20 includes two light emitting elements that emit red light, two light emitting elements that emit green light, and two light emitting elements that emit blue light. These six light emitting elements are aligned in the row direction in the display screen and correspond to six sub-pixels constituting two color pixels. In this manner, elements can be shared among a plurality of sub-pixels constituting a plurality of color pixels, and the number of elements in the pixel circuit can be reduced.
　第２変形例に係る表示装置は、６行の画素回路に対する初期化、閾値検出および書き込みを並列に行う。第２変形例に係る表示装置には、（ｎ／６）本の走査線Ｇｉ（ただし、本変形例では、ｉは１、７、…、ｎ－１１、ｎ－５のうちのいずれかの数）、（５ｎ／６）本の制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉ、および、６ｍ本のデータ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊ、Ｓ４ｊ、Ｓ５ｊ、Ｓ６ｊが設けられる。 The display device according to the second modification performs initialization, threshold value detection, and writing for the pixel circuits in six rows in parallel. The display device according to the second modification includes (n / 6) scanning lines Gi (in this modification, i is one of 1, 7,..., N-11, n-5). Number), (5n / 6) control lines GINIi, EMi, EMRi, EMGi, EMBi, and 6m data lines S1j, S2j, S3j, S4j, S5j, S6j.
　図９は、第２変形例に係る表示装置における画素回路の接続形態を示す図である。図９には、列方向に隣接した６個の画素回路１０の接続形態が記載されている。６個の画素回路１０は、いずれも、走査線Ｇｉと制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉに接続される。また、６個の画素回路１０は、それぞれ、データ線Ｓ１ｊ～Ｓ６ｊに接続される。データ線Ｓ１ｊに接続された画素回路１０は、第ｉ行第ｊ列のカラー画素に対応する。データ線Ｓ２ｊに接続された画素回路１０は、第（ｉ＋１）行第ｊ列のカラー画素に対応する。データ線Ｓ３ｊに接続された画素回路１０は、第（ｉ＋２）行第ｊ列のカラー画素に対応する。データ線Ｓ４ｊに接続された画素回路１０は、第（ｉ＋３）行第ｊ列のカラー画素に対応する。データ線Ｓ５ｊに接続された画素回路１０は、第（ｉ＋４）行第ｊ列のカラー画素に対応する。データ線Ｓ６ｊに接続された画素回路１０は、第（ｉ＋５）行第ｊ列のカラー画素に対応する。 FIG. 9 is a diagram illustrating a connection form of pixel circuits in the display device according to the second modification. FIG. 9 shows a connection form of six pixel circuits 10 adjacent in the column direction. Each of the six pixel circuits 10 is connected to the scanning line Gi and the control lines GINIi, EMi, EMRi, EMGi, and EMBi. The six pixel circuits 10 are connected to the data lines S1j to S6j, respectively. The pixel circuit 10 connected to the data line S1j corresponds to the color pixel in the i-th row and the j-th column. The pixel circuit 10 connected to the data line S2j corresponds to the color pixel of the (i + 1) th row and the jth column. The pixel circuit 10 connected to the data line S3j corresponds to the color pixel in the (i + 2) th row and the jth column. The pixel circuit 10 connected to the data line S4j corresponds to the color pixel in the (i + 3) th row and the jth column. The pixel circuit 10 connected to the data line S5j corresponds to the color pixel in the (i + 4) th row and the jth column. The pixel circuit 10 connected to the data line S6j corresponds to the color pixel in the (i + 5) th row and the jth column.
　第２変形例に係る表示装置では、１フレーム期間は３個のサブフレーム期間に分割される。走査線駆動回路とデータ線駆動回路は、６行の画素回路に対する初期化、閾値検出および書き込みを並列に行う。 In the display device according to the second modification, one frame period is divided into three subframe periods. The scanning line driving circuit and the data line driving circuit perform initialization, threshold value detection, and writing for the pixel circuits in six rows in parallel.
　第２変形例に係る表示装置では、素子を共有しない場合と比べて、データ線の本数は２倍になる。一方、走査速度は、素子を共有しない場合と比べて１／２になる。あるいは、素子を共有しない場合と比べて走査速度を変更せずに、発光期間の長さを伸ばすことができる。このようにｑ個の発光素子に対応して発光素子駆動部を設け、ｐ行の画素回路に対してデータ電位を並列に書き込む表示装置において、ｐの値（ここでは、６）をｑの値（ここでは、３）よりも大きくした場合、走査速度の増加を（ｑ／ｐ）倍（ここでは、１／２倍）に削減しながら、ｑ個のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 In the display device according to the second modification, the number of data lines is doubled compared to the case where the elements are not shared. On the other hand, the scanning speed is ½ compared to the case where the elements are not shared. Alternatively, the length of the light emission period can be extended without changing the scanning speed as compared with the case where the elements are not shared. Thus, in the display device in which the light emitting element driving unit is provided corresponding to q light emitting elements and the data potential is written in parallel to the pixel circuit in the p row, the value of p (here, 6) is changed to the value of q. When the pixel size is larger than (here, 3), the pixel is shared between the q sub-pixels while reducing the increase in scanning speed by (q / p) times (here, 1/2 times). The number of elements in the circuit can be reduced.
　第３変形例に係る表示装置は、各サブフレーム期間において複数の発光素子を発光させる。例えば、１フレーム期間を第１～第３サブフレーム期間に分割したとき、第１サブフレーム期間では、第１行～第３行の画素回路１０内の有機ＥＬ素子１８ｒと、第４行～第６行の画素回路１０内の有機ＥＬ素子１８ｇと、第７行～第９行の画素回路内の有機ＥＬ素子１８ｂとが発光する。第２サブフレーム期間では、第１行～第３行の画素回路１０内の有機ＥＬ素子１８ｇと、第４行～第６行の画素回路１０内の有機ＥＬ素子１８ｂと、第７行～第９行の画素回路内の有機ＥＬ素子１８ｒとが発光する。第３サブフレーム期間では、第１行～第３行の画素回路１０内の有機ＥＬ素子１８ｂと、第４行～第６行の画素回路１０内の有機ＥＬ素子１８ｒと、第７行～第９行の画素回路内の有機ＥＬ素子１８ｇとが発光する。第３変形例に係る表示装置によれば、各サブフレーム期間において発光色が特定の色に偏ることを防止し、表示画面のちらつきや動画表示の際の色割れを減らすことができる。 The display device according to the third modification causes a plurality of light emitting elements to emit light in each subframe period. For example, when one frame period is divided into first to third subframe periods, in the first subframe period, the organic EL elements 18r in the pixel circuits 10 in the first to third rows and the fourth to fourth subframe periods are used. The organic EL elements 18g in the pixel circuits 10 in the six rows and the organic EL elements 18b in the pixel circuits in the seventh to ninth rows emit light. In the second sub-frame period, the organic EL elements 18g in the pixel circuits 10 in the first to third rows, the organic EL elements 18b in the pixel circuits 10 in the fourth to sixth rows, and the seventh to sixth rows. The organic EL elements 18r in the 9-row pixel circuits emit light. In the third subframe period, the organic EL elements 18b in the pixel circuits 10 in the first to third rows, the organic EL elements 18r in the pixel circuits 10 in the fourth to sixth rows, and the seventh to sixth rows. The organic EL elements 18g in the 9-row pixel circuits emit light. According to the display device according to the third modification, it is possible to prevent the emission color from being biased to a specific color in each subframe period, and to reduce flickering of the display screen and color breakup during moving image display.
　（第２の実施形態）
　本発明の第２の実施形態に係る表示装置は、第１の実施形態と同じ構成（図１）を有し、同じ画素回路１０（図４）を備えている。本実施形態に係る表示装置における表示画面内のサブ画素の配置は、第１の実施形態（図２）と同じである。本実施形態と第１の実施形態では、画素回路内の有機ＥＬ素子がいずれのサブ画素に対応するかが相違する。以下、第１の実施形態との相違点を説明する。 (Second Embodiment)
The display device according to the second embodiment of the present invention has the same configuration (FIG. 1) as that of the first embodiment, and includes the same pixel circuit 10 (FIG. 4). The arrangement of the sub-pixels in the display screen in the display device according to the present embodiment is the same as that in the first embodiment (FIG. 2). This embodiment is different from the first embodiment in which sub-pixel the organic EL element in the pixel circuit corresponds to. Hereinafter, differences from the first embodiment will be described.
　図１０は、第２の実施形態に係る表示装置における画素回路１０の接続形態を示す図である。図１０に示す３個の画素回路１０の接続形態は、第１の実施形態（図３）と同じである。ただし、本実施形態では、画素回路１０に含まれる３個の有機ＥＬ素子は、同じ色に発光し、表示画面内で列方向に並んだ３個のカラー画素に含まれる同じ色のサブ画素に対応する。具体的には、データ線Ｓ１ｊに接続された画素回路１０内の３個の有機ＥＬ素子は、いずれも赤色に発光し、第ｉ行第ｊ列、第（ｉ＋１）行第ｊ列および第（ｉ＋２）行第ｊ列のカラー画素に含まれる３個のＲサブ画素に対応する。データ線Ｓ２ｊに接続された画素回路１０内の３個の有機ＥＬ素子は、いずれも緑色に発光し、上記３個のカラー画素に含まれる３個のＧサブ画素に対応する。データ線Ｓ３ｊに接続された画素回路１０内の３個の有機ＥＬ素子は、いずれも青色に発光し、上記３個のカラー画素に含まれる３個のＢサブ画素に対応する。 FIG. 10 is a diagram showing a connection form of the pixel circuit 10 in the display device according to the second embodiment. The connection form of the three pixel circuits 10 shown in FIG. 10 is the same as that of the first embodiment (FIG. 3). However, in the present embodiment, the three organic EL elements included in the pixel circuit 10 emit light in the same color, and the same color sub-pixels included in the three color pixels arranged in the column direction in the display screen. Correspond. Specifically, each of the three organic EL elements in the pixel circuit 10 connected to the data line S1j emits red light, and the i-th row, the j-th column, the (i + 1) -th row, the j-th column, and the ( i + 2) Corresponds to three R sub-pixels included in the color pixel in the row and column j. All the three organic EL elements in the pixel circuit 10 connected to the data line S2j emit green light and correspond to the three G sub-pixels included in the three color pixels. All the three organic EL elements in the pixel circuit 10 connected to the data line S3j emit blue light and correspond to the three B sub-pixels included in the three color pixels.
　本実施形態では、画素回路１０に含まれる３個の有機ＥＬ素子は、発光素子駆動部と離れた位置に配置される場合がある。図１０に示すように、発光素子駆動部は、列方向に並べて配置される。画素回路１０に含まれる３個の有機ＥＬ素子も、列方向に並べて配置される（図２を参照）。発光素子駆動部から離れた位置に有機ＥＬ素子を配置する場合には、発光素子駆動部から引き出した配線が有機ＥＬ素子に接続される。 In the present embodiment, the three organic EL elements included in the pixel circuit 10 may be disposed at a position away from the light emitting element driving unit. As shown in FIG. 10, the light emitting element driving units are arranged side by side in the column direction. Three organic EL elements included in the pixel circuit 10 are also arranged in the column direction (see FIG. 2). In the case where the organic EL element is disposed at a position away from the light emitting element driving unit, wiring drawn from the light emitting element driving unit is connected to the organic EL element.
　以下、（ｍ×ｎ）個のカラー画素を列単位に３分割し、第１列、第４列、…にあるものを第１カラー画素、第２列、第５列、…にあるものを第２カラー画素、第３列、第６列、…にあるものを第３カラー画素という。第２の実施形態に係る表示装置では、１フレーム期間は第１～第３サブフレーム期間に分割される。第１サブフレーム期間では第１カラー画素が発光し、第２サブフレーム期間では第２カラー画素が発光し、第３サブフレーム期間では第３カラー画素が発光する。第２の実施形態に係る表示装置は、３行の画素回路に対する初期化、閾値検出および書き込みを並列に行う。 In the following, (m × n) color pixels are divided into three columns, and those in the first column, fourth column,... Are in the first color pixel, second column, fifth column,. Those in the second color pixel, third column, sixth column,... Are referred to as third color pixels. In the display device according to the second embodiment, one frame period is divided into first to third subframe periods. The first color pixel emits light in the first subframe period, the second color pixel emits light in the second subframe period, and the third color pixel emits light in the third subframe period. The display device according to the second embodiment performs initialization, threshold value detection, and writing on the pixel circuits in three rows in parallel.
　図１１は、第２の実施形態に係る表示装置における画素回路１０のタイミングチャートである。本実施形態では、第１サブフレーム期間内の走査線Ｇｉの選択期間では、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊには、それぞれ、データ電位ＶＲｉｊ、ＶＧｉｊ、ＶＢｉｊが印加される。制御線ＥＭＲｉの電位がローレベルである期間では、３個の画素回路１０は、それぞれ、データ電位ＶＲｉｊ、ＶＧｉｊ、ＶＢｉｊに応じた輝度で発光する。第２サブフレーム期間内の走査線Ｇｉの選択期間では、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊには、それぞれ、データ電位ＶＲｉ＋１ｊ、ＶＧｉ＋１ｊ、ＶＢｉ＋１ｊが印加される。制御線ＥＭＧｉの電位がローレベルである期間では、３個の画素回路１０は、それぞれ、データ電位ＶＲｉ＋１ｊ、ＶＧｉ＋１ｊ、ＶＢｉ＋１ｊに応じた輝度で発光する。第３サブフレーム期間内の走査線Ｇｉの選択期間では、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊには、それぞれ、データ電位ＶＲｉ＋２ｊ、ＶＧｉ＋２ｊ、ＶＢｉ＋２ｊが印加される。制御線ＥＭＢｉの電位がローレベルである期間では、３個の画素回路１０は、それぞれ、データ電位ＶＲｉ＋２ｊ、ＶＧｉ＋２ｊ、ＶＢｉ＋２ｊに応じた輝度で発光する。 FIG. 11 is a timing chart of the pixel circuit 10 in the display device according to the second embodiment. In the present embodiment, data potentials VRij, VGij, and VBij are applied to the data lines S1j, S2j, and S3j, respectively, during the selection period of the scanning line Gi within the first subframe period. In a period in which the potential of the control line EMRi is at a low level, the three pixel circuits 10 emit light with luminance corresponding to the data potentials VRij, VGij, and VBij, respectively. In the selection period of the scanning line Gi within the second subframe period, the data potentials VRi + 1j, VGi + 1j, and VBi + 1j are applied to the data lines S1j, S2j, and S3j, respectively. In a period in which the potential of the control line EMGi is at a low level, the three pixel circuits 10 emit light with luminance corresponding to the data potentials VRi + 1j, VGi + 1j, and VBi + 1j, respectively. In the selection period of the scanning line Gi within the third subframe period, the data potentials VRi + 2j, VGi + 2j, and VBi + 2j are applied to the data lines S1j, S2j, and S3j, respectively. In a period in which the potential of the control line EMBi is at a low level, the three pixel circuits 10 emit light with luminance corresponding to the data potentials VRi + 2j, VGi + 2j, and VBi + 2j, respectively.
　第１の実施形態に係る表示装置１００では、データ線駆動回路３は、Ｒサブフレーム期間内の走査線Ｇｉの選択期間において、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊに対してデータ電位ＶＲｉｊ、ＶＲｉ＋１ｊ、ＶＲｉ＋２ｊを印加する。このように表示装置１００のデータ線駆動回路３は、異なるカラー画素に含まれる同じ色のサブ画素に対応した３個のデータ電位を並列に出力する必要がある。 In the display device 100 according to the first embodiment, the data line driving circuit 3 uses the data potentials VRij, VRi + 1j, VRi + 2j with respect to the data lines S1j, S2j, S3j in the selection period of the scanning line Gi in the R subframe period. Apply. As described above, the data line driving circuit 3 of the display device 100 needs to output three data potentials corresponding to the sub-pixels of the same color included in different color pixels in parallel.
　これに対して、本実施形態に係る表示装置では、データ線駆動回路は、第１サブフレーム期間内の走査線Ｇｉの選択期間において、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊに対してデータ電位ＶＲｉｊ、ＶＧｉｊ、ＶＢｉｊを印加する。このように本実施形態に係る表示装置のデータ線駆動回路は、１個のカラー画素に含まれる３個のサブ画素に対応した３個のデータ電位を並列に出力すればよい。したがって、表示制御回路１においてデータ信号ＤＡの並べ替えを容易に行うことができる。 On the other hand, in the display device according to the present embodiment, the data line driving circuit has the data potentials VRij, VGij with respect to the data lines S1j, S2j, S3j in the selection period of the scanning line Gi in the first subframe period. , VBij is applied. As described above, the data line driving circuit of the display device according to the present embodiment may output three data potentials corresponding to the three sub-pixels included in one color pixel in parallel. Therefore, the display control circuit 1 can easily rearrange the data signals DA.
　また、２行の画素回路に対してデータ電位を並列に書き込む表示装置では、データ線駆動回路からのデータ電位の出力順序が、インターレース方式の映像データの出力順序に一致する。したがって、データ信号ＤＡの並べ替え用のメモリを削除したり、あるいは、メモリ量を削減したりすることができる。 In a display device in which data potentials are written in parallel to two rows of pixel circuits, the output order of data potentials from the data line driving circuit matches the output order of interlaced video data. Therefore, the memory for rearranging the data signals DA can be deleted, or the amount of memory can be reduced.
　また、本実施形態では、画素回路１０は、赤色に発光する発光素子を含む画素回路、緑色に発光する発光素子を含む画素回路、および、青色に発光する発光素子を含む画素回路のいずれかである。画素回路１０に含まれる３個の発光素子は、表示画面内で列方向に並んだ３個のカラー画素に含まれる同じ色のサブ画素に対応する。このように同じ色に対応した複数のサブ画素間で素子を供給し、画素回路内の素子数を削減することができる。 In the present embodiment, the pixel circuit 10 is any one of a pixel circuit including a light emitting element that emits red light, a pixel circuit including a light emitting element that emits green light, and a pixel circuit including a light emitting element that emits blue light. is there. The three light emitting elements included in the pixel circuit 10 correspond to sub-pixels of the same color included in the three color pixels arranged in the column direction in the display screen. In this way, elements can be supplied between a plurality of subpixels corresponding to the same color, and the number of elements in the pixel circuit can be reduced.
　（第３の実施形態）
　図１２は、本発明の第３の実施形態に係る表示装置の構成を示すブロック図である。図１２に示す表示装置３００は、第１の実施形態に係る表示装置１００（図１）において、（ｎ／３）本の制御線ＥＭｉを削除し、走査線駆動回路２と画素回路１０をそれぞれ走査線駆動回路３０１と画素回路３０に置換したものである。本実施形態の構成要素のうち第１の実施形態と同一の要素については、同一の符号を付して説明を省略する。 (Third embodiment)
FIG. 12 is a block diagram showing a configuration of a display device according to the third embodiment of the present invention. In the display device 300 shown in FIG. 12, (n / 3) control lines EMi are deleted from the display device 100 (FIG. 1) according to the first embodiment, and the scanning line driving circuit 2 and the pixel circuit 10 are respectively connected. The scanning line driving circuit 301 and the pixel circuit 30 are replaced. Among the constituent elements of this embodiment, the same elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
　走査線駆動回路３０１は、走査線駆動回路２から制御線ＥＭｉを駆動する機能を削除したものである。走査線駆動回路３０１は、（ｎ／３）本の走査線Ｇｉと（４ｎ／３）本の制御線ＧＩＮＩｉ、ＧＭＲｉ、ＧＭＧｉ、ＧＭＢｉを駆動する。 The scanning line driving circuit 301 is obtained by deleting the function of driving the control line EMi from the scanning line driving circuit 2. The scanning line driving circuit 301 drives (n / 3) scanning lines Gi and (4n / 3) control lines GINIi, GMRi, GMGi, GMBi.
　図１３は、画素回路３０の回路図である。図１３に示す画素回路３０は、画素回路１０において、Ｐ型トランジスタであるＴＦＴ１３をＮ型トランジスタであるＴＦＴ３１に置換したものである。画素回路３０では、ＴＦＴ３１のドレインには電源電位ＥＬＶＤＤが印加され、ＴＦＴ３１のソースはＴＦＴ１１のソースに接続される。ＴＦＴ３１のゲートは、ＴＦＴ１２、１５のゲートと共に、走査線Ｇｉに接続される。 FIG. 13 is a circuit diagram of the pixel circuit 30. A pixel circuit 30 shown in FIG. 13 is obtained by replacing the TFT 13 that is a P-type transistor with a TFT 31 that is an N-type transistor in the pixel circuit 10. In the pixel circuit 30, the power supply potential ELVDD is applied to the drain of the TFT 31, and the source of the TFT 31 is connected to the source of the TFT 11. The gate of the TFT 31 is connected to the scanning line Gi together with the gates of the TFTs 12 and 15.
　本実施形態に係る表示装置３００によれば、第１の実施形態に係る表示装置１００と比べて、制御線ＥＭｉを削減することができる。したがって、走査線駆動回路３０１の回路量を減らし、表示パネルの額縁面積を削減することができる。 According to the display device 300 according to the present embodiment, the control lines EMi can be reduced compared to the display device 100 according to the first embodiment. Therefore, the circuit amount of the scan line driver circuit 301 can be reduced, and the frame area of the display panel can be reduced.
　なお、第１～第３の実施形態では、ＴＦＴ１４のゲートを制御線ＧＩＮＩｉに接続し、制御線ＧＩＮＩｉは走査線Ｇｉとは別の信号線であることとした。これに代えて、ＴＦＴ１４のゲートを１つ前の走査線Ｇｉ－３に接続してもよい。これにより、（ｎ／３）本の制御線ＧＩＮＩｉを削減することができる。 In the first to third embodiments, the gate of the TFT 14 is connected to the control line GINIi, and the control line GINIi is a signal line different from the scanning line Gi. Alternatively, the gate of the TFT 14 may be connected to the previous scanning line Gi-3. Thereby, (n / 3) control lines GINIi can be reduced.
　（第４の実施形態）
　図１４は、本発明の第４の実施形態に係る表示装置の構成を示すブロック図である。図１４に示す表示装置４００は、第１の実施形態に係る表示装置１００（図１）において、走査線駆動回路２と画素回路１０をそれぞれ走査線駆動回路４０１と画素回路４０に置換し、（ｎ／３）本の走査線Ｇｉを（ｎ／３）本の走査線Ｇ１ｉに置換し、（５ｎ／３）本の制御線ＧＩＮＩｉ、ＥＭｉ、ＥＭＲｉ、ＥＭＧｉ、ＥＭＢｉを２ｎ本の制御線Ｇ２ｉ、Ｇ３ｉ、Ｇ４ｉ、Ｇ５Ｒｉ、Ｇ５Ｇｉ、Ｇ５Ｂｉに置換したものである。本実施形態の構成要素のうち第１の実施形態と同一の要素については、同一の符号を付して説明を省略する。 (Fourth embodiment)
FIG. 14 is a block diagram showing a configuration of a display device according to the fourth embodiment of the present invention. 14 replaces the scanning line driving circuit 2 and the pixel circuit 10 with the scanning line driving circuit 401 and the pixel circuit 40, respectively, in the display device 100 (FIG. 1) according to the first embodiment. n / 3) the scanning lines Gi are replaced with (n / 3) scanning lines G1i, and (5n / 3) the control lines GINIi, EMi, EMRi, EMGi, EMBi are replaced with 2n control lines G2i, Substituted by G3i, G4i, G5Ri, G5Gi, G5Bi. Among the constituent elements of this embodiment, the same elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
　図１５は、画素回路４０の接続形態を示す図である。図１５には、列方向に隣接した３個の画素回路４０の接続形態が記載されている。３個の画素回路４０は、いずれも、走査線Ｇ１ｉと制御線Ｇ２ｉ、Ｇ３ｉ、Ｇ４ｉ、Ｇ５Ｒｉ、Ｇ５Ｇｉ、Ｇ５Ｂｉに接続される。また、３個の画素回路１０は、それぞれ、データ線Ｓ１ｊ、Ｓ２ｊ、Ｓ３ｊに接続される。 FIG. 15 is a diagram showing a connection form of the pixel circuit 40. FIG. 15 shows a connection form of three pixel circuits 40 adjacent in the column direction. All of the three pixel circuits 40 are connected to the scanning line G1i and the control lines G2i, G3i, G4i, G5Ri, G5Gi, and G5Bi. The three pixel circuits 10 are connected to data lines S1j, S2j, and S3j, respectively.
　図１６は、画素回路４０の回路図である。画素回路４０は、１１個のＴＦＴ４１～４５、４６ｒ、４６ｇ、４６ｂ、４７ｒ、４７ｇ、４７ｂ、コンデンサ４８、および、３個の有機ＥＬ素子４９ｒ、４９ｇ、４９ｂを含んでいる。１１個のＴＦＴはいずれもＮ型トランジスタであり、ＴＦＴ４１は駆動用トランジスタとして機能する。ＴＦＴ４１～４５、４６ｒ、４６ｇ、４６ｂ、４７ｒ、４７ｇ、４７ｂとコンデンサ４８は、発光素子駆動部として機能する。なお、画素回路４０は、特許文献２の図３８に記載された画素回路を変形したものである。 FIG. 16 is a circuit diagram of the pixel circuit 40. The pixel circuit 40 includes eleven TFTs 41 to 45, 46r, 46g, 46b, 47r, 47g, 47b, a capacitor 48, and three organic EL elements 49r, 49g, 49b. The eleven TFTs are all N-type transistors, and the TFT 41 functions as a driving transistor. The TFTs 41 to 45, 46r, 46g, 46b, 47r, 47g, 47b and the capacitor 48 function as a light emitting element driving unit. The pixel circuit 40 is a modification of the pixel circuit described in FIG.
　図１６に示すように、ＴＦＴ４５のドレインには電源電位ＥＬＶＤＤが印加される。ＴＦＴ４５のソースは、ＴＦＴ４１、４３のドレインに接続される。ＴＦＴ４３のソースは、ＴＦＴ４１のゲートとコンデンサ４８の一方の電極に接続される。ＴＦＴ４１のソースは、ＴＦＴ４２、４６ｒ、４６ｇ、４６ｂのドレインに接続される。ＴＦＴ４２のソースは、データ線Ｓ１ｊに接続される。ＴＦＴ４６ｒ、４６ｇ、４６ｂのソースは、それぞれ、ＴＦＴ４７ｒ、４７ｇ、４７ｂのソースと有機ＥＬ素子４９ｒ、４９ｇ、４９ｂのアノードに接続される。有機ＥＬ素子４９ｒ、４９ｇ、４９ｂのカソードには、電源電位ＥＬＶＳＳが印加される。コンデンサ４８の他方の電極とＴＦＴ４７ｒ、４７ｇ、４７ｂのドレインは、ＴＦＴ４４のソースに接続される。ＴＦＴ４４のドレインには、初期化電位Ｖｉｎｉが印加される。ＴＦＴ４２のゲートは走査線Ｇ１ｉに接続される。ＴＦＴ４３～４５のゲートは、それぞれ、制御線Ｇ３ｉ、Ｇ４ｉ、Ｇ２ｉに接続される。ＴＦＴ４６ｒ、４７ｒのゲートは制御線Ｇ５Ｒｉに接続され、ＴＦＴ４６ｇ、４７ｇのゲートは制御線Ｇ５Ｇｉに接続され、ＴＦＴ４６ｂ、４７ｂのゲートは制御線Ｇ５Ｂｉに接続される。 As shown in FIG. 16, the power supply potential ELVDD is applied to the drain of the TFT 45. The source of the TFT 45 is connected to the drains of the TFTs 41 and 43. The source of the TFT 43 is connected to the gate of the TFT 41 and one electrode of the capacitor 48. The source of the TFT 41 is connected to the drains of the TFTs 42, 46r, 46g, and 46b. The source of the TFT 42 is connected to the data line S1j. The sources of the TFTs 46r, 46g, and 46b are connected to the sources of the TFTs 47r, 47g, and 47b and the anodes of the organic EL elements 49r, 49g, and 49b, respectively. A power supply potential ELVSS is applied to the cathodes of the organic EL elements 49r, 49g, and 49b. The other electrode of the capacitor 48 and the drains of the TFTs 47r, 47g, 47b are connected to the source of the TFT 44. An initialization potential Vini is applied to the drain of the TFT 44. The gate of the TFT 42 is connected to the scanning line G1i. The gates of the TFTs 43 to 45 are connected to control lines G3i, G4i, and G2i, respectively. The gates of the TFTs 46r and 47r are connected to the control line G5Ri, the gates of the TFTs 46g and 47g are connected to the control line G5Gi, and the gates of the TFTs 46b and 47b are connected to the control line G5Bi.
　図１６に示す画素回路４０は、第ｉ行第ｊ列のカラー画素に対応した画素回路Ａｉｊである。第（ｉ＋１）行第ｊ列のカラー画素に対応した画素回路Ａｉ＋１ｊと、第（ｉ＋２）行第ｊ列のカラー画素に対応した画素回路Ａｉ＋２ｊも、図１６に示す構成を有する。ただし、画素回路Ａｉ＋１ｊではＴＦＴ４２のソースはデータ線Ｓ２ｊに接続され、画素回路Ａｉ＋２ｊではＴＦＴ４２のソースはデータ線Ｓ３ｊに接続される。 The pixel circuit 40 shown in FIG. 16 is a pixel circuit Aij corresponding to the color pixel in the i-th row and the j-th column. The pixel circuit Ai + 1j corresponding to the color pixel in the (i + 1) th row and the jth column and the pixel circuit Ai + 2j corresponding to the color pixel in the (i + 2) th row and the jth column also have the configuration shown in FIG. However, in the pixel circuit Ai + 1j, the source of the TFT 42 is connected to the data line S2j, and in the pixel circuit Ai + 2j, the source of the TFT 42 is connected to the data line S3j.
　画素回路４０は、図５に示すタイミングで動作する。図１７は、画素回路４０のタイミングチャートである。図１７には、列方向に隣接する３個の画素回路Ａｉｊ、Ａｉ＋１ｊ、Ａｉ＋２ｊに接続される１０本の信号線の電位の変化が記載されている。以下、走査線Ｇ１ｉの電位がハイレベルである期間を走査線Ｇ１ｉの選択期間といい、制御線Ｇ５Ｒｉ、Ｇ５Ｇｉ、Ｇ５Ｂｉの電位がハイレベルである期間を、それぞれ、Ｒ発光期間、Ｇ発光期間およびＢ発光期間という。図１７を参照して、画素回路Ａｉｊの動作を説明する。 The pixel circuit 40 operates at the timing shown in FIG. FIG. 17 is a timing chart of the pixel circuit 40. FIG. 17 shows changes in potentials of ten signal lines connected to three pixel circuits Aij, Ai + 1j, and Ai + 2j adjacent in the column direction. Hereinafter, a period in which the potential of the scanning line G1i is at a high level is referred to as a selection period of the scanning line G1i, and a period in which the potentials of the control lines G5Ri, G5Gi, and G5Bi are at a high level are respectively represented as This is called the B light emission period. The operation of the pixel circuit Aij will be described with reference to FIG.
　時刻ｔ１より前では、走査線Ｇ１ｉおよび制御線Ｇ３ｉ、Ｇ４ｉ、Ｇ５Ｒｉ、Ｇ５Ｇｉ、Ｇ５Ｂｉの電位はローレベルであり、制御線Ｇ２ｉの電位はハイレベルである。このため、ＴＦＴ４２～４４、４６ｒ、４６ｇ、４６ｂ、４７ｒ、４７ｇ、４７ｂはオフ状態であり、ＴＦＴ４５はオン状態である。時刻ｔ１において、走査線Ｇ１ｉおよび制御線Ｇ３ｉ、Ｇ４ｉの電位がハイレベルに変化する。このため、ＴＦＴ４１～４４はオン状態になる。これにより、ＴＦＴ４１のゲート電位はＥＬＶＤＤに初期化され、コンデンサ４８の他方の電極の電位はＶｉｎｉに初期化される。また、走査線Ｇ１ｉの選択期間では、データ線Ｓ１ｊにデータ電位ＶＲｉｊが印加される。このため、ＴＦＴ４１のソース電位はＶＲｉｊになる。 Prior to time t1, the potentials of the scanning line G1i and the control lines G3i, G4i, G5Ri, G5Gi, and G5Bi are at a low level, and the potential of the control line G2i is at a high level. Therefore, the TFTs 42 to 44, 46r, 46g, 46b, 47r, 47g, and 47b are in the off state, and the TFT 45 is in the on state. At time t1, the potentials of the scanning line G1i and the control lines G3i, G4i change to high level. Therefore, the TFTs 41 to 44 are turned on. As a result, the gate potential of the TFT 41 is initialized to ELVDD, and the potential of the other electrode of the capacitor 48 is initialized to Vini. In the selection period of the scanning line G1i, the data potential VRij is applied to the data line S1j. For this reason, the source potential of the TFT 41 becomes VRij.
　時刻ｔ２において、制御線Ｇ２ｉの電位はローレベルに変化する。このため、ＴＦＴ４５はオフ状態になる。ＴＦＴ４１がオン状態である間、ＴＦＴ４１、４３を通過する電流が流れ、ＴＦＴ４１のゲート電位は下降する。ＴＦＴ４１の閾値電圧をＶｔｈとすると、ＴＦＴ４１のゲート電位は（ＶＲｉｊ＋Ｖｔｈ）まで下降する。時刻ｔ３において、走査線Ｇ１ｉおよび制御線Ｇ３ｉ、Ｇ４ｉの電位はローレベルに変化する。このため、ＴＦＴ４２～４４はオフ状態になる。このときコンデンサ４８には、電位差（ＶＲｉｊ＋Ｖｔｈ－Ｖｉｎｉ）が保持される。 At time t2, the potential of the control line G2i changes to a low level. For this reason, the TFT 45 is turned off. While the TFT 41 is in the ON state, a current passing through the TFTs 41 and 43 flows, and the gate potential of the TFT 41 decreases. When the threshold voltage of the TFT 41 is Vth, the gate potential of the TFT 41 falls to (VRij + Vth). At time t3, the potentials of the scanning line G1i and the control lines G3i, G4i change to a low level. For this reason, the TFTs 42 to 44 are turned off. At this time, the capacitor 48 holds a potential difference (VRij + Vth−Vini).
　時刻ｔ４において、制御線Ｇ２ｉ、Ｇ５Ｒｉがハイレベルに変化する。Ｒ発光期間では、ＴＦＴ４５、４６ｒ、４７ｒがオン状態になる。また、ＴＦＴ４１のゲート－ソース間には、コンデンサ４８に保持された電位差（ＶＲｉｊ＋Ｖｔｈ－Ｖｉｎｉ）が印加される。Ｒ発光期間にＴＦＴ４１を通過する電流Ｉｒは、ＴＦＴ４１のゲート－ソース間の電位差Ｖｇｓと比例定数ｋを用いて、上式（１）で表される。Ｖｇｓ＝ＶＲｉｊ＋Ｖｔｈ－Ｖｉｎｉより、次式（３）が導かれる。
　　Ｉｒ＝ｋ（ＶＲｉｊ－Ｖｉｎｉ）2   …（３） At time t4, the control lines G2i and G5Ri change to high level. In the R light emission period, the TFTs 45, 46r, and 47r are turned on. Further, a potential difference (VRij + Vth−Vini) held in the capacitor 48 is applied between the gate and source of the TFT 41. The current Ir passing through the TFT 41 during the R emission period is expressed by the above formula (1) using the potential difference Vgs between the gate and the source of the TFT 41 and the proportionality constant k. From Vgs = VRij + Vth−Vini, the following expression (3) is derived.
Ir = k (VRij−Vini) 2 (3)
　式（３）で示す電流Ｉｒは、データ電位ＶＲｉｊに応じて変化するが、ＴＦＴ４１の閾値電圧Ｖｔｈには依存しない。したがって、閾値電圧Ｖｔｈにばらつきがある場合や、閾値電圧Ｖｔｈが経時的に変化する場合でも、閾値電圧Ｖｔｈに依存しない電流を有機ＥＬ素子４９ｒに流して、有機ＥＬ素子４９ｒを所望の輝度で発光させることができる。 The current Ir shown in Equation (3) changes according to the data potential VRij, but does not depend on the threshold voltage Vth of the TFT 41. Therefore, even when the threshold voltage Vth varies or when the threshold voltage Vth changes over time, a current that does not depend on the threshold voltage Vth is caused to flow through the organic EL element 49r, and the organic EL element 49r emits light with a desired luminance. Can be made.
　時刻ｔ５において、制御線Ｇ５Ｒｉの電位はローレベルに変化する。このため、ＴＦＴ４６ｒ、４７ｒはオフ状態になる。Ｇサブフレーム期間とＢサブフレーム期間において、画素回路ＡｉｊはＲサブフレーム期間と同様に動作する。画素回路Ａｉ＋１ｊ、Ａｉ＋２ｊは、画素回路Ａｉｊと並列に、画素回路Ａｉｊと同じ動作を行う。 At time t5, the potential of the control line G5Ri changes to a low level. For this reason, the TFTs 46r and 47r are turned off. In the G subframe period and the B subframe period, the pixel circuit Aij operates in the same manner as in the R subframe period. The pixel circuits Ai + 1j and Ai + 2j perform the same operation as the pixel circuit Aij in parallel with the pixel circuit Aij.
　本実施形態に係る表示装置４００によれば、アモルファスシリコンや酸化物半導体などで形成したＮ型トランジスタを用いて画素回路を構成した場合でも、複数のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 According to the display device 400 according to the present embodiment, even when a pixel circuit is configured using an N-type transistor formed of amorphous silicon, an oxide semiconductor, or the like, the elements are shared among a plurality of sub-pixels. The number of elements can be reduced.
　以上に示すように、本発明の表示装置によれば、走査速度の増加を抑制しながら、複数のサブ画素間で素子を共有して画素回路内の素子数を削減することができる。 As described above, according to the display device of the present invention, it is possible to reduce the number of elements in a pixel circuit by sharing elements among a plurality of sub-pixels while suppressing an increase in scanning speed.
　本発明の表示装置は、走査速度の増加を抑制しながら、画素回路内の素子数を削減できるという特徴を有するので、有機ＥＬディスプレイなどのアクティブマトリクス型の表示装置に利用することができる。 Since the display device of the present invention has a feature that the number of elements in the pixel circuit can be reduced while suppressing an increase in scanning speed, it can be used for an active matrix display device such as an organic EL display.
　１…表示制御回路
　２、３０１、４０１…走査線駆動回路
　３…データ線駆動回路
　４…シフトレジスタ
　５…レジスタ
　６…ラッチ回路
　７…Ｄ／Ａ変換器
　１０、２０、３０、４０…画素回路
　１１～１６、２１、３１、４１～４７…ＴＦＴ
　１７、４８…コンデンサ
　１８、２２、４９…有機ＥＬ素子
　１００、３００、４００…表示装置 DESCRIPTION OF SYMBOLS 1 ... Display control circuit 2, 301, 401 ... Scan line drive circuit 3 ... Data line drive circuit 4 ... Shift register 5 ... Register 6 ... Latch circuit 7 ... D / A converter 10, 20, 30, 40 ... Pixel circuit 11 ~ 16, 21, 31, 41 ~ 47 ... TFT
17, 48 ... Capacitors 18, 22, 49 ... Organic EL elements 100, 300, 400 ... Display devices

Claims (14)

  1. 　アクティブマトリクス型の表示装置であって、
    　行方向および列方向に並んだ複数の画素回路と、
    　行方向に伸延する複数の走査線および複数の制御線と、
    　列方向に伸延する複数のデータ線と、
    　前記走査線および前記制御線を駆動する走査線駆動回路と、
    　前記データ線を駆動するデータ線駆動回路とを備え、
    　前記画素回路のそれぞれは、
    　　複数の発光素子と、
    　　１個の駆動用トランジスタを有し、前記駆動用トランジスタを通過した電流を前記制御線の電位に基づき前記複数の発光素子のいずれかに流す発光素子駆動部とを含み、
    　前記走査線駆動回路および前記データ線駆動回路は、１フレーム期間を分割して得られたサブフレーム期間のそれぞれにおいて前記複数の画素回路にデータ電位を書き込み、サブフレーム期間ごとに前記駆動用トランジスタを通過した電流の経路を切り替え、
    　前記走査線駆動回路および前記データ線駆動回路は、複数行の画素回路に対して前記データ電位を並列に書き込むことを特徴とする、表示装置。     An active matrix display device,
    A plurality of pixel circuits arranged in a row direction and a column direction;
    A plurality of scanning lines and a plurality of control lines extending in the row direction;
    A plurality of data lines extending in the column direction;
    A scanning line driving circuit for driving the scanning line and the control line;
    A data line driving circuit for driving the data line,
    Each of the pixel circuits is
    A plurality of light emitting elements;
    A light-emitting element drive unit that includes one drive transistor, and causes a current that has passed through the drive transistor to flow to any one of the plurality of light-emitting elements based on the potential of the control line,
    The scanning line driving circuit and the data line driving circuit write data potentials to the plurality of pixel circuits in each of the subframe periods obtained by dividing one frame period, and the driving transistor is set in each subframe period. Switch the path of the current that passed,
    The display device, wherein the scanning line driving circuit and the data line driving circuit write the data potential in parallel to a plurality of rows of pixel circuits.
  2. 　前記走査線は、前記画素回路の２以上の第１の数の行に対応して１本ずつ設けられ、
    　前記データ線は、前記画素回路の各列に対応して前記第１の数ずつ設けられ、
    　前記走査線駆動回路は、前記走査線を１本ずつ順に選択することにより、前記第１の数の行の画素回路を順に選択し、
    　前記データ線駆動回路は、前記走査線駆動回路によって選択された画素回路に書き込むデータ電位を前記データ線に印加することを特徴とする、請求項１に記載の表示装置。     The scanning lines are provided one by one corresponding to a first number of rows of two or more of the pixel circuits,
    The data lines are provided by the first number corresponding to the columns of the pixel circuit,
    The scanning line driving circuit sequentially selects the pixel circuits in the first number of rows by sequentially selecting the scanning lines one by one,
    The display device according to claim 1, wherein the data line driving circuit applies a data potential to be written to the pixel circuit selected by the scanning line driving circuit to the data line.
  3. 　前記画素回路のそれぞれは、２以上の第２の数の発光素子を含み、
    　前記走査線駆動回路および前記データ線駆動回路は、１フレーム期間を前記第２の数のサブフレーム期間に分割することを特徴とする、請求項２に記載の表示装置。     Each of the pixel circuits includes a second number of light emitting elements of 2 or more,
    3. The display device according to claim 2, wherein the scanning line driving circuit and the data line driving circuit divide one frame period into the second number of subframe periods.
  4. 　前記画素回路に含まれる前記複数の発光素子は、表示画面内で行方向に並び、１個のカラー画素を構成する複数のサブ画素に対応することを特徴とする、請求項３に記載の表示装置。 4. The display according to claim 3, wherein the plurality of light emitting elements included in the pixel circuit correspond to a plurality of sub-pixels arranged in a row direction in a display screen and constituting one color pixel. 5. apparatus.
  5. 　前記画素回路のそれぞれは、赤色に発光する発光素子、緑色に発光する発光素子、および、青色に発光する発光素子を１個ずつ含むことを特徴とする、請求項４に記載の表示装置。 The display device according to claim 4, wherein each of the pixel circuits includes one light emitting element that emits red light, one light emitting element that emits green light, and one light emitting element that emits blue light.
  6. 　前記画素回路に含まれる前記複数の発光素子は、表示画面内で行方向に並び、隣接した複数のカラー画素を構成する複数のサブ画素に対応することを特徴とする、請求項３に記載の表示装置。 The plurality of light emitting elements included in the pixel circuit correspond to a plurality of subpixels arranged in a row direction in a display screen and constituting a plurality of adjacent color pixels. Display device.
  7. 　前記画素回路のそれぞれは、赤色に発光する発光素子、緑色に発光する発光素子、および、青色に発光する発光素子を複数個ずつ含むことを特徴とする、請求項６に記載の表示装置。 The display device according to claim 6, wherein each of the pixel circuits includes a plurality of light emitting elements that emit red light, light emitting elements that emit green light, and light emitting elements that emit blue light.
  8. 　前記画素回路に含まれる前記複数の発光素子は、表示画面内で列方向に並んだ複数のカラー画素に含まれる同じ色のサブ画素に対応することを特徴とする、請求項３に記載の表示装置。 The display according to claim 3, wherein the plurality of light emitting elements included in the pixel circuit correspond to sub-pixels of the same color included in the plurality of color pixels arranged in the column direction in the display screen. apparatus.
  9. 　前記画素回路は、赤色に発光する発光素子を含む画素回路、緑色に発光する発光素子を含む画素回路、および、青色に発光する発光素子を含む画素回路のいずれかであることを特徴とする、請求項８に記載の表示装置。 The pixel circuit is any one of a pixel circuit including a light emitting element that emits red light, a pixel circuit including a light emitting element that emits green light, and a pixel circuit including a light emitting element that emits blue light. The display device according to claim 8.
  10. 　前記第１の数は前記第２の数に等しいことを特徴とする、請求項３に記載の表示装置。 4. The display device according to claim 3, wherein the first number is equal to the second number.
  11. 　前記第１の数は前記第２の数よりも小さいことを特徴とする、請求項３に記載の表示装置。 The display device according to claim 3, wherein the first number is smaller than the second number.
  12. 　前記第１の数は前記第２の数よりも大きいことを特徴とする、請求項３に記載の表示装置。 The display device according to claim 3, wherein the first number is larger than the second number.
  13. 　前記発光素子駆動部は、前記駆動用トランジスタと前記発光素子のそれぞれとの間に、制御端子が互いに異なる前記制御線に接続されたスイッチ素子を含むことを特徴とする、請求項３に記載の表示装置。 The said light emitting element drive part contains the switch element connected to the said control line from which a control terminal mutually differs between the said drive transistor and each of the said light emitting element, The Claim 3 characterized by the above-mentioned. Display device.
  14. 　行方向に伸延する複数の走査線および複数の制御線と、列方向に伸延する複数のデータ線と、それぞれが複数の発光素子と、駆動用トランジスタを通過した電流を前記複数の発光素子のいずれかに流す発光素子駆動部とを含み、行方向および列方向に並んだ複数の画素回路とを備えたアクティブマトリクス型の表示装置の駆動方法であって、
    　前記走査線および前記データ線を駆動することにより、１フレーム期間を分割して得られたサブフレーム期間のそれぞれにおいて前記複数の画素回路にデータ電位を書き込むステップと、
    　前記制御線を駆動することにより、サブフレーム期間ごとに前記駆動用トランジスタを通過した電流の経路を切り替えるステップとを備え、
    　前記データ電位を書き込むステップは、複数行の画素回路に対して前記データ電位を並列に書き込むことを特徴とする、表示装置の駆動方法。     A plurality of scanning lines and a plurality of control lines extending in the row direction, a plurality of data lines extending in the column direction, a plurality of light emitting elements, and a current passing through the driving transistor A driving method of an active matrix display device including a plurality of pixel circuits arranged in a row direction and a column direction,
    Writing data potentials to the plurality of pixel circuits in each of the sub-frame periods obtained by dividing one frame period by driving the scanning lines and the data lines;
    Switching the path of the current that has passed through the driving transistor every subframe period by driving the control line, and
    The method of driving a display device, wherein the step of writing the data potential includes writing the data potential in parallel to a plurality of rows of pixel circuits.
PCT/JP2013/054279 2012-02-28 2013-02-21 Display device and method for driving same WO2013129216A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019207440A1 (en) * 2018-04-26 2019-10-31 株式会社半導体エネルギー研究所 Display device and electronic apparatus
WO2023044680A1 (en) * 2021-09-23 2023-03-30 京东方科技集团股份有限公司 Display substrate and display apparatus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006072311A (en) * 2004-08-30 2006-03-16 Samsung Sdi Co Ltd Frame memory control method and display using the same
JP2006163371A (en) * 2004-12-09 2006-06-22 Samsung Sdi Co Ltd Pixel circuit and luminescence display device
JP2009211104A (en) * 2004-11-22 2009-09-17 Samsung Mobile Display Co Ltd Light-emitting display
JP2011102932A (en) * 2009-11-11 2011-05-26 Sony Corp Display device and method of driving the same, electronic equipment, and display panel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006072311A (en) * 2004-08-30 2006-03-16 Samsung Sdi Co Ltd Frame memory control method and display using the same
JP2009211104A (en) * 2004-11-22 2009-09-17 Samsung Mobile Display Co Ltd Light-emitting display
JP2006163371A (en) * 2004-12-09 2006-06-22 Samsung Sdi Co Ltd Pixel circuit and luminescence display device
JP2011102932A (en) * 2009-11-11 2011-05-26 Sony Corp Display device and method of driving the same, electronic equipment, and display panel

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019207440A1 (en) * 2018-04-26 2019-10-31 株式会社半導体エネルギー研究所 Display device and electronic apparatus
JPWO2019207440A1 (en) * 2018-04-26 2021-06-10 株式会社半導体エネルギー研究所 Display devices and electronic devices
US11513405B2 (en) 2018-04-26 2022-11-29 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
JP7235731B2 (en) 2018-04-26 2023-03-08 株式会社半導体エネルギー研究所 Displays and electronics
US11762250B2 (en) 2018-04-26 2023-09-19 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
JP7488927B2 (en) 2018-04-26 2024-05-22 株式会社半導体エネルギー研究所 Display device
WO2023044680A1 (en) * 2021-09-23 2023-03-30 京东方科技集团股份有限公司 Display substrate and display apparatus

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