WO2013123433A2

WO2013123433A2 - Negative sequence current compensation controller and method for power conversion system

Info

Publication number: WO2013123433A2
Application number: PCT/US2013/026496
Authority: WO
Inventors: Zhuohui Tan; Dan HOU; Xinhui Wu; Maozhong Gong
Original assignee: General Electric Company
Priority date: 2012-02-17
Filing date: 2013-02-15
Publication date: 2013-08-22
Also published as: CN103259281A; CN103259281B; WO2013123433A3

Abstract

An exemplary power conversion system is disclosed including a DC bus for receiving DC power, a power converter for converting the DC power to AC power, and a controller. The controller generates a first command signal and a second command signal based on power command and feedback signals. Upon an negative sequence current occurrence, the converter controller generates first and second negative sequence current correction signals based on a detected grid current signal and a negative sequence current command signal, adjusts the first and second command signals based on the first and second negative sequence current correction signals respectively, and generates control signals for the power converter based on the adjusted first and second command signals to cause an AC voltage output from the power converter to reduce the negative sequence currents.

Description

NEGATIVE SEQUENCE CURRENT COMPENSATION CONTROLLER AND METHOD FOR POWER CONVERSION SYSTEM

BACKGROUND

[OOOIJ Embodiments of the disclosure relate generally to power conversion systems and methods for converting and providing electrical power to feed an electrical system.

[0002] Renewable power, such as solar power generated by solar power generation systems, is becoming a larger source of energy throughout the world, A typical solar power generation system includes one or more photovoltaic arrays (PV arrays) having multiple interconnected solar cells. The solar cells of the PV arrays convert solar energy into DC power. In order to interface the output of the PV arrays to a power grid, a solar power converter is typically used to change the DC power from the PV arrays into AC power to feed a power grid.

[0003] Various solar power converter configurations exist for converting the DC power output from PV arrays into AC power. One implementation of a solar power converter has two stages including a DC-DC converter stage and a DC-AC converter stage. The DC-DC converter controls the flow of DC power from the PV arrays onto a DC bus. The DC-AC converter converts the DC power supplied to the DC bus into AC power that can be output to the power grid. Existing solar power converters further utilize power converter control systems to regulate the DC-DC converter and the DC-AC converter to compensate for various system variables, such as DC bus voltage, AC grid voltage, AC grid current, and frequency, for example.

[00041 In normal power generation processes, the conventional power converter control systems are designed to regulate positive sequence signals but not to regulate negative sequence signals. Thus, during grid fault events such as single phase faults or unbalance between the three phases, the negative sequence signals may influence the system stability. In such a case, a large negative sequence current will limit the positive sequence current output from the converter, which may interfere with the converter meeting grid and/or design requirements. [0005] Therefore, it is desirable to provide systems and methods to address the above-mentioned problems.

BRIEF DESCRIPTION

[0006] in accordance with one embodiment disclosed herein, a power conversion system is provided. The power conversion system comprises a direct current (DC) bus for receiving DC power from a power source, a power converter for converting the DC power on the DC bus to alternating current (AC) power, and a controller coupled to the power converter. The controller is configured for generating a first command signal based on an active power command signal and an active power feedback signal, and generating a second command signal based on a reactive power command signal and a reactive power feedback signal. Upon an occurrence of generating negative sequence currents from a transient event, the controller is used for generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal, adjusting the first and second command signals based on the first and second negative sequence current correction signals respectively, and generating control signals for the power converter based on the adjusted first and second command signals to cause an AC voltage output from the power converter to reduce the negative sequence currents.

[0007] In accordance with another embodiment disclosed herein, a method of operating a power conversion system is provided. The method comprises generating a first command signal based on an active power command signal and an active power feedback signal; generating a second command signal based on a reactive power command signal and a reactive power feedback signal; generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal; adjusting the first and second command signals based on the first and second negative sequence current correction signals respectively; and generating control signals for a power converter of the power conversion system for causing an AC voltage output from the power converter to reduce the negative sequence currents based on the adjusted first and second command signals.

DRAWINGS

10008] These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

[0009] FIG. 1 is a schematic block diagram of a solar power conversion system in accordance with an exemplary embodiment of the present disclosure.

[0010] FIG. 2 is a control diagram of a line side controller of the solar power conversion system shown in FIG. 1 in accordance with an exemplary embodiment of the present disclosure.

[0011] FIG. 3 is a control diagram of a line side controller of the solar power conversion system shown in FIG. 1 in accordance with another exemplary embodiment of the present disclosure.

[0012] FIG. 4 is a control diagram of a negative sequence current compensation unit of the line side controllers shown in FIGs. 2 and 3 in accordance with an exemplary embodiment of the present disclosure.

[0013] FIG. 5 is a detailed control diagram of a negative sequence current detector of the negative sequence current compensation unit shown in FIG. 4 in accordance with an exemplary embodiment of the present disclosure.

[0014] FIG. 6 is a detailed control diagram of a negative sequence current regulator of the negative sequence current compensation unit shown in FIG. 4 in accordance with an exemplary embodiment of the present disclosure. [0015] FIG. 7 is a detailed control diagram of a negative sequence current regulator of the negative sequence current compensation unit shown in FIG. 4 in accordance with another exemplary embodiment of the present disclosure.

[0016J FIG, 8 is a detailed control diagram of a negative sequence current regulator of the negative sequence current compensation unit shown in FIG. 4 in accordance with yet another exemplary embodiment of the present disclosure.

[0017] FIG. 9 is a detailed control diagram of a negative sequence current regulator of the negative sequence current compensation unit shown in FIG. 4 in accordance with yet another exemplary embodiment of the present disclosure.

[0018] FIG. 10 is a detailed control diagram of a negative sequence current regulator of the negative sequence current compensation unit shown in FIG. 4 in accordance with yet another exemplary embodiment of the present disclosure.

[0019J FIG. 1 1 is a detailed control diagram of a negative sequence current regulator of the negative sequence current compensation unit shown in FIG. 4 in accordance with yet another exemplary embodiment of the present disclosure.

[0020] FIG. 12 is a control diagram of a negative sequence current compensation unit of the line side controller shown in FIG. 3 in accordance with another exemplary embodiment of the present disclosure.

[0021] FIG. 13 is a simulation diagram to show the performance after applying the negative sequence current compensation unit of the solar power conversion system shown in FIG. 1.

[0022] FIG. 14 is a control diagram of a line side controller of the solar power conversion system shown in FIG. 1 in accordance with another exemplary embodiment of the present disclosure.

[0023] FIG. 15 is a control diagram of a line side controller of the solar power conversion system shown in FIG. 1 in accordance with yet another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0024J Embodiments disclosed herein relate generally to negative sequence current compensation for power conversion systems upon occurrence of transient events or subsequent recovery processes and to a method for providing negative sequence current compensation. As used herein, "negative sequence current compensation" refers to tracking grid currents and providing real time negative sequence current information for compensation when undesired negative sequence currents are generated. The term of "transient event" as used herein refers to one or more grid side events or conditions such as single phase fault events occurring at a power grid, for example. More particularly, in one embodiment, the negative sequence current compensation described herein is implemented based on a voltage source control structure or scheme. As used herein, "voltage source control (VSC) structure or scheme" refers a control embodiment wherein one of the primary control parameters is AC voltage. In more specific embodiments, the control parameters include a phase angle command and a voltage magnitude command of the power conversion system or a pair of voltage signals in a synchronous rotating reference coordinate (also referred to as d-q coordinate). Detailed implementation of the VSC based negative sequence current compensation involves providing real time negative sequence current information in a manner as quickly as possible. Thus, upon occurrence of a transient event, an internally generated phase angle command signal and an internally generated voltage magnitude command signal (or the pair of d-q coordinate voltage signals) can be generated according to the negative sequence current information, such that corresponding adjustments can be made to ensure stable operation of the converter.

[00251 if desired, implementations of the negative sequence current compensation may be combined with a current limiting algorithm which is used for providing protection to the power conversion system by limiting the current at the output of the power conversion system according to threshold current values during transient events. If desired, implementations of the negative sequence current compensation may be combined with a phase jump compensation algorithm which is used for providing protection to the power conversion system by providing real time phase jump information for compensation when phase detection devices cannot detect the correct phase angle information as quickly as desired during transient events. If desired, implementations of the negative sequence current compensation may be combined with other control methodologies to improve the performance of the power conversion systems. One of the technical advantages of implementing the VSC based negative sequence current compensation is that the generated negative sequence currents can be quickly decreased or eliminated, which can stabilize the conversion system. Because the generated negative sequence currents are decreased or eliminated, the problem of limiting positive sequence currents due to the negative sequence currents from the grid can be avoided.

[0026] One or more specific embodiments of the present disclosure will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0027] Unless defined otherwise, technical and scientific terms used herein have the same meaning as is commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the terms "a" and "an" do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term "or" is meant to be inclusive and mean either or all of the listed items. The use of "including," "comprising" or "having" and variations thereof herein are meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms "connected" and "coupled" are not restricted to physical or mechanical connections or couplings, and can include electrical connections or couplings, whether direct or indirect. Furthermore, the terms "circuit" and "circuitry" and "controller" may include either a single component or a plurality of components, which are either active and/or passive and may be optionally be connected or otherwise coupled together to provide the described function.

[0028] FIG. 1 illustrates a schematic block diagram of a power conversion system 10 in accordance with an exemplary embodiment of the present disclosure. For ease of illustration, the power conversion system 10 is illustrated and described in the context of a solar power conversion system. However, a person having ordinary skill in the art will readily understand that the embodiments described herein are not limited to solar applications, as certain aspects of the disclosure, for example voltage source control (VSC) based negative sequence current compensation, can be applied in a similar manner to other types of power conversion systems, including but not limited to, fuel cell systems, wind power systems, and tidal power systems, for example.

[0029] in general, the solar power conversion system 10 shown in FIG. 1 includes a solar power converter system 14 configured to be an interface between a solar power source 12 and a power grid 18. More specifically, the solar power converter system 14 is configured to convert power in a form of direct current (DC) voltage or current (hereinafter referred to as DC power) generated from a solar power source 12 into power in the form of alternating current (AC) voltage or current (hereinafter referred to as AC power) suitable for feeding an electrical system shown as power grid 18. In one embodiment, the solar power source 12 may include one or more photovoltaic arrays (PV arrays) having multiple interconnected solar cells that can convert, solar radiation energy into DC power through the photovoltaic effect. In one embodiment, the electrical system 18 will be described below as an AC power grid, and the solar power conversion system 10 is configured for delivering nominally fixed frequency three-phase AC power. In other embodiments, the electrical system 18 may comprise an AC load, such as an AC electrical motor. [0030] In one implementation, the power converter system 14 shown in FIG. 1 is based on a two-stage structure including a PV side converter 142 and a Sine side converter 144. The PV side converter 142 may comprise a DC-DC converter, such as a DC-DC boost converter, that steps up a DC voltage received from the power source 12 and outputs a higher DC voltage onto a DC bus 146. The DC bus 146 may include one or more capacitors for maintaining the DC voltage of the DC bus 146 at a certain level, and thus the energy flow from the DC bus 146 to the power grid 18 can be managed. The line side converter 144 may comprise a DC- AC inverter that converts the DC voltage on the DC bus 146 to AC voltage with suitable frequency, phase, and magnitude for feeding to the AC power grid 18. In other implementations, the power converter system 14 may be based on a single stage converter structure including a DC-AC converter for converting DC voltage at a DC bus to AC voltage with suitable frequency and voltage magnitude to feed the power grid 18.

[0031] In one implementation, the power conversion system 10 shown in FIG, 1 further comprises a power converter control system 16 configured to regulate the power at the output of the line side converter 144. In one implementation, the power converter control system 16 comprises a PV side controller 162 and a line side controller 164. The PV side controller 162 sends PV side control signals 166 to the PV side converter 142 to regulate the power on DC link 146 according to various command signals and feedback signals (shown as Vdc cmd and Vdc_fbk 156 (from voltage sensor 145), for example). The line side controller, 164 is configured to send line side control signals 168 to the line side converter 144 to regulate the active power and/or reactive power output from the line side converter 144 according to various command signals and feedback signals (shown as Pcmd 212, Qcmd 222, Vdc fbk 156, Vfbk 152 (from voltage sensor 36), and Ifbk 154 (from current sensor 34), for example). The PV side converter 142 may comprise any type of converter topology such as a half bridge converter, a full bridge converter, or a push-pull converter, for example. The line side converter 144 may comprise any type of DC to AC converter topology such as a 2~level converter or a 3 -level converter, for example. The PV side converter 142 and the line side converter 144 may comprise a plurality of semiconductor switching devices (not shown), including but not limited to, integrated gate commutated thyristors (IGCTs) and insulated gate bipolar transistors (IGBTs), for example. The switching devices are switched on and off in response to the PV side control signals 166 and the line side control signals 168 respectively. Although two controllers 162, 164 are illustrated and described herein, in other embodiments, a single controller may be used to control both the PV side converter 142 and the line side converter 144.

[0032] In one implementation, the power conversion system 10 shown in FIG. 1 may further comprise a PV side filter 22 having one or more capacitive and inductive elements for removing ripple components of the DC power output from the solar power source 12 and blocking ripple signals from being transformed from the PV side converter 142 to the solar power source 12. The power conversion system 10 may further include a line side filter 24 having one or more inductive elements or capacitive elements (not shown) for removing harmonic signals for each phase of the three-phase AC voltage or AC current output from the line side converter 144.

[0033] With continuing reference to FIG. 1 , the power conversion system 10 further includes a negative sequence current (NSC) compensation unit 290 for addressing transient events including large negative sequence current events occurring in the power grid 18. In one implementation, as illustrated, a common controller may be used such that the negative sequence current compensation unit 290 is embedded within the line side controller 164. Alternatively, the controller embodiment may include the negative sequence current compensation unit 290 implemented outside of the line side controller 164 or partly within the line side controller 164. More specifically, the negative sequence current compensation unit 290 is configured for tracking current signals of the grid 18 and providing information representing a negative sequence current present in the grid 18. The information provided from the negative sequence current compensation unit 290 then is used for adjusting the grid side control signals 168 sent from the line side controller 164 to the Sine side converter 144. With this adjustment, the negative sequence current present in the grid 18 can be quickly reduced or eliminated to stabilize the grid 18. More details of the negative sequence current compensation unit 290 will be described below. [0034] FIG, 2 illustrates at least a part of an overall control diagram of the line side controller 164 in accordance with an exemplary embodiment of the present disclosure. The functional blocks of the line side controller 164 illustrated in FIG. 2 can be implemented in hardware, firmware, software, or a combination thereof. In practical applications, the line side controller 164 may be implemented by a microcontroller, a digital signal processor (DSP), or any other appropriate programmable devices. In an exemplary embodiment, the line side controller 164 is constructed based on a voltage source control (VSC) structure,

[0035] In the illustrated embodiment of FIG. 2, the VSC based line side controller 164 comprises an active power regulator 210 that is configured to receive an active power command signal 212 and an active power feedback signal 214 and generate a phase angle command signal 216 (also called first command signal) based at least on the active power command signal 212 and the active power feedback signal 214. The active power command signal 212 represents the desired power to be output by the Sine side converter 144 (see FIG. 1 ) and may be dictated by a grid operator or a design parameter, for example. The active power feedback signal 214 represents the actual active power. The phase angle command signal 216 represents a desired phase angle of the AC voltage to be output from the line side converter 144. The active power feedback signal 214 may be obtained by multiplication of a feedback current signal 154 and a feedback voltage signal 152. The feedback current signal 154 and feedback voltage signal 152 may be obtained from a current sensor 34 and a voltage sensor 36 (shown in FIG. 1) placed between the line side converter 144 and the grid 18. In one implementation, the current sensor 34 and the voltage sensor 36 may comprise Hall Effect sensors for example. Although the sensors 34 and 36 are shown in FIG. 1 as being present between filter 24 and grid 18 at a point of common coupling for purposes of example, the measurements to be used for obtaining the power feedback signals may be obtained at any desired location along the electrical path from the line side converter 144 to the grid 18.

[0036] With continued reference to FIG. 2, the VSC based line side controller 164 further comprises a reactive power regulator 220 that is configured to receive a reactive power feedback signal 224 and a reactive power command signal 222 and generate a voltage magnitude command signal 226 (also called second command signal) based at least on the reactive power command signal 222 and the reactive power feedback signal 224. The reactive power command signal 222 represents the desired reactive power at the output of line side converter 144 and may be dictated by a grid operator or a design parameter, for example. The reactive power feedback signal 224 represents the actual reactive power and may be obtained by calculation of a feedback current signal 154 and a feedback voltage signal 152 (see FIG. 1). The voltage magnitude command signal 226 represents a desired voltage magnitude of the AC voltage output from the line side converter 44. In one embodiment, the reactive power regulator 220 may comprise a summation element (not shown) for producing a reactive power error signal by subtracting the reactive power feedback signal 224 from the reactive power command signal 222. The reactive power regulator 220 may further comprise a VAR regulator and a voltage regulator (not shown) for generating the voltage magnitude command signal 226 using the resulting reactive power error signal.

|0037] With continued reference to FIG. 2, the VSC based line side controller 164 further comprises a negative sequence current compensation unit 290 that is configured to receive a feedback current signal (such as the feedback current signal 154) and a negative sequence current command signal 155 and to generate a pair of negative sequence current correction signals 291 and 292 based at least in part on the negative sequence current command signal 155 and the negative part of the feedback current signal 154. The negative sequence current command signal 155 represents the desired negative sequence currents (such as zero) at the output of line side converter 144 and may be dictated by a grid operator or a design parameter, for example. It is convenient to use the same current sensor 34 for obtaining current measurements for use obtaining the feedback current signal 154. However, in some embodiments, different current sensors may be used and situated at different positions along the electrical path between line side converter 144 and grid 18. The negative sequence current correction signals 291 and 292 are used for adjusting the phase angle command signal 216 and for adjusting the voltage magnitude command signal 226, which can reduce or eliminate the negative sequence currents generated during some transient events. In one example, upon occurrence of a transient event, the negative current correction signal 291 is combined with the phase angle command signal 216 at summation unit 217 to provide an adjusted phase angle command signal 218, and the negative current correction signal 292 is combined with the voltage magnitude cornmand signal 226 at summation unit 227 to provide an adjusted voltage magnitude command signal 228.

[0038] With continued reference to FIG. 2, a signal generator 240 is configured for generating line side control signals 168 for the line side converter 144 (see FIG. 1) according to the phase angle command signal 216 or the adjusted phase angle command signal 218 and voltage magnitude command signal 226 or the adjusted voltage magnitude command signal 228. In one implementation, the signal generator 240 may comprise a pulse width modulation (PWM) signal generator for generating the line side control signals 168 in PWM pattern for the line side converter 144.

[00391 fTC. 3 illustrates at least a part of an overall control diagram of the line side controller 164 in accordance with another exemplary embodiment of the present disclosure. The illustrated embodiment of FIG. 3 is similar to the illustrated embodiment of FIG. 2 except that the embodiment of FIG. 3 further includes a coordinate transformation unit 250 used to transform the phase angle command signal 216 and the voltage magnitude command signal 226 into a pair of voltage command signals 1216 and 1226 (also called the first and second command signals respectively) into a synchronous rotating reference coordinate (also referred to as d-q coordinate), and correspondingly an adjusted negative sequence current compensation unit 1290 is provided to receive the feedback current signal 154 and the negative sequence current command signal 155 and generate a pair of negative sequence current correction signals 12 1 and 1292 in d-q coordinate based at least on the negative sequence current command signal 155 and the negative part of the feedback current signal 154. The negative sequence current correction signals 1291 and 1292 are respectively combined at summation elements 217 and 227 for adjusting the d-axis and q-axis voltage command signals 1216 and 1226 which are then provided to the signal generator 240. {0040] With continued reference to FIG. 3, Upon occurrence of a transient event, the signal generator 240 generates the line side control signal 168 according to an adjusted d-axis voltage command signal 1218 and an adjusted q-axis voltage command signal 1228 such that the negative sequence currents caused by the transient event are reduced or eliminated. In an alternative embodiment, the d-axis voltage command signal 1218 and the q-axis voltage command signal 1228 also can be transformed into a phase angle command signal and a voltage magnitude command signal back and then be sent to the signal generator 240 according to the calculating capability of the signal generator 240. in other embodiments (not shown), the phase angle command signal 216 and the voltage magnitude command signal 226 can be adjusted into other appropriate coordinates for corresponding algorithms.

[0041 ] FIG. 4 illustrates a control diagram of the negative sequence current compensation unit 290 shown in FIG. 2 in accordance with one embodiment of the present disclosure which is also applicable to the negative sequence current compensation unit 1290 of FIG. 3. In the illustrated embodiment of FIG. 4, the negative sequence current compensation unit 290 includes a negative sequence current detector 293 and a negative sequence current regulator 295. The negative sequence current detector 293 is used to receive the feedback current signal 154 and extract negative sequence current 294 from the feedback current signal 154. The negative sequence current regulator 295 is used to generate the pair of negative sequence current correction signals 291 and 292 according to the negative sequence information (namely the negative sequence current 294) of the feedback current signal 154 and the negative sequence current command signal 155.

[ΘΘ42] FIG, 5 illustrates a detailed control diagram of the negative sequence current detector 293 shown in FIG. 4 in accordance with one embodiment of the present disclosure. In the illustrated embodiment of FIG. 5, the negative sequence current detector 293 includes a coordinate transformation unit 2931 and a negative sequence selector 2934. The negative sequence current detector 293 is used to transform the three-phase feedback current signal 154 including three phase current signals 1541, 1542, 1543 into a d-axis current signal 2932 and a q-axis voltage signal 2933 in the d-q coordinate. The negative sequence selector 2934 is used to extract d- axis negative sequence current signal 2935 and q-axis negative sequence current signal 2936 from the d-axis current signal 2932 and the q-axis voltage signal 2933 respectively. In other embodiments, the feedback negative sequence current can be calculated in other kinds of coordinates, such as a stationary reference coordinate (also referred to as α-β reference coordinate).

[0043] FIG, 6 illustrates a detailed control diagram of the negative sequence current regulator 295 shown in FIG. 4 in accordance with one embodiment of the present disclosure. In the illustrated embodiment of FIG. 6, the negative sequence current regulator 295 includes a first summation element 2953, a second summation element 2954, a first virtual resistance element 2957, a second virtual resistance element 2958, and an optional coordinate transformation unit 2961 (the use of the coordinate transformation unit 2961 depends on the type of signal to be sent to the summation elements 217 and 227 of FIGs. 2 and 3, for example). The negative sequence current regulator 295 is configured to receive the negative sequence current command signal which includes a pair of current command signals 29 1, 2952 and receive the pair of negative sequence current feedback signals 2935, 2936 and to then generate the pair of negative sequence current correction signals 2959 and 2960 based at least on the current command signals 2951 , 2952 and the current feedback signal 2935, 2936. The pair of current command signals 2951, 2952 represent the desired negative sequence currents to be generated by the line side converter 144 (see FIG. 1) and may be dictated by a grid operator or a design parameter, such as zero amperes or 50 amperes, for example. The current feedback signals 2935, 2936 represent the actual negative sequence currents in d-q coordinate.

[0044] In the illustrated embodiment of FIG. 6, the first summation element 2953 subtracts the negative sequence current feedback signal 2935 from the negative sequence current command signal 2951 and provides a d-axis negative sequence current error signal 2955 representing a difference between the negative sequence current command signal 2951 and the negative sequence current feedback signal 2935. The second summation element 2954 subtracts the negative sequence current feedback signal 2936 from the negative sequence current command signal 2952 and provides a q-axis negative sequence current error signal 2956 representing a difference between the negative sequence current command signal 2952 and the negative sequence current feedback signal 2936, The first virtual resistance element 2957 and the second virtual resistance element 2958 represent a desired first gain and a desired second gain respectively. In the embodiment of FIG, 6, the first and second gains are virtual resistance parameters that may be selected by a grid operator, for example, and that may be adjusted as discussed below, in one embodiment, the first virtual resistance element 2957 (first gain) is equal to the second virtual resistance element 2958 (second gain). In an alternative embodiment, the first virtual resistance element 2957 may be different from the second virtual resistance element 2958.

[0045] In the embodiment of FIG. 6, the d-axis negative sequence current error signal 2955 is supplied to the first virtual resistance element 2957 and then a d-axis resistance compensation voltage signal 2959 (also referenced as the negative sequence current correction signals 1291 in FIG, 3) is generated by multiplying the first virtual resistance element 2957 with the d-axis negative sequence current error signal 2955. Similarly, the q-axis negative sequence current error signal 2956 is supplied to the second virtual resistance element 2958 and then a q-axis resistance compensation voltage signal 2960 (also referenced as the negative sequence current correction signals 1292 in FIG. 3) is generated by multiplying the second virtual resistance element 2958 with the q-axis negative sequence current error signal 2956. Then, the d-axis resistance compensation voltage signal 2959 and the q-axis resistance compensation voltage signal 2960 can be used to compensate the voltage command signals 1216 and 1226 in the embodiment of FIG. 3, for example.

[0046] For using the d~axis resistance compensation voltage signal 2959 and the q-axis resistance compensation voltage signal 2960 in the embodiment of FIG. 2, the coordinate transformation unit 2961 may be used to transform these signals into the pair of negative sequence current correction signals 291 and 292. in the embodiment of FIG. 6, the first virtual resistance element 2957 and the second virtual resistance element 2958 will add damping in the system, which can limit transient currents (also called dynamic currents) when the disturbance happens to the system due to undesired negative sequence currents. [0047] In one implementation, the negative sequence current correction signals are used for adjusting the command signals whenever there is a detected negative sequence current. In another implementation, the negative sequence current regulator 295 may be configured to send the negative sequence current correction signals only when the undesired negative sequence current exceeds a certain level. More specifically, the negative sequence current regulator 295 may be configured with a current error threshold value or a current error threshold range. In this example, when the d-axis negative sequence current error signal 2955 and the q-axis negative sequence current error signal 2956 are below the predetermined current error threshold value or located within a predetermined current error threshold range, the negative sequence current correction signals are blocked from being transmitted to the summation elements 217 and 227 of FIGs. 2 and 3. When the d-axis negative sequence current error signal 2955 and the q-axis negative sequence current error signal 2956 exceed the predetermined current error threshold value or are located outside the current error threshold range, the negative sequence current correction signals are provided to the summation elements 217 and 227 of FIGs. 2 and 3 for adjusting the command signals. With this current error threshold configuration or this current error threshold range configuration, the power conversion system 10 only responds to large negative sequence currents or large signal disturbances occurring in the grid 18.

[0048] FIG. 7 illustrates a detailed control diagram of the negative sequence current regulator 295 shown in FIG. 4 in accordance with another embodiment of the present disclosure. In contrast to the embodiment of FIG. 6, the negative sequence current regulator 295 of FIG. 7 further includes a first virtual inductance element 2966, a second virtual inductance element 2967, a third summation element 2964, and a fourth summation element 2965. The first virtual inductance element 2966 together with the first virtual resistance element 2957 provides the first gain, and the second virtual inductance element 2967 together with the second virtual resistance element 2958 provides the second gain. The first virtual inductance element 2966 is configured to receive the d-axis negative sequence current signal 2935 and then generate a d-axis inductance compensation voltage signal 2982. The second virtual inductance element 2967 is configured to receive the q-axis negative sequence current signal 2936 and then generate a q-axis inductance compensation voltage signal 2983. The third summation element 2964 is configured to get a sum of the d-axis resistance compensation voltage signal 2959 and the q-axis inductance compensation voltage signal 2983, and then output a d-axis comprehensive compensation voltage signal 2980 (also referenced as the negative sequence current correction signals 1291 in FIG. 3). The fourth summation element 2965 is configured to get a difference between the q-axis resistance compensation voltage signal 2960 and the d-axis inductance compensation voltage signal 2982, and then output a q-axis comprehensive compensation voltage signal 2981 (also references as the negative sequence current correction signals 1292 in FiG. 3).

[0049J In this embodiment of FIG, 7, the d-axis comprehensive compensation voltage signal 2980 and the q-axis comprehensive compensation voltage signal 2981 in the d~q coordinate may be used directly in embodiments such as that of FIG. 3 or may be transformed into the pair of negative sequence current correction signals in polar coordinate by the coordinate transformation unit 2961 for use as signals 291 and 292 in the embodiment of FIG, 2. In addition to the compensation from the first virtual resistance element 2957 and the second virtual resistance element 2958 mentioned above with respect to FIG, 6, the first virtual inductance element 2966 and the second virtual inductance element 2967 will further provide supplementary compensation which is to decouple the internal effect between d-axis and q-axis for the system. In other embodiments, the input signals of the first virtual inductance element 2966 and the second virtual inductance element 2967 may alternatively comprise the current command signals 2951 and 2952 (in dotted lines) respectively. In still other embodiments, the input signals may comprise both of the d-axis negative sequence current signal 2935 and the current command signals 2951 and both of the q-axis negative sequence current signal 2936 and current command signals 2952, respectively.

[0050] FIG. 8 illustrates a detailed control diagram of the negative sequence current regulator 295 shown in FIG. 4 in accordance with another embodiment of the present disclosure. In comparison with the embodiment of FIG. 7, the negative sequence current regulator 295 of FIG. 8 further includes a d-axis integrating element 2962 and a q-axis integrating element 2963 for providing integrating functions in the system. The d-axis integrating element 2962 together with the first virtual inductance element 2966 and the first virtual resistance element 2957 provides the first gain, and the q-axis integrating element 2963 together with the second virtual inductance element 2967 and the second virtual resistance element 2958 provides the second gain. The d-axis integrating element 2962 is configured to receive the d-axis negative sequence current error signal 2955 and then generate a d-axis integrating compensation voltage signal 2984. The q-axis integrating element 2963 is configured to receive the q-axis negative sequence current error signal 2956 and then generate a q~axis integrating compensation voltage signal 2985, The third summation element

2964 is configured to get a sum of the d-axis resistance compensation voltage signal

2959, the q~axis inductance compensation voltage signal 2983, and the d-axis integrating compensation voltage signal 2984, and then output the d-axis comprehensive compensation voltage signal 2980. The fourth summation element

2965 is configured to get a sum of the q-axis resistance compensation voltage signal

2960, the negative of the d-axis inductance compensation voltage signal 2982, and the q-axis integrating compensation voltage signal 2985, and then output the q-axis comprehensive compensation voltage signal 2981 .

[00511 The d-axis comprehensive compensation voltage signal 2980 and the q- axis comprehensive compensation voltage signal 2981 in the d~q coordinate may be transformed into the pair of negative sequence current correction signals 291 and 292 in polar coordinate by the coordinate transformation unit 296 i . In addition to the compensation from the first virtual resistance element 2957, the second virtual resistance element 2958, the first virtual inductance element 2966, and the second virtual inductance element 2967 mentioned above, the d-axis integrating element 2962 and the q-axis integrating element 2963 will further provide supplementary compensation to reduce steady state err for the system, to ensure the steady performance thereof. More specifically, the d-axis integrating element 2962 and the q-axis integrating element 2963 are configured to handle unbalanced voltages existing in the system caused by modulation or transformer unbalance in the steady state. [0052| FIG. 9 illustrates a detailed control diagram of the negative sequence current regulator 295 shown in FIG. 4 in accordance with yet another embodiment of the present disclosure. In comparison with the embodiment of FIG. 7, the negative sequence current regulator 295 of FIG. 9 further receives a d-axis negative sequence voltage signal 2968 to add into the d-axis comprehensive compensation voltage signal 2980 through the third summation element 2964, and receives a q-axis negative sequence voltage signal 2969 to add into the q-axis comprehensive compensation voltage signal 2981 through the fourth summation element 2965. In one embodiment, the d-axis negative sequence voltage signal 2968 and q-axis negative sequence voltage signal 2969 can be obtained from the three-phase feedback voltage signal 152 (FIG. i) by applying the similar algorithm shown in FIG. 5 as described with respect to the three-phase feedback current signal 154. In other embodiments, the d-axis negative sequence voltage signal 2968 and q-axis negative sequence voltage signal 2969 may be obtained by other methods.

[0053] If desired, the d-axis negative sequence voltage signal 2968 and q-axis negative sequence voltage signal 2969 may be pre-processed via filters and/or limiters (not shown). For example, FIG. 10 shows an embodiment in which two filters 2970 and 2971 are further respectively introduced in the paths of the d-axis negative sequence voltage signal 2968 and q-axis negative sequence voltage signal 2969 to extract a certain frequency signal or range of frequency signals from the detected voltage to compensate the negative sequence voltages. Thus, the d-axis negative sequence voltage signal 2968 and q-axis negative sequence voltage signal 2969 are filtered by the filter 2970 and filter 2971 , and then the filtered d-axis negative sequence voltage 2972 and the filtered q-axis negative sequence voltage 2973 are respectively added into the d-axis comprehensive compensation voltage signal 2980 through the third summation element 2964, and into the q-axis comprehensive compensation voltage signal 2981 through the fourth summation element 2965.

[0054J In the two embodiments of FIGs. 9 and 10, the d-axis comprehensive compensation voltage signal 2980 and the q-axis comprehensive compensation voltage signal 2981 in the d-q coordinate may be transformed into the pair of negative sequence current correction signals 291 and 292 in polar coordinate by the coordinate transformation unit 2961. in addition to the compensation from the first virtual resistance element 2957, the second virtual resistance element 2958, the first virtual inductance element 2966, and the second virtual inductance element 2967 mentioned above, the d-axis negative sequence voltage signal 2968 and q-axis negative sequence voltage signal 2969 as voltage compensation signals will further provide supplementary compensation to the fast change of negative sequence voltage in the grid. In other words, the d-axis negative sequence voltage signal 2968 and q-axis negative sequence voltage signal 2969 are used to correct the initial state when the negative sequence voltage disturbance suddenly changes (such as moving into a negative sequence voltage disturbance, moving out of a negative sequence voltage disturbance, or experiencing a large change in magnitude of a negative sequence voltage level).

|00551 FIG. 1 1 illustrates a detailed control diagram of the negative sequence current regulator 295 shown in FIG. 4 in accordance with yet another embodiment of the present disclosure. In comparison with the embodiment of FIG. 8, the negative sequence current regulator 295 of FIG. 1 1 further receives the d-axis negative sequence voltage signal 2968 to add into the d-axis comprehensive compensation voltage signal 2980 through the third summation element 2964, and receives the q- axis negative sequence voltage signal 2969 to add into the q-axis comprehensive compensation voltage signal 2981 through the fourth summation element 2965 in a similar manner as discussed above with respect to FIG. 9. In other embodiments, the negative sequence cuixent regulator 295 also can add other kinds of compensation if desired.

[0056] FIG. 12 illustrates a control diagram of the negative sequence current compensation unit 1290 shown in FIG. 3 in accordance with another exemplary embodiment of the present disclosure. In comparison to the embodiment of FIG. 4, the negative sequence current correction signals 1291 and 1292 of FIG. 12 are further processed before being sent to the summation elements 217 and 227 shown in FIG. 3. In this embodiment of FIG. 12, on the transmission path of the negative sequence current correction signal 1291, a first filter 296, a first comparator 301, and a first compensation element 305 are introduced. Similarly, on the transmission path of the negative sequence current correction signal 1292, a second filter 297, a second comparator 302, and a second compensation element 306 are introduced. More particularly, the first filter 296 and the second filter 297 are configured to perform signal filtering operations to remove any high-frequency noise signals therein, and then two filtered negative sequence current correction signals 298 and 299 are generated.

[0057] The first comparator 301 and the second comparator 302 each may comprise a hysteresis function defined with an upper threshold value and a lower threshold value. The first comparator 301 and the second comparator 302 determine whether the filtered negative sequence current correction signals 298 and 299 are located within the upper phase threshold value and the lower threshold value, and block the filtered negative sequence current correction signals 298 and 299 when they are determined within the predetermined range. If the filtered negative sequence current correction signals 298 and 299 are determined to be outside the predetermined range, the first comparator 301 and the second comparator 302 allow the filtered negative sequence current correction signals 298 and 299 to pass through after which then two compared power feedback signals 303 and 304 are generated. With this phase angle range and voltage magnitude range configuration, the negative sequence current compensation unit 290 only responds to large signal disturbances,

[0058] The first compensation element 305 and the second compensation element 306 are configured to apply gain efficient to the compared negative sequence current correction signals 303 and 304, and then two compensated negative sequence current correction signals 307 and 308 are generated. After that, the compensated negative sequence current correction signals 307 and 308 are sent to the signal generator 240 through the summation elements 217 and 227. In other embodiments, one or two of the filter, the comparator, and the compensation element also can be used in one of the transmission paths of the negative sequence current correction signals 291 and 292 according to different requirements. If desired, other kinds of signal processing elements also can be used to preprocess the negative sequence current correction signals. [0059] FIG, 13 illustrates a simulation diagram to show the performance after applying the negative sequence current compensation unit. As shown in FIG. 13, a large negative sequence current in d-q coordinate generated during a grid fault process occurs at 3.0 seconds, and the negative sequence current compensation unit is applied in the system at 3.2 seconds. During the period from 3.0 and 3.2, without the negative sequence current compensation, the q-axis negative sequence current A and the d-axis negative sequence current B respectively reach 1.2KA and -2KA at the maximum. However, after adding the negative sequence current compensation unit, the q-axis negative sequence current A and the d-axis negative sequence current B are respectively reduced to 400A and OA. Therefore, the negative sequence current compensation unit is expected to have a good limitation on the undesired negative sequence currents which can make the grid 18 more stable.

[0060] FIG. 14 illustrates a control diagram implemented by the line side controller 164 shown in FIG. 1 in accordance with another exemplary embodiment. In comparison to the embodiment of FiG. 2, in FIG. 34 a first limiter 230 and a second limiter 260 are added. The first limiter 230 is configured to limit the adjusted phase angle command signal 218 and the adjusted voltage magnitude command signal 228 according to predetermined current threshold values. The limited phase angle command signal 232 and the limited voltage magnitude command signal 234 may be supplied to the signal generator 240 for generation of the PWM signals that are used for driving the switching devices of the line side converter 144. In alternative embodiments, the first limiter 230 also can be configured to limit the phase angle command signal 216 and the voltage magnitude command signal 226 before sending to the summation element 217 and 227. The second limiter 260 is configured to limit the negative sequence current correction signals 291 and 292 according to predetermined current threshold values, and then the limited negative sequence current correction signals 312 and 314 are sent to the summation elements 217 and 227. The negative sequence current correction signals 129 and 1292 of FIG. 3 also can be limited by one or more such limiters if desired.

[0061] FIG. 15 illustrates a control diagram implemented by the line side controller 164 shown in FIG. 1 in accordance with another exemplary embodiment. In comparison to the embodiment of FIG. 2, FIG. 15 further illustrates a phase jump compensation unit 250 is further included. The phase jump compensation unit 250 is coupled to the active power regulator 210. In an alternative embodiment (not shown), the phase jump compensation unit 250 may be coupled to the reactive power regulator 220). in general, phase jump compensation unit 250 is configure for tracking the grid voltage signal 152 and providing more timely phase jump information for compensation when phase detection devices such as a phase locked loop (PLL) circuit cannot detect the correct phase angle information as quickly as desired. f§062] While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

CLAIMS:

1. A power conversion system comprising: a direct current (DC) bus for receiving DC power from a power source; a power converter for converting the DC power on the DC bus to alternating current (AC) power; and a controller coupled to the power converter for executing the steps of: generating a first command signal based on an active power command signal and an active power feedback signal; generating a second command signal based on a reactive power command signal and a reactive power feedback signal; and compensating for negative sequence currents by generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal, adjusting the first command signal and the second command signal based on the first and second negative sequence current correction signals respectively, and generating control signals for the power converter based on the adjusted first and second command signals to cause an AC voltage output from the power converter to reduce the negative sequence currents,

2. The power conversion system of claim 1 , wherein the controller comprises a negative sequence current compensation unit for generating the first and second negative sequence current correction signals, wherein the negative sequence current compensation unit comprises: a negative sequence current detector for receiving the grid current signal and extracting negative sequence current signal from the grid current signal; and a negative sequence current regulator for receiving the negative sequence current signal and calculating the first and second negative sequence current correction signals based on the negative sequence current signal and the negative sequence current command signal

3, The power conversion system of claim 2, wherein the negative sequence current detector comprises: a coordinate transformation unit for transforming the grid current signal from three-phase coordinate into a d-axis current signal and a q-axis current signal in d-q coordinate; and a negative sequence selector for extracting a d-axis negative sequence current signal and a q-axis negative sequence current signal from the d-axis current signal and the q-axis current signal respectively,

4. The power conversion system of claim 3, wherein the negative sequence current regulator comprises: a first summation element for subtracting the d-axis negative sequence current signal from a d-axis negative sequence current command signal of the negative sequence current command signal, and providing a d-axis negative sequence current error signal; a second summation element for subtracting the q-axis negative sequence current signal from a q-axis negative sequence current command signal of the negative sequence current command signal, and providing a q-axis negative sequence current error signal; a first virtual resistance element for generating a d-axis resistance compensation voltage signal based on the d-axis negative sequence current error signal; and a second virtual resistance element for generating a q-axis resistance compensation voltage signal based on the q-axis negative sequence current error signal.

5. The power conversion system of claim 4, wherein the negative sequence current regulator further comprises: a first virtual inductance element for generating a d-axis inductance compensation voltage signal based on one of the d-axis negative sequence current signal, the d-axis negative sequence current command signal, or a combination thereof; a second virtual inductance element for generating a q-axis inductance compensation voltage signal based on one of the q-axis negative sequence current signal, the q-axis negative sequence current command signal, or a combination thereof; a third summation element for adding the q-axis inductance compensation voltage signal into the d-axis resistance compensation voltage signal, and providing a d-axis comprehensive compensation voltage signal; and a fourth summation element for subtracting the d-axis inductance compensation voltage signal from the q-axis resistance compensation voltage signal, and providing a q~axis comprehensive compensation voltage signal.

6. The power conversion system of claim 5, wherein the negative sequence current regulator further comprises: a d-axis integrating element for generating a d-axis integrating compensation voltage signal based on the d-axis negative sequence current error signal; and a q-axis integrating element for generating a q-axis integrating compensation voltage signal based on the q-axis negative sequence current error signal; wherein the third summation element further adds the d-axis integrating compensation voltage signal into the d~axis comprehensive compensation voltage signal; wherein the fourth summation element further adds the q~axis integrating compensation voltage signal into the q-axis comprehensive compensation voltage signal.

7. The power conversion system of claim 5, wherein the third summation element further adds a detected d~axis negative sequence voltage signal into the d-axis comprehensive compensation voltage signal, and wherein the fourth summation element further adds a detected q-axis negative sequence voltage signal into the q-axis comprehensive compensation voltage signal.

8. The power conversion system of claim 7, wherein the negative sequence current regulator further comprises: a first filter for filtering the d-axis negative sequence voltage signal before summation into the d-axis comprehensive compensation voltage signal; and a second filter for filtering the q-axis negative sequence voltage signal before summation into the q-axis comprehensive compensation voltage signal.

9. The power conversion system of claim 1 , wherein the first command signal comprises a phase angle command signal or a d-axis voltage signal, and wherein the second command signal comprises a voltage magnitude command signal or a q-axis voltage signal.

10. The power conversion system of claim 1 , further comprising a first filter, a first comparator, and a first compensation element for pre-processing the first negative sequence current before adjusting the first command signal, and a second filter, a second comparator, and a second compensation element for pre-processing the second negative sequence current correction signal before adjusting the second command signal.

1 1. The power conversion system of claim 1 , wherein the controller further comprises a limiter for limiting the adjusted first command signal according to a current threshold value and limiting the adjusted second command signal according to a current threshold value.

12. The power conversion system of claim 1 , wherein the controller further comprises a phase jump compensation unit for tracking a grid voltage signal and providing phase jump compensation based on the tracked grid voltage signal

13. A method of operating a power conversion system comprising: generating a first command signal based on an active power command signal and an active power feedback signal; generating a second command signal based on a reactive power command signal and a reactive power feedback signal; generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal; adjusting the first command signal and the second command signal based on the first and second negative sequence current correction signals respectively; and generating control signals for a power converter of the power conversion system for causing an AC voltage output from the power converter to reduce the negative sequence currents based on the adjusted first and second command signals.

14. The method of claim 13, further comprising: extracting a d-axis negative sequence current signal and a q-axis negative sequence current signal from the detected grid current signal and extracting a d~axis negative sequence current command signal and a q-axis negative sequence current command signal from the negative sequence current command signal, for generating the first and second negative sequence current correction signals,

15. The method of claim 14, wherein the step of generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal comprises: subtracting the d-axis negative sequence current signal from a d-axis negative sequence current command signal, and providing a d-axis negative sequence current error signal; subtracting the q-axis negative sequence current signal from a q~axis negative sequence current command signal, and providing a q-axis negative sequence current error signal; generating a d-axis resistance compensation voltage signal based on the d-axis negative sequence current error signal multiplying a first virtual resistance element; and generating a q-axis resistance compensation voltage signal based on the q-axis negative sequence current error signal multiplying a second virtual resistance element.

16. The method of claim 15, wherein the step of generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal farther comprises: generating a d-axis inductance compensation voltage signal based on one of the d-axis negative sequence current signal, the d-axis negative sequence current command signal, or a combination thereof multiplying a first virtual inductance element; generating a q-axis inductance compensation voltage signal based on one of the q-axis negative sequence current signal, the q-axis negative sequence current command signal, or a combination thereof multiplying a second virtual inductance element; adding the q-axis inductance compensation voltage signal into the d~axis resistance compensation voltage signal, and providing a d-axis comprehensive compensation voltage signal; and subtracting the d-axis inductance compensation voltage signal from the q-axis resistance compensation voltage signal, and providing a q-axis comprehensive compensation voltage signal.

17. The method of claim 16, wherein the step of generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal further comprises: generating a d-axis integrating compensation voltage signal based on the d-axis negative sequence current error signal multiplying a d-axis integrating element; generating a q-axis integrating compensation voltage signal based on the q- axis negative sequence current error signal multiplying a q-axis integrating element; further adding the d-axis integrating compensation voltage signal into the d- axis comprehensive compensation voltage signal; and further adding the q-axis integrating compensation voltage signal into the q- axis comprehensive compensation voltage signal.

18. The method of claim 16, wherein the step of generating a first negative sequence current correction signal and a second negative sequence current correction signal based on a detected grid current signal and a negative sequence current command signal further comprises: adding a detected d-axis negative sequence voltage signal into the d-axis comprehensive compensation voltage signal; and adding a detected q-axis negative sequence voltage signal into the q-axis comprehensive compensation voltage signal.

19. The method of claim 13, before adjusting the first command signal and the second command signal, further comprising: filtering, limiting, and compensating the first and second command signals.

20. The method of claim 13, further comprising: limiting the adjusted first and second command signals and limiting the first and second negative sequence curreni correction signals according to predetermined current threshold values.