WO2013121536A1 - Semiconductor storage device - Google Patents

Semiconductor storage device Download PDF

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Publication number
WO2013121536A1
WO2013121536A1 PCT/JP2012/053532 JP2012053532W WO2013121536A1 WO 2013121536 A1 WO2013121536 A1 WO 2013121536A1 JP 2012053532 W JP2012053532 W JP 2012053532W WO 2013121536 A1 WO2013121536 A1 WO 2013121536A1
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WO
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Prior art keywords
diffusion layer
gate
layer
transistor
transistors
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PCT/JP2012/053532
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French (fr)
Japanese (ja)
Inventor
舛岡　富士雄
紳太郎 新井
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
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Application filed by ユニサンティス エレクトロニクス シンガポール プライベート リミテッド filed Critical ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority to KR1020137021567A priority Critical patent/KR20130116334A/en
Priority to PCT/JP2012/053532 priority patent/WO2013121536A1/en
Priority to CN2012800090242A priority patent/CN103370781A/en
Priority to TW102105176A priority patent/TW201336052A/en
Publication of WO2013121536A1 publication Critical patent/WO2013121536A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Definitions

  • the present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device made of SRAM (Static Random Access to Memory).
  • SRAM Static Random Access to Memory
  • a columnar semiconductor is formed on the surface of a semiconductor substrate, and an SGT (vertical gate transistor having a gate formed so as to surround the columnar semiconductor layer on a sidewall thereof.
  • SGT vertical gate transistor having a gate formed so as to surround the columnar semiconductor layer on a sidewall thereof.
  • Patent Document 1 JP-A-2-188966
  • the drain, gate and source are arranged in the vertical direction, so that the occupied area can be greatly reduced as compared with the conventional planar type transistor.
  • Patent Document 2 International Publication No. W02009 / 096466 shows a Loadless 4T-SRAM formed on an SOI substrate using four SGTs.
  • An equivalent circuit diagram of the Loadless 4T-SRAM is shown in FIG.
  • FIG. 21 is a plan view of the Loadless 4T-SRAM disclosed in Patent Document 2
  • FIG. 22 is a cross-sectional view thereof.
  • the operation principle of the Loadless 4T-SRAM will be described below using the equivalent circuit of the Loadless 4T-SRAM shown in FIG.
  • the Loadless 4T-SRAM is composed of a total of four transistors: two access transistors for accessing a memory which is a PMOS and two driver transistors for driving a memory which is an NMOS.
  • a data holding operation in the case where “L” data is stored in the storage node Qa1 and “H” data is stored in the storage node Qb1 will be described below.
  • the word line WL1 and the bit lines BL1 and BLB1 are all driven to the “H” potential.
  • the off-leakage current of the access transistors (Qp11, Qp21) is set to be, for example, about 10 to 1000 times larger than the off-leakage current of the driver transistor. Therefore, the “H” level of the storage node Qb1 is held by the off leak current flowing from the bit line BLB1 to the storage node Qb1 through the access transistor Qp21. On the other hand, the “L” level of storage node Qa1 is stably held by driver transistor Qn11.
  • FIG. 21 shows a layout diagram of a conventional SRAM memory cell.
  • the unit cells UC shown in FIG. 21 are repeatedly arranged in the SRAM cell array.
  • 22A to 22D show cross-sectional structures taken along cut lines A-A ′, B-B ′, C-C ′, and D-D ′ in the layout diagram of FIG.
  • the storage nodes (602a, 602b) are formed by a silicon layer formed on the buried oxide film layer 601, and the silicon layer is subjected to impurity implantation or the like, thereby performing N + diffusion layer regions (604a, 604b) and P + diffusion. It consists of layer regions (603a, 603b).
  • Qp16 and Qp26 indicate access transistors, and Qn16 and Qn26 indicate driver transistors.
  • Contact 610a formed on storage node 602a is connected to contact 611b formed on the gate wiring extending from the gate electrode of driver transistor Qn26 by node connection wiring Na6, and contact 610b formed on storage node 602b is Node connection wiring Nb6 connects to contact 611a formed on the gate wiring extending from the gate electrode of driver transistor Qn16.
  • Contact 606a formed on access transistor Qp16 is connected to bit line BL6, and contact 606b formed on access transistor Qp26 is connected to bit line BLB6.
  • Contact 607 formed on the gate wiring extending from the gate electrodes of access transistors Qp16 and Qp26 is connected to word line WL6.
  • the contacts (608a, 608b) formed on the driver transistors (Qn16, Qn26) are both connected to the wiring layer Vss6, which is the ground potential.
  • P + source diffusion layers (603a, 603b) made of silicon layers as storage nodes (602a, 602b) are formed on the buried oxide film layer 601, respectively.
  • Silicide layers (613a and 613b) are formed on the source diffusion layer.
  • a columnar silicon layer 621a for forming the access transistor Qp16 is formed on the P + source diffusion layer region 603a, and a columnar silicon layer 621b for forming the access transistor Qp26 is formed on the P + source diffusion layer region 603b.
  • a gate insulating film 617 and a gate electrode 618 are formed around each columnar silicon layer.
  • a P + drain diffusion layer region 616 is formed on the columnar silicon layer by impurity implantation, and a silicide layer 615 is formed on the surface of the drain diffusion layer region.
  • Contact 606a formed on access transistor Qp16 is connected to bit line BL6, contact 606b formed on access transistor Qp26 is connected to bit line BLB6, and gate line 618a extends from the gates of access transistors Qp16 and Qp26.
  • a contact 607 formed above is connected to the word line WL6.
  • N + source diffusion layers (604a, 604b) made of silicon layers as storage nodes (602a, 602b) are formed on the buried oxide film layer 601, respectively.
  • Silicide layers (613a and 613b) are formed on the source diffusion layer.
  • Contact 611a formed on gate line 618b extending from the gate electrode of driver transistor Qn16 is connected to contact 610b formed on N + source diffusion layer 604b through storage node connection line Na6.
  • N + source diffusion layers (604a, 604b) made of a silicon layer as a storage node are formed on the buried oxide film layer 601. Silicide layers (613a and 613b) are formed on the N + source diffusion layer.
  • a columnar silicon layer 622a for forming the driver transistor Qn16 is formed in the N + source diffusion layer region 604a, and a columnar silicon layer 622b for forming the driver transistor Qn26 is formed in the N + source diffusion layer region 604b.
  • a gate insulating film 617 and a gate electrode 618 are formed around each columnar silicon layer.
  • An N + drain diffusion layer region 614 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 615 is formed on the surface of the drain diffusion layer region.
  • the contacts (608a, 608b) formed on the driver transistors (Qn16, Qn26) are both connected to the ground potential Vss6 through the wiring layer.
  • a P + source diffusion layer 603a and an N + source diffusion layer 604a made of a silicon layer as a storage node are formed on the buried oxide film layer 601.
  • a silicide layer 613a is formed on the source diffusion layer, and the P + source diffusion layer 603a and the N + source diffusion layer 604a are connected by the silicide layer 613a.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to realize a Loadless 4T-SRAM cell using an SGT having a smaller cell area than the conventionally proposed Loadless 4T-SRAM using an SGT.
  • the present invention provides a semiconductor memory device including a plurality of static memory cells in which four MOS transistors are arranged on an insulating film formed on a substrate, Each of the four MOS transistors is First and second PMOS access transistors for supplying charge to hold memory cell data and accessing the memory, and for driving the storage node to write and read data in the memory cell Functions as a second NMOS driver transistor, In the first and second PMOS access transistors, A first diffusion layer having a P-type conductivity, a first columnar semiconductor layer, and a second diffusion layer having a P-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on a substrate.
  • the first columnar semiconductor layer is disposed, and the first diffusion layer formed on the bottom of the first columnar semiconductor layer and the second diffusion layer formed on the top of the first columnar semiconductor layer A gate insulating film and a gate are formed on sidewalls of the first columnar semiconductor layer,
  • a third diffusion layer having an N-type conductivity, a second columnar semiconductor layer, and a fourth diffusion layer having an N-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on the substrate.
  • the second columnar semiconductor layer is disposed, and the third diffusion layer formed on the bottom of the second columnar semiconductor layer and the fourth diffusion layer formed on the top of the first columnar semiconductor layer.
  • a gate insulating film and a gate are formed on sidewalls of the second columnar semiconductor layer,
  • the first PMOS access transistor and the first NMOS driver transistor are arranged adjacent to each other,
  • the second PMOS access transistor and the second NMOS driver transistor are arranged adjacent to each other,
  • the first diffusion layer having the P-type conductivity formed at the bottom of the first PMOS access transistor and the first NMOS driver transistor functioning as a first storage node for holding data Disposing the third diffusion layer having the N-type conductivity type formed on the bottom on the insulating film;
  • the first diffusion layer and the third diffusion layer functioning as the first storage node are connected to each other,
  • the first diffusion layer having the P-type conductivity formed at the bottom of the second PMOS access transistor and the second NMOS driver transistor functioning as a second storage node for holding data Disposing the third diffusion layer having the N-type conductivity type formed on the bottom on the insulating film;
  • the first diffusion layer and the third diffusion layer functioning as the second storage node are connected
  • a word line is formed by being connected to each gate of the access transistors of Provided is a semiconductor memory device, wherein a first contact is formed on the first gate wiring which is a word line for each of a plurality of adjacent memory cells.
  • a pillar is disposed in the region where the first contact is formed on the first gate wiring which is the word line, similarly to the memory cell.
  • An apparatus is provided.
  • a second gate wiring extending from a gate of the first NMOS driver transistor is connected to a diffusion layer functioning as the second storage node by a second contact in common, and 3.
  • a semiconductor memory device characterized in that a third gate wiring extending from the gate of the second NMOS driver transistor is connected to the diffusion layer functioning as the first storage node by a common third contact.
  • the peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS driver transistors is the side wall of the columnar semiconductor layer forming the first and second PMOS access transistors.
  • the columnar semiconductor layer forming the first and second NMOS driver transistors has a columnar shape forming the first and second PMOS access transistors.
  • a semiconductor memory device having a value equal to or less than the peripheral length of the side wall of the semiconductor layer.
  • the four MOS transistors are arranged in two rows and two columns on the insulating film, the first PMOS access transistors are arranged in the first row and first column, and the first transistors The NMOS driver transistor is arranged in the second row and the first column, the second PMOS access transistor is arranged in the first row and the second column, and the second NMOS driver transistor is arranged in the second row and the second column.
  • a semiconductor memory device is provided.
  • the four MOS transistors are arranged on the insulating film, the first PMOS access transistor and the second PMOS access transistor are arranged adjacent to each other, and the first PMOS access transistor is arranged adjacent to the first PMOS access transistor.
  • the first NMOS driver transistor is arranged adjacent to the first PMOS access transistor in one direction orthogonal to the adjacent direction of the PMOS access transistor and the second PMOS access transistor
  • the second NMOS driver transistor is arranged adjacent to the second PMOS access transistor in the other direction orthogonal to the adjacent direction of the second PMOS access transistor and the second PMOS access transistor.
  • semiconductor memory device characterized by It is.
  • 1 is a plan view of an SRAM showing a first embodiment of the present invention.
  • 1 is a plan view of an SRAM showing a first embodiment of the present invention.
  • 1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention.
  • 1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention.
  • 1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention.
  • 1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention.
  • 1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention. It is process drawing which shows the manufacturing method of this invention in process order.
  • SRAM which shows the 3rd Example of this invention. It is a top view of SRAM which shows the 4th Example of this invention. It is a top view of SRAM which shows the 5th Example of this invention. It is a top view of SRAM which shows the 5th Example of this invention. It is a top view which shows SRAM using the conventional SGT. It is sectional drawing which shows SRAM using the conventional SGT. It is sectional drawing which shows SRAM using the conventional SGT. It is sectional drawing which shows SRAM using the conventional SGT. It is sectional drawing which shows SRAM using the conventional SGT. It is sectional drawing which shows SRAM using the conventional SGT.
  • FIG. 2 shows a layout diagram of the SRAM memory cell in the first embodiment of the present invention.
  • the unit cells UC shown in FIG. 2 are repeatedly arranged in the SRAM memory cell array.
  • FIGS. 3A to 3D show cross-sectional structures along cut lines A-A ′, B-B ′, C-C ′, and D-D ′ in the layout diagram of FIG.
  • one unit cell UC includes transistors arranged in 2 rows and 2 columns on a substrate.
  • an access transistor Qp11 and a driver transistor Qn11 are arranged on the first storage node Qa1 from the upper side of the drawing, respectively.
  • an access transistor Qp21 and a driver transistor Qn21 are arranged on the second storage node Qb1 from the upper side in the drawing.
  • a gate wiring 134 extending from the gate of the access transistor is shared with a plurality of memory cells adjacent in the horizontal direction to form a word line.
  • the SRAM cell array of this embodiment is configured by continuously arranging unit cells UC having such four transistors in the vertical direction of the figure.
  • the storage nodes (102a, 102b) are formed of a silicon layer formed on the buried oxide film layer 101, and the silicon layer is subjected to impurity implantation or the like, so that N + diffusion layer regions (104a, 104b) and P + diffusion are formed. It consists of layer regions (103a, 103b).
  • Qp11 and Qp21 indicate access transistors, and Qn11 and Qn21 indicate driver transistors.
  • Contact 110a formed on storage node 102a is connected to contact 111b formed on the gate wiring extending from the gate electrode of driver transistor Qn21 by node connection wiring Na1, and contact 110b formed on storage node 102b is Node connection wiring Nb1 connects to contact 111a formed on the gate wiring extending from the gate electrode of driver transistor Qn11.
  • the contacts (108a, 108b) formed on the driver transistors (Qn11, Qn21) are both connected to the wiring layer Vss1 which is the ground potential.
  • Contact 106a formed on access transistor Qp11 is connected to bit line BL1
  • contact 106b formed on access transistor Qp21 is connected to bit line BLB1.
  • Gate wiring (118a) extending from the gate electrodes of access transistors Qp11 and Qp21 is connected as a word line to a plurality of memory cells adjacent in the horizontal direction.
  • the node connection wiring Na1, the node connection wiring Nb1, and the ground potential wiring Vss1 are formed by lower layer wirings, and the bit lines (BL1, BLB1) are formed by upper layer wirings. It is feasible.
  • FIG. 3A shows a plan view of a part of an SRAM memory cell array composed of a plurality of SRAM memory cells.
  • a plurality of memory cells are arranged in the horizontal direction, and the word line 118a is shared by the plurality of memory cells arranged in the horizontal direction.
  • the word line is connected to the upper layer wiring by the contact 107 formed in the contact area, and is backed by the wiring layer as necessary. Therefore, unlike the SRAM cell of Patent Document 2, it is not necessary to form a contact to the word line in each cell, so that the SRAM cell area can be reduced.
  • FIG. 3B shows a plan view of a part of an SRAM cell array composed of a plurality of SRAM cells in another case. Similarly, in the cell array area in the figure, a plurality of memory cells are arranged in the horizontal direction, and the word lines 118a are shared in the memory cells arranged in the horizontal direction. However, in FIG.
  • pillars are arranged in the contact area as well as in the cell array area. In this way, by arranging the pillars in the contact area in the same pattern as the memory cell region, the same pillar arrangement regularity as in the cell array can be maintained also in the contact area. A difference in dimension between pillars not adjacent to the area can be reduced, and an error between the characteristics of the SGT adjacent to the contact area and the SGT characteristics not adjacent to the contact area can be minimized.
  • FIG. 3 the configuration of the word lines and the word line contacts is described using the layout of the first embodiment as an example. The same configuration of word lines and word line contacts can be applied in FIG.
  • the source and drain of each transistor constituting the SRAM are defined as follows.
  • a diffusion layer formed above the columnar semiconductor layer connected to the ground voltage is defined as a source diffusion layer
  • a diffusion layer formed below the columnar semiconductor layer is defined as a drain diffusion layer.
  • the access transistors (Qp11, Qp21) depending on the operating state, both the diffusion layer formed above the columnar semiconductor layer and the diffusion layer formed below are the source or drain.
  • the diffusion layer formed in (1) is defined as the source diffusion layer
  • the diffusion layer formed under the columnar semiconductor layer is defined as the drain diffusion layer.
  • P + source diffusion layers (103a, 103b) made of silicon layers as storage nodes (102a, 102b) are formed on the buried oxide film layer 101, respectively.
  • Silicide layers (113a and 113b) are formed on the source diffusion layer.
  • a columnar silicon layer 121a for forming the access transistor Qp11 is formed on the P + source diffusion layer region 103a, and a columnar silicon layer 121b for forming the access transistor Qp21 is formed on the P + source diffusion layer region 103b.
  • a gate insulating film 117 and a gate electrode 118 are formed around each columnar silicon layer.
  • a P + drain diffusion layer region 116 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 115 is formed on the surface of the drain diffusion layer region.
  • Contact 106a formed on access transistor Qp11 is connected to bit line BL1
  • contact 106b formed on access transistor Qp21 is connected to bit line BLB1.
  • N + source diffusion layers (104a, 104b) made of silicon layers as storage nodes (102a, 102b) are formed on the buried oxide film layer 101, respectively.
  • Silicide layers (113a and 113b) are formed on the source diffusion layer.
  • Contact 111a formed on gate line 118b extending from the gate electrode of driver transistor Qn11 is connected to contact 110b formed on N + source diffusion layer 104b through storage node connection line Na.
  • N + source diffusion layers (104a, 104b) made of a silicon layer as a storage node are formed on the buried oxide film layer 101.
  • Silicide layers (113a, 113b) are formed on the N + source diffusion layer.
  • a columnar silicon layer 122a for forming the driver transistor Qn11 is formed in the N + source diffusion layer region 104a, and a columnar silicon layer 122b for forming the driver transistor Qn21 is formed in the N + source diffusion layer region 104b.
  • a gate insulating film 117 and a gate electrode 118 are formed around each columnar silicon layer.
  • An N + drain diffusion layer region 114 is formed on the columnar silicon layer by impurity implantation, and a silicide layer 115 is formed on the surface of the drain diffusion layer region.
  • the contacts (108a, 108b) formed on the driver transistors (Qn11, Qn21) are both connected to the ground potential Vss1 through the wiring layer.
  • a P + source diffusion layer 103a and an N + source diffusion layer 104a made of a silicon layer as a storage node are formed on the buried oxide film layer 101.
  • a silicide layer 113a is formed on the source diffusion layer, and the P + source diffusion layer 103a and the N + source diffusion layer 104a are connected by the silicide layer 113a.
  • the N + source diffusion layer and the P + source diffusion layer are connected by silicide.
  • the contact resistance between the N + source diffusion layer and the P + source diffusion layer is sufficiently small, it is not necessary to form silicide.
  • the N + source diffusion layer and the P + source diffusion layer are connected by contact with the N + source diffusion layer and the P + source diffusion layer by contact, or by other methods. Layers may be connected.
  • FIG. 4E shows a cross-sectional structure taken along line EE ′ of FIG.
  • a P + source diffusion layer 103 made of the silicon layer of the left cell and the right cell is formed.
  • a silicide layer 113 is formed on each source diffusion layer.
  • a columnar silicon layer 121 for forming an access transistor is formed on each P + source diffusion layer region 103, and a columnar silicon layer 121 for forming an access transistor is formed on the P + source diffusion layer region 103.
  • a gate insulating film 117 and a gate electrode 118 are formed around each columnar silicon layer.
  • a P + drain diffusion layer region 116 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 115 is formed on the surface of the drain diffusion layer region.
  • a contact 106 formed on each access transistor is connected to a bit line, and a contact 107 formed on the word line 118a is connected to a lower resistance word line formed by an upper wiring layer.
  • FIGS. An example of a manufacturing method for forming the semiconductor device of the present invention will be described below with reference to FIGS.
  • (a) is a plan view
  • (b) is a cross-sectional view taken along D-D '.
  • a silicon nitride film or the like is formed on an SOI substrate, and a pattern of columnar silicon layers (121a, 122a, 121b, 122b) is formed by lithography and etched to form a silicon nitride film.
  • a mask 119 and a columnar silicon layer (121a, 122a, 121b, 122b) are formed.
  • the silicon layer (120) is separated to form a silicon layer which is a storage node (102a, 102b).
  • impurities are introduced into the P + implantation region 124 and the N + implantation region 125 by ion implantation or the like to form drain diffusion layers (103a, 103b, 104a, 104b) below the columnar silicon layer on the substrate. To do.
  • a gate insulating film 117 and a gate conductive film 118 are formed.
  • the gate insulating film 117 is formed of an oxide film or a high-k film.
  • the gate conductive film is formed of polysilicon or a metal film.
  • a gate wiring pattern is formed by lithography using a resist 133 or the like.
  • the gate conductive film 117 and the gate insulating film 118 are etched and removed using the resist 133 as a mask. Thereby, gate wirings (118a to 118c) are formed.
  • the mask 119 on the pillar is removed by wet etching or dry etching.
  • an insulating film such as a silicon nitride film
  • it is etched back so that the sidewall of the columnar silicon layer and the sidewall of the gate electrode are covered with an insulating film 134 such as a silicon nitride film.
  • impurities are introduced into the P + implantation region 124 and the N + implantation region 125 by ion implantation or the like, respectively, to form source diffusion layers (114, 116) above the columnar silicon layer.
  • the silicide layers (113a, 113b) on the drain diffusion layer and the silicide layer 115 on the source diffusion layer above the columnar silicon layer are formed.
  • the drain-gate and source-gate short circuit due to the silicide layer can be suppressed by the insulating film 134 such as a silicon nitride film covering the columnar silicon layer and the side wall of the gate electrode.
  • contacts (106a, 106b, 108a, 108b, 110a, 110b, 111a, 111b) are formed after a silicon oxide film as an interlayer film is formed.
  • FIG. 16 shows the SRAM layout of this embodiment.
  • This embodiment is different from the first embodiment in that the shape of the columnar silicon layer forming the access transistor is different from the size of the columnar silicon layer forming the driver transistor.
  • the leakage current is set by setting the peripheral length of the columnar silicon layer forming the access transistor larger than the peripheral length of the columnar silicon layer forming the driver transistor as shown in FIG. Can be increased.
  • the peripheral length of the columnar silicon layer of the driver transistor is formed larger than the peripheral length of the columnar silicon layer forming the access transistor, and the current of the driver transistor is increased to increase the read margin.
  • the pillar layout similar to that of the first embodiment is used as an example.
  • the layout of the first embodiment is not limited to the layout of the first embodiment. An example can be applied. Since the other points are the same as the configuration shown in the first embodiment, description thereof is omitted.
  • FIG. 17 shows the SRAM cell layout of this embodiment.
  • the present embodiment is different from the first embodiment in the following points.
  • the storage node Qa3 formed by the first diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn23 are connected to each other by a common contact 310a formed over both of them.
  • Qb3, which is a storage node formed by the second diffusion layer, and a gate wiring extending from the gate electrode of driver transistor Qn13 are connected by a common contact 310b formed across both.
  • the number of contacts in the SRAM cell can be reduced by directly connecting the gate and the storage node with the contact instead of the wiring layer. Therefore, the cell area can be reduced by adjusting the arrangement of the columnar silicon layer and the contact. Can be reduced.
  • a configuration in which Vss3 is formed of a lower layer wiring and bit lines (BL3, BLB3) are formed of an upper layer wiring can be realized.
  • the node connection wiring Na1 and the node connection wiring Nb1 are formed by contacts.
  • the same pillar layout as in the first embodiment is used as an example.
  • the layout is not limited to this layout in practice, and the present embodiment can be similarly applied to other layouts. it can. Since the other points are the same as the configuration shown in the first embodiment, description thereof is omitted.
  • FIG. 18 shows the SRAM cell layout of this embodiment.
  • the present embodiment is different from the first embodiment in the following points.
  • the contact 110a is disposed only adjacent to the driver transistor Qn11 on the storage node Qa1, but the contact 110b is provided between the driver transistor Qn21 and the access transistor Qp21 on the storage node Qb1.
  • Such an asymmetry of the layout may cause an asymmetry in the characteristics of the SRAM cell, and the operation margin may be narrowed.
  • the access transistor Qp14, contacts (410a, 411a) and driver transistor Qn14 on the first storage node Qa4 and the access transistor Qp24, contacts (410b, 411b) and driver transistor on the second storage node Qb4 are used. Since the layout of Qn24 is symmetric, the operation margin is not deteriorated due to the asymmetry as described above, and an SRAM cell having a wide operation margin is possible.
  • the node connection wiring Na4, the node connection wiring Nb4, and the ground potential wiring Vss4 are formed by lower layer wirings, and the bit lines (BL1, BLB1) are formed by upper layer wirings. It is feasible.
  • FIG. 19 shows the SRAM cell layout of this embodiment. Since the layout of this embodiment is symmetrical as in the fourth embodiment, an SRAM cell having a wide operation margin is possible.
  • Qa5 which is a storage node formed by the first diffusion layer on the substrate, and a gate wiring extending from the gate electrode of the driver transistor Qn25 are formed over both.
  • the storage node Qb5 connected by the contact 510a and formed by the second diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn15 are connected by a common contact 510b formed over both. Connected.
  • bit line wiring and the ground potential wiring are preferably arranged in a layer higher than the node connection wiring which is a wiring in each memory cell, in order to share the wiring with other memory cells.
  • the node connection wiring is formed by contacts.
  • Vss3 is formed by a lower layer wiring
  • bit lines (BL5, BLB5) are formed by an upper layer wiring.
  • the node connection wiring Na5 and the node connection wiring Nb5 are formed by contacts.
  • FIG. 20A shows a plan view of a part of an SRAM memory cell array composed of a plurality of SRAM memory cells.
  • a plurality of memory cells are arranged in the horizontal direction, and the word lines 518a are shared by the plurality of memory cells arranged in the horizontal direction.
  • the word line is connected to the upper layer wiring by a contact 507 formed in the contact area, and backed by the wiring layer as necessary. Therefore, unlike the SRAM cell of Patent Document 2, it is not necessary to form a contact to the word line in each cell, so that the SRAM cell area can be reduced.
  • FIG. 20B shows a plan view of a part of an SRAM cell array composed of a plurality of SRAM cells in other cases. Similarly, in the cell array area in the figure, a plurality of memory cells are arranged in the horizontal direction, and the word line 518a is shared in the memory cells arranged in the horizontal direction. However, in FIG. 20B, pillars are arranged in the contact area as well as in the cell array area. As described above, by arranging the pillars in the contact area, it is possible to minimize the error in the characteristics of the SGT adjacent to the contact area and the SGT not adjacent to the contact area.
  • the MOS transistor is an SGT in which a drain, a gate, and a source are arranged in a vertical direction, and an access transistor CMOS having a very small memory cell area by sharing a plurality of cells adjacent to each other in a row (in the horizontal direction in the drawing) as a word line and forming one contact to the word line for each of the plurality of cells.
  • SGT in which a drain, a gate, and a source are arranged in a vertical direction
  • CMOS having a very small memory cell area by sharing a plurality of cells adjacent to each other in a row (in the horizontal direction in the drawing) as a word line and forming one contact to the word line for each of the plurality of cells.
  • a type Loadless 4T-SRAM can be realized.

Abstract

The present invention provides a loadless 4T-SRAM configured from a vertical transistor SGT, the loadless 4T-SRAM having a small SRAM cell area. A stick-type memory cell configured by using four MOS transistors, wherein: the MOS transistors are SGTs which are formed on an SOI substrate and of which the drain, gate, and source are arranged in a perpendicular direction; the gate of an access transistor functioning as a wide line is shared by multiple cells that are adjacent to one another in the horizontal direction; and one contact to the wide line is formed per multiple cells. As a consequence, it is possible to provide a CMOS-type loadless 4T-SRAM having an extremely small memory cell area.

Description

半導体記憶装置Semiconductor memory device
本発明は半導体記憶装置に関し、特にＳＲＡＭ（Ｓｔａｔｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）からなる半導体記憶装置に関する。 The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device made of SRAM (Static Random Access to Memory).
半導体装置の高集積化、高性能化を実現するため、半導体基板の表面に柱状半導体を形成し、その側壁に柱状半導体層を取り囲むように形成されたゲートを有する縦型ゲートトランジスタであるＳＧＴ（Ｓｕｒｒｏｕｎｄｉｎｇ Ｇａｔｅ Ｔｒａｎｓｉｓｔｏｒ）が提案された（例えば、特許文献１：特開平２－１８８９６６）。ＳＧＴではドレイン、ゲート、ソースが垂直方向に配置されるため、従来のプレーナー型トランジスタに比べて占有面積を大幅に縮小することができる。 In order to realize high integration and high performance of a semiconductor device, a columnar semiconductor is formed on the surface of a semiconductor substrate, and an SGT (vertical gate transistor having a gate formed so as to surround the columnar semiconductor layer on a sidewall thereof. (Surrounding Gate Transistor) has been proposed (for example, Patent Document 1: JP-A-2-188966). In the SGT, the drain, gate and source are arranged in the vertical direction, so that the occupied area can be greatly reduced as compared with the conventional planar type transistor.
ＳＧＴを用いてＬＳＩ（大規模集積回路）を構成する場合、それらのキャッシュ用メモリとしてＳＧＴの組み合わせで構成されるＳＲＡＭを用いることが必須である。近年、ＬＳＩに搭載されるＳＲＡＭに対する大容量化の要求は非常に強いため、ＳＧＴを用いた場合にも小さいセル面積を持つＳＲＡＭを実現することが必須である。 When an LSI (Large Scale Integrated Circuit) is configured using SGT, it is essential to use an SRAM configured by a combination of SGTs as the cache memory. In recent years, there is a strong demand for a large capacity for SRAM mounted on an LSI, and it is essential to realize an SRAM having a small cell area even when SGT is used.
特許文献２（国際公開番号Ｗ０２００９／０９６４６６）に４個のＳＧＴを用いてＳＯＩ基板上に形成されたＬｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭが示されている。Ｌｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭの等価回路図を図１に示す。また、特許文献２のＬｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭの平面図を図２１に、断面図を図２２に示す。 Patent Document 2 (International Publication No. W02009 / 096466) shows a Loadless 4T-SRAM formed on an SOI substrate using four SGTs. An equivalent circuit diagram of the Loadless 4T-SRAM is shown in FIG. FIG. 21 is a plan view of the Loadless 4T-SRAM disclosed in Patent Document 2, and FIG. 22 is a cross-sectional view thereof.
図１に示したＬｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭの等価回路を用いて、Ｌｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭの動作原理について以下に示す。Ｌｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭはＰＭＯＳであるメモリにアクセスするための２個のアクセストランジスタとＮＭＯＳであるメモリを駆動するための２個のドライバトランジスタの計４個のトランジスタにより構成されている。
以下に図１のメモリセルの動作の一例として、記憶ノードＱａ１に“Ｌ”のデータが、記憶ノードＱｂ１に“Ｈ”のデータが記憶されている場合のデータの保持動作について説明する。データ保持中はワード線ＷＬ１、ビット線ＢＬ１およびＢＬＢ１はすべて“Ｈ”電位に駆動されている。アクセストランジスタ（Ｑｐ１１、Ｑｐ２１）のオフリーク電流はドライバトランジスタのオフリーク電流より、例えば１０倍～１０００倍程度大きくなるように設定されている。このため、記憶ノードＱｂ１の“Ｈ”レベルはアクセストランジスタＱｐ２１を通してビット線ＢＬＢ１から記憶ノードＱｂ１にＯｆｆリーク電流が流れることにより保持される。一方、記憶ノードＱａ１の“Ｌ”レベルはドライバトランジスタＱｎ１１により安定して保持される。 The operation principle of the Loadless 4T-SRAM will be described below using the equivalent circuit of the Loadless 4T-SRAM shown in FIG. The Loadless 4T-SRAM is composed of a total of four transistors: two access transistors for accessing a memory which is a PMOS and two driver transistors for driving a memory which is an NMOS.
As an example of the operation of the memory cell in FIG. 1, a data holding operation in the case where “L” data is stored in the storage node Qa1 and “H” data is stored in the storage node Qb1 will be described below. During data retention, the word line WL1 and the bit lines BL1 and BLB1 are all driven to the “H” potential. The off-leakage current of the access transistors (Qp11, Qp21) is set to be, for example, about 10 to 1000 times larger than the off-leakage current of the driver transistor. Therefore, the “H” level of the storage node Qb1 is held by the off leak current flowing from the bit line BLB1 to the storage node Qb1 through the access transistor Qp21. On the other hand, the “L” level of storage node Qa1 is stably held by driver transistor Qn11.
図２１に従来のＳＲＡＭメモリセルのレイアウト図を示す。ＳＲＡＭセルアレイ内においては図２１に示したユニットセルＵＣが繰り返し配置されている。図２２（ａ）～（ｄ）に図２１のレイアウト図のカットラインＡ－Ａ’、Ｂ－Ｂ’、Ｃ－Ｃ’及びＤ－Ｄ’における断面構造をそれぞれ示す。 FIG. 21 shows a layout diagram of a conventional SRAM memory cell. The unit cells UC shown in FIG. 21 are repeatedly arranged in the SRAM cell array. 22A to 22D show cross-sectional structures taken along cut lines A-A ′, B-B ′, C-C ′, and D-D ′ in the layout diagram of FIG.
まず、図２１及び図２２を用いて特許文献２の実施例１のＳＲＡＭセルのレイアウトについて説明する。
記憶ノード（６０２ａ、６０２ｂ）は埋め込み酸化膜層６０１上に形成されたシリコン層により形成されており、上記シリコン層は不純物注入等を行うことにより、Ｎ＋拡散層領域（６０４ａ、６０４ｂ）およびＰ＋拡散層領域（６０３ａ、６０３ｂ）から構成されている。Ｑｐ１６およびＱｐ２６はアクセストランジスタ、Ｑｎ１６およびＱｎ２６はドライバトランジスタを示している。記憶ノード６０２ａ上に形成されるコンタクト６１０ａはノード接続配線Ｎａ６によりドライバトランジスタＱｎ２６のゲート電極より延在するゲート配線上に形成されるコンタクト６１１ｂと接続され、記憶ノード６０２ｂ上に形成されるコンタクト６１０ｂはノード接続配線Ｎｂ６によりドライバトランジスタＱｎ１６のゲート電極より延在するゲート配線上に形成されるコンタクト６１１ａと接続される。アクセストランジスタＱｐ１６上部に形成されるコンタクト６０６ａはビット線ＢＬ６に接続され、アクセストランジスタＱｐ２６上部に形成されるコンタクト６０６ｂはビット線ＢＬＢ６に接続される。アクセストランジスタＱｐ１６およびＱｐ２６のゲート電極から延在するゲート配線上に形成されるコンタクト６０７はワード線ＷＬ６に接続される。また、ドライバトランジスタ（Ｑｎ１６、Ｑｎ２６）上部に形成されるコンタクト（６０８ａ、６０８ｂ）はともに接地電位である配線層Ｖｓｓ６に接続される。 First, the layout of the SRAM cell of Example 1 of Patent Document 2 will be described with reference to FIGS. 21 and 22.
The storage nodes (602a, 602b) are formed by a silicon layer formed on the buried oxide film layer 601, and the silicon layer is subjected to impurity implantation or the like, thereby performing N + diffusion layer regions (604a, 604b) and P + diffusion. It consists of layer regions (603a, 603b). Qp16 and Qp26 indicate access transistors, and Qn16 and Qn26 indicate driver transistors. Contact 610a formed on storage node 602a is connected to contact 611b formed on the gate wiring extending from the gate electrode of driver transistor Qn26 by node connection wiring Na6, and contact 610b formed on storage node 602b is Node connection wiring Nb6 connects to contact 611a formed on the gate wiring extending from the gate electrode of driver transistor Qn16. Contact 606a formed on access transistor Qp16 is connected to bit line BL6, and contact 606b formed on access transistor Qp26 is connected to bit line BLB6. Contact 607 formed on the gate wiring extending from the gate electrodes of access transistors Qp16 and Qp26 is connected to word line WL6. The contacts (608a, 608b) formed on the driver transistors (Qn16, Qn26) are both connected to the wiring layer Vss6, which is the ground potential.
続いて、図２２の断面図を用いて特許文献２の実施例１のＳＲＡＭセルの構造について説明する。
図２２（ａ）より、埋め込み酸化膜層６０１上に記憶ノード（６０２ａ、６０２ｂ）であるシリコン層よりなるＰ＋ソース拡散層（６０３ａ、６０３ｂ）がそれぞれ形成されている。ソース拡散層上にはシリサイド層（６１３ａ、６１３ｂ）が形成されている。Ｐ＋ソース拡散層領域６０３ａ上にアクセストランジスタＱｐ１６を形成する柱状シリコン層６２１ａが形成され、Ｐ＋ソース拡散層領域６０３ｂ上にアクセストランジスタＱｐ２６を形成する柱状シリコン層６２１ｂが形成される。それぞれの柱状シリコン層の周囲にはゲート絶縁膜６１７およびゲート電極６１８が形成されている。柱状シリコン層上部にはＰ＋ドレイン拡散層領域６１６が不純物注入などにより形成され、ドレイン拡散層領域表面にはシリサイド層６１５が形成されている。アクセストランジスタＱｐ１６上に形成されるコンタクト６０６ａはビット線ＢＬ６に接続され、アクセストランジスタＱｐ２６上に形成されるコンタクト６０６ｂはビット線ＢＬＢ６に接続され、アクセストランジスタＱｐ１６およびＱｐ２６のゲートより延在するゲート配線６１８ａ上に形成されるコンタクト６０７はワード線ＷＬ６に接続される。 Next, the structure of the SRAM cell of Example 1 of Patent Document 2 will be described using the cross-sectional view of FIG.
As shown in FIG. 22A, P + source diffusion layers (603a, 603b) made of silicon layers as storage nodes (602a, 602b) are formed on the buried oxide film layer 601, respectively. Silicide layers (613a and 613b) are formed on the source diffusion layer. A columnar silicon layer 621a for forming the access transistor Qp16 is formed on the P + source diffusion layer region 603a, and a columnar silicon layer 621b for forming the access transistor Qp26 is formed on the P + source diffusion layer region 603b. A gate insulating film 617 and a gate electrode 618 are formed around each columnar silicon layer. A P + drain diffusion layer region 616 is formed on the columnar silicon layer by impurity implantation, and a silicide layer 615 is formed on the surface of the drain diffusion layer region. Contact 606a formed on access transistor Qp16 is connected to bit line BL6, contact 606b formed on access transistor Qp26 is connected to bit line BLB6, and gate line 618a extends from the gates of access transistors Qp16 and Qp26. A contact 607 formed above is connected to the word line WL6.
図２２（ｂ）より、埋め込み酸化膜層６０１上に記憶ノード（６０２ａ、６０２ｂ）であるシリコン層よりなるＮ＋ソース拡散層（６０４ａ、６０４ｂ）がそれぞれ形成されている。ソース拡散層上にはシリサイド層（６１３ａ、６１３ｂ）が形成されている。ドライバトランジスタＱｎ１６のゲート電極から延在するゲート配線６１８ｂ上に形成されるコンタクト６１１ａは記憶ノード接続配線Ｎａ６を通じてＮ＋ソース拡散層６０４ｂ上に形成されるコンタクト６１０ｂに接続される。 As shown in FIG. 22B, N + source diffusion layers (604a, 604b) made of silicon layers as storage nodes (602a, 602b) are formed on the buried oxide film layer 601, respectively. Silicide layers (613a and 613b) are formed on the source diffusion layer. Contact 611a formed on gate line 618b extending from the gate electrode of driver transistor Qn16 is connected to contact 610b formed on N + source diffusion layer 604b through storage node connection line Na6.
図２２（ｃ）より、埋め込み酸化膜層６０１上に記憶ノードであるシリコン層よりなるＮ＋ソース拡散層（６０４ａ、６０４ｂ）が形成されている。Ｎ＋ソース拡散層上にはシリサイド層（６１３ａ、６１３ｂ）が形成されている。Ｎ＋ソース拡散層領域６０４ａにドライバトランジスタＱｎ１６を形成する柱状シリコン層６２２ａが形成され、Ｎ＋ソース拡散層領域６０４ｂにドライバトランジスタＱｎ２６を形成する柱状シリコン層６２２ｂが形成される。それぞれの柱状シリコン層の周囲にゲート絶縁膜６１７およびゲート電極６１８が形成されている。柱状シリコン層上部にはＮ＋ドレイン拡散層領域６１４が不純物注入などにより形成され、ドレイン拡散層領域表面にはシリサイド層６１５が形成されている。ドライバトランジスタ（Ｑｎ１６、Ｑｎ２６）上に形成されるコンタクト（６０８ａ、６０８ｂ）はともに配線層を通して接地電位Ｖｓｓ６に接続される。 As shown in FIG. 22C, N + source diffusion layers (604a, 604b) made of a silicon layer as a storage node are formed on the buried oxide film layer 601. Silicide layers (613a and 613b) are formed on the N + source diffusion layer. A columnar silicon layer 622a for forming the driver transistor Qn16 is formed in the N + source diffusion layer region 604a, and a columnar silicon layer 622b for forming the driver transistor Qn26 is formed in the N + source diffusion layer region 604b. A gate insulating film 617 and a gate electrode 618 are formed around each columnar silicon layer. An N + drain diffusion layer region 614 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 615 is formed on the surface of the drain diffusion layer region. The contacts (608a, 608b) formed on the driver transistors (Qn16, Qn26) are both connected to the ground potential Vss6 through the wiring layer.
図２２（ｄ）より、埋め込み酸化膜層６０１上に記憶ノードであるシリコン層よりなるＰ＋ソース拡散層６０３ａおよびＮ＋ソース拡散層６０４ａが形成される。ソース拡散層上にはシリサイド層６１３ａが形成され、シリサイド層６１３ａによってＰ＋ソース拡散層６０３ａとＮ＋ソース拡散層６０４ａは接続されている。 22D, a P + source diffusion layer 603a and an N + source diffusion layer 604a made of a silicon layer as a storage node are formed on the buried oxide film layer 601. A silicide layer 613a is formed on the source diffusion layer, and the P + source diffusion layer 603a and the N + source diffusion layer 604a are connected by the silicide layer 613a.
図２１及び図２２の４Ｔ－ＳＲＡＭセルにおいては、アクセストランジスタ間のゲート上に形成されるワード線コンタクトにより、上下方向にデッドスペースが発生し、効率的に小さいＳＲＡＭセルを形成することができない。 In the 4T-SRAM cell of FIGS. 21 and 22, a dead space is generated in the vertical direction due to the word line contact formed on the gate between the access transistors, and an efficient small SRAM cell cannot be formed.
本発明は上記の事情を鑑みてなされたもので、従来提案されていたＳＧＴを用いたＬｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭより、さらにセル面積の小さいＳＧＴを用いたＬｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭセルを実現することを目的とする。 The present invention has been made in view of the above circumstances, and an object of the present invention is to realize a Loadless 4T-SRAM cell using an SGT having a smaller cell area than the conventionally proposed Loadless 4T-SRAM using an SGT.
　上記課題を解決するために、本発明は、４個のＭＯＳトランジスタが基板上に形成された絶縁膜上に配列された複数のスタティック型メモリセルを備えた半導体記憶装置であって、
　前記４個のＭＯＳトランジスタの各々は、
　メモリセルデータを保持するために電荷を供給すると共にメモリにアクセスするための第１及び第２のＰＭＯＳのアクセストランジスタと、メモリセルのデータを書き込み及び読み出しするために記憶ノードを駆動する第１及び第２のＮＭＯＳのドライバトランジスタとして機能し、
　前記第１及び第２のＰＭＯＳのアクセストランジスタにおいて、
　Ｐ型の導電型を持つ第１の拡散層、第１の柱状半導体層及びＰ型の導電型を持つ第２の拡散層が、基板上に形成された絶縁膜上に垂直方向に階層的に配置され、前記第１の柱状半導体層は前記第１の柱状半導体層の底部に形成される前記第１の拡散層と前記第１の柱状半導体層の上部に形成される前記第２の拡散層の間に配置され、前記第１の柱状半導体層の側壁にゲート絶縁膜及びゲートが形成されており、
　前記第１及び第２のＮＭＯＳのドライバトランジスタにおいて、
　Ｎ型の導電型を持つ第３の拡散層、第２の柱状半導体層及びＮ型の導電型を持つ第４の拡散層が、基板上に形成された絶縁膜上に垂直方向に階層的に配置され、前記第２の柱状半導体層は前記第２の柱状半導体層の底部に形成される前記第３の拡散層と前記第１の柱状半導体層の上部に形成される前記第４の拡散層の間に配置され、前記第２の柱状半導体層の側壁にゲート絶縁膜及びゲートが形成されており、
　前記第１のＰＭＯＳのアクセストランジスタ及び前記第１のＮＭＯＳのドライバトランジスタは、互いに隣接して配列され、
　前記第２のＰＭＯＳのアクセストランジスタ及び前記第２のＮＭＯＳのドライバトランジスタは、互いに隣接して配列され、
　データを保持する第１の記憶ノードとして機能する、前記第１のＰＭＯＳのアクセストランジスタの底部に形成されるＰ型の導電型を持つ前記第１の拡散層及び前記第１のＮＭＯＳのドライバトランジスタの底部に形成されるＮ型の導電型を持つ前記第３の拡散層を前記絶縁膜上に配置し、
　前記第１の記憶ノードとして機能する、前記第１の拡散層、前記第３の拡散層は相互に接続され、
　データを保持する第２の記憶ノードとして機能する、前記第２のＰＭＯＳのアクセストランジスタの底部に形成されるＰ型の導電型を持つ前記第１の拡散層及び前記第２のＮＭＯＳのドライバトランジスタの底部に形成されるＮ型の導電型を持つ前記第３の拡散層を前記絶縁膜上に配置し、
　前記第２の記憶ノードとして機能する、前記第１の拡散層、前記第３の拡散層は相互に接続され、
　前記第１及び前記第２のＰＭＯＳのドライバトランジスタのそれぞれのゲートは第１のゲート配線により互いに接続され、前記第１のゲート配線は隣接する複数のメモリセルにおける前記第１及び前記第２のＰＭＯＳのアクセストランジスタのそれぞれのゲートと互いに接続されることによりワード線を形成しており、
　隣接する複数のメモリセルごとに、ワード線である前記第１のゲート配線上に第１のコンタクトが形成されることを特徴とする半導体記憶装置を提供する。
　本発明の好ましい態様では、前記ワード線である前記第１のゲート配線上に前記第１のコンタクトが形成される領域において、メモリセルと同様にピラーが配置されていることを特徴とする半導体記憶装置が提供される。
　別の好ましい態様では、前記第１のＮＭＯＳのドライバトランジスタのゲートより延在する第２のゲート配線が、前記第２の記憶ノードとして機能する拡散層と共通の第２のコンタクトにより接続され、前記第２のＮＭＯＳのドライバトランジスタのゲートより延在する第３のゲート配線が、前記第１の記憶ノードとして機能する拡散層と共通の第３のコンタクトにより接続されることを特徴とする半導体記憶装置が提供される。
　更に別の好ましい態様では、前記第１及び第２のＮＭＯＳのドライバトランジスタを形成する柱状半導体層の側壁の周囲長は、前記第１及び第２のＰＭＯＳのアクセストランジスタを形成する柱状半導体層の側壁の周囲長以上の値を持つこと、又は前記第１及び第２のＮＭＯＳのドライバトランジスタを形成する柱状半導体層の側壁の周囲長は、前記第１及び第２のＰＭＯＳのアクセストランジスタを形成する柱状半導体層の側壁の周囲長以下の値を持つことを特徴とする半導体記憶装置が提供される。
　更に別の好ましい態様では、前記４個のＭＯＳトランジスタは、前記絶縁膜上に２行２列に配列され、前記第１のＰＭＯＳのアクセストランジスタは１行１列目に配列され、前記第１のＮＭＯＳのドライバトランジスタは２行１列目に配列され、前記第２のＰＭＯＳのアクセストランジスタは１行２列目に配列され、前記第２のＮＭＯＳのドライバトランジスタは２行２列目に配列されていることを特徴とする半導体記憶装置が提供される。
　更に別の好ましい態様では、前記４個のＭＯＳトランジスタは前記絶縁膜上に配列され、前記第１のＰＭＯＳのアクセストランジスタと前記第２のＰＭＯＳのアクセストランジスタは隣接して配列され、前記第１のＰＭＯＳのアクセストランジスタと前記第２のＰＭＯＳのアクセストランジスタの隣接方向に直交する一方の方向において前記第１のＮＭＯＳのドライバトランジスタは前記第１のＰＭＯＳのアクセストランジスタと隣接して配列され、前記第１のＰＭＯＳのアクセストランジスタと前記第２のＰＭＯＳのアクセストランジスタの隣接方向に直交する他方の方向において前記第２のＮＭＯＳのドライバトランジスタは前記第２のＰＭＯＳのアクセストランジスタと隣接して配列されていることを特徴とする半導体記憶装置が提供される。 In order to solve the above problems, the present invention provides a semiconductor memory device including a plurality of static memory cells in which four MOS transistors are arranged on an insulating film formed on a substrate,
Each of the four MOS transistors is
First and second PMOS access transistors for supplying charge to hold memory cell data and accessing the memory, and for driving the storage node to write and read data in the memory cell Functions as a second NMOS driver transistor,
In the first and second PMOS access transistors,
A first diffusion layer having a P-type conductivity, a first columnar semiconductor layer, and a second diffusion layer having a P-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on a substrate. The first columnar semiconductor layer is disposed, and the first diffusion layer formed on the bottom of the first columnar semiconductor layer and the second diffusion layer formed on the top of the first columnar semiconductor layer A gate insulating film and a gate are formed on sidewalls of the first columnar semiconductor layer,
In the first and second NMOS driver transistors,
A third diffusion layer having an N-type conductivity, a second columnar semiconductor layer, and a fourth diffusion layer having an N-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on the substrate. The second columnar semiconductor layer is disposed, and the third diffusion layer formed on the bottom of the second columnar semiconductor layer and the fourth diffusion layer formed on the top of the first columnar semiconductor layer. A gate insulating film and a gate are formed on sidewalls of the second columnar semiconductor layer,
The first PMOS access transistor and the first NMOS driver transistor are arranged adjacent to each other,
The second PMOS access transistor and the second NMOS driver transistor are arranged adjacent to each other,
The first diffusion layer having the P-type conductivity formed at the bottom of the first PMOS access transistor and the first NMOS driver transistor functioning as a first storage node for holding data Disposing the third diffusion layer having the N-type conductivity type formed on the bottom on the insulating film;
The first diffusion layer and the third diffusion layer functioning as the first storage node are connected to each other,
The first diffusion layer having the P-type conductivity formed at the bottom of the second PMOS access transistor and the second NMOS driver transistor functioning as a second storage node for holding data Disposing the third diffusion layer having the N-type conductivity type formed on the bottom on the insulating film;
The first diffusion layer and the third diffusion layer functioning as the second storage node are connected to each other,
The gates of the first and second PMOS driver transistors are connected to each other by a first gate line, and the first gate line is connected to the first and second PMOSs in a plurality of adjacent memory cells. A word line is formed by being connected to each gate of the access transistors of
Provided is a semiconductor memory device, wherein a first contact is formed on the first gate wiring which is a word line for each of a plurality of adjacent memory cells.
In a preferred aspect of the present invention, a pillar is disposed in the region where the first contact is formed on the first gate wiring which is the word line, similarly to the memory cell. An apparatus is provided.
In another preferred embodiment, a second gate wiring extending from a gate of the first NMOS driver transistor is connected to a diffusion layer functioning as the second storage node by a second contact in common, and 3. A semiconductor memory device, characterized in that a third gate wiring extending from the gate of the second NMOS driver transistor is connected to the diffusion layer functioning as the first storage node by a common third contact. Is provided.
In a further preferred aspect, the peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS driver transistors is the side wall of the columnar semiconductor layer forming the first and second PMOS access transistors. Of the columnar semiconductor layer forming the first and second NMOS driver transistors has a columnar shape forming the first and second PMOS access transistors. There is provided a semiconductor memory device having a value equal to or less than the peripheral length of the side wall of the semiconductor layer.
In still another preferred embodiment, the four MOS transistors are arranged in two rows and two columns on the insulating film, the first PMOS access transistors are arranged in the first row and first column, and the first transistors The NMOS driver transistor is arranged in the second row and the first column, the second PMOS access transistor is arranged in the first row and the second column, and the second NMOS driver transistor is arranged in the second row and the second column. A semiconductor memory device is provided.
In another preferred aspect, the four MOS transistors are arranged on the insulating film, the first PMOS access transistor and the second PMOS access transistor are arranged adjacent to each other, and the first PMOS access transistor is arranged adjacent to the first PMOS access transistor. The first NMOS driver transistor is arranged adjacent to the first PMOS access transistor in one direction orthogonal to the adjacent direction of the PMOS access transistor and the second PMOS access transistor, and The second NMOS driver transistor is arranged adjacent to the second PMOS access transistor in the other direction orthogonal to the adjacent direction of the second PMOS access transistor and the second PMOS access transistor. Provided by semiconductor memory device characterized by It is.
本発明のＳＲＡＭを示す等価回路である。3 is an equivalent circuit showing the SRAM of the present invention. 本発明の第１の実施例を示すＳＲＡＭの平面図である。1 is a plan view of an SRAM showing a first embodiment of the present invention. 本発明の第１の実施例を示すＳＲＡＭの平面図である。1 is a plan view of an SRAM showing a first embodiment of the present invention. 本発明の第１の実施例を示すＳＲＡＭの断面図である。1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention. 本発明の第１の実施例を示すＳＲＡＭの断面図である。1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention. 本発明の第１の実施例を示すＳＲＡＭの断面図である。1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention. 本発明の第１の実施例を示すＳＲＡＭの断面図である。1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention. 本発明の第１の実施例を示すＳＲＡＭの断面図である。1 is a cross-sectional view of an SRAM showing a first embodiment of the present invention. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of this invention in process order. 本発明の第２の実施例を示すＳＲＡＭの平面図である。It is a top view of SRAM which shows the 2nd Example of this invention. 本発明の第３の実施例を示すＳＲＡＭの平面図である。It is a top view of SRAM which shows the 3rd Example of this invention. 本発明の第４の実施例を示すＳＲＡＭの平面図である。It is a top view of SRAM which shows the 4th Example of this invention. 本発明の第５の実施例を示すＳＲＡＭの平面図である。It is a top view of SRAM which shows the 5th Example of this invention. 本発明の第５の実施例を示すＳＲＡＭの平面図である。It is a top view of SRAM which shows the 5th Example of this invention. 従来のＳＧＴを用いたＳＲＡＭを示す平面図である。It is a top view which shows SRAM using the conventional SGT. 従来のＳＧＴを用いたＳＲＡＭを示す断面図である。It is sectional drawing which shows SRAM using the conventional SGT. 従来のＳＧＴを用いたＳＲＡＭを示す断面図である。It is sectional drawing which shows SRAM using the conventional SGT. 従来のＳＧＴを用いたＳＲＡＭを示す断面図である。It is sectional drawing which shows SRAM using the conventional SGT. 従来のＳＧＴを用いたＳＲＡＭを示す断面図である。It is sectional drawing which shows SRAM using the conventional SGT.
図２に本発明の第１の実施例におけるＳＲＡＭメモリセルのレイアウト図を示す。ＳＲＡＭメモリセルアレイ内においては図２に示したユニットセルＵＣが繰り返し配置されている。図３（ａ）～（ｄ）に図２のレイアウト図のカットラインＡ－Ａ’、Ｂ－Ｂ’、Ｃ－Ｃ’及びＤ－Ｄ’における断面構造をそれぞれ示す。 FIG. 2 shows a layout diagram of the SRAM memory cell in the first embodiment of the present invention. The unit cells UC shown in FIG. 2 are repeatedly arranged in the SRAM memory cell array. FIGS. 3A to 3D show cross-sectional structures along cut lines A-A ′, B-B ′, C-C ′, and D-D ′ in the layout diagram of FIG.
まず図２のレイアウト図を参考にして本実施例について説明する。
Ｑｐ１１およびＱｐ２１はＰＭＯＳであるメモリセルにアクセスするためのアクセストランジスタであり、Ｑｎ１１およびＱｎ２１はＮＭＯＳであるメモリセルを駆動するドライバトランジスタである。
本実施例では、１つのユニットセルＵＣは、基板上に２行２列に配列されたトランジスタを備えている。１列目には、第１の記憶ノードＱａ１上に、図の上側からアクセストランジスタＱｐ１１及びドライバトランジスタＱｎ１１がそれぞれ配列されている。また、２列目には、第２の記憶ノードＱｂ１上に、図の上側からアクセストランジスタＱｐ２１及びドライバトランジスタＱｎ２１がそれぞれ配列されている。また、アクセストランジスタのゲートから延在するゲート配線１３４は横方向に隣接する複数のメモリセルと共通化され、ワード線を形成している。本実施例のＳＲＡＭセルアレイは、このような４個のトランジスタを備えたユニットセルＵＣを図の上下方向に連続的に配列することにより構成される。 First, the present embodiment will be described with reference to the layout diagram of FIG.
Qp11 and Qp21 are access transistors for accessing a memory cell that is a PMOS, and Qn11 and Qn21 are driver transistors that drive the memory cell that is an NMOS.
In this embodiment, one unit cell UC includes transistors arranged in 2 rows and 2 columns on a substrate. In the first column, an access transistor Qp11 and a driver transistor Qn11 are arranged on the first storage node Qa1 from the upper side of the drawing, respectively. In the second column, an access transistor Qp21 and a driver transistor Qn21 are arranged on the second storage node Qb1 from the upper side in the drawing. A gate wiring 134 extending from the gate of the access transistor is shared with a plurality of memory cells adjacent in the horizontal direction to form a word line. The SRAM cell array of this embodiment is configured by continuously arranging unit cells UC having such four transistors in the vertical direction of the figure.
記憶ノード（１０２ａ、１０２ｂ）は埋め込み酸化膜層１０１上に形成されたシリコン層により形成されており、上記シリコン層は不純物注入等を行うことにより、Ｎ＋拡散層領域（１０４ａ、１０４ｂ）およびＰ＋拡散層領域（１０３ａ、１０３ｂ）から構成されている。Ｑｐ１１およびＱｐ２１はアクセストランジスタ、Ｑｎ１１およびＱｎ２１はドライバトランジスタを示している。記憶ノード１０２ａ上に形成されるコンタクト１１０ａはノード接続配線Ｎａ１によりドライバトランジスタＱｎ２１のゲート電極より延在するゲート配線上に形成されるコンタクト１１１ｂと接続され、記憶ノード１０２ｂ上に形成されるコンタクト１１０ｂはノード接続配線Ｎｂ１によりドライバトランジスタＱｎ１１のゲート電極より延在するゲート配線上に形成されるコンタクト１１１ａと接続される。ドライバトランジスタ（Ｑｎ１１、Ｑｎ２１）上部に形成されるコンタクト（１０８ａ、１０８ｂ）はともに接地電位である配線層Ｖｓｓ１に接続される。アクセストランジスタＱｐ１１上部に形成されるコンタクト１０６ａはビット線ＢＬ１に接続され、アクセストランジスタＱｐ２１上部に形成されるコンタクト１０６ｂはビット線ＢＬＢ１に接続される。アクセストランジスタＱｐ１１およびＱｐ２１のゲート電極から延在するゲート配線（１１８ａ）はワード線として横方向に隣接する複数のメモリセルに接続されている。
階層的な配線の構成の一例として、ノード接続配線Ｎａ１、ノード接続配線Ｎｂ１、及び接地電位の配線Ｖｓｓ１を下層の配線で形成し、ビット線（ＢＬ１、ＢＬＢ１）を上層の配線で形成する構成が実現可能である。 The storage nodes (102a, 102b) are formed of a silicon layer formed on the buried oxide film layer 101, and the silicon layer is subjected to impurity implantation or the like, so that N + diffusion layer regions (104a, 104b) and P + diffusion are formed. It consists of layer regions (103a, 103b). Qp11 and Qp21 indicate access transistors, and Qn11 and Qn21 indicate driver transistors. Contact 110a formed on storage node 102a is connected to contact 111b formed on the gate wiring extending from the gate electrode of driver transistor Qn21 by node connection wiring Na1, and contact 110b formed on storage node 102b is Node connection wiring Nb1 connects to contact 111a formed on the gate wiring extending from the gate electrode of driver transistor Qn11. The contacts (108a, 108b) formed on the driver transistors (Qn11, Qn21) are both connected to the wiring layer Vss1 which is the ground potential. Contact 106a formed on access transistor Qp11 is connected to bit line BL1, and contact 106b formed on access transistor Qp21 is connected to bit line BLB1. Gate wiring (118a) extending from the gate electrodes of access transistors Qp11 and Qp21 is connected as a word line to a plurality of memory cells adjacent in the horizontal direction.
As an example of the hierarchical wiring configuration, the node connection wiring Na1, the node connection wiring Nb1, and the ground potential wiring Vss1 are formed by lower layer wirings, and the bit lines (BL1, BLB1) are formed by upper layer wirings. It is feasible.
図３（ａ）に複数のＳＲＡＭメモリセルからなるＳＲＡＭメモリセルアレイの一部の平面図を示す。
図におけるＣｅｌｌ　ａｒｒａｙ　Ａｒｅａにおいては複数のメモリセルが横方向に配置されており、横方向に配置された複数のメモリセルにおいて、ワード線１１８ａが共通化されている。ワード線はＣｏｎｔａｃｔ　Ａｒｅａに形成されたコンタクト１０７により上層の配線に接続され、必要に応じて配線層で裏打ちされる。このため、特許文献２のＳＲＡＭセルとは異なり、各々のセルにワード線へのコンタクトを形成する必要がないので、ＳＲＡＭセル面積を縮小することができる。
ワード線１１８ａに複数のセルを接続することにより、ワード線コンタクト１０７から遠い側のセルにおいてはワード線の信号の遅延による読み出しや書き込みの遅延が問題になる可能性がある。このため、ワード線に接続するセルの数は、各デバイスの設計仕様等に基づいて読み出しや書き込みの遅延が問題ない範囲で決めることができる。
図３（ｂ）に他の場合における複数のＳＲＡＭセルからなるＳＲＡＭセルアレイの一部の平面図を示す。図におけるＣｅｌｌ　ａｒｒａｙ　Ａｒｅａにおいても同様に、複数のメモリセルが横方向に配置されており、横方向に配置されたメモリセルにおいて、ワード線１１８ａが共通化されている。しかし、図３（ｂ）においてはＣｏｎｔａｃｔ　Ａｒｅａにおいても、Ｃｅｌｌ　ａｒｒａｙ　Ａｒｅａと同様にピラーが配置されている。このようにＣｏｎｔａｃｔ 　Ａｒｅａにおいてもピラーをメモリセル領域と同じパターンで配置することにより、Ｃｏｎｔａｃｔ　ＡｒｅａにおいてもＣｅｌｌ　ａｒｒａｙ内と同じピラー配置の規則性を保つことができるため、Ｃｏｎｔａｃｔ　Ａｒｅａに隣接するピラーとＣｏｎｔａｃｔ　Ａｒｅａに隣接していないピラー間の寸法の差を小さくすることができ、Ｃｏｎｔａｃｔ　Ａｒｅａに隣接するＳＧＴの特性とＣｏｎｔａｃｔ　Ａｒｅａに隣接していないＳＧＴ特性の誤差を最小限に抑えることができる。
図３においては、一例として実施例１のレイアウトを用いてワード線及びワード線コンタクトの構成について述べたが、実際には実施例１のレイアウトに限定されるものではなく、他の実施例のレイアウトにおいても同様なワード線及びワード線コンタクトの構成を適用することができる。 FIG. 3A shows a plan view of a part of an SRAM memory cell array composed of a plurality of SRAM memory cells.
In the cell array area in the figure, a plurality of memory cells are arranged in the horizontal direction, and the word line 118a is shared by the plurality of memory cells arranged in the horizontal direction. The word line is connected to the upper layer wiring by the contact 107 formed in the contact area, and is backed by the wiring layer as necessary. Therefore, unlike the SRAM cell of Patent Document 2, it is not necessary to form a contact to the word line in each cell, so that the SRAM cell area can be reduced.
By connecting a plurality of cells to the word line 118a, a delay in reading or writing due to a delay in the signal of the word line may be a problem in a cell far from the word line contact 107. For this reason, the number of cells connected to the word line can be determined based on the design specifications of each device and the like in a range where there is no problem in reading and writing.
FIG. 3B shows a plan view of a part of an SRAM cell array composed of a plurality of SRAM cells in another case. Similarly, in the cell array area in the figure, a plurality of memory cells are arranged in the horizontal direction, and the word lines 118a are shared in the memory cells arranged in the horizontal direction. However, in FIG. 3B, pillars are arranged in the contact area as well as in the cell array area. In this way, by arranging the pillars in the contact area in the same pattern as the memory cell region, the same pillar arrangement regularity as in the cell array can be maintained also in the contact area. A difference in dimension between pillars not adjacent to the area can be reduced, and an error between the characteristics of the SGT adjacent to the contact area and the SGT characteristics not adjacent to the contact area can be minimized.
In FIG. 3, the configuration of the word lines and the word line contacts is described using the layout of the first embodiment as an example. The same configuration of word lines and word line contacts can be applied in FIG.
本発明において、ＳＲＡＭを構成する各トランジスタのソースおよびドレインを以下のように定義する。ドライバトランジスタ（Ｑｎ１１、Ｑｎ２１）については、接地電圧に接続される柱状半導体層の上部に形成される拡散層をソース拡散層、柱状半導体層の下部に形成される拡散層をドレイン拡散層と定義する。アクセストランジスタ（Ｑｐ１１、Ｑｐ２１）については、動作状態によっては柱状半導体層の上部に形成される拡散層および下部に形成される拡散層がともにソースまたはドレインになるが、便宜的に柱状半導体層の上部に形成される拡散層をソース拡散層、柱状半導体層の下部に形成される拡散層をドレイン拡散層と定義する。 In the present invention, the source and drain of each transistor constituting the SRAM are defined as follows. For the driver transistors (Qn11, Qn21), a diffusion layer formed above the columnar semiconductor layer connected to the ground voltage is defined as a source diffusion layer, and a diffusion layer formed below the columnar semiconductor layer is defined as a drain diffusion layer. . As for the access transistors (Qp11, Qp21), depending on the operating state, both the diffusion layer formed above the columnar semiconductor layer and the diffusion layer formed below are the source or drain. The diffusion layer formed in (1) is defined as the source diffusion layer, and the diffusion layer formed under the columnar semiconductor layer is defined as the drain diffusion layer.
続いて、図４の断面構造を参照して本発明について説明する。
図４（ａ）より、埋め込み酸化膜層１０１上に記憶ノード（１０２ａ、１０２ｂ）であるシリコン層よりなるＰ＋ソース拡散層（１０３ａ、１０３ｂ）がそれぞれ形成されている。ソース拡散層上にはシリサイド層（１１３ａ、１１３ｂ）が形成されている。Ｐ＋ソース拡散層領域１０３ａ上にアクセストランジスタＱｐ１１を形成する柱状シリコン層１２１ａが形成され、Ｐ＋ソース拡散層領域１０３ｂ上にアクセストランジスタＱｐ２１を形成する柱状シリコン層１２１ｂが形成される。それぞれの柱状シリコン層の周囲にはゲート絶縁膜１１７およびゲート電極１１８が形成されている。柱状シリコン層上部にはＰ＋ドレイン拡散層領域１１６が不純物注入などにより形成され、ドレイン拡散層領域表面にはシリサイド層１１５が形成されている。アクセストランジスタＱｐ１１上に形成されるコンタクト１０６ａはビット線ＢＬ１に接続され、アクセストランジスタＱｐ２１上に形成されるコンタクト１０６ｂはビット線ＢＬＢ１に接続される。 Next, the present invention will be described with reference to the cross-sectional structure of FIG.
As shown in FIG. 4A, P + source diffusion layers (103a, 103b) made of silicon layers as storage nodes (102a, 102b) are formed on the buried oxide film layer 101, respectively. Silicide layers (113a and 113b) are formed on the source diffusion layer. A columnar silicon layer 121a for forming the access transistor Qp11 is formed on the P + source diffusion layer region 103a, and a columnar silicon layer 121b for forming the access transistor Qp21 is formed on the P + source diffusion layer region 103b. A gate insulating film 117 and a gate electrode 118 are formed around each columnar silicon layer. A P + drain diffusion layer region 116 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 115 is formed on the surface of the drain diffusion layer region. Contact 106a formed on access transistor Qp11 is connected to bit line BL1, and contact 106b formed on access transistor Qp21 is connected to bit line BLB1.
図４（ｂ）より、埋め込み酸化膜層１０１上に記憶ノード（１０２ａ、１０２ｂ）であるシリコン層よりなるＮ＋ソース拡散層（１０４ａ、１０４ｂ）がそれぞれ形成されている。ソース拡散層上にはシリサイド層（１１３ａ、１１３ｂ）が形成されている。ドライバトランジスタＱｎ１１のゲート電極から延在するゲート配線１１８ｂ上に形成されるコンタクト１１１ａは記憶ノード接続配線Ｎａを通じてＮ＋ソース拡散層１０４ｂ上に形成されるコンタクト１１０ｂに接続される。 As shown in FIG. 4B, N + source diffusion layers (104a, 104b) made of silicon layers as storage nodes (102a, 102b) are formed on the buried oxide film layer 101, respectively. Silicide layers (113a and 113b) are formed on the source diffusion layer. Contact 111a formed on gate line 118b extending from the gate electrode of driver transistor Qn11 is connected to contact 110b formed on N + source diffusion layer 104b through storage node connection line Na.
図４（ｃ）より、埋め込み酸化膜層１０１上に記憶ノードであるシリコン層よりなるＮ＋ソース拡散層（１０４ａ、１０４ｂ）が形成されている。Ｎ＋ソース拡散層上にはシリサイド層（１１３ａ、１１３ｂ）が形成されている。Ｎ＋ソース拡散層領域１０４ａにドライバトランジスタＱｎ１１を形成する柱状シリコン層１２２ａが形成され、Ｎ＋ソース拡散層領域１０４ｂにドライバトランジスタＱｎ２１を形成する柱状シリコン層１２２ｂが形成される。それぞれの柱状シリコン層の周囲にゲート絶縁膜１１７およびゲート電極１１８が形成されている。柱状シリコン層上部にはＮ＋ドレイン拡散層領域１１４が不純物注入などにより形成され、ドレイン拡散層領域表面にはシリサイド層１１５が形成されている。ドライバトランジスタ（Ｑｎ１１、Ｑｎ２１）上に形成されるコンタクト（１０８ａ、１０８ｂ）はともに配線層を通して接地電位Ｖｓｓ１に接続される。 As shown in FIG. 4C, N + source diffusion layers (104a, 104b) made of a silicon layer as a storage node are formed on the buried oxide film layer 101. Silicide layers (113a, 113b) are formed on the N + source diffusion layer. A columnar silicon layer 122a for forming the driver transistor Qn11 is formed in the N + source diffusion layer region 104a, and a columnar silicon layer 122b for forming the driver transistor Qn21 is formed in the N + source diffusion layer region 104b. A gate insulating film 117 and a gate electrode 118 are formed around each columnar silicon layer. An N + drain diffusion layer region 114 is formed on the columnar silicon layer by impurity implantation, and a silicide layer 115 is formed on the surface of the drain diffusion layer region. The contacts (108a, 108b) formed on the driver transistors (Qn11, Qn21) are both connected to the ground potential Vss1 through the wiring layer.
図４（ｄ）より、埋め込み酸化膜層１０１上に記憶ノードであるシリコン層よりなるＰ＋ソース拡散層１０３ａおよびＮ＋ソース拡散層１０４ａが形成される。ソース拡散層上にはシリサイド層１１３ａが形成され、シリサイド層１１３ａによってＰ＋ソース拡散層１０３ａとＮ＋ソース拡散層１０４ａは接続されている。
本実施例においてはシリサイドによってＮ＋ソース拡散層とＰ＋ソース拡散層が接続されているが、Ｎ＋ソース拡散層とＰ＋ソース拡散層間の接触抵抗が十分小さい場合にはシリサイドを形成する必要はない。また、シリサイドでＮ＋ソース拡散層とＰ＋ソース拡散層を接続する代わりにコンタクトでＮ＋ソース拡散層とＰ＋ソース拡散層で裏打ちすることによって接続したり、他の方法でＮ＋ソース拡散層とＰ＋ソース拡散層を接続してもよい。 As shown in FIG. 4D, a P + source diffusion layer 103a and an N + source diffusion layer 104a made of a silicon layer as a storage node are formed on the buried oxide film layer 101. A silicide layer 113a is formed on the source diffusion layer, and the P + source diffusion layer 103a and the N + source diffusion layer 104a are connected by the silicide layer 113a.
In this embodiment, the N + source diffusion layer and the P + source diffusion layer are connected by silicide. However, if the contact resistance between the N + source diffusion layer and the P + source diffusion layer is sufficiently small, it is not necessary to form silicide. Further, instead of connecting the N + source diffusion layer and the P + source diffusion layer with silicide, the N + source diffusion layer and the P + source diffusion layer are connected by contact with the N + source diffusion layer and the P + source diffusion layer by contact, or by other methods. Layers may be connected.
図４（ｅ）に図３（ａ）のＥ－Ｅ’における断面構造を示す。
埋め込み酸化膜層１０１上に左側のセル及び右側のセルのシリコン層よりなるＰ＋ソース拡散層１０３が形成されている。それぞれのソース拡散層上にはシリサイド層１１３が形成されている。それぞれのＰ＋ソース拡散層領域１０３上にアクセストランジスタを形成する柱状シリコン層１２１が形成され、Ｐ＋ソース拡散層領域１０３上にアクセストランジスタを形成する柱状シリコン層１２１が形成される。それぞれの柱状シリコン層の周囲にはゲート絶縁膜１１７およびゲート電極１１８が形成されている。柱状シリコン層上部にはＰ＋ドレイン拡散層領域１１６が不純物注入などにより形成され、ドレイン拡散層領域表面にはシリサイド層１１５が形成されている。それぞれのアクセストランジスタ上に形成されるコンタクト１０６はビット線に接続され、ワード線１１８ａ上に形成されるコンタクト１０７は上層の配線層により形成されるより低抵抗なワード線に接続される。 FIG. 4E shows a cross-sectional structure taken along line EE ′ of FIG.
On the buried oxide film layer 101, a P + source diffusion layer 103 made of the silicon layer of the left cell and the right cell is formed. A silicide layer 113 is formed on each source diffusion layer. A columnar silicon layer 121 for forming an access transistor is formed on each P + source diffusion layer region 103, and a columnar silicon layer 121 for forming an access transistor is formed on the P + source diffusion layer region 103. A gate insulating film 117 and a gate electrode 118 are formed around each columnar silicon layer. A P + drain diffusion layer region 116 is formed on the columnar silicon layer by impurity implantation or the like, and a silicide layer 115 is formed on the surface of the drain diffusion layer region. A contact 106 formed on each access transistor is connected to a bit line, and a contact 107 formed on the word line 118a is connected to a lower resistance word line formed by an upper wiring layer.
以下に本発明の半導体装置を形成するための製造方法の一例を図５～図１３を参照して説明する。各図において（ａ）は平面図、（ｂ）はＤ－Ｄ’間の断面図を示している。 An example of a manufacturing method for forming the semiconductor device of the present invention will be described below with reference to FIGS. In each figure, (a) is a plan view, and (b) is a cross-sectional view taken along D-D '.
図５に示されるように、ＳＯＩ基板上にシリコン窒化膜等を成膜して、柱状シリコン層（１２１ａ、１２２ａ、１２１ｂ、１２２ｂ）のパターンをリソグラフィーにより形成し、エッチングすることにより、シリコン窒化膜マスク１１９および柱状シリコン層（１２１ａ、１２２ａ、１２１ｂ、１２２ｂ）を形成する。 As shown in FIG. 5, a silicon nitride film or the like is formed on an SOI substrate, and a pattern of columnar silicon layers (121a, 122a, 121b, 122b) is formed by lithography and etched to form a silicon nitride film. A mask 119 and a columnar silicon layer (121a, 122a, 121b, 122b) are formed.
図６に示されるように、シリコン層（１２０）を分離して、記憶ノード（１０２ａ、１０２ｂ）であるシリコン層を形成する。 As shown in FIG. 6, the silicon layer (120) is separated to form a silicon layer which is a storage node (102a, 102b).
図７に示されるように、Ｐ＋注入領域１２４およびＮ＋注入領域１２５にそれぞれイオン注入などにより不純物を導入し、基板上に柱状シリコン層下部のドレイン拡散層（１０３ａ、１０３ｂ、１０４ａ、１０４ｂ）を形成する。 As shown in FIG. 7, impurities are introduced into the P + implantation region 124 and the N + implantation region 125 by ion implantation or the like to form drain diffusion layers (103a, 103b, 104a, 104b) below the columnar silicon layer on the substrate. To do.
図８に示されるように、ゲート絶縁膜１１７およびゲート導電膜１１８を成膜する。ゲート絶縁膜１１７は酸化膜やＨｉｇｈ－ｋ膜により形成される。また、ゲート導電膜はポリシリコンや金属膜により形成される。 As shown in FIG. 8, a gate insulating film 117 and a gate conductive film 118 are formed. The gate insulating film 117 is formed of an oxide film or a high-k film. The gate conductive film is formed of polysilicon or a metal film.
図９に示されるように、レジスト等１３３を用いて、リソグラフィーによりゲート配線パターンを形成する。 As shown in FIG. 9, a gate wiring pattern is formed by lithography using a resist 133 or the like.
図１０に示されるように、レジスト１３３をマスクにして、ゲート導電膜１１７及びゲート絶縁膜１１８をエッチングし、除去する。これによりゲート配線（１１８ａ～１１８ｃ）が形成される。 As shown in FIG. 10, the gate conductive film 117 and the gate insulating film 118 are etched and removed using the resist 133 as a mask. Thereby, gate wirings (118a to 118c) are formed.
図１１に示されるように、ピラー上のマスク１１９をウェットエッチやドライエッチでなどで除去する。 As shown in FIG. 11, the mask 119 on the pillar is removed by wet etching or dry etching.
図１２に示されるように、シリコン窒化膜等の絶縁膜を成膜後、エッチバックして、柱状シリコン層の側壁およびゲート電極の側壁をシリコン窒化膜等の絶縁膜１３４で覆う構造にする。 As shown in FIG. 12, after an insulating film such as a silicon nitride film is formed, it is etched back so that the sidewall of the columnar silicon layer and the sidewall of the gate electrode are covered with an insulating film 134 such as a silicon nitride film.
図１３に示されるように、Ｐ＋注入領域１２４およびＮ＋注入領域１２５にそれぞれイオン注入などにより不純物を導入し、柱状シリコン層上部のソース拡散層（１１４、１１６）を形成する。 As shown in FIG. 13, impurities are introduced into the P + implantation region 124 and the N + implantation region 125 by ion implantation or the like, respectively, to form source diffusion layers (114, 116) above the columnar silicon layer.
図１４に示されるように、Ｎｉなどの金属をスパッタして、熱処理を行うことにより、ドレイン拡散層上のシリサイド層（１１３ａ、１１３ｂ）および柱状シリコン層上部のソース拡散層上のシリサイド層１１５を形成する。
ここで、柱状シリコン層およびゲート電極の側壁を覆っているシリコン窒化膜等の絶縁膜１３４により、シリサイド層に起因するドレイン－ゲート間およびソース－ゲート間のショートを抑制することができる。 As shown in FIG. 14, by performing a heat treatment by sputtering a metal such as Ni, the silicide layers (113a, 113b) on the drain diffusion layer and the silicide layer 115 on the source diffusion layer above the columnar silicon layer are formed. Form.
Here, the drain-gate and source-gate short circuit due to the silicide layer can be suppressed by the insulating film 134 such as a silicon nitride film covering the columnar silicon layer and the side wall of the gate electrode.
図１５に示されるように、層間膜であるシリコン酸化膜を形成後にコンタクト（１０６ａ、１０６ｂ、１０８ａ、１０８ｂ、１１０ａ、１１０ｂ、１１１ａ、１１１ｂ）を形成する。 As shown in FIG. 15, contacts (106a, 106b, 108a, 108b, 110a, 110b, 111a, 111b) are formed after a silicon oxide film as an interlayer film is formed.
図１６に本実施例のＳＲＡＭレイアウトを示す。本実施例において実施例１と異なる点は、アクセストランジスタを形成する柱状シリコン層の形状とドライバトランジスタを形成する柱状シリコン層の大きさが異なる点である。本発明のＬｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭでは、アクセストランジスタのリーク電流をドライバトランジスタのリーク電流より大きく設定する必要がある。アクセストランジスタのリーク電流を増加させる一つの手段として、図１６のようにアクセストランジスタを形成する柱状シリコン層の周囲長を、ドライバトランジスタを形成する柱状シリコン層の周囲長より大きく設定することによってリーク電流を増加させることができる。
一方、読み出しマージンを改善したい場合には、ドライバトランジスタの柱状シリコン層の周囲長を、アクセストランジスタを形成する柱状シリコン層の周囲長より大きく形成して、ドライバトランジスタの電流を大きくすることによって読み出しマージンを改善することができる。
本実施例においては、一例として実施例１と同様のピラーのレイアウトを用いたが、実際には実施例１のレイアウトに限定されるものではなく、他の実施例のレイアウトにおいても同様に本実施例を適用することができる。
これ以外の点に関しては実施例１に示す構成と同一であるので説明を省略する。 FIG. 16 shows the SRAM layout of this embodiment. This embodiment is different from the first embodiment in that the shape of the columnar silicon layer forming the access transistor is different from the size of the columnar silicon layer forming the driver transistor. In the Loadless 4T-SRAM of the present invention, it is necessary to set the leak current of the access transistor to be larger than the leak current of the driver transistor. As one means for increasing the leakage current of the access transistor, the leakage current is set by setting the peripheral length of the columnar silicon layer forming the access transistor larger than the peripheral length of the columnar silicon layer forming the driver transistor as shown in FIG. Can be increased.
On the other hand, when it is desired to improve the read margin, the peripheral length of the columnar silicon layer of the driver transistor is formed larger than the peripheral length of the columnar silicon layer forming the access transistor, and the current of the driver transistor is increased to increase the read margin. Can be improved.
In this embodiment, the pillar layout similar to that of the first embodiment is used as an example. However, the layout of the first embodiment is not limited to the layout of the first embodiment. An example can be applied.
Since the other points are the same as the configuration shown in the first embodiment, description thereof is omitted.
図１７に本実施例のＳＲＡＭセルレイアウトを示す。本実施例においては以下の点において、実施例１と異なる。基板上の第１の拡散層により形成される記憶ノードであるＱａ３と、ドライバトランジスタＱｎ２３のゲート電極より延在するゲート配線は両者にまたがって形成される共通のコンタクト３１０ａにより接続され、基板上の第２の拡散層により形成される記憶ノードであるＱｂ３と、ドライバトランジスタＱｎ１３のゲート電極より延在するゲート配線は両者にまたがって形成される共通のコンタクト３１０ｂにより接続される。上記のようにゲートと記憶ノードを配線層ではなくコンタクトで直接接続することによって、ＳＲＡＭセル内におけるコンタクトの数を減らすことができるので、柱状シリコン層やコンタクトの配置を調整することによりセル面積を縮小することができる。
階層的な配線の構成の一例として、Ｖｓｓ３を下層の配線で形成し、ビット線（ＢＬ３、ＢＬＢ３）を上層の配線で形成する構成が実現可能である。なお、本実施例ではノード接続配線Ｎａ１、ノード接続配線Ｎｂ１はコンタクトにより形成されている。
本実施例においては、一例として実施例１と同様のピラーのレイアウトを用いたが、実際にはこのレイアウトに限定されるものではなく、他のレイアウトにおいても同様に本実施例を適用することができる。
これ以外の点に関しては実施例１に示す構成と同一であるので説明を省略する。 FIG. 17 shows the SRAM cell layout of this embodiment. The present embodiment is different from the first embodiment in the following points. The storage node Qa3 formed by the first diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn23 are connected to each other by a common contact 310a formed over both of them. Qb3, which is a storage node formed by the second diffusion layer, and a gate wiring extending from the gate electrode of driver transistor Qn13 are connected by a common contact 310b formed across both. As described above, the number of contacts in the SRAM cell can be reduced by directly connecting the gate and the storage node with the contact instead of the wiring layer. Therefore, the cell area can be reduced by adjusting the arrangement of the columnar silicon layer and the contact. Can be reduced.
As an example of a hierarchical wiring configuration, a configuration in which Vss3 is formed of a lower layer wiring and bit lines (BL3, BLB3) are formed of an upper layer wiring can be realized. In this embodiment, the node connection wiring Na1 and the node connection wiring Nb1 are formed by contacts.
In the present embodiment, the same pillar layout as in the first embodiment is used as an example. However, the layout is not limited to this layout in practice, and the present embodiment can be similarly applied to other layouts. it can.
Since the other points are the same as the configuration shown in the first embodiment, description thereof is omitted.
図１８に本実施例のＳＲＡＭセルレイアウトを示す。本実施例においては以下の点において、実施例１と異なる。実施例１においては、記憶ノードＱａ１上においては、コンタクト１１０ａはドライバトランジスタＱｎ１１にのみ隣接して配置されているが、記憶ノードＱｂ１上においては、コンタクト１１０ｂはドライバトランジスタＱｎ２１とアクセストランジスタＱｐ２１の間の拡散層上に配置されている。このようなレイアウトの非対称性により、ＳＲＡＭセルの特性に非対称性が生じ、動作マージンが狭くなる可能性がある。本実施例においては、第１の記憶ノードＱａ４上のアクセストランジスタＱｐ１４、コンタクト（４１０ａ、４１１ａ）及びドライバトランジスタＱｎ１４と第２の記憶ノードＱｂ４上のアクセストランジスタＱｐ２４、コンタクト（４１０ｂ、４１１ｂ）及びドライバトランジスタＱｎ２４のレイアウトが対称であるため、上記のような非対称性に起因する動作マージンの劣化はなく、広い動作マージンを持つＳＲＡＭセルが可能である。
階層的な配線の構成の一例として、ノード接続配線Ｎａ４、ノード接続配線Ｎｂ４、及び接地電位の配線Ｖｓｓ４を下層の配線で形成し、ビット線（ＢＬ１、ＢＬＢ１）を上層の配線で形成する構成が実現可能である。 FIG. 18 shows the SRAM cell layout of this embodiment. The present embodiment is different from the first embodiment in the following points. In the first embodiment, the contact 110a is disposed only adjacent to the driver transistor Qn11 on the storage node Qa1, but the contact 110b is provided between the driver transistor Qn21 and the access transistor Qp21 on the storage node Qb1. Arranged on the diffusion layer. Such an asymmetry of the layout may cause an asymmetry in the characteristics of the SRAM cell, and the operation margin may be narrowed. In this embodiment, the access transistor Qp14, contacts (410a, 411a) and driver transistor Qn14 on the first storage node Qa4 and the access transistor Qp24, contacts (410b, 411b) and driver transistor on the second storage node Qb4 are used. Since the layout of Qn24 is symmetric, the operation margin is not deteriorated due to the asymmetry as described above, and an SRAM cell having a wide operation margin is possible.
As an example of the hierarchical wiring configuration, the node connection wiring Na4, the node connection wiring Nb4, and the ground potential wiring Vss4 are formed by lower layer wirings, and the bit lines (BL1, BLB1) are formed by upper layer wirings. It is feasible.
図１９に本実施例のＳＲＡＭセルレイアウトを示す。
本実施例は実施例４と同様にレイアウトが対称であるため、広い動作マージンを持つＳＲＡＭセルが可能である。
また、実施例２と同様に、基板上の第１の拡散層により形成される記憶ノードであるＱａ５と、ドライバトランジスタＱｎ２５のゲート電極より延在するゲート配線は両者にまたがって形成される共通のコンタクト５１０ａにより接続され、基板上の第２の拡散層により形成される記憶ノードであるＱｂ５と、ドライバトランジスタＱｎ１５のゲート電極より延在するゲート配線は両者にまたがって形成される共通のコンタクト５１０ｂにより接続される。
なお、ビット線の配線及び接地電位の配線は、望ましくは、他のメモリセルの配線と共用するために、各メモリセル内での配線であるノード接続配線より上位の層に配置される。本実施例ではノード接続配線はコンタクトにより形成されている。
階層的な配線の構成の一例として、Ｖｓｓ３を下層の配線で形成し、ビット線（ＢＬ５、ＢＬＢ５）を上層の配線で形成する構成が実現可能である。なお、本実施例ではノード接続配線Ｎａ５、ノード接続配線Ｎｂ５はコンタクトにより形成されている。 FIG. 19 shows the SRAM cell layout of this embodiment.
Since the layout of this embodiment is symmetrical as in the fourth embodiment, an SRAM cell having a wide operation margin is possible.
Similarly to the second embodiment, Qa5, which is a storage node formed by the first diffusion layer on the substrate, and a gate wiring extending from the gate electrode of the driver transistor Qn25 are formed over both. The storage node Qb5 connected by the contact 510a and formed by the second diffusion layer on the substrate and the gate wiring extending from the gate electrode of the driver transistor Qn15 are connected by a common contact 510b formed over both. Connected.
Note that the bit line wiring and the ground potential wiring are preferably arranged in a layer higher than the node connection wiring which is a wiring in each memory cell, in order to share the wiring with other memory cells. In this embodiment, the node connection wiring is formed by contacts.
As an example of a hierarchical wiring configuration, it is possible to realize a configuration in which Vss3 is formed by a lower layer wiring and bit lines (BL5, BLB5) are formed by an upper layer wiring. In this embodiment, the node connection wiring Na5 and the node connection wiring Nb5 are formed by contacts.
図２０（ａ）に複数のＳＲＡＭメモリセルからなるＳＲＡＭメモリセルアレイの一部の平面図を示す。
図におけるＣｅｌｌ　ａｒｒａｙ　Ａｒｅａにおいては複数のメモリセルが横方向に配置されており、横方向に配置された複数のメモリセルにおいて、ワード線５１８ａが共通化されている。ワード線はＣｏｎｔａｃｔ　Ａｒｅａに形成されたコンタクト５０７により上層の配線に接続され、必要に応じて配線層で裏打ちされる。このため、特許文献２のＳＲＡＭセルとは異なり、各々のセルにワード線へのコンタクトを形成する必要がないので、ＳＲＡＭセル面積を縮小することができる。
ワード線５１８ａに複数のセルを接続することにより、ワード線コンタクト５０７から遠い側のセルにおいてはワード線の信号の遅延による読み出しや書き込みの遅延が問題になる可能性がある。このため、ワード線に接続するセルの数は読み出しや書き込みの遅延が問題ない範囲で決めることができる。
図２０（ｂ）に他の場合における複数のＳＲＡＭセルからなるＳＲＡＭセルアレイの一部の平面図を示す。図におけるＣｅｌｌ　ａｒｒａｙ　Ａｒｅａにおいても同様に、複数のメモリセルが横方向に配置されており、横方向に配置されたメモリセルにおいて、ワード線５１８ａが共通化されている。しかし、図２０（ｂ）においてはＣｏｎｔａｃｔ　Ａｒｅａにおいても、Ｃｅｌｌ　ａｒｒａｙ　Ａｒｅａと同様にピラーが配置されている。このようにＣｏｎｔａｃｔ 　Ａｒｅａにおいてもピラーを配置することにより、Ｃｏｎｔａｃｔ　Ａｒｅａに隣接するＳＧＴの特性とＣｏｎｔａｃｔ　Ａｒｅａに隣接していないＳＧＴとの特性の誤差を最小限に抑えることができる。 FIG. 20A shows a plan view of a part of an SRAM memory cell array composed of a plurality of SRAM memory cells.
In the cell array area in the figure, a plurality of memory cells are arranged in the horizontal direction, and the word lines 518a are shared by the plurality of memory cells arranged in the horizontal direction. The word line is connected to the upper layer wiring by a contact 507 formed in the contact area, and backed by the wiring layer as necessary. Therefore, unlike the SRAM cell of Patent Document 2, it is not necessary to form a contact to the word line in each cell, so that the SRAM cell area can be reduced.
By connecting a plurality of cells to the word line 518a, a read or write delay due to a delay of a word line signal may be a problem in a cell far from the word line contact 507. For this reason, the number of cells connected to the word line can be determined within a range in which there is no problem in reading or writing delay.
FIG. 20B shows a plan view of a part of an SRAM cell array composed of a plurality of SRAM cells in other cases. Similarly, in the cell array area in the figure, a plurality of memory cells are arranged in the horizontal direction, and the word line 518a is shared in the memory cells arranged in the horizontal direction. However, in FIG. 20B, pillars are arranged in the contact area as well as in the cell array area. As described above, by arranging the pillars in the contact area, it is possible to minimize the error in the characteristics of the SGT adjacent to the contact area and the SGT not adjacent to the contact area.
以上説明したように、本発明によれば４個のＭＯＳトランジスタを用いて構成されたスタティック型メモリセルにおいて、前記ＭＯＳトランジスタはドレイン、ゲート、ソースが垂直方向に配置されたＳＧＴであり、アクセストランジスタのゲートをワードラインとして一列（図面では横方向）に隣接する複数のセルで共通化し、ワード線へのコンタクトを複数のセルごとに１個形成することにより、非常に小さいメモリセル面積を持つＣＭＯＳ型Ｌｏａｄｌｅｓｓ４Ｔ－ＳＲＡＭを実現することができる。 As described above, according to the present invention, in a static memory cell configured using four MOS transistors, the MOS transistor is an SGT in which a drain, a gate, and a source are arranged in a vertical direction, and an access transistor CMOS having a very small memory cell area by sharing a plurality of cells adjacent to each other in a row (in the horizontal direction in the drawing) as a word line and forming one contact to the word line for each of the plurality of cells. A type Loadless 4T-SRAM can be realized.
１０１、２０１、３０１、４０１、５０１：埋め込み酸化膜
１０２、１０２ａ、１０２ｂ、２０２ａ、２０２ｂ、３０２ａ、３０２ｂ、４０２ａ、４０２ｂ、５０２ａ、５０２ｂ、６０２ａ、６０２ｂ：シリコン層
１０３、１０３ａ、１０３ｂ、２０３ａ、２０３ｂ、６０３ａ、６０３ｂ：ｐ＋拡散層
１０４ａ、１０４ｂ、２０４ａ、２０４ｂ、６０４ａ、６０４ｂ：ｎ＋拡散層
１０６、１０６ａ、２０６ａ、３０６ａ、４０６ａ、５０６ａ、１０６ｂ、２０６ｂ、３０６ｂ、４０６ｂ、５０６ｂ：アクセストランジスタ柱状シリコン層上コンタクト
１０７：ワード線コンタクト
１０８ａ、２０８ａ、３０８ａ、４０８ａ、５０８ａ、１０８ｂ、２０８ｂ、３０８ｂ、４０８ｂ、５０８ｂ：ドライバトランジスタ柱状シリコン層上コンタクト
１１０ａ、２１０ａ、３１０ａ、４１０ａ、１１０ｂ、２１０ｂ、３１０ｂ、４１０ｂ：記憶ノード上コンタクト
１１１ａ、２１１ａ、１１１ｂ、２１１ｂ：ゲート配線上コンタクト
１１３、１１３ａ、１１３ｂ、１１５、５１３ａ、５１３ｂ、５１５：シリサイド層
１１４、５１４：ピラー上部Ｎ＋拡散層
１１６、５１６：ピラー上部Ｐ＋拡散層
１１７、５１７：ゲート絶縁膜
１１８、５１８：ゲート電極
１１８ａ、１１８ｂ、１１８ｃ、５１８ａ、５１８ｂ、５１８ｃ：ゲート配線
１１８ａ、２１８ａ、３１８ａ、４１８ａ：ワード線
１１９：シリコン酸化膜等のマスク層
１２０：シリコン層
１２１、１２１ａ、１２１ｂ、５２１ａ、５２１ｂ：アクセストランジスタ柱状シリコン層
１２２ａ、１２２ｂ、５２２ａ、５２２ｂ：ドライバトランジスタ柱状シリコン層
１２４、５２４：Ｐ＋注入領域
１２５、５２５：Ｎ＋注入領域
１３１：シリコン酸化膜
１３２：シリコン窒化膜サイドウォール
１３３：レジスト
１３４：シリコン窒化膜
Ｑｐ１１、Ｑｐ２１、Ｑｐ１２、Ｑｐ２２、Ｑｐ１３、Ｑｐ２３、Ｑｐ１４、Ｑｐ２４、Ｑｐ１５、Ｑｐ２５：アクセストランジスタ
Ｑｎ１１、Ｑｎ２１、Ｑｎ１２、Ｑｎ２２、Ｑｎ１３、Ｑｎ２３、Ｑｎ１４、Ｑｎ２４、Ｑｎ１５、Ｑｎ２５：ドライバトランジスタ
ＢＬ１、ＢＬ３、ＢＬ４、ＢＬ５、ＢＬＢ１、ＢＬＢ３、ＢＬＢ４、ＢＬＢ５：ビット線
Ｖｓｓ１、Ｖｓｓ２、Ｖｓｓ３、Ｖｓｓ４、Ｖｓｓ５：接地電位線
Ｎａ１、Ｎｂ１、Ｎａ２、Ｎｂ２、Ｎａ５、Ｎｂ５：ノード接続配線 101, 201, 301, 401, 501: buried oxide films 102, 102a, 102b, 202a, 202b, 302a, 302b, 402a, 402b, 502a, 502b, 602a, 602b: silicon layers 103, 103a, 103b, 203a, 203b 603a, 603b: p + diffusion layers 104a, 104b, 204a, 204b, 604a, 604b: n + diffusion layers 106, 106a, 206a, 306a, 406a, 506a, 106b, 206b, 306b, 406b, 506b: access transistor columnar silicon layers Upper contact 107: Word line contact 108a, 208a, 308a, 408a, 508a, 108b, 208b, 308b, 408b, 508b: Driver transistor columnar silicon layer upper contact 10a, 210a, 310a, 410a, 110b, 210b, 310b, 410b: storage node contacts 111a, 211a, 111b, 211b: gate wiring contacts 113, 113a, 113b, 115, 513a, 513b, 515: silicide layers 114, 514: Pillar upper N + diffusion layer 116, 516: Pillar upper P + diffusion layer 117, 517: Gate insulating film 118, 518: Gate electrodes 118a, 118b, 118c, 518a, 518b, 518c: Gate wirings 118a, 218a, 318a, 418a : Word line 119: Mask layer 120 such as silicon oxide film: Silicon layers 121, 121a, 121b, 521a, 521b: Access transistor columnar silicon layers 122a, 122b, 522a, 522b: Driver Transistor columnar silicon layers 124, 524: P + implantation region 125, 525: N + implantation region 131: Silicon oxide film 132: Silicon nitride film sidewall 133: Resist 134: Silicon nitride films Qp11, Qp21, Qp12, Qp22, Qp13, Qp23, Qp14, Qp24, Qp15, Qp25: Access transistors Qn11, Qn21, Qn12, Qn22, Qn13, Qn23, Qn14, Qn24, Qn15, Qn25: Driver transistors BL1, BL3, BL4, BL5, BLB1, BLB3, BLB4, BLB5: Bit lines Vss1, Vss2, Vss3, Vss4, Vss5: Ground potential lines Na1, Nb1, Na2, Nb2, Na5, Nb5: Node connection wiring

Claims (6)

  1. 　４個のＭＯＳトランジスタが基板上に形成された絶縁膜上に配列された複数のスタティック型メモリセルを備えた半導体記憶装置であって、
    　前記４個のＭＯＳトランジスタの各々は、
    　メモリセルデータを保持するために電荷を供給すると共にメモリにアクセスするための第１及び第２のＰＭＯＳのアクセストランジスタと、メモリセルのデータを書き込み及び読み出しするために記憶ノードを駆動する第１及び第２のＮＭＯＳのドライバトランジスタとして機能し、
    　前記第１及び第２のＰＭＯＳのアクセストランジスタにおいて、
    　Ｐ型の導電型を持つ第１の拡散層、第１の柱状半導体層及びＰ型の導電型を持つ第２の拡散層が、基板上に形成された絶縁膜上に垂直方向に階層的に配置され、前記第１の柱状半導体層は前記第１の柱状半導体層の底部に形成される前記第１の拡散層と前記第１の柱状半導体層の上部に形成される前記第２の拡散層の間に配置され、前記第１の柱状半導体層の側壁にゲート絶縁膜及びゲートが形成されており、
    　前記第１及び第２のＮＭＯＳのドライバトランジスタにおいて、
    　Ｎ型の導電型を持つ第３の拡散層、第２の柱状半導体層及びＮ型の導電型を持つ第４の拡散層が、基板上に形成された絶縁膜上に垂直方向に階層的に配置され、前記第２の柱状半導体層は前記第２の柱状半導体層の底部に形成される前記第３の拡散層と前記第１の柱状半導体層の上部に形成される前記第４の拡散層の間に配置され、前記第２の柱状半導体層の側壁にゲート絶縁膜及びゲートが形成されており、
    　前記第１のＰＭＯＳのアクセストランジスタ及び前記第１のＮＭＯＳのドライバトランジスタは、互いに隣接して配列され、
    　前記第２のＰＭＯＳのアクセストランジスタ及び前記第２のＮＭＯＳのドライバトランジスタは、互いに隣接して配列され、
    　データを保持する第１の記憶ノードとして機能する、前記第１のＰＭＯＳのアクセストランジスタの底部に形成されるＰ型の導電型を持つ前記第１の拡散層及び前記第１のＮＭＯＳのドライバトランジスタの底部に形成されるＮ型の導電型を持つ前記第３の拡散層を前記絶縁膜上に配置し、
    　前記第１の記憶ノードとして機能する、前記第１の拡散層、前記第３の拡散層は相互に接続され、
    　データを保持する第２の記憶ノードとして機能する、前記第２のＰＭＯＳのアクセストランジスタの底部に形成されるＰ型の導電型を持つ前記第１の拡散層及び前記第２のＮＭＯＳのドライバトランジスタの底部に形成されるＮ型の導電型を持つ前記第３の拡散層を前記絶縁膜上に配置し、
    　前記第２の記憶ノードとして機能する、前記第１の拡散層、前記第３の拡散層は相互に接続され、
    　前記第１及び前記第２のＰＭＯＳのドライバトランジスタのそれぞれのゲートは第１のゲート配線により互いに接続され、前記第１のゲート配線は隣接する複数のメモリセルにおける前記第１及び前記第２のＰＭＯＳのアクセストランジスタのそれぞれのゲートと互いに接続されることによりワード線を形成しており、
    　隣接する複数のメモリセルごとに、ワード線である前記第１のゲート配線上に第１のコンタクトが形成されることを特徴とする半導体記憶装置。     A semiconductor memory device comprising a plurality of static memory cells in which four MOS transistors are arranged on an insulating film formed on a substrate,
    Each of the four MOS transistors is
    First and second PMOS access transistors for supplying charge to hold memory cell data and accessing the memory, and for driving the storage node to write and read data in the memory cell Functions as a second NMOS driver transistor,
    In the first and second PMOS access transistors,
    A first diffusion layer having a P-type conductivity, a first columnar semiconductor layer, and a second diffusion layer having a P-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on a substrate. The first columnar semiconductor layer is disposed, and the first diffusion layer formed on the bottom of the first columnar semiconductor layer and the second diffusion layer formed on the top of the first columnar semiconductor layer A gate insulating film and a gate are formed on sidewalls of the first columnar semiconductor layer,
    In the first and second NMOS driver transistors,
    A third diffusion layer having an N-type conductivity, a second columnar semiconductor layer, and a fourth diffusion layer having an N-type conductivity are hierarchically formed in a vertical direction on an insulating film formed on the substrate. The second columnar semiconductor layer is disposed, and the third diffusion layer formed on the bottom of the second columnar semiconductor layer and the fourth diffusion layer formed on the top of the first columnar semiconductor layer. A gate insulating film and a gate are formed on sidewalls of the second columnar semiconductor layer,
    The first PMOS access transistor and the first NMOS driver transistor are arranged adjacent to each other,
    The second PMOS access transistor and the second NMOS driver transistor are arranged adjacent to each other,
    The first diffusion layer having the P-type conductivity formed at the bottom of the first PMOS access transistor and the first NMOS driver transistor functioning as a first storage node for holding data Disposing the third diffusion layer having the N-type conductivity type formed on the bottom on the insulating film;
    The first diffusion layer and the third diffusion layer functioning as the first storage node are connected to each other,
    The first diffusion layer having the P-type conductivity formed at the bottom of the second PMOS access transistor and the second NMOS driver transistor functioning as a second storage node for holding data Disposing the third diffusion layer having the N-type conductivity type formed on the bottom on the insulating film;
    The first diffusion layer and the third diffusion layer functioning as the second storage node are connected to each other,
    The gates of the first and second PMOS driver transistors are connected to each other by a first gate line, and the first gate line is connected to the first and second PMOSs in a plurality of adjacent memory cells. A word line is formed by being connected to each gate of the access transistors of
    A semiconductor memory device, wherein a first contact is formed on the first gate wiring that is a word line for each of a plurality of adjacent memory cells.
  2. 　前記ワード線である前記第１のゲート配線上に前記第１のコンタクトが形成される領域において、メモリセルの領域と同様にピラーが配置されていることを特徴とする請求項１に記載の半導体記憶装置。 2. The semiconductor according to claim 1, wherein a pillar is disposed in a region where the first contact is formed on the first gate wiring which is the word line, similarly to a memory cell region. Storage device.
  3. 　前記第１のＮＭＯＳのドライバトランジスタのゲートより延在する第２のゲート配線が、前記第２の記憶ノードとして機能する拡散層と共通の第２のコンタクトにより接続され、
    　前記第２のＮＭＯＳのドライバトランジスタのゲートより延在する第３のゲート配線が、前記第１の記憶ノードとして機能する拡散層と共通の第３のコンタクトにより接続されることを特徴とする請求項１に記載の半導体記憶装置。     A second gate wiring extending from a gate of the first NMOS driver transistor is connected to the diffusion layer functioning as the second storage node by a second contact in common;
    The third gate wiring extending from the gate of the second NMOS driver transistor is connected to the diffusion layer functioning as the first storage node by a common third contact. 2. The semiconductor memory device according to 1.
  4. 　前記第１及び第２のＮＭＯＳのドライバトランジスタを形成する柱状半導体層の側壁の周囲長は、前記第１及び第２のＰＭＯＳのアクセストランジスタを形成する柱状半導体層の側壁の周囲長以上の値を持つこと、
    　又は前記第１及び第２のＮＭＯＳのドライバトランジスタを形成する柱状半導体層の側壁の周囲長は、前記第１及び第２のＰＭＯＳのアクセストランジスタを形成する柱状半導体層の側壁の周囲長以下の値を持つことを特徴とする請求項１に記載の半導体記憶装置。     The peripheral length of the side wall of the columnar semiconductor layer that forms the first and second NMOS driver transistors is equal to or greater than the peripheral length of the side wall of the columnar semiconductor layer that forms the first and second PMOS access transistors. Having
    Alternatively, the peripheral length of the side wall of the columnar semiconductor layer forming the first and second NMOS driver transistors is equal to or less than the peripheral length of the side wall of the columnar semiconductor layer forming the first and second PMOS access transistors. The semiconductor memory device according to claim 1, wherein:
  5. 　前記４個のＭＯＳトランジスタは、前記絶縁膜上に２行２列に配列され、
    　前記第１のＰＭＯＳのアクセストランジスタは１行１列目に配列され、
    　前記第１のＮＭＯＳのドライバトランジスタは２行１列目に配列され、
    　前記第２のＰＭＯＳのアクセストランジスタは１行２列目に配列され、
    　前記第２のＮＭＯＳのドライバトランジスタは２行２列目に配列されていることを特徴とする請求項１に記載の半導体記憶装置。     The four MOS transistors are arranged in two rows and two columns on the insulating film,
    The first PMOS access transistor is arranged in the first row and the first column,
    The first NMOS driver transistor is arranged in the second row and the first column,
    The second PMOS access transistor is arranged in the first row and the second column,
    2. The semiconductor memory device according to claim 1, wherein the second NMOS driver transistors are arranged in the second row and the second column.
  6. 　前記４個のＭＯＳトランジスタは前記絶縁膜上に配列され、
    　前記第１のＰＭＯＳのアクセストランジスタと前記第２のＰＭＯＳのアクセストランジスタは隣接して配列され、
    　前記第１のＰＭＯＳのアクセストランジスタと前記第２のＰＭＯＳのアクセストランジスタの隣接方向に直交する一方の方向において前記第１のＮＭＯＳのドライバトランジスタは前記第１のＰＭＯＳのアクセストランジスタと隣接して配列され、
    　前記第１のＰＭＯＳのアクセストランジスタと前記第２のＰＭＯＳのアクセストランジスタの隣接方向に直交する他方の方向において前記第２のＮＭＯＳのドライバトランジスタは前記第２のＰＭＯＳのアクセストランジスタと隣接して配列されていることを特徴とする請求項１に記載の半導体記憶装置。     The four MOS transistors are arranged on the insulating film,
    The first PMOS access transistor and the second PMOS access transistor are arranged adjacent to each other;
    The first NMOS driver transistor is arranged adjacent to the first PMOS access transistor in one direction orthogonal to the adjacent direction of the first PMOS access transistor and the second PMOS access transistor. ,
    The second NMOS driver transistor is arranged adjacent to the second PMOS access transistor in the other direction orthogonal to the adjacent direction of the first PMOS access transistor and the second PMOS access transistor. The semiconductor memory device according to claim 1, wherein:
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