WO2013100085A1 - Solar cell element, method for manufacturing solar cell element, and solar cell module - Google Patents
Solar cell element, method for manufacturing solar cell element, and solar cell module Download PDFInfo
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- WO2013100085A1 WO2013100085A1 PCT/JP2012/083957 JP2012083957W WO2013100085A1 WO 2013100085 A1 WO2013100085 A1 WO 2013100085A1 JP 2012083957 W JP2012083957 W JP 2012083957W WO 2013100085 A1 WO2013100085 A1 WO 2013100085A1
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- solar cell
- passivation layer
- layer
- cell element
- main surface
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Definitions
- the present invention relates to a solar cell element, a method for manufacturing a solar cell element, and a solar cell module including the solar cell element.
- a passivation film is provided on the surface of the silicon substrate in order to reduce minority carrier recombination.
- the passivation film use of an oxide film made of silicon oxide, aluminum oxide, or the like, or a nitride film made of a silicon nitride film or the like has been studied (see, for example, JP-A-2009-164544).
- the solar cell elements having the above-described configuration may not be improved enough to contribute to power generation efficiency. Therefore, a solar cell element, a manufacturing method thereof, and a solar cell module in which output characteristics are further improved by reducing carrier recombination are desired.
- a solar cell element has an n-type semiconductor region on a first main surface, and a second main surface located on the side opposite to the first main surface.
- an antireflection layer having a fixed charge density larger than that of the first passivation layer on the positive side.
- a solar cell element has an n-type semiconductor region on a first main surface, and a p-type semiconductor region on a second main surface located on the opposite side to the first main surface.
- a semiconductor substrate made of silicon and having a first passivation layer which is disposed on the n-type semiconductor region and is made of at least one selected from aluminum oxide, hafnium oxide and zirconium oxide, and It may be provided with an antireflection layer made of silicon oxide or silicon nitride disposed on one passivation layer.
- the first main surface has an n-type semiconductor region
- the second main surface located on the side opposite to the first main surface is p.
- a solar cell module includes the solar cell element having the above-described configuration.
- FIG. 2 is a schematic view showing an example of a solar cell element according to an embodiment of the present invention, and is a cross-sectional view taken along line AA in FIG. It is the plane schematic diagram which looked at an example of the solar cell element concerning one form of the present invention from the 2nd principal surface side.
- ⁇ Basic configuration of solar cell element> 1 to 3 show a solar cell element 10 according to the present embodiment.
- the solar cell element 10 has an n-type semiconductor region on the first main surface 10a, and a semiconductor having a p-type semiconductor region on the second main surface 10b located on the opposite side of the first main surface 10a.
- the basic configuration is that the antireflection layer 5 having a fixed charge density larger on the positive side than the layer 8 is provided.
- the solar cell element 10 has an n-type semiconductor region on the first main surface 10a, and has a p-type semiconductor region on the second main surface 10b located on the opposite side to the first main surface 10a.
- a semiconductor substrate 1 made of silicon, a first passivation layer 8 disposed on the n-type semiconductor region and made of at least one selected from aluminum oxide, hafnium oxide and zirconium oxide, and a first passivation layer
- an antireflection layer 5 made of silicon oxide or silicon nitride.
- the solar cell element 10 includes a light receiving surface (a top surface in FIG. 3 and hereinafter referred to as a first main surface) 10a on which light is incident, and the first main surface 10a. It has a non-light-receiving surface (a lower surface in FIG. 3, hereinafter referred to as a second main surface) 10b corresponding to a surface (back surface) located on the opposite side, and a side surface 10c.
- the solar cell element 10 includes a semiconductor substrate 1 which is a plate-like polycrystalline silicon substrate, for example.
- the semiconductor substrate 1 is provided, for example, on the first semiconductor layer 2 that is a one-conductivity type semiconductor region (p-type semiconductor region) and on the first main surface 10 a side in the first semiconductor layer 2. And a second semiconductor layer 3 which is a reverse conductivity type semiconductor region (n-type semiconductor region).
- the solar cell element 10 is disposed on the second semiconductor layer 3 (specifically, on the first main surface 10a side of the second semiconductor layer 3), and the first passivation layer 8 made of aluminum oxide or the like.
- an antireflection layer 5 made of silicon nitride, for example, on the first passivation layer 8.
- the solar cell element 10 is disposed on the first semiconductor layer 2 (specifically, on the second main surface 10b side of the first semiconductor layer 2), and the second passivation layer 9 made of aluminum oxide or the like. It has.
- the solar cell element 10 includes a semiconductor substrate 1 (first semiconductor layer 2 and second semiconductor layer 3), a third semiconductor layer 4, an antireflection layer 5, a first electrode 6, A second electrode 7, a first passivation layer 8 and a second passivation layer 9 are provided.
- the semiconductor substrate 1 is a polycrystalline silicon substrate, and includes the first semiconductor layer 2 and the second semiconductor layer 3 provided on the first main surface 10a side of the first semiconductor layer 2. .
- the first semiconductor layer 2 As the first semiconductor layer 2, as described above, a plate-like semiconductor exhibiting a p-type can be used.
- a polycrystalline silicon substrate As the semiconductor constituting the first semiconductor layer 2, a polycrystalline silicon substrate can be used.
- the average thickness of the first semiconductor layer 2 can be, for example, 250 ⁇ m or less, and further 150 ⁇ m or less.
- the shape of the 1st semiconductor layer 2 is not specifically limited, From a viewpoint on a manufacturing method, it is good also as a square shape by planar view. If the first semiconductor layer 2 made of a polycrystalline silicon substrate is p-type, for example, boron or gallium can be used as the dopant element.
- the second semiconductor layer 3 is a semiconductor layer that forms a pn junction with this and the first semiconductor layer 2.
- the second semiconductor layer 3 is a layer having a conductivity type opposite to that of the first semiconductor layer 2, that is, an n-type, and is provided on the first main surface 10 a side in the first semiconductor layer 2.
- the second semiconductor layer 3 can be formed by diffusing impurities such as phosphorus on the first main surface 10a side of the silicon substrate.
- a pyramidal uneven shape 1 a is provided on the first main surface 10 a side of the semiconductor substrate 1.
- the height of the convex portion of the concavo-convex shape 1a is about 0.1 to 10 ⁇ m, and the width of the convex portion is about 0.1 to 20 ⁇ m.
- the shape of the concavo-convex shape 1a is not limited to the pyramid shape, and may be a concavo-convex shape in which the concave portion is substantially spherical.
- the height of the convex portion here refers to, for example, a straight line passing through the bottom surface of the concave portion in the cross-sectional view of FIG. 3, and from the reference line to the top surface of the convex portion in a direction perpendicular to the reference line. Is the distance.
- the width of the convex portion is a distance between the top surfaces of adjacent convex portions in a direction parallel to the reference line.
- the first passivation layer 8 is formed on the first main surface 10a side of the semiconductor substrate 1.
- the first passivation layer 8 is composed of a layer containing at least one selected from aluminum oxide, hafnium oxide, and zirconium oxide.
- the first passivation layer 8 can be an aluminum oxide layer, a hafnium oxide layer, or a zirconium oxide layer.
- the n-type second semiconductor layer 3 has minority carriers (holes) at the interface with the first passivation layer. ) The band near the interface bends in the direction of rising. This has the problem of increased surface recombination.
- the antireflection layer 5 that is larger on the positive side than the negative fixed charge density of this layer is formed.
- the antireflection layer 5 having a large fixed charge density on the positive side is the antireflection layer 5 having a positive fixed charge density or the antireflection layer 5 having a negative fixed charge density smaller than that of the first passivation layer 8.
- the average thickness of the first passivation layer 8 can be about 30 to 1000 mm, for example.
- the antireflection layer 5 is formed of, for example, a silicon nitride layer or a silicon oxide layer.
- the thickness of the antireflection layer 5 can be appropriately selected depending on the type of material, and may be a thickness that can realize non-reflection conditions with respect to appropriate incident light.
- the antireflective layer 5 can have a refractive index of about 1.8 to 2.3 and an average thickness of about 200 to 1200 mm.
- the fixed charge density of the aluminum oxide layer is about ⁇ 1 ⁇ 10 11 to ⁇ 1 ⁇ 10 13 cm ⁇ 2 , and the fixed charge densities of hafnium oxide and zirconium oxide are ⁇ 1 ⁇ 10 11 to ⁇ 5 ⁇ 10 12 cm ⁇ 2.
- the fixed charge density of the silicon nitride layer is about + 1 ⁇ 10 12 cm ⁇ 2 , and the fixed charge density of the silicon oxide layer is about + 6 ⁇ 10 10 cm ⁇ 2 .
- the fixed charge density of the passivation layer can be calculated by, for example, a capacitance-voltage measurement method (CV measurement method).
- an aluminum electrode is disposed on the passivation layer disposed on the surface of the semiconductor substrate, and an aluminum electrode disposed on the back surface of the semiconductor substrate is disposed and applied by changing within a certain range between the aluminum electrodes. It can be calculated from a CV characteristic curve obtained by measuring each capacity at each voltage.
- the second passivation layer 9 is formed on the second main surface 10b side of the semiconductor substrate 1.
- the second passivation layer 9 is composed of a layer containing one or more selected from aluminum oxide, hafnium oxide and zirconium oxide. According to the said structure, the open circuit voltage is high and the solar cell element excellent in output characteristics can be obtained. This is presumably because surface recombination could be reduced by the surface passivation effect.
- the aluminum oxide layer, the hafnium oxide layer, and the zirconium oxide layer all have a negative fixed charge density
- the semiconductor substrate 1 At the interface between the first semiconductor layer 2) and the second passivation layer 9, the band near the interface is bent in the direction in which minority carriers (electrons) decrease, so that surface recombination can be further reduced.
- the average thickness of the second passivation layer 9 can be about 30 to 1000 mm, for example.
- the first passivation layer 8 and the second passivation layer 9 are mainly made of an amorphous aluminum oxide layer, for example, so that a large amount of hydrogen is contained in the aluminum oxide, and hydrogen is easily diffused into the semiconductor substrate. Become.
- the above “mainly amorphous aluminum oxide layer” means that the crystallization rate in the aluminum oxide layer is less than 50%.
- the dangling bonds are terminated with hydrogen due to the presence of the aluminum oxide layer, and surface recombination can be further reduced.
- the crystalline aluminum oxide layer tends to grow perpendicular to the growth interface. Therefore, when using a substrate having a grain boundary and a crystal grain having a different crystal orientation such as a polycrystalline silicon substrate, the growth interface of the crystalline aluminum oxide layer has a grain boundary and crystal orientation of the substrate surface. It is easily affected and the growth interface of the aluminum oxide layer tends to have a random direction.
- the semiconductor substrate 1 when a polycrystalline silicon substrate is used as the semiconductor substrate 1, an amorphous aluminum oxide layer is mainly used. Under the influence of crystal grain boundaries and crystal orientations on the surface of the polycrystalline silicon substrate, the crystalline aluminum oxide layer grows in random directions, and the crystal grains that have started to interfere with each other cause this interference. It is possible to reduce the occurrence of defects on the surface. As a result, the first passivation layer 8 and the second passivation layer 9 can have an excellent passivation effect.
- the average thickness of the first passivation layer 8 thinner than the average thickness of the antireflection film layer 5, it is possible to reduce the loss of light due to reflection, and to reduce the deterioration of output characteristics.
- what is necessary is just to average the result of having measured 5 places, for example using said ellipsometer (SE-400adv by SENTECH) for said average thickness.
- first passivation layer 8 and the second passivation layer 9 can have a further excellent passivation effect by being composed of layers having a negative fixed charge density, such as the same aluminum oxide layer. .
- the generation of leakage current can be further reduced and the fabrication can be performed easily.
- the side surface 10c of the semiconductor substrate 1 has a third passivation layer having a negative fixed charge density such as an aluminum oxide layer. 11 may be provided.
- the antireflection layer 5 may be provided on the side surface of the semiconductor substrate 1, and at this time, the antireflection layer 5 is preferably formed using an insulating material.
- the antireflection layer 5 fills the opening and comes into contact with the first semiconductor layer 2. Therefore, since the antireflection layer 5 is made of an insulating material, the generation of leakage current can be reduced.
- the third semiconductor layer 4 is disposed on the second main surface 10b side of the semiconductor substrate 1 and has the same conductivity type as the first semiconductor layer 2, that is, p-type.
- the concentration of the dopant contained in the third semiconductor layer 4 is higher than the concentration of the dopant contained in the first semiconductor layer 2. That is, the dopant element is present in the third semiconductor layer 4 at a concentration higher than the concentration of the dopant element doped to exhibit one conductivity type in the first semiconductor layer 2.
- the third semiconductor layer 4 has a role of reducing a decrease in conversion efficiency due to carrier recombination in the vicinity of the second main surface 10b of the semiconductor substrate 1, and the second main surface 10b of the semiconductor substrate 1 is used. An internal electric field is formed on the side.
- the third semiconductor layer 4 can be formed, for example, by diffusing a dopant element such as boron or aluminum on the second main surface 10b side of the semiconductor substrate 1. At this time, the concentration of the dopant element contained in the third semiconductor layer 4 can be about 1 ⁇ 10 18 to 5 ⁇ 10 21 atoms / cm 3 .
- the third semiconductor layer 4 is preferably formed at a contact portion between a second electrode 7 and a semiconductor substrate 1 described later.
- the first electrode 6 is an electrode provided on the first main surface 10a side of the semiconductor substrate 1, and as shown in FIG. 1, the first output extraction electrode 6a and a plurality of linear first current collecting electrodes 6b. And have. At least a part of the first output extraction electrode 6a intersects the first current collecting electrode 6b and is electrically connected.
- the first current collecting electrode 6b is linear and has a width of, for example, about 50 to 200 ⁇ m in the lateral direction.
- the first output extraction electrode 6a has a width of, for example, about 1.3 to 2.5 mm in the short direction. And the width
- a plurality of first current collecting electrodes 6b are provided with an interval of about 1.5 to 3 mm.
- the thickness of the first electrode 6 is about 10 to 40 ⁇ m.
- Such a first electrode 6 can be formed by, for example, applying a conductive paste containing silver as a main component into a desired shape by screen printing or the like and then baking it.
- the second electrode 7 is an electrode provided on the second main surface 10b side of the semiconductor substrate 1, and has, for example, the same form as the first electrode, that is, as shown in FIG. 2, the second output extraction electrode 7a and And a plurality of linear second collector electrodes 7b. At least a part of the second output extraction electrode 7a intersects the second collector electrode 7b and is electrically connected.
- the second current collecting electrode 7b is linear and has a width of, for example, about 50 to 300 ⁇ m in the short direction.
- the second output extraction electrode 7a has a width of, for example, about 1.3 to 3 mm in the short direction.
- the width of the second collector electrode 7b in the short direction is smaller than the width of the second output extraction electrode 7a in the short direction.
- a plurality of second current collecting electrodes 7b are provided with an interval of about 1.5 to 3 mm.
- the thickness of the second electrode 7 is about 10 to 40 ⁇ m.
- Such a second electrode 7 can be formed by, for example, applying a conductive paste containing silver as a main component into a desired shape by screen printing or the like and then baking it.
- the 2nd electrode 7 can make the width
- aluminum may be mainly used as the material of the second collector electrode 7b, and silver may be mainly used as the material of the second output extraction electrode 7a.
- the manufacturing method of the solar cell element 10 of this embodiment has an n-type semiconductor region on the first main surface 10a, and a p-type semiconductor on the second main surface 10b located on the opposite side to the first main surface 10a.
- the semiconductor substrate preparation process of the semiconductor substrate 1 having the first semiconductor layer 2 which is a p-type semiconductor region will be described.
- the semiconductor substrate 1 is formed by, for example, an existing casting method.
- an example in which a p-type polycrystalline silicon substrate is used as the semiconductor substrate 1 will be described.
- an ingot of polycrystalline silicon is produced by a casting method.
- the ingot is sliced to a thickness of 250 ⁇ m or less, for example.
- the surface of the semiconductor substrate 1 may be etched by a very small amount with an aqueous solution such as NaOH, KOH, hydrofluoric acid or hydrofluoric nitric acid.
- the uneven shape 1 a is formed on the first main surface 10 a of the semiconductor substrate 1.
- a wet etching method using an alkali solution such as NaOH or an acid solution such as hydrofluoric acid, or a dry etching method using RIE (Reactive Ion Etching) or the like can be used.
- a step of forming the second semiconductor layer 3 which is an n-type semiconductor region is performed on the first main surface 10a of the semiconductor substrate 1 having the concavo-convex shape 1a formed by the above steps. Specifically, the n-type second semiconductor layer 3 is formed in the surface layer on the first main surface 10a side in the semiconductor substrate 1 having the uneven shape 1a.
- Such a second semiconductor layer 3 may be formed by applying a thermal diffusion method in which phosphorus pentoxide (P 2 O 5 ) in a paste state is applied to the surface of the semiconductor substrate 1 and thermally diffused, or in a gas state. It is formed by a vapor phase thermal diffusion method using (POCl 3 ) as a diffusion source.
- the second semiconductor layer 3 is formed to have a depth of about 0.2 to 2 ⁇ m and a sheet resistance value of about 40 to 200 ⁇ / ⁇ .
- the semiconductor substrate 1 is heat-treated at a temperature of about 600 ° C. to 800 ° C.
- the second semiconductor layer 3 is formed on the first main surface side of the semiconductor substrate 1.
- the second semiconductor layer 3 formed on the second main surface 10b side is also formed on the second main surface 10b side. Only etch away. Thereby, the p-type conductivity type region is exposed on the second main surface 10b side.
- the second semiconductor layer 3 formed on the second main surface 10b side is removed by immersing only the second main surface 10b side of the semiconductor substrate 1 in a hydrofluoric acid solution. Thereafter, the phosphor glass adhering to the surface (first main surface 10a side) of the semiconductor substrate 1 when forming the second semiconductor layer 3 is removed by etching.
- the phosphorous glass remains on the first major surface 10a side, and the second semiconductor layer 3 formed on the second major surface 10b side is removed, so that the first glass on the first major surface 10a side is removed by phosphorous glass. 2 It is possible to reduce the semiconductor layer 3 from being removed or damaged. Further, the second semiconductor layer 3 formed on the side surface of the semiconductor substrate 1 may also be removed.
- a diffusion mask is formed in advance on the second main surface 10b side, the second semiconductor layer 3 is formed by vapor phase thermal diffusion or the like, and then the diffusion mask. May be removed. Even by such a process, it is possible to form a similar structure. In this case, since the second semiconductor layer 3 is not formed on the second main surface 10b side, the second main surface 10b side is formed. A step of removing the second semiconductor layer 3 is not necessary.
- the method for forming the second semiconductor layer 3 is not limited to the above method.
- a thin film technique is used to form an n-type hydrogenated amorphous silicon film or a crystalline silicon film including a microcrystalline silicon film. May be.
- an i-type silicon region may be formed between the first semiconductor layer 2 and the second semiconductor layer 3.
- the semiconductor substrate 1 of the polycrystalline silicon substrate in which the second semiconductor layer 3 which is the n-type semiconductor region is disposed on the first main surface 10a side and which includes the first semiconductor layer 2 which is the p-type semiconductor region. Can be prepared.
- a passivation layer forming step for forming a passivation layer on the first main surface 10a side and the second main surface 10b side of the semiconductor substrate 1 will be described.
- a first passivation layer 8 is formed on the second semiconductor layer 3, and a second passivation layer 9 is formed on the first semiconductor layer 2.
- the first passivation layer 8 and the second passivation layer 9 can be simultaneously formed on the entire periphery of the semiconductor substrate 1 by using, for example, an ALD (Atomic Layer Deposition) method. That is, the third passivation layer 11 made of, for example, an aluminum oxide layer is also formed on the side surface 10 c of the semiconductor substrate 1.
- the above-described semiconductor substrate 1 is placed in the deposition chamber, and the substrate temperature is heated to 100 to 300 ° C.
- an aluminum raw material such as trimethylaluminum is supplied onto the semiconductor substrate 1 together with a carrier gas such as argon gas or nitrogen gas for 0.5 seconds so that the aluminum raw material is adsorbed on the entire periphery of the semiconductor substrate 1 (step 1). ).
- a carrier gas such as argon gas or nitrogen gas for 0.5 seconds
- the aluminum raw material in the space is removed, and among the aluminum raw material adsorbed on the semiconductor substrate 1, components other than those adsorbed at the atomic layer level are removed ( Step 2).
- an oxidizing agent such as water or ozone gas is supplied into the film formation chamber for 4 seconds to remove CH 3 that is an alkyl group of trimethylaluminum that is an aluminum raw material, and to oxidize dangling bonds of aluminum, thereby producing a semiconductor.
- An atomic layer of aluminum oxide is formed on the substrate 1 (step 3).
- purging the film formation chamber with nitrogen gas for 1.5 seconds removes the oxidant in the space and removes the oxidant that did not contribute to the reaction other than aluminum oxide at the atomic layer level.
- the aluminum oxide layer which has predetermined thickness can be formed by repeating the said process 1 to the process 4.
- hydrogen is easily contained in the aluminum oxide layer by containing hydrogen in the oxidizing agent used in step 3, and the hydrogen passivation effect can be increased.
- the antireflection layer 5 is formed using, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition) method, vapor deposition method, sputtering method, or the like.
- PECVD Pulsma Enhanced Chemical Vapor Deposition
- vapor deposition method vapor deposition method
- sputtering method or the like.
- a mixed gas of silane (SiH 4 ) and ammonia (NH 3 ) is diluted with nitrogen (N 2 ), and glow discharge is performed.
- the antireflection layer 5 is formed by forming the plasma by decomposition and depositing it.
- the film formation chamber at this time can be set to about 500 ° C.
- first electrode 6 first output extraction electrode 6a, first collector electrode 6b
- second electrode 7 second output extraction electrode 7a, second collector electrode 7b
- the first electrode 6 is manufactured using a conductive paste containing, for example, a metal powder made of silver or the like, an organic vehicle, and glass frit. This conductive paste is applied to the first main surface 10a of the semiconductor substrate 1, and then fired at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes to form the first electrode 6.
- a screen printing method or the like can be used as the coating method. After coating, the solvent may be evaporated at a predetermined temperature and dried.
- the first electrode 6 includes a first output extraction electrode 6a and a first current collection electrode 6b. However, by using screen printing, the first extraction electrode 6a and the first current collection electrode 6b are one It can be formed in a process.
- An aluminum paste containing glass frit is applied directly onto the second passivation layer 9 in a predetermined region, and the applied paste component is applied to the second paste by a fire-through method in which a heat treatment at a maximum temperature of 600 to 800 ° C. is performed. Passing through the passivation layer 9, the third semiconductor layer 4 is formed on the second main surface 10b side of the semiconductor substrate 1, and an aluminum layer is formed thereon.
- This aluminum layer can be used as the second electrode 7, and as its formation region, for example, as shown in FIG. 4, the second current collecting electrode 7b and the second output of the second main surface 10b are used.
- the 2nd output extraction electrode 7a is produced using the electrically conductive paste containing the metal powder which consists of silver etc., an organic vehicle, and glass frit, for example.
- This conductive paste is applied to the second passivation layer 9 and then baked at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes to form the second output extraction electrode 7a.
- the coating method a screen printing method or the like can be used. After coating, the solvent may be evaporated at a predetermined temperature and dried.
- the second output extraction electrode 7a made of silver is connected to the second collector electrode 7b by contacting the aluminum layer.
- the second output extraction electrode 7a made of silver may be formed first, and then the second current collecting electrode 7b made of aluminum may be formed. Further, the second output extraction electrode 7 a does not need to be in direct contact with the semiconductor substrate 1, and the second passivation layer 9 may exist between the second output extraction electrode 7 a and the semiconductor substrate 1.
- the aluminum layer formed on the third semiconductor layer 4 may be removed, and the second extraction electrode 7a and the second current collecting electrode 7b may be formed using the same conductive paste. Further, the first electrode 6 and the second electrode 7 may be formed by applying the respective conductive pastes and firing them simultaneously.
- these electrodes can also be formed using thin film formation, such as vapor deposition and sputtering, and plating formation. is there.
- the hydrogen passivation effect can be increased by setting the maximum temperature heat treatment in each step to 800 ° C. or less. it can.
- the heat history by heat treatment at 300 to 500 ° C. may be 5 to 30 minutes.
- the solar cell element 10 can be manufactured as described above.
- the third semiconductor layer 4 may be formed before the second passivation layer 9 is formed.
- boron or a predetermined region in the second main surface 10b is formed before forming the second passivation layer 9. What is necessary is just to diffuse aluminum. Boron is diffused by heating at a temperature of about 800 to 1100 ° C. using a thermal diffusion method using boron tribromide (BBr 3 ) as a diffusion source.
- BBr 3 boron tribromide
- a p-type hydrogenated amorphous silicon film or a crystalline silicon film including a microcrystalline silicon film may be formed as the third semiconductor layer 4 using thin film technology.
- an i-type silicon region may be formed between the semiconductor substrate 1 and the third semiconductor layer 4.
- the semiconductor substrate 1 may be cleaned before forming the first passivation layer 8 and the second passivation layer 9.
- the cleaning process include hydrofluoric acid treatment, RCA cleaning (cleaning method developed by RCA, USA, high temperature / high concentration sulfuric acid / hydrogen peroxide solution, dilute hydrofluoric acid (room temperature), ammonia water / hydrogen peroxide. Cleaning method using water or hydrochloric acid / hydrogen peroxide solution) and hydrofluoric acid treatment after the cleaning, or SPM (Sulfuric Acid / Hydrogen Peroxide / Water Mixture) cleaning and cleaning method using hydrofluoric acid treatment after the cleaning Can be used.
- RCA cleaning cleaning method developed by RCA, USA, high temperature / high concentration sulfuric acid / hydrogen peroxide solution, dilute hydrofluoric acid (room temperature), ammonia water / hydrogen peroxide. Cleaning method using water or hydrochloric acid / hydrogen peroxide solution) and hydrofluoric acid treatment after the cleaning, or SPM (Sulfuric Acid / Hydro
- annealing is performed using a gas containing hydrogen, and the recombination speed in the semiconductor substrate 1 is further increased. It can be reduced.
- the solar cell module 20 includes one or more solar cell elements 10 of the present embodiment described above. Specifically, in the solar cell module 20, a plurality of the solar cell elements 10 are electrically connected.
- the solar cell module 20 is configured by connecting a plurality of solar cell elements 10 in series and in parallel, such as when the electric output of a single solar cell element 10 is small. By combining a plurality of solar cell modules 20, a practical electrical output can be taken out.
- the solar cell module 20 includes, for example, a transparent member 22 such as glass, a front filler 24 made of transparent EVA or ethylene- ⁇ -olefin copolymer, and a plurality of solar cells.
- Battery element 10 wiring member 21 connecting the plurality of solar battery elements 10, back side filler 25 made of EVA or ethylene- ⁇ -olefin copolymer, polyethylene terephthalate (PET) or polyvinyl fluoride resin ( It is made of a material such as PVF, and mainly includes a back surface protective material 23 having a single layer or a laminated structure.
- Adjacent solar cell elements 10 are electrically connected in series with each other by connecting the first electrode 6 of one solar cell element 10 and the second electrode 7 of the other solar cell element 10 by a wiring member 21. It is connected.
- the wiring member 21 for example, a member in which the entire surface of a copper foil having a thickness of about 0.1 to 0.2 mm and a width of about 2 mm is covered with a solder material is used.
- the solar cell module 20 may include a frame 28 made of aluminum or the like.
- the solar cell module 20 it is possible to realize a highly functional back surface reflection structure by using the white backside filler 25.
- EVA contains vinyl acetate as its component
- EVA tends to be hydrolyzed with time due to permeation of moisture or water at a high temperature to easily generate acetic acid.
- an acid acceptor made of magnesium hydroxide or calcium hydroxide may be added to the front side filler 24 or the back side filler 25.
- the generation of acetic acid can be reduced, the durability of the solar cell module can be improved, and acid damage to the first passivation layer 8 and the second passivation layer 9 can be further reduced. Can do. Therefore, long-term reliability of the solar cell module can be ensured.
- the solar cell module 20 since the solar cell module 20 according to the present embodiment includes the solar cell element 10 having the above-described passivation layer, the solar cell module 20 is excellent in output characteristics.
- the solar cell element 10 may be a back contact solar cell element having a metal wrap through structure in which the first output extraction electrode 6a is provided on the second main surface 10b side.
- the back contact solar cell element 30 having a metal wrap through structure includes a first semiconductor layer 2 and a second semiconductor provided on the first main surface 10 a side of the first semiconductor layer 2.
- a plurality of through holes 31 are provided in the semiconductor substrate 1 including the layer 3. Further, in the through hole 31, a first current collecting electrode 6b provided on the first main surface 10a side and a first output extraction electrode 6a provided on the second main surface 10b side are electrically connected.
- a connection electrode 6c is formed.
- the first connection electrode 4 c may be formed directly on the through hole 31, but the fourth passivation layer 32 made of aluminum oxide may be formed on the inner wall of the through hole 31. By providing the fourth passivation layer 32 also on the inner wall of the through hole 31, the passivation effect can be further enhanced.
- the fourth passivation layer 32 functions as an insulating layer, so that the occurrence of leakage is reduced. can do.
- the antireflection layer 5 may be formed on the fourth passivation layer 32.
- a negative fixed charge density such as an aluminum oxide layer on the fourth passivation layer 32. It is suitable to provide the antireflection layer 5 which is larger on the positive side than the layer having s.
- the first passivation layer 8, the second passivation layer 9, and the fourth passivation layer 32 are all formed of a layer having a negative fixed charge density such as the same aluminum oxide layer, thereby further enhancing the passivation effect. it can. It is more preferable to provide a layer having a negative fixed charge density such as an aluminum oxide layer around the entire periphery of the semiconductor substrate 1. That is, the third passivation layer 11 having a negative fixed charge density such as an aluminum oxide layer is formed not only on the first main surface 10a, the second main surface 10b, and the through hole 31 of the semiconductor substrate 1 but also on the side surface of the semiconductor substrate 1. It is good to provide.
- a concavo-convex structure 1a as shown in FIG. 3 was formed on the first main surface 10a side of each prepared polycrystalline silicon substrate by using the RIE method.
- phosphorus atoms were diffused to form an n-type second semiconductor layer 3 having a sheet resistance of about 90 ⁇ / ⁇ on the surface of the substrate 1.
- the second semiconductor layer 3 formed on the side surface and the second main surface 10b side was removed with a hydrofluoric acid solution, and thereafter the phosphorous glass remaining on the second semiconductor layer 3 was removed with a hydrofluoric acid solution.
- a first passivation layer 8, a second passivation layer 9, and a third passivation layer 11 made of an aluminum oxide layer are formed on the entire periphery of the semiconductor substrate 1 by the ALD method, and the first passivation layer 8 is formed on the first passivation layer 8.
- An antireflection layer 5 made of a silicon nitride layer was formed by plasma CVD.
- a silver paste is applied in a linear pattern as shown in FIG. 1 on the first main surface 10a side, and an aluminum paste is applied on the second main surface 10b side as a second current collecting electrode 7b as shown in FIG. 2 and a part of the second output extraction electrode 7a, and further silver paste was applied to the pattern of the second output extraction electrode 7a as shown in FIG. Thereafter, the patterns of these pastes were baked to form the third semiconductor layer 4, the first electrode 6, and the second electrode 7, as shown in FIGS. The first electrode 6 and the second collector electrode 7b were in contact with the semiconductor substrate 1 by the fire-through method, respectively.
- Example 1 the average thickness of the first passivation layer 8, the second passivation layer 9, and the third passivation layer 11 is 35 nm, and the average thickness of the antireflection layer 5 is 45 nm. 2, the average thickness of the first passivation layer 8, the second passivation layer 9, and the third passivation layer 11 was 45 nm, and the average thickness of the antireflection layer 5 was 35 nm.
- a solar cell element (Comparative Example 1) in which only a silicon nitride layer having an average thickness of 80 nm is formed on the first main surface 10a side.
- a solar cell element (Comparative Example 2) in which only an aluminum oxide layer having an average thickness of 80 nm is formed on the first main surface 10a side, and a silicon nitride layer having an average thickness of 45 nm are formed on the first main surface 10a side.
- said average thickness was calculated
- the solar cell element output characteristics (short-circuit current Isc, open-circuit voltage Voc, fill factor (FF) and photoelectric conversion efficiency) were measured and evaluated. Table 1 shows the measurement results of these characteristics. In addition, the measurement of these characteristics was measured on the conditions of irradiation of AM (Air Mass) 1.5 and 100 mW / cm ⁇ 2 > based on JISC8913.
- Example 1 had a higher short circuit current Isc and higher photoelectric conversion efficiency than Example 2.
Abstract
A solar cell element (10) is provided with: a semiconductor substrate (1) having an n-type semiconductor region provided on a first principal surface (10a) and a p-type semiconductor region provided on a second principal surface (10b) which is located opposite the first principal surface (10a); a first passivation layer (8) which is arranged on said n-type semiconductor region and has a negative fixed charge density; and an antireflection layer (5) which is arranged on the first passivation layer (8) and has a fixed charge density that is more positive than that of the first passivation layer (8).
Description
本発明は、太陽電池素子、太陽電池素子の製造方法および太陽電池素子を備えている太陽電池モジュールに関する。
The present invention relates to a solar cell element, a method for manufacturing a solar cell element, and a solar cell module including the solar cell element.
シリコン基板を備えた太陽電池素子において、少数キャリアの再結合を低減するためにパッシベーション膜がシリコン基板の表面に設けられる。このパッシベーション膜として、酸化シリコンもしくは酸化アルミニウム等からなる酸化膜、または窒化シリコン膜等からなる窒化膜を用いることが研究されている（例えば特開２００９－１６４５４４号公報を参照）。
In a solar cell element provided with a silicon substrate, a passivation film is provided on the surface of the silicon substrate in order to reduce minority carrier recombination. As the passivation film, use of an oxide film made of silicon oxide, aluminum oxide, or the like, or a nitride film made of a silicon nitride film or the like has been studied (see, for example, JP-A-2009-164544).
しかし、昨今の厳しい使用条件下での太陽電池素子の特性向上のニーズの高まりに伴い、上記構成の太陽電池素子では、発電効率に寄与するだけの改善が不十分となる場合があった。そのため、キャリアの再結合を低減して出力特性をより一層高めた太陽電池素子およびその製造方法ならびに太陽電池モジュールが望まれている。
However, with the recent increase in the needs for improving the characteristics of solar cell elements under severe use conditions, the solar cell elements having the above-described configuration may not be improved enough to contribute to power generation efficiency. Therefore, a solar cell element, a manufacturing method thereof, and a solar cell module in which output characteristics are further improved by reducing carrier recombination are desired.
上記課題を解決するため、本発明の一形態に係る太陽電池素子は、第１主面にｎ型半導体領域を有しており、前記第１主面とは反対側に位置する第２主面にｐ型半導体領域を有している半導体基板と、前記ｎ型半導体領域の上に配置されており、負の固定電荷密度を有している第１パッシベーション層と、該第１パッシベーション層の上に配置されている、該第１パッシベーション層よりも固定電荷密度が正側に大きい反射防止層とを備えている。
In order to solve the above problems, a solar cell element according to an embodiment of the present invention has an n-type semiconductor region on a first main surface, and a second main surface located on the side opposite to the first main surface. A p-type semiconductor region, a first passivation layer disposed on the n-type semiconductor region and having a negative fixed charge density, and on the first passivation layer And an antireflection layer having a fixed charge density larger than that of the first passivation layer on the positive side.
また、本発明の一形態に係る太陽電池素子は、第１主面にｎ型半導体領域を有しており、前記第１主面とは反対側に位置する第２主面にｐ型半導体領域を有しているシリコンからなる半導体基板と、前記ｎ型半導体領域の上に配置されており、酸化アルミニウム、酸化ハフニウムおよび酸化ジルコニウムから選択される１種以上からなる第１パッシベーション層と、該第１パッシベーション層の上に配置されている、酸化シリコンまたは窒化シリコンからなる反射防止層とを備えているものでもよい。
In addition, a solar cell element according to one embodiment of the present invention has an n-type semiconductor region on a first main surface, and a p-type semiconductor region on a second main surface located on the opposite side to the first main surface. A semiconductor substrate made of silicon and having a first passivation layer which is disposed on the n-type semiconductor region and is made of at least one selected from aluminum oxide, hafnium oxide and zirconium oxide, and It may be provided with an antireflection layer made of silicon oxide or silicon nitride disposed on one passivation layer.
また、本発明の一形態に係る太陽電池素子の製造方法は、第１主面にｎ型半導体領域を有しており、前記第１主面とは反対側に位置する第２主面にｐ型半導体領域を有している半導体基板を準備する半導体基板準備工程と、前記ｎ型半導体領域の上に、原子層蒸着法によって負の固定電荷密度を有するパッシベーション層を形成するパッシベーション層形成工程と、前記パッシベーション層の上に、プラズマＣＶＤ法によって前記パッシベーション層よりも固定電荷密度が正側に大きい反射防止層を形成する反射防止層形成工程とを含む。
In the method for manufacturing a solar cell element according to one aspect of the present invention, the first main surface has an n-type semiconductor region, and the second main surface located on the side opposite to the first main surface is p. A semiconductor substrate preparation step of preparing a semiconductor substrate having a type semiconductor region, and a passivation layer formation step of forming a passivation layer having a negative fixed charge density on the n-type semiconductor region by an atomic layer deposition method, And an antireflection layer forming step of forming an antireflection layer having a fixed charge density larger than that of the passivation layer on the positive side by a plasma CVD method on the passivation layer.
また、本発明の一形態に係る太陽電池モジュールは、上記構成の太陽電池素子を備えている。
Further, a solar cell module according to one embodiment of the present invention includes the solar cell element having the above-described configuration.
上記の太陽電池素子、太陽電池素子の製造方法および太陽電池モジュールによれば、開放電圧が高く、出力特性に優れた太陽電池素子および太陽電池モジュールを提供できる。
According to the above solar cell element, solar cell element manufacturing method, and solar cell module, it is possible to provide a solar cell element and a solar cell module having a high open-circuit voltage and excellent output characteristics.
以下、本発明の一形態に係る太陽電池素子およびその製造方法、ならびに太陽電池モジュールについて図面を参照しつつ詳細に説明する。なお、図面は模式的に示したものであるので、図面における各構成の寸法比および位置関係等は適宜変更しうる。
Hereinafter, a solar cell element, a manufacturing method thereof, and a solar cell module according to an embodiment of the present invention will be described in detail with reference to the drawings. In addition, since drawing is shown typically, the dimension ratio of each structure in a drawing, a positional relationship, etc. can be changed suitably.
＜太陽電池素子の基本構成＞
図１乃至図３に本実施形態に係る太陽電池素子１０を示す。太陽電池素子１０は、第１主面１０ａにｎ型半導体領域を有しており、第１主面１０ａとは反対側に位置する第２主面１０ｂにｐ型半導体領域を有している半導体基板１と、ｎ型半導体領域の上に配置されており、負の固定電荷密度を有している第１パッシベーション層８と、この第１パッシベーション層８の上に配置されている、第１パッシベーション層８よりも固定電荷密度が正側に大きい反射防止層５とを備えていることを基本構成とする。 <Basic configuration of solar cell element>
1 to 3 show asolar cell element 10 according to the present embodiment. The solar cell element 10 has an n-type semiconductor region on the first main surface 10a, and a semiconductor having a p-type semiconductor region on the second main surface 10b located on the opposite side of the first main surface 10a. A first passivation layer 8 disposed on the substrate 1 and the n-type semiconductor region and having a negative fixed charge density, and a first passivation layer disposed on the first passivation layer 8 The basic configuration is that the antireflection layer 5 having a fixed charge density larger on the positive side than the layer 8 is provided.
図１乃至図３に本実施形態に係る太陽電池素子１０を示す。太陽電池素子１０は、第１主面１０ａにｎ型半導体領域を有しており、第１主面１０ａとは反対側に位置する第２主面１０ｂにｐ型半導体領域を有している半導体基板１と、ｎ型半導体領域の上に配置されており、負の固定電荷密度を有している第１パッシベーション層８と、この第１パッシベーション層８の上に配置されている、第１パッシベーション層８よりも固定電荷密度が正側に大きい反射防止層５とを備えていることを基本構成とする。 <Basic configuration of solar cell element>
1 to 3 show a
また、太陽電池素子１０は、第１主面１０ａにｎ型半導体領域を有しており、第１主面１０ａとは反対側に位置する第２主面１０ｂにｐ型半導体領域を有しているシリコンからなる半導体基板１と、前記ｎ型半導体領域の上に配置されており、酸化アルミニウム、酸化ハフニウムおよび酸化ジルコニウムから選択される１種以上からなる第１パッシベーション層８と、第１パッシベーション層８の上に配置されている、酸化シリコンまたは窒化シリコンからなる反射防止層５とを備えているものとしてもよい。
Further, the solar cell element 10 has an n-type semiconductor region on the first main surface 10a, and has a p-type semiconductor region on the second main surface 10b located on the opposite side to the first main surface 10a. A semiconductor substrate 1 made of silicon, a first passivation layer 8 disposed on the n-type semiconductor region and made of at least one selected from aluminum oxide, hafnium oxide and zirconium oxide, and a first passivation layer And an antireflection layer 5 made of silicon oxide or silicon nitride.
また、図１乃至図３に示すように、太陽電池素子１０は、光が入射する受光面（図３における上面であり、以下では第１主面という）１０ａと、この第１主面１０ａの反対側に位置する面（裏面）に相当する非受光面（図３における下面であり、以下では第２主面という）１０ｂと、側面１０ｃとを有する。また、太陽電池素子１０は、例えば板状の多結晶シリコン基板の半導体基板１を備えている。
Further, as shown in FIGS. 1 to 3, the solar cell element 10 includes a light receiving surface (a top surface in FIG. 3 and hereinafter referred to as a first main surface) 10a on which light is incident, and the first main surface 10a. It has a non-light-receiving surface (a lower surface in FIG. 3, hereinafter referred to as a second main surface) 10b corresponding to a surface (back surface) located on the opposite side, and a side surface 10c. Moreover, the solar cell element 10 includes a semiconductor substrate 1 which is a plate-like polycrystalline silicon substrate, for example.
半導体基板１は、図３に示すように、例えば、一導電型の半導体領域（ｐ型半導体領域）である第１半導体層２と、この第１半導体層２における第１主面１０ａ側に設けられた逆導電型の半導体領域（ｎ型半導体領域）である第２半導体層３とを有する。また、太陽電池素子１０は、第２半導体層３の上に（具体的には、第２半導体層３の第１主面１０ａ側に）配置された、酸化アルミニウム等からなる第１パッシベーション層８と、第１パッシベーション層８の上に例えば窒化シリコンからなる反射防止層５とを備えている。さらに、太陽電池素子１０は、第１半導体層２の上に（具体的には、第１半導体層２の第２主面１０ｂ側に）配置された、酸化アルミニウム等からなる第２パッシベーション層９を備えている。
As shown in FIG. 3, the semiconductor substrate 1 is provided, for example, on the first semiconductor layer 2 that is a one-conductivity type semiconductor region (p-type semiconductor region) and on the first main surface 10 a side in the first semiconductor layer 2. And a second semiconductor layer 3 which is a reverse conductivity type semiconductor region (n-type semiconductor region). Further, the solar cell element 10 is disposed on the second semiconductor layer 3 (specifically, on the first main surface 10a side of the second semiconductor layer 3), and the first passivation layer 8 made of aluminum oxide or the like. And an antireflection layer 5 made of silicon nitride, for example, on the first passivation layer 8. Further, the solar cell element 10 is disposed on the first semiconductor layer 2 (specifically, on the second main surface 10b side of the first semiconductor layer 2), and the second passivation layer 9 made of aluminum oxide or the like. It has.
具体的には図３に示すように、太陽電池素子１０は、半導体基板１（第１半導体層２と第２半導体層３）、第３半導体層４、反射防止層５、第１電極６、第２電極７、第１パッシベーション層８および第２パッシベーション層９を備えている。
Specifically, as shown in FIG. 3, the solar cell element 10 includes a semiconductor substrate 1 (first semiconductor layer 2 and second semiconductor layer 3), a third semiconductor layer 4, an antireflection layer 5, a first electrode 6, A second electrode 7, a first passivation layer 8 and a second passivation layer 9 are provided.
上述したように、半導体基板１は多結晶シリコン基板であり、第１半導体層２と、該第１半導体層２の第１主面１０ａ側に設けられた第２半導体層３とを備えている。
As described above, the semiconductor substrate 1 is a polycrystalline silicon substrate, and includes the first semiconductor layer 2 and the second semiconductor layer 3 provided on the first main surface 10a side of the first semiconductor layer 2. .
第１半導体層２としては、上述したように、ｐ型を呈する板状の半導体を用いることができる。第１半導体層２を構成する半導体としては、多結晶シリコン基板を用いることができる。第１半導体層２の平均厚みは、例えば、２５０μｍ以下、さらには１５０μｍ以下とすることができる。第１半導体層２の形状は、特に限定されるものではないが、製法上の観点から平面視で四角形状としてもよい。多結晶シリコン基板からなる第１半導体層２がｐ型を呈するようにする場合であれば、ドーパント元素としては、例えば、ボロンあるいはガリウムを用いることができる。
As the first semiconductor layer 2, as described above, a plate-like semiconductor exhibiting a p-type can be used. As the semiconductor constituting the first semiconductor layer 2, a polycrystalline silicon substrate can be used. The average thickness of the first semiconductor layer 2 can be, for example, 250 μm or less, and further 150 μm or less. Although the shape of the 1st semiconductor layer 2 is not specifically limited, From a viewpoint on a manufacturing method, it is good also as a square shape by planar view. If the first semiconductor layer 2 made of a polycrystalline silicon substrate is p-type, for example, boron or gallium can be used as the dopant element.
第２半導体層３は、これと第１半導体層２とでｐｎ接合を形成する半導体層である。第２半導体層３は、第１半導体層２に対して逆の導電型、すなわち、ｎ型を呈する層であり、第１半導体層２における第１主面１０ａ側に設けられている。第１半導体層２がｐ型の導電型を呈するシリコン基板において、例えば、第２半導体層３はシリコン基板の第１主面１０ａ側にリン等の不純物を拡散させることによって形成できる。
The second semiconductor layer 3 is a semiconductor layer that forms a pn junction with this and the first semiconductor layer 2. The second semiconductor layer 3 is a layer having a conductivity type opposite to that of the first semiconductor layer 2, that is, an n-type, and is provided on the first main surface 10 a side in the first semiconductor layer 2. In the silicon substrate in which the first semiconductor layer 2 exhibits p-type conductivity, for example, the second semiconductor layer 3 can be formed by diffusing impurities such as phosphorus on the first main surface 10a side of the silicon substrate.
図３に示すように、半導体基板１における第１主面１０ａ側には、例えばピラミッド状の凹凸形状１ａが設けられている。凹凸形状１ａの凸部の高さは０．１～１０μｍ程度、凸部の幅は０．１～２０μｍ程度である。凹凸形状１ａの形状はピラミッド状に限定されるものではなく、例えば、凹部が略球面状である凹凸形状であってもよい。
As shown in FIG. 3, for example, a pyramidal uneven shape 1 a is provided on the first main surface 10 a side of the semiconductor substrate 1. The height of the convex portion of the concavo-convex shape 1a is about 0.1 to 10 μm, and the width of the convex portion is about 0.1 to 20 μm. The shape of the concavo-convex shape 1a is not limited to the pyramid shape, and may be a concavo-convex shape in which the concave portion is substantially spherical.
なお、ここでいう凸部の高さとは、例えば図３の断面図において、凹部の底面を通る直線を基準線とし、該基準線に垂直な方向における、該基準線から凸部の頂面までの距離のことである。凸部の幅とは、前記基準線に平行な方向における、隣接する凸部の頂面間の距離のことである。
Note that the height of the convex portion here refers to, for example, a straight line passing through the bottom surface of the concave portion in the cross-sectional view of FIG. 3, and from the reference line to the top surface of the convex portion in a direction perpendicular to the reference line. Is the distance. The width of the convex portion is a distance between the top surfaces of adjacent convex portions in a direction parallel to the reference line.
第１パッシベーション層８は、半導体基板１の第１主面１０ａ側に形成される。第１パッシベーション層８は酸化アルミニウム、酸化ハフニウムおよび酸化ジルコニウムから選択される１種以上を含む層からなる。例えば、第１パッシベーション層８は酸化アルミニウム層、酸化ハフニウム層または酸化ジルコニウム層とすることができる。このような構成によって、開放電圧が高く、出力特性に優れた太陽電池素子を得ることができる。これは、表面パッシベーション効果によって表面再結合を低減できたためと推察される。但し、酸化アルミニウム層、酸化ハフニウム層および酸化ジルコニウム層は、いずれも負の固定電荷を有することから、またｎ型の第２半導体層３では、第１パッシベーション層との界面において少数キャリア（正孔）が上昇する方向に界面付近のバンドが曲がる。このことから、表面再結合が増加する問題を有する。
The first passivation layer 8 is formed on the first main surface 10a side of the semiconductor substrate 1. The first passivation layer 8 is composed of a layer containing at least one selected from aluminum oxide, hafnium oxide, and zirconium oxide. For example, the first passivation layer 8 can be an aluminum oxide layer, a hafnium oxide layer, or a zirconium oxide layer. With such a configuration, a solar cell element having a high open-circuit voltage and excellent output characteristics can be obtained. This is presumably because the surface recombination could be reduced by the surface passivation effect. However, since the aluminum oxide layer, the hafnium oxide layer, and the zirconium oxide layer all have negative fixed charges, the n-type second semiconductor layer 3 has minority carriers (holes) at the interface with the first passivation layer. ) The band near the interface bends in the direction of rising. This has the problem of increased surface recombination.
そこで、例えば酸化アルミニウム層、酸化ハフニウム層または酸化ジルコニウム層からなる第１パッシベーション層８の上に、この層の負の固定電荷密度よりも正側に大きい反射防止層５を形成する。固定電荷密度が正側に大きい反射防止層５とは、正の固定電荷密度をもつ反射防止層５または負の固定電荷密度が第１パッシベーション層８よりも小さい反射防止層５である。このような反射防止層５を形成することによって、開放電圧が高く、出力特性に優れた太陽電池素子を得ることができる。理由は定かではないが、第１パッシベーション層８の上に固定電荷密度が正側に大きい反射防止層５を設けることによって、上記界面付近のバンドが曲がる影響を低減できるためと推察される。反射防止層５としては、正の固定電荷密度を有する反射防止層５を用いることがより好適である。第１パッシベーション層８の平均厚みは、例えば、３０～１０００Å程度とすることができる。
Therefore, on the first passivation layer 8 made of, for example, an aluminum oxide layer, a hafnium oxide layer, or a zirconium oxide layer, the antireflection layer 5 that is larger on the positive side than the negative fixed charge density of this layer is formed. The antireflection layer 5 having a large fixed charge density on the positive side is the antireflection layer 5 having a positive fixed charge density or the antireflection layer 5 having a negative fixed charge density smaller than that of the first passivation layer 8. By forming such an antireflection layer 5, a solar cell element having a high open-circuit voltage and excellent output characteristics can be obtained. Although the reason is not clear, it is presumed that by providing the antireflection layer 5 having a large fixed charge density on the positive side on the first passivation layer 8, the influence of bending of the band near the interface can be reduced. As the antireflection layer 5, it is more preferable to use the antireflection layer 5 having a positive fixed charge density. The average thickness of the first passivation layer 8 can be about 30 to 1000 mm, for example.
また、反射防止層５は、例えば窒化シリコン層または酸化シリコン層などから形成される。反射防止層５の厚みは、材料の種類によって適宜選択可能であり、適当な入射光に対して無反射条件を実現できる厚みを採用すればよい。例えば、反射防止層５の屈折率は１．８～２．３程度、平均厚みは２００～１２００Å程度とすることができる。
The antireflection layer 5 is formed of, for example, a silicon nitride layer or a silicon oxide layer. The thickness of the antireflection layer 5 can be appropriately selected depending on the type of material, and may be a thickness that can realize non-reflection conditions with respect to appropriate incident light. For example, the antireflective layer 5 can have a refractive index of about 1.8 to 2.3 and an average thickness of about 200 to 1200 mm.
なお、酸化アルミニウム層の固定電荷密度は－１×１０１１～－１×１０１３ｃｍ－２程度、酸化ハフニウムおよび酸化ジルコニウムの固定電荷密度は－１×１０１１～－５×１０１２ｃｍ－２程、窒化シリコン層の固定電荷密度は＋１×１０１２ｃｍ－２程度、酸化シリコン層の固定電荷密度は＋６×１０１０ｃｍ－２程度である。また、パッシベーション層の固定電荷密度は例えば容量－電圧測定法（Ｃ－Ｖ測定法）によって算出することができる。例えば、半導体基板の表面に配置されたパッシベーション層の上にアルミニウム電極を配置して、半導体基板の裏面に配置されたアルミニウム電極を配置して、アルミニウム電極間にある一定の範囲で変化させて印加した各電圧における各容量の測定によって求めたＣ－Ｖ特性カーブ等から算出することができる。
The fixed charge density of the aluminum oxide layer is about −1 × 10 11 to −1 × 10 13 cm −2 , and the fixed charge densities of hafnium oxide and zirconium oxide are −1 × 10 11 to −5 × 10 12 cm −2. The fixed charge density of the silicon nitride layer is about + 1 × 10 12 cm −2 , and the fixed charge density of the silicon oxide layer is about + 6 × 10 10 cm −2 . The fixed charge density of the passivation layer can be calculated by, for example, a capacitance-voltage measurement method (CV measurement method). For example, an aluminum electrode is disposed on the passivation layer disposed on the surface of the semiconductor substrate, and an aluminum electrode disposed on the back surface of the semiconductor substrate is disposed and applied by changing within a certain range between the aluminum electrodes. It can be calculated from a CV characteristic curve obtained by measuring each capacity at each voltage.
第２パッシベーション層９は、半導体基板１の第２主面１０ｂ側に形成される。第２パッシベーション層９は酸化アルミニウム、酸化ハフニウムおよび酸化ジルコニウムから選択される１種以上を含む層からなる。上記構成によれば、開放電圧が高く、出力特性に優れた太陽電池素子を得ることができる。これは、表面パッシベーション効果により表面再結合を低減できたためと推察される。また、酸化アルミニウム層、酸化ハフニウム層および酸化ジルコニウム層は、いずれも負の固定電荷密度を有することから、ｐ型の半導体基板１の上に第２パッシベーション層９を設ける場合は、半導体基板１（第１半導体層２）と第２パッシベーション層９との界面において、少数キャリア（電子）が減少する方向に界面付近のバンドが曲がることから、さらに表面再結合を低減できる。第２パッシベーション層９の平均厚みは、例えば、３０～１０００Å程度とすることができる。
The second passivation layer 9 is formed on the second main surface 10b side of the semiconductor substrate 1. The second passivation layer 9 is composed of a layer containing one or more selected from aluminum oxide, hafnium oxide and zirconium oxide. According to the said structure, the open circuit voltage is high and the solar cell element excellent in output characteristics can be obtained. This is presumably because surface recombination could be reduced by the surface passivation effect. Further, since the aluminum oxide layer, the hafnium oxide layer, and the zirconium oxide layer all have a negative fixed charge density, when the second passivation layer 9 is provided on the p-type semiconductor substrate 1, the semiconductor substrate 1 ( At the interface between the first semiconductor layer 2) and the second passivation layer 9, the band near the interface is bent in the direction in which minority carriers (electrons) decrease, so that surface recombination can be further reduced. The average thickness of the second passivation layer 9 can be about 30 to 1000 mm, for example.
また、第１パッシベーション層８および第２パッシベーション層９は、例えば、主に非晶質の酸化アルミニウム層を用いることによって、酸化アルミニウム中に含まれる水素が多く、半導体基板中に水素が拡散しやすくなる。なお、上記の「主に非晶質の酸化アルミニウム層」とは、酸化アルミニウム層における結晶化率が５０％未満であることをいう。
The first passivation layer 8 and the second passivation layer 9 are mainly made of an amorphous aluminum oxide layer, for example, so that a large amount of hydrogen is contained in the aluminum oxide, and hydrogen is easily diffused into the semiconductor substrate. Become. The above “mainly amorphous aluminum oxide layer” means that the crystallization rate in the aluminum oxide layer is less than 50%.
そして、酸化アルミニウム層の存在によってダングリングボンドが水素で終端されて、さらに表面再結合を低減できる。また、結晶質の酸化アルミニウム層は成長界面に対して垂直に成長する傾向がある。そのため、多結晶シリコン基板のような粒界および結晶方位の異なる結晶粒が存在する基板を用いる場合には、結晶質の酸化アルミニウム層の成長界面が基板表面における結晶粒の粒界および結晶方位の影響を受け易く、酸化アルミニウム層の成長界面がランダムな方向を有し易い傾向にある。
The dangling bonds are terminated with hydrogen due to the presence of the aluminum oxide layer, and surface recombination can be further reduced. Also, the crystalline aluminum oxide layer tends to grow perpendicular to the growth interface. Therefore, when using a substrate having a grain boundary and a crystal grain having a different crystal orientation such as a polycrystalline silicon substrate, the growth interface of the crystalline aluminum oxide layer has a grain boundary and crystal orientation of the substrate surface. It is easily affected and the growth interface of the aluminum oxide layer tends to have a random direction.
そこで、半導体基板１として多結晶シリコン基板を用いる場合においては、主に非晶質の酸化アルミニウム層を用いるとよい。多結晶シリコン基板の表面における結晶粒の粒界および結晶方位の影響を受けて、結晶質の酸化アルミニウム層がランダムな方向に成長して、成長を始めた結晶粒同士が干渉して、この干渉面で欠陥が生じることを低減できる。その結果、第１パッシベーション層８および第２パッシベーション層９は優れたパッシベンション効果を有することができる。
Therefore, when a polycrystalline silicon substrate is used as the semiconductor substrate 1, an amorphous aluminum oxide layer is mainly used. Under the influence of crystal grain boundaries and crystal orientations on the surface of the polycrystalline silicon substrate, the crystalline aluminum oxide layer grows in random directions, and the crystal grains that have started to interfere with each other cause this interference. It is possible to reduce the occurrence of defects on the surface. As a result, the first passivation layer 8 and the second passivation layer 9 can have an excellent passivation effect.
また、第１パッシベーション層８の平均厚みを反射防止膜層５の平均厚みよりも薄く設けることによって、反射による光のロスを低減することができて、出力特性の低下を低減することができる。なお、上記の平均厚みは、例えばエリプソメータ（SENTECH社製SE-400adv）を使用して、５箇所を測定した結果を平均すればよい。
Also, by providing the average thickness of the first passivation layer 8 thinner than the average thickness of the antireflection film layer 5, it is possible to reduce the loss of light due to reflection, and to reduce the deterioration of output characteristics. In addition, what is necessary is just to average the result of having measured 5 places, for example using said ellipsometer (SE-400adv by SENTECH) for said average thickness.
また、第１パッシベーション層８および第２パッシベーション層９は、同一の酸化アルミニウム層等の負の固定電荷密度を有している層から構成されることによって、さらに優れたパッシベーション効果を有することができる。また、半導体基板１の全周囲に酸化アルミニウム層を設けることによって、リーク電流の発生をより低減することができて、作製も容易に行なえる。
Further, the first passivation layer 8 and the second passivation layer 9 can have a further excellent passivation effect by being composed of layers having a negative fixed charge density, such as the same aluminum oxide layer. . In addition, by providing an aluminum oxide layer around the entire periphery of the semiconductor substrate 1, the generation of leakage current can be further reduced and the fabrication can be performed easily.
このように、半導体基板１の第１主面１０ａおよび第２主面１０ｂだけではなく、半導体基板１の側面１０ｃにおいても酸化アルミニウム層等の負の固定電荷密度を有している第３パッシベーション層１１を設けるとよい。
Thus, not only the first main surface 10a and the second main surface 10b of the semiconductor substrate 1, but also the side surface 10c of the semiconductor substrate 1 has a third passivation layer having a negative fixed charge density such as an aluminum oxide layer. 11 may be provided.
また、反射防止層５は半導体基板１の側面に設けられてもよく、このとき反射防止層５は絶縁材料を用いて形成されることが好ましい。半導体基板１の側面１０ｃに設けられた第３パッシベーション層１１にピンホール等の微小な開口部が存在した場合には、反射防止層５が開口部を埋めて第１半導体層２と接触することから、リーク電流の発生源となる可能性があるため、反射防止層５が絶縁材料であることによってリーク電流の発生を低減することができる。
Further, the antireflection layer 5 may be provided on the side surface of the semiconductor substrate 1, and at this time, the antireflection layer 5 is preferably formed using an insulating material. When a minute opening such as a pinhole is present in the third passivation layer 11 provided on the side surface 10c of the semiconductor substrate 1, the antireflection layer 5 fills the opening and comes into contact with the first semiconductor layer 2. Therefore, since the antireflection layer 5 is made of an insulating material, the generation of leakage current can be reduced.
第３半導体層４は、半導体基板１の第２主面１０ｂ側に配置されており、第１半導体層２と同一の導電型、すなわちｐ型を呈している。そして、第３半導体層４が含有するドーパントの濃度は、第１半導体層２が含有するドーパントの濃度よりも高い。すなわち、第３半導体層４中には、第１半導体層２において一導電型を呈するためにドープされるドーパント元素の濃度よりも高い濃度でドーパント元素が存在する。このような第３半導体層４は、半導体基板１における第２主面１０ｂの近傍でキャリアの再結合による変換効率の低下を低減させる役割を有しており、半導体基板１における第２主面１０ｂ側で内部電界を形成するものである。第３半導体層４は、例えば、半導体基板１の第２主面１０ｂ側にボロンまたはアルミニウムなどのドーパント元素を拡散させることによって形成できる。このとき、第３半導体層４が含有するドーパント元素の濃度は１×１０１８～５×１０２１ａｔｏｍｓ／ｃｍ３程度とすることができる。第３半導体層４は後述する第２電極７と半導体基板１との接触部分に形成されるのが好適である。
The third semiconductor layer 4 is disposed on the second main surface 10b side of the semiconductor substrate 1 and has the same conductivity type as the first semiconductor layer 2, that is, p-type. The concentration of the dopant contained in the third semiconductor layer 4 is higher than the concentration of the dopant contained in the first semiconductor layer 2. That is, the dopant element is present in the third semiconductor layer 4 at a concentration higher than the concentration of the dopant element doped to exhibit one conductivity type in the first semiconductor layer 2. The third semiconductor layer 4 has a role of reducing a decrease in conversion efficiency due to carrier recombination in the vicinity of the second main surface 10b of the semiconductor substrate 1, and the second main surface 10b of the semiconductor substrate 1 is used. An internal electric field is formed on the side. The third semiconductor layer 4 can be formed, for example, by diffusing a dopant element such as boron or aluminum on the second main surface 10b side of the semiconductor substrate 1. At this time, the concentration of the dopant element contained in the third semiconductor layer 4 can be about 1 × 10 18 to 5 × 10 21 atoms / cm 3 . The third semiconductor layer 4 is preferably formed at a contact portion between a second electrode 7 and a semiconductor substrate 1 described later.
第１電極６は、半導体基板１の第１主面１０ａ側に設けられた電極であり、図１に示すように、第１出力取出電極６ａと、複数の線状の第１集電電極６ｂとを有する。第１出力取出電極６ａの少なくとも一部は、第１集電電極６ｂと交差して電気的に接続されている。一方、第１集電電極６ｂは線状であり、短手方向において、例えば５０～２００μｍ程度の幅を有している。第１出力取出電極６ａは、短手方向において、例えば１．３～２．５ｍｍ程度の幅を有している。そして、第１集電電極６ｂの短手方向の幅は、第１出力取出電極６ａの短手方向の幅よりも小さい。また、第１集電電極６ｂは、互いに１．５～３ｍｍ程度の間隔を空けて複数設けられている。この第１電極６の厚みは１０～４０μｍ程度である。このような第１電極６は、例えば、銀を主成分とする導電性ペーストをスクリーン印刷等によって所望の形状に塗布した後、焼成することによって形成することができる。
The first electrode 6 is an electrode provided on the first main surface 10a side of the semiconductor substrate 1, and as shown in FIG. 1, the first output extraction electrode 6a and a plurality of linear first current collecting electrodes 6b. And have. At least a part of the first output extraction electrode 6a intersects the first current collecting electrode 6b and is electrically connected. On the other hand, the first current collecting electrode 6b is linear and has a width of, for example, about 50 to 200 μm in the lateral direction. The first output extraction electrode 6a has a width of, for example, about 1.3 to 2.5 mm in the short direction. And the width | variety of the transversal direction of the 1st current collection electrode 6b is smaller than the width | variety of the transversal direction of the 1st output extraction electrode 6a. A plurality of first current collecting electrodes 6b are provided with an interval of about 1.5 to 3 mm. The thickness of the first electrode 6 is about 10 to 40 μm. Such a first electrode 6 can be formed by, for example, applying a conductive paste containing silver as a main component into a desired shape by screen printing or the like and then baking it.
第２電極７は、半導体基板１の第２主面１０ｂ側に設けられた電極であり、例えば、第１電極と同様の形態、つまり、図２に示すように、第２出力取出電極７ａと、複数の線状の第２集電電極７ｂとを有する。第２出力取出電極７ａの少なくとも一部は、第２集電電極７ｂと交差して電気的に接続されている。一方、第２集電電極７ｂは線状であり、短手方向において、例えば５０～３００μｍ程度の幅を有している。第２出力取出電極７ａは、短手方向において、例えば１．３～３ｍｍ程度の幅を有している。そして、第２集電電極７ｂの短手方向の幅は、第２出力取出電極７ａの短手方向の幅よりも小さい。また、第２集電電極７ｂは、互いに１．５～３ｍｍ程度の間隔を空けて複数設けられている。この第２電極７の厚みは１０～４０μｍ程度である。
The second electrode 7 is an electrode provided on the second main surface 10b side of the semiconductor substrate 1, and has, for example, the same form as the first electrode, that is, as shown in FIG. 2, the second output extraction electrode 7a and And a plurality of linear second collector electrodes 7b. At least a part of the second output extraction electrode 7a intersects the second collector electrode 7b and is electrically connected. On the other hand, the second current collecting electrode 7b is linear and has a width of, for example, about 50 to 300 μm in the short direction. The second output extraction electrode 7a has a width of, for example, about 1.3 to 3 mm in the short direction. The width of the second collector electrode 7b in the short direction is smaller than the width of the second output extraction electrode 7a in the short direction. Further, a plurality of second current collecting electrodes 7b are provided with an interval of about 1.5 to 3 mm. The thickness of the second electrode 7 is about 10 to 40 μm.
このような第２電極７は、例えば、銀を主成分とする導電性ペーストをスクリーン印刷等によって所望の形状に塗布した後、焼成することによって形成することができる。なお、第２電極７は第１電極６に比べて短手方向の幅を広くすることによって、第２電極７の直列抵抗を下げて、太陽電池素子１０の出力特性を向上することができる。また、第２集電電極７ｂの材料に主にアルミニウムを使用して、第２出力取出電極７ａの材料に主に銀を使用してもよい。
Such a second electrode 7 can be formed by, for example, applying a conductive paste containing silver as a main component into a desired shape by screen printing or the like and then baking it. In addition, the 2nd electrode 7 can make the width | variety of a transversal direction wide compared with the 1st electrode 6, can lower the series resistance of the 2nd electrode 7, and can improve the output characteristic of the solar cell element 10. FIG. Alternatively, aluminum may be mainly used as the material of the second collector electrode 7b, and silver may be mainly used as the material of the second output extraction electrode 7a.
＜太陽電池素子の製造方法＞
本実施形態の太陽電池素子１０の製造方法は、第１主面１０ａにｎ型半導体領域を有しており、第１主面１０ａとは反対側に位置する第２主面１０ｂにｐ型半導体領域を有している半導体基板１を準備する半導体基板準備工程と、ｎ型半導体領域の上に、原子層蒸着法によって負の固定電荷密度を有する第１パッシベーション層８を形成するパッシベーション層形成工程と、第１パッシベーション層８の上に、プラズマＣＶＤ法またはスパッタリング法によって第１パッシベーション層８よりも固定電荷密度が正側に大きい反射防止層を形成する反射防止層形成工程とを含む。 <Method for producing solar cell element>
The manufacturing method of thesolar cell element 10 of this embodiment has an n-type semiconductor region on the first main surface 10a, and a p-type semiconductor on the second main surface 10b located on the opposite side to the first main surface 10a. A semiconductor substrate preparation step of preparing a semiconductor substrate 1 having a region, and a passivation layer formation step of forming a first passivation layer 8 having a negative fixed charge density on the n-type semiconductor region by an atomic layer deposition method And an antireflection layer forming step of forming an antireflection layer having a fixed charge density larger than that of the first passivation layer 8 on the positive side by the plasma CVD method or the sputtering method on the first passivation layer 8.
本実施形態の太陽電池素子１０の製造方法は、第１主面１０ａにｎ型半導体領域を有しており、第１主面１０ａとは反対側に位置する第２主面１０ｂにｐ型半導体領域を有している半導体基板１を準備する半導体基板準備工程と、ｎ型半導体領域の上に、原子層蒸着法によって負の固定電荷密度を有する第１パッシベーション層８を形成するパッシベーション層形成工程と、第１パッシベーション層８の上に、プラズマＣＶＤ法またはスパッタリング法によって第１パッシベーション層８よりも固定電荷密度が正側に大きい反射防止層を形成する反射防止層形成工程とを含む。 <Method for producing solar cell element>
The manufacturing method of the
次に、太陽電池素子１０の製造方法の上記各工程について、詳細に説明する。
Next, each process of the method for manufacturing the solar cell element 10 will be described in detail.
まず、ｐ型半導体領域である第１半導体層２を有する半導体基板１の半導体基板準備工程について説明する。半導体基板１は、例えば、既存の鋳造法などによって形成される。なお、以下では、半導体基板１として、ｐ型を呈する多結晶シリコン基板を用いた例について説明する。
First, the semiconductor substrate preparation process of the semiconductor substrate 1 having the first semiconductor layer 2 which is a p-type semiconductor region will be described. The semiconductor substrate 1 is formed by, for example, an existing casting method. Hereinafter, an example in which a p-type polycrystalline silicon substrate is used as the semiconductor substrate 1 will be described.
最初に、例えば、鋳造法によって多結晶シリコンのインゴットを作製する。次いで、そのインゴットを、例えば、２５０μｍ以下の厚みにスライスする。その後、半導体基板１の切断面の機械的ダメージ層および汚染層を清浄するために、半導体基板１の表面をＮａＯＨ、ＫＯＨ、フッ酸またはフッ硝酸などの水溶液でごく微量エッチングしてもよい。
First, for example, an ingot of polycrystalline silicon is produced by a casting method. Next, the ingot is sliced to a thickness of 250 μm or less, for example. Thereafter, in order to clean the mechanical damage layer and the contaminated layer on the cut surface of the semiconductor substrate 1, the surface of the semiconductor substrate 1 may be etched by a very small amount with an aqueous solution such as NaOH, KOH, hydrofluoric acid or hydrofluoric nitric acid.
次に、半導体基板１の第１主面１０ａに凹凸形状１ａを形成する。凹凸形状の形成方法としては、ＮａＯＨ等のアルカリ溶液またはフッ硝酸等の酸溶液を使用したウエットエッチング方法またはＲＩＥ（Reactive Ion Etching）等を使用したドライエッチング方法を用いることができる。
Next, the uneven shape 1 a is formed on the first main surface 10 a of the semiconductor substrate 1. As a method for forming the concavo-convex shape, a wet etching method using an alkali solution such as NaOH or an acid solution such as hydrofluoric acid, or a dry etching method using RIE (Reactive Ion Etching) or the like can be used.
次に、上記工程によって形成された凹凸形状１ａを有する半導体基板１の第１主面１０ａに対して、ｎ型半導体領域である第２半導体層３を形成する工程を行なう。具体的には、凹凸形状１ａを有する半導体基板１における第１主面１０ａ側の表層内にｎ型の第２半導体層３を形成する。
Next, a step of forming the second semiconductor layer 3 which is an n-type semiconductor region is performed on the first main surface 10a of the semiconductor substrate 1 having the concavo-convex shape 1a formed by the above steps. Specifically, the n-type second semiconductor layer 3 is formed in the surface layer on the first main surface 10a side in the semiconductor substrate 1 having the uneven shape 1a.
このような第２半導体層３は、ペースト状態にした五酸化リン（Ｐ２Ｏ５）を半導体基板１の表面に塗布して熱拡散させる塗布熱拡散法、または、ガス状態にしたオキシ塩化リン（ＰＯＣｌ３）を拡散源とした気相熱拡散法などによって形成される。この第２半導体層３は、０．２～２μｍ程度の深さ、４０～２００Ω／□程度のシート抵抗値を有するように形成される。例えば、気相熱拡散法では、ＰＯＣｌ３等からなる拡散ガスを有する雰囲気中で６００℃～８００℃程度の温度において、半導体基板１を５～３０分程度熱処理して燐ガラスを半導体基板１の表面に形成する。その後、アルゴンや窒素等の不活性ガス雰囲気中で８００～９００℃程度の高い温度において、半導体基板１を１０～４０分間程度熱処理することによって、燐ガラスから半導体基板１にリンが拡散して、半導体基板１の第１主面側に第２半導体層３が形成される。
Such a second semiconductor layer 3 may be formed by applying a thermal diffusion method in which phosphorus pentoxide (P 2 O 5 ) in a paste state is applied to the surface of the semiconductor substrate 1 and thermally diffused, or in a gas state. It is formed by a vapor phase thermal diffusion method using (POCl 3 ) as a diffusion source. The second semiconductor layer 3 is formed to have a depth of about 0.2 to 2 μm and a sheet resistance value of about 40 to 200 Ω / □. For example, in the vapor phase thermal diffusion method, the semiconductor substrate 1 is heat-treated at a temperature of about 600 ° C. to 800 ° C. for about 5 to 30 minutes in an atmosphere having a diffusion gas made of POCl 3 or the like to convert the phosphor glass into the semiconductor substrate 1. Form on the surface. Thereafter, by heat-treating the semiconductor substrate 1 for about 10 to 40 minutes at a high temperature of about 800 to 900 ° C. in an inert gas atmosphere such as argon or nitrogen, phosphorus diffuses from the phosphor glass to the semiconductor substrate 1, The second semiconductor layer 3 is formed on the first main surface side of the semiconductor substrate 1.
次に、上記第２半導体層３の形成工程において、第２主面１０ｂ側にも第２半導体層３が形成された場合には、第２主面１０ｂ側に形成された第２半導体層３のみをエッチングして除去する。これにより、第２主面１０ｂ側にｐ型の導電型領域を露出させる。例えば、フッ硝酸溶液に半導体基板１における第２主面１０ｂ側のみを浸して、第２主面１０ｂ側に形成された第２半導体層３を除去する。その後に、第２半導体層３を形成する際に半導体基板１の表面（第１主面１０ａ側）に付着した燐ガラスをエッチングして除去する。
Next, in the step of forming the second semiconductor layer 3, when the second semiconductor layer 3 is also formed on the second main surface 10b side, the second semiconductor layer 3 formed on the second main surface 10b side. Only etch away. Thereby, the p-type conductivity type region is exposed on the second main surface 10b side. For example, the second semiconductor layer 3 formed on the second main surface 10b side is removed by immersing only the second main surface 10b side of the semiconductor substrate 1 in a hydrofluoric acid solution. Thereafter, the phosphor glass adhering to the surface (first main surface 10a side) of the semiconductor substrate 1 when forming the second semiconductor layer 3 is removed by etching.
このように、第１主面１０ａ側に燐ガラスを残存させて、第２主面１０ｂ側に形成された第２半導体層３を除去することによって、燐ガラスによって第１主面１０ａ側の第２半導体層３が除去されたり、ダメージを受けたりするのを低減することができる。また、半導体基板１の側面に形成された第２半導体層３も合わせて除去してもよい。
In this way, the phosphorous glass remains on the first major surface 10a side, and the second semiconductor layer 3 formed on the second major surface 10b side is removed, so that the first glass on the first major surface 10a side is removed by phosphorous glass. 2 It is possible to reduce the semiconductor layer 3 from being removed or damaged. Further, the second semiconductor layer 3 formed on the side surface of the semiconductor substrate 1 may also be removed.
また、上記第２半導体層３の形成工程において、予め第２主面１０ｂ側に拡散マスクを形成しておき、気相熱拡散法等によって第２半導体層３を形成して、続いて拡散マスクを除去してもよい。このようなプロセスによっても、同様の構造を形成することが可能であり、この場合には、上記した第２主面１０ｂ側に第２半導体層３は形成されないため、第２主面１０ｂ側の第２半導体層３を除去する工程が不要である。
Further, in the step of forming the second semiconductor layer 3, a diffusion mask is formed in advance on the second main surface 10b side, the second semiconductor layer 3 is formed by vapor phase thermal diffusion or the like, and then the diffusion mask. May be removed. Even by such a process, it is possible to form a similar structure. In this case, since the second semiconductor layer 3 is not formed on the second main surface 10b side, the second main surface 10b side is formed. A step of removing the second semiconductor layer 3 is not necessary.
なお、第２半導体層３の形成方法は上記方法に限定されるものではなく、例えば薄膜技術を用いて、ｎ型の水素化アモルファスシリコン膜または微結晶シリコン膜を含む結晶質シリコン膜などを形成してもよい。さらに、第１半導体層２と第２半導体層３との間にｉ型シリコン領域を形成してもよい。
The method for forming the second semiconductor layer 3 is not limited to the above method. For example, a thin film technique is used to form an n-type hydrogenated amorphous silicon film or a crystalline silicon film including a microcrystalline silicon film. May be. Furthermore, an i-type silicon region may be formed between the first semiconductor layer 2 and the second semiconductor layer 3.
以上により、第１主面１０ａ側にｎ型半導体領域である第２半導体層３が配置されて、且つ、ｐ型半導体領域である第１半導体層２を含む多結晶シリコン基板の半導体基板１を準備することができる。
As described above, the semiconductor substrate 1 of the polycrystalline silicon substrate in which the second semiconductor layer 3 which is the n-type semiconductor region is disposed on the first main surface 10a side and which includes the first semiconductor layer 2 which is the p-type semiconductor region. Can be prepared.
次に、半導体基板１の第１主面１０ａ側および第２主面１０ｂ側にパッシベーション層を形成するパッシベーション層形成工程について説明する。第２半導体層３の上に第１パッシベーション層８を形成して、第１半導体層２の上に第２パッシベーション層９を形成する。第１パッシベーション層８および第２パッシベーション層９は、例えば、ＡＬＤ（Atomic Layer Deposition：原子層蒸着）法を用いることによって、半導体基板１の全周囲に同時に形成することができる。つまり、半導体基板１の側面１０ｃにも例えば酸化アルミニウム層からなる第３パッシベーション層１１が形成される。
Next, a passivation layer forming step for forming a passivation layer on the first main surface 10a side and the second main surface 10b side of the semiconductor substrate 1 will be described. A first passivation layer 8 is formed on the second semiconductor layer 3, and a second passivation layer 9 is formed on the first semiconductor layer 2. The first passivation layer 8 and the second passivation layer 9 can be simultaneously formed on the entire periphery of the semiconductor substrate 1 by using, for example, an ALD (Atomic Layer Deposition) method. That is, the third passivation layer 11 made of, for example, an aluminum oxide layer is also formed on the side surface 10 c of the semiconductor substrate 1.
より具体的には、成膜室内に上述の半導体基板１を載置して、基板温度を１００～３００℃に加熱する。次に、トリメチルアルミニウム等のアルミニウム原料を、アルゴンガス、窒素ガス等のキャリアガスとともに０．５秒間、半導体基板１上に供給して、半導体基板１の全周囲にアルミニウム原料を吸着させる（工程１）。次に、窒素ガスによって成膜室内を１秒間パージすることによって、空間中のアルミニウム原料を除去するとともに、半導体基板１に吸着したアルミニウム原料のうち、原子層レベルで吸着した成分以外を除去する（工程２）。次に、水またはオゾンガス等の酸化剤を、成膜室内に４秒間供給して、アルミニウム原料であるトリメチルアルミニウムのアルキル基であるＣＨ３を除去するとともに、アルミニウムの未結合手を酸化させ、半導体基板１に酸化アルミニウムの原子層を形成する（工程３）。次に、窒素ガスによって成膜室内を１．５秒間パージすることによって、空間中の酸化剤を除去するとともに、原子層レベルの酸化アルミニウム以外、例えば、反応に寄与しなかった酸化剤等を除去する（工程４）。そして、上記工程１から工程４を繰り返すことによって、所定厚みを有する、酸化アルミニウム層を形成することができる。また、工程３で用いる酸化剤に水素を含有させることによって、酸化アルミニウム層に水素が含有されやすくなり、水素パッシベーション効果を増大させることができる。
More specifically, the above-described semiconductor substrate 1 is placed in the deposition chamber, and the substrate temperature is heated to 100 to 300 ° C. Next, an aluminum raw material such as trimethylaluminum is supplied onto the semiconductor substrate 1 together with a carrier gas such as argon gas or nitrogen gas for 0.5 seconds so that the aluminum raw material is adsorbed on the entire periphery of the semiconductor substrate 1 (step 1). ). Next, by purging the film formation chamber with nitrogen gas for 1 second, the aluminum raw material in the space is removed, and among the aluminum raw material adsorbed on the semiconductor substrate 1, components other than those adsorbed at the atomic layer level are removed ( Step 2). Next, an oxidizing agent such as water or ozone gas is supplied into the film formation chamber for 4 seconds to remove CH 3 that is an alkyl group of trimethylaluminum that is an aluminum raw material, and to oxidize dangling bonds of aluminum, thereby producing a semiconductor. An atomic layer of aluminum oxide is formed on the substrate 1 (step 3). Next, purging the film formation chamber with nitrogen gas for 1.5 seconds removes the oxidant in the space and removes the oxidant that did not contribute to the reaction other than aluminum oxide at the atomic layer level. (Step 4). And the aluminum oxide layer which has predetermined thickness can be formed by repeating the said process 1 to the process 4. Moreover, hydrogen is easily contained in the aluminum oxide layer by containing hydrogen in the oxidizing agent used in step 3, and the hydrogen passivation effect can be increased.
次に、半導体基板１における第１主面１０ａ側に、すなわち、第１パッシベーション層８の上に反射防止層５を形成する反射防止層形成工程ついて説明する。反射防止層５は、例えば、ＰＥＣＶＤ（Plasma Enhanced Chemical Vapor Deposition）法、蒸着法またはスパッタリング法などを用いて形成される。例えば、窒化シリコン膜からなる反射防止層５をＰＥＣＶＤ法で形成する場合であれば、シラン（ＳｉＨ４）とアンモニア（ＮＨ３）との混合ガスを窒素（Ｎ２）で希釈して、グロー放電分解でプラズマ化させて堆積させることで反射防止層５が形成される。このときの成膜室内は５００℃程度とすることができる。
Next, an antireflection layer forming step for forming the antireflection layer 5 on the first main surface 10a side of the semiconductor substrate 1, that is, on the first passivation layer 8 will be described. The antireflection layer 5 is formed using, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition) method, vapor deposition method, sputtering method, or the like. For example, when the antireflection layer 5 made of a silicon nitride film is formed by PECVD, a mixed gas of silane (SiH 4 ) and ammonia (NH 3 ) is diluted with nitrogen (N 2 ), and glow discharge is performed. The antireflection layer 5 is formed by forming the plasma by decomposition and depositing it. The film formation chamber at this time can be set to about 500 ° C.
また、上述したように第１パッシベーション層８および第２パッシベーション層９の形成においてＡＬＤ法を使用することによって、半導体基板１表面の微小な凹凸に応じて酸化アルミニウム層が形成されることから、表面パッシベーション効果を高めることができる。そして、反射防止層５をＡＬＤ法以外のＰＥＣＶＤ法またはスパッタリング法を用いることによって、必要とする膜厚を速く形成することができて、生産性を向上させることができる。
In addition, as described above, by using the ALD method in the formation of the first passivation layer 8 and the second passivation layer 9, an aluminum oxide layer is formed according to minute irregularities on the surface of the semiconductor substrate 1, so that the surface The passivation effect can be enhanced. Then, by using the PECVD method or the sputtering method other than the ALD method for the antireflection layer 5, the required film thickness can be formed quickly, and the productivity can be improved.
次に、第１電極６（第１出力取出電極６ａ、第１集電電極６ｂ）と第２電極７（第２出力取出電極７ａ、第２集電電極７ｂ）とを以下のようにして形成する。
Next, the first electrode 6 (first output extraction electrode 6a, first collector electrode 6b) and the second electrode 7 (second output extraction electrode 7a, second collector electrode 7b) are formed as follows. To do.
最初に、第１電極６について説明する。第１電極６は、例えば銀等からなる金属粉末と、有機ビヒクルと、ガラスフリットとを含有する導電性ペーストを用いて作製される。この導電性ペーストを、半導体基板１の第１主面１０ａに塗布して、その後、最高温度６００～８００℃で数十秒～数十分程度焼成することによって第１電極６を形成する。塗布法としては、スクリーン印刷法などを用いることができて、塗布後、所定の温度で溶剤を蒸散させて乾燥してもよい。なお、第１電極６は、第１出力取出電極６ａと第１集電電極６ｂとを有するが、スクリーン印刷を用いることで、第１取出電極６ａと第１集電電極６ｂとは、１つの工程で形成することができる。
First, the first electrode 6 will be described. The first electrode 6 is manufactured using a conductive paste containing, for example, a metal powder made of silver or the like, an organic vehicle, and glass frit. This conductive paste is applied to the first main surface 10a of the semiconductor substrate 1, and then fired at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes to form the first electrode 6. As the coating method, a screen printing method or the like can be used. After coating, the solvent may be evaporated at a predetermined temperature and dried. The first electrode 6 includes a first output extraction electrode 6a and a first current collection electrode 6b. However, by using screen printing, the first extraction electrode 6a and the first current collection electrode 6b are one It can be formed in a process.
次に、第３半導体層４および第２電極７の形成工程について説明する。ガラスフリットを含有したアルミニウムペーストを第２パッシベーション層９の上に直接、所定領域に塗布し、最高温度が６００～８００℃の高温の熱処理を行なうファイヤースルー法によって、塗布されたペースト成分が第２パッシベーション層９を突き破り、半導体基板１の第２主面１０ｂ側に第３半導体層４が形成されて、その上にアルミニウム層が形成される。なお、このアルミニウム層は第２電極７として使用することができて、その形成領域としては、例えば、図４に示すように、第２主面１０ｂのうち第２集電電極７ｂと第２出力取出電極７ａとの一部が形成される領域内とすればよい。そして、第２出力取出電極７ａは、例えば銀等からなる金属粉末と、有機ビヒクルと、ガラスフリットとを含有する導電性ペーストを用いて作製される。この導電性ペーストを、第２パッシベーション層９に塗布して、その後、最高温度６００～８００℃で数十秒～数十分程度焼成することによって、第２出力取出電極７ａを形成する。塗布法としては、スクリーン印刷法などを用いることができて、塗布後、所定の温度で溶剤を蒸散させて乾燥してもよい。銀からなる第２出力取出電極７ａはアルミニウム層と接触することによって、第２集電電極７ｂと接続される。なお、先に銀からなる第２出力取出電極７ａを形成して、その後、アルミニウムからなる第２集電電極７ｂを形成してもよい。また、第２出力取出電極７ａは半導体基板１と直接接触する必要はなく、第２出力取出電極７ａと半導体基板１との間に第２パッシベーション層９が存在しても構わない。なお、第３半導体層４の上に形成されたアルミニウム層は除去してもよく、同一の導電性ペーストを用いて第２取出電極７ａと第２集電電極７ｂとを形成してもよい。また、第１電極６および第２電極７は、各々の導電性ペーストを塗布した後、同時に焼成して形成しても構わない。
Next, a process for forming the third semiconductor layer 4 and the second electrode 7 will be described. An aluminum paste containing glass frit is applied directly onto the second passivation layer 9 in a predetermined region, and the applied paste component is applied to the second paste by a fire-through method in which a heat treatment at a maximum temperature of 600 to 800 ° C. is performed. Passing through the passivation layer 9, the third semiconductor layer 4 is formed on the second main surface 10b side of the semiconductor substrate 1, and an aluminum layer is formed thereon. This aluminum layer can be used as the second electrode 7, and as its formation region, for example, as shown in FIG. 4, the second current collecting electrode 7b and the second output of the second main surface 10b are used. What is necessary is just to set it as the area | region in which a part with extraction electrode 7a is formed. And the 2nd output extraction electrode 7a is produced using the electrically conductive paste containing the metal powder which consists of silver etc., an organic vehicle, and glass frit, for example. This conductive paste is applied to the second passivation layer 9 and then baked at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes to form the second output extraction electrode 7a. As the coating method, a screen printing method or the like can be used. After coating, the solvent may be evaporated at a predetermined temperature and dried. The second output extraction electrode 7a made of silver is connected to the second collector electrode 7b by contacting the aluminum layer. Alternatively, the second output extraction electrode 7a made of silver may be formed first, and then the second current collecting electrode 7b made of aluminum may be formed. Further, the second output extraction electrode 7 a does not need to be in direct contact with the semiconductor substrate 1, and the second passivation layer 9 may exist between the second output extraction electrode 7 a and the semiconductor substrate 1. The aluminum layer formed on the third semiconductor layer 4 may be removed, and the second extraction electrode 7a and the second current collecting electrode 7b may be formed using the same conductive paste. Further, the first electrode 6 and the second electrode 7 may be formed by applying the respective conductive pastes and firing them simultaneously.
なお、上記では印刷・焼成法によって第１電極６および第２電極７を形成する形態を例示したが、これらの電極は蒸着やスパッタリング等の薄膜形成やメッキ形成を用いて形成することも可能である。
In addition, although the form which forms the 1st electrode 6 and the 2nd electrode 7 by the printing / baking method was illustrated above, these electrodes can also be formed using thin film formation, such as vapor deposition and sputtering, and plating formation. is there.
なお、上述の第１パッシベーション層８および第２パッシベーション層９を形成する工程の後の各工程において、各工程における最高温度の熱処理を８００℃以下とすることによって、水素パッシベーション効果を増大させることができる。例えば、第１パッシベーション層８および第２パッシベーション層９を形成する工程の後に行なう各工程において、３００～５００℃の熱処理による熱履歴を５～３０分とすればよい。
In each step after the step of forming the first passivation layer 8 and the second passivation layer 9 described above, the hydrogen passivation effect can be increased by setting the maximum temperature heat treatment in each step to 800 ° C. or less. it can. For example, in each step performed after the step of forming the first passivation layer 8 and the second passivation layer 9, the heat history by heat treatment at 300 to 500 ° C. may be 5 to 30 minutes.
以上のようにして、太陽電池素子１０を作製することができる。
The solar cell element 10 can be manufactured as described above.
なお、本発明は上記形態に限定されるものではなく、多くの修正および変更を加えることができる。例えば、第２パッシベーション層９を形成する前に第３半導体層４を形成してもよく、この場合、第２パッシベーション層９の形成工程の前に、第２主面１０ｂにおける所定領域にボロンまたはアルミニウムを拡散すればよい。ボロンは三臭化ボロン（ＢＢｒ３）を拡散源とした熱拡散法を用いて温度８００～１１００℃程度で加熱することによって拡散される。
In addition, this invention is not limited to the said form, Many corrections and changes can be added. For example, the third semiconductor layer 4 may be formed before the second passivation layer 9 is formed. In this case, before forming the second passivation layer 9, boron or a predetermined region in the second main surface 10b is formed. What is necessary is just to diffuse aluminum. Boron is diffused by heating at a temperature of about 800 to 1100 ° C. using a thermal diffusion method using boron tribromide (BBr 3 ) as a diffusion source.
また、例えば、第３半導体層４として、薄膜技術を用いて、ｐ型の水素化アモルファスシリコン膜、または微結晶シリコン膜を含む結晶質シリコン膜などを形成してもよい。さらに、半導体基板１と第３半導体層４との間にｉ型シリコン領域を形成してもよい。
Alternatively, for example, a p-type hydrogenated amorphous silicon film or a crystalline silicon film including a microcrystalline silicon film may be formed as the third semiconductor layer 4 using thin film technology. Further, an i-type silicon region may be formed between the semiconductor substrate 1 and the third semiconductor layer 4.
また、第１パッシベーション層８および第２パッシベーション層９を形成する前に、半導体基板１を洗浄してもよい。洗浄工程としては、例えば、フッ酸処理、ＲＣＡ洗浄（米国ＲＣＡ社が開発した洗浄法であり、高温・高濃度の硫酸・過酸化水素水、希フッ酸（室温）、アンモニア水・過酸化水素水、または、塩酸・過酸化水素水などによる洗浄方法）および該洗浄後のフッ酸処理、またはＳＰＭ（Sulfuric Acid/Hydrogen Peroxide/Water Mixture）洗浄および該洗浄後のフッ酸処理等による洗浄方法を用いることができる。
Further, the semiconductor substrate 1 may be cleaned before forming the first passivation layer 8 and the second passivation layer 9. Examples of the cleaning process include hydrofluoric acid treatment, RCA cleaning (cleaning method developed by RCA, USA, high temperature / high concentration sulfuric acid / hydrogen peroxide solution, dilute hydrofluoric acid (room temperature), ammonia water / hydrogen peroxide. Cleaning method using water or hydrochloric acid / hydrogen peroxide solution) and hydrofluoric acid treatment after the cleaning, or SPM (Sulfuric Acid / Hydrogen Peroxide / Water Mixture) cleaning and cleaning method using hydrofluoric acid treatment after the cleaning Can be used.
また、第１パッシベーション層８および第２パッシベーション層９を形成する工程の後の任意の工程において、水素を含んだガスを用いてアニール処理を行なうことで、さらに、半導体基板１における再結合速度を低下させることが可能である。
Further, in an optional step after the step of forming the first passivation layer 8 and the second passivation layer 9, annealing is performed using a gas containing hydrogen, and the recombination speed in the semiconductor substrate 1 is further increased. It can be reduced.
＜太陽電池モジュール＞
本実施形態に係る太陽電池モジュール２０について、図５（ａ）および図５（ｂ）を用いて詳細に説明する。太陽電池モジュール２０は、上述した本実施形態の太陽電池素子１０を１つ以上備えている。具体的には、太陽電池モジュール２０においては、上記太陽電池素子１０が複数電気的に接続されている。 <Solar cell module>
Thesolar cell module 20 according to the present embodiment will be described in detail with reference to FIGS. 5 (a) and 5 (b). The solar cell module 20 includes one or more solar cell elements 10 of the present embodiment described above. Specifically, in the solar cell module 20, a plurality of the solar cell elements 10 are electrically connected.
本実施形態に係る太陽電池モジュール２０について、図５（ａ）および図５（ｂ）を用いて詳細に説明する。太陽電池モジュール２０は、上述した本実施形態の太陽電池素子１０を１つ以上備えている。具体的には、太陽電池モジュール２０においては、上記太陽電池素子１０が複数電気的に接続されている。 <Solar cell module>
The
単独の太陽電池素子１０の電気出力が小さい場合など、複数の太陽電池素子１０を直列および並列に接続することで太陽電池モジュール２０が構成される。この太陽電池モジュール２０を複数個組み合わせることによって、実用的な電気出力の取り出しが可能となる。
The solar cell module 20 is configured by connecting a plurality of solar cell elements 10 in series and in parallel, such as when the electric output of a single solar cell element 10 is small. By combining a plurality of solar cell modules 20, a practical electrical output can be taken out.
図５（ａ）に示すように、太陽電池モジュール２０は、例えば、ガラスなどの透明部材２２と、透明のＥＶＡまたはエチレン－α－オレフィン共重合体などからなる表側充填材２４と、複数の太陽電池素子１０と、これら複数の太陽電池素子１０を接続する配線部材２１と、ＥＶＡまたはエチレン－α－オレフィン共重合体などからなる裏側充填材２５と、ポリエチレンテレフタレート（ＰＥＴ）またはポリフッ化ビニル樹脂（ＰＶＦ）等の材料からなり、単層または積層構造の裏面保護材２３とを主として備えている。
As shown in FIG. 5 (a), the solar cell module 20 includes, for example, a transparent member 22 such as glass, a front filler 24 made of transparent EVA or ethylene-α-olefin copolymer, and a plurality of solar cells. Battery element 10, wiring member 21 connecting the plurality of solar battery elements 10, back side filler 25 made of EVA or ethylene-α-olefin copolymer, polyethylene terephthalate (PET) or polyvinyl fluoride resin ( It is made of a material such as PVF, and mainly includes a back surface protective material 23 having a single layer or a laminated structure.
隣接する太陽電池素子１０同士は、一方の太陽電池素子１０の第１電極６と他方の太陽電池素子１０の第２電極７とが配線部材２１によって接続されることで、互いに電気的に直列に接続されている。
Adjacent solar cell elements 10 are electrically connected in series with each other by connecting the first electrode 6 of one solar cell element 10 and the second electrode 7 of the other solar cell element 10 by a wiring member 21. It is connected.
配線部材２１としては、例えば、厚さ０．１～０．２ｍｍ程度、幅２ｍｍ程度の銅箔の全面を半田材料によって被覆された部材が用いられる。
As the wiring member 21, for example, a member in which the entire surface of a copper foil having a thickness of about 0.1 to 0.2 mm and a width of about 2 mm is covered with a solder material is used.
また、直列接続された複数の太陽電池素子１０のうち、最初の太陽電池素子１０と最後の太陽電池素子１０の電極の一端は、各々、出力取出部である端子ボックス２７に、出力取出配線２６によって接続される。また、図５（ａ）では図示を省略しているが、図５（ｂ）に示すように、太陽電池モジュール２０は、アルミニウムなどからなる枠２８を備えていてもよい。
In addition, among the plurality of solar cell elements 10 connected in series, one end of the electrode of the first solar cell element 10 and the last solar cell element 10 is respectively connected to a terminal box 27 which is an output extraction part, and an output extraction wiring 26. Connected by. Although not shown in FIG. 5A, as shown in FIG. 5B, the solar cell module 20 may include a frame 28 made of aluminum or the like.
また、太陽電池モジュール２０において、白色系の裏側充填材２５を用いることによって、高機能の裏面反射構造を実現することが可能である。
Moreover, in the solar cell module 20, it is possible to realize a highly functional back surface reflection structure by using the white backside filler 25.
また、表側充填材２４がＥＶＡからなる場合、ＥＶＡがその成分として酢酸ビニルを含むため、ＥＶＡは高温時における湿気または水等の透過によって、経時的に加水分解して酢酸を生じ易い傾向にあるが、第１パッシベーション層８の上に反射防止層５を設けることによって、酸によるダメージを低減することができる。そのため、太陽電池モジュールの長期信頼性を確保することができる。さらに、表側充填材２４または裏側充填材２５がＥＶＡからなる場合には、表側充填材２４または裏側充填材２５に水酸化マグネシウムまたは水酸化カルシウム等からなる受酸剤を添加してもよい。受酸剤を設けることによって酢酸の発生を低減して、太陽電池モジュールの耐久性を向上させることができて、第１パッシベーション層８および第２パッシベーション層９への酸によるダメージをより低減することができる。そのため、太陽電池モジュールの長期信頼性を確保することができる。
Further, when the front side filler 24 is made of EVA, since EVA contains vinyl acetate as its component, EVA tends to be hydrolyzed with time due to permeation of moisture or water at a high temperature to easily generate acetic acid. However, by providing the antireflection layer 5 on the first passivation layer 8, damage due to acid can be reduced. Therefore, long-term reliability of the solar cell module can be ensured. Furthermore, when the front side filler 24 or the back side filler 25 is made of EVA, an acid acceptor made of magnesium hydroxide or calcium hydroxide may be added to the front side filler 24 or the back side filler 25. By providing an acid acceptor, the generation of acetic acid can be reduced, the durability of the solar cell module can be improved, and acid damage to the first passivation layer 8 and the second passivation layer 9 can be further reduced. Can do. Therefore, long-term reliability of the solar cell module can be ensured.
本実施形態に係る太陽電池モジュール２０は、上述したパッシベーション層を有する太陽電池素子１０を備えるため、太陽電池モジュール２０は出力特性に優れる。
Since the solar cell module 20 according to the present embodiment includes the solar cell element 10 having the above-described passivation layer, the solar cell module 20 is excellent in output characteristics.
以上、本発明に係るいくつかの実施形態について例示したが、本発明は上述した実施形態に限定されるものではなく、本発明の要旨を逸脱しない限り任意のものとすることができることは言うまでもない。
As mentioned above, although some embodiment which concerns on this invention was illustrated, this invention is not limited to embodiment mentioned above, It cannot be overemphasized that it can be made arbitrary, unless it deviates from the summary of this invention. .
例えば、太陽電池素子１０は第１出力取出電極６ａを第２主面１０ｂ側に設けたメタル・ラップ・スルー構造のバックコンタクト太陽電池素子であっても構わない。メタル・ラップ・スルー構造のバックコンタクト太陽電池素子３０としては、図６に示すように、第１半導体層２と、該第１半導体層２の第１主面１０ａ側に設けられた第２半導体層３と、を備えた半導体基板１に複数の貫通孔３１が設けられている。また、貫通孔３１内には第１主面１０ａ側に設けられた第１集電電極６ｂと第２主面１０ｂ側に設けられた第１出力取出電極６ａとを電気的に接続する第１接続電極６ｃが形成される。
For example, the solar cell element 10 may be a back contact solar cell element having a metal wrap through structure in which the first output extraction electrode 6a is provided on the second main surface 10b side. As shown in FIG. 6, the back contact solar cell element 30 having a metal wrap through structure includes a first semiconductor layer 2 and a second semiconductor provided on the first main surface 10 a side of the first semiconductor layer 2. A plurality of through holes 31 are provided in the semiconductor substrate 1 including the layer 3. Further, in the through hole 31, a first current collecting electrode 6b provided on the first main surface 10a side and a first output extraction electrode 6a provided on the second main surface 10b side are electrically connected. A connection electrode 6c is formed.
また、第１接続電極４ｃが貫通孔３１の上に直接形成されても構わないが、貫通孔３１の内壁において酸化アルミニウムからなる第４パッシベーション層３２が形成されてもよい。貫通孔３１の内壁にも第４パッシベーション層３２を設けることによってパッシベーション効果をさらに高めることができる。
The first connection electrode 4 c may be formed directly on the through hole 31, but the fourth passivation layer 32 made of aluminum oxide may be formed on the inner wall of the through hole 31. By providing the fourth passivation layer 32 also on the inner wall of the through hole 31, the passivation effect can be further enhanced.
また、図６（ａ）に示すように、貫通孔３１内面が一導電型の第１半導体層２からなる場合には、第４パッシベーション層３２は絶縁層として機能するため、リークの発生を低減することができる。
Further, as shown in FIG. 6A, when the inner surface of the through hole 31 is made of the first semiconductor layer 2 of one conductivity type, the fourth passivation layer 32 functions as an insulating layer, so that the occurrence of leakage is reduced. can do.
また、第４パッシベーション層３２の上に反射防止層５が形成されていても構わない。また、図６（ｂ）に示すように、貫通孔３１内面が逆導電型の第２半導体層３からなる場合には、第４パッシベーション層３２の上に酸化アルミニウム層等の負の固定電荷密度を有する層よりも正側に大きい反射防止層５を設けることが適している。
Further, the antireflection layer 5 may be formed on the fourth passivation layer 32. As shown in FIG. 6B, when the inner surface of the through hole 31 is composed of the second semiconductor layer 3 of the reverse conductivity type, a negative fixed charge density such as an aluminum oxide layer on the fourth passivation layer 32. It is suitable to provide the antireflection layer 5 which is larger on the positive side than the layer having s.
また、第１パッシベーション層８、第２パッシベーション層９および第４パッシベーション層３２は、いずれも同じ酸化アルミニウム層等の負の固定電荷密度を有する層から形成することによって、さらにパッシベーション効果を高めることができる。また、半導体基板１の全周囲に酸化アルミニウム層等の負の固定電荷密度を有する層を設けることがより好適である。つまり、半導体基板１の第１主面１０ａ、第２主面１０ｂ、貫通孔３１だけではなく、半導体基板１の側面においても酸化アルミニウム層等の負の固定電荷密度を有する第３パッシベーション層１１を設けるとよい。
Further, the first passivation layer 8, the second passivation layer 9, and the fourth passivation layer 32 are all formed of a layer having a negative fixed charge density such as the same aluminum oxide layer, thereby further enhancing the passivation effect. it can. It is more preferable to provide a layer having a negative fixed charge density such as an aluminum oxide layer around the entire periphery of the semiconductor substrate 1. That is, the third passivation layer 11 having a negative fixed charge density such as an aluminum oxide layer is formed not only on the first main surface 10a, the second main surface 10b, and the through hole 31 of the semiconductor substrate 1 but also on the side surface of the semiconductor substrate 1. It is good to provide.
以下に、上記実施形態のより具体的な実施例について説明する。まず、半導体基板１として、１辺が１５６ｍｍで厚さが約２００μｍの多結晶シリコン基板を多数用意した。これらの多結晶シリコン基板は、予めｐ型の導電型を呈するようにボロンをドープしたものを用いた。
Hereinafter, more specific examples of the above embodiment will be described. First, a large number of polycrystalline silicon substrates having a side of 156 mm and a thickness of about 200 μm were prepared as the semiconductor substrate 1. These polycrystalline silicon substrates were previously doped with boron so as to exhibit p-type conductivity.
用意したそれぞれの多結晶シリコン基板の第１主面１０ａ側に、ＲＩＥ法を用いて、図３に示すような凹凸構造１ａを形成した。
A concavo-convex structure 1a as shown in FIG. 3 was formed on the first main surface 10a side of each prepared polycrystalline silicon substrate by using the RIE method.
次に、リン原子を拡散させて、シート抵抗が９０Ω／□程度となるｎ型の第２半導体層３を基板１の表面に形成した。なお、側面および第２主面１０ｂ側に形成された第２半導体層３はフッ硝酸溶液で除去し、その後、第２半導体層３上に残った燐ガラスをフッ酸溶液で除去した。
Next, phosphorus atoms were diffused to form an n-type second semiconductor layer 3 having a sheet resistance of about 90 Ω / □ on the surface of the substrate 1. The second semiconductor layer 3 formed on the side surface and the second main surface 10b side was removed with a hydrofluoric acid solution, and thereafter the phosphorous glass remaining on the second semiconductor layer 3 was removed with a hydrofluoric acid solution.
次に、半導体基板１の全周囲にはＡＬＤ法によって酸化アルミニウム層からなる第１パッシベーション層８、第２パッシベーション層９および第３パッシベーション層１１を形成して、第１パッシベーション層８の上にはプラズマＣＶＤ法によって窒化シリコン層からなる反射防止層５を形成した。
Next, a first passivation layer 8, a second passivation layer 9, and a third passivation layer 11 made of an aluminum oxide layer are formed on the entire periphery of the semiconductor substrate 1 by the ALD method, and the first passivation layer 8 is formed on the first passivation layer 8. An antireflection layer 5 made of a silicon nitride layer was formed by plasma CVD.
そして、第１主面１０ａ側には銀ペーストを図１に示すような線状パターンに塗布し、第２主面１０ｂ側には、アルミニウムペーストを図４に示すような第２集電電極７ｂのパターンと第２出力取出電極７ａの一部とに塗布し、さらに銀ペーストを図２に示すような第２出力取出電極７ａのパターンに塗布した。その後、これらのペーストのパターンを焼成することによって、図１および図２に示すように、第３半導体層４、第１電極６および第２電極７を形成した。なお、第１電極６および第２集電電極７ｂはファイヤースルー法によって、それぞれ半導体基板１とコンタクトをとった。
Then, a silver paste is applied in a linear pattern as shown in FIG. 1 on the first main surface 10a side, and an aluminum paste is applied on the second main surface 10b side as a second current collecting electrode 7b as shown in FIG. 2 and a part of the second output extraction electrode 7a, and further silver paste was applied to the pattern of the second output extraction electrode 7a as shown in FIG. Thereafter, the patterns of these pastes were baked to form the third semiconductor layer 4, the first electrode 6, and the second electrode 7, as shown in FIGS. The first electrode 6 and the second collector electrode 7b were in contact with the semiconductor substrate 1 by the fire-through method, respectively.
このようにして太陽電池素子１０を作製した。ここで、実施例として、実施例１においては、第１パッシベーション層８、第２パッシベーション層９および第３パッシベーション層１１の平均厚みが３５ｎｍ、反射防止層５の平均厚みが４５ｎｍであり、実施例２においては、第１パッシベーション層８、第２パッシベーション層９および第３パッシベーション層１１の平均厚みが４５ｎｍ、反射防止層５の平均厚みが３５ｎｍであった。また、比較例として、実施例の第１パッシベーション層８および反射防止膜５に代えて、第１主面１０ａ側に平均厚み８０ｎｍの窒化シリコン層のみを形成した太陽電池素子（比較例１）、第１主面１０ａ側に平均厚み８０ｎｍの酸化アルミニウム層のみを形成した太陽電池素子（比較例２）および第１主面１０ａ側に平均厚み４５ｎｍの窒化シリコン層を形成し、その窒化シリコン層の上に平均厚み３５ｎｍの酸化アルミニウム層を形成した太陽電池素子（比較例３）を作製した。なお、上記の平均厚みは、エリプソメータ（SENTECH社製SE-400adv）を使用して、５箇所を測定した結果を平均して求めた。
In this way, a solar cell element 10 was produced. Here, as an example, in Example 1, the average thickness of the first passivation layer 8, the second passivation layer 9, and the third passivation layer 11 is 35 nm, and the average thickness of the antireflection layer 5 is 45 nm. 2, the average thickness of the first passivation layer 8, the second passivation layer 9, and the third passivation layer 11 was 45 nm, and the average thickness of the antireflection layer 5 was 35 nm. As a comparative example, instead of the first passivation layer 8 and the antireflection film 5 of the example, a solar cell element (Comparative Example 1) in which only a silicon nitride layer having an average thickness of 80 nm is formed on the first main surface 10a side. A solar cell element (Comparative Example 2) in which only an aluminum oxide layer having an average thickness of 80 nm is formed on the first main surface 10a side, and a silicon nitride layer having an average thickness of 45 nm are formed on the first main surface 10a side. A solar cell element (Comparative Example 3) having an aluminum oxide layer with an average thickness of 35 nm formed thereon was produced. In addition, said average thickness was calculated | required by averaging the result of having measured 5 places using the ellipsometer (SE-400adv by SENTECH).
実施例および比較例のそれぞれについて、太陽電池素子出力特性（短絡電流Ｉｓｃ、開放電圧Ｖｏｃ、曲線因子ＦＦ（Fill Factor）および光電変換効率）を測定して評価した。これら特性の測定結果を表１に示す。なお、これらの特性の測定はＪＩＳ Ｃ ８９１３に基づいて、ＡＭ（Air Mass）１．５および１００ｍＷ／ｃｍ２の照射の条件下にて測定した。
For each of the examples and comparative examples, the solar cell element output characteristics (short-circuit current Isc, open-circuit voltage Voc, fill factor (FF) and photoelectric conversion efficiency) were measured and evaluated. Table 1 shows the measurement results of these characteristics. In addition, the measurement of these characteristics was measured on the conditions of irradiation of AM (Air Mass) 1.5 and 100 mW / cm < 2 > based on JISC8913.
実施例１、２は比較例１～３に比べて光電変換効率が高いことを確認した。さらに、実施例１は実施例２に比べて短絡電流Ｉｓｃが高く、光電変換効率が高いことを確認した。
Examples 1 and 2 were confirmed to have higher photoelectric conversion efficiency than Comparative Examples 1 to 3. Furthermore, it was confirmed that Example 1 had a higher short circuit current Isc and higher photoelectric conversion efficiency than Example 2.
１ ：半導体基板（多結晶シリコン基板）
２ ：第１半導体層（ｐ型半導体領域）
３ ：第２半導体層（ｎ型半導体領域）
４ ：第３半導体層
５ ：反射防止層
６ ：第１電極
６ａ ：第１出力取出電極
６ｂ ：第１集電電極
７ ：第２電極
７ａ ：第２出力取出電極
７ｂ ：第２集電電極
８ ：第１パッシベーション層
９ ：第２パッシベーション層
１０ ：太陽電池素子
１０ａ：第１主面
１０ｂ：第２主面
１０ｃ：側面
１１ ：第３パッシベーション層
３０ ：太陽電池素子
３１ ：貫通孔
３２ ：第４パッシベーション層 1: Semiconductor substrate (polycrystalline silicon substrate)
2: First semiconductor layer (p-type semiconductor region)
3: Second semiconductor layer (n-type semiconductor region)
4: 3rd semiconductor layer 5: Antireflection layer 6:1st electrode 6a: 1st output extraction electrode 6b: 1st current collection electrode 7: 2nd electrode 7a: 2nd output extraction electrode 7b: 2nd current collection electrode 8 : 1st passivation layer 9: 2nd passivation layer 10: Solar cell element 10a: 1st main surface 10b: 2nd main surface 10c: Side surface 11: 3rd passivation layer 30: Solar cell element 31: Through-hole 32: 4th Passivation layer
２ ：第１半導体層（ｐ型半導体領域）
３ ：第２半導体層（ｎ型半導体領域）
４ ：第３半導体層
５ ：反射防止層
６ ：第１電極
６ａ ：第１出力取出電極
６ｂ ：第１集電電極
７ ：第２電極
７ａ ：第２出力取出電極
７ｂ ：第２集電電極
８ ：第１パッシベーション層
９ ：第２パッシベーション層
１０ ：太陽電池素子
１０ａ：第１主面
１０ｂ：第２主面
１０ｃ：側面
１１ ：第３パッシベーション層
３０ ：太陽電池素子
３１ ：貫通孔
３２ ：第４パッシベーション層 1: Semiconductor substrate (polycrystalline silicon substrate)
2: First semiconductor layer (p-type semiconductor region)
3: Second semiconductor layer (n-type semiconductor region)
4: 3rd semiconductor layer 5: Antireflection layer 6:
Claims (15)
- 第１主面にｎ型半導体領域を有しており、前記第１主面とは反対側に位置する第２主面にｐ型半導体領域を有している半導体基板と、
前記ｎ型半導体領域の上に配置されており、負の固定電荷密度を有している第１パッシベーション層と、
該第１パッシベーション層の上に配置されている、該第１パッシベーション層よりも固定電荷密度が正側に大きい反射防止層とを備えている太陽電池素子。 A semiconductor substrate having an n-type semiconductor region on the first main surface and having a p-type semiconductor region on a second main surface located on the opposite side of the first main surface;
A first passivation layer disposed on the n-type semiconductor region and having a negative fixed charge density;
A solar cell element comprising: an antireflection layer disposed on the first passivation layer and having a higher fixed charge density on the positive side than the first passivation layer. - 前記半導体基板がシリコンからなり、前記第１パッシベーション層が酸化アルミニウム、酸化ハフニウムおよび酸化ジルコニウムから選択される１種以上からなる請求項１に記載の太陽電池素子。 The solar cell element according to claim 1, wherein the semiconductor substrate is made of silicon, and the first passivation layer is made of at least one selected from aluminum oxide, hafnium oxide, and zirconium oxide.
- 前記反射防止層は正の固定電荷密度を有している請求項１または２に記載の太陽電池素子。 The solar cell element according to claim 1 or 2, wherein the antireflection layer has a positive fixed charge density.
- 第１主面にｎ型半導体領域を有しており、前記第１主面とは反対側に位置する第２主面にｐ型半導体領域を有しているシリコンからなる半導体基板と、
前記ｎ型半導体領域の上に配置されており、酸化アルミニウム、酸化ハフニウムおよび酸化ジルコニウムから選択される１種以上からなる第１パッシベーション層と、
該第１パッシベーション層の上に配置されている、酸化シリコンまたは窒化シリコンからなる反射防止層とを備えている太陽電池素子。 A semiconductor substrate made of silicon having an n-type semiconductor region on the first main surface and having a p-type semiconductor region on a second main surface located on the opposite side of the first main surface;
A first passivation layer that is disposed on the n-type semiconductor region and comprises at least one selected from aluminum oxide, hafnium oxide, and zirconium oxide;
The solar cell element provided with the antireflection layer which consists of a silicon oxide or silicon nitride arrange | positioned on this 1st passivation layer. - 前記第１パッシベーション層が酸化アルミニウムからなる請求項４に記載の太陽電池素子。 The solar cell element according to claim 4, wherein the first passivation layer is made of aluminum oxide.
- 前記第１パッシベーション層の平均厚みは前記反射防止膜層の平均厚みよりも薄い請求項１乃至５のいずれかに記載の太陽電池素子。 The solar cell element according to any one of claims 1 to 5, wherein an average thickness of the first passivation layer is thinner than an average thickness of the antireflection film layer.
- 前記ｐ型半導体領域の上に第２パッシベーション層が配置されている請求項１乃至６のいずれかに記載の太陽電池素子。 The solar cell element according to any one of claims 1 to 6, wherein a second passivation layer is disposed on the p-type semiconductor region.
- 前記半導体基板の側面に第３パッシベーション層が配置されている請求項１乃至７のいずれかに記載の太陽電池素子。 The solar cell element according to any one of claims 1 to 7, wherein a third passivation layer is disposed on a side surface of the semiconductor substrate.
- 前記半導体基板の側面側にも前記反射防止層が配置されている請求項１乃至８のいずれかに記載の太陽電池素子。 The solar cell element according to any one of claims 1 to 8, wherein the antireflection layer is also disposed on a side surface side of the semiconductor substrate.
- 前記第１パッシベーション層および前記第２パッシベーション層が同一材料からなる請求項７に記載の太陽電池素子。 The solar cell element according to claim 7, wherein the first passivation layer and the second passivation layer are made of the same material.
- 前記第１パッシベーション層および前記第３パッシベーション層が同一材料からなる請求項８に記載の太陽電池素子。 The solar cell element according to claim 8, wherein the first passivation layer and the third passivation layer are made of the same material.
- 第１主面にｎ型半導体領域を有しており、前記第１主面とは反対側に位置する第２主面にｐ型半導体領域を有している半導体基板を準備する半導体基板準備工程と、
前記ｎ型半導体領域の上に、原子層蒸着法によって負の固定電荷密度を有するパッシベーション層を形成するパッシベーション層形成工程と、
前記パッシベーション層の上に、プラズマＣＶＤ法によって前記パッシベーション層よりも固定電荷密度が正側に大きい反射防止層を形成する反射防止層形成工程とを含む太陽電池素子の製造方法。 A semiconductor substrate preparation step of preparing a semiconductor substrate having an n-type semiconductor region on the first main surface and having a p-type semiconductor region on a second main surface located on the opposite side of the first main surface When,
A passivation layer forming step of forming a passivation layer having a negative fixed charge density on the n-type semiconductor region by an atomic layer deposition method;
A method of manufacturing a solar cell element, comprising: forming an antireflection layer having a fixed charge density larger on the positive side than the passivation layer on the passivation layer by a plasma CVD method. - 前記パッシベーション層形成工程において、前記ｐ型半導体領域の上にも前記パッシベーション層を形成する請求項１２に記載の太陽電池素子の製造方法。 The method for manufacturing a solar cell element according to claim 12, wherein in the passivation layer forming step, the passivation layer is also formed on the p-type semiconductor region.
- 前記パッシベーション層形成工程において、前記半導体基板の側面にも前記パッシベーション層を形成する請求項１２または１３に記載の太陽電池素子の製造方法。 The method for manufacturing a solar cell element according to claim 12 or 13, wherein, in the passivation layer forming step, the passivation layer is also formed on a side surface of the semiconductor substrate.
- 請求項１乃至１１のいずれかに記載の太陽電池素子を備えている太陽電池モジュール。 A solar cell module comprising the solar cell element according to any one of claims 1 to 11.
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| JP2015144243A (en) * | 2013-12-25 | 2015-08-06 | 東京応化工業株式会社 | Method for forming surface-coating film, and solar battery having surface-coating film |
| JP2015191907A (en) * | 2014-03-27 | 2015-11-02 | 京セラ株式会社 | solar cell element |
| JP2016006869A (en) * | 2014-05-28 | 2016-01-14 | 京セラ株式会社 | Solar cell element and solar cell module |
| JP2016092424A (en) * | 2014-11-04 | 2016-05-23 | エルジー エレクトロニクス インコーポレイティド | Solar cell |
| JP2017059763A (en) * | 2015-09-18 | 2017-03-23 | シャープ株式会社 | Photoelectric conversion element and method of manufacturing the same |
| EP4002495A4 (en) * | 2019-07-19 | 2023-07-19 | Shangrao Jinko solar Technology Development Co., LTD | Solar cell and manufacturing method therefor |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2015144243A (en) * | 2013-12-25 | 2015-08-06 | 東京応化工業株式会社 | Method for forming surface-coating film, and solar battery having surface-coating film |
| JP2015191907A (en) * | 2014-03-27 | 2015-11-02 | 京セラ株式会社 | solar cell element |
| JP2016006869A (en) * | 2014-05-28 | 2016-01-14 | 京セラ株式会社 | Solar cell element and solar cell module |
| JP2016092424A (en) * | 2014-11-04 | 2016-05-23 | エルジー エレクトロニクス インコーポレイティド | Solar cell |
| JP2017059763A (en) * | 2015-09-18 | 2017-03-23 | シャープ株式会社 | Photoelectric conversion element and method of manufacturing the same |
| EP4002495A4 (en) * | 2019-07-19 | 2023-07-19 | Shangrao Jinko solar Technology Development Co., LTD | Solar cell and manufacturing method therefor |
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