WO2013097213A1 - 一种非接触式的wl/wlp芯片高温老化测试方法及装置 - Google Patents

一种非接触式的wl/wlp芯片高温老化测试方法及装置 Download PDF

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Publication number
WO2013097213A1
WO2013097213A1 PCT/CN2011/085126 CN2011085126W WO2013097213A1 WO 2013097213 A1 WO2013097213 A1 WO 2013097213A1 CN 2011085126 W CN2011085126 W CN 2011085126W WO 2013097213 A1 WO2013097213 A1 WO 2013097213A1
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Prior art keywords
test
aging
circuit
wafer
chain
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PCT/CN2011/085126
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English (en)
French (fr)
Inventor
崔小乐
李崇仁
伟程
王小兵
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北京大学深圳研究生院
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Priority to PCT/CN2011/085126 priority Critical patent/WO2013097213A1/zh
Publication of WO2013097213A1 publication Critical patent/WO2013097213A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/3025—Wireless interface with the DUT
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating

Definitions

  • the present invention relates to a wafer level burn-in test for a chip and an aging test method for a WLP (Wafer Level Package) chip. current technology
  • the chip burn test (burn in tes t) is a chip test method that applies strong stress (such as temperature, voltage, etc.) to the chip to accelerate the chip through the early failure stage and improve the reliability of the chip.
  • the high temperature aging test is an important type of aging test method, which has a significant effect on the reliability growth of chip products and has been widely used in the industry.
  • Aging furnace equipment is usually used for high temperature aging tests. It is common practice in the industry to place wafers or cut chips in an aging furnace and apply a specified ambient temperature through an aging furnace for a certain period of time.
  • the aging furnace equipment is a kind of high-power equipment, which can generally be consumed at the KW level. Therefore, the long-term use of the aging furnace equipment for the chip aging test has higher energy consumption and higher cost.
  • Wafer-level package Wafer Leve l Package
  • WLP Wafer Leve l Package
  • This patent proposes a non-contact aging test method for the wafer level aging test of the completed chip and the chip aging test of the wafer level package, which can avoid the high test cost and reduce the test probe. Test the purpose of energy consumption.
  • Patented "No Contact Wafer Level Aging" (Application No.: 200580042001. 1 , Publication No.: CN 1011605 33A)
  • a RF energy and initial test data between a test system and a wafer have been proposed.
  • Transmission, method of aging test by BIST circuit on the wafer has the following weaknesses: First, the aging test is implemented by the BIST circuit, which essentially generates a test vector from the BIST circuit to heat the circuit under test, and the initial (seed) vector data required for the BIST circuit to operate from the RF port is tested. The system is transmitted. Once the initial test vector is received from outside the wafer, the BI ST circuit generates the test vector itself, which cannot be controlled by external signals during the test.
  • each test chip is provided with a set of RF interface and BIST circuit.
  • This solution requires the same number of RF interface circuits on the wafer as the chip under test, and the occupied area on the wafer is occupied.
  • the illustration shows that the patent arranges these circuits on one side of the chip under test. The single-side arrangement of the BIST circuit used in this patent is not conducive to the homogenization of the aging temperature.
  • the present invention is directed to a wafer or wafer level package, and proposes a non-contact wafer level high temperature aging test method, which can achieve the purpose of reducing test energy consumption.
  • the present invention provides a radio frequency interface for a test system, and provides an RF test interface on the wafer, an aging circuit, an aging test vector generation and selection method, and an aging circuit arrangement method.
  • the system architecture of the present invention is illustrated in Figure 1.
  • the test system includes a main control computer, a data transmission line, and a radio frequency interface.
  • the master computer calculates the test vector and sends the test vector, test control command, and status data to the RF interface module through the data transmission line.
  • the RF interface circuit setting on the test system and the aging test cavity, the signal from the RF test interface circuit on a test system can be used to aging the aging test of multiple wafers in the test cavity. jobs.
  • the RF test interface circuit includes components such as an antenna, a PA, a mixer, a filter, a transmit power conditioner, and the like (as shown in FIG. 2).
  • the main function of the RF interface is to provide test vectors, test control commands, and energy transfer to the wafer under test.
  • the transmit power of the RF interface can be adjusted according to the actual situation of the test plan configuration.
  • the RF test interface and the aging circuit on the wafer are fabricated on a blank area on the wafer and are not electrically connected to the circuit under test.
  • the circuit architecture on the wafer for aging test purposes is shown in Figure 3.
  • the RF test interface circuit on the wafer is used to receive test vectors and test control commands from the test system, and collect RF energy, which is converted to DC for powering itself and the aging circuit.
  • the RF test interface circuit mainly includes an antenna, an LNA, a mixer, a filter, and the like, and includes a rectification and voltage stabilization circuit and a clock generation circuit for forming a DC power supply (as shown in FIG. 4).
  • the aging circuit on the wafer is implemented based on a register chain/ring or inverter chain/ring.
  • the register unit When implemented based on the register chain/loop circuit, it works in shift mode.
  • the register unit can use a D flip-flop or other type of flip-flop to connect the output of the pre-stage register to the subsequent register input to form a register chain structure. Or on the basis of the register chain, the feedback path and the register input signal selection circuit are added to form a register ring.
  • the input of the first stage register is connected to the corresponding data line of the RF test interface, so that the test vector can be obtained from the RF test interface.
  • the path selection signal of the multiplexer used by the register loop is connected to the control signal line of the RF test interface, so that the test input of the register chain can be selected according to the control command sent by the test system master computer.
  • the clock signal required by the register chain/ring is connected to the clock generator output of the RF test interface.
  • the power supply of the register chain/ring is connected to the output of the rectifier in the RF test interface, that is, the energy transmitted by the RF transmission channel is used to supply power to the circuit.
  • the register chain/loop circuit structure for the aging test is shown in Figure 5).
  • the aging circuit can also be implemented based on an inverter chain/ring.
  • the inverter chain consists of cascaded inverters, the latter stage
  • the input to the inverter is the output of the preamplifier.
  • the feedback path and the inverter input signal selection circuit are added to form an inverter ring.
  • the input of the first stage inverter is connected to the corresponding data line of the RF test interface, so that the test vector can be obtained from the RF test interface.
  • the path selection signal of the multiplexer used by the inverter ring is connected to the control signal line of the RF test interface, so that the test input of the register chain can be selected according to the control command sent by the test system host computer.
  • the power supply of the inverter chain/ring is connected to the rectifier output of the RF test interface, that is, the energy transmitted by the RF transmission channel is used to supply power to the circuit.
  • the number of stages of the inverter chain must be set to an odd number.
  • the inverter chain/loop circuit structure for the aging test is as shown in Fig. 5(b).
  • the main feature of the aging circuit is that it needs to be fabricated on the surface of the wafer by a pre-semiconductor process, or other chipless parts, and is not connected to the circuit under test on the wafer.
  • the burn-in test vector is applied from the outside of the wafer to the aging circuit on the wafer through the RF test interface.
  • the thermal characteristic of the test vector is the temperature produced by the aging circuit when a test vector is applied.
  • the thermal characteristic calculation method of the test vector is as follows: (1) Calculate the register chain/loop circuit by testing the number of bit flips in the vector, the operating frequency of the register circuit, the operating voltage, and the load capacitance. Dynamic power consumption; (2) Consider the specific gate type and process parameters used in the implementation of the register chain, calculate the static power consumption under different input conditions according to the process file; (3) Find the sum of dynamic power and static power , obtaining the total power consumption of the register chain under the test vector input; (4) calculating the degree of convergence according to the thermal resistance of the material between the register chain circuit and the chip under test, the heat sink distribution, the ambient temperature, and the like.
  • the test vector thermal characteristic calculation method is: (1) Calculate the dynamic power consumption of the inverter chain/loop circuit by testing the number of bit flips in the vector, the operating frequency, operating voltage, and load capacitance of the inverter circuit; (2) Considering the implementation of the inverter chain The specific gate type and process parameters used, and the static power consumption under different input conditions are calculated according to the process file;
  • the aging temperature according to the thermal resistance of the material between the inverter chain circuit and the chip under test, the heat sink distribution, the ambient temperature, and the like.
  • the inverter chain circuit in order to obtain continuous circuit level inversion, it is necessary to continuously apply a hopping signal to the input of the inverter input signal of the inverter chain.
  • the inverter loop circuit when the multiplexer on the feedback path is set to the output of the first-stage inverter as the output signal of the tail-stage inverter, and the number of stages of the inverter ring is odd, only at the initial When any logic level is applied at all times, the inverter loop circuit can produce continuous oscillation.
  • the arrangement of the RF test interface circuit and the aging test circuit on the wafer is mainly based on the aging target and the aging temperature calculation, and the RF test interface is based on the driving capability of the aging circuit, and can be flexibly configured under the same structure.
  • the RF test interface circuit can be configured one-to-one with the aging circuit, that is, one register chain/ring or one inverter chain/ring corresponds to one RF test interface circuit, and can also perform one-to-many configuration, that is, data of the RF test interface circuit.
  • the output, control signal output, level output, clock output, etc. are connected to a plurality of burn-in test circuits through a serial/parallel conversion circuit. The stronger the drive capability of the RF test interface, the longer the number of aging circuits that can be attached, and the longer the number of aging circuits.
  • the aging circuit on the whole wafer can be uniformly used with a register chain/loop circuit or a unified inverter chain/loop circuit, or a mixture of two aging test circuits.
  • register chain/ring based aging circuits the faster the chip aging temperature changes are required, the shorter the register chain can be used. It is generally recommended to place the RF test interface close to the edge of the wafer. If the heat generated by the single aging circuit chain is insufficient to bring the adjacent chip to the specified aging temperature, the number of aging units (registers or inverters) on the side of the tested chip or the arrangement of multiple chains may be increased. Meet the aging temperature requirements.
  • a register chain For a single chip type of wafer, in order to achieve full wafer aging temperature, a register chain can be evenly arranged around each chip. For multi-project wafers (MPW), register chains of different lengths and densities can be arranged for chip areas of different projects.
  • the invention has the advantages that: (1) the aging furnace is not needed, the test energy consumption is low, and the cost is low; (2) providing the aging circuit input vector, the number of chains, the arrangement, the working mode, the working voltage, the working frequency and the like.
  • the aging test temperature is controllable; (3)
  • the aging temperature of all the tested chips on the wafer can be made uniform by rationally arranging the aging circuit chain. (4) It is not necessary to use test probes or pogo pins for testing, and the cost is reasonable.
  • the aging circuit chain is arranged in the scribe groove. It is not necessary to modify the circuit under test as in the conventional on-chip BIST scheme, and has no effect on the area and performance of the chip under test.
  • the test vector and test control signals are dynamically applied to the wafer from the RF test interface, and the input can be dynamically adjusted according to the test conditions, thereby enhancing the controllability of the test process.
  • Figure 1 shows the test system architecture
  • Figure 2 shows the RF interface in the test chamber
  • Figure 3 shows the On Wafer test architecture
  • Figure 4 shows the On Wafer RF test interface
  • Figure 5 shows: two aging circuits (register chain/ring, inverter chain/ring);
  • Figure 6 shows several test waveforms;
  • Figure 7 is a groove isomorphic double strand
  • Figure 8 is a trough isomerized three-strand
  • Figure 9 is arranged for the purpose of uniform aging temperature
  • FIG. 10 is a heterogeneous aging circuit arrangement scheme on a wafer for MPW
  • the length of the register chain/inverter chain refers to the number of registers/inverter units in the register chain/inverter chain.
  • Circuit power consumption P is mainly composed of dynamic power consumption and static power consumption.
  • Ta is the ambient temperature
  • P is the circuit power consumption
  • Rja is the thermal resistance
  • the temperature difference between the temperature in the register chain and the chip under test can be generated. Therefore, the heat generated by the register chain located in the scribe groove can be used as a heating source for the aging test, and the chip can be supplied with an adjustable ambient temperature by thermal conduction. .
  • the aging circuit of the present invention has two modes of operation: one is a chain type, that is, the input of the first stage register/inverter is introduced by the radio frequency test interface, and the input of the post stage register/inverter is output by the pre-stage register. Provided, therefore, the power consumption of the aging circuit varies with the number of bit flips in the external test vector, thereby generating heat that acts on the chip under test.
  • the second is the ring type, that is, the input of the first stage register/inverter is provided by the output feedback of the last stage register/inverter, and the input of the other stage registers/inverters is still by the pre-stage register/inverter The output is provided.
  • the choice of the two modes can be selected by the multiplexer circuit in front of the first stage register/inverter. In general, the inverter chain can generate more level jumps than the register chain, thus having higher heat generation efficiency.
  • the register/inverter chain operation and test vector input can be dynamically adjusted based on the temperature required for the burn-in test. In the case where the operating voltage, operating frequency, and the like are constant, the power consumption of the register/inverter chain circuit is determined by the bit characteristics in the input vector.
  • the maximum operating power consumption of the register/inverter chain circuit is obtained under the vector of the register input: 10101 01010... or 0101 01010..., the second largest working power is obtained under the 11011011 0 ⁇ or 001 001001...
  • the register/inverter chain In order to produce a constant power dissipation in the register/inverter chain, first work in a chain and input the appropriate test vector. Assuming the length of the register chain is N, the register chain is initialized after N clock cycles. It can then be set to a ring and the test vector is repeated over and over. It is also possible to input the same test vector externally. If the inverter-based aging circuit does not need to wait for N clock cycles, the circuit can perform the heating function immediately after inputting the test data. If there are odd-numbered inverters in the inverter chain/ring, when set to the ring mode, the circuit can oscillate, resulting in maximum operating power consumption.
  • the aging temperature may continue to rise until it is stabilized at a certain temperature by the heat sink (Hea t s ink), and the circuit may be damaged due to the accumulation of heat. Therefore, in order to keep the aging temperature constant and the circuit from being damaged, the dynamic adjustment register/inverter test vector input is required.
  • the temperature rises rapidly select a large power vector.
  • the temperature needs to rise slowly select a smaller power vector.
  • select the 000...vector or 111...vector select the 000...vector or 111...vector and continue for a while.
  • temperature cycling can also be achieved by reasonably dynamically selecting test vector sequences.
  • the length of the register chain is related to the aging temperature change rate requirement. Since the register chain operates in a shifting manner, if the length of the register chain is long, the register temperature may change slowly. However, the circuit implementation of the long register chain scheme is less expensive, and therefore has an advantage in cost. In contrast, a shorter register chain can control faster changes in aging temperatures, facilitating temperature shocks or rapidly changing temperature cycles, but the corresponding implementation costs are increased. Therefore, specific design is required according to the requirements of the aging test.
  • Fig. 7 and Fig. 8 respectively show a configuration case of a slotted isomorphic double chain and a slotted heterogeneous triple chain.
  • the circuits produced on a single wafer are identical, and it is generally desirable to have consistent performance across all circuits.
  • the aging circuit of the same type or the same type can be evenly arranged in the horizontal and vertical scribe grooves of the wafer, and the number of registers/inverters around the chip is made as equal as possible ( As shown in Figure 9).
  • the aging test vector input on the same wafer can be achieved by providing different register/inverter chain arrangements for different types of circuits on a single wafer.
  • An aging circuit configuration scheme on an MPW wafer is illustrated in Figure 10. Therefore, the aging method proposed by the present invention can achieve the effect that the aging furnace aging method cannot achieve. Adjust the number, length, and layout of the aging circuit chains/rings until the aging test requirements are met.
  • Step 2 Circuit manufacturing and packaging
  • the RF test interface circuit, the register/inverter chain/ring, and the matching power source and ground are simultaneously fabricated in the scribe groove and the partial blank position of the wafer. Network, signal string/parallel conversion circuit, etc.
  • the multiplexer is used to output signals from the feedback signal and the RF test interface circuit. The input signal of the first stage register/inverter is selected. Input signal of the first stage register/inverter of the register/inverter, matching power supply and ground, and path selection signal of multiplexer, register chain/ring clock signal, etc. (inverter chain / The ring does not require a clock signal) to be connected to the corresponding output signal line of the RF test interface.
  • the test system's master computer transmits the prepared test vector sequence and control command sequence to the RF test interface in the aging test chamber through the data line, and sends it to the RF test interface on the wafer through the RF signal.
  • the RF test interface circuit on the wafer acquires the RF energy, the power supply voltage is formed, and the test vector is demodulated and sent to the aging circuit.
  • the aging circuit produces a controllable and adjustable aging temperature for the circuit under test until the aging test plan is completed.

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Abstract

本发明提供一种晶圆老化和晶圆级封装芯片的老化测试方法。利用晶圆制作天线、射频数据收发器、功率提取电路、老化温度产生器等电路，在老化测试***中加装相应的天线和射频收发器，并与主控计算机相连。根据老化测试要求，主控计算机产生测试和功率信号，通过天线和射频数据收发器将能量和测试数据发送到晶圆上。由晶圆上的功率提取电路将射频能量转换为直流电平，用于向老化温度产生电路提供电源。晶圆上的老化温度产生电路可以由芯片周围的反相器链/环电路或寄存器链/环电路实现，电路工作所产生的热量可加热被测芯片，实现老化测试。本发明可在同一测试架构下灵活配置测试方案，降低使用测试探针的高测试成本，且可降低测试能耗。

Description

一种非接触式的 WL/WLP芯片高温老化测试方法及装置
技术领域
本发明涉及芯片的晶圓级老化测试和 WLP (晶圓级封装） 芯片的老化测试方法。 现有技术
芯片老化测试（burn in tes t )是对芯片施加较强应力 （如温度、 电压等） 条件下的一种芯片测试方法， 用于使芯片加速通过早期失效阶段， 提高芯片的 可靠性。 高温老化测试是一类重要的老化测试方法， 对芯片产品的可靠性增长 具有显著作用， 已被工业界广泛应用。 高温老化测试通常采用老化炉设备。 工 业界一般的做法是将晶圓或已切割的芯片放置在老化炉中， 通过老化炉施加规 定的环境温度， 进行一定时间的测试。 老化炉设备是一类大功率设备， 一般能 耗在 KW级别， 因此长时间使用老化炉设备进行芯片老化测试的能耗较高， 成本 较大。
晶圓级封装（WLP: Wafer Leve l Package )技术是指在晶圓的前道工序完 成后， 直接对晶圓利用半导体工艺进行后道封装， 再切割分离成单个芯片。 WLP 不同于传统芯片封装方法， 体现了后道工艺前道化的特点， 可以在晶圓上一次 封装大量芯片， 从而大大提高封装的生产率。
本专利针对已完成芯片的晶圓级老化测试和晶圓级封装的芯片老化测试， 提出一种非接触式老化的测试方法， 可回避使用测试探针所带来的高测试成本， 并达到降低测试能耗的目的。
专利 "无接点晶圓级老化" （申请号： 200580042001. 1 , 公开号： CN 1011605 33A ) 曾提出过一种测试***与晶圓之间进行射频能量和初始测试数据 传输， 通过晶圓上的 BIST电路实现老化测试的方法。 但该方法有以下弱点： 其 一， 通过 BIST电路实现老化测试， 实质上是由 BIST电路产生测试矢量来加热 被测电路， 而 BIST电路工作所需的初始（种子） 矢量数据由射频端口从测试系 统传输而来。 一旦收到晶圓外的传来的初始测试矢量， BI ST 电路即自行产生测 试矢量， 测试过程中无法通过外界信号控制。 这种方式不易根据老化测试目标 的不同进行灵活的动态测试控制， 只能针对特定的老化测试要求进行一次性设 计， 应用扩展性受限。 其二、 每个被测芯片设置一套射频接口和 BIST电路， 这 种方案需要在晶圓上制造与被测芯片同等数量的射频接口电路， 对晶圓上空闲 面积的占用较大。 其三、 其图示显示该专利将这些电路排布于被测芯片之一侧。 该专利中所采用的 BIST电路单侧排布方式不利于老化温度的均匀化。 这些缺点 均将在本专利中给与解决。 发明的内容
本发明针对晶圓或晶圓级封装， 提出一种非接触的晶圓级高温老化测试方 法， 可达到降低测试能耗的目的。
为了实现上述目的， 本发明为测试***设置射频接口， 并提供一种晶圓上 的射频测试接口， 老化电路、 老化测试矢量产生与选择方法和老化电路排布方 法。 本发明的***架构如附图 1所示。 测试***包括主控计算机、 数据传输线、 射频接口等部分。 主控计算机计 算测试矢量， 通过数据传输线将测试矢量、 测试控制命令、 状态数据送至射频 接口模块。 测试***上的射频接口电路设置与老化测试腔内， 一个测试***上 的射频测试接口电路所发出的信号可以用于老化测试腔内多片晶圓的老化测试 工作。 射频测试接口电路包括天线、 PA、 混频器、 滤波器、 发射功率调节器等 部件（如附图 2所示）。 射频接口的主要作用在于向被测晶圓提供测试矢量、 测 试控制命令， 同时传输能量。 射频接口的发射功率可以视测试方案配置的实际 情况进行调整。 晶圓上的射频测试接口、 老化电路均制作在晶圓上的空白面积上， 不与被 测电路产生电气连接。 面向老化测试目的的晶圓上的电路架构如附图 3所示。 晶圓上的射频测试接口电路的作用为接收测试***发来的测试矢量和测试控制 命令， 并收集射频能量， 将其转换为直流， 用于对自身和老化电路供电。 射频 测试接口电路的主要包括天线、 LNA、 混频器、 滤波器等部件配置外， 还包括用 于形成直流供电电源的整流及稳压电路和时钟产生电路（如附图 4所示）。
晶圓上的老化电路基于寄存器链 /环或反相器链 /环而实现。
基于寄存器链 /环电路实现时， 采用移位方式工作。 寄存器单元可以采用 D 触发器或其它类型触发器， 将前级寄存器的输出与后继寄存器输入相连， 形成 寄存器链结构。 亦或在寄存器链的基础上， 增加反馈通路和寄存器输入信号选 择电路， 形成寄存器环。 第一级寄存器的输入与射频测试接口的对应数据线相 连， 从而可从射频测试接口获得测试矢量。 寄存器环所使用的多路选择器的通 路选择信号与射频测试接口的控制信号线相连， 从而可以根据测试***主控计 算机发来的控制命令选择寄存器链的测试输入。 寄存器链 /环所需的时钟信号与 射频测试接口的时钟产生器输出相连。 寄存器链 /环的电源与射频测试接口中整 流器输出相连， 即使用射频传输通道上传来的能量对电路进行供电。 面向老化 测试的寄存器链 /环电路结构如附图 5 )所示。
老化电路也可基于反相器链 /环实现。 反相器链由级连的反相器构成， 后级 反相器的输入为前级反相器的输出。 亦或在反相器链的基础上， 增加反馈通路 和反相器输入信号选择电路， 形成反相器环。 第一级反相器的输入与射频测试 接口的对应数据线相连， 从而可从射频测试接口获得测试矢量。 反相器环所使 用的多路选择器的通路选择信号与射频测试接口的控制信号线相连， 从而可以 根据测试***主控计算机发来的控制命令选择寄存器链的测试输入。 反相器链 / 环的电源与射频测试接口中整流器输出相连， 即使用射频传输通道上传来的能 量对电路进行供电。 为了使反相器环可在获得初始测试数据后形成振荡， 须将 反相器链的级数设置为奇数。面向老化测试的反相器链 /环电路结构如附图 5( b ) 所示。
老化电路主要特点在于需要将其通过半导体前道工序制作在晶圓表面的划线槽 ( scr ibe 1 ine )或其它无芯片部分， 且不与晶圓上的被测电路相连。 老化测试矢量通过射频测试接口由晶圓外部施加到晶圓上的老化电路。 测 试矢量的热特征是指施加某个测试矢量时， 老化电路所产生的温度。
当采用寄存器链 /环作为老化电路时， 测试矢量的热特征计算方法为： （1 )通过 测试矢量中位翻转数量， 寄存器电路的工作频率、 工作电压、 负载电容情况， 计算寄存器链 /环电路的动态功耗； （ 2 )考虑寄存器链实现时所使用的具体门电 路类型和工艺参数， 依据工艺文件计算不同输入情况下的静态功耗； （3 ) 求动 态功耗与静态功耗之和， 得到寄存器链在该测试矢量输入下的总功耗； （4 )根 据寄存器链电路到被测芯片之间材料的热阻和热沉分布、 环境温度等， 计算寄 度。
当采用反相器链 /环电路作为老化电路时， 测试矢量热特征计算方法为： ( 1 )通过测试矢量中位翻转数量， 反相器电路的工作频率、 工作电压、 负载电 容情况， 计算反相器链 /环电路的动态功耗； （2 )考虑反相器链实现时所使用的 具体门电路类型和工艺参数， 依据工艺文件计算不同输入情况下的静态功耗；
( 3 )求动态功耗与静态功耗之和，得到反相器链在该测试矢量输入下的总功耗；
( 4 )根据反相器链电路到被测芯片之间材料的热阻和热沉分布、 环境温度等， 老化温度。 对于反相器链电路， 为了获得连续的电路电平翻转， 需要连续在反 相器链的首级反相器信号输入端施加跳变的信号。 而对于反相器环电路， 当反 馈通路上的多路选择器设置为首级反相器输入为尾级反相器输出反馈信号， 且 反相器环的级数为奇数时， 只需在初始时刻施加任意逻辑电平， 反相器环电路 即可产生连续振荡。 晶圓上射频测试接口电路与老化测试电路的排布主要以老化目标和老化温 度计算、 射频测试接口对老化电路的驱动能力为依据， 可以在同一结构下灵活 配置。
射频测试接口电路可以与老化电路进行一对一配置， 即一条寄存器链 /环或 一条反相器链 /环对应一个射频测试接口电路， 也可以进行一对多配置， 即射频 测试接口电路的数据输出、 控制信号输出、 电平输出、 时钟输出等通过串 /并转 换电路， 同时与多条老化测试电路相连。 射频测试接口的驱动能力越强， 可挂 接的老化电路数量越长， 老化电路的级数越长。 全片晶圓上的老化电路可以统 一采用寄存器链 /环电路或统一采用反相器链 /环电路， 亦可混合使用两种老化 测试电路。 对于基于寄存器链 /环的老化电路， 芯片老化温度变化要求越快， 可 采用越短的寄存器链。 一般建议将射频测试接口设置在靠近晶圓边缘的位置， 若单条老化电路链所产生热量不足以使邻近的芯片达到规定的老化温度， 可以采用增加该被测芯片边长上的老化单元（寄存器或反相器）数量或多链的 排布方式， 使达到老化温度要求。
对于单一芯片种类的晶圓， 为了实现全晶圓老化温度的均勾化， 可采用在 每个芯片的四周均匀排布寄存器链的方式。 而对于多项目晶圓 （MPW ), 可以对 不同项目的芯片区域排布不同长度和密度的寄存器链。 本发明的优点在于： （1 )无需使用老化炉， 测试能耗低， 成本低； （2 )提 供老化电路输入矢量、 链数量、 排布、 工作方式、 工作电压、 工作频率等多种 手段使老化测试温度可控； （ 3 )可通过合理排布老化电路链， 使晶圓上所有被 测芯片的老化温度均匀化。 （4 )测试时无需使用测试探针或 pogo pin, 成本合 理。 （ 5 )老化电路链排布在划线槽中， 不需要象一般片上 BIST方案一样修改被 测电路， 对被测芯片的面积和性能均无影响。 （6 ) 测试矢量和测试控制信号从 射频测试接口动态施加到晶圓上， 可以根据测试情况动态调整输入， 从而增强 测试过程的可控性。 附图说明
图 1为测试***架构；
图 2为测试腔中的射频接口；
图 3为 On Wafer测试架构；
图 4为 On Wafer射频测试接口；
图 5为： 两种老化电路（寄存器链 /环、 反相器链 /环）； 图 6为几种测试波形；
图 7是一槽同构双链；
图 8为一槽异构三链；
图 9为以均匀老化温度为目的排布；
图 1 0为一种 MPW用晶圓上的异构老化电路排布方案； 具体实施方式
下面结合附图对本发明的技术方案作进一步描述。
本发明的需要按照三个主要阶段实施：
第一阶段： 方案设计
获取工艺文件、 晶圓材料参数、 晶圓布局及尺寸、 老化测试要求等信息。 计算不同长度的寄存器链 /环、 反相器链 /环在不同测试矢量下所能产生的 老化温度以及维持该老化电路工作所需的电源驱动能力。 对于寄存器链 /环构成 的老化电路， 计算时钟信号的驱动能力。 这里， 寄存器链 /反相器链的长度指寄 存器链 /反相器链中的寄存器 /反相器单元数量。
电路功耗 P主要由动态功耗、 静态功耗组成。
电路动态功耗由公式（ 1 ) 决定：
Pdyn : \ll . C . V N . f ( 1 ) 其中， V为电路工作电压， C为电路负载电容， f 为工作频率， N为电路电 平跳变数量。 电路制作完成后， 电路负载电容 C基本不可变， 电路工作电压 V、 电路工作频率 f 等参数可在一定范围内调整， 一段时间内电路电平跳变数量可 由电路输入矢量进行较大范围的控制。
对于 90nm以上工艺制造的电路， 动态功耗在总功耗中所占比例很大， 静态 功耗可忽略不计。 在 90nm及以下工艺条件下， 需根据构成寄存器链所使用的门 电路类型， 查工艺文件获得静态功耗大小。
根据动态功耗和静态功耗， 求和得到寄存器链 /环在特定测试矢量输入下的 总功耗。
寄存器传输链的工作温度由公式（2 ) 决定：
Tj=Ta+P Rja ( 2 )
其中 Ta是环境温度， P是电路功耗， Rja是热阻。
寄存器链上的温度与被测芯片之间可产生温度差， 因此位于划线槽内的寄 存器链所产生的热量可作为老化测试所需的加热源， 通过热传导方式对芯片提 供可调的环境温度。
本发明中的老化电路有两种工作方式： 其一是链式， 即第一级寄存器 /反相 器的输入由射频测试接口引入， 后级寄存器 /反相器的输入由前级寄存器的输出 提供， 因此老化电路的功耗随外部测试矢量中位翻转数量的变化而变化， 从而 产生作用于被测芯片的热量。 其二是环式， 即第一级寄存器 /反相器的输入由最 后一级寄存器 /反相器的输出反馈提供， 其它各级寄存器 /反相器的输入仍由前 级寄存器 /反相器输出提供。 两种方式的选择可由第一级寄存器 /反相器前的多 路选择器电路进行选择。 通常， 反相器链可比寄存器链产生更多的电平跳变， 因此具有更高的发热效率。
计算每个射频测试接口电路的功耗、 电源、 时钟驱动能力及面积， 确定射 频测试接口与老化电路的配置关系以及老化电路的种类与长度。 若采取一对多 的配置关系， 则需增加串 /并转换电路用于数据的多链分发。
综合晶圓上所有射频接口电路的功率要求， 调整测试***端射频测试接口的发 射功率， 以便为晶圓上的老化测试电路提供足够的驱动能力和能量。 根据老化测试要求的温度， 可以动态调整寄存器 /反相器链工作方式和测试 矢量输入。 在工作电压、 工作频率等因素均不变的情况下， 寄存器 /反相器链电 路功耗由输入矢量中的位特征决定。 寄存器 /反相器链电路的最大工作功耗在寄 存器输入为： 10101 01010…或 0101 01010…的矢量下获得， 次大工作功耗在 11011011 0···或 001 001001…矢量输入下获得， 再次大工作功耗在 110011 001100…或 00110011001 1 ···矢量下获得, 依次类推。 功耗最小的情况为 输入矢量为 000000…时，此时仅静态功耗其作用，输入矢量为 11111 1…时次之。 部分典型测试输入波形如附图 6所示。
为了使寄存器 /反相器链产生恒定的功耗， 首先工作于链式， 输入合适的测 试矢量。假设寄存器链的长度为 N,则 N个时钟周期后，寄存器链被初始化完毕。 然后可以将其设置为环式， 不断重复该测试矢量。 也可持续通过外部输入相同 的测试矢量。 若基于反相器的老化电路， 则无需等待 N个时钟周期， 该电路可 在输入测试数据后立即发挥加热功能。 若反相器链 /环中有奇数级反相器， 则设 置为环式工作方式后， 该电路可产生振荡， 产生最大的工作功耗。 老化温度可 能持续上升直至在热沉（Hea t s ink )作用下稳定于某温度， 也可能由于热量不 断累积而导致电路损坏。 因此为了使老化温度恒定并使电路不致损坏， 需要动 态调整寄存器 /反相器测试矢量输入。 需要温度快速上升时， 选择大功耗矢量。 需要温度緩慢上升时， 选择较小功耗矢量。 需要温度下降时， 选择 000…矢量或 111…矢量， 并持续一段时间。
同样， 温度循环也可通过合理动态选择测试矢量序列实现。
计算不同长度的寄存器 /反相器链的最大功耗对被测电路所产生老化温度。 若该温度大于等于规定的最高老化温度， 可通过调节测试矢量输入实现动态温 度控制。 若该温度小于规定的最高老化温度， 则需要采取多链的方案， 并重新 计算老化电路链组的功耗、 温度及对被测芯片产生的老化温度。 每个划线槽中 老化电路链的数量受限于划线槽的宽度以及老化电路的尺寸。
寄存器链的长度与老化温度变化速度要求有关。 由于寄存器链以移位方式 工作， 若寄存器链的长度很长， 可能造成寄存器温度变化较为緩慢。 但长寄存 器链方案的电路实现代价较小， 因此成本上较有优势。 与此相反， 较短的寄存 器链可以控制老化温度较快的变化， 有利于实现温度沖击或快速变化的温度循 环， 但相应的实现成本有所增加。 因此， 需要根据老化测试的要求进行具体设 计。 附图 7与附图 8分别示意一槽同构双链和一槽异构三链的配置案例情况。 通常， 一片晶圓上所生产的电路是相同的， 一般希望所有电路性能具有一致性。 为了实现晶圓的均匀老化， 可在晶圓的横向和纵向划线槽中均匀排布同种类型 或同种类型搭配的老化电路， 并尽量使芯片四周的寄存器 /反相器数量大致相等 (如附图 9所示）。
在 MPW ( Mul t i Proj ect Wafer ) 流片使用的晶圓上， 可能存在多种不同电 路， 每种电路的温度要求也可能不同。 这种情况下， 可以通过对一片晶圓上的 不同种类电路提供不同的寄存器 /反相器链排布方案来达到同一片晶圓上老化 测试矢量输入等。 一个 MPW晶圓上的老化电路配置方案示意如附图 10所示。 因 此， 本发明所提出的老化方法可以做到普通老化炉老化方法所做不到的效果。 调整老化电路链 /环的数量、 长度及布局， 直至满足老化测试要求。
在确定的老化电路链 /环的数量、 长度及布局条件下， 计算不同输入矢量对 已确定使用的寄存器 /反相器链的功耗、 温升及对被测芯片温升的作用， 获取不 同温升条件所对应的测试矢量集。 对特定老化温度测试要求， 设计老化测试计划， 内容包括测试矢量序列、 老化电路工作模式（链式或环式）、 测试矢量施加时间等。 第二步： 电路制造及封装阶段
在晶圓上制造电路图形的过程中， 按照设计在晶圓的划线槽及部分空白位 置上同时制造射频测试接口电路、 寄存器 /反相器链 /环， 以及与之匹配的电源 和地的网络、 信号串 /并变换电路等。 其中， 寄存器 /反相器环电路中， 从最后 一级寄存器 /反相器至第一级寄存器 /反相器的反馈通路上， 用多路选择器从反 馈信号和射频测试接口电路输出信号中选择出第一级寄存器 /反相器的输入信 号。 将寄存器 /反相器的第一级寄存器 /反相器的输入信号、 与之匹配的电源和 地、 以及多路选择器的通路选择信号、 寄存器链 /环时钟信号等 （反相器链 /环 无需时钟信号 ) 与射频测试接口的对应输出信号线相连。
在进行晶圓级封装时， 注意不要对射频测试接口部分进行封装， 以在封装 前后保持射频测试接口性能的一致性。
第三步， 老化测试阶段
将被测晶圓放置在测试***的老化测试腔中， 对老化测试腔端的射频测试 接口进行发射功率设置。
测试开始， 测试***的主控计算机将已经准备好的测试矢量序列和控制命 令序列通过数据线传输送到老化测试腔中的射频测试接口， 通过射频信号形式 发送到晶圓上的射频测试接口。 晶圓上的射频测试接口电路获取射频能量后， 形成供电电源电压， 并解调出测试矢量， 发送给老化电路。 随测试矢量输入动 态变化， 老化电路对被测电路产生可控可调的老化温度， 直至老化测试计划执 行完毕。

Claims

1. 基于射频测试接口和 On Wafer 老化测试电路的晶圓老化 /晶圓级封装 老化测试架构， 其特征在于： 测试***的主控计算机通过数据线与设置在老化 测试腔内的射频测试接口相连。 被测晶圓与测试***通过 On Wafer射频测试接 口相连，获取射频能量，建立供电电源，并解调出测试矢量及控制命令。 On Wafer 射频测试接口与老化电路相连， 为其提供测试矢量、 电路工作模式选择信号、 电源网络、 时钟信号等。 老化电路可以基于寄存器或反相器链 /环实现， 依据老 化测试要求进行配置， 排布于晶圓上的划线槽、 被测芯片周围的空白位置。 由 测试***端通过射频测试接口动态加载测试矢量， 控制老化电路产生工作功耗， 为被测芯片加热， 从而实现老化测试方案。
2. 测试***端的射频测试接口， 其特征在于： 包括天线、 PA、 混频器、 滤波器、 发射功率调节器等部件， 可对测试***主控计算机送来的测试矢量、 测试命令进行上变频， 以射频信号形式发送至被测晶圓。 该射频测试接口的发 射功率可根据测试配置要求进行配置， 保证被测晶圓上获得足够的能量。
3. On Wafer 的射频测试接口， 其特征在于： 包括天线、 LNA、 混频器、 调 制解调器、 滤波器等部件配置外， 还包括用于形成直流供电电源的整流及稳压 电路和时钟产生电路。 该射频测试接口的输出包括数据、 时钟、 电源、 控制命 令等， 分别与 On Wafer的老化测试电路对应相连。 该射频测试接口还可选配信 号串 /并变换电路， 用于射频测试接口与老化电路的一对多配置的情形。
4. 用于 WL/WLP老化测试的 On Wafer老化电路， 其特征在于：
老化电路可基于寄存器或反相器电路实现， 具有链式和环式两种工作模式。 将 寄存器 /反相器链通过半导体前道工艺制作在晶圓的划线槽中， 寄存器 /反相器 链中的第一级寄存器 /反相器输入、 电源、 地、 多路选择器通路选择输入、 时钟 (反相器链 /环无需时钟信号）等与射频测使接口的相应输出相连。 寄存器链以 移位方式工作， 其输入由第一级寄存器的输入确定， 通过多路选择器通路选择 输入控制寄存器链中第一级寄存器的输入。 反相器链输入由第一级反相器的输 入确定， 通过多路选择器通路选择输入控制反相器链中第一级反相器的输入。
5. 用于 WL/WLP老化测试的测试矢量集， 其特征在于：
当老化电路所产生的温升等于芯片热沉所损耗的温度时， 老化温度恒定不 变。 当老化电路产生的温升大于芯片热沉所损耗的温度时， 老化温度上升， 反 之， 老化温度下降。 根据老化测试方案 （如恒定高温试验、 温度循环试验等） 中的温升要求， 设计测试矢量与测试输入波形。 不同温升要求形成不同测试矢 量集。
6. 用于 WL/WLP的老化测试方案设计方法， 其特征在于
根据老化测试要求， 在权力要求 1 所述的总体测试架构下， 在老化电路产生温 度评估、 时钟驱动能力评估、 电源驱动能力评估的基础上， 设计以下内容：
( 1 )老化电路所用的寄存器 /反相器的大小、 长短、 工作电压、 工作频率等。
( 2 )老化电路在晶圓上的排布方式（一对一配置、 一对多配置、 单链、 多 链、 同构、 异构）
( 3 )老化电路上的输入矢量序列及工作方式（链式、 环式）。
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