WO2013089648A1

WO2013089648A1 - Capacitive micromachined ultrasonic transducer arrangement and method of fabricating the same

Info

Publication number: WO2013089648A1
Application number: PCT/SG2012/000479
Authority: WO
Inventors: Bin Guo; Jinli Qu
Original assignee: Agency For Science, Technology And Research
Priority date: 2011-12-16
Filing date: 2012-12-17
Publication date: 2013-06-20

Abstract

Various embodiments provide a capacitive micromachined ultrasonic transducer (CMUT) arrangement. The CMUT arrangement may include a substrate including a plurality of trenches formed therein; and a plurality of transducer elements. Each transducer element may include at least one transducer cell, wherein each transducer cell includes a cavity formed above a surface of the substrate and a membrane formed above the cavity. The plurality of trenches are filled with insulating material, and at least one of the plurality of trenches are doped at at least one sidewall.

Description

CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER ARRANGEMENT AND METHOD OF FABRICATING THE SAME

Cross-reference to Related Applications

[0001] The present application claims the benefit of the Singapore patent application 201109381-2 filed on 16 December 2011, the entire contents of which are incorporated herein by reference for all purposes.

Technical Field

[0002] Embodiments relate generally to ultrasonic transducers. More particularly, embodiments relate to a capacitive micromachined ultrasonic transducer (CMUT) arrangement and a method of fabricating a CMUT arrangement.

Background

[0003] Capacitive Micromachined Ultrasonic Transducers (CMUT) arrays are receiving increased attention from medical imaging device companies as well as semiconductor device companies. Compared to traditional piezoelectric ceramic based ultrasound devices, CMUT provide much wider bandwidth, better coupling to medium and potential for integration with electronics.

[0004] For CMUT arrays with large number of elements, e.g. in imaging applications, good cell-to-cell isolation and vertical connection (stacking) with IC (integrated circuit) are needed. For fully populated 2D arrays in 3D imaging, for example, the number of elements increases (e.g. for a 32x32 an-ay, there are 1024 elements) and at the same time the pitch size decreases for high frequency ultrasound, while the fill factor needs to be as large as possible (which requires narrow spacing). Traditional interconnection and routing approaches become unfeasible as the space available on the wafer surface is insufficient. CMUT-to-IC stacking is thus preferred for its vertical interconnects to address individual elements and to avoid processing on thin membranes.

[0005] To form vertical connections, current available approaches, such as through- silicon- via (TSV), is difficult to be integrated with CMUT devices and involves complex process flows. To achieve trench isolation together with TSV, the prior art uses double SOI (silicon on insulator) wafers so the resulted fabrication process is complex and costly.

[0006] Fig. 1 illustrates a hypothetical CMUT-to-IC stacking structure.

[0007] The CMUT-to-IC stacking structure 100 includes a CMUT structure 102 stacked on the IC 104, and the cells 106 of the CMUT structure 102 are connected to the IC 104 through the TSV 108 and the flip-chip bonding 110.

[0008] There are intrinsic difficulties and problems associated with the structure 100. Firstly, trench at location 112 is preferred for better cell-to-cell isolation. In addition, bonding-post-independent isolation is needed for lower parasitics and better breakdown prevention.

[0009] Secondly, it is difficult to have an etching stop at location 114 when trying to implement a traditional TSV structure in the CMUT structure 102. Traditional polysilicon or Copper based TSV is not compatible with the fusion bonding process, due to high temperature and low surface roughness in fusion bonding. [0010] Thirdly, backside alignment as shown at 116 is normally difficult and involves unique equipment, time-consuming procedure and non-batch process.

Summary

[0011] Various embodiments provide a capacitive micromachined ultrasonic transducer (CMUT) arrangement. The CMUT arrangement may include a substrate including a plurality of trenches formed therein; and a plurality of transducer elements. Each transducer element may include at least one transducer cell, wherein each transducer cell includes a cavity formed above a surface of the substrate and a membrane formed above the cavity. The plurality of trenches are filled with insulating material, and at least one of the plurality of trenches are doped at at least one sidewall.

[0012] Various embodiments provide a method of fabricating a capacitive micromachined ultrasonic transducer (CMUT) arrangement. The method may include providing a substrate; forming a plurality of trenches in the substrate; forming a doping layer at at least one side wall of at least one of the plurality of trenches; depositing insulating materials in the trenches; forming a plurality of insulating posts on a surface of the substrate, wherein the insulating posts define a plurality of cavities on the surface of the substrate; and forming a membrane, said membrane being supported on the insulating posts.

Brief Description of the Drawings

[0013] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:

Fig. 1 illustrates a hypothetical CMUT-to-IC stacking structure.

Fig. 2 shows a 2D CMUT array according to an embodiment.

Fig. 3 shows a CMUT arrangement according to an embodiment.

Fig. 4 shows a CMUT arrangement according to another embodiment.

Fig. 5 shows a flowchart illustrating a method for fabricating a CMUT arrangement according to an embodiment.

Fig. 6A-6E show a process of fabricating the CMUT arrangement according to an embodiment.

Fig. 7A-7E show a process of fabricating the CMUT arrangement according to another embodiment.

Fig. 8 shows a CMUT arrangement according to another embodiment.

Fig. 9A-9E show a process of fabricating the CMUT arrangement according to another embodiment.

Fig. 1 OA- IOC show a process of trench formation according to an embodiment.

Fig. 1 1 illustrates the performance of a CMUT arrangement according to an embodiment.

Fig. 12 shows experimental results about the trench doping and filling, and the vertical connection resistance according to an embodiment.

Fig. 13 shows experimental results according to an embodiment. Description

[0014] Various embodiments provide a simple and robust way to implement CMUT array and IC stacking, which enables the fabrication of high performance ultrasonic biomedical devices in an efficient manner. The proposed CMUT arrangement structure also allows the fabrication of CMUTs using fusion bonding technology, which is beneficial for achieving high performance transducers through better processing control and easier realization of large arrays. Various embodiments provide a vertical integration/stacking of the CMUT and IC, wherein interconnects for addressing individual transducer elements are formed and processing on think membranes is avoided.

[0015] Various features described below in the context of the CMUT arrangement may analogously hold true for the corresponding method for fabricating the CMUT arrangement, and vice versa.

[0016] One embodiment is directed to a capacitive micromachined ultrasonic transducer (CMUT) arrangement. The CMUT arrangement may include a substrate including a plurality of trenches formed therein; and a plurality of transducer elements. Each transducer element may include at least one transducer cell, wherein each transducer cell includes a cavity formed above a surface of the substrate and a membrane formed above the cavity. The plurality of trenches are filled with insulating material, and at least one of the plurality of trenches are doped at at least one sidewall.

[0017] In an embodiment, the insulating material filled in the plurality of trenches may include or may be silicon dioxide or silicon nitride. [0018] In an embodiment, the CMUT arrangement may include a plurality of insulating posts disposed on the surface of the substrate above which the cavities are formed, wherein the insulating posts are arranged to support the membrane above the cavities of the transducer cells. In an embodiment, the plurality of insulating posts may include or may be silicon dioxide or silicon nitride.

[0019] According to an embodiment, the CMUT arrangement may further include a plurality of insulating posts disposed at another surface of the substrate opposite the surface of the substrate above which the cavities are formed, wherein the insulating posts are connected to a first group of trenches selected out of the plurality of trenches.

[0020] According to an embodiment, the first group of trenches may include or may be trenches formed next to or along the perimeter of the transducer cells. In an embodiment, the first group of trenches may be formed in a rectangular shape along the perimeter of the transducer cells. In an embodiment, each of the first group of trenches may be doped (e.g. via diffusion) at only one side wall, and the other side wall closer to the perimeter of the transducer cells is not doped for insulation purposes. Accordingly, the insulating posts connected to the first group of trenches may server to isolate the selected transducer cells next to or along the perimeter of these transducer cells, to achieve cell-to-cell isolation.

[0021] In a further embodiment, the CMUT arrangement may further include a plurality of interconnects disposed at the another surface of the substrate, i.e. the another surface opposite the surface of the substrate above which the cavities are formed. The interconnects may be connected to a second group of trenches selected from the trenches being doped at the at least one side wall, wherein the second group of trenches may include or may be trenches different from the trenches of the first group of trenches.

[0022] According to an embodiment, the second group of trenches may include or may be trenches formed within the perimeter of the transducer cells. Accordingly, the transducer cells are connected to the interconnects through the second group of trenches.

[0023] In an embodiment, the CMUT arrangement may include an electronic circuit bonded to the another surface of the substrate opposite the surface of the substrate above which the cavities are formed. In an embodiment, the electronic circuit may be bonded to the plurality of interconnects disposed at the another surface of the substrate through solder bonding, for example. The interconnects may include or may be conductive material, such as metal, e.g. gold (Au).

[0024] The electronic circuit may be selected from a group consisting of a printed circuit board, an integrated circuit and a wafer.

[0025] According to an embodiment, the at least one doped sidewall of the trenches include doped polysilicon.

[0026] In an embodiment, the membrane may include a SOI wafer., or a silicon wafer.

[0027] Various embodiments described in the context of the CMUT arrangement are analogously valid for the corresponding method of fabricating a CMUT arrangement.

[0028] Another embodiment is directed to a method of fabricating a capacitive micromachined ultrasonic transducer (CMUT) arrangement. The method may include providing a substrate; forming a plurality of trenches in the substrate; forming a doping layer at at least one side wall of at least one of the plurality of trenches; depositing insulating materials in the trenches; forming a plurality of insulating posts on a surface of the substrate, wherein the insulating posts define a plurality of cavities on the surface of the substrate; and forming a membrane, said membrane being supported on the insulating posts.

[0029] It is understood that in various embodiments the method may form one or more insulating posts on the surface of the substrate to define one or more cavities, depending on the number of transducer cells to be formed. For example, if only one transducer cell is to be formed, the method may form an insulating post on the surface of the substrate to define one cavity of the transducer cell.

[0030] According to an embodiment, a transducer cell may be formed by at least one insulating post of the plurality of insulating posts, the cavity defined on the surface of the substrate, the membrane, and the substrate.

[0031] In an embodiment, the membrane may include a SOI wafer, or a silicon wafer.

[0032] In an embodiment, the insulating post may be formed as a supporting structure surrounding the cavity. In an embodiment, the insulating post may be formed via thermal oxidation, photolithography and reactive ion etching. The insulating post between adjacent transducer cells may isolate the adjacent transducer cells. In a further embodiment, the adjacent insulating posts may be connected or joined to each other, such that each insulating post may define the perimeter of a transducer cell and the connected/joined portion of adjacent insulating posts may serve to isolate adjacent transducer cells.

[0033] In an embodiment, the method may further include forming a plurality of insulating posts at another surface of the substrate opposite the surface of the substrate on which the cavities are defined, wherein the insulating posts are connected to a first group of trenches selected out of the plurality of trenches.

[0034] According to an embodiment, the first group of trenches may include or may be trenches formed next to or along the perimeter of the transducer cells. In an embodiment, the first group of trenches may be formed in a rectangular shape along the perimeter of the transducer cells. In an embodiment, each of the first group of trenches may be doped at only one side wall, and the other side wall closer to the perimeter of the transducer cells is not doped for insulation purposes. Accordingly, the insulating posts connected to the first group of trenches may server to isolate the selected transducer cells next to or along the perimeter of these transducer cells, to achieve cell-to-cell isolation.

[0035] According to an embodiment, the method may further include forming a plurality of interconnects at another surface of the substrate opposite the surface of the substrate on which the cavities are defined, wherein the plurality of interconnects are conductively connected with a second group of trenches selected from the trenches being doped at the at least one side wall. The second group of trenches includes trenches different from the trenches of the first group of trenches. In an embodiment, the interconnects may be formed via electron beam evaporation

[0036] According to an embodiment, the second group of trenches may include or may be trenches formed within the perimeter of the transducer cells. Accordingly, the transducer cells are connected to the interconnects through the second group of trenches. In an embodiment, the second group of trenches may be formed via reactive ion etching. [0037] In an embodiment, the method may include bonding an electronic circuit to said another surface of the substrate opposite the surface of the substrate on which the cavities are defined, e.g. via flip-chip bonding.

[0038] In an embodiment, the electronic circuit may be selected from a group consisting of a printed circuit board, an integrated circuit and a wafer.

[0039] According to an embodiment, forming the doping layer (e.g. via diffusion) at the at least one side wall of the at least one trench includes forming a doped polysilicon layer at the at least one side wall of the at least one trench.

[0040] Various embodiments described in the context of the method of fabricating a CMUT arrangement are analogously valid for the corresponding CMUT arrangement.

[0041] Fig. 2 shows a 2D CMUT array according to an embodiment.

[0042] The 2D CMUT array 200 may include a plurality of transducer elements 202. In an illustrative embodiment, the CMUT array 200 may include 16x16 transducer elements, i.e. 256 transducer elements, in an area of about lOmmxlOmm. Accordingly, when the CMUT array 200 is stacked on an IC, 256 connections are needed for the CMUT-IC interface.

[0043] Each transducer element 202 may include a plurality of transducer cells 204. In an illustrative example, a transducer element 202 may include 20x20 cells 204, with 30μηιχ30μΓη pitch for each cell 204 and about 2μπι spacing between adjacent transducer cells 204.

[0044] Fig. 3 shows a CMUT arrangement according to an embodiment, wherein the left part of Fig. 3 shows a top view layout of the CMUT arrangement viewing from line A-A' in the right part of Fig. 3. The right part of Fig. 3 shows a cross-sectional view of the CMtJT arrangement viewing from line B-B' in the left part of Fig. 3.

[0045] In Fig. 3, the CMUT arrangement 300 includes a substrate 302 having a plurality of trenches 304, 306 formed therein.

[0046] The CMUT arrangement 300 may include a plurality of transducer elements, wherein each transducer element may include at least one transducer cell. It is understood that the CMUT arrangement 300 may include one or more transducer elements and each transducer element may include one or more transducer cells in various embodiments. In this embodiment illustrated in Fig. 3, only one transducer element 308 and two cells 310, 312 of the transducer element 308 are shown.

[0047] Each transducer cell 310, 312 may include a cavity 314 formed above a surface of the substrate 302 and a membrane 316 formed above the cavity 314. The plurality of trenches 304, 306 are filled with insulating material, and at least one of the plurality of trenches 304, 306 are doped at at least one sidewall.

[0048] According to an embodiment, the at least one doped sidewall of the trenches 304, 306 include doped polysilicon. The membrane 316 may include a SOI wafer, and may be connected to a common GND.

[0049] The CMUT arrangement 300 may include a plurality of insulating posts 318 disposed on the surface of the substrate 302 above which the cavities 314 are formed, wherein the insulating posts 318 are arranged to support the membrane 316 above the cavities 314 of the transducer cells 310, 312. The insulating posts 318 serve as bonding posts for bonding the substrate 302 and the membrane 316, e.g. using fusion bonding. [0050] In an embodiment, the insulating posts 318 may be formed as a supporting structure surrounding the cavities 314, e.g. as the rectangular shaped supporting structure shown in the left part of Fig. 3, which may define the perimeter of the transducer cells 310, 312. The insulating post 318 between adjacent transducer cells 310, 312 may isolate the adjacent transducer cells 310, 312.

[0051] In another embodiment, the adjacent insulating posts 318 may be connected or joined to each other, e.g. at one side of the rectangular shaped insulating posts 318, as shown in the left part of Fig. 3. The connected/joined portion of adjacent insulating posts 318 may be an edge shared by adjacent insulating posts 318 as shown in Fig. 3. In this manner, each insulating post 318 may define the perimeter of a transducer cell 310, 312 and the connected/joined portion of adjacent insulating posts 318 may serve to isolate adjacent transducer cells 310, 312. In other embodiments, the adjacent edges of the adjacent insulating posts 318 may be arranged side by side or spaced apart (not shown).

[0052] In one embodiment, the entire surface of the substrate 302 above which the cavities 314 are formed may be doped, e.g. with doped polysilicon. In another embodiment, the surface of the substrate 302 above which the cavities 314 are formed may be selectively undoped to provide better isolation between adjacent transducer cells/elements. In an embodiment, the top surface of the substrate 302 where the insulating posts 318 are located may be undoped. For example, as shown in Fig. 3, at 328 where the two cells 310, 312 are isolated from each other and where the insulating post 318 is located, the top surface of the substrate 302 is undoped. The bottom surface of the substrate 302, i.e., the surface opposite the surface above which the cavities 314 are formed, is not doped due to the presence of trenches 306 for vertical connection, as shown in Fig. 3. In other embodiments not shown in Fig. 3, the bottom surface of the substrate 302 may also be doped.

[0053] According to an embodiment, the CMUT arrangement 300 may further include a plurality of insulating posts 320 disposed at another surface of the substrate 302 opposite the surface of the substrate 302 above which the cavities 314 are formed, wherein the insulating posts 320 are connected to a first group of trenches 304 selected out of the plurality of trenches 304, 306. Different from the insulating posts 318 which also serve as bonding posts for bonding the substrate 302 and the membrane 316, the insulating posts 320 provide bonding-post-independent thick dielectric for break-down prevention and parasitic capacitance reduction.

[0054] According to an embodiment, the first group of trenches 304 may include or may be trenches formed next to or along the perimeter of the transducer cells 310, 312. In an embodiment, the first group of trenches 304 may be formed in a rectangular shape along the perimeter of the transducer cells 310, 312, as shown in the left part of Fig. 3. In an embodiment as shown in Fig. 3, each of the first group of trenches 304 may be doped at both side walls. In another embodiment (not shown), each of the first group of trenches 304 may be doped at only one side wall, and the other side wall closer to the perimeter of the transducer cells 310, 312 is not doped for better isolation between the transducer cells 310, 312. The insulating posts 320 in connection with the first group of trenches 304 filled with insulating material may serve to isolate the transducer cells 310, 312 next to or along the perimeter of these transducer cells, to achieve cell-to-cell isolation. The first group of trenches 304 with side-wall doping and insulating filling may be referred to as isolation trenches. [0055] In a further embodiment, the CMUT arrangement 300 may further include a plurality of interconnects 322 disposed at the another surface of the substrate 302, i.e. the another surface opposite the surface of the substrate 302 above which the cavities 314 are formed. The interconnects 322 may be connected to a second group of trenches 306 selected from the trenches 304, 306 being doped at the at least one side wall. The second group of trenches 306 may include or may be trenches different from the trenches of the first group of trenches 304.

[0056] According to an embodiment, the second group of trenches 306 may include or may be trenches formed within the perimeter of the transducer cells 310, 312. In an embodiment, the second group of trenches 306 may be doped at one or both side walls, and may be referred to as feed-through having side-wall doping and insulating filling. Accordingly, the transducer cells 310, 312 are connected to the interconnects 322 through the second group of trenches 306.

[0057] As shown in Fig. 3, the two cells 310, 312 are respectively connected to the interconnects 322, and are isolated from each other at 328 which provides electrically floating or grounded cell-to-cell independent isolation for low parasitic capacitance. The isolation at 328 may be grounded to provide shielding for cross-talking suppression.

[0058] Fig. 4 shows a CMUT arrangement according to another embodiment. The top part of Fig. 4 shows a top view layout of the CMUT arrangement viewing from line A-A' in the bottom part of Fig. 4. The bottom part of Fig. 4 shows a cross-sectional view of the CMUT arrangement viewing from line B-B' in the top part of Fig. 4.

[0059] The CMUT arrangement 400 in Fig. 4 is similar to the CMUT arrangement 300 of Fig. 3, but shows more than one transducer elements. [0060] The CMUT arrangement 400 includes a substrate 302 having a plurality of trenches 304, 306 formed therein. The CMUT arrangement 400 further includes a plurality of transducer elements 308, 408, wherein each transducer element 308, 408 may include at least one transducer cell. In this embodiment illustrated in Fig. 4, two transducer elements 308, 408 are shown, wherein two cells 310, 312 of the transducer element 308 and two cells 410, 412 of the transducer element 408 are shown. In an example, each transducer cell 310, 312, 410, 412 may have a length of about 28μηι.

[0061] Similar to the CMUT arrangement 300 of Fig. 3, each transducer cell 310, 312, 410, 412 of the CMUT arrangement 400 may include a cavity 314 formed above a surface of the substrate 302 and a membrane 316 formed above the cavity 314. The cavities 314 may be a vacuum gap having a height of about ΙΟΟθΑ. The membrane 316 may be a SOI wafer, and may be connected to a common GND. In an example, the membrane 316 may have a thickness of about 2-3 μιη..

[0062] The plurality of trenches 304, 306 are filled with insulating material, and at least one of the plurality of trenches 304, 306 are doped at at least one sidewall. According to an embodiment, the at least one doped sidewall of the trenches 304, 306 include doped polysilicon.

[0063] The CMUT arrangement 400 may include a plurality of insulating posts 318 disposed on the surface of the substrate 302 above which the cavities 314 are formed, wherein the insulating posts 318 are arranged to support the membrane 316 above the cavities 314 of the transducer cells 310, 312. In an example, the width of the insulating posts 318 may be about 2μηι. The insulating posts 318 serve as bonding posts for bonding the substrate 302 and the membrane 316, e.g. using fusion bonding. [0064] In an embodiment, the insulating posts 318 may be formed as a supporting structure surrounding the cavities 314, e.g. as the rectangular shaped supporting structure shown in Fig. 4, which may define the perimeter of the transducer cells 310, 312, 410, 412. The insulating post 318 between adjacent transducer cells 310, 312, 410, 412 may isolate the adjacent transducer cells 310, 312.

[0065] In another embodiment, the adjacent insulating posts 318 may be connected or joined to each other, e.g. at one side of the rectangular shaped insulating posts 318, as shown in Fig. 4. The connected/joined portion of adjacent insulating posts 318 may be an edge shared by adjacent insulating posts 318 as shown in Fig. 4. In this manner, each insulating post 318 may define the perimeter of a transducer cell 310, 312, 410, 412 and the connected/joined portion of adjacent insulating posts 318 may serve to isolate adjacent transducer cells 310, 312. In other embodiments, the adjacent edges of the adjacent insulating posts 318 may be arranged side by side or spaced apart (not shown).

[0066] In one embodiment, the entire surface of the substrate 302 above which the cavities 314 are formed may be doped, e.g. with doped polysilicon. In another embodiment, the surface of the substrate 302 above which the cavities 314 are formed may be selectively undoped to provide better isolation between adjacent transducer cells/elements. In an embodiment, the top surface of the substrate 302 where the insulating posts 318 are located may be undoped. For example, as shown in Fig. 4, at 428 where the two cells 312, 410 are isolated from each other and where the insulating post 318 is located, the top surface of the substrate 302 is undoped. The bottom surface of the substrate 302, i.e., the surface opposite the surface above which the cavities 314 are formed, is not doped due to the presence of trenches 306 for vertical connection, as shown in Fig. 4. In other embodiments not shown in Fig. 4, the bottom surface of the substrate 302 may also be doped.

[0067] Similar to the CMUT arrangement 300, the CMUT arrangement 400 may further include a plurality of insulating posts 320 disposed at another surface of the substrate 302 opposite the surface of the substrate 302 above which the cavities 314 are formed, wherein the insulating posts 320 are connected to a first group of trenches 304 selected out of the plurality of trenches 304, 306. Different from the insulating posts 318 which also serve as bonding posts for bonding the substrate 302 and the membrane 316, the insulating posts 320 provide bonding-post-independent thick dielectric for breakdown prevention and parasitic capacitance reduction.

[0068] The first group of trenches 304 may include or may be trenches formed next to or along the perimeter of the transducer cells 310, 312, 410, 412. In an embodiment as shown in Fig. 4, each of the first group of trenches 3,04 may be doped at only one side wall, and the other side wall closer to the perimeter of the transducer cells 310, 312, 410, 412 is not doped for better insulation. In another embodiment not shown in Fig. 4, both side walls of the first group of trenches 304 are doped. The first group of trenches 304 with side-wall doping and insulating filling may be referred to as isolation trenches.

[0069] The CMUT arrangement 400 may further include a plurality of interconnects 322 disposed at the another surface of the substrate 302, i.e. the another surface opposite the surface of the substrate 302 above which the cavities 314 are formed. The interconnects 322 may include electrically conductive material, such as metal or other suitable conductive material. The interconnects 322 may be connected to a second group of trenches 306 selected from the trenches 304, 306 being doped at the at least one side wall. The second group of trenches 306 may include or may be trenches different from the trenches of the first group of trenches 304. According to an embodiment, the second group of trenches 306 may include or may be trenches formed within the perimeter of the transducer cells 310, 312, 410, 412. In an embodiment, the second group of trenches 306 may be doped at one or both side walls, and may be referred to as feed-through having side-wall doping and insulating filling. Accordingly, the transducer cells 310, 312, 410, 412 are connected to the interconnects 322 through the second group of trenches 306.

[0070] In an embodiment, the CMUT arrangement 400 may include an electronic circuit 424 bonded to the another surface of the substrate 302 opposite the surface of the substrate 302 above which the cavities 314 are formed. In an embodiment, the electronic circuit 424 may be bonded to the plurality of interconnects 322 disposed at the another surface of the substrate 302 through solder balls 426. The electronic circuit 424 may be an integrated circuit 424 , for example.

[0071] As shown in Fig. 4, the two transducer elements 308, 408 are respectively connected to the IC 424, and are isolated from each other at 428 which provides electrically floating or grounded cell-to-cell independent isolation for low parasitic capacitance.

[0072] Fig. 5 shows a flowchart illustrating a method of fabricating a CMUT arrangement according to an embodiment.

[0073] At 502, a substrate is provided. The substrate may include a silicon wafer or a SOI wafer, and may be referred as a device wafer in this description.

[0074] At 504, a plurality of trenches are formed in the substrate. [0075] At 506, a doping layer is formed at at least one side wall of at least one of the plurality of trenches.

[0076] At 508, insulating materials are deposited in the trenches.

[0077] At 510, a plurality of insulating posts are formed on a surface of the substrate, wherein the insulating posts define a plurality of cavities on the surface of the substrate.

[0078] At 512, a membrane is formed, said membrane being supported on the insulating posts. The membrane may be a SOI wafer.

[0079] The method of Fig. 5 may be used to fabricate the CMUT arrangements 300, 400 described above.

[0080] The CMUT arrangements 300, 400 may be fabricated uses four masks to achieve the stacking of CMUT with IC. Only the device wafer (also referred to as prime wafer), i.e. the substrate described above, is patterned, which eliminates the complex process flow of double wafer processing. The backside alignment is automatically achieved by the through silicon trenches in the device wafer. For an embodiment wherein the size of transducer cells is about 30- 50μηι, the CMUT arrangements according to various embodiments above provide a connection resistance of about 2Ω to 4Ω per cell. The expected connection capacitance is around 10% of the device capacitance for a polysilicon trench filling. Compared with existing approaches involving complicated process flow for integrating double SOI wafers and TSV, the method of -various embodiments uses a simple and easy-to-implement process flow and the CMUT arrangement fabricated according to various embodiments provide a performance comparable with existing CMUT devices. [0081] The CMUT arrangements of various embodiments use side-wall-doped deep trenches with insulating filling for both cell-to-cell isolation and electrical connection. The bonding-post-independent isolation, i.e. the insulating posts 320 in Fig. 3 and 4, provides break-down prevention and low parasitic capacitance. Vertical connection and cell-to-cell isolation are fonned before wafer bonding and thinning, which largely increases the robustness of the structure during fabrication. In addition, only the device wafer is patterned, and the backside alignment is automatically achieved by the exposed trenches. These features help to simplify the fabrication process.

[0082] In accordance with various embodiments, the CMUT arrangements 300, 400 may be made by fusion bonding of a pre-patterned device wafer and a SOI wafer.

[0083] Deep trenches may be opened from the front side of the device wafer, and these trenches may be doped to form side-wall vertical connection which is used for contact to IC later. The doping can be made blankly, over the wafer surface, or can be done locally on selected trenches and side walls.

[0084] Insulating materials are filled into the deep trenches, and form isolation between neighboring transducer cells. The filling of the insulating material needs to be conformal. The insulating material are selected such that it can withstand the high temperature during fusion bonding.

[0085] Before fusion bonding to the front side of the SOI wafer, the CMUT cavities are patterned on the front side of the device wafer. The depth of the cavity needs to be well controlled and may be achieved by dry oxidation. [0086] After bonding, the handle of the SOI wafer is removed and the SOI device layer forms a thin membrane on the CMUT cavities. This membrane can vibrate and generate ultrasound waves when electrical actuation is added on the CMUT transducers.

[0087] The backside of the device wafer is then thinned to expose the doped trenches. On the exposed trenches, passivation and metal interconnection metallization are formed to finish the CMUT transducers. The passivation layer may be customized, and may be thick to prevent breakdown and to reduce parasitic capacitance. The silicon island between adjacent transducer cells from two neighboring transducer elements is electrically isolated from the CMUT devices, and can provide low parasitic capacitance.

[0088] Finally, flip-chip bonding is used to stack the CMUT array to an IC chip or a wafer, which will also form the vertical electrical connection between the CMUT an-ay and the IC chip/wafer.

[0089] The detailed processes for fabricating the CMUT arrangements 300, 400 are described below with reference to Figs. 6 and 7.

[0090] Fig. 6A-6E show a process of fabricating the CMUT arrangement 300, 400 according to an embodiment.

[0091] In Fig. 6A, a first mask is used for forming isolation trenches. On the silicon wafer 602, deep trenches 604 are opened, e.g. via Si DRIE (Deep Reactive-Ion Etching) and are doped (e.g. via diffusion) at the side walls 606 for electrical feed-through. The doping can be carried out over the surface of the wafer 602, or may be carried out locally on the side walls of selected trenches 604. The surface of the wafer 602 may be selectively undoped, for example, at the location where isolation posts 612 are to be formed in Fig. 6B below. Pad oxidation is then formed, and a layer of nitride 608 (e.g. Si3 ₄) is deposited, e.g. via LPCVD (low pressure chemical vapor deposition).

[0092] Insulating material 610, such as TEOS (Tetraethyl orthosilicate) and/or polysilicon, may be filled into the deep trenches 604, e.g., via LPCVD. Recess may be formed via CMP (chemical mechanical polishing/planarization) or dry etch back.

[0093] In Fig. 6B, a second mask is used for cavity formation. The nitride layer 608 and the pad oxide may be stripped. Oxidation and patterning may be then performed to form the insulating posts 612 and to form the cavities 614 with a predetei-mined thickness, e.g. ΙΟΟθΑ.

[0094] In Fig. 6C, a silicon wafer 616 is bonded to the front side of the silicon wafer 602, e.g. on the insulating posts 612. The handle of the silicon wafer 616 may be optionally removed.

[0095] In Fig. 6D, a temporary bonding is performed to glue the silicon wafer 616 with a temporary handle wafer 620 through an adhesive layer 618. Then, grinding and polishing are carried out to thin the backside of the silicon wafer 602, thereby exposing the doped trenches 604. The thinned silicon wafer 602 may have a thickness of about 20- 80μηι.

[0096] In Fig. 6E, a third mask is used for passivation and a fourth mask is used for metallization. Passivation is carried out to form the insulating posts 622 being connected with a first group of selected trenches. Metallization (e.g. via electron beam evaporation) is carried out to form the interconnects 624 (also referred to as feed-through) being connected with a second group of selected trenches. [0097] The CMUT arrangement 300 of Fig. 3 may be formed according to the process of Fig. 6A - 6E. This CMUT arrangement may be stacked onto an electronic circuit, such as an IC, through flip-chip bonding. The CMUT arrangement 400 of Fig. 4 may be formed similarly.

[0098] Fig. 7A-7E shows a process of fabricating the CMUT arrangement 300, 400 according to another embodiment, which uses double SOI.

[0099] In Fig. 7A, a first mask is used for forming isolation trenches. On the SOI wafer 702, deep trenches 704 are opened, e.g. via Si DRIE (Deep Reactive-Ion Etching) and are doped (e.g. via diffusion) at the side walls 706 for electrical feed-through. The doping can be carried out over the surface of the SOI wafer 702, or may be carried out locally on the side walls of selected trenches 704. The surface of the wafer 702 may be selectively undoped, for example, at the location where isolation posts 712 are to be formed in Fig. 7B below. Pad oxidation is then formed, and a layer of nitride 708 (e.g. S13N4) is deposited, e.g. via LPCVD (low pressure chemical vapor deposition).

[00100] Insulating material 710, such as TEOS (Tetraethyl orthosilicate) and/or polysilicon, may be filled into the deep trenches 704, e.g., via LPCVD. Recess may be formed via CMP (chemical mechanical polishing/planarization) or dry etch back.

[00101] In Fig. 7B, a second mask is used for cavity formation. The nitride layer 708 and the pad oxide may be stripped (e.g. via reactive ion etching). Oxidation and patterning may be then performed to form the insulating posts 712 and to form the cavities 714 with a predetermined thickness, e.g. IOOOA.

[00102] In Fig. 7C, oxidation is carried out, and a SOI wafer 716 is bonded to the front side of the SOI wafer 702, e.g. on the insulating posts 712. The handle of the SOI wafer 716 may be optionally removed. The oxidation is used to form electrical insulating layer between the SOI wafer 716 and the SOI wafer 702 to avoid potential electrical short circuit during operation.

[00103] In Fig. 7D, a temporary bonding is performed to glue the SOI wafer 716 with a temporary handle wafer 720 through an adhesive layer 718. Then, grinding is carried out, and the bottom handle of SOI wafer 702 is removed. The SOI wafer 702 may have a thickness of about 20-40μπι after handle removal.

[00104] In Fig. 7E, a third mask is used for passivation and a fourth mask is used for metallization. Passivation (e.g. S13N4 deposition) is carried out to form the insulating posts 722 being connected with a first group of selected trenches. Metallization (e.g. Au deposition) is carried out to form the interconnects 724 (also referred to as feed-through) being connected with a second group of selected trenches.

[00105] The CMUT arrangement 300 of Fig. 3 may be formed according to the process of Fig. 7A - 7E.

[00106] Fig. 8 shows a CMUT arrangement according to another embodiment, wherein the left part of Fig. 8 shows a top view layout of the CMUT arrangement viewing from line A-A' in the right part of Fig. 8. The right part of Fig. 8 shows a cross- sectional view of the CMUT arrangement viewing from line B-B' in the left part of Fig. 8.

[00107] In Fig. 8, the CMUT arrangement 800 includes a substrate 802 having a plurality of trenches 804 and one or more through- silicon- via (TSV) 806 formed therein. The TSV 806 may be referred to as feed-through for electrical connection. [00108] The CMUT arrangement 800 may include one or more transducer elements, wherein each transducer element may include one or more transducer cells. In this embodiment illustrated in Fig. 8, only one transducer element 808 and two cells 810, 812 of the transducer element 808 are shown.

[00109] Each transducer cell 810, 812 may include a cavity 814 formed above a surface of the substrate 802 and a membrane 816 formed above the cavity 814. The plurality of trenches 804 are filled with insulating material, and at least one of the plurality of trenches 804 are doped at at least one sidewall. According to an embodiment, the at least one doped sidewall of the trenches 804 include doped polysilicon. In the embodiment shown in Fig. 8, the entire surface of the substrate 802 above which the cavities 814 are formed is doped, e.g. with doped polysilicon. In other embodiments, the surface of the substrate 802 may be selectively undoped. The bottom surface of the substrate 802 opposite to the surface above which the cavities 814 are formed may be undoped, or may be doped depending on the process flow and design requirement.

[00110] In an embodiment, the surface of the substrate 802 facing the cavities 814 may also be doped. The membrane 816 may include a SOI wafer, and may be connected to a common GND.

[00111] In each transducer element 808 according to the embodiment of Fig. 8, a TSV 806 is formed to provide vertical connection by side-wall doping, and an isolation trench 804 is formed along the perimeter of the transducer element 808 to provide isolation between adjacent transducer elements.

[00112] The CMUT arrangement 800 may include a plurality of insulating posts 818 disposed on the surface of the substrate 802 above which the cavities 814 are formed, wherein the insulating posts 818 are arranged to support the membrane 816 above the cavities 814 of the transducer cells 810, 812. The insulating posts 818 serve as bonding posts for bonding the substrate 802 and the membrane 816, e.g. using fusion bonding.

[00113] In an embodiment, the insulating posts 818 may be formed as a supporting structure surrounding the cavities 814, e.g. as the rectangular shaped supporting structure shown in the left part of Fig. 8, which may define the perimeter of the transducer cells 810, 812. The insulating post 818 between adjacent transducer cells 810, 812 may isolate the adjacent transducer cells 810, 812.

[00114] In another embodiment, the adjacent insulating posts 818 may be connected or joined to each other, e.g. at one side of the rectangular shaped insulating posts 818, as shown in the left part of Fig. 8. The connected/joined portion of adjacent insulating posts 818 may be an edge shared by adjacent insulating posts 818 as shown in Fig. 8. In this manner, each insulating post 818 may define the perimeter of a transducer cell 810, 812 and the connected/joined portion of adjacent insulating posts 818 may serve to isolate adjacent transducer cells 810, 812. In other embodiments, the adjacent edges of the adjacent insulating posts 818 may be arranged side by side or spaced apart (not shown).

[00115] According to an embodiment, the CMUT arrangement 800 may further include a plurality of insulating posts 820 disposed at another surface of the substrate 802 opposite the surface of the substrate 802 above which the cavities 814 are formed, wherein the insulating posts 820 are connected to the trenches 804. Different from the insulating posts 818 which also serve as bonding posts for bonding the substrate 802 and the membrane 816, the insulating posts 820 provide bonding-post-independent thick dielectric for break-down prevention and parasitic capacitance reduction. [00116] According to an embodiment, the trenches 804 may include or may be trenches formed next to or along the perimeter of the transducer cells 810, 812. In an embodiment, the trench 804 for each transducer element 808 may be formed in a rectangular shape outside the perimeter of the transducer cells 810, 812, as shown in the left part of Fig. 8. The trench 804 may be doped at one or both side walls. The insulating posts 820 in connection with the trench 804 filled with insulating material may server to isolate the transducer element 808 from its adjacent transducer elements.

[00117] In a further embodiment, the CMUT arrangement 800 may further include one or more interconnects 822 disposed at the another surface of the substrate 802, i.e. the another surface opposite the surface of the substrate 802 above which the cavities 814 are formed. The interconnects 822 may be connected to the TSV 806 being doped at the at least one side wall. The TSV 806 is used for vertical connection to an IC stacked to the backside of the CMUT arrangement 800.

[00118] According to an embodiment, the TSV 806 may be formed within the perimeter of the transducer cell 812. In an embodiment, the TSV 806 may be doped at one or both side walls. Accordingly, the transducer cells 810, 812 are connected to the interconnects 822 through the TSV 806.

[00119] Fig. 9A-9E show a process of fabricating the CMUT arrangement 800 according to an embodiment. The process of Fig. 9A-9E and the CMUT arrangement 800 fabricated by the process simplifies the isolation and via opening, and can be used as an easy-to-implement prototyping flow.

[00120] In Fig. 9A, a first mask is used for forming isolation trenches and TSV. On the silicon wafer 902, trenches 904 are opened, e.g. via Si DRIE (Deep Reactive-Ion Etching) and are doped (e.g. via diffusion) at the side walls 906 for electrical feed- through. The doping can be carried out over the surface of the wafer 902, or may be earned out locally on the side walls of selected trenches 904. Pad oxidation is then formed, and a layer of nitride 908 (e.g. Si₃ 4) is deposited, e.g. via LPCVD (low pressure chemical vapor deposition).

[00121] Insulating material 910, such as TEOS (Tetraethyl orthosilicate) and/or polysilicon, may be filled into the trenches 904, e.g., via LPCVD. Recess may be formed via CMP (chemical mechanical polishing/planarization) or dry etch back.

[00122] In Fig. 9B, a second mask is used for cavity formation. The nitride layer 908 and the pad oxide may be stripped (e.g. via reactive ion etching). Oxidation and patterning may be then performed to form the insulating posts 912 and to form the cavities 914 with a predetermined thickness, e.g. ΙΟΟθΑ.

[00123] In Fig. 9C, oxidation is performed, and a silicon wafer 916 is bonded (e.g. via fusion bonding) to the front side of the silicon wafer 902, e.g. on the insulating posts 912. The handle of the silicon wafer 916 may be optionally removed.

[00124] In Fig. 9D, a temporary bonding is performed to glue the silicon wafer 916 with a temporary handle wafer 920 through an adhesive layer 918. Then, grinding is carried out to thin the backside of the silicon wafer 902, thereby exposing the doped trenches 904 and the TSV 906 with doped side walls. The thinned silicon wafer 902 may have a thickness of about 20-80μιη.

[00125] In Fig. 9E, a third mask is used for passivation and a fourth mask is used for metallization. Passivation (e.g. via thermal oxidation) is carried out to form the insulating posts 922 being connected with the trenches 904. Metallization (e.g. via Au deposition) is earned out to form the interconnects 924 (also referred to as feed-through) being connected with the TSV 906.

[00126] The CMUT arrangement 300 of Fig. 3 may be formed according to the process of Fig. 9A - 9E. The CMUT arrangement 400 of Fig. 4 may be formed similarly.

[00127] Fig. lOA-lOC show a process of trench formation according to an embodiment. The process in Fig. 1 OA- IOC can be used to form the trenches in Figs. 6A- 6E, 7A-7E and 9A-9E above.

[00128] In Fig. 10A, on the silicon wafer 1002, trenches 1004 are opened, e.g. via Si DRIE (Deep Reactive-Ion Etching) and are doped (e.g. via diffusion) at the side walls 1006 for electrical feed-through. The doping can be carried out over the surface of the wafer 1002, or may be carried out locally on the side walls of selected trenches 1004. A layer of nitride 1008 (e.g. Si₃N₄) is deposited, e.g. via LPCVD (low pressure chemical vapor deposition).

[00129] In Fig. 10B, insulating material 1010, such as TEOS (Tetraethyl orthosilicate) or polysilicon, may be filled into the trenches 1004, e.g., via LPCVD. In an embodiment, the trenches 1004 are filled with insulating material 1010 such that no void exists in the trenches 1004. In another embodiment, at least part of the trenches 1004 is fully filled with insulating material 1010. CMP (chemical mechanical polishing/planarization) and/or dry/wet etching may be used for surface planarization.

[00130] In Fig. IOC, the nitride layer 1008 is stripped to expose the recess 1004 and the top surface of the substrate 1002 which may have been doped.

[00131] Fig. 11 illustrates the performance of a CMUT arrangement according to an embodiment. In this embodiment, theoretical calculations are conducted to analyze the performance of the CMUT structure 300, in particular, to analyze the connection resistance and capacitance of the vertical interconnection/isolation.

[00132] In the performance analysis, it is assumed that the width of the TSV (e.g. the first group of trenches 304) and the trenches (e.g. the second group of trenches 306) is about 2μηι, the thickness of the silicon substrate (i.e. the device wafer 302) is about 50 μιτι, the width of the bonding oxide post 318 is about 2 μπι, the trench-post spacing is about 2 μηι, and the TSV-trench spacing is about 2 μιη.

[00133] For fixed trench width, Si substrate thickness and bonding oxide post width, when the transducer cell size increases, the ratio between the connection resistance and the device impedance increases but stays within a very small range (<0.015%). On the other hand, the ratio between the connection capacitance (C_len_ch) ^an<^ the device capacitance decreases as the cell size increases. Sheet resistance is about 1.28Ω, as represented by "Doping Rc = 1.28" in Fig. 1 1.

[00134] Fig. 12 shows experimental results 1200 about the trench doping and filling, and the vertical connection resistance.

[00135] As shown in the left part of Fig. 12, deep trench etching, doping and filling have been carried out successfully. Around 50μηι deep trenches are etched and then doped by gas phase diffusion doping. Dielectrics and polysilicon are then deposited to fill up the trenches. Vertical connection resistance is measured using test structures shown in the top-right part of Fig. 12. Two probes are places on two pieces of silicon surfaces isolated by the doped deep trenches. The total resistance including the contact resistance between the probe and Silicon agrees well with the calculated result shown in Fig. 11. Results of "Center 1" and "Center2" correspond to the situation that celll and cell2 are located on the center of the wafer under testing. Results of "Edgel" and "Edge2" correspond to the situation that celll and cell2 are located on the edge of the wafer under testing.

[00136] Fig. 13 shows experimental results 1300 according to an embodiment.

[00137] In Fig. 13, doping is performed by diffusion using POCl₃ based dopant source, under the temperature of about 1050°C in a duration of about 2 hours. Fig. 13 shows that the impurity concentration decreases when the substrate depth increases.

[00138] Various embodiments produce a CMUT arrangement using fusion bonding, wherein vertical connection is provided by doped trenches. Various embodiments use four masks for fabrication process, wherein only the prime device wafer is patterned and automatic backside alignment is achieved. In accordance with an embodiment, the CMUT arrangement having a frequency of 50MHz is fabricated, wherein the width of oxide post is Ιμιη or 5μιη. In an embodiment, transducer element of about 600μπι is produced. For transducer cell size of 30μηι, the connection resistance is less than 3.80 per cell. For transducer cell size of 50μηι, the connection resistance is less than 2.30 per cell. For trenches with polysilicon filling, the ratio between connection capacitance and device capacitance is about 9.3%; and for trenches with oxide filling, the ratio between connection capacitance and device capacitance is about 3.5%. The CMUT arrangement of various embodiments has independent isolation and achieves low parasitic capacitance.

[00139] Various embodiments provide an easy-to-implement CMUT and IC stacking structure, which provides cell-to-cell isolation and vertical feedthrough but requires no processing on thin membranes. The CMUT arrangement of the embodiment is at least partially morphologically demonstrated and verified by electrical test. The experimental results show that the CMUT arrangement of the embodiment can provide very small vertical connection resistance. In addition, from theoretical analysis, the CMUT arrangement of the embodiment can also provide low connection capacitance. Thus, various embodiments enable the fabrication of high performance ultrasonic biomedical devices in an efficient manner and is expected to be useful in the mass production of such CMUT based ultrasound devices.

[00140] Various embodiments above provide structures for Capacitive Ultrasonic Transducers (CMUT) array and IC vertical integration (stacking). Compared with existing approaches involving complex and costly through- Si- via and double SOI wafers processing to achieve CMUT and IC stacking, various embodiments above provide a simple and robust method and structure. The CMUT structure of various embodiments apply side-wall-doped deep trenches with insulating filling for cell-to-cell isolation and electrical connection. At the same time, bonding-post-independent isolation provides break-down prevention and low parasitic capacitance. The CMUT transducers can be made by fusion bonding of a pre-patterned device wafer and a SOI wafer. The device wafer is processed with deep trenches opened from the front side. After wafer thinning back-side alignment is automatically achieved by the exposed trenches, which simplifies the process flow and increase its robustness. Stacking to IC chip or wafer can then be achieved by flip-chip solder bonding. Therefore, an easy-to-implement and yet effective CMUT-to-IC stacking is achieved by various embodiment.

[00141] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

Claims What is claimed is:

1. A capacitive micromachined ultrasonic transducer (CMUT) arrangement, comprising

a substrate comprising a plurality of trenches formed therein; and

a plurality of transducer elements, each transducer element comprising at least one transducer cell, wherein each transducer cell comprises a cavity formed above a surface of the substrate and a membrane formed above the cavity;

wherein the plurality of trenches are filled with insulating material, and at least one of the plurality of trenches are doped at at least one sidewall.

2. The capacitive micromachined ultrasonic transducer arrangement of claim 1, further comprising:

a plurality of insulating posts disposed on the surface of the substrate above which the cavities are formed, wherein the insulating posts are arranged to support the membrane above the cavities of the transducer cells.

3. The capacitive micromachined ultrasonic transducer arrangement of claim 1 or 2, further comprising: a plurality of insulating posts disposed at another surface of the substrate opposite the surface of the substrate above which the cavities are formed, wherein the insulating posts are connected to a first group of trenches selected out of the plurality of trenches.

4. The capacitive micromachined ultrasonic transducer arrangement of claim 3, wherein the first group of trenches comprises trenches formed next to or along the perimeter of the transducer cells.

5. The capacitive micromachined ultrasonic transducer arrangement of claim 3 or 4, further comprising:

a plurality of interconnects disposed at the another surface of the substrate, wherein the interconnects are connected to a second group of trenches selected from the trenches being doped at the at least one side wall, the second group of trenches comprising trenches different from the trenches of the first group of trenches.

6. The capacitive micromachined ultrasonic transducer arrangement of claim 5, wherein the second group of trenches comprises trenches formed within the perimeter of the transducer cells.

7. The capacitive micromachined ultrasonic transducer arrangement of any one of claims 1 to 6, further comprising: an electronic circuit bonded to another surface of the substrate opposite the surface of the substrate above which the cavities are formed .

8. The capacitive micromachined ultrasonic transducer arrangement of claim 7, wherein the electronic circuit is selected from a group consisting of a printed circuit board, an integrated circuit and a wafer.

9.. The capacitive micromachined ultrasonic transducer arrangement of any one of claims 1 to 8,

wherein the at least one doped sidewall of the trenches comprises doped polysilicon.

10. A method of fabricating a capacitive micromachined ultrasonic transducer (CMUT) arrangement, the method comprising:

providing a substrate;

forming a plurality of trenches in the substrate;

forming a doping layer at at least one side wall of at least one of the plurality of trenches;

depositing insulating materials in the trenches;

forming a plurality of insulating posts on a surface of the substrate, wherein the insulating posts define a plurality of cavities on the surface of the substrate; and forming a membrane, said membrane being supported on the insulating posts.

11. The method of claim 10, wherein

a transducer cell is formed by at least one insulating post of the plurality of insulating posts, the cavity defined on the surface of the substrate, the membrane, and the substrate.

12. The method of claim 11, further comprising:

forming a plurality of insulating posts at another surface of the substrate opposite the surface of the substrate on which the cavities are defined, wherein the insulating posts are connected to a first group of trenches selected out of the plurality of trenches.

13. The method of claim 12,

wherein the first group of trenches comprises trenches formed next to or along the perimeter of the transducer cells.

14. The method of claim 12 or 13, further comprising:

forming a plurality of interconnects at another surface of the substrate opposite the surface of the substrate on which the cavities are defined, wherein the plurality of interconnects are conductively connected with a second group of trenches selected from the trenches being doped at the at least one side wall, the second group of trenches comprising trenches different from the trenches of the first group of trenches.

15. The method of claim 14,

wherein the second group of trenches comprises trenches formed within the perimeter of the transducer cells.

16. The method of any one of claims 10 to 15, further comprising:

bonding an electronic circuit to another surface of the substrate opposite the surface of the substrate on which the cavities are defined.

17. The method of any one of claims 10 to 16, wherein

forming the doping layer at the at least one side wall of the at least one trench comprises forming a doped polysilicon layer at the at least one side wall of the at least one trench.