WO2013076470A3 - Clock generator - Google Patents
Clock generator Download PDFInfo
- Publication number
- WO2013076470A3 WO2013076470A3 PCT/GB2012/052868 GB2012052868W WO2013076470A3 WO 2013076470 A3 WO2013076470 A3 WO 2013076470A3 GB 2012052868 W GB2012052868 W GB 2012052868W WO 2013076470 A3 WO2013076470 A3 WO 2013076470A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frequency
- signal
- clock signal
- error signal
- input clock
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
- H03L7/235—Nested phase locked loops
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
A clock generator receives a first input clock signal and a second input clock signal. A first frequency comparator generates a first frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the first input clock signal, and a first subtractor forms a first error signal representing a difference between an input desired frequency ratio and the first frequency comparison signal. A first digital filter receives the first error signal and forms a filtered first error signal. A second frequency comparator generates a second frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the second input clock signal, and a second subtractor forms a second error signal representing a difference between the filtered first error signal and the second frequency comparison signal. A second digital filter receives the second error signal and forms a filtered second error signal. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201280067552.3A CN104067520B (en) | 2011-11-21 | 2012-11-20 | Clock generator |
KR1020207016428A KR102222865B1 (en) | 2011-11-21 | 2012-11-20 | Clock generator |
KR1020197020114A KR102122509B1 (en) | 2011-11-21 | 2012-11-20 | Clock generator |
KR1020147016887A KR102000756B1 (en) | 2011-11-21 | 2012-11-20 | Clock generator |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1120016.9A GB2496673B (en) | 2011-11-21 | 2011-11-21 | Clock generator |
GB1120016.9 | 2011-11-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2013076470A2 WO2013076470A2 (en) | 2013-05-30 |
WO2013076470A3 true WO2013076470A3 (en) | 2013-07-25 |
Family
ID=45475440
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2012/052868 WO2013076470A2 (en) | 2011-11-21 | 2012-11-20 | Clock generator |
Country Status (4)
Country | Link |
---|---|
KR (3) | KR102000756B1 (en) |
CN (3) | CN107359874B (en) |
GB (1) | GB2496673B (en) |
WO (1) | WO2013076470A2 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103843795A (en) * | 2012-12-07 | 2014-06-11 | 陕西美邦农药有限公司 | Fungicidal composition containing fenpyrazamine |
GB2557051B (en) * | 2013-10-23 | 2018-08-22 | Cirrus Logic Int Semiconductor Ltd | Class-D amplifier circuits |
US9674480B2 (en) * | 2014-10-01 | 2017-06-06 | Teac Corporation | Camera link recorder |
CN104777378A (en) * | 2015-03-09 | 2015-07-15 | 国核自仪***工程有限公司 | FPGA clock signal self-detecting method |
CN104702365A (en) * | 2015-03-09 | 2015-06-10 | 烽火通信科技股份有限公司 | Delta sigma principle-based clock adjustment system and method |
WO2017154126A1 (en) * | 2016-03-09 | 2017-09-14 | 三菱電機株式会社 | Pulse shifting circuit and frequency synthesizer |
WO2019032899A1 (en) * | 2017-08-09 | 2019-02-14 | Planar Systems, Inc. | Clock synthesis circuitry and associated techniques for generating clock signals refreshing display screen content |
CN113196184B (en) * | 2018-10-22 | 2022-10-18 | 盈诺飞公司 | Wide-measuring-range high-sensitivity time-to-digital converter |
US10734977B1 (en) * | 2019-04-10 | 2020-08-04 | Silicon Laboratories Inc. | Efficient voltage controlled oscillator (VCO) analog-to-digital converter (ADC) |
CN110739970B (en) * | 2019-11-01 | 2023-12-26 | 上海艾为电子技术股份有限公司 | Analog-to-digital conversion circuit, portable device, and analog-to-digital conversion method |
CN112150962B (en) * | 2020-10-23 | 2024-04-05 | 维沃移动通信有限公司 | Chip clock frequency adjusting method and device, chip and electronic equipment |
KR102477864B1 (en) * | 2020-12-11 | 2022-12-15 | 한국과학기술원 | A frequency hopping spread spectrum frequency synthesizer |
CN113093510B (en) * | 2021-02-26 | 2022-07-22 | 山东师范大学 | Clock frequency signal error measuring instrument and method |
CN113193848B (en) * | 2021-04-30 | 2022-09-30 | 广东电网有限责任公司电力科学研究院 | Online measurement method for improving high-frequency noise power gain of novel basic controller |
CN115223578B (en) * | 2022-09-21 | 2023-07-14 | 浙江地芯引力科技有限公司 | Audio signal synchronization method, device, equipment and storage medium |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6385267B1 (en) * | 1998-12-22 | 2002-05-07 | Microsoft Corporation | System and method for locking disparate video formats |
WO2008132583A1 (en) * | 2007-05-01 | 2008-11-06 | Dialogic Corporation | Filterless digital frequency locked loop |
US7746972B1 (en) * | 2007-03-22 | 2010-06-29 | Cirrus Logic, Inc. | Numerically-controlled phase-lock loop with input timing reference-dependent ratio adjustment |
Family Cites Families (22)
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SE445868B (en) * | 1984-12-12 | 1986-07-21 | Ellemtel Utvecklings Ab | DEVICE FOR DIVIDING A CLOCK RATE |
US5870592A (en) * | 1996-10-31 | 1999-02-09 | International Business Machines Corp. | Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator |
US5825253A (en) * | 1997-07-15 | 1998-10-20 | Qualcomm Incorporated | Phase-locked-loop with noise shaper |
US8374075B2 (en) * | 2006-06-27 | 2013-02-12 | John W. Bogdan | Phase and frequency recovery techniques |
GB2409383B (en) * | 2003-12-17 | 2006-06-21 | Wolfson Ltd | Clock synchroniser |
GB2413043B (en) * | 2004-04-06 | 2006-11-15 | Wolfson Ltd | Clock synchroniser and clock and data recovery apparatus and method |
CN100353671C (en) * | 2004-05-26 | 2007-12-05 | 华为技术有限公司 | Clock synthesizing method and system |
US7499106B1 (en) * | 2004-10-13 | 2009-03-03 | Cirrus Logic, Inc. | Method and system for synchronizing video information derived from an asynchronously sampled video signal |
US7558358B1 (en) * | 2004-10-13 | 2009-07-07 | Cirrus Logic, Inc. | Method and apparatus for generating a clock signal according to an ideal frequency ratio |
US7512175B2 (en) * | 2005-03-16 | 2009-03-31 | Ibiquity Digital Corporation | Method for synchronizing exporter and exciter clocks |
US7873133B2 (en) * | 2005-06-30 | 2011-01-18 | Infinera Corporation | Recovery of client clock without jitter |
US7330058B2 (en) * | 2005-07-01 | 2008-02-12 | Via Technologies, Inc. | Clock and data recovery circuit and method thereof |
JP2007124044A (en) * | 2005-10-25 | 2007-05-17 | Nec Electronics Corp | Reference clock reproduction circuit and data receiver |
CN101385294B (en) * | 2006-02-17 | 2011-12-07 | 标准微体系有限公司 | System and method for transferring different types of streaming and packetized data across an Ethernet transmission line using a frame and packet structure demarcated with ethernet coding violations |
US7599462B2 (en) * | 2006-09-25 | 2009-10-06 | Cirrus Logic, Inc. | Hybrid analog/digital phase-lock loop with high-level event synchronization |
US7680236B1 (en) * | 2006-09-25 | 2010-03-16 | Cirrus Logic, Inc. | Hybrid analog/digital phase-lock loop for low-jitter synchronization |
CN101557208B (en) * | 2008-04-10 | 2011-09-28 | 智原科技股份有限公司 | Adjusting circuit, integrated circuit applying the same and signal filtering method |
CN101673351A (en) * | 2008-09-11 | 2010-03-17 | 北京同方微电子有限公司 | Pseudo-random number generating circuit and generating method of radio frequency identification tag chip |
US8031009B2 (en) * | 2008-12-02 | 2011-10-04 | Electronics And Telecommunications Research Institute | Frequency calibration loop circuit |
US8452429B2 (en) * | 2009-01-21 | 2013-05-28 | Cirrus Logic, Inc. | Audio processor with internal oscillator-generated audio intermediate frequency reference |
CN101520672B (en) * | 2009-03-20 | 2011-02-09 | 东南大学 | All-digital spread-spectrum clock generator for use in SATA |
US8433027B2 (en) * | 2009-10-08 | 2013-04-30 | Dialog Semiconductor Gmbh | Digital controller for automatic rate detection and tracking of audio interface clocks |
-
2011
- 2011-11-21 GB GB1120016.9A patent/GB2496673B/en active Active
-
2012
- 2012-11-20 KR KR1020147016887A patent/KR102000756B1/en active IP Right Grant
- 2012-11-20 CN CN201710702456.6A patent/CN107359874B/en active Active
- 2012-11-20 KR KR1020207016428A patent/KR102222865B1/en active IP Right Grant
- 2012-11-20 CN CN202011448492.2A patent/CN112564701A/en active Pending
- 2012-11-20 WO PCT/GB2012/052868 patent/WO2013076470A2/en active Application Filing
- 2012-11-20 CN CN201280067552.3A patent/CN104067520B/en active Active
- 2012-11-20 KR KR1020197020114A patent/KR102122509B1/en active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6385267B1 (en) * | 1998-12-22 | 2002-05-07 | Microsoft Corporation | System and method for locking disparate video formats |
US7746972B1 (en) * | 2007-03-22 | 2010-06-29 | Cirrus Logic, Inc. | Numerically-controlled phase-lock loop with input timing reference-dependent ratio adjustment |
WO2008132583A1 (en) * | 2007-05-01 | 2008-11-06 | Dialogic Corporation | Filterless digital frequency locked loop |
Also Published As
Publication number | Publication date |
---|---|
KR20190086778A (en) | 2019-07-23 |
KR102222865B1 (en) | 2021-03-03 |
KR102122509B1 (en) | 2020-06-12 |
WO2013076470A2 (en) | 2013-05-30 |
GB201120016D0 (en) | 2012-01-04 |
CN104067520A (en) | 2014-09-24 |
CN112564701A (en) | 2021-03-26 |
CN104067520B (en) | 2017-09-05 |
KR102000756B1 (en) | 2019-07-16 |
GB2496673B (en) | 2014-06-11 |
KR20140103970A (en) | 2014-08-27 |
CN107359874A (en) | 2017-11-17 |
GB2496673A (en) | 2013-05-22 |
CN107359874B (en) | 2021-01-01 |
KR20200069390A (en) | 2020-06-16 |
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