WO2013069559A1 - Dispositif d'affichage et son procédé de commande - Google Patents

Dispositif d'affichage et son procédé de commande Download PDF

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Publication number
WO2013069559A1
WO2013069559A1 PCT/JP2012/078435 JP2012078435W WO2013069559A1 WO 2013069559 A1 WO2013069559 A1 WO 2013069559A1 JP 2012078435 W JP2012078435 W JP 2012078435W WO 2013069559 A1 WO2013069559 A1 WO 2013069559A1
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Prior art keywords
pixel
line
potential
auxiliary
auxiliary capacitance
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PCT/JP2012/078435
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English (en)
Japanese (ja)
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耕平 田中
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シャープ株式会社
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Publication of WO2013069559A1 publication Critical patent/WO2013069559A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present invention relates to a display device, and more particularly to a display device having a configuration in which one pixel is divided into a plurality of subpixels and a driving method thereof in order to improve viewing angle characteristics.
  • the multi-pixel structure different voltages are applied to the liquid crystal layer between the two sub-pixels (that is, a relatively bright light pixel and a relatively dark pixel are provided), so that different gamma characteristics are obtained. Since the images are mixed and observed, the viewing angle dependency of the gamma characteristic is improved.
  • FIG. 27 is an equivalent circuit diagram showing a configuration of a pixel formation portion having a multi-pixel structure disclosed in Patent Document 1.
  • the pixel formation unit 20 (i, j) disposed corresponding to the intersection of the source line SLj and the gate line GLi includes the first subpixel formation unit 21 (i, j) and the second subpixel formation unit 21 (i, j).
  • the sub-pixel forming unit 22 (i, j) is configured.
  • Two CS lines CSL1 and CSL2 are provided along the gate line GLi.
  • the pixel electrode Epix1 of the first subpixel forming unit 21 (i, j) is connected to the source line SLj via the thin film transistor T1, and is connected to the CS line CSL1 via the capacitor Ccs1.
  • a liquid crystal capacitor Clc1 is formed between the pixel electrode Epix1 and the common electrode COM.
  • the pixel electrode Epix2 of the second subpixel formation unit 22 (i, j) is connected to the source line SLj via the thin film transistor T2, and is connected to the CS line CSL2 via the capacitor Ccs2.
  • a liquid crystal capacitor Clc2 is formed between the pixel electrode Epix2 and the common electrode COM.
  • the CS lines CSL1 and CSL2 are driven in a phase opposite to each other and at a constant cycle.
  • the potentials (more specifically, effective values) of the pixel electrodes Epix1 and Epix2 are different from each other.
  • the voltage to be applied to the liquid crystal layer can be made different between the first subpixel forming portion 21 (i, j) and the second subpixel forming portion 22 (i, j).
  • one of the pixel electrodes Epix1 and Epix2 is boosted and the other is lowered.
  • “the pixel electrode is stepped up or stepped down” may be referred to as “the subpixel forming portion is stepped up or stepped down”, respectively.
  • boost means to increase the potential with reference to the common potential Vcom which is the potential of the common electrode COM when performing a positive display, and when performing a negative display. Means to lower the potential with reference to the common potential Vcom.
  • step-down refers to lowering the potential with reference to the common potential Vcom when performing a positive display, and increasing the potential with reference to the common potential Vcom when performing a negative display. To do.
  • the pixel formation unit 20 (i, j) corresponds to positive polarity and the pixel formation unit 20 (i, j + 1) adjacent in the row direction corresponds to negative polarity in a certain frame.
  • the first subpixel forming unit 21 (i, j) is boosted, and the first subpixel forming unit 21 (i, j + 1) is stepped down.
  • the second subpixel formation unit 22 (i, j) is stepped down, and the second subpixel formation unit 22 (i, j + 1) is stepped up.
  • the first sub-pixel forming portions 21 (i, j) and 21 (i, j + 1) correspond to the bright pixels and the dark pixels, respectively, and the second sub-pixel forming portions 22 (i, j) and 22 (i, j + 1).
  • the bright pixels and the dark pixels are alternately arranged in the row direction and the column direction (in this specification, the direction in which the source line extends) (that is, the bright pixels and the dark pixels are so-called staggered). Display quality is reduced. Further, in order to maintain a high aperture ratio in such an arrangement of bright pixels and dark pixels, it is necessary to fix the area ratio between the bright pixels and the dark pixels to 1: 1. For this reason, it becomes difficult to adopt the area ratio of the bright pixel and the dark pixel so that better display quality can be obtained.
  • an object of the present invention is to provide a display device with improved viewing angle characteristics and a driving method thereof while improving display quality compared to the conventional one.
  • a first aspect of the present invention is a matrix corresponding to a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signal lines and the plurality of scanning signal lines.
  • a plurality of pixel formation portions arranged in a shape and a common electrode provided in common to the plurality of pixel formation portions, and at least a first predetermined number of video signal lines in a direction in which the scanning signal lines extend
  • An active matrix display device that performs polarity inversion driving by changing the polarity of the potential every time, A first auxiliary capacitance line and a second auxiliary capacitance line which are provided so as to correspond to the respective scanning signal lines and have different potentials and change in potential after at least the end of the selection period of the scanning signal line;
  • Each pixel forming part A first pixel electrode and a second pixel electrode to which a potential corresponding to an image to be displayed is to be respectively applied;
  • the first predetermined number is one.
  • the potential of the first auxiliary capacitance line is the end of the selection period of the scanning signal line corresponding to the pixel forming portion when the pixel forming portion including the first auxiliary capacitance connected to the first auxiliary capacitance line performs a positive display. It changes in the direction that rises later, and when performing negative polarity display, it changes in the direction that goes down after the selection period of the scanning signal line corresponding to the pixel formation portion,
  • the potential of the second auxiliary capacitance line is the end of the selection period of the scanning signal line corresponding to the pixel formation portion when the pixel formation portion including the first auxiliary capacitance connected to the second auxiliary capacitance line performs a positive display. It changes in the direction of rising later, and when performing negative display, it changes in the direction of lowering after the end of the selection period of the scanning signal line corresponding to the pixel formation portion.
  • the potentials of the first auxiliary capacitance line and the second auxiliary capacitance line change every second predetermined number of selection periods in which the second predetermined number of scanning signal lines are selected. To do.
  • the one of the first auxiliary capacitor line and the second auxiliary capacitor line to be connected to the first auxiliary capacitor, the first auxiliary capacitor line to be connected to the second auxiliary capacitor, and the second The other of the storage capacitor lines is switched for each of the second predetermined number of the pixel forming portions in the extending direction of the video signal line.
  • the first switching element and the first conduction terminal of the second switching element in the other pixel formation part of the part are respectively connected to one and the other of the two video signal lines adjacent to each other. It is characterized by.
  • the second predetermined number is one.
  • the second predetermined number is plural.
  • Each pixel forming part A third storage capacitor formed between the other of the first storage capacitor line and the second storage capacitor line and the second pixel electrode; And a fourth auxiliary capacitance formed between the one of the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode and having a capacitance value smaller than that of the third auxiliary capacitance. It is characterized by.
  • Each pixel forming part A third storage capacitor formed between the one of the first storage capacitor line and the second storage capacitor line and the second pixel electrode; And a fourth auxiliary capacitance formed between the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the second pixel electrode and having a capacitance value smaller than that of the third auxiliary capacitance. It is characterized by.
  • the storage device further includes an auxiliary capacitance line driving circuit that independently drives the first auxiliary capacitance line and the second auxiliary capacitance line in a pixel formation portion arranged in a direction in which the video signal line extends.
  • a third auxiliary capacitance line provided to correspond to each scanning signal line and to which a fixed potential is applied;
  • Each pixel formation portion is formed between the third auxiliary capacitance line and the second pixel electrode, and the first pixel electrode and the second pixel at the end of the selection period of the scanning signal line corresponding to the pixel formation portion.
  • It further includes an adjustment capacitor whose capacitance value is set so that the potential changes of the electrodes are substantially equal to each other.
  • Each pixel forming part A first adjustment capacitor formed between the scanning signal line and the first pixel electrode; A second adjustment capacitor formed between the scanning signal line and the second pixel electrode;
  • the capacitance values of the first adjustment capacitor and the second adjustment capacitor are the potential changes of the first pixel electrode and the second pixel electrode at the end of the selection period of the scanning signal line corresponding to the pixel formation portion. It is characterized by being set to be substantially equal to each other.
  • the first conduction terminal of the second switching element or the first conduction terminal of the first switching element is connected to the video signal line via the first switching element or the second switching element, respectively. It is characterized by that.
  • Each of the first switching element and the second switching element is a thin film transistor in which a channel layer is formed of an oxide semiconductor or microcrystalline silicon.
  • a sixteenth aspect of the present invention is a matrix corresponding to a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signal lines and the plurality of scanning signal lines.
  • a plurality of pixel formation portions arranged in a shape and a common electrode provided in common to the plurality of pixel formation portions, and at least a first predetermined number of video signal lines in a direction in which the scanning signal lines extend It is a driving method of an active matrix type display device that performs polarity inversion driving by changing the polarity of the potential every time,
  • a potential control step of applying different potentials to the first auxiliary capacitance line and the second auxiliary capacitance line provided so as to correspond to each scanning signal line and changing a potential to be applied at least after the selection period of the scanning signal line is ended.
  • a first display capacitor formed between the first pixel electrode and the common electrode;
  • a second display capacitor formed between the second pixel electrode and the common electrode;
  • a first storage capacitor formed between one of the first storage capacitor line and the second storage capacitor line and the first pixel electrode;
  • a second auxiliary capacitance formed between the other of the first auxiliary capacitance line and the second auxiliary capacitance line and the first pixel electrode and having a capacitance value smaller than that of the first auxiliary capacitance;
  • a seventeenth aspect of the present invention is the sixteenth aspect of the present invention,
  • the first predetermined number is one.
  • the potential applied to the first auxiliary capacitance line is the selection of the scanning signal line corresponding to the pixel formation portion when the pixel formation portion including the first auxiliary capacitance connected to the first auxiliary capacitance line performs a positive display.
  • the potential applied to the second auxiliary capacitance line is the selection of the scanning signal line corresponding to the pixel formation portion when the pixel formation portion including the first auxiliary capacitance connected to the second auxiliary capacitance line performs a positive display. It changes in the direction of rising after the end of the period, and when performing negative polarity display, it is controlled to change in the direction of lowering after the selection period of the scanning signal line corresponding to the pixel formation portion.
  • the nineteenth aspect of the present invention is the eighteenth aspect of the present invention.
  • the potentials of the first auxiliary capacitance line and the second auxiliary capacitance line are set for each second predetermined number of selection periods in which the second predetermined number of scanning signal lines are selected. It is controlled to change.
  • the first auxiliary capacitor and the second auxiliary having a capacitance value smaller than that of the first auxiliary capacitor are provided in the first pixel electrode.
  • a capacity is provided.
  • Different auxiliary capacitance lines (first auxiliary capacitance line or second auxiliary capacitance line) are connected to the first auxiliary capacitance and the second auxiliary capacitance, and auxiliary capacitances to which the first auxiliary capacitance and the second auxiliary capacitance are connected are connected.
  • the line is switched for each first predetermined number of pixel formation portions in the row direction (direction in which the scanning signal line extends).
  • the polarity of the potential differs for each of the first predetermined number of video signal lines in at least the direction in which the scanning signal lines extend, and the potentials of the first auxiliary capacitance line and the second auxiliary capacitance line are the same for each scanning signal line. Changes at the end of the selection period.
  • the potential of the auxiliary capacitance line to which the first auxiliary capacitance is connected changes in a direction in which the potential increases after the selection period of the scanning signal line corresponding to the pixel forming portion performing the positive polarity display, and the negative polarity display.
  • a bright pixel is realized according to the potential of the first pixel electrode
  • a dark pixel is realized according to the potential of the second pixel electrode.
  • the bright pixel and the dark pixel are arranged side by side in the row direction.
  • the area ratio between the bright pixels and the dark pixels can be arbitrarily set. Therefore, for example, the area of the second pixel electrode can be set to be larger than the area of the first pixel electrode in order to prevent so-called black floating in which the low gradation pixel becomes brighter than the actual pixel.
  • the display polarity (the polarity of the potential of the first pixel electrode and the second pixel electrode in the pixel formation portion) is different for each first predetermined number of pixel formation portions in at least the row direction, at least the first predetermined number of columns
  • Unit column inversion driving (inversion driving performed in units of columns) can be performed.
  • the potential of the auxiliary capacitance line (first auxiliary capacitance line or second auxiliary capacitance line) to which the first auxiliary capacitance is connected performs positive polarity display. It changes in a direction that rises after the selection period of the scanning signal line corresponding to the pixel formation portion, and changes in a direction that goes down after the selection period of the scanning signal line that corresponds to the pixel formation portion that performs negative display.
  • the same effect as that of the second aspect or the seventeenth aspect of the present invention can be obtained.
  • the display polarity can be made different for each predetermined number of pixel forming portions in the column direction (direction in which the video signal line extends).
  • the fifth aspect of the present invention in the configuration in which the storage capacitor lines to which the first storage capacitor and the second storage capacitor are connected are replaced for each second predetermined number of pixel formation portions in the column direction. The same effect as in the fourth aspect can be obtained.
  • the sixth aspect of the present invention in the configuration in which the video signal line to which the pixel forming units arranged in the column direction are connected is one of the two video signal lines adjacent to each other, The same effect as the fourth aspect of the invention or the fifth aspect of the invention can be obtained.
  • the seventh aspect of the present invention for example, by changing the polarity of the potential of the video signal line for each selection period or by making the polarity of the potential of the video signal line constant within each frame,
  • the display polarity can be made different for each pixel forming portion.
  • the display polarity can be made different for each pixel forming portion in the column direction.
  • the potential difference between the potential of the first pixel electrode and the potential of the second pixel electrode is larger than in the first aspect of the present invention. For this reason, since the luminance difference between the luminance according to the potential of the first pixel electrode and the luminance according to the potential of the second pixel electrode becomes larger, it is possible to further suppress black floating.
  • the potential of the second pixel electrode changes in the same direction as the potential of the first pixel electrode, and the potential change of the second pixel electrode is smaller than the potential change of the first pixel electrode.
  • a bright pixel is realized according to the potential of the first pixel electrode in each pixel formation portion, a dark pixel is realized according to the potential of the second pixel electrode, and the drive amplitude of the video signal line is reduced. . Thereby, low power consumption can be achieved.
  • the eleventh aspect of the present invention since the first auxiliary capacitance line and the second auxiliary capacitance line are independently driven by the auxiliary capacitance line drive circuit in the pixel formation portion arranged in the column direction, In the section, the potentials of the first auxiliary capacitance line and the second auxiliary capacitance line are constant between the end of the selection period of the scanning signal line and the start of the selection period of the next frame. For this reason, the potential of the first pixel electrode is higher than that of the first aspect of the present invention during positive polarity display, and the potential of the first pixel electrode is lower than that of the first aspect of the present invention during negative polarity display. As a result, the luminance difference between the luminance according to the potential of the first pixel electrode and the luminance according to the potential of the second pixel electrode becomes larger, so that black floating can be further suppressed.
  • the thirteenth aspect of the present invention by providing the first adjustment capacitor and the second adjustment capacitor, variations in potential fluctuations in the first pixel electrode and the second pixel electrode at the end of the scanning signal line selection period can be obtained. It is suppressed.
  • the parasitic capacitance formed between the video signal line and the scanning signal line becomes relatively small. For this reason, since the capacity of the video signal line is reduced, power consumption can be reduced.
  • each of the first switching element and the second switching element is a thin film transistor, and its channel layer is formed of an oxide semiconductor or microcrystalline silicon. Since the oxide semiconductor and microcrystalline silicon have higher mobility than amorphous silicon or the like, the size of the first switching element and the second switching element can be reduced. For this reason, it is possible to improve the aperture ratio of the pixel formation portion and reduce the load on the bus lines (video signal lines and scanning signal lines).
  • FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 3 is an equivalent circuit diagram illustrating a configuration of a pixel formation unit in the first embodiment. It is a figure which shows the layout of the pixel formation part vicinity in the said 1st Embodiment. It is a signal waveform diagram for demonstrating the drive method in the said 1st Embodiment. It is an equivalent circuit diagram which shows the structure of the pixel formation part in the 2nd Embodiment of this invention. It is a signal waveform diagram for demonstrating the drive method in the said 2nd Embodiment.
  • FIG. 10 is an equivalent circuit diagram illustrating a configuration of a pixel formation unit according to a third embodiment of the present invention.
  • FIG. 4A is a plan view showing a layout of a thin film transistor.
  • B is a sectional view taken along line AA of (A).
  • m and n are integers of 2 or more, i is an integer of 1 to m, and j is an integer of 1 to n.
  • the number based on the row direction corresponds to the first predetermined number, and the number based on the column direction corresponds to the second predetermined number.
  • FIG. 1 is a block diagram showing the overall configuration of an active matrix display device according to a first embodiment of the present invention.
  • the liquid crystal display device includes a display unit 100, a display control circuit 200, a source driver 300 as a video signal line driving circuit, and a gate driver 400 as a scanning signal line driving circuit.
  • the display unit 100 includes source lines SL1 to SLn (hereinafter referred to as SL when not distinguished from each other) as a plurality (n) of video signal lines, and a plurality (m) of scanning signal lines.
  • a plurality of (m ⁇ n) pixel forming portions are formed.
  • a first CS line CSL1 as a first auxiliary capacitance line and a second CS line CSL2 as a second auxiliary capacitance line are provided along each gate line GL.
  • the first CS line CSL1 and the second CS line CSL2 along the gate line GLi may be referred to as the “i-th first CS line CSL1” and the “i-th second CS line CSL2”, respectively.
  • Each first CS line CSL1 is connected to the first CS bus line CB1
  • each second CS line CSL2 is connected to the second CS bus line CB2.
  • the display control circuit 200 receives image data DAT sent from the outside and a timing signal group TG such as a horizontal synchronizing signal and a vertical synchronizing signal, and receives a digital video signal DV and a source start pulse signal for controlling image display on the display unit 100.
  • SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP, and gate clock signal GCK are output.
  • the potential control step is executed by the display control circuit 200. That is, the display control circuit 200 supplies the first auxiliary capacitance signal and the second auxiliary capacitance signal to the first CS bus line CB1 and the second CS bus line CB2, respectively.
  • the present invention is not limited to this, and the first auxiliary capacitance signal and the second auxiliary capacitance signal may be supplied from other circuits to the first CS bus line CB1 and the second CS bus line CB2, respectively. good. A detailed description of the first auxiliary capacitance signal and the second auxiliary capacitance signal will be described later.
  • the source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and applies a driving video signal to each source line SL.
  • the gate driver 400 receives the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, and applies a scanning signal to each gate line GL.
  • a scanning signal is applied to each gate line GL and a driving video signal is applied to each source line SL, whereby an image based on image data DAT sent from the outside is displayed on the display unit 100. Is done.
  • FIG. 2 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (four pixel formation units) in the display unit 100 in the present embodiment.
  • the pixel formation portion provided corresponding to the i-th gate line GLi and the j-th source line SLj, that is, the i-th row and j-th column pixel formation portion is denoted by reference numeral 10 (i, j).
  • the pixel forming portions are simply represented by reference numeral 10.
  • the pixel forming portion 10 has a multi-pixel structure. That is, the pixel forming unit 10 includes a first subpixel forming unit 11 and a second subpixel forming unit 12.
  • the first subpixel formation unit 11 and the second subpixel formation unit 12 in the pixel formation unit 10 (i, j) in the i-th row and j-th column are denoted by reference numerals 11 (i, j) and 12 respectively. (I, j).
  • the first subpixel forming unit 11 (i, j) and the second subpixel forming unit 12 (i, j) are respectively referred to as “first subpixel forming unit in i row and j column” and “i row j”. It may be referred to as “second sub-pixel formation portion in the column”.
  • the first subpixel forming unit 11 corresponds to a bright pixel
  • the second subpixel forming unit 12 corresponds to a dark pixel.
  • the first sub-pixel forming unit 11 includes a first thin film transistor T1 as a first switching element, a first pixel electrode Epix1, a first liquid crystal capacitor Clc1 as a first display capacitor, a first auxiliary capacitor CcsA, and a second auxiliary capacitor. Includes CcsB.
  • the capacitance values of the first liquid crystal capacitor, the first auxiliary capacitor, and the second auxiliary capacitor may be represented by Clc1, CcsA, and CcsB, respectively. In this embodiment and each embodiment described later, CcsA> CcsB.
  • the connection relationship between the components in the first subpixel forming unit 11 is as follows.
  • the gate line GL is connected to the gate electrode as the control terminal
  • the source line SL is connected to the source electrode as the first conduction terminal
  • the first pixel electrode Epix1 is the drain as the second conduction terminal.
  • a first liquid crystal capacitor Clc is formed between the first pixel electrode Epix1 and the common electrode COM provided in common in each pixel forming unit 10.
  • a common potential Vcom that is a fixed potential is applied to the common electrode COM.
  • One end of each of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB is connected to the first pixel electrode Epix1.
  • connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are switched for each column. That is, in the first sub-pixel forming unit 11 (i, j) in the i-th row and j-th column, the other end of the first auxiliary capacitor CcsA is connected to the first CS line CSL1, and the other end of the second auxiliary capacitor CcsB is the second CS.
  • the other end of the first auxiliary capacitor CcsA is connected to the second CS line CSL2 in the first subpixel formation unit 11 (i, j + 1) in the i-th row, j + 1-th column,
  • the other end of the auxiliary capacitor CcsB is connected to the first CS line CSL1.
  • the other end of the first auxiliary capacitor CcsA is connected to the first CS line CSL1, and the other of the second auxiliary capacitor CcsB.
  • the end is connected to the second CS line CSL2.
  • the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are the same in each first sub-pixel forming unit 11.
  • the second subpixel forming unit 12 includes a second thin film transistor T2 as a second switching element, a second pixel electrode Epix2, and a second liquid crystal capacitor Clc2 as a second display capacitor.
  • a predetermined auxiliary capacitor may be provided in parallel with the second liquid crystal capacitor Clc2, that is, between the second pixel electrode Epix2 and the common electrode COM.
  • the connection relationship between the components in the second subpixel forming unit 12 is as follows.
  • the gate line GL is connected to the gate electrode as the control terminal
  • the source line SL is connected to the source electrode as the first conduction terminal
  • the second pixel electrode Epix2 is the drain as the second conduction terminal. Connected to the electrode.
  • gate line GL and the source line SL are the gate lines connected to the gate electrode of the first thin film transistor T1 in the first subpixel forming unit 11 in the pixel forming unit 10 including the second subpixel forming unit 12.
  • the GL and the source line SL connected to the source electrode of the first thin film transistor T1 are the same.
  • a second liquid crystal capacitor Clc2 is formed between the second pixel electrode Epix2 and the common electrode COM.
  • the channel layers of the first and second thin film transistors T1 and T2 in this embodiment and each embodiment described later are formed of, for example, an oxide semiconductor. Note that the present invention is not limited to this, and microcrystalline silicon may be used instead of the oxide semiconductor. In addition, although the mobility of the first and second thin film transistors T1 and T2 is lower than that in the case of using an oxide semiconductor or microcrystalline silicon, amorphous silicon or the like may be used for those channel layers.
  • FIG. 3 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG.
  • the gate metal that forms the gate line GL, the gate metal that forms the first CS line CSL1, and the gate metal that forms the second CS line CSL2 are arranged in parallel to each other.
  • another metal disposed in the same layer as the gate metal forming the gate line GL is also called a gate metal.
  • the gate metal and the source metal forming the source line SL are arranged so as to be orthogonal to each other. Of the region between two adjacent source lines SL, a portion other than the region where the gate line GL is disposed (except for a portion of the region where the first CS line CSL1 is disposed).
  • the first pixel electrode Epix1 and the second pixel electrode Epix2 are formed.
  • the first pixel electrode Epix1 and the second pixel electrode Epix2 are formed as transparent electrodes.
  • the area ratio between the first pixel electrode Epix1 corresponding to the bright pixel and the second pixel electrode Epix2 corresponding to the dark pixel is such that the area of the second pixel electrode Epix2 is equal to that of the first pixel electrode Epix1, as shown in FIG. It is set to be larger than the area.
  • Such setting of the area ratio is disclosed in Patent Document 2, for example.
  • the present invention is not limited to this, and the area ratio between the first pixel electrode Epix1 and the second pixel electrode Epix2 can be arbitrarily set.
  • the drain electrode of the first thin film transistor T1 and the first pixel electrode Epix1 in the first subpixel formation unit 11 are electrically connected to each other by the source metal SE1 and the contact CT1.
  • first facing area the area of the source metal SE1 facing the first CS line CSL1 in the i-th row
  • second opposing area the area of the portion of the source metal SE1 that faces the second CS line CSL2
  • the first auxiliary capacitor CcsA is formed in the portion where the source metal SE1 and the first CS line CSL1 in the i-th row overlap each other, and the source metal SE1.
  • a second auxiliary capacitor CcsB is formed at a portion where the second CS line CSL2 and the second CS line CSL2 overlap each other.
  • the first counter area is larger than the area of the second counter area. Is set too small.
  • the first opposing area and the second opposing area in the first subpixel forming unit 11 (i, j + 1) in the i row j + 1 column are respectively the first subpixel forming unit 11 in the i row j column ( It is substantially the same as the second opposing area and the first opposing area in i, j).
  • the second auxiliary capacitor CcsB is formed in a portion where the source metal SE1 and the first CS line CSL1 overlap each other, and the source metal SE1 and the second CS line are formed.
  • the first auxiliary capacitor CcsA is formed at a portion where the CSL2 and the CSL2 overlap each other.
  • the layout of the first subpixel forming unit 11 (i + 1, j) in the i + 1 row and j column is that of the first subpixel forming unit 11 (i, j) in the i row and j column.
  • the layout of the first subpixel formation unit 11 (i + 1, j + 1) in the (i + 1) th row j + 1th column is the same as that of the first subpixel formation unit 11 (i, j + 1) in the ith row j + 1th column. .
  • the first auxiliary capacitor CcsA or the second auxiliary capacitor CcsB is formed at a portion where the source metal SE1 and the first CS line CSL1 or the second CS line CSL2 overlap each other, the first CS line is actually formed.
  • a capacitance (hereinafter referred to as “capacitance to be considered in design”) is also formed in a portion where the CSL1 or the second CS line CSL2 overlaps the first pixel electrode Epix1. Therefore, in practice, the sum of the capacity to be considered in design and the first auxiliary capacity CcsA or the second auxiliary capacity CcsB is set as the first auxiliary capacity CcsA or the second auxiliary capacity CcsB in the design. The same applies to the layout description described later.
  • the drain electrode of the second thin film transistor T2 and the second pixel electrode Epix2 in the second pixel formation portion 12 are electrically connected to each other by the source metal SE2 and the contact CT2.
  • FIG. 4 is a signal waveform diagram for explaining the driving method in the present embodiment. More specifically, in a selection period (a period for performing writing to the first pixel electrode Epix1 and the second pixel electrode Epix2 according to an image to be displayed in each pixel forming unit 10) and a sub-pixel CS driving period described later. It is a signal waveform diagram for demonstrating operation
  • the length of the selection period corresponds to the length of one horizontal scanning period (indicated as “1H” in FIG. 4) in the liquid crystal display device.
  • the sub-pixel CS driving period is a period for making potentials different between the first pixel electrode Epix and the second pixel electrode Epix2, and specifically, the Nth frame (N is an integer of 1 or more). Means the period from the end of the selection period to the start of the selection period in the (N + 1) th frame.
  • the pixel forming unit 10 (i, j) in the i-th row and j-th column performs a positive display in the Nth frame and performs a negative display in the (N + 1) th frame.
  • the potential of the first pixel electrode Epix1 is referred to as a “first pixel potential” and is represented by a symbol Vpix1.
  • the potential of the second pixel electrode Epix2 is referred to as a “second pixel potential”, and is represented by the symbol Vpix2.
  • Vpix1 and Vpix2 may also represent the potentials of the first pixel potentials Vpix1 and Vpix2, respectively.
  • the polarity with respect to the common potential Vcom of the potential of the source line SLj is inverted every horizontal scanning period and every frame.
  • the polarity is reversed between the adjacent source lines SL.
  • the potentials of the first CS line CSL1 and the second CS line CSL2 repeat the high level Vch and the low level Vcl every horizontal scanning period, and the potentials are inverted.
  • the magnitudes of the high level Vch and the low level Vcl may also be represented by Vch and Vcl.
  • the operation in the Nth frame will be described.
  • the first thin film transistor T1 and the second thin film transistor T2 whose gate terminals are connected to the gate line GLi are turned on. Therefore, the video signal potential Vdata (positive polarity) is supplied from the source line SLj to the first pixel electrode Epix1 and the second pixel electrode Epix2, respectively.
  • the video signal potential Vdata is a potential determined according to the display image.
  • the magnitude of the video signal potential Vdata may also be represented by Vdata.
  • the first pixel potential Vpix1 and the second pixel potential Vpix2 in the selection period are given by the following equation (1).
  • the first CS line CSL1 is at the low level Vcl
  • the second CS line CSL2 is at the high level Vch.
  • the first thin film transistor T1 and the second thin film transistor T2 whose gate terminals are connected to the gate line GLi are turned off. For this reason, the first pixel electrode Epix1 and the second pixel electrode Epix2 are in a floating state.
  • the first CS line CSL1 changes to the high level Vch
  • the 2CS line CSL2 changes to the low level Vcl.
  • the first pixel potential Vpix1 changes as shown in the following equation (2).
  • Vpix1 Vdata + ((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc (2)
  • Ctot and ⁇ Vc are given by the following equations (3) and (4), respectively.
  • Ctot Clc1 + CcsA + CcsB + Cp (3)
  • ⁇ Vc Vch-Vcl (4)
  • Cp is a parasitic capacitance in the first subpixel formation unit 10.
  • the parasitic capacitance Cp is formed between the first pixel electrode Epix1 and an electrode (for example, a gate line) that operates at an amplitude or timing different from the potential change of the first CS line CSL1 and the second CS line CSL2.
  • an electrode for example, a gate line
  • Vpix1 Vdata + ((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc- ⁇ Vg (5)
  • Vpix2 Vdata- ⁇ Vg (6)
  • the field through voltage ⁇ Vg is described as not occurring in FIG. 4 and each signal waveform diagram described later.
  • the first CS line CSL1 changes to the low level Vcl
  • the second CS line CSL2 changes to the high level Vch.
  • the first pixel potential Vpix1 changes as in the following equation (7).
  • Vpix1 Vdata- ⁇ Vg (7)
  • the second pixel potential Vpix2 does not change. That is, in the second one horizontal scanning period, the first pixel potential Vpix1 and the second pixel potential Vpix2 are equal to each other.
  • the operation in the first one horizontal scanning period and the operation in the second one horizontal scanning period in the sub-pixel CS driving period are sequentially repeated until the start of the selection period of the (N + 1) th frame.
  • the effective first pixel potential Vpix1 when performing positive display is given by the following equation (8).
  • Vpix1 Vdata + ((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg... (8)
  • the effective second pixel potential Vpix2 when performing a positive display is as shown in Expression (6).
  • the first pixel potential Vpix1 is the same as the pixel potential in the liquid crystal display device that does not have a multi-pixel structure when performing positive display. It turns out that it becomes higher. In this way, when performing positive display, a bright pixel is realized in the first sub-pixel formation unit 11 (i, j) in the i-th row and j-th column, and the second sub-pixel formation unit in the i-th row and j-th column. A dark pixel is realized at 12 (i, j).
  • the operation in the (N + 1) th frame will be described.
  • the first thin film transistor T1 and the second thin film transistor T2 whose gate terminals are connected to the gate line GLi are turned on. Therefore, the video signal potential Vdata (negative polarity) is supplied from the source line SLj to the first pixel electrode Epix1 and the second pixel electrode Epix2, respectively.
  • the first pixel potential Vpix1 and the second pixel potential Vpix2 in the selection period are given by the above formula (1).
  • the first CS line CSL1 is at the high level Vch
  • the second CS line CSL2 is at the low level Vcl.
  • the first thin film transistor T1 and the second thin film transistor T2 whose gate terminals are connected to the gate line GLi are turned off. For this reason, the first pixel electrode Epix1 and the second pixel electrode Epix2 are in a floating state.
  • the first CS line CSL1 changes to the low level Vcl
  • the second CS line CSL2 changes to the high level Vch.
  • the first pixel potential Vpix1 changes as shown in the following equation (9).
  • Vpix1 Vdata-((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc (9)
  • Vpix1 Vdata-((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc- ⁇ Vg (10)
  • the second pixel potential Vpix2 is given by the above equation (6).
  • the first CS line CSL1 changes to the high level Vch
  • the second CS line CSL2 changes to the low level Vcl.
  • the first pixel potential Vpix1 changes as shown in the above equation (7).
  • the second pixel potential Vpix2 does not change. That is, similarly to the Nth frame, the first pixel potential Vpix1 and the second pixel potential Vpix2 are equal to each other in the second horizontal scanning period of the subpixel CS driving period.
  • the operation in the first one horizontal scanning period and the operation in the second one horizontal scanning period in the sub-pixel CS driving period are sequentially repeated until the start of the selection period of the (N + 1) th frame.
  • the effective first pixel potential Vpix1 when performing negative display is given by the following equation (11).
  • Vpix1 Vdata-((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg (11)
  • the effective second pixel potential Vpix2 when performing negative display is as shown in the above equation (6).
  • the potential of the first CS line CSL1 to which the first auxiliary capacitor CcsA is connected changes in the direction in which the first pixel potential Vpix1 is boosted after the selection period when the negative display is performed. For this reason, from the expressions (11) and (6), the first pixel potential Vpix1 is the same as the pixel potential in the liquid crystal display device that does not have the multi-pixel structure when performing negative display. It turns out that it becomes lower than Vpix2.
  • a bright pixel is realized in the first sub-pixel forming unit 11 (i, j) in the i-th row and j-th column, and the second sub-pixel in the i-th row and j-th column is formed.
  • a dark pixel is realized in the section 12 (i, j).
  • connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are switched every column, and the polarity of the source line SLj is inverted every horizontal scanning period and every column. . Therefore, the operation of the pixel formation unit 10 (i, j + 1) in the i row j + 1 column is not illustrated, but the first pixel potential Vpix1 in the operation of the pixel formation unit 10 (i, j) in the i row j column. In addition, the polarity of the second pixel potential Vpix2 is inverted.
  • the operation of the pixel forming unit 10 (i + 1, 1) in the (i + 1) th row and jth column is the same as the first pixel potential Vpix1 and the second pixel potential Vpix2 in the operation of the pixel forming unit 10 (i, j) in the ith row and jth column. And the potential change is delayed by one horizontal scanning period.
  • the operation of the pixel forming unit 10 (i + 1, j + 1) in the (i + 1) th row j + 1 column is the same as the first pixel potential Vpix1 and the second pixel potential Vpix2 in the operation of the pixel forming unit 10 (i + 1,1) in the (i + 1) th row j column.
  • the polarity is reversed.
  • display polarities (referring to the polarities of the first pixel potential Vpix1 and the second pixel potential Vpix2 in the pixel forming portion 10) are different between the pixel forming portions 10 adjacent to each other in the row direction and the column direction. Become a thing. Therefore, in this embodiment, so-called dot inversion driving is performed.
  • a bright pixel is realized by the first subpixel forming unit 11 in each pixel forming unit 10 in both the positive display and the negative display, and the second subpixel forming unit 12 is used.
  • the second pixel potential Vpix2 of the second subpixel forming unit 12 is the same as the potential when the multi-pixel structure is not adopted.
  • the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsA are added to the first subpixel forming unit 11 of the two subpixel forming units constituting the pixel forming unit 10.
  • An auxiliary capacitor CcsB is provided.
  • the relationship between the capacitance values of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB is CcsA> CcsB.
  • Different CS lines are connected to the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB, and the CS line connected to the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB is connected to the first auxiliary capacitor CcsA.
  • the CS lines are switched for each pixel forming portion in the row direction so that the CS lines change in the direction in which the first pixel potential Vpix1 is boosted after the selection period ends. For this reason, in each of the positive polarity display and the negative polarity display, a bright pixel is realized by the first subpixel formation unit 11 and a dark pixel is realized by the second subpixel formation unit 12 in each pixel formation unit 10. . Thereby, the bright pixel and the dark pixel are arranged side by side in the row direction. By arranging the bright pixels and the dark pixels side by side in the row direction, the area ratio between the bright pixels and the dark pixels can be arbitrarily set.
  • the area of the second pixel electrode Epix2 can be set to be larger than the area of the first pixel electrode Epix1 in order to prevent black floating.
  • the present embodiment it is possible to improve the viewing angle characteristics while improving the display quality as compared with the related art. Note that by increasing the first pixel potential Vpix1 using the first CS line CSL1 and the second CS line CSL2, a video signal having a large amplitude for realizing a bright pixel is not required, so that power consumption can be reduced. it can.
  • the second pixel potential Vpix2 of the second subpixel forming unit 12 corresponding to the dark pixel is the same as the potential when the multi-pixel structure is not used, and thus the luminance does not decrease ( (Normally black mode). For this reason, display quality can be further improved.
  • dot inversion driving in units of one pixel
  • the channel layers of the first and second thin film transistors T1 and T2 are formed of an oxide semiconductor. Since the oxide semiconductor has higher mobility than amorphous silicon or the like, the size of the first and second thin film transistors T1 and T2 can be reduced. Therefore, it is possible to improve the aperture ratio of the pixel formation portion 10 and reduce the load on the bus lines (source line SL and gate line GL). The same effect can be obtained when microcrystalline silicon is used for the channel layers of the first and second thin film transistors T1 and T2.
  • FIG. 5 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (eight pixel formation units) in the display unit 100 according to the second embodiment of the present invention.
  • the same referential mark is attached
  • the connection destination of the other end of each of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB in the configuration of the first embodiment is different for each predetermined number of rows (two rows).
  • the first sub-pixel forming unit 11 (i ⁇ 1, j) (not shown) in the (i ⁇ 1) th row and j-th column and the first sub-pixel forming unit 11 in the i-th row and j-th column.
  • the other end of the first auxiliary capacitor CcsA is connected to the first CS line CSL1
  • the other end of the second auxiliary capacitor CcsB is connected to the second CS line CSL2.
  • the other end of the first auxiliary capacitor CcsA is The other end of the second auxiliary capacitor CcsB is connected to the first CS line CSL1.
  • the first auxiliary capacitance CcsA The other end of the second auxiliary capacitor CcsB is connected to the first CS line CSL1, and the other end of the second auxiliary capacitor CcsB is connected to the second CS line CSL2.
  • connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB noted in the j + 1th column the respective connections of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB noted in the jth column.
  • the connection destination at the other end is reversed.
  • the layout in the vicinity of the pixel formation portion is the same as that in the first embodiment, and a description thereof will be omitted.
  • FIG. 6 is a signal waveform diagram for explaining the driving method in the present embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column during the selection period. Note that description of portions common to the first embodiment is omitted as appropriate.
  • the potentials of the first CS line CSL1 and the second CS line CSL2 repeat the high level Vch and the low level Vcl every two horizontal scanning periods. The potentials are inverted from each other.
  • the video signal potential Vdata (positive polarity) is supplied from the source line SLj to the first pixel electrode Epix1 and the second pixel electrode Epix2, respectively.
  • the first CS line CSL1 is at the low level Vcl
  • the second CS line CSL2 is at the high level Vch.
  • the potentials of the first CS line CSL1 and the 2CS line CSL2 do not change in the present embodiment.
  • the video signal potential Vdata (negative polarity) is applied from the source line SLj to the first pixel electrode Epix1 and the second pixel electrode Epix2 of the pixel forming portion 10 (i + 1, j) in the i + 1th row and jth column. Is given.
  • the first CS line CSL1 changes to the high level Vch
  • the second CS line CSL2 changes to the low level Vcl.
  • the first pixel electrode Epix1 changes as shown in the above equation (5).
  • the first CS line CSL1 and the second CS line CSL2 are set in the same manner as the first horizontal scanning period.
  • the potential does not change.
  • the fourth horizontal scanning period (hereinafter referred to as “fourth horizontal scanning period”) of the sub-pixel CS driving period the first CS line CSL1 changes to the low level Vcl, and the second CS line CSL2 changes to the high level. Change to Vch.
  • the first pixel electrode Epix1 changes as shown in the above equation (7).
  • connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are switched every column and every two rows, and the polarity of the source line SLj is changed every horizontal scan period and 1 Invert every column.
  • the operation of the pixel forming unit 10 (i + 1, j) in the (i + 1) th row and jth column is not shown, but the first pixel potential Vpix1 in the operation of the pixel forming unit 10 (i, j) in the ith row / jth column.
  • the polarity of the second pixel potential Vpix2 is inverted, and the portion corresponding to the first one horizontal scanning period of the operation of the pixel forming unit 10 (i, j) in the i-th row and j-th column is omitted.
  • the operation of the pixel formation unit 10 (i + 2, j) in the (i + 2) th row and the jth column is the same as the first pixel potential Vpix1 and the second pixel potential Vpix2 in the operation of the pixel formation unit 10 (i, j) in the ith row and jth column.
  • the potential change is delayed by two horizontal scanning periods.
  • the operation of the pixel forming unit 10 (i + 3, j) in the (i + 3) th row and jth column inverts the polarities of the first pixel potential Vpix1 and the second pixel potential Vpix2 in the operation of the pixel forming unit 10 (i + 2, j).
  • a portion corresponding to the first one horizontal scanning period of the operation of the pixel forming portion 10 (i + 2, j) in the (i + 2) th row and the jth column is omitted.
  • the operation of the j-th row is the polarity reversed in the operation of the i-th row.
  • the display polarities are different between the pixel forming portions 10 adjacent to each other in the row direction and the column direction. That is, in this embodiment, so-called dot inversion driving is performed.
  • the present embodiment in the configuration in which the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are replaced every column and every two rows, the first CS line CSL1 and the second CS line CSL2 By changing the potential every two horizontal scanning periods, the same effect as in the first embodiment can be obtained.
  • the driving frequency of the first CS line CSL1 and the second CS line CSL2 is about 1 ⁇ 2 that of the first embodiment, power consumption can be further reduced.
  • FIG. 7 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (four pixel formation units) in the display unit 100 according to the third embodiment of the present invention.
  • the same referential mark is attached
  • the connection destinations at the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are different for each row in the configuration of the first embodiment. Yes.
  • the other end of the first auxiliary capacitor CcsA is connected to the first CS line CSL1 and the second auxiliary pixel is formed.
  • the other end of the capacitor CcsB is connected to the second CS line CSL2.
  • the other end of the first auxiliary capacitor CcsA is connected to the second CS line CSL2, and the other end of the second auxiliary capacitor CcsB is the first CS. Connected to line CSL1.
  • the other end of the first auxiliary capacitor CcsA is connected to the first CS line CSL1, and the other of the second auxiliary capacitor CcsB.
  • the end is connected to the second CS line CSL2.
  • the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB noted in the j + 1th column the respective connections of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB noted in the jth column. Since the connection destination at the other end is reversed, detailed description thereof is omitted.
  • the layout in the vicinity of the pixel formation portion is the same as that in the first embodiment, and a description thereof will be omitted.
  • FIG. 8 is a signal waveform diagram for explaining the driving method in the present embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column during the selection period. Note that description of portions common to the first embodiment is omitted as appropriate.
  • the polarity of the source line SLj does not change in each frame.
  • the polarity of the source line SLj is positive in the Nth frame and negative in the N + 1th frame.
  • the polarity is reversed between the adjacent source lines SL.
  • the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column in the Nth frame and the (N + 1) th frame is the same as that in the first embodiment as shown in FIG.
  • the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are switched every column and every row, and the polarity of the source line SLj is changed every frame and every column. Invert. Therefore, the operation of the pixel formation unit 10 (i, j + 1) in the i row j + 1 column is not illustrated, but the first pixel potential Vpix1 in the operation of the pixel formation unit 10 (i, j) in the i row j column.
  • the polarity of the second pixel potential Vpix2 is inverted.
  • the operation of the pixel forming unit 10 (i + 1, 1) in the (i + 1) th row and jth column is the same as the first pixel potential Vpix1 and the second pixel potential Vpix2 in the operation of the pixel forming unit 10 (i, j) in the ith row and jth column.
  • the potential change is delayed by one horizontal scanning period.
  • the operation of the pixel forming unit 10 (i + 1, j + 1) in the (i + 1) th row j + 1 column is the same as the first pixel potential Vpix1 and the second pixel potential Vpix2 in the operation of the pixel forming unit 10 (i + 1,1) in the (i + 1) th row j column.
  • the polarity is reversed. That is, in the present embodiment, the display polarities are different between the pixel forming portions 10 adjacent to each other in the row direction, and the display polarities are the same between the pixel forming portions 10 adjacent to each other in the column direction. Therefore, in this embodiment, so-called column inversion driving (referred to as line inversion driving performed in units of source lines SL) can be performed.
  • the polarity of the potential of the source line SL is set to one frame in a configuration in which the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are replaced every column and every row.
  • the same effect as in the first embodiment can be obtained while performing column inversion driving.
  • the drive amplitude within one frame of the source line SL is reduced as compared with the first embodiment, the power consumption can be further reduced.
  • FIG. 9 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (four pixel formation units) in the display unit 100 according to the fourth embodiment of the present invention.
  • the same referential mark is attached
  • two pixel forming portions 10 adjacent to each other in the column direction are connected to two adjacent source lines SL in the third embodiment. .
  • the source terminal of the thin film transistor T2 is connected to the source line SLj of the jth column, whereas the source terminal of the first thin film transistor T1 and the i + 1 in the first subpixel formation unit 11 (i + 1, j) of the (i + 1) th row and jth column.
  • the source terminal of the second thin film transistor T2 in the second subpixel formation portion 12 (i + 1, j) in the row j column is connected to the source line SLj + 1 in the j + 1 column.
  • the second thin film transistor T2 is connected to the j-th source line SLj.
  • the description about the j ⁇ 1th column shown in FIG. 9 is the same as that for the jth column, the j + 1th column source lines SLj and SLj + 1 in the jth column description. Since only the source lines SLj-1 and SLj are replaced, details thereof are omitted.
  • the operation of the pixel forming unit 10 (i, j) in the i-th row and j-th column in the present embodiment is the same as that in the third embodiment.
  • the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are switched every column, and the polarity of the source line SLj is inverted every frame and every column.
  • the two pixel forming portions 10 adjacent to each other in the column direction are respectively connected to two adjacent source lines SL. In other words, the source line SL to which the pixel formation portion is connected is changed every row.
  • the operation of the pixel formation unit 10 (i, j-1) in the i-th row and j-1th column is not shown, but the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column is the first.
  • the polarities of the one pixel potential Vpix1 and the second pixel potential Vpix2 are inverted.
  • the operation of the pixel forming unit 10 (i + 1, j) in the (i + 1) th row and jth column is the same as the operation of the pixel forming unit 10 (i, j) in the ith row and jth column in the first pixel potential Vpix1 and the second pixel potential Vpix2.
  • the potential change is delayed by one horizontal scanning period.
  • the operation of the pixel formation unit 10 (i + 1, j ⁇ 1) in the (i + 1) th row and the (j ⁇ 1) th column is the same as the first pixel potential Vpix1 and the first pixel potential Vpix1 in the operation of the pixel formation unit 10 (i + 1, j) in the (i + 1) th row and the jth column.
  • the polarity of the two-pixel potential Vpix2 is inverted. Therefore, in this embodiment, so-called dot inversion driving is performed.
  • FIG. 10 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (eight pixel formation units) in the display unit 100 in a modification of the present embodiment.
  • the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are further different for each predetermined number of rows (two rows) in the configuration of the fourth embodiment. That is, for example, when attention is paid to the jth column, the first subpixel formation unit 11 (i ⁇ 1, j) in the (i ⁇ 1) th row and jth column and the first subpixel formation unit 11 (i, j in the ith row and jth column).
  • the other end of the first auxiliary capacitor CcsA is connected to the first CS line CSL1, and the other end of the second auxiliary capacitor CcsB is connected to the second CS line CSL2.
  • the other end of the first auxiliary capacitor CcsA is The other end of the second auxiliary capacitor CcsB is connected to the first CS line CSL1.
  • the other end of the one auxiliary capacitor CcsA is connected to the first CS line CSL1
  • the other end of the second auxiliary capacitor CcsB is connected to the second CS line CSL2.
  • the connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB noted in the j ⁇ 1th column are the same as those of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB noted in the jth column.
  • the connection destination of each other end is reversed.
  • FIG. 11 is a signal waveform diagram for explaining a driving method in the present modification. More specifically, it is a signal waveform diagram for explaining the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column during the selection period.
  • the potentials of the first CS line CSL1 and the second CS line CSL2 repeat the high level Vch and the low level Vcl every two horizontal scanning periods. The potentials are inverted from each other.
  • the operation in this modification is the same as the operation in the second embodiment except that the polarity of the source line SLj does not change in each frame, and thus detailed description thereof is omitted. Also in this modified example, since the display polarity is different for each pixel forming portion in the row direction and the column direction, so-called dot inversion driving is performed.
  • the driving frequencies of the first CS line CSL1 and the second CS line CSL2 are higher than those in the fourth embodiment. Reduced. For this reason, power consumption can be reduced.
  • the source line SL to which the pixel forming unit 10 is connected is replaced every line.
  • the present invention is not limited to this.
  • the source line SL to which the pixel forming unit 10 is connected may be replaced every plural rows.
  • the potentials of the first CS line CSL1 and the second CS line CSL2 are inverted every plural horizontal scanning periods. Therefore, also in this case, the driving frequency of the first CS line CSL1 and the second CS line CSL2 is reduced as in the above modification. For this reason, power consumption can be reduced.
  • FIG. 12 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (four pixel formation units) in the display unit 100 according to the fifth embodiment of the present invention.
  • the same referential mark is attached
  • a first auxiliary capacitor CcsA and a second auxiliary capacitor CcsB are further provided in the second subpixel forming unit 12.
  • the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB provided in the first sub-pixel forming unit 11 are referred to as “the first auxiliary capacitor Ccs1A for bright pixels” and “the second auxiliary pixel for bright pixels”, respectively. This is referred to as “auxiliary capacitor Ccs1B”. Further, the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB provided in the second sub-pixel forming unit 12 are referred to as “dark pixel first auxiliary capacitor Ccs2A” and “dark pixel second auxiliary capacitor Ccs2B”, respectively. .
  • Ccs1A, Ccs1B, Ccs2A, and Ccs2B are the capacitances of the first auxiliary capacitor Ccs1A for bright pixels, the second auxiliary capacitor Ccs1B for bright pixels, the first auxiliary capacitor Ccs2A for dark pixels, and the second auxiliary capacitor Ccs2B for dark pixels, respectively. May also represent a value.
  • the configuration of the first subpixel forming unit 11 is the same as that of the first embodiment, and a description thereof will be omitted.
  • two second CS lines CSL2 are provided along each gate line GL. Of these two second CS lines CSL 2, one corresponds to the first subpixel formation unit 11, and the other corresponds to the second subpixel formation unit 12. However, a configuration with one second CS line CSL2 may be employed. Instead of providing two second CS lines CSL2, two first CS lines CSL1 may be provided.
  • each of the dark pixel first auxiliary capacitor Ccs2A and the dark pixel second auxiliary capacitor Ccs2B is connected to the first pixel electrode Epix1.
  • the connection destination of the other end of each of the dark pixel first auxiliary capacitor Ccs2A and the dark pixel second auxiliary capacitor Ccs2B is the same as the connection destination of the bright pixel first auxiliary capacitor Ccs1A and the bright pixel second auxiliary capacitor Ccs1B. It is changed every row.
  • the other end of the dark pixel first auxiliary capacitor Ccs2A is connected to the second CS line CSL2 in the i-th row
  • the other end of the second auxiliary capacitor Ccs2B is connected to the first CS line CSL1 in the i + 1th row
  • the second subpixel formation unit 12 (i, j + 1) in the ith row j + 1th column has the first dark pixel first.
  • the other end of the auxiliary capacitor Ccs2A is connected to the first CS line CSL1 in the (i + 1) th row, and the other end of the second auxiliary capacitor Ccs2B for dark pixels is connected to the second CS line CSL2 in the i-th row.
  • the connection destinations of the other ends of the dark pixel first auxiliary capacitor Ccs2A and the dark pixel second auxiliary capacitor Ccs2B are the same in the second sub-pixel forming portions 12.
  • the connection destination of the other end of the first auxiliary capacitor for dark pixels Ccs2A and the connection destination of the other end of the first auxiliary capacitor for bright pixels Ccs1A are different from each other.
  • the connection destination at the other end of the second auxiliary capacitor Ccs2B is different from the second auxiliary capacitor Ccs1B for bright pixels.
  • FIG. 13 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG. Note that description of portions common to the layout in the first embodiment (such as the layout of the first pixel formation portion 11) is omitted as appropriate.
  • the area facing the second pixel electrode Epix2 in the second CS line CSL2 corresponding to the second subpixel forming unit 12 (hereinafter referred to as “dark pixel CS area”).
  • the area facing the first pixel electrode Epix1 in the second CS line CSL2 corresponding to the first subpixel forming portion 11 (hereinafter referred to as “bright pixel CS area”) is set to be substantially the same.
  • the area of the source metal SE2 that faces the second CS line CSL2 in the i-th row (hereinafter referred to as “third counter area”). ) Is set to be larger than the area of the source metal SE2 facing the first CS line CSL1 of the (i + 1) th row (hereinafter referred to as “fourth counter area”).
  • the dark pixel first auxiliary capacitance Ccs2A is formed in a portion where the source metal SE2 and the second CS line CSL2 in the i-th row overlap each other.
  • the dark pixel second auxiliary capacitance Ccs2B is formed at a portion where the source metal SE2 and the first CS line CSL1 in the (i + 1) th row overlap each other.
  • the third counter area is smaller than the fourth counter area. Is set.
  • the dark pixel second auxiliary capacitance Ccs2B is formed in a portion where the source metal SE2 and the i-th second CS line CSL2 overlap each other.
  • the dark pixel first auxiliary capacitance Ccs2A is formed in a portion where the source metal SE2 and the first CS line CSL1 in the (i + 1) th row overlap each other.
  • the layout of the second subpixel forming unit 12 (i + 1, j) in i + 1 row and j column is that of the second subpixel forming unit 12 (i, j) in i row and j column.
  • the layout of the second subpixel forming unit 12 (i + 1, j + 1) in the i + 1 row j + 1 column is the same as that of the second subpixel forming unit 12 (i, j + 1) in the i row j + 1 column. .
  • FIG. 14 is a signal waveform diagram for explaining the driving method in the present embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column during the selection period. Note that description of portions common to the first embodiment is omitted as appropriate.
  • the first pixel potential Vpix1 has the same potential change as the first embodiment, as in the first embodiment.
  • the potential change of the second pixel potential Vpix2 is obtained by inverting the potential change of the first pixel potential Vpix1 with reference to the video signal potential Vdata (more specifically, Vdata ⁇ Vg) in the sub-pixel CS driving period. It has become.
  • the video signal potential Vdata (positive polarity) is supplied from the source line SLj to the first pixel electrode Epix1 and the second pixel electrode Epix2, respectively.
  • the first CS line CSL1 is at the low level Vcl
  • the second CS line CSL2 is at the high level Vch.
  • the first CS line CSL1 changes to the high level Vch
  • the second CS line CSL2 changes to the low level Vcl.
  • the first pixel potential Vpix1 changes as shown in the following equation (12).
  • Vpix1 Vdata + ((Ccs1A-Ccs1B) / Ctot1) ⁇ ⁇ Vc- ⁇ Vg (12)
  • Ctot1 is given by the following equation (13).
  • Ctot1 Clc1 + Ccs1A + Ccs1B + Cp1 (13)
  • Cp1 is a parasitic capacitance in the first subpixel formation unit 11.
  • the parasitic capacitance Cp1 is formed between the first pixel electrode Epix1 and an electrode (for example, a gate line) that operates at an amplitude or timing different from the potential change of the first CS line CSL1 and the second CS line CSL2.
  • ⁇ Vc is given by the above equation (4).
  • Vpix2 Vdata-((Ccs2A-Ccs2B) / Ctot2) ⁇ ⁇ Vc- ⁇ Vg (14)
  • Ctot2 is given by the following equation (15).
  • Ctot2 Clc2 + Ccs2A + Ccs2B + Cp2 (15)
  • Cp2 is a parasitic capacitance in the second subpixel forming unit 12.
  • the parasitic capacitance Cp2 is formed between the second pixel electrode Epix2 and an electrode (for example, a gate line) that operates at an amplitude or timing different from the potential change of the first CS line CSL1 and the second CS line CSL2.
  • an electrode for example, a gate line
  • the first pixel potential Vpix1 and the second pixel potential Vpix2 change in the positive and negative directions.
  • the first CS line CSL1 changes to the low level Vcl
  • the second CS line CSL2 changes to the high level Vch. Therefore, the first pixel potential Vpix1 and the second pixel potential Vpix2 change as shown in the above formulas (7) and (6), respectively. That is, in the second one horizontal scanning period, the first pixel potential Vpix1 and the second pixel potential Vpix2 are equal to each other.
  • Vpix1 Vdata + ((Ccs1A-Ccs1B) / Ctot1) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg (16)
  • Vpix2 Vdata-((Ccs2A-Ccs2B) / Ctot2) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg (17)
  • the first CS line CSL1 which is the connection destination of the first auxiliary capacitor Ccs1A for bright pixels and the second auxiliary capacitor Ccs2B for dark pixels, is connected to the first pixel potential Vpix1 and the second pixel potential.
  • the second CS line CSL2 to which the second auxiliary capacitor Ccs1B for bright pixels and the first auxiliary capacitor Ccs2A for dark pixels are connected has the first pixel potential Vpix1 and the second pixel potential Vpix2.
  • the potential changes in the direction of decreasing the voltage.
  • the first pixel potential Vpix1 is higher than the second pixel potential Vpix2 when the positive display is performed.
  • a bright pixel is realized in the first sub-pixel formation unit 11 (i, j) in the i-th row and j-th column, and the second sub-pixel formation unit in the i-th row and j-th column.
  • a dark pixel is realized at 12 (i, j).
  • the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that in the first embodiment.
  • Vpix1 Vdata-((Ccs1A-Ccs1B) / Ctot1) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg (18)
  • Vpix2 Vdata + ((Ccs2A-Ccs2B) / Ctot2) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg (19)
  • the first CS line CSL1 which is the connection destination of the first auxiliary capacitor Ccs1A for the bright pixel and the second auxiliary capacitor Ccs2B for the dark pixel, is increased in the direction in which the first pixel potential Vpix1 is boosted.
  • the potential of the second CS line CSL2 which is the connection destination of the first auxiliary capacitor Ccs1B for the bright pixel and the first auxiliary capacitor Ccs2A for the dark pixel, changes in the direction in which the first pixel potential Vpix1 is stepped down.
  • the first pixel potential Vpix1 is lower than the second pixel potential Vpix2 when the negative display is performed.
  • a bright pixel is realized in the first sub-pixel formation unit 11 (i, j) in the i-th row and j-th column, and the second sub-pixel formation unit in the i-th row and j-th column.
  • a dark pixel is realized at 12 (i, j).
  • the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that in the first embodiment.
  • dot inversion driving is performed as in the first embodiment.
  • the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 in the subpixel CS driving period is larger than that in the first embodiment.
  • the luminance difference between the first subpixel forming unit 11 and the second subpixel forming unit 12 is larger than that in the first embodiment.
  • FIG. 15 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (four pixel formation units) in the display unit 100 according to the sixth embodiment of the present invention.
  • the same referential mark is attached
  • the connection destination of the other end of the dark pixel first auxiliary capacitor Ccs2A and the other end of the dark pixel second auxiliary capacitor Ccs2B are connected.
  • FIG. 16 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG. Note that description of portions common to the layout in the first embodiment or the fifth embodiment is omitted as appropriate.
  • the dark pixel CS area is set smaller than the bright pixel CS area.
  • the third facing area is set smaller than the fourth facing area.
  • the dark pixel second auxiliary capacitance Ccs2B is formed in a portion where the source metal SE2 and the i-th row second CS line CSL2 overlap each other.
  • the dark pixel first auxiliary capacitance Ccs2A is formed in a portion where the source metal SE2 and the first CS line CSL1 in the (i + 1) th row overlap each other.
  • the fourth facing area is smaller than the first facing area.
  • the third counter area is substantially the same as the second counter area.
  • the third facing area is set larger than the fourth facing area.
  • the dark pixel first auxiliary capacitance Ccs2A is formed in a portion where the source metal SE2 and the second-th CS line CSL2 in the i-th row overlap each other.
  • the dark pixel second auxiliary capacitance Ccs2B is formed at a portion where the source metal SE2 and the first CS line CSL1 in the (i + 1) th row overlap each other.
  • the fourth facing area is substantially the same as the first facing area.
  • the third counter area is smaller than the second counter area.
  • the layout of the second subpixel forming unit 12 (i + 1, j + 1) in the i + 1 row j + 1 column is the same as that of the second subpixel forming unit 12 (i, j + 1) in the i row j + 1 column. .
  • FIG. 17 is a signal waveform diagram for explaining the driving method in the present embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column during the selection period. Note that description of portions common to the first embodiment is omitted as appropriate.
  • the operation in the present embodiment is the same as the potential change in the first pixel potential Vpix1 in the second pixel potential Vpix2 during the sub-pixel CS drive period in the operation in the fifth embodiment.
  • the direction is smaller than the potential change of the first pixel potential Vpix1. Since the potential change of the first pixel potential Vpix1 is the same as that of the fifth embodiment, the following description focuses on the potential change of the second pixel potential Vpix2.
  • Vpix2 Vdata + ((Ccs2A-Ccs2B) / Ctot2) ⁇ ⁇ Vc- ⁇ Vg (20)
  • the first CS line CSL1 changes to the low level Vcl
  • the second CS line CSL2 changes to the high level Vch.
  • the second pixel potential Vpix2 changes as shown in the above equation (6) as in the fifth embodiment.
  • Vpix2 Vdata + ((Ccs2A-Ccs2B) / Ctot2) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg (21)
  • the first CS line CSL1 to which the first auxiliary capacitor Ccs1A for bright pixels and the first auxiliary capacitor Ccs2A for dark pixels are connected is connected to the first pixel potential Vpix1 and the second pixel potential.
  • the second CS line CSL2 to which the second auxiliary capacitor Ccs1B for bright pixels and the second auxiliary capacitor Ccs2B for dark pixels are connected has the first pixel potential Vpix1 and the second pixel potential.
  • Vpix2 Vdata-((Ccs2A-Ccs2B) / Ctot2) ⁇ ⁇ Vc ⁇ (1/2) - ⁇ Vg (22)
  • the first CS line CSL1 which is the connection destination of the first auxiliary capacitor Ccs1A for bright pixels and the first auxiliary capacitor Ccs2A for dark pixels, is connected to the first pixel potential Vpix1 and the second pixel potential.
  • the second CS line CSL2 to which the second auxiliary capacitor Ccs1B for bright pixels and the second auxiliary capacitor Ccs2B for dark pixels are connected has the first pixel potential Vpix1 and the second pixel potential.
  • boosting is performed not only at the first pixel potential Vpix1 but also at the second pixel potential Vpix2, and the first pixel potential Vpix1 is boosted more than the second pixel potential Vpix2. For this reason, it is possible to reduce the drive amplitude of the source line while realizing a bright pixel by the first subpixel forming unit 11 and a dark pixel by the second subpixel forming unit 12. Thereby, low power consumption can be achieved.
  • FIG. 18 is a block diagram showing the overall configuration of an active matrix display device according to the seventh embodiment of the present invention.
  • the same referential mark is attached
  • the liquid crystal display device according to the present embodiment includes a CS driver 500 as an auxiliary capacitance line driving circuit in addition to the components in the first embodiment.
  • the first CS bus line CB1 and the second CS bus line CB2 are not provided.
  • the display control circuit 200 outputs a CS start pulse signal CCP and a CS clock signal CCK for controlling the operation of the CS driver 500 instead of outputting the first auxiliary capacitance signal and the second auxiliary capacitance signal.
  • the CS driver 500 receives the CS start pulse signal CCP and the CS clock signal CCK output from the display control circuit 200, and drives the first CS line CSL1 and the second CS line CSL2 of each row.
  • the first CS line and the second CS line in the i-th row are represented by reference signs “CSL1 (i)” and “CSL2 (i)”, respectively.
  • the first CS lines CSL1 in each row in this embodiment are driven independently.
  • the second CS line CSL2 of each row is driven independently.
  • FIG. 19 is an equivalent circuit diagram illustrating a configuration of a part of the pixel formation units (four pixel formation units) in the display unit 100 in the present embodiment.
  • the configuration of the pixel formation portion in this embodiment is basically the same as that in the first embodiment (the reference numbers of the first CS line and the second CS line are different). Omitted.
  • the layout in the vicinity of the pixel formation portion is the same as that in the first embodiment, and a description thereof will be omitted.
  • FIG. 20 is a signal waveform diagram for explaining the driving method in the present embodiment. More specifically, it is a signal waveform diagram for explaining the operation of the pixel formation unit 10 (i, j) in the i-th row and j-th column during the selection period. Note that description of portions common to the first embodiment is omitted as appropriate. Since each first CS line CSL1 and each second CS line CSL2 in the present embodiment are driven by a CS driver 500, as shown in FIG. 20, the potential change of the first CS line CSL1 and the second CS line CSL2 is the first It is different from the embodiment.
  • the potentials of the first CS line CSL1 and the second CS line CSL2 of the row change, and these potentials are changed in the sub-pixel CS driving period (that is, in the selection period of the next frame). Until the start).
  • the change in the second pixel potential Vpix2 is the same as in the first embodiment, and a description thereof will be omitted.
  • the potential control step is executed by the CS driver 500.
  • the video signal potential Vdata (positive polarity) is supplied from the source line SLj to the first pixel electrode Epix1 and the second pixel electrode Epix2, respectively.
  • the i-th first CS line CSL1 (i) is at the low level Vcl
  • the i-th second CS line CSL2 (i) is at the high level Vch.
  • the i-th first CS line CSL1 (i) changes to the high level Vch, and the i-th second CS line CSL2 (i) is low. It changes to level Vcl.
  • the first pixel potential Vpix1 changes as in the above equation (5).
  • the first pixel potential Vpix1 maintains the potential expressed by the above formula (5). That is, the effective first pixel potential Vpix1 when performing positive display in the present embodiment is given by the following equation (23).
  • Vpix1 Vdata + ((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc- ⁇ Vg (23)
  • the potential of the first CS line CSL1 to which the first auxiliary capacitor CcsA is connected changes in the direction in which the first pixel potential Vpix1 is boosted after the selection period when the positive display is performed. For this reason, from the expressions (23) and (6), the first pixel potential Vpix1 is the same as the pixel potential in the liquid crystal display device that does not have the multi-pixel structure when performing positive display. It turns out that it becomes higher than Vpix2.
  • a bright pixel is realized in the first sub-pixel formation unit 11 (i, j) in the i-th row and j-th column, and the second sub-pixel formation unit in the i-th row and j-th column.
  • a dark pixel is realized at 12 (i, j).
  • the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that in the first embodiment.
  • Vpix1 Vdata-((CcsA-CcsB) / Ctot) ⁇ ⁇ Vc- ⁇ Vg (24)
  • the potential of the first CS line CSL to which the first auxiliary capacitor CcsA is connected changes in the direction in which the first pixel potential Vpix1 is boosted after the selection period when the negative display is performed. Therefore, from the equations (24) and (6), the first pixel potential Vpix1 is the same as the pixel potential in the liquid crystal display device that does not have a multi-pixel structure when performing negative display. It turns out that it becomes lower than Vpix2.
  • a bright pixel is realized in the first sub-pixel forming unit 11 (i, j) in the i-th row and j-th column, and the second sub-pixel in the i-th row and j-th column is formed.
  • a dark pixel is realized in the section 12 (i, j).
  • the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 is larger than that in the first embodiment.
  • connection destinations of the other ends of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are switched every column, and the polarity of the source line SLj is inverted every horizontal scanning period and every column. .
  • the display polarities are different between the pixel forming portions 10 adjacent to each other in the row direction and the column direction. Therefore, in this embodiment, so-called dot inversion driving is performed as in the first embodiment.
  • a bright pixel is realized by the first subpixel forming unit 11 in each pixel forming unit 10 in both the positive display and the negative display, and the second subpixel forming unit 12 is used.
  • the second pixel potential Vpix2 of the second subpixel forming unit 12 is the same as the potential when the multi-pixel structure is not adopted.
  • the same effect as in the first embodiment can be obtained in the aspect in which the first CS line CSL1 and the second CS line CSL2 are driven using the CS driver 500.
  • the second pixel potential Vpix2 of the second subpixel formation unit 12 is the same as the potential when the multi-pixel structure is not adopted, and the potential difference between the first pixel potential Vpix1 and the second pixel potential Vpix2 in the subpixel CS driving period. Is larger than that of the first embodiment. As a result, it is possible to further suppress black floating while suppressing a decrease in luminance of the second subpixel forming unit 12 corresponding to the dark pixel.
  • FIG. 21 is an equivalent circuit diagram showing a configuration of the pixel formation unit 10 (i, j) in the i-th row and the j-th column in the eighth embodiment of the present invention.
  • the same referential mark is attached
  • a third CS line CSL3 as a third auxiliary capacitance line is provided along each gate line GL, and a second subpixel forming unit is provided.
  • auxiliary capacitor CcsC as an adjustment capacitor.
  • a predetermined fixed potential is applied to the third CS line CSL3.
  • One end of the third auxiliary capacitor CcsC is connected to the second pixel electrode Epix2, and the other end is connected to the third CS line CSL3.
  • Parasitic capacitance is formed in the pixel forming unit 10. For example, as shown in FIG. 21, a first parasitic capacitance Cgdt1 is formed between the gate and drain of the first thin film transistor T1, and a second parasitic capacitance Cgdt2 is formed between the gate and drain of the second thin film transistor T2.
  • parasitic capacitance may be formed in other locations, but illustration is omitted here for convenience. Due to the presence of these parasitic capacitances, the first pixel potential Vpix1 and the second pixel potential Vpix2 change when the gate line GL switches from the selected state to the non-selected state (at the end of the selection period).
  • the above-described field through voltage ⁇ Vg is generated in the first pixel electrode Epix1 and the second pixel electrode Epix2.
  • the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are connected to the first pixel electrode Epix1, while they are not connected to the second pixel electrode Epix2, the first pixel electrode Epix1 and the second auxiliary capacitor CcsB are connected.
  • Field through voltages ⁇ Vg generated in the two pixel electrodes Epix2 are different from each other.
  • the third auxiliary capacitor CcsC is provided to suppress such variation in potential fluctuation.
  • Cgdt1 / (CcsA + CcsB + Clc1 + Cp1) Cgdt2 / (CcsC + Clc2 + Cp2) (25)
  • Cp1 is a parasitic capacitance other than the first parasitic capacitance Cgdt1 formed in the first subpixel formation unit 11
  • Cp2 is other than the second parasitic capacitance Cgdt2 formed in the second subpixel formation unit 12. Parasitic capacitance.
  • Cgdt1 and Cgdt2 are the potential change of the gate line GL at the end of the selection period and the field through voltage ⁇ Vg at the first pixel electrode Epix1 due to the first parasitic capacitance Cgdt1, and the gate line GL at the end of the selection period.
  • the field-through voltage ⁇ Vg at the second pixel electrode Epix2 due to the potential change and the second parasitic capacitance Cgdt2 is set to be substantially equal to each other.
  • FIG. 22 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG. Note that description of portions common to the layout in the first embodiment is omitted.
  • the third auxiliary capacitor CcsC is formed at a portion where the source metal SE2 and the third CS line CSL3 (gate metal) overlap each other.
  • FIG. 23 is an equivalent circuit diagram illustrating a configuration of the pixel formation unit 10 (i, j) in the i-th row and the j-th column in a modification example of the present embodiment.
  • the same referential mark is attached
  • a first adjustment capacitor Cgd1 and a second adjustment capacitor Cgd2 are provided instead of the third CS line CSL3 and the third auxiliary capacitor CcsC.
  • first adjustment capacitor Cgd1 is connected to the first pixel electrode Epix1, and the other end is connected to the gate line GLi.
  • One end of the second adjustment capacitor Cgd2 is connected to the second pixel electrode Epix2, and the other end is connected to the gate line GLi.
  • the first adjustment capacitor Cgd1 and the second adjustment capacitor Cgd2 are potential fluctuations of the first pixel potential Vpix1 and the second pixel potential Vpix2 at the end of the selection period of the gate line GL. It is provided in order to suppress the non-uniformity of.
  • Cgdt1 + Cgd1) / (CcsA + CcsB + Clc1 + Cp1) (Cgdt2 + Cgd2) / (Clc2 + Cp2) (26)
  • Cgd1 and Cgd2 are the potential change of the gate line GL at the end of the selection period and the field through voltage ⁇ Vg at the first pixel electrode Epix1 due to the first parasitic capacitance Cgdt1, and the gate line GL at the end of the selection period.
  • the field-through voltage ⁇ Vg at the second pixel electrode Epix2 due to the potential change and the second parasitic capacitance Cgdt2 is set to be substantially equal to each other.
  • FIG. 24 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG. Note that description of portions common to the layout in the first embodiment is omitted.
  • part of the gate line GL (gate metal) other than the portion where the first thin film transistor T1 and the second thin film transistor T2 are provided overlaps the source metal SE1 and the source metal SE2.
  • a first adjustment capacitor Cgd1 is formed at a portion where the source metal SE1 and the gate line GL overlap each other
  • a second adjustment capacitor Cgd2 is formed at a portion where the source metal SE2 and the gate line GL overlap each other.
  • a third auxiliary capacitor CcsC a first adjustment capacitor Cgd1, and a second adjustment capacitor Cgd2 may be provided.
  • FIG. 25 is an equivalent circuit diagram showing a configuration of the pixel formation unit 10 (i, j) in the i-th row and the j-th column in the ninth embodiment of the present invention.
  • the same referential mark is attached
  • the first thin film transistor T1 and the second thin film transistor T2 are arranged in parallel.
  • the first thin film transistor T1 and the second thin film transistor T2 are arranged in series. ing.
  • the source terminal (first conduction terminal) of the second thin film transistor T2 is connected to the source line SLj via the first thin film transistor T1.
  • the first thin film transistor T1 and the second thin film transistor T2 share the drain terminal (second conduction terminal) of the first thin film transistor T1 and the source terminal of the second thin film transistor T2.
  • the pixel formation units other than the pixel formation unit 10 (i, j) in the i-th row and j-th column have the same configuration.
  • the source terminal of the first thin film transistor T1 may be connected to the source line SLj via the second thin film transistor T1 without being limited to the configuration illustrated in FIG. That is, the first thin film transistor T1 and the second thin film transistor T2 may share the source terminal of the first thin film transistor T1 and the drain terminal of the second thin film transistor T2.
  • FIG. 26 is a diagram for explaining the layout of the first thin film transistor T1 and the second thin film transistor T2 in the present embodiment. More specifically, FIG. 26A is a plan view showing a layout of the first thin film transistor T1 and the second thin film transistor T2. FIG. 26B is a cross-sectional view taken along the line AA in FIG. In the layout of each of the above embodiments, the first thin film transistor T1 and the second thin film transistor T2 are arranged in parallel (see FIGS. 3, 13, 16, 22, and 24). However, in the present embodiment, as shown in FIG. 26A, the first thin film transistor T1 and the second thin film transistor T2 are arranged in series. As shown in FIG.
  • the first thin film transistor T1 and the second thin film transistor T2 are arranged in series in the first thin film transistor T1 and the second thin film transistor T2, and the first thin film transistor T1 and the first thin film transistor T1. 2 Realized by a configuration sharing the source terminal (first conduction terminal) of the thin film transistor T2.
  • the channel layer 13b is shared by the first thin film transistor T1 and the second thin film transistor T2, but such sharing of the channel layer 13 is not essential.
  • a gate insulating film 13a is formed between the channel layer 13a and the gate line GL.
  • the source line SL and the gate line GL are closer to each other in the vicinity of the first thin film transistor T1 and the second thin film transistor T2 than when they are arranged in parallel.
  • the areas where they overlap each other can be reduced (see FIGS. 26A, 3, 13, 16, 22, and 24). For this reason, the parasitic capacitance formed between the source line SL and the gate line GL becomes relatively small.
  • the current supplied to the second pixel electrode Epix2 via the source metal SE2 is supplied to the first pixel electrode Epix1 via the source metal SE1. May be lower than the current applied.
  • a semiconductor with high mobility such as an oxide semiconductor or microcrystalline silicon for the channel layer 13b
  • charging of the second pixel electrode Epix2 due to a decrease in current supplied via the source metal SE2 is prevented. Can be resolved.
  • the pixel capacitance of the first subpixel formation unit 11 for example, Clc1 + CcsA + CcsB in the first embodiment
  • the pixel capacitance of the second subpixel formation unit 12 for example, in the first embodiment, in the case of Clc2
  • the first pixel electrode Epix1 is connected to the source metal SE1
  • the second subpixel formation unit 12 when the pixel capacitance is larger, it is preferable to connect the second pixel electrode Epix2 to the source metal SE1.
  • the parasitic capacitance formed between the source line SL and the gate line GL becomes relatively small. For this reason, since the capacity
  • the present embodiment can be applied to each of the above embodiments.
  • the polarity inversion drive is performed by changing the polarity of the potential for each of a predetermined number (first predetermined number) of video signal lines in at least the row direction, and the first auxiliary capacitor CcsA and the first The connection destination of the other end of each of the two auxiliary capacitors CcsB is switched for each predetermined number of columns in the row direction, and when the positive polarity is displayed, the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are connected after the selection period of the gate line GL.
  • the potential of the other end of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB decreases and rises after the selection period of the gate line GL, respectively, when the negative potential is displayed. Change to Thereby, column inversion driving can be performed for at least a predetermined number of columns.
  • the present invention can be applied to a display device having a configuration in which one pixel is divided into a plurality of sub-pixels and a driving method thereof in order to improve viewing angle characteristics.
  • SYMBOLS 10 Pixel formation part 11 ... 1st subpixel formation part 12 ... 2nd subpixel formation part 13b ... Channel layer 100 ... Display part 200 ... Display control circuit 300 ... Source driver 400 ... Gate driver 500 ... CS driver (auxiliary capacitance line) Drive circuit) SL ... Source line (video signal line) GL: Gate line (scanning signal line) CSL1 to CSL3... First to third auxiliary capacitance lines Epix1, Epix2... First and second pixel electrodes Clc1, Clc2... First and second liquid crystal capacitances CcsA, Ccs1A.
  • CcsB, Ccs1B second auxiliary capacitance, second auxiliary capacitance for bright pixels
  • Ccs2A first auxiliary capacitance for dark pixels (third auxiliary capacitance)
  • Ccs2B dark pixel second auxiliary capacitance (fourth auxiliary capacitance)
  • CcsC Third auxiliary capacity (adjustment capacity)
  • First and second thin film transistors first and second switching elements

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

La présente invention porte sur un dispositif d'affichage qui peut améliorer des caractéristiques d'angle d'observation tout en augmentant une qualité d'affichage par rapport au dispositif classique. Une unité formant pixel (10) comprend de première et seconde unités formant sous-pixel (11, 12). La première unité formant sous-pixel (11) comprend un premier transistor en couches minces (T1), une première électrode de pixel (Epix1), un premier condensateur de cristaux liquides (Clc1), un premier condensateur auxiliaire (CcsA) et un second condensateur auxiliaire (CcsB), où CcsA > CcsB. Une extrémité de chacun des premier et second condensateurs auxiliaires (CcsA, CcsB) est reliée à la première électrode de pixel (Epix1). La destination de liaison de l'autre extrémité de chacun des premier et second condensateurs auxiliaires (CcsA, CcsB) est une première ligne CS (CSL1) ou une seconde ligne CS (CSL2). L'autre destination de liaison d'extrémité aux premier et second condensateurs auxiliaires (CcsA, CcsB) change en alternance pour chaque colonne. La seconde partie formant sous-pixel (12) comprend un second transistor en couches minces (T2), une seconde électrode de pixel (Epix2) et un second condensateur de cristaux liquides (Clc2).
PCT/JP2012/078435 2011-11-10 2012-11-02 Dispositif d'affichage et son procédé de commande WO2013069559A1 (fr)

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WO2015170614A1 (fr) * 2014-05-07 2015-11-12 ソニー株式会社 Dispositif d'affichage et appareil électronique
CN111856826A (zh) * 2019-04-25 2020-10-30 堺显示器制品株式会社 液晶显示装置

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WO2007091365A1 (fr) * 2006-02-06 2007-08-16 Sharp Kabushiki Kaisha Dispositif d'affichage, substrat de matrice active, dispositif d'affichage à cristaux liquides et récepteur de télévision
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WO2015170614A1 (fr) * 2014-05-07 2015-11-12 ソニー株式会社 Dispositif d'affichage et appareil électronique
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US10593704B2 (en) 2014-05-07 2020-03-17 Sony Corporation Display device with pixel circuit having integrally arranged drive and control transistor channel portions
US11195860B2 (en) 2014-05-07 2021-12-07 Sony Group Corporation Display unit and electronic apparatus
US11798951B2 (en) 2014-05-07 2023-10-24 Sony Group Corporation Display device with pixel and channel region arrangements
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CN111856826A (zh) * 2019-04-25 2020-10-30 堺显示器制品株式会社 液晶显示装置

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