WO2013066146A1

WO2013066146A1 - Dark count elimination

Info

Publication number: WO2013066146A1
Application number: PCT/MY2012/000181
Authority: WO
Inventors: Firdaus Hj Yaakob WIRA; Che Lah HANIF; Witjaksono Gunawan; Siswanto Meilana
Original assignee: Mimos Berhad
Priority date: 2011-11-03
Filing date: 2012-06-29
Publication date: 2013-05-10

Abstract

The present invention relates to a processing unit and, more particularly, to a dark count elimination method applied to a quantum random signal refinement. One of the advantages of the processing unit of the present invention is capable for dark count elimination for dark counts which are not consistent and same shape. Another advantage of the present invention is that it is a Register Transfer Level (RTL) hardware based to detect and eliminate photon dark count signals.

Description

DARK COUNT ELIMINATION

FIELD OF THE INVENTION

The present invention relates to a processing unit and, more particularly, to a dark count elimination method applied to a quantum random signal refinement.

BACKGROUND OF THE INVENTION

In the field of photon detection, an avalanche photodiode (hereinafter, referred to as APD) is generally used as an element for detecting a single photon. A basic photon detection technique is as follows. A reverse-bias voltage not less than an APD breakdown voltage (VBd) is applied to an APD so that the multiplication factor of the APD is increased to an extremely large value, whereby a photocurrent triggered by a single photon is amplified to such an extent that the signal amplitude becomes large enough for an external circuit to be able to process the signal.

Dark count is a phenomenon when a detection signal is measured in the absence of an incident photon. It is also known as pulse noise or false signal. Avalanche Photodiode (APD) has an inherence dark count as natural phenomena. This signal that is in pulse- shaped is detected at the single-photon detector circuit even though the APD circuit has been switched off. The APD circuit is a circuit that converts detected photons into electrical pulses. This conversion process is required before the digital processing. The detected dark count signal is generated and transmitted to the digital modules, and then the digital modules produce and transmit false random numbers to the host. Therefore, an inaccuracy and irregular randomness on the binary sequences have been generated. Furthermore, with irregular randomness on the binary sequences generated, errors are occurred in the generated crypto key at a later stage.

Some prior arts have suggested a solution to overcome these issues, such as shown in prior art of US Patent No. 7,560,683 where a dark count is eliminated by using two approaches; i.e. the use of a pulse noise mask signal that indicates the timing of occurrence of a pulse noise to eliminate the pulse noise and the use of average pulse signal to eliminate pulse noise by subtracting it to the estimated pulse noise from the APD output signal. The drawback of the prior art as it is tied to the expectation that the waveform of pulse noise which always in the same shape. There is a need for a processing unit that is capable for dark count elimination for dark counts which are not consistent and same shape. The present invention overcomes these and other deficiencies of the above-mentioned drawbacks by providing a processing unit that is capable for dark count elimination. The invention provides a considerable reduction of materials with even greater efficiency and economically during operation.

SUMMARY OF THE INVENTION

The present invention provides a processing unit with dark count signals elimination in a random number generator system comprising a digital module for acquiring data and whitening data to produce a binary random source; a linear feedback shift register for randomizing the binary random source into a random number; characterized in that a signal interval detection for determining a dark count signal in the acquired data; and a dark count filtering for filtering the dark count signal determined by the signal interval detection. A processing unit is a digital processing unit located inside a quantum random number generator system and the signal interval detection comprising a digital counter for determining a period of time detected signal and comparing with a predetermined threshold signal value; if the period of time detected signal more than the predetermined threshold signal value and a dark count signal detected, a dark count flag is activated as an input for the dark count filtering; and if the period of time detected signal less than the predetermined threshold signal value and a dark count signal is not detected, a real count flag is activated as an input for the dark count filtering.

The signal interval detection of the present invention having two pulse detected counters for counting pulses due to dark counts and the dark count filtering comprising a multiplexer for selecting and determining the period of time detected signal for a dark count signal from the signal interval detection; generating a logic '0' upon filtering the dark count signal and sending the logic '0' to an output serial module; and sending a binary random number to an output serial module if no dark count signal detected. Both the signal interval detection and dark count filtering are implemented in an embedded system device.

A method of operating a processing unit with dark count signals elimination in a random number generator system comprising acquiring a digital signal from a analog to digital converter; detecting the digital signal by acquisition module and signal interval detection simultaneously; producing a binary source and restoring the binary source to be a binary random number using a linear feedback register; determining a period of time detected signal by a signal interval detection and comparing with a predetermined threshold signal value; activating a dark count flag in a dark count filtering if the period of time detected signal more than the predetermined threshold signal value; generating a logic '0' and sending the logic '0' to an output serial module; activating a real count flag in a dark count filtering if the period of time detected signal less than the predetermined threshold signal value; and sending a binary random number to an output serial module.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Figure 1 illustrates a Quantum Random Signal Refinement (Q-RSR) system having a processing unit with Signal Interval Detection (SID) and Dark Count Filtering (DCF) in accordance of an embodiment of the present invention.

Figure 2 illustrates all modules in a processing unit with Signal Interval Detection (SID) and Dark Count Filtering (DCF) in accordance of an embodiment of the present invention. Figure 3 illustrates main modules of Dark Count Filtering (DCF) in a processing unit in accordance of an embodiment of the present invention.

Figure 4 illustrates a flowchart of the Quantum Random Signal Refinement (Q-RSR) system in accordance of an embodiment of the present invention. Figure 5 illustrates a flowchart of Signal Interval Detection (SID) process in a processing unit in accordance of an embodiment of the present invention.

Figure 6 illustrates a flowchart of Dark Count Filtering (DCF) process in a processing unit in accordance of an embodiment of the present invention.

DETAILED DESCRIPTIONS OF THE INVENTION

The present invention will now be described in detail in connection with specific embodiments with reference to the accompanying drawings. Unless the context requires otherwise, throughout the specification and claims which follow, the word "comprise" and variations thereof, such as, "comprises" and "comprising" are to be construed in an open, inclusive sense that is as "including, but not limited to". Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity. Furthermore, in those instances where a convention analogous to "at least one of A, B and C," etc. is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B and C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B and C together, etc.). In those instances where a convention analogous to "at least one of A, B or C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, or C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

The present invention relates to a Register Transfer Level (RTL) hardware based used to detect and eliminate photon dark count signals. Figure 1 illustrates a Quantum Random Signal Refinement (Q-RSR) system (100) having a processing unit (125) with Signal Interval Detection (SID) (150) and Dark Count Filtering (DCF) (160). Unlike the conventional Quantum Random Signal Refinement (Q-RSR) system (100) without dark count elimination which only comprising an optical component (110), an analog part (120), a processing unit and a serial module(170), the processing unit (125) of the present invention comprising a digital module (140) for acquiring data and whitening data to produce a binary random source, a linear feedback shift register (LFSR) for randomizing the binary random source into a random number, a signal interval detection (150) for determining a dark count signal in the acquired data and a dark count filtering (160) for filtering the dark count signal determined by the signal interval detection (150). The processing unit (130) of the present invention is a digital processing unit located inside a quantum random number generator system.

Figure 2 illustrates all modules in a processing unit (200) with Signal Interval Detection (SID) and Dark Count Filtering (DCF) in accordance of an embodiment of the present invention. During the data conversion from analog(from optical component (210) connected to analog process(220)) to digital, signals from the pulses of detected photons are going through a conventional process such as acquisition (230), whitening (240), restoring process (260) with the assistance of the linear feedback shift register (LFSR) (250) for randomizing the binary random source into a random number. For the purposes of eliminating the dark count in the data collected, Signal Interval Detection (SID) and Dark Count Filtering (DCF) are provided. Signal Interval Detection (SID) (270) is connected to the input of the detection signals module and subsequently connected to dark count filtering (290). The signal interval detection (SID) (270) comprising a digital counter for determining a period of time detected signal and comparing with a predetermined threshold signal value. If the period of time detected signal more than the predetermined threshold signal value and a dark count signal detected, a dark count flag is activated as an input for the dark count filtering (290) and if the period of time detected signal less than the predetermined threshold signal value and a dark count signal is not detected, a real count flag is activated as an input for the dark count filtering (290). Logic '0' is generated by register '0' binary signals (280) upon filtering the dark count signal and sending the logic 0 to an output serial module (291). Figure 3 illustrates main modules of Dark Count Filtering (DCF) in a processing unit in accordance of an embodiment of the present invention. The dark count filtering comprising a multiplexer (300) for selecting and determining the period of time detected signal for a dark count signal from the signal interval detection, generating a logic Ό' upon filtering the dark count signal and sending the logic '0' to an output serial module; and sending a binary random number to an output serial module if no dark count signal detected.

Figure 4 illustrates a flowchart of the Quantum Random Signal Refinement (Q-RSR) system in accordance of an embodiment of the present invention. When the Avalanche Photodiode (APD) circuit is being activated, a true random processing module begins to receive pulses of detected photons. These pulses are then measured and processed before being transmitted to a host through a serial module. The serial data transferred to the host are collected using terminal software. The data is then tested using NIST software to ensure that the generated random number is a truly random. During transferring a signal (data) to serial module, the Dark Count Filtering (DCF) will receive a signal from Signal Interval Detection (SID). The signal low indicates that DCF will transfer the random data produced by the earlier process and the signal high indicates the DCF will send signal "0" to output. The details and generation process of the dark count flag and the real count flag are further illustrated in Figure 5 and Figure 6. When the Avalanche Photodiode (APD) circuit is deactivated, the true random processing module is not receiving any pulses. If pulses detected, these pulses are due to dark count signals from an optical setup. As shown in Figure 5, Signal Interval Detection (SID) has two pulse detected counters to begin for counting upon receiving the COUNT_UP_A or COUNT_UP_B acknowledge signals. When a first photon pulse detected, the COUNT_UP_A flag signal is set to HIGH. When the subsequent or next photon pulse detected, COUNT_UP_A flag signal is set to LOW and COUNT_UP_B flag signal is set to HIGH. These flag signals are acknowledge signals and acknowledge the counters i.e. COUNTER_A and COUNTER_B to count the period of time taken between the two consecutive single photon pulses. The COUNTER_A counts the time interval between the first detected single photon pulse to the second detected single photon pulse. Meanwhile, COUNTER_B counts the time interval between the second detected single photon pulse to the third detected single photon pulse. The time interval of two consecutive single photon pulses is counted alternately between COUNTER_A and COUNTER_B. By default, COUNTER_A and COUNTER_B are set to logic Ό' if these counters are not activated by the COUNT_UP_A or COUNT_UP_B flag signals.

During the deactivation of the Avalanche Photodiode (APD) circuit, the time interval counts of COUNTER_A and/or COUNTER_B exceed the dark count time interval or threshold. As shown in Figure 6, the dark count flag is enabled and the data output to the serial module is set to logic Ό'. The circuit diagram of this process is illustrated in Figure 3. Thus, there is a correction in this process and no false data due to dark count signals is transmitted to the host. When the Avalanche Photodiode (APD) circuit is activated again, a real count flag (C2) is set to HIGH again while the dark count flag (C1) is set to LOW. The truly random data is transmitted again to the host. The signal interval detection and dark count filtering of the present invention are implemented in an embedded system device.

Experiments

The present invention has been implemented on a Spartan 3™ field programmable gate array (FPGA) and complex programmable logic device (CLPD) and tested with an optical setup. The generated random data has also been tested with National Institute of Standards and Technology (NIST) Statistical Test Suite Software as illustrated in Table 1. The NIST statistical tests are useful in determining whether output from a random number generator is suitable for cryptographic application or not. However, no set of statistical tests can absolutely certify a random number generator is 100 percent truly random for cryptography usage.

Table 1. NIST Result for Q-RSR

A method of operating a processing unit with dark count signals elimination in a random number generator system of the present invention comprising firstly acquiring a digital signal from an analog to digital converter followed by detecting the digital signal by acquisition module and signal interval detection simultaneously. A binary source is then produced and restored the binary source to be a binary random number using a linear feedback register. A period of time detected signal by signal interval detection is determined and compared with a predetermined threshold signal value. Next, a dark count flag is activated in a dark count filtering if the period of time detected signal more than the predetermined threshold signal value and a logic '0' is passed through by the Dark Count Filtering (DCF) to an output serial module. However, if the period of time detected signal less than the predetermined threshold signal value, a real count flag is activated in a dark count filtering and a binary random number is sent to an output serial module. One of the advantages of the processing unit of the present invention is capable for dark count elimination for dark counts which are not consistent and same shape. Another advantage of the present invention is that it is a Register Transfer Level (RTL) hardware based to detect and eliminate photon dark count signals. In addition to the application to photon receivers in quantum encryption communications, the processing unit according to the present invention can be also applicable to a photon detector for use in general optical communications and a photo measurement device for use in optical measurement.

The foregoing embodiment and advantages are merely exemplary and are not to be construed as limiting the present invention. The description of the embodiments of the present invention is intended to be illustrative and not to limit the scope of the claims and many alternatives, modifications and variations will be apparent to those skilled in the art.

Claims

1. A processing unit with dark count signals elimination in a random number generator system comprising: a digital module for acquiring data and whitening data to produce a binary random source;

a linear feedback shift register for randomizing the binary random source into a random number; characterized in that

a signal interval detection for determining a dark count signal in the acquired data; and a dark count filtering for filtering the dark count signal determined by the signal interval detection.

2. The processing unit as claimed in Claim 1 wherein the processing unit is a digital processing unit located inside a quantum random number generator system.

3. The processing unit as claimed in Claim 1 wherein the signal interval detection comprising a digital counter for determining a period of time detected signal and comparing with a predetermined threshold signal value;

if the period of time detected signal more than the predetermined threshold signal value and a dark count signal detected, a dark count flag is activated as an input for the dark count filtering; and

if the period of time detected signal less than the predetermined threshold signal value and a dark count signal is not detected, a real count flag is activated as an input for the dark count filtering.

4. The processing unit as claimed in Claim 3 wherein the signal interval detection having two pulses detected counters for counting pulses due to dark counts.

5. The processing unit as claimed in Claim 1 wherein the dark count filtering comprising a multiplexer for selecting and determining the period of time detected signal for a dark count signal from the signal interval detection; generating a logic '0' upon filtering the dark count signal and sending the logic '0' to an output serial module; and

sending a binary random number to an output serial module if no dark count signal detected.

6. The processing unit as claimed in Claim 1 wherein the signal interval detection and dark count filtering are implemented in an embedded system device.

7. A method of operating a processing unit with dark count signals elimination in a random number generator system comprising

acquiring a digital signal from a analog to digital converter;

detecting the digital signal by acquisition module and signal interval detection simultaneously;

producing a binary source and restoring the binary source to be a binary random number using a linear feedback register;

determining a period of time detected signal by a signal interval detection and comparing with a predetermined threshold signal value;

activating a dark count flag in a dark count filtering if the period of time detected signal more than the predetermined threshold signal value;

generating a logic '0' and sending the logic '0' to an output serial module;

activating a real count flag in a dark count filtering if the period of time detected signal less than the predetermined threshold signal value; and

sending a binary random number to an output serial module.

8. The method as claimed in Claim 7 wherein the signal interval detection and dark count filtering are implemented in an embedded system device.