WO2013057920A1 - Non-volatile storage element and method for manufacturing same - Google Patents

Non-volatile storage element and method for manufacturing same Download PDF

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Publication number
WO2013057920A1
WO2013057920A1 PCT/JP2012/006601 JP2012006601W WO2013057920A1 WO 2013057920 A1 WO2013057920 A1 WO 2013057920A1 JP 2012006601 W JP2012006601 W JP 2012006601W WO 2013057920 A1 WO2013057920 A1 WO 2013057920A1
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Prior art keywords
layer
plug
nonvolatile memory
memory element
preventing layer
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PCT/JP2012/006601
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French (fr)
Japanese (ja)
Inventor
敦史 姫野
英昭 村瀬
伊藤　理
三河　巧
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パナソニック株式会社
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Publication of WO2013057920A1 publication Critical patent/WO2013057920A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to a variable resistance nonvolatile memory element having a variable resistance element whose resistance value changes by application of an electric pulse, and a method for manufacturing the variable resistance nonvolatile memory element.
  • the resistance change element refers to an element having a property that the resistance value reversibly changes by an electric signal (electric pulse) and can store information corresponding to the resistance value in a nonvolatile manner.
  • variable resistance nonvolatile memory a variable resistance layer is used.
  • an electric pulse for example, a voltage pulse
  • the resistance value of the variable resistance layer changes from the high resistance state to the low resistance state, or from the low resistance state to the high resistance state.
  • the variable resistance nonvolatile memory element stores information corresponding to the resistance value as data.
  • 1) the two values of the low resistance state and the high resistance state are clearly distinguished, 2) the low resistance state and the high resistance state are stably changed at high speed, and 3) these two values are nonvolatile. 4) It is necessary to adapt to copper damascene technology and to achieve miniaturization and high integration.
  • Patent Documents 1 and 2 disclose, as examples of nonvolatile memory elements equipped with variable resistance elements, electrical devices that are compatible with copper damascene technology and can be manufactured by a less complicated method. This electric device is configured by electrically connecting a punch-through diode and a programmable resistor in series.
  • FIG. 13 is a cross-sectional view showing a conventional variable resistance nonvolatile memory element described in Patent Document 1.
  • the nonvolatile memory element 50 shown in FIG. 13 is manufactured as follows. First, after the copper metallization layer 201 and the corresponding plug 202 are formed, the first stacked body 207 is formed on the plug 202.
  • the first stacked body 207 includes a barrier layer 208 (eg, tantalum (Ta)), a contact layer 209 (eg, gold germanium nickel (AuGeNi)), a semiconductor 210 (eg, n-type gallium arsenide (GaAs)),
  • the contact layer 211 and the barrier layer 212 are formed by depositing in this order. Thus, a punch-through diode is formed.
  • the second stacked body 213 is formed on the first stacked body 207.
  • the second stacked body 213 is formed by depositing a barrier layer 214, an electrode layer 215, a PMC (Programmable Metallization Cell) material 216, a contact layer 217, and a barrier layer 218 in this order by sputtering.
  • an intermetal dielectric layer (not shown) is deposited.
  • the surface of the intermetal dielectric layer is planarized by a dielectric film CMP (Chemical Mechanical Polishing). In this way, a programmable resistor is formed.
  • CMP Chemical Mechanical Polishing
  • an IMD (Inter Metal Dielectric) layer 203 is deposited, and a groove 204 is formed on the upper surface of the IMD layer 203 by etching. After the trench 204 is filled with the barrier layer 205 and copper, copper CMP is performed. In this way, a copper interconnect layer 206 is formed.
  • IMD Inter Metal Dielectric
  • the manufacturing process described above can be repeated multiple times. This allows the manufacture of electrical devices having multiple layers of individually accessible memory elements. That is, a three-dimensional array of memory elements can be configured.
  • the present inventor in a conventional nonvolatile memory element, a portion of the upper surface of the plug formed under the nonvolatile memory element that is not covered with the stack of nonvolatile memory elements is plug-formed. It was found that there was a problem in that it was oxidized or deteriorated by exposure to gas or plasma used in a later process. This problem causes a problem that the electrical characteristics of the plug are impaired.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory element that can maintain good electrical characteristics of a plug and a method for manufacturing the same.
  • a nonvolatile memory element includes a first wiring and a plug that is disposed over the first wiring and electrically connected to the first wiring. And a whole of the upper surface of the plug, covering the entire surface of the anti-altering layer, covering a part of the upper surface of the anti-altering layer, and electrically connected to the plug via the anti-altering layer. And a second wiring that is disposed on the stacked body and electrically connected to the stacked body, the resistance state of the stacked body reversibly changes based on an applied electrical signal.
  • the resistance change layer is included, the horizontal cross-sectional area of the lower surface of the alteration preventing layer is equal to the horizontal sectional area of the upper surface of the plug, and a part of the upper surface of the alteration preventing layer is not covered with the laminate.
  • the nonvolatile memory element of the present invention since the entire upper surface of the plug formed under the nonvolatile memory element is covered with the alteration preventing layer, the gas or plasma used in the plug forming process is used. Etc., the upper surface of the plug is not exposed. Therefore, oxidation or alteration on the upper surface of the plug can be prevented, and the electrical characteristics of the plug can be kept good. Thereby, in the nonvolatile memory element including the resistance change element, it is possible to provide a nonvolatile memory element having a device structure capable of obtaining good electrical characteristics and a method for manufacturing the nonvolatile memory element.
  • FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2B is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2C is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 4A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 4B is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 5A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 5B is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 2 of the present invention.
  • FIG. 7 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 3 of the present invention.
  • FIG. 8 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embod
  • FIG. 9C is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 10A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 10B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 10C is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 11A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 11B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 12A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 12B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 13 is a cross-sectional view showing a configuration of a conventional nonvolatile memory element.
  • FIG. 14 is an electron micrograph of a cross section of a nonvolatile memory element showing an example of a defect of a conventional nonvolatile memory element.
  • FIG. 14 is an electron micrograph of a cross section of a conventional nonvolatile memory element produced by the present inventors.
  • the resistance change element 302 is disposed on the lower layer plug 301
  • the upper layer plug 303 is disposed on the resistance change element 302.
  • the horizontal cross-sectional area of the upper surface of the lower layer plug 301 and the horizontal cross-sectional area of the lower surface of the variable resistance element 302 are substantially equal, and the central axis of the variable resistance element 302 is relative to the central axis of the lower layer plug 301.
  • the position is shifted in the horizontal direction (right direction in FIG. 14). Therefore, an exposed portion that is not covered with the resistance change element 302 is generated on the upper surface of the lower layer plug 301.
  • a defective area 304 occurs in a part of the lower layer plug 301.
  • the defect region 304 is formed by an active area (that is, a resistance change element) by insulating a side wall surface of the resistance change element 302 by a dry etching process and a resist ashing process in which the resistance change element 302 is processed into a dot shape. It is considered that this is caused by oxidation or alteration occurring in the exposed portion of the upper surface of the lower layer plug 301 when the step of reducing the effective area that affects the electrical characteristics of the lower layer plug 301 is performed. Note that the defect area 304 can be easily identified by the difference in contrast of the electron micrograph as shown in FIG.
  • the horizontal sectional area of the lower surface of the resistance change element was sufficiently larger than the horizontal sectional area of the upper surface of the lower layer plug. Therefore, even when the horizontal displacement between the multilayer body and the lower layer plug occurs, the entire upper surface of the lower layer plug is covered with the multilayer body. Therefore, it is difficult to think that a part of the upper surface of the lower layer plug exposed by the misalignment is exposed to an etching gas or plasma used for dry etching when processing the laminated body. There were no concerns about alteration.
  • the horizontal cross-sectional area of the resistance change element tends to be miniaturized in order to improve the integration degree of the memory element.
  • the horizontal cross-sectional area of the lower surface of the laminated body tends to be equal to or smaller than the horizontal cross-sectional area of the upper surface of the lower layer plug.
  • the occurrence of the defect area 304 as shown in FIG. 14 becomes a more serious problem. If a part of the lower layer plug is oxidized or deteriorated, an electrical characteristic failure such as an increase in resistance of the lower layer plug occurs, and as a result, a problem such as an unstable write voltage applied to the variable resistance element occurs. .
  • the present inventor has devised a nonvolatile memory element that can eliminate the above-described problems by adopting a structure including an alteration preventing layer.
  • a nonvolatile memory element includes a first wiring, a plug disposed over the first wiring and electrically connected to the first wiring, and the entire upper surface of the plug.
  • An anti-altering layer having electrical conductivity, a laminate covering a part of the upper surface of the anti-altering layer, and electrically connected to the plug via the anti-altering layer, and disposed on the laminate
  • a second wiring electrically connected to the laminate, the laminate including a resistance change layer whose resistance state reversibly changes based on an applied electric signal, and the alteration
  • the horizontal sectional area of the lower surface of the prevention layer is equal to the horizontal sectional area of the upper surface of the plug, and a part of the upper surface of the alteration preventing layer is not covered with the laminate.
  • the upper surface of the plug is not exposed to gas or plasma used in the process after the plug is formed. Therefore, oxidation or alteration on the upper surface of the plug can be prevented, and the electrical characteristics of the plug can be kept good. Further, even in the step of oxidizing the side wall surface of the stacked body in order to reduce the active area of the stacked body, it is possible to prevent oxidation or degeneration on the upper surface of the plug. By maintaining good electrical characteristics of the plug, the write voltage applied to the variable resistance layer can be stabilized.
  • the stacked body further includes a first electrode electrically connected to the plug through the alteration preventing layer, and an electrical connection to the second wiring.
  • the variable resistance layer may be configured to be disposed between the first electrode and the second electrode.
  • the laminate is configured by laminating the first electrode, the resistance change layer, and the second electrode in this order.
  • a resistance change element can be comprised by such a laminated body.
  • the horizontal cross-sectional area of the lower surface of the first electrode may be configured to be smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer.
  • the horizontal sectional area of the lower surface of the first electrode is smaller than the horizontal sectional area of the upper surface of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the first electrode.
  • the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the horizontal cross-sectional area of the lower surface of the first electrode is equal to the horizontal cross-sectional area of the upper surface of the alteration preventing layer or the horizontal sectional area of the upper surface of the alteration preventing layer.
  • the center axis of the laminate is deviated from the center axis of the alteration preventing layer, and a part of the upper surface of the alteration preventing layer is not covered with the first electrode. Also good.
  • the central axis of the laminate is deviated from the central axis of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the first electrode. Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the alteration preventing layer functions as a first electrode that is electrically connected to the plug, and the stacked body is further electrically connected to the second wiring.
  • the resistance change layer may be arranged between the alteration preventing layer as the first electrode and the second electrode.
  • the alteration preventing layer also functions as the first electrode, the number of steps can be reduced as compared with the case where the alteration preventing layer and the first electrode are formed of separate layers.
  • the horizontal cross-sectional area of the lower surface of the variable resistance layer may be configured to be smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer.
  • the horizontal cross-sectional area of the lower surface of the resistance change layer is smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the resistance change layer. The Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the horizontal cross-sectional area of the lower surface of the resistance change layer is equal to the horizontal cross-sectional area of the upper surface of the alteration preventing layer or the horizontal sectional area of the upper surface of the alteration preventing layer.
  • the center axis of the laminate is deviated from the center axis of the alteration preventing layer, and a part of the upper surface of the alteration preventing layer is not covered with the resistance change layer. Also good.
  • the central axis of the laminate is deviated from the central axis of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the resistance change layer. Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the nonvolatile memory element further includes an interlayer insulating layer disposed on the first wiring and having a contact hole.
  • the plug and the alteration preventing layer are both the contact hole. You may comprise so that it may be embedded in.
  • the plug and the alteration preventing layer are both embedded in the contact hole of the interlayer insulating layer, adjacent plugs are short-circuited when a plurality of nonvolatile memory elements are arranged at intervals. Can be surely prevented.
  • the alteration preventing layer may be configured to be composed of a metal nitride that forms the plug.
  • the alteration preventing layer can be easily formed on the upper surface of the plug by nitriding.
  • the nonvolatile memory element further includes an interlayer insulating layer disposed on the first wiring and having a contact hole.
  • the plug is embedded in the contact hole, and the alteration prevention is performed.
  • the layer may be configured to protrude outside the contact hole.
  • the plug is embedded in the contact hole of the interlayer insulating layer and the alteration preventing layer protrudes outside the contact hole, for example, when the upper surface of the alteration preventing layer is planarized, Loss that the upper surface is scraped can be suppressed.
  • the plug may be formed of tungsten or copper.
  • the plug can be made of tungsten or copper.
  • the alteration preventing layer may be configured to have an oxygen barrier property and an etching resistance.
  • the alteration preventing layer has an oxygen barrier property and etching resistance, it is possible to suppress the alteration preventing layer from being affected by the etching gas, for example, in an etching process after forming the plug.
  • the alteration preventing layer is formed of any one of tungsten nitride, cobalt-tungsten-phosphorus alloy, cobalt-tungsten-boron alloy, and palladium. It may be configured.
  • the alteration preventing layer is composed of any one of tungsten nitride, cobalt tungsten phosphorous alloy, cobalt tungsten tungsten boron alloy and palladium, the alteration preventing layer is affected by the etching gas. Can be effectively suppressed.
  • the resistance change layer may be configured of a transition metal oxide or an aluminum oxide.
  • variable resistance layer can be composed of a transition metal oxide or an aluminum oxide.
  • variable resistance layer includes at least one transition metal selected from oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, and oxygen-deficient zirconium oxide. You may comprise so that it may be comprised with the oxide.
  • the resistance change layer is composed of one or more transition metal oxides of oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, and oxygen-deficient zirconium oxide.
  • the variable resistance layer is made of an oxygen-deficient tantalum oxide
  • the nonvolatile memory element can be manufactured by a manufacturing process having a high affinity for a normal Si semiconductor process.
  • the resistance change layer includes a first resistance change layer including a first metal oxide, and a degree of oxygen deficiency higher than that of the first metal oxide. And a second variable resistance layer composed of a second metal oxide having a small thickness.
  • the resistance change layer is formed by stacking two types of metal oxides having different degrees of oxygen deficiency, so that the polarity of resistance change is always stable and the operation characteristics of the nonvolatile memory element are stabilized. be able to.
  • the method for manufacturing a nonvolatile memory element includes a step of forming a first wiring, and a plug electrically connected to the first wiring over the first wiring.
  • the alteration preventing layer is formed so as to cover the entire area of the upper surface of the plug, the upper surface of the plug is not exposed to gas or plasma used in the process after the plug is formed. Therefore, oxidation or alteration can be prevented from occurring on the upper surface of the plug, and a nonvolatile memory element having a plug with good electrical characteristics can be manufactured.
  • the step of forming the stacked body further includes forming a first electrode electrically connected to the plug through the alteration preventing layer. Including the steps of: forming the resistance change layer on the first electrode; forming the second electrode on the resistance change layer; and forming the second wiring, The second wiring electrically connected to the second electrode may be formed.
  • the laminate is formed by laminating the first electrode, the resistance change layer, and the second electrode in this order.
  • a resistance change element can be formed by such a laminated body.
  • the alteration preventing layer that functions as a first electrode electrically connected to the plug is formed.
  • the step of forming the laminated body includes a step of forming the resistance change layer on the alteration preventing layer and a step of forming a second electrode on the resistance change layer, and the second wiring is formed.
  • the second wiring electrically connected to the second electrode may be formed.
  • the manufacturing process of the nonvolatile memory element can be simplified as compared with the case where the alteration preventing layer and the first electrode are formed as separate layers.
  • the alteration preventing layer is formed by nitriding the entire upper surface of the plug. May be.
  • the alteration preventing layer can be easily formed on the upper surface of the plug by nitriding.
  • the alteration preventing layer in the step of forming the alteration preventing layer, may be formed by electroless plating.
  • the alteration preventing layer can be easily formed on the upper surface of the plug by electroless plating.
  • nonvolatile memory element a variable resistance nonvolatile memory element (hereinafter also simply referred to as “nonvolatile memory element”) and a manufacturing method thereof according to one embodiment of the present invention will be described with reference to the drawings.
  • FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element 10 according to Embodiment 1 of the present invention.
  • a nonvolatile memory element 10 shown in FIG. 1 includes a first interlayer insulating layer 101, a first wiring 102, a second interlayer insulating layer 103, a first plug 104, an alteration preventing layer 105, a resistance change element 109 (laminated layer).
  • Such a nonvolatile memory element 10 constitutes a part of a region called a memory cell array or a memory main body in a general semiconductor memory device.
  • the semiconductor memory device may include a drive circuit for driving the memory cell array in addition to the memory cell array including the nonvolatile memory element 10.
  • the drive circuit applies an electric pulse (electric signal) to the nonvolatile memory element 10 in the memory cell array.
  • the resistance state of the resistance change element 109 of the nonvolatile memory element 10 is reversibly changed by an electric pulse for data writing. Further, the resistance state of the variable resistance element 109 of the nonvolatile memory element 10 is read by an electric pulse for reading data.
  • the first interlayer insulating layer 101 is formed on a semiconductor substrate (not shown) on which transistors and the like are formed.
  • the first interlayer insulating layer 101 is made of, for example, silicon oxide.
  • the first wiring 102 is formed on the first interlayer insulating layer 101.
  • the first wiring 102 is made of, for example, copper or aluminum.
  • the second interlayer insulating layer 103 is formed on the first wiring 102.
  • the second interlayer insulating layer 103 is made of, for example, silicon oxide having a thickness of 100 to 500 nm.
  • the first plug 104 is formed inside the second interlayer insulating layer 103.
  • the first plug 104 is electrically connected to the first wiring 102.
  • the first plug 104 is made of, for example, tungsten or copper.
  • the diameter of the first plug 104 is, for example, 70 to 240 nm.
  • the alteration preventing layer 105 is formed so as to cover the entire upper surface of the first plug 104.
  • the “upper surface” and the “lower surface” are defined such that the direction from the first wiring 102 to the stacked body is the top and the direction from the stacked body to the first wiring 102 is the bottom.
  • “A whole area of the upper surface of the first plug 104” means a surface exposed to the upper side immediately after the first plug 104 is formed.
  • the alteration preventing layer 105 is made of a material having conductivity, oxygen barrier properties and etching resistance, such as tungsten nitride.
  • the horizontal sectional area of the lower surface of the alteration preventing layer 105 is configured to be equal to the horizontal sectional area of the upper surface of the plug 104.
  • the horizontal cross-sectional area means an area of a cross section cut by a horizontal plane perpendicular to the vertical direction (vertical direction) in a state where the resistance change element 109 is disposed on the upper side and the first plug 104 is disposed on the lower side. .
  • the alteration preventing layer 105 Since the alteration preventing layer 105 has an oxygen barrier property, as will be described later, when the resistance change element 109 is formed into a dot shape by etching, the upper surface of the alteration preventing layer 105 is oxidized by the etching gas. It is suppressed. Further, since the alteration preventing layer 105 has etching resistance, as will be described later, when the resistance change element 109 is formed into a dot shape by etching, the upper surface of the alteration preventing layer 105 is suppressed from being etched by etching. The
  • the resistance change element 109 is formed on the second interlayer insulating layer 103 and is electrically connected to the first plug 104 via the alteration preventing layer 105.
  • the resistance change element 109 is formed as a dot-shaped laminate.
  • the dot shape refers to the shape of a laminate having a rectangular horizontal cross section with a side of 100 to 400 nm.
  • the horizontal cross-sectional area of the lower surface of the resistance change element 109 (that is, the lower surface of the first electrode 106) is the upper surface of the alteration preventing layer 105 that covers the upper surface of the first plug 104. It is configured to be smaller than the horizontal cross sectional area.
  • the diameter of the first plug 104 including the alteration preventing layer 105 may be 240 nm
  • the horizontal cross section of the resistance change element 109 may be a rectangular shape having a side of 200 nm.
  • the resistance change element 109 includes the first electrode 106, the resistance change layer 107, and the second electrode 108.
  • the first electrode 106 and the second electrode 108 are disposed to face each other.
  • the first electrode 106 is electrically connected to the first plug 104 through the alteration preventing layer 105.
  • the resistance change layer 107 is interposed between the first electrode 106 and the second electrode 108, and the resistance value reversibly changes based on an electrical signal applied between the first electrode 106 and the second electrode 108. It is a layer to do.
  • the resistance change layer 107 is, for example, a layer that reversibly transitions between a high resistance state and a low resistance state according to the polarity of the voltage applied between the first electrode 106 and the second electrode 108.
  • the resistance change layer 107 is configured by stacking at least two layers of a first resistance change layer 107 a connected to the first electrode 106 and a second resistance change layer 107 b connected to the second electrode 108. The The material constituting the resistance change layer 107 will be described later.
  • the third interlayer insulating layer 110 is formed on the second interlayer insulating layer 103.
  • a variable resistance element 109 is formed inside the third interlayer insulating layer 110.
  • the second plug 111 is formed inside the third interlayer insulating layer 110.
  • the second plug 111 is electrically connected to the second electrode 108 of the variable resistance element 109.
  • the second wiring 112 is formed on the third interlayer insulating layer 110 and on the upper surface of the second plug 111.
  • the second wiring 112 is electrically connected to the second plug 111.
  • the first resistance change layer 107a is composed of an oxygen-deficient first metal oxide
  • the second resistance change layer 107b is a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide. It consists of things.
  • a minute local region in which the degree of oxygen deficiency reversibly changes according to the application of the electric pulse is formed.
  • the local region is considered to include a filament composed of oxygen defect sites.
  • the resistance change layer 107 can be made of a transition metal oxide such as tantalum oxide, for example.
  • the first resistance change layer 107a is made of an oxygen-deficient transition metal oxide
  • the second resistance change layer 107b is oxygen having a lower oxygen deficiency than the first resistance change layer 107a. It is composed of a deficient transition metal oxide.
  • the oxygen-deficient transition metal oxide has an oxygen content (atomic ratio: the ratio of the number of oxygen atoms to the total number of atoms) compared to a transition metal oxide having a stoichiometric composition. It refers to less oxide.
  • Oxygen deficiency means the stoichiometric composition of metal oxide (if there are multiple stoichiometric compositions, the stoichiometric composition having the highest resistance value among them). This refers to the proportion of oxygen that is deficient with respect to the amount of oxygen that forms the oxide. Stoichiometric metal oxides are more stable and have higher resistance values than other metal oxides.
  • the oxide having the stoichiometric composition according to the above definition is Ta 2 O 5 , and can be expressed as TaO 2.5 .
  • the oxygen excess metal oxide has a negative oxygen deficiency.
  • the oxygen deficiency is described as including a positive value, 0, and a negative value.
  • An oxide with a low degree of oxygen deficiency has a high resistance value because it is closer to a stoichiometric oxide, and an oxide with a high degree of oxygen deficiency has a low resistance value because it is closer to the metal constituting the oxide.
  • the “oxygen content” is the ratio of oxygen atoms to the total number of atoms.
  • the oxygen content of Ta 2 O 5 is the ratio of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%.
  • the oxygen content has a corresponding relationship with the degree of oxygen deficiency. That is, when the oxygen content of the second metal oxide is greater than the oxygen content of the first metal oxide, the oxygen deficiency of the second metal oxide is greater than the oxygen deficiency of the first metal oxide. small.
  • the metal constituting the resistance change layer 107 may be a metal other than tantalum.
  • a metal constituting the resistance change layer 107 a transition metal or aluminum (Al) can be used. That is, the resistance change layer 107 can be made of a transition metal oxide or aluminum oxide.
  • the transition metal tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), nickel (Ni), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.
  • the composition of the first metal oxide is HfO x
  • x is 0.9 or more and 1.6 or less
  • the composition of the second metal oxide is HfO x.
  • the resistance value of the resistance change layer 107 can be stably changed at high speed.
  • the thickness of the second metal oxide may be 3 to 4 nm.
  • the composition of the first metal oxide is ZrO x
  • x is 0.9 or more and 1.4 or less
  • the composition of the second metal oxide is ZrO x.
  • the thickness of the second metal oxide may be 1 to 5 nm.
  • the first resistance change layer 107a when the first resistance change layer 107a is composed of oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, or oxygen-deficient zirconium oxide, the first resistance change layer 107a includes tantalum, It can be formed by a so-called reactive sputtering method in which hafnium or zirconium is used as a target and sputtering is performed in argon gas and oxygen gas.
  • the degree of oxygen deficiency of the first resistance change layer 107a can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. This treatment can be performed at room temperature without particularly heating the semiconductor substrate.
  • the second resistance change layer 107b can be formed by exposing the surface of the first resistance change layer 107a formed by a reactive sputtering method to plasma of argon gas and oxygen gas.
  • the resistance change layer 107 is made of, for example, oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, or oxygen-deficient zirconium oxide, in addition to high-speed operation, reversibly stable rewriting characteristics and good
  • the nonvolatile memory element 10 having a retention characteristic with a satisfactory resistance value can be realized.
  • the resistance change layer 107 is made of an oxygen-deficient tantalum oxide
  • the nonvolatile memory element 10 can be manufactured by a manufacturing process having a high affinity for a normal Si semiconductor process.
  • the second metal oxide may have a lower degree of oxygen deficiency than the first metal oxide, that is, may have a higher resistance.
  • a first metal constituting the first metal oxide to be the first resistance change layer 107a, a second metal constituting the second metal oxide to be the second resistance change layer 107b, are made of different materials, the standard electrode potential of the second metal may be lower than the standard electrode potential of the first metal.
  • the standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize. Thereby, an oxidation-reduction reaction easily occurs in the second metal oxide having a relatively low standard electrode potential.
  • the resistance change phenomenon is caused by a change in the filament (conducting path) caused by an oxidation-reduction reaction in a minute local region formed in the second metal oxide having a high resistance. Degree) is considered to change.
  • metal oxide Al 2 O 3
  • Al 2 O 3 aluminum oxide
  • oxygen-deficient tantalum oxide (TaO x ) may be used for the first metal oxide
  • aluminum oxide (Al 2 O 3 ) may be used for the second metal oxide.
  • the resistance change phenomenon in the resistance change layer 107 having the laminated structure is caused by a redox reaction in a minute local region formed in the second metal oxide having a high resistance, and a filament (conducting path) in the local region.
  • Changes the resistance value is considered to change. That is, when a positive voltage is applied to the second electrode 108 connected to the second metal oxide with reference to the first electrode 106, oxygen ions in the resistance change layer 107 are moved to the second metal oxide side. Gravitate. As a result, an oxidation reaction occurs in a small local region formed in the second metal oxide, and the degree of oxygen deficiency is reduced. As a result, it is considered that the filaments in the local region are not easily connected and the resistance value is increased.
  • the second electrode 108 connected to the second metal oxide having a lower oxygen deficiency constitutes the second metal oxide such as platinum (Pt), iridium (Ir), palladium (Pd), etc.
  • the metal and the material constituting the first electrode 106 are made of a material having a higher standard electrode potential.
  • the first electrode 106 connected to the first metal oxide having a higher degree of oxygen deficiency is, for example, tungsten (W), nickel (Ni), tantalum (Ta), titanium (Ti), aluminum (Al ), Tantalum nitride (TaN), titanium nitride (TiN), or the like, a material having a lower standard electrode potential than the metal constituting the first metal oxide may be used.
  • the standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize.
  • the standard electrode potential V2 of the second electrode 108, the standard electrode potential Vr2 of the metal constituting the second metal oxide, the standard electrode potential Vr1 of the metal constituting the first metal oxide, the first electrode 106 The relationship of V r2 ⁇ V 2 and V 1 ⁇ V 2 may be satisfied with the standard electrode potential V1. Furthermore, V2> Vr2 and Vr1 ⁇ V1 may be satisfied.
  • a voltage is first applied to the resistance change element 109, and a part of the second resistance change layer 107b having a low oxygen deficiency is locally applied. An initial break to short circuit is performed. What is important at this time is that a sufficient voltage is applied to the resistance change element 109 without applying an unnecessary voltage to transistors other than the resistance change element 109 and parasitic resistance components.
  • a voltage satisfying a predetermined condition is applied between the first electrode 106 and the second electrode 108 by an external power source (not shown) and a drive circuit. Apply between.
  • 2A to 5B are cross-sectional views illustrating a method for manufacturing the nonvolatile memory element 10 according to the present embodiment.
  • the process, material, film thickness, etc. which are demonstrated below are an illustration to the last, and the manufacturing method of the non-volatile memory element 10 which concerns on this invention is not limited to this Embodiment.
  • the order of each process etc. can be changed as needed, or another well-known process can be added.
  • a first interlayer insulating layer 101 made of silicon oxide is formed on a semiconductor substrate (not shown) on which transistors and the like are formed in advance by using plasma CVD or the like. To do. Thereafter, the first wiring 102 is formed over the first interlayer insulating layer 101.
  • the first wiring 102 can be formed by a general semiconductor process, for example, film formation by sputtering, shape processing by photolithography, and dry etching. it can.
  • copper (Cu) is used as the material for the first wiring 102
  • the first wiring 102 can be embedded in the first interlayer insulating layer 101 by using a damascene method.
  • a first plug 104 that is electrically connected to the first wiring 102 is formed on the first wiring 102.
  • a second interlayer insulating layer 103 is further deposited on the first wiring 102. Note that, if necessary, step relaxation is performed on the upper surface of the second interlayer insulating layer 103 by CMP.
  • a contact hole 113 for embedding the first plug 104 is formed in a portion of the second interlayer insulating layer 103 corresponding to a predetermined position on the first wiring 102 by photolithography and dry etching. .
  • a barrier metal layer composed of titanium nitride (for example, a film thickness of 5 to 40 nm) and titanium (for example, a film thickness of 5 to 40 nm) is formed on the second interlayer insulating layer 103 including the formed contact hole 113. Is deposited by sputtering or the like. Further, tungsten (for example, a film thickness of 50 to 300 nm) as a conductive material is deposited by CVD or the like.
  • the first plug 104 is formed in the contact hole 113 by filling the contact hole 113 with the barrier metal layer and tungsten. Thereafter, the excess tungsten and barrier metal layer on the upper surface of the first plug 104 are removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104 are formed flat.
  • the upper surface of the first plug 104 is overpolished by CMP to form a recess (concave portion) 114 having a depth of about 10 to 50 nm on the upper side of the first plug 104.
  • etch back by dry etching can be performed.
  • a cap metal film 105 ′ made of, for example, tungsten nitride is deposited on the second interlayer insulating layer 103 including the recess 114 by CVD or the like. By filling the recess 114 with tungsten nitride, the alteration preventing layer 105 is formed in the recess 114.
  • the excess cap metal film 105 ′ on the upper surface of the second interlayer insulating layer 103 is removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the alteration preventing layer 105 are removed. Are formed flat.
  • the first plug 104 and the alteration preventing layer 105 are both embedded in the contact hole 113, when a plurality of the nonvolatile memory elements 10 are arranged at intervals, the adjacent first plugs 104 are arranged. It is possible to reliably prevent the 104 from being short-circuited.
  • tungsten nitride can be used as the alteration preventing layer 105 covering only the upper surface of the first plug 104 made of tungsten.
  • the first plug 104 made of tungsten is formed, and then the first plug 104 is subjected to plasma of argon gas and nitrogen gas. There are ways to expose the surface.
  • the alteration preventing layer 105 that covers only the upper surface of the first plug 104 and is made of tungsten nitride can be formed in a self-forming manner.
  • a resistance change element 109 as a stacked body is formed on the first plug 104 via the alteration preventing layer 105.
  • a first electrode layer 106 ′ (for example, a film thickness of 30 nm) made of tantalum nitride, an oxygen-deficient type is formed on the second interlayer insulating layer 103 including the alteration preventing layer 105.
  • a resistance change thin film 107 ′ (for example, a film thickness of 50 nm) made of tantalum oxide and a second electrode layer 108 ′ (for example, a film thickness of 50 nm) made of iridium are deposited so as to be stacked horizontally in this order.
  • the resistance change thin film 107 ′ is configured by laminating a first resistance change thin film 107 a ′ and a second resistance change thin film 107 b ′ in this order.
  • the first resistance change thin film 107a ' is formed by using a so-called reactive sputtering method in which sputtering is performed in an argon and oxygen gas atmosphere using tantalum as a target.
  • the oxygen concentration in the deposition chamber is controlled to 44.6 to 65.5 atm% by adjusting the flow rate of oxygen.
  • the resistivity of the first resistance change thin film 107a ' can be adjusted to 0.5 to 20 m ⁇ ⁇ cm.
  • the first variable resistance thin film 107a' having a resistivity of about 2 m ⁇ ⁇ cm can be formed.
  • the first electrode layer 106 'and the second electrode layer 108' are formed by the reactive sputtering method as described above.
  • the second resistance change thin film 107b ′ may be formed on the outermost surface layer of the first resistance change thin film 107a ′ by oxidizing the surface of the first resistance change thin film 107a ′.
  • the second resistance change thin film 107b ′ is formed of a Ta 2 O 5 layer having a stoichiometric composition that has a lower degree of oxygen deficiency than that of the first resistance change thin film 107a ′ or is not deficient in oxygen.
  • the thickness may be in the range of 2 to 12 nm.
  • each side is 200 nm.
  • the dot-shaped resistance change element 109 is formed.
  • the upper surface of the first plug 104 is covered with the alteration preventing layer 105, when the resistance change element 109 is formed into a dot shape by etching, The upper surface of the plug 104 is not exposed to an etching gas containing chlorine, fluorine, oxygen, or the like used for dry etching.
  • an etching gas containing chlorine, fluorine, oxygen, or the like used for dry etching.
  • the top surface of the first plug 104 can be prevented from being oxidized or denatured, and a first plug with good electrical characteristics can be formed.
  • a conductive hard mask (on the second electrode layer 108a ′ is used to prevent the uppermost second electrode 108 from being etched away. (Not shown) may be deposited by sputtering or the like. As the material of the hard mask, for example, any one of tantalum nitride, titanium nitride, and titanium-aluminum nitride is used. After the variable resistance element 109 is formed in a dot shape, the hard mask remaining on the second electrode 108 may be removed by etching or the like.
  • the resistance change element 109 may be processed into a dot shape, and then annealed in an oxygen atmosphere (temperature: 300 to 450 ° C.) to oxidize the side wall surface of the first resistance change layer 107a and insulate it. .
  • an oxygen atmosphere temperature: 300 to 450 ° C.
  • the active area is reduced and the leakage current is reduced, so that the initial break voltage is lowered and the application time is shortened. be able to.
  • the oxidation of the first plug 104 is performed when the side wall surface of the variable resistance element 109 is oxidized. Can be prevented.
  • the nonvolatile memory element 10 that has a small parasitic resistance component other than the resistance change element 109 and operates stably can be realized.
  • a third interlayer insulating layer 110 for embedding and forming the second plug 111 is deposited on the second interlayer insulating layer 103 including the resistance change element 109 by plasma CVD or the like. To do.
  • the third interlayer insulating layer 110 is made of silicon oxide or the like. If necessary, the step is reduced on the upper surface of the third interlayer insulating layer 110 by CMP.
  • the second electrode 108 is electrically connected to the inside of the third interlayer insulating layer 110 and on the variable resistance element 109 by a method similar to the method of forming the first plug 104.
  • the second plug 111 to be formed is formed.
  • the second plug 111 is made of tungsten or the like.
  • a second wiring 112 electrically connected to the second plug 111 is formed on the third interlayer insulating layer 110 and the second plug 111. Similar to the first wiring 102, the second wiring 112 is made of aluminum, copper, or the like.
  • the nonvolatile memory element 10 shown in FIG. 1 is formed.
  • the dry etching and the active area of the resistance change element 109 are reduced by forming the alteration preventing layer 105 that covers the upper surface of the first plug 104.
  • the first plug 104 can be prevented from being oxidized or deteriorated, and the first plug 104 with good electrical characteristics can be formed.
  • the nonvolatile memory element 10 that has a small parasitic resistance component other than the resistance change element 109 and operates stably can be realized.
  • the second electrode 108 of the variable resistance element 109 is made of iridium, but the present invention is not limited to this.
  • the second electrode 108 may be made of any metal of platinum, copper, tungsten, iridium, and palladium, or a combination or alloy of these metals.
  • the initial break voltage refers to a voltage that can be applied to the resistance change element 109 to reduce the resistance value of the resistance change layer 107 from the initial resistance value to the normal operating range.
  • tantalum and titanium nitride may be used as the material for the first electrode 106.
  • the resistance change layer 107 may be formed by stacking two or more resistance change layers made of the same kind of transition metal oxide.
  • FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory element 20 according to the present embodiment.
  • the horizontal cross-sectional area of the lower surface of the resistance change element 109A (that is, the lower surface of the first electrode 106) is horizontal with respect to the upper surface of the alteration preventing layer 105A.
  • the central axis 120a of the variable resistance element 109A is offset in the horizontal direction (right side in FIG. 6) with respect to the central axis 120b of the first plug 104A. Therefore, a part of the upper surface of the alteration preventing layer 105A is exposed without being covered by the lower surface of the resistance change element 109A.
  • the “center axis” is defined by a line that passes through the center of the horizontal section of the variable resistance element 109A and the first plug 104A and is perpendicular to the horizontal section when the horizontal section is circular.
  • the horizontal cross section of the resistance change element 109A and the first plug 104A is a polygon or the like, it is defined by a line that passes through the center of gravity and is perpendicular to the horizontal cross section.
  • the center axis of the first plug 104A and the center of the resistance change element 109A Misalignment with the shaft may occur. Therefore, especially when the horizontal cross-sectional area of the lower surface of the first electrode 106 is larger than the horizontal cross-sectional area of the upper surface of the first plug 104A, the above-described misalignment tends to occur as shown in FIG.
  • the alteration preventing layer 105A since the upper surface of the first plug 104A is covered with the alteration preventing layer 105A, dry etching for processing the resistance change element 109A into a dot shape and an active area for reducing the active area of the resistance change element 109A are reduced. Oxidation or alteration of the first plug 104A due to side wall surface oxidation can be prevented.
  • FIG. 7 is a cross-sectional view showing the configuration of the nonvolatile memory element 30 according to this embodiment.
  • the first electrode of the resistance change element 109B is omitted, and the alteration preventing layer 105B also functions as the first electrode of the resistance change element 109B.
  • the resistance change layer 107 is disposed between the alteration preventing layer 105 ⁇ / b> B and the second electrode 108.
  • the horizontal sectional area of the lower surface of the resistance change layer 107 is configured to be smaller than the horizontal sectional area of the upper surface of the alteration preventing layer 105B.
  • Other configurations of the nonvolatile memory element 30 according to the present embodiment are substantially the same as those of the nonvolatile memory element 10 according to the first embodiment.
  • the resistance change element 109B when the resistance change element 109B is formed in a dot shape by dry etching, a stacked body including the second electrode 108 and the resistance change layer 107 may be processed.
  • the type and thickness of the target film can be reduced. Thereby, the dimensional variation of the resistance change element 109B can be reduced, and the resistance change element 109B can be easily miniaturized.
  • the second electrode 108 As a material of the second electrode 108, a material having a higher standard electrode potential than the material constituting the transition metal constituting the resistance change layer 107B and the alteration preventing layer 105B, such as platinum (Pt) or iridium (Ir), is used. By using it, a redox reaction occurs selectively in the resistance change layer 107 in the vicinity of the interface between the second electrode 108 and the resistance change layer 107, and a stable resistance change phenomenon is obtained.
  • platinum platinum
  • Ir iridium
  • the horizontal cross-sectional area of the lower surface of the resistance change layer 107 is configured to be equal to or larger than the horizontal cross-sectional area of the upper surface of the alteration preventing layer 105B to change the resistance.
  • the central axis of the element 109B can be offset in the horizontal direction with respect to the central axis of the first plug 104.
  • FIG. 8 is a cross-sectional view showing a configuration of the nonvolatile memory element 40 according to the present embodiment.
  • the alteration preventing layer 105 ⁇ / b> C is formed so as to protrude upward from the upper surface of the second interlayer insulating layer 103.
  • the upper side of the upper surface of the second interlayer insulating layer 103 may be referred to as “outside of the contact hole 113”.
  • the first wiring 102C and the second wiring 112C are embedded in the first interlayer insulating layer 101C and the third interlayer insulating layer 110C, respectively.
  • the second plug is not provided.
  • Other configurations of the nonvolatile memory element 40 according to the present embodiment are substantially the same as those of the nonvolatile memory element 10 according to the first embodiment.
  • 9A to 12B are cross-sectional views showing a method for manufacturing the nonvolatile memory element 40 according to the present embodiment.
  • a first interlayer insulating layer 101C is formed on a semiconductor substrate (not shown) on which transistors and the like are formed in advance. Thereafter, a wiring groove 115 for embedding and forming the first wiring 102C is formed in the first interlayer insulating layer 101C by photolithography and dry etching.
  • a wiring material 102C ′ is deposited on the first interlayer insulating layer 101C including the wiring trench 115 by a sputtering method or the like.
  • the wiring material 102C ′ includes, for example, a barrier metal layer in which tantalum nitride (film thickness 5 to 40 nm) and tantalum (5 to 40 nm) are stacked, copper (50 to 300 nm) serving as a seed layer for electrolytic plating, and Consists of.
  • copper is further deposited on the copper seed layer by electrolytic plating to fill the wiring trench 102 ⁇ / b> C ′ with copper.
  • the second interlayer insulating layer 103 made of silicon nitride or silicon oxide is formed on the first interlayer insulating layer 101C including the first wiring 102C by plasma CVD or the like. Is further deposited. Note that, if necessary, step relaxation is performed on the upper surface of the second interlayer insulating layer 103 by CMP. Thereafter, a contact hole 113 for embedding the first plug 104 is formed at a predetermined position on the first wiring 102C by photolithography and dry etching.
  • a barrier metal layer made of tantalum nitride and tantalum and copper as a conductive material are deposited on the second interlayer insulating layer 103 including the formed contact hole 113 by sputtering or the like.
  • copper is further deposited by electrolytic plating using copper as a seed to fill the contact hole 113 with the barrier metal layer and copper.
  • the first plug 104 is formed.
  • excess copper and the barrier metal layer on the upper surface of the first plug 104 are removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104 are formed flat. As a result, the first plug 104 is completely embedded in the contact hole 113.
  • an alteration preventing layer 105C covering the upper surface of the first plug 104 is formed by an electroless plating method.
  • the alteration preventing layer 105 ⁇ / b> C is formed so as to protrude upward with respect to a flat surface constituted by the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104.
  • the alteration preventing layer 105C is made of a cobalt-tungsten-phosphorus (CoWP) alloy.
  • CoWP cobalt-tungsten-phosphorus
  • the alteration preventing layer 105C is selectively deposited only on the upper surface of the first plug 104 made of a conductive material, and on the second interlayer insulating layer 103 made of an insulating material. Therefore, the alteration preventing layer 105C that covers only the upper surface of the first plug 104 can be formed selectively. Further, by using the electroless plating method, it is not necessary to perform shape processing by CMP, dry etching, or the like, which is convenient for miniaturization. Furthermore, since copper has a resistivity lower than that of tungsten, the resistivity of the first plug 104 can be lowered by configuring the first plug 104 with copper, and the influence of wiring delay is small and high-speed operation is possible. A nonvolatile memory element 40 can be realized.
  • a plating bath containing hypophosphite such as sodium hypophosphite
  • hypophosphite such as sodium hypophosphite
  • the surface of the first plug 104 made of copper may be preliminarily immersed in an aqueous palladium chloride solution for several seconds to provide a palladium catalyst layer. This is because the surface of the metal is catalyzed by impregnating iron group elements such as iron (Fe), nickel (Ni), cobalt (Co) and palladium (Pa), and metals of platinum group elements. This is because an oxidation reaction of hypophosphite ions occurs.
  • a cap layer made of silicon nitride is deposited in order to prevent copper from diffusing into the interlayer insulating layer from the upper surface of the wiring and the plug.
  • depositing a cap layer made of silicon nitride, which is an insulator increases the charge capacity between the wiring layers and causes a problem of RC delay of the circuit.
  • the alteration preventing layer 105C made of a conductive material is used, the charge capacity between the wiring layers can be reduced as compared with the case where the alteration preventing layer made of an insulating material is used. Since the RC delay can be suppressed, the nonvolatile memory element 40 capable of high-speed operation can be realized.
  • variable resistance element 109 is formed on the first plug 104 including the alteration preventing layer 105C by a method similar to the method for manufacturing the nonvolatile memory element 10 according to Embodiment 1. .
  • a third interlayer insulating layer 110C is deposited on the second interlayer insulating layer 103 including the resistance change element 109 by plasma CVD or the like.
  • the third interlayer insulating layer 110C is made of silicon oxide or the like. Note that, if necessary, the step is relaxed on the upper surface of the third interlayer insulating layer 110C by CMP.
  • a wiring trench 116 for embedding the second wiring 112C is formed in the third interlayer insulating layer 110C by photolithography and dry etching.
  • a wiring material 112C ' is deposited on the third interlayer insulating layer 110C including the wiring trench 116 by sputtering or the like.
  • the wiring material 112C ′ includes, for example, a barrier metal layer in which tantalum nitride (for example, a film thickness of 5 to 40 nm) and tantalum (for example, 5 to 40 nm) are laminated, and copper (for example, a seed layer for electrolytic plating) (for example, , 50 to 300 nm). Thereafter, copper is further deposited on the copper seed layer by electrolytic plating to fill the wiring trench 112C 'with copper.
  • tantalum nitride for example, a film thickness of 5 to 40 nm
  • tantalum for example, 5 to 40 nm
  • copper for example, a seed layer for electrolytic plating
  • excess copper on the upper surface of the third interlayer insulating layer 110C is removed by CMP from the deposited barrier metal layer and copper, and the upper surface of the third interlayer insulating layer 110C and the first copper are removed.
  • the upper surface of the second wiring 112C is formed flat. Thereby, the second wiring 112C is formed.
  • the nonvolatile memory element 40 shown in FIG. 8 is formed.
  • the horizontal cross-sectional area of the lower surface of the first electrode 106 is configured to be equal to or larger than the horizontal cross-sectional area of the upper surface of the alteration preventing layer 105C to change the resistance.
  • the central axis of the element 109 can be offset in the horizontal direction with respect to the central axis of the first plug 104.
  • the first electrode of the resistance change element 109 may be omitted, and the alteration preventing layer 105C may also function as the first electrode of the resistance change element 109.
  • non-volatile memory element which concerns on the one or several aspect of this invention, and its manufacturing method were demonstrated based on embodiment, this invention is not limited to this embodiment. Unless it deviates from the gist of the present invention, one or more of the present invention may be applied to various modifications that can be conceived by those skilled in the art, or forms constructed by combining components in different embodiments. It may be included within the scope of the embodiments.
  • the transition metal oxide constituting the resistance change layer has been described.
  • the transition metal oxide layer sandwiched between them it is only necessary to include an oxide layer such as tantalum, hafnium, and zirconium as the main resistance change layer that exhibits resistance change. It may be included. It is possible to intentionally include a small amount of other elements by fine adjustment of the resistance value, and such a case is also included in the scope of the present invention. For example, when nitrogen is added to the resistance change layer, the resistance value of the resistance change layer increases and the resistance change resistance can be improved.
  • variable resistance thin film when a variable resistance thin film is formed by sputtering, an unintended trace amount of elements may be mixed into the variable resistance thin film due to residual gas and gas release from the vacuum vessel wall. Naturally, such a trace amount of elements mixed in the resistance change thin film is also included in the scope of the present invention.
  • variable resistance element of the present invention is not limited to this shape.
  • the alteration preventing layer can also prevent alteration with respect to other steps. For example, alteration (oxidation, nitridation, fluorination, etc.) when forming an interlayer insulating layer after plug formation can be prevented.
  • alteration preventing layer of the present invention has an effect of preventing alteration caused by gas or plasma used in the process after plug formation.
  • the variable resistance element is configured by the ReRAM including the variable resistance layer including the oxygen-deficient transition metal oxide.
  • the variable resistance element is used as an electrical signal. Any element that reversibly changes between a high resistance state and a low resistance state having a resistance value lower than that of the high resistance state may be used. Therefore, the resistance change element includes, for example, a phase change memory (PCRAM: Phase-Change RAM) using a phase change material, a magnetic substance as a storage element, and a magnetoresistive memory (MRAM) adopting spin injection magnetization reversal as a writing method. : Magnetoretic RAM) or the like.
  • PCRAM Phase-Change RAM
  • MRAM magnetoresistive memory
  • FeRAM Ferroelectric RAM
  • the nonvolatile memory elements according to the first to fourth embodiments described above are typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
  • the numerical values that define the dimensions of the constituent elements of the nonvolatile memory elements used in the first to fourth embodiments and the process conditions for manufacturing are all examples for specifically explaining the present invention.
  • the present invention is not limited to the exemplified numerical values.
  • all the materials of the constituent elements shown in the above-described Embodiments 1 to 4 are exemplified for specifically explaining the present invention, and the present invention is not limited to the exemplified materials.
  • tungsten nitride or cobalt / tungsten / phosphorous alloy is used as the material for the alteration preventing layer.
  • cobalt / tungsten / boron alloy or palladium is used in addition to these. You can also.
  • variable resistance layer of the variable resistance element has a two-layer structure.
  • a single-layer structure may be used.
  • the present invention can be applied to a variable resistance nonvolatile memory element and a manufacturing method thereof. Further, the present invention is useful for various electronic devices using a nonvolatile memory element.
  • Nonvolatile memory element 101 101C First interlayer insulating layer 102, 102C First wiring 102C 'Wiring material 103 Second interlayer insulating layer 104, 104A First plug 105, 105A 105B, 105C Anti-altering layer 105 ′
  • Cap metal film 106 First electrode 106 ′ First electrode thin film 107 Resistance change layer 107a First resistance change layer 107b Second resistance change layer 107 ′ Resistance change thin film 107a ′ First Resistance change thin film 107b ′ Second resistance change thin film 108 Second electrode 108 ′ Second electrode thin film 109, 109A, 109B Resistance change element 110, 110C Third interlayer insulating layer 111 Second plug 112, 112C Second wiring 112C 'wiring material 113 contact hole 114 recess 115 wiring groove 116 wiring groove 1 0a, 120b Central axis 201 Copper metallization layer 202 Plug 203 IMD layer 204 Groove 205 Barrier layer 206 Copper interconnect layer 207

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Abstract

A non-volatile storage element is provided with a first wiring (102), a first plug (104) which is arranged on and electrically connected with the first wiring (102), an alteration prevention layer (105) which covers the entire region of an upper surface of the first plug (104) and which has electrical conductivity, a variable resistance element (109) which covers a part of an upper surface of the alteration prevention layer (105) and which is electrically coupled with the first plug (104) via the alteration prevention layer (105), and a second wiring (112) which is arranged on and electrically connected with the variable resistance element (109). The variable resistance element (109) includes a variable resistance layer (107) with a state of resistance that reversibly changes on the basis of an electric signal imparted thereto, and the horizontal cross sectional area of a lower surface of the alteration prevention layer (105) is equal to the horizontal cross sectional area of the upper surface of the first plug (104).

Description

不揮発性記憶素子及びその製造方法Nonvolatile memory element and manufacturing method thereof
　本発明は、電気パルスの印加により抵抗値が変化する抵抗変化素子を有する抵抗変化型の不揮発性記憶素子及びその製造方法に関する。 The present invention relates to a variable resistance nonvolatile memory element having a variable resistance element whose resistance value changes by application of an electric pulse, and a method for manufacturing the variable resistance nonvolatile memory element.
　近年、デジタル技術の進展に伴って携帯情報機器及び情報家電等の電子機器が、より一層高機能化している。これらの電子機器の高機能化に伴い、使用される半導体素子の微細化及び高速化が急速に進んでいる。その中でも、フラッシュメモリに代表される大容量の不揮発性メモリの用途が急速に拡大している。さらに、このフラッシュメモリに置き換わる次世代の不揮発性メモリとして、抵抗変化素子を用いた抵抗変化型の不揮発性ＲＡＭ（ＲｅＲＡＭ：Ｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）の研究開発が進んでいる。ここで、抵抗変化素子とは、電気的信号（電気パルス）によって抵抗値が可逆的に変化する性質を有し、この抵抗値に対応した情報を不揮発的に記憶することが可能な素子をいう。 In recent years, electronic devices such as portable information devices and information home appliances have become more sophisticated with the progress of digital technology. As these electronic devices have higher functions, the semiconductor elements used have been rapidly miniaturized and increased in speed. Among them, the use of a large-capacity nonvolatile memory represented by a flash memory is rapidly expanding. Further, as a next-generation nonvolatile memory that replaces this flash memory, research and development of a resistance change type nonvolatile RAM (ReRAM: Resistive Random Access Memory) using a resistance change element is progressing. Here, the resistance change element refers to an element having a property that the resistance value reversibly changes by an electric signal (electric pulse) and can store information corresponding to the resistance value in a nonvolatile manner. .
　この抵抗変化型の不揮発性メモリでは、抵抗変化層が用いられる。電気パルス（例えば電圧パルス）を当該抵抗変化層に印加することによって、抵抗変化層の抵抗値が高抵抗状態から低抵抗状態へ、又は低抵抗状態から高抵抗状態へと変化する。これにより、抵抗変化型の不揮発性記憶素子は、この抵抗値に対応した情報をデータとして記憶する。この場合、１）低抵抗状態及び高抵抗状態の２値を明確に区別し、２）低抵抗状態と高抵抗状態との間を高速に安定して変化させ、３）これら２値が不揮発的に保持され、且つ、４）銅ダマシン技術に適合させ微細化、高集積化を図ることが必要である。 In this variable resistance nonvolatile memory, a variable resistance layer is used. By applying an electric pulse (for example, a voltage pulse) to the variable resistance layer, the resistance value of the variable resistance layer changes from the high resistance state to the low resistance state, or from the low resistance state to the high resistance state. Thereby, the variable resistance nonvolatile memory element stores information corresponding to the resistance value as data. In this case, 1) the two values of the low resistance state and the high resistance state are clearly distinguished, 2) the low resistance state and the high resistance state are stably changed at high speed, and 3) these two values are nonvolatile. 4) It is necessary to adapt to copper damascene technology and to achieve miniaturization and high integration.
　特許文献１及び２には、抵抗変化素子を搭載した不揮発性記憶素子の例として、銅ダマシン技術に適合し、より複雑でない方法で製造することができる電気デバイスが開示されている。この電気デバイスは、パンチスルーダイオードとプログラマブル抵抗器とが電気的に直列接続されることにより構成されている。 Patent Documents 1 and 2 disclose, as examples of nonvolatile memory elements equipped with variable resistance elements, electrical devices that are compatible with copper damascene technology and can be manufactured by a less complicated method. This electric device is configured by electrically connecting a punch-through diode and a programmable resistor in series.
　図１３は、特許文献１に記載された、従来の抵抗変化型の不揮発性記憶素子を示す断面図である。図１３に示す不揮発性記憶素子５０は、次のようにして製造される。まず、銅メタライゼーション層２０１及びこれに対応するプラグ２０２が形成された後に、プラグ２０２上に第１の積層体２０７が形成される。この第１の積層体２０７は、バリア層２０８（例えば、タンタル（Ｔａ））、コンタクト層２０９（例えば、金ゲルマニウムニッケル（ＡｕＧｅＮｉ））、半導体２１０（例えば、ｎ型ガリウム砒素（ＧａＡｓ））、再びコンタクト層２１１及びバリア層２１２がこの順に堆積されることにより形成される。このようにしてパンチスルーダイオードが形成される。 FIG. 13 is a cross-sectional view showing a conventional variable resistance nonvolatile memory element described in Patent Document 1. In FIG. The nonvolatile memory element 50 shown in FIG. 13 is manufactured as follows. First, after the copper metallization layer 201 and the corresponding plug 202 are formed, the first stacked body 207 is formed on the plug 202. The first stacked body 207 includes a barrier layer 208 (eg, tantalum (Ta)), a contact layer 209 (eg, gold germanium nickel (AuGeNi)), a semiconductor 210 (eg, n-type gallium arsenide (GaAs)), The contact layer 211 and the barrier layer 212 are formed by depositing in this order. Thus, a punch-through diode is formed.
　その後、第１の積層体２０７上に第２の積層体２１３が形成される。この第２の積層体２１３は、バリア層２１４、電極層２１５、ＰＭＣ（Ｐｒｏｇｒａｍｍａｂｌｅ　Ｍｅｔａｌｌｉｚａｔｉｏｎ　Ｃｅｌｌ）材料２１６、コンタクト層２１７及びバリア層２１８がスパッタリングによってこの順に堆積されることにより形成される。第１の積層体２０７及び第２の積層体２１３がパターニングされた後、金属間誘電体層（図示せず）が堆積される。金属間誘電体層は誘電体膜ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）により、その表面が平坦化される。このようにしてプログラマブル抵抗器が形成される。 Thereafter, the second stacked body 213 is formed on the first stacked body 207. The second stacked body 213 is formed by depositing a barrier layer 214, an electrode layer 215, a PMC (Programmable Metallization Cell) material 216, a contact layer 217, and a barrier layer 218 in this order by sputtering. After the first stack 207 and the second stack 213 are patterned, an intermetal dielectric layer (not shown) is deposited. The surface of the intermetal dielectric layer is planarized by a dielectric film CMP (Chemical Mechanical Polishing). In this way, a programmable resistor is formed.
　その後、ＩＭＤ（Ｉｎｔｅｒ　Ｍｅｔａｌ　Ｄｉｅｌｅｃｔｒｉｃ）層２０３が堆積され、エッチングによりＩＭＤ層２０３の上面に溝２０４が形成される。溝２０４がバリア層２０５及び銅によって充填された後に、銅ＣＭＰが行われる。このようにして、銅相互接続層２０６が形成される。 Thereafter, an IMD (Inter Metal Dielectric) layer 203 is deposited, and a groove 204 is formed on the upper surface of the IMD layer 203 by etching. After the trench 204 is filled with the barrier layer 205 and copper, copper CMP is performed. In this way, a copper interconnect layer 206 is formed.
　上述した製造工程は、複数回繰り返すことができる。これにより、個々にアクセス可能なメモリ素子の層を複数有する電気デバイスの製造が可能になる。即ち、メモリ素子の３次元アレイを構成することが可能になる。 The manufacturing process described above can be repeated multiple times. This allows the manufacture of electrical devices having multiple layers of individually accessible memory elements. That is, a three-dimensional array of memory elements can be configured.
国際公開第２００５／１２４７８７号International Publication No. 2005/124787 国際公開第２００９／０５０８３３号International Publication No. 2009/050833
　本発明者は、後述するように、従来の不揮発性記憶素子において、不揮発性記憶素子の下に形成されたプラグの上面のうち不揮発性記憶素子の積層体に覆われていない部分が、プラグ形成後の工程で用いるガス又はプラズマ等によって曝されて、酸化又は変質する不具合を見出した。この不具合により、プラグの電気的特性が損なわれるという問題が生じる。 As will be described later, the present inventor, in a conventional nonvolatile memory element, a portion of the upper surface of the plug formed under the nonvolatile memory element that is not covered with the stack of nonvolatile memory elements is plug-formed. It was found that there was a problem in that it was oxidized or deteriorated by exposure to gas or plasma used in a later process. This problem causes a problem that the electrical characteristics of the plug are impaired.
　本発明は、上記の課題を解決するためになされたものであり、その目的は、プラグの電気的特性を良好に保つことができる不揮発性記憶素子及びその製造方法を提供することである。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory element that can maintain good electrical characteristics of a plug and a method for manufacturing the same.
　上記目的を達成するために、本発明の一態様に係る不揮発性記憶素子は、第１の配線と、前記第１の配線上に配置され、前記第１の配線に電気的に接続されるプラグと、前記プラグの上面の全域を覆い、導電性を有する変質防止層と、前記変質防止層の上面の一部を覆い、前記変質防止層を介して前記プラグに電気的に接続される積層体と、前記積層体上に配置され、前記積層体に電気的に接続される第２の配線と、を備え、前記積層体は、与えられる電気的信号に基づいて抵抗状態が可逆的に変化する抵抗変化層を含み、前記変質防止層の下面の水平断面積は、前記プラグの上面の水平断面積と等しく、前記変質防止層の上面の一部は、前記積層体で覆われていない。 In order to achieve the above object, a nonvolatile memory element according to one embodiment of the present invention includes a first wiring and a plug that is disposed over the first wiring and electrically connected to the first wiring. And a whole of the upper surface of the plug, covering the entire surface of the anti-altering layer, covering a part of the upper surface of the anti-altering layer, and electrically connected to the plug via the anti-altering layer. And a second wiring that is disposed on the stacked body and electrically connected to the stacked body, the resistance state of the stacked body reversibly changes based on an applied electrical signal. The resistance change layer is included, the horizontal cross-sectional area of the lower surface of the alteration preventing layer is equal to the horizontal sectional area of the upper surface of the plug, and a part of the upper surface of the alteration preventing layer is not covered with the laminate.
　以上説明したように、本発明の不揮発性記憶素子は、不揮発性記憶素子の下に形成されたプラグの上面の全域が変質防止層によって覆われているので、プラグ形成の工程で用いるガス又はプラズマ等にプラグの上面が曝されることがない。そのため、プラグの上面において酸化又は変質が起きるのを防止することができ、プラグの電気的特性を良好に保つことができる。これにより、抵抗変化素子を含む不揮発性記憶素子において、良好な電気的特性が得られるデバイス構造を有する不揮発性記憶素子及びその製造方法を提供することができる。 As described above, in the nonvolatile memory element of the present invention, since the entire upper surface of the plug formed under the nonvolatile memory element is covered with the alteration preventing layer, the gas or plasma used in the plug forming process is used. Etc., the upper surface of the plug is not exposed. Therefore, oxidation or alteration on the upper surface of the plug can be prevented, and the electrical characteristics of the plug can be kept good. Thereby, in the nonvolatile memory element including the resistance change element, it is possible to provide a nonvolatile memory element having a device structure capable of obtaining good electrical characteristics and a method for manufacturing the nonvolatile memory element.
図１は、本発明の実施の形態１に係る不揮発性記憶素子の構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention. 図２Ａは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 2A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図２Ｂは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 2B is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図２Ｃは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 2C is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図３Ａは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 3A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図３Ｂは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 3B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図４Ａは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 4A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図４Ｂは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 4B is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図５Ａは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 5A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図５Ｂは、本発明の実施の形態１に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 5B is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention. 図６は、本発明の実施の形態２に係る不揮発性記憶素子の構成を示す断面図である。FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 2 of the present invention. 図７は、本発明の実施の形態３に係る不揮発性記憶素子の構成を示す断面図である。FIG. 7 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 3 of the present invention. 図８は、本発明の実施の形態４に係る不揮発性記憶素子の構成を示す断面図である。FIG. 8 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 4 of the present invention. 図９Ａは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 9A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図９Ｂは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 9B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図９Ｃは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 9C is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１０Ａは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 10A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１０Ｂは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 10B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１０Ｃは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 10C is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１１Ａは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 11A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１１Ｂは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 11B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１２Ａは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 12A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１２Ｂは、本発明の実施の形態４に係る不揮発性記憶素子の製造方法を示す断面図である。FIG. 12B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention. 図１３は、従来の不揮発性記憶素子の構成を示す断面図である。FIG. 13 is a cross-sectional view showing a configuration of a conventional nonvolatile memory element. 図１４は、従来の不揮発性記憶素子の不具合実例を示す、不揮発性記憶素子の断面の電子顕微鏡写真である。FIG. 14 is an electron micrograph of a cross section of a nonvolatile memory element showing an example of a defect of a conventional nonvolatile memory element.
　（本発明の基礎となった知見）
　まず、本発明の実施の形態を説明する前に、本発明者が見出した、従来の不揮発性記憶素子において生じる不具合について説明する。なお、以下の説明は、本発明を理解する上で一助となるものであるが、以下の種々の条件等は本発明を限定するものではない。 (Knowledge that became the basis of the present invention)
First, before describing the embodiments of the present invention, problems that occur in the conventional nonvolatile memory element found by the present inventor will be described. In addition, although the following description helps to understand this invention, the following various conditions etc. do not limit this invention.
　図１４は、本発明者が作製した従来の不揮発性記憶素子の断面の電子顕微鏡写真である。図１４に示す従来の不揮発性記憶素子は、下層プラグ３０１の上に抵抗変化素子３０２が配置され、抵抗変化素子３０２の上に上層プラグ３０３が配置されている。図１４に示される実験例では、下層プラグ３０１の上面の水平断面積と抵抗変化素子３０２の下面の水平断面積とはほぼ等しく、抵抗変化素子３０２の中心軸が下層プラグ３０１の中心軸に対して水平方向（図１４において右方向）に位置ずれしている。そのため、下層プラグ３０１の上面には、抵抗変化素子３０２で覆われていない露出部分が生じている。 FIG. 14 is an electron micrograph of a cross section of a conventional nonvolatile memory element produced by the present inventors. In the conventional nonvolatile memory element shown in FIG. 14, the resistance change element 302 is disposed on the lower layer plug 301, and the upper layer plug 303 is disposed on the resistance change element 302. In the experimental example shown in FIG. 14, the horizontal cross-sectional area of the upper surface of the lower layer plug 301 and the horizontal cross-sectional area of the lower surface of the variable resistance element 302 are substantially equal, and the central axis of the variable resistance element 302 is relative to the central axis of the lower layer plug 301. Thus, the position is shifted in the horizontal direction (right direction in FIG. 14). Therefore, an exposed portion that is not covered with the resistance change element 302 is generated on the upper surface of the lower layer plug 301.
　図１４の実験例では、下層プラグ３０１の一部に不具合領域３０４が発生している。この不具合領域３０４は、抵抗変化素子３０２をドット形状に加工するドライエッチング工程及びレジストアッシング工程、或いは、抵抗変化素子３０２の側壁面を酸化して絶縁化することによりアクティブ面積（即ち、抵抗変化素子の電気的特性に影響する実効面積）を縮小する工程が行われる際に、下層プラグ３０１の上面の露出部分において酸化又は変質が起こることにより発生したと考えられる。なお、この不具合領域３０４は、図１４に示されるように、電子顕微鏡写真のコントラストの違いにより容易に判別することができる。 In the experimental example of FIG. 14, a defective area 304 occurs in a part of the lower layer plug 301. The defect region 304 is formed by an active area (that is, a resistance change element) by insulating a side wall surface of the resistance change element 302 by a dry etching process and a resist ashing process in which the resistance change element 302 is processed into a dot shape. It is considered that this is caused by oxidation or alteration occurring in the exposed portion of the upper surface of the lower layer plug 301 when the step of reducing the effective area that affects the electrical characteristics of the lower layer plug 301 is performed. Note that the defect area 304 can be easily identified by the difference in contrast of the electron micrograph as shown in FIG.
　従来の典型的な不揮発性記憶素子は、抵抗変化素子（積層体）の下面の水平断面積が、下層プラグの上面の水平断面積よりも十分に大きかった。そのため、積層体と下層プラグとの水平方向の位置ずれが起こった場合であっても、下層プラグの上面の全域が積層体に覆われていた。そのため、位置ずれによって露出した下層プラグの上面の一部が、積層体を加工する際のドライエッチングに用いられるエッチングガス又はプラズマ等に曝されること等は考え難く、下層プラグの表面に酸化又は変質が起こる懸念はなかった。 In the conventional typical nonvolatile memory element, the horizontal sectional area of the lower surface of the resistance change element (laminated body) was sufficiently larger than the horizontal sectional area of the upper surface of the lower layer plug. Therefore, even when the horizontal displacement between the multilayer body and the lower layer plug occurs, the entire upper surface of the lower layer plug is covered with the multilayer body. Therefore, it is difficult to think that a part of the upper surface of the lower layer plug exposed by the misalignment is exposed to an etching gas or plasma used for dry etching when processing the laminated body. There were no concerns about alteration.
　しかしながら、近年では、メモリ素子の集積度を向上させるために、抵抗変化素子（積層体）の水平断面積が微細化される傾向にある。このため、積層体の下面の水平断面積は、下層プラグの上面の水平断面積と等しく又は下層プラグの上面の水平断面積よりも小さくなる傾向にある。そのような場合、上記図１４に示されるような不具合領域３０４の発生は、より深刻な問題となる。下層プラグの一部が酸化又は変質すると、下層プラグが高抵抗化する等の電気的特性不良が発生し、その結果、抵抗変化素子に印加される書き込み電圧が不安定となる等の問題が生じる。 However, in recent years, the horizontal cross-sectional area of the resistance change element (laminated body) tends to be miniaturized in order to improve the integration degree of the memory element. For this reason, the horizontal cross-sectional area of the lower surface of the laminated body tends to be equal to or smaller than the horizontal cross-sectional area of the upper surface of the lower layer plug. In such a case, the occurrence of the defect area 304 as shown in FIG. 14 becomes a more serious problem. If a part of the lower layer plug is oxidized or deteriorated, an electrical characteristic failure such as an increase in resistance of the lower layer plug occurs, and as a result, a problem such as an unstable write voltage applied to the variable resistance element occurs. .
　そこで、本発明者は、上記知見に基づいて、鋭意検討した結果、変質防止層を備える構成とすることによって、上記の不具合を解消することができる不揮発性記憶素子を考案した。 Therefore, as a result of intensive studies based on the above knowledge, the present inventor has devised a nonvolatile memory element that can eliminate the above-described problems by adopting a structure including an alteration preventing layer.
　本発明の一態様に係る不揮発性記憶素子は、第１の配線と、前記第１の配線上に配置され、前記第１の配線に電気的に接続されるプラグと、前記プラグの上面の全域を覆い、導電性を有する変質防止層と、前記変質防止層の上面の一部を覆い、前記変質防止層を介して前記プラグに電気的に接続される積層体と、前記積層体上に配置され、前記積層体に電気的に接続される第２の配線と、を備え、前記積層体は、与えられる電気的信号に基づいて抵抗状態が可逆的に変化する抵抗変化層を含み、前記変質防止層の下面の水平断面積は、前記プラグの上面の水平断面積と等しく、前記変質防止層の上面の一部は、前記積層体で覆われていない。 A nonvolatile memory element according to one embodiment of the present invention includes a first wiring, a plug disposed over the first wiring and electrically connected to the first wiring, and the entire upper surface of the plug. An anti-altering layer having electrical conductivity, a laminate covering a part of the upper surface of the anti-altering layer, and electrically connected to the plug via the anti-altering layer, and disposed on the laminate And a second wiring electrically connected to the laminate, the laminate including a resistance change layer whose resistance state reversibly changes based on an applied electric signal, and the alteration The horizontal sectional area of the lower surface of the prevention layer is equal to the horizontal sectional area of the upper surface of the plug, and a part of the upper surface of the alteration preventing layer is not covered with the laminate.
　本態様によれば、プラグの上面の全域が変質防止層によって覆われているので、プラグ形成後の工程で用いるガス又はプラズマ等にプラグの上面が曝されることがない。そのため、プラグの上面において酸化又は変質が起きるのを防止することができ、プラグの電気的特性を良好に保つことができる。また、積層体のアクティブ面積を縮小させるために、積層体の側壁面を酸化させる工程においても、プラグの上面において酸化又は変質が起きるのを防止することができる。プラグの電気的特性を良好に保つことにより、抵抗変化層に印加される書き込み電圧を安定化することができる。 According to this aspect, since the entire upper surface of the plug is covered with the alteration preventing layer, the upper surface of the plug is not exposed to gas or plasma used in the process after the plug is formed. Therefore, oxidation or alteration on the upper surface of the plug can be prevented, and the electrical characteristics of the plug can be kept good. Further, even in the step of oxidizing the side wall surface of the stacked body in order to reduce the active area of the stacked body, it is possible to prevent oxidation or degeneration on the upper surface of the plug. By maintaining good electrical characteristics of the plug, the write voltage applied to the variable resistance layer can be stabilized.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記積層体はさらに、前記変質防止層を介して前記プラグに電気的に接続される第１電極と、前記第２の配線に電気的に接続される第２電極と、を含み、前記抵抗変化層は、前記第１電極と前記第２電極との間に配置されているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the stacked body further includes a first electrode electrically connected to the plug through the alteration preventing layer, and an electrical connection to the second wiring. And the variable resistance layer may be configured to be disposed between the first electrode and the second electrode.
　本態様によれば、積層体は、第１電極、抵抗変化層及び第２電極がこの順に積層されることにより構成される。このような積層体によって抵抗変化素子を構成することができる。 According to this aspect, the laminate is configured by laminating the first electrode, the resistance change layer, and the second electrode in this order. A resistance change element can be comprised by such a laminated body.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記第１電極の下面の水平断面積は、前記変質防止層の上面の水平断面積よりも小さいように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the horizontal cross-sectional area of the lower surface of the first electrode may be configured to be smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer.
　本態様によれば、第１電極の下面の水平断面積が変質防止層の上面の水平断面積よりも小さいために、変質防止層の上面の一部が第１電極によって覆われずに露出される。このような場合であっても、プラグの上面の全域が変質防止層によって覆われているので、プラグ形成後の工程で用いるガス又はプラズマ等にプラグの上面が曝されるのを防止することができる。 According to this aspect, since the horizontal sectional area of the lower surface of the first electrode is smaller than the horizontal sectional area of the upper surface of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the first electrode. The Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記第１電極の下面の水平断面積は、前記変質防止層の上面の水平断面積と等しい又は前記変質防止層の上面の水平断面積よりも大きく、前記積層体の中心軸は、前記変質防止層の中心軸に対して偏倚し、前記変質防止層の上面の一部は、前記第１電極で覆われていないように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the horizontal cross-sectional area of the lower surface of the first electrode is equal to the horizontal cross-sectional area of the upper surface of the alteration preventing layer or the horizontal sectional area of the upper surface of the alteration preventing layer. The center axis of the laminate is deviated from the center axis of the alteration preventing layer, and a part of the upper surface of the alteration preventing layer is not covered with the first electrode. Also good.
　本態様によれば、積層体の中心軸が変質防止層の中心軸に対して偏倚しているために、変質防止層の上面の一部が第１電極によって覆われずに露出される。このような場合であっても、プラグの上面の全域が変質防止層によって覆われているので、プラグ形成後の工程で用いるガス又はプラズマ等にプラグの上面が曝されるのを防止することができる。 According to this aspect, since the central axis of the laminate is deviated from the central axis of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the first electrode. Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記変質防止層は、前記プラグに電気的に接続される第１電極として機能し、前記積層体はさらに、前記第２の配線に電気的に接続される第２電極を含み、前記抵抗変化層は、前記第１電極としての前記変質防止層と前記第２電極との間に配置されているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the alteration preventing layer functions as a first electrode that is electrically connected to the plug, and the stacked body is further electrically connected to the second wiring. The resistance change layer may be arranged between the alteration preventing layer as the first electrode and the second electrode.
　本態様によれば、変質防止層が第１電極としても機能するので、変質防止層と第１電極とを別個の層で構成する場合に比べて、工程数を削減することができる。 According to this aspect, since the alteration preventing layer also functions as the first electrode, the number of steps can be reduced as compared with the case where the alteration preventing layer and the first electrode are formed of separate layers.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記抵抗変化層の下面の水平断面積は、前記変質防止層の上面の水平断面積よりも小さいように構成してもよい。 For example, in the nonvolatile memory element according to one aspect of the present invention, the horizontal cross-sectional area of the lower surface of the variable resistance layer may be configured to be smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer.
　本態様によれば、抵抗変化層の下面の水平断面積が変質防止層の上面の水平断面積よりも小さいために、変質防止層の上面の一部が抵抗変化層によって覆われずに露出される。このような場合であっても、プラグの上面の全域が変質防止層によって覆われているので、プラグ形成後の工程で用いるガス又はプラズマ等にプラグの上面が曝されるのを防止することができる。 According to this aspect, since the horizontal cross-sectional area of the lower surface of the resistance change layer is smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the resistance change layer. The Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記抵抗変化層の下面の水平断面積は、前記変質防止層の上面の水平断面積と等しい又は前記変質防止層の上面の水平断面積よりも大きく、前記積層体の中心軸は、前記変質防止層の中心軸に対して偏倚し、前記変質防止層の上面の一部は、前記抵抗変化層で覆われていないように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the horizontal cross-sectional area of the lower surface of the resistance change layer is equal to the horizontal cross-sectional area of the upper surface of the alteration preventing layer or the horizontal sectional area of the upper surface of the alteration preventing layer. The center axis of the laminate is deviated from the center axis of the alteration preventing layer, and a part of the upper surface of the alteration preventing layer is not covered with the resistance change layer. Also good.
　本態様によれば、積層体の中心軸が変質防止層の中心軸に対して偏倚しているために、変質防止層の上面の一部が抵抗変化層によって覆われずに露出される。このような場合であっても、プラグの上面の全域が変質防止層によって覆われているので、プラグ形成後の工程で用いるガス又はプラズマ等にプラグの上面が曝されるのを防止することができる。 According to this aspect, since the central axis of the laminate is deviated from the central axis of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the resistance change layer. Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
　例えば、本発明の一態様に係る不揮発性記憶素子において、さらに、前記第１の配線上に配置され、コンタクトホールを有する層間絶縁層を備え、前記プラグ及び前記変質防止層はともに、前記コンタクトホールに埋め込まれているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the nonvolatile memory element further includes an interlayer insulating layer disposed on the first wiring and having a contact hole. The plug and the alteration preventing layer are both the contact hole. You may comprise so that it may be embedded in.
　本態様によれば、プラグ及び変質防止層はともに、層間絶縁層のコンタクトホールに埋め込まれているので、不揮発性記憶素子が間隔を置いて複数配置されている際に、隣接するプラグがショートするのを確実に防止することができる。 According to this aspect, since the plug and the alteration preventing layer are both embedded in the contact hole of the interlayer insulating layer, adjacent plugs are short-circuited when a plurality of nonvolatile memory elements are arranged at intervals. Can be surely prevented.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記変質防止層は、前記プラグを構成する金属の窒化物で構成されるように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the alteration preventing layer may be configured to be composed of a metal nitride that forms the plug.
　本態様によれば、窒化処理によって、変質防止層をプラグの上面に容易に形成することができる。 According to this aspect, the alteration preventing layer can be easily formed on the upper surface of the plug by nitriding.
　例えば、本発明の一態様に係る不揮発性記憶素子において、さらに、前記第１の配線上に配置され、コンタクトホールを有する層間絶縁層を備え、前記プラグは前記コンタクトホールに埋め込まれ、前記変質防止層は、前記コンタクトホールの外部に突出されているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the nonvolatile memory element further includes an interlayer insulating layer disposed on the first wiring and having a contact hole. The plug is embedded in the contact hole, and the alteration prevention is performed. The layer may be configured to protrude outside the contact hole.
　本態様によれば、プラグは層間絶縁層のコンタクトホールに埋め込まれ、変質防止層はコンタクトホールの外部に突出されているので、例えば変質防止層の上面を平坦化する際に、層間絶縁層の上面が削られてしまうロスを抑制することができる。 According to this aspect, since the plug is embedded in the contact hole of the interlayer insulating layer and the alteration preventing layer protrudes outside the contact hole, for example, when the upper surface of the alteration preventing layer is planarized, Loss that the upper surface is scraped can be suppressed.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記プラグは、タングステン又は銅で構成されているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the plug may be formed of tungsten or copper.
　本態様によれば、プラグをタングステン又は銅で構成することができる。 According to this aspect, the plug can be made of tungsten or copper.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記変質防止層は、酸素バリア性及び耐エッチング性を有するように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the alteration preventing layer may be configured to have an oxygen barrier property and an etching resistance.
　本態様によれば、変質防止層は、酸素バリア性及び耐エッチング性を有するので、例えばプラグ形成後のエッチング工程で、変質防止層がエッチングガスの影響を受けるのを抑制することができる。 According to this aspect, since the alteration preventing layer has an oxygen barrier property and etching resistance, it is possible to suppress the alteration preventing layer from being affected by the etching gas, for example, in an etching process after forming the plug.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記変質防止層は、タングステン窒化物、コバルト・タングステン・リン合金、コバルト・タングステン・ボロン合金及びパラジウムのいずれかで構成されているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the alteration preventing layer is formed of any one of tungsten nitride, cobalt-tungsten-phosphorus alloy, cobalt-tungsten-boron alloy, and palladium. It may be configured.
　本態様によれば、変質防止層は、タングステン窒化物、コバルト・タングステン・リン合金、コバルト・タングステン・ボロン合金及びパラジウムのいずれかで構成されているので、変質防止層がエッチングガスの影響を受けるのを効果的に抑制することができる。 According to this aspect, since the alteration preventing layer is composed of any one of tungsten nitride, cobalt tungsten phosphorous alloy, cobalt tungsten tungsten boron alloy and palladium, the alteration preventing layer is affected by the etching gas. Can be effectively suppressed.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記抵抗変化層は、遷移金属酸化物又はアルミニウム酸化物で構成されているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the resistance change layer may be configured of a transition metal oxide or an aluminum oxide.
　本態様によれば、抵抗変化層を遷移金属酸化物又はアルミニウム酸化物で構成することができる。 According to this aspect, the variable resistance layer can be composed of a transition metal oxide or an aluminum oxide.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記抵抗変化層は、酸素不足型タンタル酸化物、酸素不足型ハフニウム酸化物及び酸素不足型ジルコニウム酸化物のうちの１つ以上の遷移金属酸化物で構成されているように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the variable resistance layer includes at least one transition metal selected from oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, and oxygen-deficient zirconium oxide. You may comprise so that it may be comprised with the oxide.
　本態様によれば、抵抗変化層は、酸素不足型タンタル酸化物、酸素不足型ハフニウム酸化物及び酸素不足型ジルコニウム酸化物のうちの１つ以上の遷移金属酸化物で構成されているので、動作の高速性に加えて、可逆的に安定した書き換え特性及び良好な抵抗値のリテンション特性を有する不揮発性記憶素子を実現することができる。特に、抵抗変化層を酸素不足型タンタル酸化物で構成した場合には、通常のＳｉ半導体プロセスに対して親和性の高い製造プロセスで不揮発性記憶素子を製造することができる。 According to this aspect, since the resistance change layer is composed of one or more transition metal oxides of oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, and oxygen-deficient zirconium oxide, In addition to the high speed, a non-volatile memory element having reversibly stable rewriting characteristics and good resistance retention characteristics can be realized. In particular, when the variable resistance layer is made of an oxygen-deficient tantalum oxide, the nonvolatile memory element can be manufactured by a manufacturing process having a high affinity for a normal Si semiconductor process.
　例えば、本発明の一態様に係る不揮発性記憶素子において、前記抵抗変化層は、第１の金属酸化物で構成される第１の抵抗変化層と、前記第１の金属酸化物より酸素不足度が小さい第２の金属酸化物で構成される第２の抵抗変化層と、を有するように構成してもよい。 For example, in the nonvolatile memory element according to one embodiment of the present invention, the resistance change layer includes a first resistance change layer including a first metal oxide, and a degree of oxygen deficiency higher than that of the first metal oxide. And a second variable resistance layer composed of a second metal oxide having a small thickness.
　本態様によれば、抵抗変化層を酸素不足度が異なる２種類の金属酸化物を積層して構成することによって、抵抗変化する極性が常に安定し、不揮発性記憶素子の動作特性を安定化させることができる。 According to this aspect, the resistance change layer is formed by stacking two types of metal oxides having different degrees of oxygen deficiency, so that the polarity of resistance change is always stable and the operation characteristics of the nonvolatile memory element are stabilized. be able to.
　また、本発明の一態様に係る不揮発性記憶素子の製造方法は、第１の配線を形成する工程と、前記第１の配線上に、前記第１の配線に電気的に接続されるプラグを形成する工程と、前記プラグの上面の全域を覆い且つ導電性を有する変質防止層を形成する工程と、前記変質防止層の上面の一部を覆い且つ前記変質防止層を介して前記プラグに電気的に接続される積層体を形成する工程と、前記積層体上に配置され且つ前記積層体に電気的に接続される第２の配線を形成する工程と、を含み、前記変質防止層を形成する工程では、前記変質防止層の下面の水平断面積が前記プラグの上面の水平断面積と等しくなるように前記変質防止層を形成し、前記積層体を形成する工程では、前記変質防止層の上面の一部が前記積層体で覆われないように前記積層体を形成し、前記積層体は、与えられる電気的信号に基づいて抵抗状態が可逆的に変化する抵抗変化層を含む。 The method for manufacturing a nonvolatile memory element according to one embodiment of the present invention includes a step of forming a first wiring, and a plug electrically connected to the first wiring over the first wiring. A step of forming, a step of forming an anti-altering layer covering the entire upper surface of the plug and having conductivity, and an electrical connection to the plug through the anti-altering layer covering a part of the upper surface of the anti-altering layer. Forming a layered structure to be connected to each other, and forming a second wiring disposed on the layered body and electrically connected to the layered body, and forming the alteration preventing layer In the step of forming the alteration preventing layer so that the horizontal sectional area of the lower surface of the alteration preventing layer is equal to the horizontal sectional area of the upper surface of the plug, and in the step of forming the laminated body, A part of the upper surface is not covered with the laminate. Serial to form a laminate, said laminate comprises a variable resistance layer resistance state reversibly changes based on an electrical signal applied.
　本態様によれば、プラグの上面の全域を覆うように変質防止層を形成するので、プラグ形成後の工程で用いるガス又はプラズマ等にプラグの上面が曝されることがない。そのため、プラグの上面において酸化又は変質が起きるのを防止することができ、電気的特性が良好なプラグを有する不揮発性記憶素子を製造することができる。 According to this aspect, since the alteration preventing layer is formed so as to cover the entire area of the upper surface of the plug, the upper surface of the plug is not exposed to gas or plasma used in the process after the plug is formed. Therefore, oxidation or alteration can be prevented from occurring on the upper surface of the plug, and a nonvolatile memory element having a plug with good electrical characteristics can be manufactured.
　例えば、本発明の一態様に係る不揮発性記憶素子の製造方法において、前記積層体を形成する工程は、さらに、前記変質防止層を介して前記プラグに電気的に接続される第１電極を形成する工程と、前記第１電極上に前記抵抗変化層を形成する工程と、前記抵抗変化層上に第２電極を形成する工程と、を含み、前記第２の配線を形成する工程では、前記第２電極と電気的に接続される前記第２の配線を形成するように構成してもよい。 For example, in the method for manufacturing a nonvolatile memory element according to one embodiment of the present invention, the step of forming the stacked body further includes forming a first electrode electrically connected to the plug through the alteration preventing layer. Including the steps of: forming the resistance change layer on the first electrode; forming the second electrode on the resistance change layer; and forming the second wiring, The second wiring electrically connected to the second electrode may be formed.
　本態様によれば、積層体は、第１電極、抵抗変化層及び第２電極がこの順に積層されることにより形成される。このような積層体によって抵抗変化素子を形成することができる。 According to this aspect, the laminate is formed by laminating the first electrode, the resistance change layer, and the second electrode in this order. A resistance change element can be formed by such a laminated body.
　例えば、本発明の一態様に係る不揮発性記憶素子の製造方法において、前記変質防止層を形成する工程では、前記プラグに電気的に接続される第１電極として機能する前記変質防止層を形成し、前記積層体を形成する工程では、前記変質防止層上に前記抵抗変化層を形成する工程と、前記抵抗変化層上に第２電極を形成する工程と、を含み、前記第２の配線を形成する工程では、前記第２電極と電気的に接続される前記第２の配線を形成するように構成してもよい。 For example, in the method for manufacturing a nonvolatile memory element according to one embodiment of the present invention, in the step of forming the alteration preventing layer, the alteration preventing layer that functions as a first electrode electrically connected to the plug is formed. The step of forming the laminated body includes a step of forming the resistance change layer on the alteration preventing layer and a step of forming a second electrode on the resistance change layer, and the second wiring is formed. In the forming step, the second wiring electrically connected to the second electrode may be formed.
　本態様によれば、変質防止層と第１電極とを別個の層として形成する場合に比べて、不揮発性記憶素子の製造工程を簡略化することができる。 According to this aspect, the manufacturing process of the nonvolatile memory element can be simplified as compared with the case where the alteration preventing layer and the first electrode are formed as separate layers.
　例えば、本発明の一態様に係る不揮発性記憶素子の製造方法において、前記変質防止層を形成する工程では、前記プラグの上面の全域を窒化することにより前記変質防止層を形成するように構成してもよい。 For example, in the method for manufacturing a nonvolatile memory element according to one aspect of the present invention, in the step of forming the alteration preventing layer, the alteration preventing layer is formed by nitriding the entire upper surface of the plug. May be.
　本態様によれば、窒化処理によって、変質防止層をプラグの上面に容易に形成することができる。 According to this aspect, the alteration preventing layer can be easily formed on the upper surface of the plug by nitriding.
　例えば、本発明の一態様に係る不揮発性記憶素子の製造方法において、前記変質防止層を形成する工程では、無電解めっきによって前記変質防止層を形成するように構成してもよい。 For example, in the method for manufacturing a nonvolatile memory element according to one embodiment of the present invention, in the step of forming the alteration preventing layer, the alteration preventing layer may be formed by electroless plating.
　本態様によれば、無電解めっき処理によって、変質防止層をプラグの上面に容易に形成することができる。 According to this aspect, the alteration preventing layer can be easily formed on the upper surface of the plug by electroless plating.
　以下、本発明の一態様に係る抵抗変化型の不揮発性記憶素子（以下、単に「不揮発性記憶素子」ともいう）及びその製造方法について、図面を参照しながら説明する。 Hereinafter, a variable resistance nonvolatile memory element (hereinafter also simply referred to as “nonvolatile memory element”) and a manufacturing method thereof according to one embodiment of the present invention will be described with reference to the drawings.
　なお、以下で説明する実施の形態は、いずれも包括的又は具体的な例を示すものである。以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、ステップ、ステップの順序等は、一例であり、本発明を限定する主旨ではない。また、以下の実施の形態における構成要素のうち、最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。図面において同じ符号が付与された構成要素については、説明を省略する場合がある。また、図面は理解しやすくするために、それぞれの構成要素を模式的に示したものであり、形状及び寸法等については正確な表示ではない。 Note that all of the embodiments described below show a comprehensive or specific example. Numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements. The description of the components given the same reference numerals in the drawings may be omitted. In addition, the drawings schematically show each component for easy understanding, and the shape, dimensions, etc. are not accurate.
　（実施の形態１）
　図１は、本発明の実施の形態１に係る不揮発性記憶素子１０の構成を示す断面図である。図１に示す不揮発性記憶素子１０は、第１の層間絶縁層１０１、第１の配線１０２、第２の層間絶縁層１０３、第１のプラグ１０４、変質防止層１０５、抵抗変化素子１０９（積層体を構成する）、第３の層間絶縁層１１０、第２のプラグ１１１及び第２の配線１１２を備えている。 (Embodiment 1)
FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element 10 according to Embodiment 1 of the present invention. A nonvolatile memory element 10 shown in FIG. 1 includes a first interlayer insulating layer 101, a first wiring 102, a second interlayer insulating layer 103, a first plug 104, an alteration preventing layer 105, a resistance change element 109 (laminated layer). A third interlayer insulating layer 110, a second plug 111, and a second wiring 112.
　このような不揮発性記憶素子１０は、一般的な半導体記憶装置においてメモリセルアレイ又はメモリ本体部等と呼ばれる領域の一部分を構成する。なお、半導体記憶装置は、このような不揮発性記憶素子１０を含むメモリセルアレイとともに、メモリセルアレイを駆動するための駆動回路を備えていてもよい。駆動回路は、メモリセルアレイ中の不揮発性記憶素子１０に電気パルス（電気的信号）を印加する。不揮発性記憶素子１０の抵抗変化素子１０９の抵抗状態は、データ書き込み用の電気パルスによって可逆的に変化される。また、不揮発性記憶素子１０の抵抗変化素子１０９の抵抗状態は、データ読み出し用の電気パルスによって読み出される。 Such a nonvolatile memory element 10 constitutes a part of a region called a memory cell array or a memory main body in a general semiconductor memory device. The semiconductor memory device may include a drive circuit for driving the memory cell array in addition to the memory cell array including the nonvolatile memory element 10. The drive circuit applies an electric pulse (electric signal) to the nonvolatile memory element 10 in the memory cell array. The resistance state of the resistance change element 109 of the nonvolatile memory element 10 is reversibly changed by an electric pulse for data writing. Further, the resistance state of the variable resistance element 109 of the nonvolatile memory element 10 is read by an electric pulse for reading data.
　第１の層間絶縁層１０１は、トランジスタ等が形成された半導体基板（図示せず）上に形成されている。第１の層間絶縁層１０１は、例えば、シリコン酸化物で構成される。 The first interlayer insulating layer 101 is formed on a semiconductor substrate (not shown) on which transistors and the like are formed. The first interlayer insulating layer 101 is made of, for example, silicon oxide.
　第１の配線１０２は、第１の層間絶縁層１０１上に形成されている。第１の配線１０２は、例えば、銅又はアルミニウム等で構成される。 The first wiring 102 is formed on the first interlayer insulating layer 101. The first wiring 102 is made of, for example, copper or aluminum.
　第２の層間絶縁層１０３は、第１の配線１０２上に形成されている。第２の層間絶縁層１０３は、例えば、膜厚１００～５００ｎｍのシリコン酸化物で構成される。 The second interlayer insulating layer 103 is formed on the first wiring 102. The second interlayer insulating layer 103 is made of, for example, silicon oxide having a thickness of 100 to 500 nm.
　第１のプラグ１０４は、第２の層間絶縁層１０３の内部に形成されている。第１のプラグ１０４は、第１の配線１０２と電気的に接続されている。第１のプラグ１０４は、例えば、タングステン又は銅等で構成される。第１のプラグ１０４の直径は、例えば、７０～２４０ｎｍで構成される。 The first plug 104 is formed inside the second interlayer insulating layer 103. The first plug 104 is electrically connected to the first wiring 102. The first plug 104 is made of, for example, tungsten or copper. The diameter of the first plug 104 is, for example, 70 to 240 nm.
　変質防止層１０５は、第１のプラグ１０４上面の全域を覆うように形成されている。なお、本明細書において、「上面」及び「下面」は、第１の配線１０２から積層体へ向かう方向を上とし、積層体から第１の配線１０２へ向かう方向を下として規定される。「第１のプラグ１０４の上面の全域」とは、第１のプラグ１０４を形成した直後に、上側に露出している面を意味する。 The alteration preventing layer 105 is formed so as to cover the entire upper surface of the first plug 104. Note that in this specification, the “upper surface” and the “lower surface” are defined such that the direction from the first wiring 102 to the stacked body is the top and the direction from the stacked body to the first wiring 102 is the bottom. “A whole area of the upper surface of the first plug 104” means a surface exposed to the upper side immediately after the first plug 104 is formed.
　変質防止層１０５は、導電性、酸素バリア性及び耐エッチング性を有する材料、例えば、タングステン窒化物等で構成される。変質防止層１０５の下面の水平断面積は、プラグ１０４の上面の水平断面積と等しく構成されている。ここで、水平断面積とは、抵抗変化素子１０９を上側、第１のプラグ１０４を下側に配置した状態で、鉛直方向（上下方向）に対して直交する水平面によって切断した断面の面積をいう。 The alteration preventing layer 105 is made of a material having conductivity, oxygen barrier properties and etching resistance, such as tungsten nitride. The horizontal sectional area of the lower surface of the alteration preventing layer 105 is configured to be equal to the horizontal sectional area of the upper surface of the plug 104. Here, the horizontal cross-sectional area means an area of a cross section cut by a horizontal plane perpendicular to the vertical direction (vertical direction) in a state where the resistance change element 109 is disposed on the upper side and the first plug 104 is disposed on the lower side. .
　なお、変質防止層１０５が酸素バリア性を有することにより、後述するように、抵抗変化素子１０９をエッチングによりドット形状に形成する際に、変質防止層１０５の上面がエッチングガスにより酸化されるのが抑制される。また、変質防止層１０５が耐エッチング性を有することにより、後述するように、抵抗変化素子１０９をエッチングによりドット形状に形成する際に、変質防止層１０５の上面がエッチングにより削られるのが抑制される。 Since the alteration preventing layer 105 has an oxygen barrier property, as will be described later, when the resistance change element 109 is formed into a dot shape by etching, the upper surface of the alteration preventing layer 105 is oxidized by the etching gas. It is suppressed. Further, since the alteration preventing layer 105 has etching resistance, as will be described later, when the resistance change element 109 is formed into a dot shape by etching, the upper surface of the alteration preventing layer 105 is suppressed from being etched by etching. The
　抵抗変化素子１０９は、第２の層間絶縁層１０３上に形成されるとともに、変質防止層１０５を介して第１のプラグ１０４と電気的に接続されている。この抵抗変化素子１０９は、ドット形状の積層体として形成されている。ここで、ドット形状とは、一辺が１００～４００ｎｍの矩形状の水平断面を有する積層体の形状をいう。 The resistance change element 109 is formed on the second interlayer insulating layer 103 and is electrically connected to the first plug 104 via the alteration preventing layer 105. The resistance change element 109 is formed as a dot-shaped laminate. Here, the dot shape refers to the shape of a laminate having a rectangular horizontal cross section with a side of 100 to 400 nm.
　本実施の形態では、図１に示すように、抵抗変化素子１０９の下面（即ち、第１電極１０６の下面）の水平断面積は、第１のプラグ１０４の上面を覆う変質防止層１０５の上面の水平断面積よりも小さく構成されている。なお、例えば、変質防止層１０５を含む第１のプラグ１０４の直径を２４０ｎｍとし、抵抗変化素子１０９の水平断面を一辺が２００ｎｍの矩形状としてもよい。これにより、変質防止層１０５の上面の一部は、抵抗変化素子１０９により覆われていない、即ち、抵抗変化素子１０９により覆われずに露出されている。 In the present embodiment, as shown in FIG. 1, the horizontal cross-sectional area of the lower surface of the resistance change element 109 (that is, the lower surface of the first electrode 106) is the upper surface of the alteration preventing layer 105 that covers the upper surface of the first plug 104. It is configured to be smaller than the horizontal cross sectional area. For example, the diameter of the first plug 104 including the alteration preventing layer 105 may be 240 nm, and the horizontal cross section of the resistance change element 109 may be a rectangular shape having a side of 200 nm. Thereby, a part of the upper surface of the alteration preventing layer 105 is not covered with the resistance change element 109, that is, is not covered with the resistance change element 109.
　また、本実施の形態では、抵抗変化素子１０９は、第１電極１０６、抵抗変化層１０７及び第２電極１０８を含む。第１電極１０６及び第２電極１０８は、相互に対向して配置されている。第１電極１０６は、変質防止層１０５を介して第１のプラグ１０４と電気的に接続されている。 In the present embodiment, the resistance change element 109 includes the first electrode 106, the resistance change layer 107, and the second electrode 108. The first electrode 106 and the second electrode 108 are disposed to face each other. The first electrode 106 is electrically connected to the first plug 104 through the alteration preventing layer 105.
　抵抗変化層１０７は、第１電極１０６と第２電極１０８との間に介在され、第１電極１０６と第２電極１０８との間に与えられる電気的信号に基づいて可逆的に抵抗値が変化する層である。抵抗変化層１０７は、例えば、第１電極１０６と第２電極１０８との間に与えられる電圧の極性に応じて高抵抗状態と低抵抗状態とを可逆的に遷移する層である。抵抗変化層１０７は、第１電極１０６に接続される第１の抵抗変化層１０７ａと、第２電極１０８に接続される第２の抵抗変化層１０７ｂとの少なくとも２層を積層することにより構成される。抵抗変化層１０７を構成する材料については、後述する。 The resistance change layer 107 is interposed between the first electrode 106 and the second electrode 108, and the resistance value reversibly changes based on an electrical signal applied between the first electrode 106 and the second electrode 108. It is a layer to do. The resistance change layer 107 is, for example, a layer that reversibly transitions between a high resistance state and a low resistance state according to the polarity of the voltage applied between the first electrode 106 and the second electrode 108. The resistance change layer 107 is configured by stacking at least two layers of a first resistance change layer 107 a connected to the first electrode 106 and a second resistance change layer 107 b connected to the second electrode 108. The The material constituting the resistance change layer 107 will be described later.
　第３の層間絶縁層１１０は、第２の層間絶縁層１０３上に形成されている。第３の層間絶縁層１１０の内部には、抵抗変化素子１０９が形成されている。 The third interlayer insulating layer 110 is formed on the second interlayer insulating layer 103. A variable resistance element 109 is formed inside the third interlayer insulating layer 110.
　第２のプラグ１１１は、第３の層間絶縁層１１０の内部に形成されている。第２のプラグ１１１は、抵抗変化素子１０９の第２電極１０８と電気的に接続されている。 The second plug 111 is formed inside the third interlayer insulating layer 110. The second plug 111 is electrically connected to the second electrode 108 of the variable resistance element 109.
　第２の配線１１２は、第３の層間絶縁層１１０上且つ第２のプラグ１１１の上面に形成されている。第２の配線１１２は、第２のプラグ１１１と電気的に接続されている。 The second wiring 112 is formed on the third interlayer insulating layer 110 and on the upper surface of the second plug 111. The second wiring 112 is electrically connected to the second plug 111.
　次に、抵抗変化素子１０９の抵抗変化層１０７を構成する材料について説明する。第１の抵抗変化層１０７ａは、酸素不足型の第１の金属酸化物で構成され、第２の抵抗変化層１０７ｂは、第１の金属酸化物よりも酸素不足度が小さい第２の金属酸化物で構成されている。抵抗変化素子１０９の第２の抵抗変化層１０７ｂ中には、電気パルスの印加に応じて酸素不足度が可逆的に変化する微小な局所領域が形成されている。局所領域は、酸素欠陥サイトから構成されるフィラメントを含むと考えられる。 Next, the material constituting the variable resistance layer 107 of the variable resistance element 109 will be described. The first resistance change layer 107a is composed of an oxygen-deficient first metal oxide, and the second resistance change layer 107b is a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide. It consists of things. In the second resistance change layer 107b of the resistance change element 109, a minute local region in which the degree of oxygen deficiency reversibly changes according to the application of the electric pulse is formed. The local region is considered to include a filament composed of oxygen defect sites.
　抵抗変化層１０７は、例えば、タンタル酸化物等の遷移金属酸化物で構成することができる。この場合には、例えば、第１の抵抗変化層１０７ａは酸素不足型の遷移金属酸化物で構成され、第２の抵抗変化層１０７ｂは第１の抵抗変化層１０７ａよりも酸素不足度が小さい酸素不足型の遷移金属酸化物で構成される。これにより、抵抗変化する極性が常に安定し、不揮発性記憶素子１０として安定な動作特性を得ることができる。ここで、酸素不足型の遷移金属酸化物とは、化学量論的組成を有する遷移金属酸化物と比較して、酸素の含有量（原子比：総原子数に占める酸素原子数の割合）が少ない酸化物をいう。 The resistance change layer 107 can be made of a transition metal oxide such as tantalum oxide, for example. In this case, for example, the first resistance change layer 107a is made of an oxygen-deficient transition metal oxide, and the second resistance change layer 107b is oxygen having a lower oxygen deficiency than the first resistance change layer 107a. It is composed of a deficient transition metal oxide. As a result, the polarity of the resistance change is always stable, and stable operating characteristics can be obtained as the nonvolatile memory element 10. Here, the oxygen-deficient transition metal oxide has an oxygen content (atomic ratio: the ratio of the number of oxygen atoms to the total number of atoms) compared to a transition metal oxide having a stoichiometric composition. It refers to less oxide.
　なお、「酸素不足度」とは、金属酸化物において、その化学量論的組成（複数の化学量論的組成が存在する場合は、その中で最も抵抗値が高い化学量論的組成）の酸化物を構成する酸素の量に対し、不足している酸素の割合をいう。化学量論的組成の金属酸化物は、他の組成の金属酸化物と比べて、より安定であり且つより高い抵抗値を有している。 “Oxygen deficiency” means the stoichiometric composition of metal oxide (if there are multiple stoichiometric compositions, the stoichiometric composition having the highest resistance value among them). This refers to the proportion of oxygen that is deficient with respect to the amount of oxygen that forms the oxide. Stoichiometric metal oxides are more stable and have higher resistance values than other metal oxides.
　例えば、金属がタンタル（Ｔａ）の場合、上述の定義による化学量論的組成の酸化物はＴａ２Ｏ５であるので、ＴａＯ２．５と表現できる。ＴａＯ２．５の酸素不足度は０％であり、ＴａＯ１．５の酸素不足度は、酸素不足度＝（２．５－１．５）／２．５＝４０％となる。また、酸素過剰の金属酸化物は、酸素不足度が負の値となる。なお、本明細書中では、特に断りのない限り、酸素不足度は正の値、０、負の値も含むものとして説明する。酸素不足度の小さい酸化物は化学量論的組成の酸化物により近いため抵抗値が高く、酸素不足度の大きい酸化物は酸化物を構成する金属により近いため抵抗値が低い。 For example, when the metal is tantalum (Ta), the oxide having the stoichiometric composition according to the above definition is Ta 2 O 5 , and can be expressed as TaO 2.5 . The oxygen deficiency of TaO 2.5 is 0%, and the oxygen deficiency of TaO 1.5 is oxygen deficiency = (2.5−1.5) /2.5=40%. In addition, the oxygen excess metal oxide has a negative oxygen deficiency. In the present specification, unless otherwise specified, the oxygen deficiency is described as including a positive value, 0, and a negative value. An oxide with a low degree of oxygen deficiency has a high resistance value because it is closer to a stoichiometric oxide, and an oxide with a high degree of oxygen deficiency has a low resistance value because it is closer to the metal constituting the oxide.
　なお、「酸素含有率」とは、総原子数に占める酸素原子の比率である。例えば、Ｔａ２Ｏ５の酸素含有率は、総原子数に占める酸素原子の比率（Ｏ／（Ｔａ＋Ｏ））であり、７１．４ａｔｍ％となる。したがって、酸素不足型のタンタル酸化物は、酸素含有率は０より大きく、７１．４ａｔｍ％より小さいことになる。例えば、第１の金属酸化物層を構成する金属と、第２の金属酸化物層を構成する金属とが同種である場合、酸素含有率は酸素不足度と対応関係にある。すなわち、第２の金属酸化物の酸素含有率が第１の金属酸化物の酸素含有率よりも大きいとき、第２の金属酸化物の酸素不足度は第１の金属酸化物の酸素不足度より小さい。 The “oxygen content” is the ratio of oxygen atoms to the total number of atoms. For example, the oxygen content of Ta 2 O 5 is the ratio of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%. For example, when the metal constituting the first metal oxide layer and the metal constituting the second metal oxide layer are of the same type, the oxygen content has a corresponding relationship with the degree of oxygen deficiency. That is, when the oxygen content of the second metal oxide is greater than the oxygen content of the first metal oxide, the oxygen deficiency of the second metal oxide is greater than the oxygen deficiency of the first metal oxide. small.
　抵抗変化層１０７を構成する金属は、タンタル以外の金属を用いてもよい。抵抗変化層１０７を構成する金属としては、遷移金属又はアルミニウム（Ａｌ）を用いることができる。すなわち、抵抗変化層１０７は、遷移金属酸化物又はアルミニウム酸化物で構成することができる。遷移金属としては、タンタル（Ｔａ）、チタン（Ｔｉ）、ハフニウム（Ｈｆ）、ジルコニウム（Ｚｒ）、ニオブ（Ｎｂ）、タングステン（Ｗ）、ニッケル（Ｎｉ）等を用いることができる。遷移金属は複数の酸化状態をとることができるため、異なる抵抗状態を酸化還元反応により実現することが可能である。 The metal constituting the resistance change layer 107 may be a metal other than tantalum. As a metal constituting the resistance change layer 107, a transition metal or aluminum (Al) can be used. That is, the resistance change layer 107 can be made of a transition metal oxide or aluminum oxide. As the transition metal, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), nickel (Ni), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.
　例えば、ハフニウム酸化物を用いる場合において、第１の金属酸化物の組成をＨｆＯｘとした場合にｘが０．９以上１．６以下であり、且つ、第２の金属酸化物の組成をＨｆＯｙとした場合にｙがｘの値よりも大である場合に、抵抗変化層１０７の抵抗値を安定して高速に変化させることができる。この場合、第２の金属酸化物の膜厚は、３～４ｎｍとしてもよい。 For example, in the case of using hafnium oxide, when the composition of the first metal oxide is HfO x , x is 0.9 or more and 1.6 or less, and the composition of the second metal oxide is HfO x. When y is larger than the value x, the resistance value of the resistance change layer 107 can be stably changed at high speed. In this case, the thickness of the second metal oxide may be 3 to 4 nm.
　また、ジルコニウム酸化物を用いる場合において、第１の金属酸化物の組成をＺｒＯｘとした場合にｘが０．９以上１．４以下であり、且つ、第２の金属酸化物の組成をＺｒＯｙとした場合にｙがｘの値よりも大である場合に、抵抗変化層１０７の抵抗値を安定して高速に変化させることができる。この場合、第２の金属酸化物の膜厚は、１～５ｎｍとしてもよい。 Further, in the case of using zirconium oxide, when the composition of the first metal oxide is ZrO x , x is 0.9 or more and 1.4 or less, and the composition of the second metal oxide is ZrO x. When y is larger than the value x, the resistance value of the resistance change layer 107 can be stably changed at high speed. In this case, the thickness of the second metal oxide may be 1 to 5 nm.
　例えば、第１の抵抗変化層１０７ａが酸素不足型タンタル酸化物、酸素不足型ハフニウム酸化物又は酸素不足型ジルコニウム酸化物で構成されている場合には、第１の抵抗変化層１０７ａは、タンタル、ハフニウム又はジルコニウムをそれぞれターゲットに用いてアルゴンガス及び酸素ガス中でスパッタリングする、いわゆる反応性スパッタリング法によって形成することができる。第１の抵抗変化層１０７ａの酸素不足度は、反応性スパッタリング中のアルゴンガスに対する酸素ガスの流量比を変えることにより容易に調整することができる。なお、この処理は、半導体基板を特に加熱することなく室温で行うことができる。 For example, when the first resistance change layer 107a is composed of oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, or oxygen-deficient zirconium oxide, the first resistance change layer 107a includes tantalum, It can be formed by a so-called reactive sputtering method in which hafnium or zirconium is used as a target and sputtering is performed in argon gas and oxygen gas. The degree of oxygen deficiency of the first resistance change layer 107a can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. This treatment can be performed at room temperature without particularly heating the semiconductor substrate.
　第２の抵抗変化層１０７ｂは、反応性スパッタリング法で形成された第１の抵抗変化層１０７ａの表面をアルゴンガスと酸素ガスとのプラズマに暴露することにより形成することができる。 The second resistance change layer 107b can be formed by exposing the surface of the first resistance change layer 107a formed by a reactive sputtering method to plasma of argon gas and oxygen gas.
　抵抗変化層１０７を例えば酸素不足型タンタル酸化物、酸素不足型ハフニウム酸化物又は酸素不足型ジルコニウム酸化物で構成した場合には、動作の高速性に加えて、可逆的に安定した書き換え特性及び良好な抵抗値のリテンション特性を有する不揮発性記憶素子１０を実現することができる。特に、抵抗変化層１０７を酸素不足型タンタル酸化物で構成した場合には、通常のＳｉ半導体プロセスに対して親和性の高い製造プロセスで不揮発性記憶素子１０を製造することができる。 When the resistance change layer 107 is made of, for example, oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, or oxygen-deficient zirconium oxide, in addition to high-speed operation, reversibly stable rewriting characteristics and good Thus, the nonvolatile memory element 10 having a retention characteristic with a satisfactory resistance value can be realized. In particular, when the resistance change layer 107 is made of an oxygen-deficient tantalum oxide, the nonvolatile memory element 10 can be manufactured by a manufacturing process having a high affinity for a normal Si semiconductor process.
　なお、第１の金属酸化物を構成する第１の金属と、第２の金属酸化物を構成する第２の金属とは、異なる金属を用いてもよい。この場合、第２の金属酸化物は、第１の金属酸化物よりも酸素不足度が小さい、つまり抵抗が高くてもよい。このような構成とすることにより、抵抗変化時に第１電極１０６と第２電極１０８との間に印加された電圧は、第２の金属酸化物に、より多くの電圧が分配され、第２の金属酸化物中で発生する酸化還元反応をより起こしやすくすることができる。 In addition, you may use a different metal for the 1st metal which comprises a 1st metal oxide, and the 2nd metal which comprises a 2nd metal oxide. In this case, the second metal oxide may have a lower degree of oxygen deficiency than the first metal oxide, that is, may have a higher resistance. With such a configuration, the voltage applied between the first electrode 106 and the second electrode 108 at the time of resistance change is more distributed to the second metal oxide, and the second The oxidation-reduction reaction generated in the metal oxide can be more easily caused.
　また、第１の抵抗変化層１０７ａとなる第１の金属酸化物を構成する第１の金属と、第２の抵抗変化層１０７ｂとなる第２の金属酸化物を構成する第２の金属と、を互いに異なる材料で構成する場合、第２の金属の標準電極電位は、第１の金属の標準電極電位より低くてもよい。標準電極電位は、その値が高いほど酸化しにくい特性を表す。これにより、標準電極電位が相対的に低い第２の金属酸化物において、酸化還元反応が起こりやすくなる。なお、抵抗変化現象は、抵抗が高い第２の金属酸化物中に形成された微小な局所領域中で酸化還元反応が起こってフィラメント（導電パス）が変化することにより、その抵抗値（酸素不足度）が変化すると考えられる。 Also, a first metal constituting the first metal oxide to be the first resistance change layer 107a, a second metal constituting the second metal oxide to be the second resistance change layer 107b, Are made of different materials, the standard electrode potential of the second metal may be lower than the standard electrode potential of the first metal. The standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize. Thereby, an oxidation-reduction reaction easily occurs in the second metal oxide having a relatively low standard electrode potential. Note that the resistance change phenomenon is caused by a change in the filament (conducting path) caused by an oxidation-reduction reaction in a minute local region formed in the second metal oxide having a high resistance. Degree) is considered to change.
　例えば、第１の金属酸化物に酸素不足型のタンタル酸化物（ＴａＯｘ）を用い、第２の金属酸化物にチタン酸化物（ＴｉＯ２）を用いることにより、安定した抵抗変化動作が得られる。チタン（標準電極電位＝－１．６３ｅＶ）はタンタル（標準電極電位＝－０．６ｅＶ）より標準電極電位が低い材料である。このように、第２の金属酸化物に第１の金属酸化物より標準電極電位が低い金属の酸化物を用いることにより、第２の金属酸化物中でより酸化還元反応が発生しやすくなる。その他の組み合わせとして、高抵抗層となる第２の金属酸化物にアルミニウム酸化物（Ａｌ２Ｏ３）を用いることができる。例えば、第１の金属酸化物に酸素不足型のタンタル酸化物（ＴａＯｘ）を用い、第２の金属酸化物にアルミニウム酸化物（Ａｌ２Ｏ３）を用いてもよい。 For example, by using oxygen-deficient tantalum oxide (TaO x ) for the first metal oxide and titanium oxide (TiO 2 ) for the second metal oxide, stable resistance change operation can be obtained. . Titanium (standard electrode potential = −1.63 eV) is a material having a lower standard electrode potential than tantalum (standard electrode potential = −0.6 eV). As described above, by using a metal oxide whose standard electrode potential is lower than that of the first metal oxide as the second metal oxide, a redox reaction is more likely to occur in the second metal oxide. As another combination, aluminum oxide (Al 2 O 3 ) can be used for the second metal oxide to be the high resistance layer. For example, oxygen-deficient tantalum oxide (TaO x ) may be used for the first metal oxide, and aluminum oxide (Al 2 O 3 ) may be used for the second metal oxide.
　積層構造の抵抗変化層１０７における抵抗変化現象は、いずれも抵抗が高い第２の金属酸化物中に形成された微小な局所領域中で酸化還元反応が起こって、局所領域中のフィラメント（導電パス）が変化することにより、その抵抗値が変化すると考えられる。つまり、第２の金属酸化物に接続する第２電極１０８に、第１電極１０６を基準にして正の電圧を印加したとき、抵抗変化層１０７中の酸素イオンが第２の金属酸化物側に引き寄せられる。これによって、第２の金属酸化物中に形成された微小な局所領域中で酸化反応が発生し、酸素不足度が減少する。その結果、局所領域中のフィラメントが繋がりにくくなり、抵抗値が増大すると考えられる。 The resistance change phenomenon in the resistance change layer 107 having the laminated structure is caused by a redox reaction in a minute local region formed in the second metal oxide having a high resistance, and a filament (conducting path) in the local region. ) Changes, the resistance value is considered to change. That is, when a positive voltage is applied to the second electrode 108 connected to the second metal oxide with reference to the first electrode 106, oxygen ions in the resistance change layer 107 are moved to the second metal oxide side. Gravitate. As a result, an oxidation reaction occurs in a small local region formed in the second metal oxide, and the degree of oxygen deficiency is reduced. As a result, it is considered that the filaments in the local region are not easily connected and the resistance value is increased.
　逆に、第２の金属酸化物に接続する第２電極１０８に、第１電極１０６を基準にして負の電圧を印加したとき、第２の金属酸化物中の酸素イオンが第１の金属酸化物側に押しやられる。これによって、第２の金属酸化物中に形成された微小な局所領域中で還元反応が発生し、酸素不足度が増加する。その結果、局所領域中のフィラメントが繋がりやすくなり、抵抗値が減少すると考えられる。 Conversely, when a negative voltage is applied to the second electrode 108 connected to the second metal oxide with respect to the first electrode 106, oxygen ions in the second metal oxide are converted into the first metal oxide. Pushed to the object side. As a result, a reduction reaction occurs in a minute local region formed in the second metal oxide, and the degree of oxygen deficiency increases. As a result, it is considered that the filaments in the local region are easily connected and the resistance value decreases.
　酸素不足度がより小さい第２の金属酸化物に接続されている第２電極１０８は、例えば、白金（Ｐｔ）、イリジウム（Ｉｒ）、パラジウム（Ｐｄ）等、第２の金属酸化物を構成する金属及び第１電極１０６を構成する材料と比べて標準電極電位がより高い材料で構成される。また、酸素不足度がより高い第１の金属酸化物に接続されている第１電極１０６は、例えば、タングステン（Ｗ）、ニッケル（Ｎｉ）、タンタル（Ｔａ）、チタン（Ｔｉ）、アルミニウム（Ａｌ）、窒化タンタル（ＴａＮ）、窒化チタン（ＴｉＮ）等、第１の金属酸化物を構成する金属と比べて標準電極電位がより低い材料で構成してもよい。標準電極電位は、その値が高いほど酸化しにくい特性を表す。 The second electrode 108 connected to the second metal oxide having a lower oxygen deficiency constitutes the second metal oxide such as platinum (Pt), iridium (Ir), palladium (Pd), etc. The metal and the material constituting the first electrode 106 are made of a material having a higher standard electrode potential. The first electrode 106 connected to the first metal oxide having a higher degree of oxygen deficiency is, for example, tungsten (W), nickel (Ni), tantalum (Ta), titanium (Ti), aluminum (Al ), Tantalum nitride (TaN), titanium nitride (TiN), or the like, a material having a lower standard electrode potential than the metal constituting the first metal oxide may be used. The standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize.
　すなわち、第２の電極１０８の標準電極電位Ｖ２、第２の金属酸化物を構成する金属の標準電極電位Ｖｒ２、第１の金属酸化物を構成する金属の標準電極電位Ｖｒ１、第１の電極１０６の標準電極電位Ｖ１との間には、Ｖｒ２＜Ｖ２、且つＶ１＜Ｖ２なる関係を満足してもよい。さらには、Ｖ２＞Ｖｒ２で、Ｖｒ１≧Ｖ１の関係を満足してもよい。 That is, the standard electrode potential V2 of the second electrode 108, the standard electrode potential Vr2 of the metal constituting the second metal oxide, the standard electrode potential Vr1 of the metal constituting the first metal oxide, the first electrode 106 The relationship of V r2 <V 2 and V 1 <V 2 may be satisfied with the standard electrode potential V1. Furthermore, V2> Vr2 and Vr1 ≧ V1 may be satisfied.
　上記の構成とすることにより、第２電極１０８と第２の金属酸化物の界面近傍の第２の金属酸化物中において、選択的に酸化還元反応が発生し、安定した抵抗変化現象が得られる。 With the above configuration, a redox reaction occurs selectively in the second metal oxide in the vicinity of the interface between the second electrode 108 and the second metal oxide, and a stable resistance change phenomenon is obtained. .
　さらに、抵抗変化が安定して発現する状態に遷移させるためには、抵抗変化素子１０９に最初に電圧を印加して、酸素不足度の低い第２の抵抗変化層１０７ｂの一部を局所的に短絡させる初期ブレイクが行われる。このときに重要なことは、抵抗変化素子１０９以外のトランジスタ及び寄生抵抗成分に不要な電圧が印加されることなく、抵抗変化素子１０９に十分な電圧が印加されることである。 Furthermore, in order to make a transition to a state in which the resistance change stably appears, a voltage is first applied to the resistance change element 109, and a part of the second resistance change layer 107b having a low oxygen deficiency is locally applied. An initial break to short circuit is performed. What is important at this time is that a sufficient voltage is applied to the resistance change element 109 without applying an unnecessary voltage to transistors other than the resistance change element 109 and parasitic resistance components.
　以上のように構成された不揮発性記憶素子１０を駆動する際には、外部の電源（図示せず）及び駆動回路によって、所定の条件を満たす電圧を第１電極１０６と第２電極１０８との間に印加する。 When driving the nonvolatile memory element 10 configured as described above, a voltage satisfying a predetermined condition is applied between the first electrode 106 and the second electrode 108 by an external power source (not shown) and a drive circuit. Apply between.
　次に、本実施の形態に係る不揮発性記憶素子１０の製造方法について説明する。図２Ａ～図５Ｂは、本実施の形態に係る不揮発性記憶素子１０の製造方法を示す断面図である。なお、以下で説明するプロセス、材料及び膜厚等はあくまでも例示であり、本発明に係る不揮発性記憶素子１０の製造方法は、本実施の形態に限定されない。また、必要に応じて、各工程の順序等を変更することができ、或いは、他の公知の工程を追加することができる。 Next, a method for manufacturing the nonvolatile memory element 10 according to this embodiment will be described. 2A to 5B are cross-sectional views illustrating a method for manufacturing the nonvolatile memory element 10 according to the present embodiment. In addition, the process, material, film thickness, etc. which are demonstrated below are an illustration to the last, and the manufacturing method of the non-volatile memory element 10 which concerns on this invention is not limited to this Embodiment. Moreover, the order of each process etc. can be changed as needed, or another well-known process can be added.
　まず、図２Ａに示すように、トランジスタ等が予め形成された半導体基板（図示せず）上に、プラズマＣＶＤ等を用いることにより、シリコン酸化物で構成される第１の層間絶縁層１０１を形成する。その後、第１の層間絶縁層１０１上に第１の配線１０２を形成する。第１の配線１０２の材料としてアルミニウム（Ａｌ）を用いる場合には、一般的な半導体プロセス、例えばスパッタリングによる成膜、フォトリソグラフィー及びドライエッチングによる形状加工により、第１の配線１０２を形成することができる。また、第１の配線１０２の材料として銅（Ｃｕ）を用いる場合には、ダマシン法を用いることにより、第１の層間絶縁層１０１中に第１の配線１０２を埋め込み形成することができる。 First, as shown in FIG. 2A, a first interlayer insulating layer 101 made of silicon oxide is formed on a semiconductor substrate (not shown) on which transistors and the like are formed in advance by using plasma CVD or the like. To do. Thereafter, the first wiring 102 is formed over the first interlayer insulating layer 101. When aluminum (Al) is used as the material of the first wiring 102, the first wiring 102 can be formed by a general semiconductor process, for example, film formation by sputtering, shape processing by photolithography, and dry etching. it can. When copper (Cu) is used as the material for the first wiring 102, the first wiring 102 can be embedded in the first interlayer insulating layer 101 by using a damascene method.
　次に、図２Ｂに示すように、第１の配線１０２上に、第１の配線１０２と電気的に接続される第１のプラグ１０４を形成する。この工程では、まず、第１の配線１０２上に第２の層間絶縁層１０３をさらに堆積させる。なお、必要に応じて、ＣＭＰにより第２の層間絶縁層１０３の上面に対して段差緩和を行う。その後、フォトリソグラフィー及びドライエッチングにより、第１の配線１０２上の所定の位置に対応する第２の層間絶縁層１０３の部位に、第１のプラグ１０４を埋め込み形成するためのコンタクトホール１１３を形成する。その後、形成されたコンタクトホール１１３を含む第２の層間絶縁層１０３上に、チタン窒化物（例えば、膜厚５～４０ｎｍ）及びチタン（例えば、膜厚５～４０ｎｍ）で構成されるバリアメタル層をスパッタ法等によって堆積させる。さらに、ＣＶＤ等により導電材料のタングステン（例えば、膜厚５０～３００ｎｍ）を堆積させる。このようにコンタクトホール１１３をバリアメタル層とタングステンとで満たすことにより、第１のプラグ１０４がコンタクトホール１１３に形成される。その後、ＣＭＰによって、第１のプラグ１０４の上面の余分なタングステン及びバリアメタル層を除去するとともに、第２の層間絶縁層１０３の上面と第１のプラグ１０４の上面とを平坦状に形成する。 Next, as shown in FIG. 2B, a first plug 104 that is electrically connected to the first wiring 102 is formed on the first wiring 102. In this step, first, a second interlayer insulating layer 103 is further deposited on the first wiring 102. Note that, if necessary, step relaxation is performed on the upper surface of the second interlayer insulating layer 103 by CMP. Thereafter, a contact hole 113 for embedding the first plug 104 is formed in a portion of the second interlayer insulating layer 103 corresponding to a predetermined position on the first wiring 102 by photolithography and dry etching. . Thereafter, a barrier metal layer composed of titanium nitride (for example, a film thickness of 5 to 40 nm) and titanium (for example, a film thickness of 5 to 40 nm) is formed on the second interlayer insulating layer 103 including the formed contact hole 113. Is deposited by sputtering or the like. Further, tungsten (for example, a film thickness of 50 to 300 nm) as a conductive material is deposited by CVD or the like. Thus, the first plug 104 is formed in the contact hole 113 by filling the contact hole 113 with the barrier metal layer and tungsten. Thereafter, the excess tungsten and barrier metal layer on the upper surface of the first plug 104 are removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104 are formed flat.
　次に、図２Ｃに示すように、ＣＭＰによって第１のプラグ１０４の上面をオーバーポリッシュすることにより、第１のプラグ１０４の上側に深さ１０～５０ｎｍ程度のリセス（凹部）１１４を形成する。なお、リセス１１４を形成する別の方法として、ドライエッチングによるエッチバックを行うこともできる。 Next, as shown in FIG. 2C, the upper surface of the first plug 104 is overpolished by CMP to form a recess (concave portion) 114 having a depth of about 10 to 50 nm on the upper side of the first plug 104. As another method of forming the recess 114, etch back by dry etching can be performed.
　その後、図３Ａに示すように、リセス１１４を含む第２の層間絶縁層１０３上に、例えば、タングステン窒化物で構成されるキャップメタル膜１０５’をＣＶＤ等により堆積させる。リセス１１４をタングステン窒化物で充填することにより、リセス１１４に変質防止層１０５が形成される。 Thereafter, as shown in FIG. 3A, a cap metal film 105 ′ made of, for example, tungsten nitride is deposited on the second interlayer insulating layer 103 including the recess 114 by CVD or the like. By filling the recess 114 with tungsten nitride, the alteration preventing layer 105 is formed in the recess 114.
　その後、図３Ｂに示すように、ＣＭＰによって、第２の層間絶縁層１０３の上面の余分なキャップメタル膜１０５’を除去するとともに、第２の層間絶縁層１０３の上面と変質防止層１０５の上面とを平坦状に形成する。このように第１のプラグ１０４及び変質防止層１０５はともに、コンタクトホール１１３に埋め込まれているので、不揮発性記憶素子１０が間隔を置いて複数配置されている際に、隣接する第１のプラグ１０４がショートするのを確実に防止することができる。 Thereafter, as shown in FIG. 3B, the excess cap metal film 105 ′ on the upper surface of the second interlayer insulating layer 103 is removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the alteration preventing layer 105 are removed. Are formed flat. As described above, since the first plug 104 and the alteration preventing layer 105 are both embedded in the contact hole 113, when a plurality of the nonvolatile memory elements 10 are arranged at intervals, the adjacent first plugs 104 are arranged. It is possible to reliably prevent the 104 from being short-circuited.
　なお、タングステンで構成される第１のプラグ１０４の上面のみを覆う変質防止層１０５としては、タングステン窒化物を用いることができる。第１のプラグ１０４の上面にタングステン窒化物層を形成する別の方法として、タングステンで構成される第１のプラグ１０４を形成した後に、アルゴンガスと窒素ガスとのプラズマに第１のプラグ１０４の表面を暴露する方法がある。これにより、自己形成的に、第１のプラグ１０４の上面のみを覆い且つタングステン窒化物で構成される変質防止層１０５を形成することができる。 Note that tungsten nitride can be used as the alteration preventing layer 105 covering only the upper surface of the first plug 104 made of tungsten. As another method for forming a tungsten nitride layer on the upper surface of the first plug 104, the first plug 104 made of tungsten is formed, and then the first plug 104 is subjected to plasma of argon gas and nitrogen gas. There are ways to expose the surface. Thereby, the alteration preventing layer 105 that covers only the upper surface of the first plug 104 and is made of tungsten nitride can be formed in a self-forming manner.
　次に、図４Ａ及び図４Ｂに示すように、変質防止層１０５を介して第１のプラグ１０４上に、積層体としての抵抗変化素子１０９を形成する。 Next, as shown in FIGS. 4A and 4B, a resistance change element 109 as a stacked body is formed on the first plug 104 via the alteration preventing layer 105.
　まず、図４Ａに示すように、変質防止層１０５を含む第２の層間絶縁層１０３上に、タンタル窒化物で構成される第１電極層１０６’（例えば、膜厚３０ｎｍ）、酸素不足型のタンタル酸化物で構成される抵抗変化薄膜１０７’（例えば、膜厚５０ｎｍ）及びイリジウムで構成される第２電極層１０８’（例えば、膜厚５０ｎｍ）をこの順に水平に積層させるように堆積させる。抵抗変化薄膜１０７’は、第１の抵抗変化薄膜１０７ａ’及び第２の抵抗変化薄膜１０７ｂ’がこの順に積層されることにより構成される。 First, as shown in FIG. 4A, on the second interlayer insulating layer 103 including the alteration preventing layer 105, a first electrode layer 106 ′ (for example, a film thickness of 30 nm) made of tantalum nitride, an oxygen-deficient type is formed. A resistance change thin film 107 ′ (for example, a film thickness of 50 nm) made of tantalum oxide and a second electrode layer 108 ′ (for example, a film thickness of 50 nm) made of iridium are deposited so as to be stacked horizontally in this order. The resistance change thin film 107 ′ is configured by laminating a first resistance change thin film 107 a ′ and a second resistance change thin film 107 b ′ in this order.
　第１の抵抗変化薄膜１０７ａ’は、タンタルをターゲットとしてアルゴン及び酸素ガス雰囲気中でスパッタリングする、いわゆる反応性スパッタ法を用いることにより形成される。ここで、酸素の流量を調整することにより、成膜チャンバー内の酸素濃度を４４．６～６５．５ａｔｍ％に制御する。これにより、第１の抵抗変化薄膜１０７ａ’の抵抗率を０．５～２０ｍΩ・ｃｍに調整することができる。例えば、第１の抵抗変化薄膜１０７ａ’の酸素濃度を６０ａｔｍ％とすることにより、約２ｍΩ・ｃｍの抵抗率を有する第１の抵抗変化薄膜１０７ａ’を形成することができる。また、第１電極層１０６’及び第２電極層１０８’は、上述と同様に反応性スパッタ法により形成される。 The first resistance change thin film 107a 'is formed by using a so-called reactive sputtering method in which sputtering is performed in an argon and oxygen gas atmosphere using tantalum as a target. Here, the oxygen concentration in the deposition chamber is controlled to 44.6 to 65.5 atm% by adjusting the flow rate of oxygen. Accordingly, the resistivity of the first resistance change thin film 107a 'can be adjusted to 0.5 to 20 mΩ · cm. For example, by setting the oxygen concentration of the first variable resistance thin film 107a 'to 60 atm%, the first variable resistance thin film 107a' having a resistivity of about 2 mΩ · cm can be formed. Further, the first electrode layer 106 'and the second electrode layer 108' are formed by the reactive sputtering method as described above.
　なお、第１の抵抗変化薄膜１０７ａ’に対して表面に酸化処理を行うことにより、第１の抵抗変化薄膜１０７ａ’の最表面層に、第２の抵抗変化薄膜１０７ｂ’を形成してもよい。また、第２の抵抗変化薄膜１０７ｂ’は、第１の抵抗変化薄膜１０７ａ’に比べて酸素不足度がより小さい、又は酸素が不足していない化学量論的組成のＴａ２Ｏ５層を膜厚２～１２ｎｍの範囲で形成してもよい。 Note that the second resistance change thin film 107b ′ may be formed on the outermost surface layer of the first resistance change thin film 107a ′ by oxidizing the surface of the first resistance change thin film 107a ′. . Further, the second resistance change thin film 107b ′ is formed of a Ta 2 O 5 layer having a stoichiometric composition that has a lower degree of oxygen deficiency than that of the first resistance change thin film 107a ′ or is not deficient in oxygen. The thickness may be in the range of 2 to 12 nm.
　次に、図４Ｂに示すように、フォトリソグラフィー及びドライエッチングによって、水平に積層した第１電極層１０６’、抵抗変化薄膜１０７’及び第２電極層１０８’を加工することにより、例えば一辺が２００ｎｍのドット形状の抵抗変化素子１０９を形成する。 Next, as shown in FIG. 4B, by horizontally processing the first electrode layer 106 ′, the resistance change thin film 107 ′, and the second electrode layer 108 ′ that are stacked horizontally by photolithography and dry etching, for example, each side is 200 nm. The dot-shaped resistance change element 109 is formed.
　本実施の形態では、図４Ｂに示すように、第１のプラグ１０４の上面が変質防止層１０５によって覆われているので、エッチングにより抵抗変化素子１０９をドット形状に形成する際に、第１のプラグ１０４の上面がドライエッチングに用いる塩素、フッ素及び酸素等を含むエッチングガスに曝されることがない。これにより、第１のプラグ１０４の上面が酸化又は変質するのを防止することができ、電気的特性が良好な第１のプラグを形成することができる。 In the present embodiment, as shown in FIG. 4B, since the upper surface of the first plug 104 is covered with the alteration preventing layer 105, when the resistance change element 109 is formed into a dot shape by etching, The upper surface of the plug 104 is not exposed to an etching gas containing chlorine, fluorine, oxygen, or the like used for dry etching. Thus, the top surface of the first plug 104 can be prevented from being oxidized or denatured, and a first plug with good electrical characteristics can be formed.
　なお、エッチングにより抵抗変化素子１０９をドット形状に形成する際に、最上層の第２電極１０８がエッチングにより削られるのを防止するために、第２電極層１０８ａ’上に導電性のハードマスク（図示せず）をスパッタ法等により堆積してもよい。ハードマスクの材料として、例えば、タンタル窒化物、チタン窒化物及びチタン－アルミニウム窒化物のいずれかが用いられる。抵抗変化素子１０９をドット形状に形成した後には、第２電極１０８上に残存するハードマスクをエッチング等により除去すればよい。 When the resistance change element 109 is formed in a dot shape by etching, a conductive hard mask (on the second electrode layer 108a ′ is used to prevent the uppermost second electrode 108 from being etched away. (Not shown) may be deposited by sputtering or the like. As the material of the hard mask, for example, any one of tantalum nitride, titanium nitride, and titanium-aluminum nitride is used. After the variable resistance element 109 is formed in a dot shape, the hard mask remaining on the second electrode 108 may be removed by etching or the like.
　また、抵抗変化素子１０９をドット形状に加工した後、酸素雰囲気中でアニールすることにより（温度：３００～４５０℃）、第１の抵抗変化層１０７ａの側壁面を酸化させて絶縁化してもよい。ここで、第２の抵抗変化層１０７ｂ’が最初から絶縁層に近い場合は、第２の抵抗変化層１０７ｂの側壁面はほとんど酸化されない。 Further, the resistance change element 109 may be processed into a dot shape, and then annealed in an oxygen atmosphere (temperature: 300 to 450 ° C.) to oxidize the side wall surface of the first resistance change layer 107a and insulate it. . Here, when the second variable resistance layer 107b 'is close to the insulating layer from the beginning, the side wall surface of the second variable resistance layer 107b is hardly oxidized.
　このように抵抗変化素子１０９の側壁面を酸化させて絶縁化することにより、アクティブ面積が縮小されるとともにリーク電流が低減され、初期ブレイク電圧の低電圧化及び印加時間の短時間化を実現することができる。本実施の形態では、第１のプラグ１０４の上面が変質防止層１０５によって覆われているので、抵抗変化素子１０９の側壁面に対して酸化処理を施した際に、第１のプラグ１０４が酸化するのを防止することができる。これにより、抵抗変化素子１０９以外の寄生抵抗成分が小さく、安定的に動作する不揮発性記憶素子１０を実現することができる。 Thus, by oxidizing the side wall surface of the resistance change element 109 and insulating it, the active area is reduced and the leakage current is reduced, so that the initial break voltage is lowered and the application time is shortened. be able to. In the present embodiment, since the upper surface of the first plug 104 is covered with the alteration preventing layer 105, the oxidation of the first plug 104 is performed when the side wall surface of the variable resistance element 109 is oxidized. Can be prevented. As a result, the nonvolatile memory element 10 that has a small parasitic resistance component other than the resistance change element 109 and operates stably can be realized.
　その後、図５Ａに示すように、抵抗変化素子１０９を含む第２の層間絶縁層１０３上に、第２のプラグ１１１を埋め込み形成するための第３の層間絶縁層１１０を、プラズマＣＶＤ等により堆積する。第３の層間絶縁層１１０は、シリコン酸化物等で構成される。なお、必要に応じて、ＣＭＰにより第３の層間絶縁層１１０の上面に対して段差緩和を行う。 Thereafter, as shown in FIG. 5A, a third interlayer insulating layer 110 for embedding and forming the second plug 111 is deposited on the second interlayer insulating layer 103 including the resistance change element 109 by plasma CVD or the like. To do. The third interlayer insulating layer 110 is made of silicon oxide or the like. If necessary, the step is reduced on the upper surface of the third interlayer insulating layer 110 by CMP.
　その後、図５Ｂに示すように、第１のプラグ１０４を形成する方法と同様の方法により、第３の層間絶縁層１１０の内部且つ抵抗変化素子１０９上に、第２電極１０８と電気的に接続される第２のプラグ１１１を形成する。第２のプラグ１１１は、タングステン等で構成される。 Thereafter, as shown in FIG. 5B, the second electrode 108 is electrically connected to the inside of the third interlayer insulating layer 110 and on the variable resistance element 109 by a method similar to the method of forming the first plug 104. The second plug 111 to be formed is formed. The second plug 111 is made of tungsten or the like.
　最後に、第３の層間絶縁層１１０上且つ第２のプラグ１１１上に、第２のプラグ１１１と電気的に接続される第２の配線１１２を形成する。第２の配線１１２は、第１の配線１０２と同様に、アルミニウム又は銅等で構成される。 Finally, a second wiring 112 electrically connected to the second plug 111 is formed on the third interlayer insulating layer 110 and the second plug 111. Similar to the first wiring 102, the second wiring 112 is made of aluminum, copper, or the like.
　以上の工程により、図１に示される不揮発性記憶素子１０が形成される。 Through the above steps, the nonvolatile memory element 10 shown in FIG. 1 is formed.
　以上説明したように、本実施の形態に係る不揮発性記憶素子１０では、第１のプラグ１０４の上面を覆う変質防止層１０５を形成することによって、抵抗変化素子１０９のドライエッチング及びアクティブ面積を縮小させる抵抗変化素子１０９の側壁面酸化を行った際に、第１のプラグ１０４の酸化又は変質を防止することができ、電気的特性が良好な第１のプラグ１０４を形成することができる。これにより、抵抗変化素子１０９以外の寄生抵抗成分が小さく、安定的に動作する不揮発性記憶素子１０を実現することができる。 As described above, in the nonvolatile memory element 10 according to the present embodiment, the dry etching and the active area of the resistance change element 109 are reduced by forming the alteration preventing layer 105 that covers the upper surface of the first plug 104. When the side wall surface oxidation of the variable resistance element 109 to be performed is performed, the first plug 104 can be prevented from being oxidized or deteriorated, and the first plug 104 with good electrical characteristics can be formed. As a result, the nonvolatile memory element 10 that has a small parasitic resistance component other than the resistance change element 109 and operates stably can be realized.
　なお、本実施の形態においては、抵抗変化素子１０９の第２電極１０８をイリジウムで構成しているが、本発明はこれに限られない。例えば、第２電極１０８を、白金、銅、タングステン、イリジウム及びパラジウムのいずれかの金属、或いは、これらの金属の組み合わせ又は合金で構成してもよい。例えば、第２電極１０８を合金で構成することにより、抵抗変化層１０７の初期抵抗値の低下及びばらつきを抑えつつ、初期ブレイク電圧を低く抑えることができる。ここで、初期ブレイク電圧とは、抵抗変化素子１０９に印加することによって、抵抗変化層１０７の抵抗値を初期抵抗値から通常の動作レンジに低下させることができる電圧をいう。 In the present embodiment, the second electrode 108 of the variable resistance element 109 is made of iridium, but the present invention is not limited to this. For example, the second electrode 108 may be made of any metal of platinum, copper, tungsten, iridium, and palladium, or a combination or alloy of these metals. For example, by configuring the second electrode 108 with an alloy, it is possible to suppress the initial break voltage to a low level while suppressing a decrease and variation in the initial resistance value of the resistance change layer 107. Here, the initial break voltage refers to a voltage that can be applied to the resistance change element 109 to reduce the resistance value of the resistance change layer 107 from the initial resistance value to the normal operating range.
　また、第１電極１０６の材料として、タンタル窒化物以外に、タンタル及びチタン窒化物等を用いてもよい。 In addition to tantalum nitride, tantalum and titanium nitride may be used as the material for the first electrode 106.
　さらに、抵抗変化層１０７は、同種の遷移金属酸化物で構成される抵抗変化層を２層以上積層して構成してもよい。 Furthermore, the resistance change layer 107 may be formed by stacking two or more resistance change layers made of the same kind of transition metal oxide.
　（実施の形態２）
　図６は、本実施の形態に係る不揮発性記憶素子２０の構成を示す断面図である。本実施の形態に係る不揮発性記憶素子２０では、図６に示すように、抵抗変化素子１０９Ａの下面（即ち、第１電極１０６の下面）の水平断面積は、変質防止層１０５Ａの上面の水平断面積よりも大きく、抵抗変化素子１０９Ａの中心軸１２０ａが第１のプラグ１０４Ａの中心軸１２０ｂに対して水平方向（図６において右側）に偏倚している。そのため、変質防止層１０５Ａの上面の一部は、抵抗変化素子１０９Ａの下面によって覆われずに露出している。本実施の形態に係る不揮発性記憶素子２０の他の構成は、実施の形態１に係る不揮発性記憶素子１０とほぼ同様である。なお、本明細書において「中心軸」とは、抵抗変化素子１０９Ａ及び第１のプラグ１０４Ａの水平断面が円形の場合はその水平断面の中心を通り、水平断面に対して垂直な線で規定され、また抵抗変化素子１０９Ａ及び第１のプラグ１０４Ａの水平断面が多角形等の場合はその重心を通り、水平断面に対して垂直な線で規定される。 (Embodiment 2)
FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory element 20 according to the present embodiment. In the nonvolatile memory element 20 according to the present embodiment, as shown in FIG. 6, the horizontal cross-sectional area of the lower surface of the resistance change element 109A (that is, the lower surface of the first electrode 106) is horizontal with respect to the upper surface of the alteration preventing layer 105A. The central axis 120a of the variable resistance element 109A is offset in the horizontal direction (right side in FIG. 6) with respect to the central axis 120b of the first plug 104A. Therefore, a part of the upper surface of the alteration preventing layer 105A is exposed without being covered by the lower surface of the resistance change element 109A. Other configurations of the nonvolatile memory element 20 according to the present embodiment are substantially the same as those of the nonvolatile memory element 10 according to the first embodiment. In this specification, the “center axis” is defined by a line that passes through the center of the horizontal section of the variable resistance element 109A and the first plug 104A and is perpendicular to the horizontal section when the horizontal section is circular. When the horizontal cross section of the resistance change element 109A and the first plug 104A is a polygon or the like, it is defined by a line that passes through the center of gravity and is perpendicular to the horizontal cross section.
　第１のプラグ１０４Ａが形成されている位置に合わせて、フォトリソグラフィーとドライエッチングとにより抵抗変化素子１０９Ａをドット形状に加工する際に、第１のプラグ１０４Ａの中心軸と抵抗変化素子１０９Ａの中心軸との位置合わせずれが発生する場合がある。そのため、特に、第１電極１０６の下面の水平断面積が第１のプラグ１０４Ａの上面の水平断面積よりも大きい場合には、図６に示すように、上述した位置合わせずれが発生しやすい。 When the resistance change element 109A is processed into a dot shape by photolithography and dry etching in accordance with the position where the first plug 104A is formed, the center axis of the first plug 104A and the center of the resistance change element 109A Misalignment with the shaft may occur. Therefore, especially when the horizontal cross-sectional area of the lower surface of the first electrode 106 is larger than the horizontal cross-sectional area of the upper surface of the first plug 104A, the above-described misalignment tends to occur as shown in FIG.
　本実施の形態では、第１のプラグ１０４Ａの上面が変質防止層１０５Ａによって覆われているので、抵抗変化素子１０９Ａをドット形状に加工するドライエッチング及び抵抗変化素子１０９Ａのアクティブ面積を縮小するための側壁面酸化による第１のプラグ１０４Ａの酸化又は変質を防止することができる。 In this embodiment, since the upper surface of the first plug 104A is covered with the alteration preventing layer 105A, dry etching for processing the resistance change element 109A into a dot shape and an active area for reducing the active area of the resistance change element 109A are reduced. Oxidation or alteration of the first plug 104A due to side wall surface oxidation can be prevented.
　なお、第１電極１０６Ａの下面の水平断面積を変質防止層１０５Ａの上面の水平断面積と等しく構成した場合であっても、本実施の形態と同様の効果を得ることができる。 Even when the horizontal cross-sectional area of the lower surface of the first electrode 106A is configured to be equal to the horizontal cross-sectional area of the upper surface of the alteration preventing layer 105A, the same effect as in the present embodiment can be obtained.
　（実施の形態３）
　図７は、本実施の形態に係る不揮発性記憶素子３０の構成を示す断面図である。本実施の形態に係る不揮発性記憶素子３０では、抵抗変化素子１０９Ｂの第１電極が省略され、変質防止層１０５Ｂが抵抗変化素子１０９Ｂの第１電極としての機能を兼ねている。抵抗変化層１０７は、変質防止層１０５Ｂと第２電極１０８との間に配置されている。抵抗変化層１０７の下面の水平断面積は、変質防止層１０５Ｂの上面の水平断面積よりも小さく構成されている。本実施の形態に係る不揮発性記憶素子３０の他の構成は、実施の形態１に係る不揮発性記憶素子１０とほぼ同様である。 (Embodiment 3)
FIG. 7 is a cross-sectional view showing the configuration of the nonvolatile memory element 30 according to this embodiment. In the nonvolatile memory element 30 according to the present embodiment, the first electrode of the resistance change element 109B is omitted, and the alteration preventing layer 105B also functions as the first electrode of the resistance change element 109B. The resistance change layer 107 is disposed between the alteration preventing layer 105 </ b> B and the second electrode 108. The horizontal sectional area of the lower surface of the resistance change layer 107 is configured to be smaller than the horizontal sectional area of the upper surface of the alteration preventing layer 105B. Other configurations of the nonvolatile memory element 30 according to the present embodiment are substantially the same as those of the nonvolatile memory element 10 according to the first embodiment.
　本実施の形態では、ドライエッチングにより抵抗変化素子１０９Ｂをドット形状に形成する際に、第２電極１０８及び抵抗変化層１０７の２層で構成される積層体を加工すればよいので、ドライエッチングの対象となる膜の種類及び厚みを低減することができる。これにより、抵抗変化素子１０９Ｂの寸法ばらつきを低減することができ、抵抗変化素子１０９Ｂの微細化が容易になる。 In the present embodiment, when the resistance change element 109B is formed in a dot shape by dry etching, a stacked body including the second electrode 108 and the resistance change layer 107 may be processed. The type and thickness of the target film can be reduced. Thereby, the dimensional variation of the resistance change element 109B can be reduced, and the resistance change element 109B can be easily miniaturized.
　第２電極１０８の材料として、抵抗変化層１０７Ｂを構成する遷移金属及び変質防止層１０５Ｂを構成する材料と比べて標準電極電位がより高い材料、例えば、白金（Ｐｔ）又はイリジウム（Ｉｒ）等を用いることにより、第２電極１０８と抵抗変化層１０７との界面近傍の抵抗変化層１０７中において、選択的に酸化還元反応が発生し、安定した抵抗変化現象が得られる。 As a material of the second electrode 108, a material having a higher standard electrode potential than the material constituting the transition metal constituting the resistance change layer 107B and the alteration preventing layer 105B, such as platinum (Pt) or iridium (Ir), is used. By using it, a redox reaction occurs selectively in the resistance change layer 107 in the vicinity of the interface between the second electrode 108 and the resistance change layer 107, and a stable resistance change phenomenon is obtained.
　なお、本実施の形態においても、実施の形態２と同様に、抵抗変化層１０７の下面の水平断面積を変質防止層１０５Ｂの上面の水平断面積と等しく又はこれよりも大きく構成し、抵抗変化素子１０９Ｂの中心軸を第１のプラグ１０４の中心軸に対して水平方向に偏倚させることができる。 Also in the present embodiment, as in the second embodiment, the horizontal cross-sectional area of the lower surface of the resistance change layer 107 is configured to be equal to or larger than the horizontal cross-sectional area of the upper surface of the alteration preventing layer 105B to change the resistance. The central axis of the element 109B can be offset in the horizontal direction with respect to the central axis of the first plug 104.
　（実施の形態４）
　図８は、本実施の形態に係る不揮発性記憶素子４０の構成を示す断面図である。本実施の形態に係る不揮発性記憶素子４０では、変質防止層１０５Ｃは、第２の層間絶縁層１０３の上面に対して、上側に突出して形成されている。なお、本明細書において、第２の層間絶縁層１０３の上面に対して上側を「コンタクトホール１１３の外部」と呼ぶことがある。また、第１の配線１０２Ｃ及び第２の配線１１２Ｃはそれぞれ、第１の層間絶縁層１０１Ｃ及び第３の層間絶縁層１１０Ｃの内部に埋め込み形成されている。さらに、第２のプラグは設けられていない。本実施の形態に係る不揮発性記憶素子４０の他の構成は、実施の形態１に係る不揮発性記憶素子１０とほぼ同様である。 (Embodiment 4)
FIG. 8 is a cross-sectional view showing a configuration of the nonvolatile memory element 40 according to the present embodiment. In the nonvolatile memory element 40 according to the present embodiment, the alteration preventing layer 105 </ b> C is formed so as to protrude upward from the upper surface of the second interlayer insulating layer 103. In this specification, the upper side of the upper surface of the second interlayer insulating layer 103 may be referred to as “outside of the contact hole 113”. In addition, the first wiring 102C and the second wiring 112C are embedded in the first interlayer insulating layer 101C and the third interlayer insulating layer 110C, respectively. Furthermore, the second plug is not provided. Other configurations of the nonvolatile memory element 40 according to the present embodiment are substantially the same as those of the nonvolatile memory element 10 according to the first embodiment.
　次に、本実施の形態に係る不揮発性記憶素子４０の製造方法について説明する。図９Ａ～図１２Ｂは、本実施の形態に係る不揮発性記憶素子４０の製造方法を示す断面図である。 Next, a method for manufacturing the nonvolatile memory element 40 according to this embodiment will be described. 9A to 12B are cross-sectional views showing a method for manufacturing the nonvolatile memory element 40 according to the present embodiment.
　まず、図９Ａに示すように、トランジスタ等が予め形成された半導体基板（図示せず）上に第１の層間絶縁層１０１Ｃを形成する。その後、第１の層間絶縁層１０１Ｃの内部に、第１の配線１０２Ｃを埋め込み形成するための配線溝１１５をフォトリソグラフィー及びドライエッチングにより形成する。 First, as shown in FIG. 9A, a first interlayer insulating layer 101C is formed on a semiconductor substrate (not shown) on which transistors and the like are formed in advance. Thereafter, a wiring groove 115 for embedding and forming the first wiring 102C is formed in the first interlayer insulating layer 101C by photolithography and dry etching.
　その後、図９Ｂに示すように、この配線溝１１５を含む第１の層間絶縁層１０１Ｃ上に配線材料１０２Ｃ’をスパッタ法等により堆積させる。この配線材料１０２Ｃ’は、例えば、タンタル窒化物（膜厚５～４０ｎｍ）及びタンタル（５～４０ｎｍ）を積層させたバリアメタル層と、電解めっき法のシード層となる銅（５０～３００ｎｍ）とで構成される。その後、電解めっき法により、銅のシード層上に銅をさらに堆積させることにより、配線溝１０２Ｃ’を銅で充填する。 Thereafter, as shown in FIG. 9B, a wiring material 102C ′ is deposited on the first interlayer insulating layer 101C including the wiring trench 115 by a sputtering method or the like. The wiring material 102C ′ includes, for example, a barrier metal layer in which tantalum nitride (film thickness 5 to 40 nm) and tantalum (5 to 40 nm) are stacked, copper (50 to 300 nm) serving as a seed layer for electrolytic plating, and Consists of. Thereafter, copper is further deposited on the copper seed layer by electrolytic plating to fill the wiring trench 102 </ b> C ′ with copper.
　その後、図９Ｃに示すように、堆積したバリアメタル層及び銅のうち、第１の層間絶縁層１０１Ｃの上面の余分な銅をＣＭＰによって除去しながら、第１の層間絶縁層１０１Ｃの上面と第１の配線１０２Ｃの上面とを平坦状に形成する。これにより、第１の配線１０２Ｃが形成される。 Thereafter, as shown in FIG. 9C, of the deposited barrier metal layer and copper, excess copper on the upper surface of the first interlayer insulating layer 101C is removed by CMP, and the upper surface of the first interlayer insulating layer 101C and the first copper are removed. The upper surface of one wiring 102C is formed flat. Thereby, the first wiring 102C is formed.
　次に、図１０Ａに示すように、プラズマＣＶＤ等により、第１の配線１０２Ｃを含む第１の層間絶縁層１０１Ｃ上に、シリコン窒化物又はシリコン酸化物で構成される第２の層間絶縁層１０３をさらに堆積させる。なお、必要に応じて、ＣＭＰにより第２の層間絶縁層１０３の上面に対して段差緩和を行う。その後、フォトリソグラフィー及びドライエッチングにより、第１の配線１０２Ｃ上の所定の位置に、第１のプラグ１０４を埋め込み形成するためのコンタクトホール１１３を形成する。 Next, as shown in FIG. 10A, the second interlayer insulating layer 103 made of silicon nitride or silicon oxide is formed on the first interlayer insulating layer 101C including the first wiring 102C by plasma CVD or the like. Is further deposited. Note that, if necessary, step relaxation is performed on the upper surface of the second interlayer insulating layer 103 by CMP. Thereafter, a contact hole 113 for embedding the first plug 104 is formed at a predetermined position on the first wiring 102C by photolithography and dry etching.
　その後、形成されたコンタクトホール１１３を含む第２の層間絶縁層１０３上に、タンタル窒化物及びタンタルで構成されるバリアメタル層と導電材料の銅とをスパッタ法等により堆積させる。そして、電解めっき法により銅をシードとして、銅をさらに堆積させてコンタクトホール１１３をバリアメタル層及び銅で満たす。これにより、第１のプラグ１０４が形成される。その後、ＣＭＰによって、第１のプラグ１０４の上面の余分な銅及びバリアメタル層を除去するとともに、第２の層間絶縁層１０３の上面と第１のプラグ１０４の上面とを平坦状に形成する。これにより、第１のプラグ１０４は、コンタクトホール１１３に完全に埋め込まれた状態となる。 Thereafter, a barrier metal layer made of tantalum nitride and tantalum and copper as a conductive material are deposited on the second interlayer insulating layer 103 including the formed contact hole 113 by sputtering or the like. Then, copper is further deposited by electrolytic plating using copper as a seed to fill the contact hole 113 with the barrier metal layer and copper. Thereby, the first plug 104 is formed. Thereafter, excess copper and the barrier metal layer on the upper surface of the first plug 104 are removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104 are formed flat. As a result, the first plug 104 is completely embedded in the contact hole 113.
　次に、図１０Ｂに示すように、第１のプラグ１０４の上面を覆う変質防止層１０５Ｃを無電解めっき法により形成する。これにより、変質防止層１０５Ｃは、第２の層間絶縁層１０３の上面及び第１のプラグ１０４の上面で構成される平坦面に対して、上側に突出して形成される。本実施の形態では、変質防止層１０５Ｃは、コバルト・タングステン・リン（ＣｏＷＰ）合金で構成される。その後、ＣＭＰによって、変質防止層１０５Ｃの上面を平坦状に形成する。このとき、変質防止層１０５Ｃは、上記平坦面に対して上側に突出して形成されているので、ＣＭＰにより変質防止層１０５Ｃの上面のみが削られる。これにより、第２の層間絶縁層１０３の上面が削れてしまうロスを抑制することができる。 Next, as shown in FIG. 10B, an alteration preventing layer 105C covering the upper surface of the first plug 104 is formed by an electroless plating method. Thereby, the alteration preventing layer 105 </ b> C is formed so as to protrude upward with respect to a flat surface constituted by the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104. In the present embodiment, the alteration preventing layer 105C is made of a cobalt-tungsten-phosphorus (CoWP) alloy. Thereafter, the upper surface of the alteration preventing layer 105C is formed flat by CMP. At this time, since the alteration preventing layer 105C is formed so as to protrude upward with respect to the flat surface, only the upper surface of the alteration preventing layer 105C is scraped by CMP. Thereby, the loss which the upper surface of the 2nd interlayer insulation layer 103 scrapes can be suppressed.
　無電解めっき法を用いることにより、変質防止層１０５Ｃは導電材料で構成される第１のプラグ１０４の上面のみに選択的に析出し、絶縁材料で構成される第２の層間絶縁層１０３上には析出しないため、選択成長的に第１のプラグ１０４の上面のみを覆う変質防止層１０５Ｃを形成することができる。また、無電解めっき法を用いることにより、ＣＭＰ及びドライエッチング等による形状加工を行う必要がなく、微細化に好都合である。さらに、銅はタングステンよりも抵抗率が小さいため、第１のプラグ１０４を銅で構成することにより、第１のプラグ１０４の抵抗率を下げることができ、配線遅延の影響が小さく且つ高速動作可能な不揮発性記憶素子４０を実現することができる。 By using the electroless plating method, the alteration preventing layer 105C is selectively deposited only on the upper surface of the first plug 104 made of a conductive material, and on the second interlayer insulating layer 103 made of an insulating material. Therefore, the alteration preventing layer 105C that covers only the upper surface of the first plug 104 can be formed selectively. Further, by using the electroless plating method, it is not necessary to perform shape processing by CMP, dry etching, or the like, which is convenient for miniaturization. Furthermore, since copper has a resistivity lower than that of tungsten, the resistivity of the first plug 104 can be lowered by configuring the first plug 104 with copper, and the influence of wiring delay is small and high-speed operation is possible. A nonvolatile memory element 40 can be realized.
　このコバルト・タングステン・リン合金の無電解めっきには、次亜リン酸塩（次亜リン酸ナトリウムなど）を還元剤として含むめっき浴が用いられる。この場合、無電解めっき処理前に、銅で構成される第１のプラグ１０４の表面を予め塩化パラジウム水溶液に数秒間浸漬し、パラジウム触媒層を付与するとよい。これは、次亜リン酸水溶液は、鉄（Ｆｅ）、ニッケル（Ｎｉ）、コバルト（Ｃｏ）及びパラジウム（Ｐａ）等の鉄族元素及び白金族元素の金属を含浸することにより金属の表面が触媒となり、次亜リン酸イオンの酸化反応が起こるためである。 For the electroless plating of this cobalt / tungsten / phosphorus alloy, a plating bath containing hypophosphite (such as sodium hypophosphite) as a reducing agent is used. In this case, before the electroless plating treatment, the surface of the first plug 104 made of copper may be preliminarily immersed in an aqueous palladium chloride solution for several seconds to provide a palladium catalyst layer. This is because the surface of the metal is catalyzed by impregnating iron group elements such as iron (Fe), nickel (Ni), cobalt (Co) and palladium (Pa), and metals of platinum group elements. This is because an oxidation reaction of hypophosphite ions occurs.
　一般に、銅で構成された配線及びプラグでは、配線及びプラグの上面から銅が層間絶縁層中へ拡散することを防止するために、シリコン窒化物で構成されるキャップ層を堆積する。しかしながら、絶縁体であるシリコン窒化物で構成されるキャップ層を堆積することによって、配線層間の電荷容量が増加し、回路のＲＣ遅延が発生するという問題が生じる。本実施の形態では、導電材料で構成される変質防止層１０５Ｃを用いるため、絶縁材料で構成される変質防止層を用いる場合に比べて、配線層間の電荷容量を低減することができ、さらに回路のＲＣ遅延を抑制することができるため、高速動作可能な不揮発性記憶素子４０を実現できるという効果もある。 Generally, in a wiring and a plug made of copper, a cap layer made of silicon nitride is deposited in order to prevent copper from diffusing into the interlayer insulating layer from the upper surface of the wiring and the plug. However, depositing a cap layer made of silicon nitride, which is an insulator, increases the charge capacity between the wiring layers and causes a problem of RC delay of the circuit. In this embodiment, since the alteration preventing layer 105C made of a conductive material is used, the charge capacity between the wiring layers can be reduced as compared with the case where the alteration preventing layer made of an insulating material is used. Since the RC delay can be suppressed, the nonvolatile memory element 40 capable of high-speed operation can be realized.
　その後、図１０Ｃに示すように、実施の形態１に係る不揮発性記憶素子１０の製造方法と同様の方法により、変質防止層１０５Ｃを含む第１のプラグ１０４上に、抵抗変化素子１０９を形成する。 Thereafter, as shown in FIG. 10C, the variable resistance element 109 is formed on the first plug 104 including the alteration preventing layer 105C by a method similar to the method for manufacturing the nonvolatile memory element 10 according to Embodiment 1. .
　その後、図１１Ａに示すように、抵抗変化素子１０９を含む第２の層間絶縁層１０３上に、プラズマＣＶＤ等により第３の層間絶縁層１１０Ｃを堆積する。第３の層間絶縁層１１０Ｃは、シリコン酸化物等で構成される。なお、必要に応じて、ＣＭＰにより第３の層間絶縁層１１０Ｃの上面に対して段差緩和を行う。 Thereafter, as shown in FIG. 11A, a third interlayer insulating layer 110C is deposited on the second interlayer insulating layer 103 including the resistance change element 109 by plasma CVD or the like. The third interlayer insulating layer 110C is made of silicon oxide or the like. Note that, if necessary, the step is relaxed on the upper surface of the third interlayer insulating layer 110C by CMP.
　続いて、図１１Ｂに示すように、第３の層間絶縁層１１０Ｃの内部に、第２の配線１１２Ｃを埋め込み形成するための配線溝１１６をフォトリソグラフィー及びドライエッチングにより形成する。その後、図１２Ａに示すように、この配線溝１１６を含む第３の層間絶縁層１１０Ｃ上に配線材料１１２Ｃ’をスパッタ法等により堆積させる。この配線材料１１２Ｃ’は、例えば、タンタル窒化物（例えば、膜厚５～４０ｎｍ）及びタンタル（例えば、５～４０ｎｍ）を積層させたバリアメタル層と、電解めっき法のシード層となる銅（例えば、５０～３００ｎｍ）とで構成される。その後、電解めっき法により、銅のシード層上に銅をさらに堆積させることにより、配線溝１１２Ｃ’を銅で充填する。 Subsequently, as shown in FIG. 11B, a wiring trench 116 for embedding the second wiring 112C is formed in the third interlayer insulating layer 110C by photolithography and dry etching. Thereafter, as shown in FIG. 12A, a wiring material 112C 'is deposited on the third interlayer insulating layer 110C including the wiring trench 116 by sputtering or the like. The wiring material 112C ′ includes, for example, a barrier metal layer in which tantalum nitride (for example, a film thickness of 5 to 40 nm) and tantalum (for example, 5 to 40 nm) are laminated, and copper (for example, a seed layer for electrolytic plating) (for example, , 50 to 300 nm). Thereafter, copper is further deposited on the copper seed layer by electrolytic plating to fill the wiring trench 112C 'with copper.
　その後、図１２Ｂに示すように、堆積したバリアメタル層及び銅のうち、第３の層間絶縁層１１０Ｃの上面の余分な銅をＣＭＰによって除去しながら、第３の層間絶縁層１１０Ｃの上面と第２の配線１１２Ｃの上面とを平坦状に形成する。これにより、第２の配線１１２Ｃが形成される。 After that, as shown in FIG. 12B, excess copper on the upper surface of the third interlayer insulating layer 110C is removed by CMP from the deposited barrier metal layer and copper, and the upper surface of the third interlayer insulating layer 110C and the first copper are removed. The upper surface of the second wiring 112C is formed flat. Thereby, the second wiring 112C is formed.
　以上の工程により、図８に示される不揮発性記憶素子４０が形成される。 Through the above steps, the nonvolatile memory element 40 shown in FIG. 8 is formed.
　なお、本実施の形態においても、実施の形態２と同様に、第１電極１０６の下面の水平断面積を変質防止層１０５Ｃの上面の水平断面積と等しく又はこれよりも大きく構成し、抵抗変化素子１０９の中心軸を第１のプラグ１０４の中心軸に対して水平方向に偏倚させることができる。また、実施の形態３と同様に、抵抗変化素子１０９の第１電極を省略し、変質防止層１０５Ｃが抵抗変化素子１０９の第１電極としての機能を兼ねるように構成することができる。 Also in the present embodiment, as in the second embodiment, the horizontal cross-sectional area of the lower surface of the first electrode 106 is configured to be equal to or larger than the horizontal cross-sectional area of the upper surface of the alteration preventing layer 105C to change the resistance. The central axis of the element 109 can be offset in the horizontal direction with respect to the central axis of the first plug 104. Further, similarly to the third embodiment, the first electrode of the resistance change element 109 may be omitted, and the alteration preventing layer 105C may also function as the first electrode of the resistance change element 109.
　以上、本発明の一つ又は複数の態様に係る不揮発性記憶素子及びその製造方法について、実施の形態に基づいて説明したが、本発明は、この実施の形態に限定されるものではない。本発明の趣旨を逸脱しない限り、当業者が思い付く各種変形を本実施の形態に施したものや、異なる実施の形態における構成要素を組み合わせて構築される形態も、本発明の一つ又は複数の態様の範囲内に含まれてもよい。 As mentioned above, although the non-volatile memory element which concerns on the one or several aspect of this invention, and its manufacturing method were demonstrated based on embodiment, this invention is not limited to this embodiment. Unless it deviates from the gist of the present invention, one or more of the present invention may be applied to various modifications that can be conceived by those skilled in the art, or forms constructed by combining components in different embodiments. It may be included within the scope of the embodiments.
　上記の実施の形態１～４においては、抵抗変化層を構成する遷移金属酸化物として、タンタル酸化物、ハフニウム酸化物及びジルコニウム酸化物の場合について説明したが、第１電極と第２電極との間に挟まれる遷移金属酸化物層としては、抵抗変化を発現する主たる抵抗変化層として、タンタル、ハフニウム及びジルコニウム等の酸化物層が含まれていればよく、これ以外に例えば微量の他元素が含まれていても構わない。抵抗値の微調整等で、他元素を少量、意図的に含めることも可能であり、このような場合も本発明の範囲に含まれる。例えば、抵抗変化層に窒素を添加した場合には、抵抗変化層の抵抗値が上昇し、抵抗変化の反応性を改善することができる。 In the first to fourth embodiments described above, the case where tantalum oxide, hafnium oxide, and zirconium oxide are used as the transition metal oxide constituting the resistance change layer has been described. As the transition metal oxide layer sandwiched between them, it is only necessary to include an oxide layer such as tantalum, hafnium, and zirconium as the main resistance change layer that exhibits resistance change. It may be included. It is possible to intentionally include a small amount of other elements by fine adjustment of the resistance value, and such a case is also included in the scope of the present invention. For example, when nitrogen is added to the resistance change layer, the resistance value of the resistance change layer increases and the resistance change resistance can be improved.
　また、スパッタリングにより抵抗変化薄膜を形成した際に、残留ガス及び真空容器壁からのガス放出等により、意図しない微量の元素が抵抗変化薄膜に混入する場合がある。このような微量の元素が抵抗変化薄膜に混入した場合も、本発明の範囲に含まれることは当然である。 Also, when a variable resistance thin film is formed by sputtering, an unintended trace amount of elements may be mixed into the variable resistance thin film due to residual gas and gas release from the vacuum vessel wall. Naturally, such a trace amount of elements mixed in the resistance change thin film is also included in the scope of the present invention.
　上記の実施の形態１～４では、抵抗変化素子がドット形状に形成されている例について説明したが、本発明の抵抗変化素子は当該形状に限定されない。 In Embodiments 1 to 4 described above, the example in which the variable resistance element is formed in a dot shape has been described, but the variable resistance element of the present invention is not limited to this shape.
　上記の実施の形態１～４では、抵抗変化素子をドライエッチングによってドット形状に加工する際に用いるエッチングガス又はプラズマ等による変質が、変質防止層によって防止される例について説明したが、当該加工工程は必ずしも必要ではない。変質防止層は、他の工程に対しても、変質を防止し得る。例えば、プラグ形成後に層間絶縁層を形成する際の変質（酸化、窒化及びフッ化等）も防止し得る。要するに、本発明の変質防止層は、プラグ形成後の工程で用いるガス又はプラズマ等によって引き起こされる変質に対して、防止効果を奏する。 In the first to fourth embodiments described above, the example in which the alteration by the etching gas or plasma used when the variable resistance element is processed into a dot shape by dry etching is prevented by the alteration preventing layer has been described. Is not necessarily required. The alteration preventing layer can also prevent alteration with respect to other steps. For example, alteration (oxidation, nitridation, fluorination, etc.) when forming an interlayer insulating layer after plug formation can be prevented. In short, the alteration preventing layer of the present invention has an effect of preventing alteration caused by gas or plasma used in the process after plug formation.
　上記の実施の形態１～４では、抵抗変化素子が酸素不足型の遷移金属酸化物を含む抵抗変化層を備えるＲｅＲＡＭで構成された例について説明したが、当該抵抗変化素子は、電気的信号に基づいて、高抵抗状態と当該高抵抗状態より抵抗値が低い低抵抗状態との間を可逆的に変化する素子であればよい。従って、抵抗変化素子は、例えば、相変化材料を用いた相変化メモリ（ＰＣＲＡＭ：Ｐｈａｓｅ－Ｃｈａｎｇｅ　ＲＡＭ）及び記憶素子に磁性体を用い、書き込み方式にスピン注入磁化反転を採用する磁気抵抗メモリ（ＭＲＡＭ：Ｍａｇｎｅｔｏｒｅｓｉｓｔｉｖｅ　ＲＡＭ）等で構成してもよい。 In the first to fourth embodiments described above, the example in which the variable resistance element is configured by the ReRAM including the variable resistance layer including the oxygen-deficient transition metal oxide has been described. However, the variable resistance element is used as an electrical signal. Any element that reversibly changes between a high resistance state and a low resistance state having a resistance value lower than that of the high resistance state may be used. Therefore, the resistance change element includes, for example, a phase change memory (PCRAM: Phase-Change RAM) using a phase change material, a magnetic substance as a storage element, and a magnetoresistive memory (MRAM) adopting spin injection magnetization reversal as a writing method. : Magnetoretic RAM) or the like.
　また、厳密に言うと抵抗変化素子ではないが、電気的信号に基づいて、分極反転による電流が流れるかどうかで１と０とを判定する強誘電体メモリ（ＦｅＲＡＭ：Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　ＲＡＭ）であってもよい。 Strictly speaking, although it is not a resistance change element, even a ferroelectric memory (FeRAM: Ferroelectric RAM) that determines 1 and 0 based on whether a current due to polarization reversal flows based on an electrical signal. Good.
　上記の実施の形態１～４では、各プラグや各配線にバリアメタル層及びシード層が設けられている例について説明したが、本発明においてこれらは必須の構成ではなく、設計に応じて適宜設けられる構成に過ぎない。 In the first to fourth embodiments described above, the example in which the barrier metal layer and the seed layer are provided in each plug and each wiring has been described. However, in the present invention, these are not indispensable structures and are appropriately provided according to the design. It is only the composition made.
　上記の実施の形態１～４に係る不揮発性記憶素子は、典型的には集積回路であるＬＳＩとして実現される。これらは個別に１チップ化されてもよく、或いは、一部又は全てを含むように１チップ化されてもよい。 The nonvolatile memory elements according to the first to fourth embodiments described above are typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
　上記の実施の形態１～４を説明するための各図面において、各構成要素の角部及び辺を直線的に記載しているが、製造上の理由により、各構成要素が角部及び辺が丸みを帯びた場合も本発明の範囲に含まれる。 In each of the drawings for explaining the first to fourth embodiments, corners and sides of each component are linearly described. However, for manufacturing reasons, each component has corners and sides. A rounded case is also included in the scope of the present invention.
　上記の実施の形態１～４で用いた不揮発性記憶素子の各構成要素の寸法及び製造のためのプロセス条件を規定する数値は全て、本発明を具体的に説明するために例示するものであり、本発明は例示された数値に制限されない。また、上記の実施形態１～４で示した各構成要素の材料は全て、本発明を具体的に説明するために例示するものであり、本発明は例示された材料に制限されない。 The numerical values that define the dimensions of the constituent elements of the nonvolatile memory elements used in the first to fourth embodiments and the process conditions for manufacturing are all examples for specifically explaining the present invention. The present invention is not limited to the exemplified numerical values. In addition, all the materials of the constituent elements shown in the above-described Embodiments 1 to 4 are exemplified for specifically explaining the present invention, and the present invention is not limited to the exemplified materials.
　また、上記の実施の形態１～４では、変質防止層の材料として、タングステン窒化物又はコバルト・タングステン・リン合金を用いたが、これら以外に、コバルト・タングステン・ボロン合金又は及びパラジウムを用いることもできる。 In the first to fourth embodiments, tungsten nitride or cobalt / tungsten / phosphorous alloy is used as the material for the alteration preventing layer. However, cobalt / tungsten / boron alloy or palladium is used in addition to these. You can also.
　また、上記の実施の形態１～４では、抵抗変化素子の抵抗変化層を２層構造としたが、１層構造とすることもできる。 In the first to fourth embodiments, the variable resistance layer of the variable resistance element has a two-layer structure. However, a single-layer structure may be used.
　本発明は、抵抗変化型の不揮発性記憶素子及びその製造方法に適用することができる。また、本発明は、不揮発性記憶素子を用いた種々の電子機器に対して有用である。 The present invention can be applied to a variable resistance nonvolatile memory element and a manufacturing method thereof. Further, the present invention is useful for various electronic devices using a nonvolatile memory element.
　１０，２０，３０，４０，５０　不揮発性記憶素子
　１０１，１０１Ｃ　第１の層間絶縁層
　１０２，１０２Ｃ　第１の配線
　１０２Ｃ’　配線材料
　１０３　第２の層間絶縁層
　１０４，１０４Ａ　第１のプラグ
　１０５，１０５Ａ，１０５Ｂ，１０５Ｃ　変質防止層
　１０５’　キャップメタル膜
　１０６　第１電極
　１０６’　第１電極薄膜
　１０７　抵抗変化層
　１０７ａ　第１の抵抗変化層
　１０７ｂ　第２の抵抗変化層
　１０７’　抵抗変化薄膜
　１０７ａ’　第１の抵抗変化薄膜
　１０７ｂ’　第２の抵抗変化薄膜
　１０８　第２電極
　１０８’　第２電極薄膜
　１０９，１０９Ａ，１０９Ｂ　抵抗変化素子
　１１０，１１０Ｃ　第３の層間絶縁層
　１１１　第２のプラグ
　１１２，１１２Ｃ　第２の配線
　１１２Ｃ’　配線材料
　１１３　コンタクトホール
　１１４　リセス
　１１５　配線溝
　１１６　配線溝
　１２０ａ，１２０ｂ　中心軸
　２０１　銅メタライゼーション層
　２０２　プラグ
　２０３　ＩＭＤ層
　２０４　溝
　２０５　バリア層
　２０６　銅相互接続層
　２０７　第１の積層体
　２０８　バリア層
　２０９　コンタクト層
　２１０　半導体
　２１１　コンタクト層
　２１２　バリア層
　２１３　第２の積層体
　２１４　バリア層
　２１５　電極層
　２１６　ＰＭＣ材料
　２１７　コンタクト層
　２１８　バリア層
　３０１　下層プラグ
　３０２　抵抗変化素子
　３０３　上層プラグ
　３０４　不具合領域 10, 20, 30, 40, 50 Nonvolatile memory element 101, 101C First interlayer insulating layer 102, 102C First wiring 102C 'Wiring material 103 Second interlayer insulating layer 104, 104A First plug 105, 105A 105B, 105C Anti-altering layer 105 ′ Cap metal film 106 First electrode 106 ′ First electrode thin film 107 Resistance change layer 107a First resistance change layer 107b Second resistance change layer 107 ′ Resistance change thin film 107a ′ First Resistance change thin film 107b ′ Second resistance change thin film 108 Second electrode 108 ′ Second electrode thin film 109, 109A, 109B Resistance change element 110, 110C Third interlayer insulating layer 111 Second plug 112, 112C Second wiring 112C 'wiring material 113 contact hole 114 recess 115 wiring groove 116 wiring groove 1 0a, 120b Central axis 201 Copper metallization layer 202 Plug 203 IMD layer 204 Groove 205 Barrier layer 206 Copper interconnect layer 207 First stack 208 Barrier layer 209 Contact layer 210 Semiconductor 211 Contact layer 212 Barrier layer 213 Second stack Body 214 Barrier layer 215 Electrode layer 216 PMC material 217 Contact layer 218 Barrier layer 301 Lower layer plug 302 Resistance change element 303 Upper layer plug 304 Failure region

Claims (21)

  1. 　第１の配線と、
    　前記第１の配線上に配置され、前記第１の配線に電気的に接続されるプラグと、
    　前記プラグの上面の全域を覆い、導電性を有する変質防止層と、
    　前記変質防止層の上面の一部を覆い、前記変質防止層を介して前記プラグに電気的に接続される積層体と、
    　前記積層体上に配置され、前記積層体に電気的に接続される第２の配線と、を備え、
    　前記積層体は、与えられる電気的信号に基づいて抵抗状態が可逆的に変化する抵抗変化層を含み、
    　前記変質防止層の下面の水平断面積は、前記プラグの上面の水平断面積と等しく、前記変質防止層の上面の一部は、前記積層体で覆われていない
    　不揮発性記憶素子。     A first wiring;
    A plug disposed on the first wiring and electrically connected to the first wiring;
    Covering the entire area of the upper surface of the plug, and having a conductivity-preventing alteration layer,
    A laminate that covers a part of the upper surface of the anti-altering layer and is electrically connected to the plug via the anti-altering layer;
    A second wiring disposed on the laminate and electrically connected to the laminate,
    The laminate includes a resistance change layer in which a resistance state reversibly changes based on an applied electrical signal,
    A non-volatile memory element, wherein a horizontal cross-sectional area of a lower surface of the alteration preventing layer is equal to a horizontal sectional area of an upper surface of the plug, and a part of the upper surface of the alteration preventing layer is not covered with the laminate.
  2. 　前記積層体はさらに、前記変質防止層を介して前記プラグに電気的に接続される第１電極と、前記第２の配線に電気的に接続される第２電極と、を含み、
    　前記抵抗変化層は、前記第１電極と前記第２電極との間に配置されている
    　請求項１に記載の不揮発性記憶素子。     The stacked body further includes a first electrode electrically connected to the plug through the alteration preventing layer, and a second electrode electrically connected to the second wiring,
    The nonvolatile memory element according to claim 1, wherein the variable resistance layer is disposed between the first electrode and the second electrode.
  3. 　前記第１電極の下面の水平断面積は、前記変質防止層の上面の水平断面積よりも小さい
    　請求項２に記載の不揮発性記憶素子。     The nonvolatile memory element according to claim 2, wherein a horizontal cross-sectional area of the lower surface of the first electrode is smaller than a horizontal cross-sectional area of the upper surface of the alteration preventing layer.
  4. 　前記第１電極の下面の水平断面積は、前記変質防止層の上面の水平断面積と等しい又は前記変質防止層の上面の水平断面積よりも大きく、
    　前記積層体の中心軸は、前記変質防止層の中心軸に対して偏倚し、
    　前記変質防止層の上面の一部は、前記第１電極で覆われていない
    　請求項２に記載の不揮発性記憶素子。     The horizontal cross-sectional area of the lower surface of the first electrode is equal to or greater than the horizontal cross-sectional area of the upper surface of the alteration preventing layer,
    The central axis of the laminate is deviated with respect to the central axis of the alteration preventing layer,
    The nonvolatile memory element according to claim 2, wherein a part of the upper surface of the alteration preventing layer is not covered with the first electrode.
  5. 　前記変質防止層は、前記プラグに電気的に接続される第１電極として機能し、前記積層体はさらに、前記第２の配線に電気的に接続される第２電極を含み、
    　前記抵抗変化層は、前記第１電極としての前記変質防止層と前記第２電極との間に配置されている
    　請求項１に記載の不揮発性記憶素子。     The alteration preventing layer functions as a first electrode electrically connected to the plug, and the stacked body further includes a second electrode electrically connected to the second wiring,
    The nonvolatile memory element according to claim 1, wherein the resistance change layer is disposed between the alteration preventing layer as the first electrode and the second electrode.
  6. 　前記抵抗変化層の下面の水平断面積は、前記変質防止層の上面の水平断面積よりも小さい
    　請求項５に記載の不揮発性記憶素子。     The nonvolatile memory element according to claim 5, wherein a horizontal cross-sectional area of the lower surface of the resistance change layer is smaller than a horizontal cross-sectional area of the upper surface of the alteration preventing layer.
  7. 　前記抵抗変化層の下面の水平断面積は、前記変質防止層の上面の水平断面積と等しい又は前記変質防止層の上面の水平断面積よりも大きく、
    　前記積層体の中心軸は、前記変質防止層の中心軸に対して偏倚し、
    　前記変質防止層の上面の一部は、前記抵抗変化層で覆われていない
    　請求項５に記載の不揮発性記憶素子。     The horizontal cross-sectional area of the lower surface of the resistance change layer is equal to or larger than the horizontal cross-sectional area of the upper surface of the alteration preventing layer,
    The central axis of the laminate is deviated with respect to the central axis of the alteration preventing layer,
    The nonvolatile memory element according to claim 5, wherein a part of the upper surface of the alteration preventing layer is not covered with the resistance change layer.
  8. 　さらに、前記第１の配線上に配置され、コンタクトホールを有する層間絶縁層を備え、
    　前記プラグ及び前記変質防止層はともに、前記コンタクトホールに埋め込まれている
    　請求項１～７のいずれか１項に記載の不揮発性記憶素子。     And an interlayer insulating layer disposed on the first wiring and having a contact hole,
    The nonvolatile memory element according to claim 1, wherein both the plug and the alteration preventing layer are embedded in the contact hole.
  9. 　前記変質防止層は、前記プラグを構成する金属の窒化物で構成される
    　請求項８に記載の不揮発性記憶素子。     The nonvolatile memory element according to claim 8, wherein the alteration preventing layer is made of a metal nitride constituting the plug.
  10. 　さらに、前記第１の配線上に配置され、コンタクトホールを有する層間絶縁層を備え、
    　前記プラグは前記コンタクトホールに埋め込まれ、前記変質防止層は、前記コンタクトホールの外部に突出されている
    　請求項１～７のいずれか１項に記載の不揮発性記憶素子。     And an interlayer insulating layer disposed on the first wiring and having a contact hole,
    The nonvolatile memory element according to any one of claims 1 to 7, wherein the plug is embedded in the contact hole, and the alteration preventing layer protrudes outside the contact hole.
  11. 　前記プラグは、タングステン又は銅で構成されている
    　請求項１～１０のいずれか１項に記載の不揮発性記憶素子。     The nonvolatile memory element according to any one of claims 1 to 10, wherein the plug is made of tungsten or copper.
  12. 　前記変質防止層は、酸素バリア性及び耐エッチング性を有する
    　請求項１～１１のいずれか１項に記載の不揮発性記憶素子。     The nonvolatile memory element according to any one of claims 1 to 11, wherein the alteration preventing layer has an oxygen barrier property and an etching resistance.
  13. 　前記変質防止層は、タングステン窒化物、コバルト・タングステン・リン合金、コバルト・タングステン・ボロン合金及びパラジウムのいずれかで構成されている
    　請求項１２に記載の不揮発性記憶素子。     The nonvolatile memory element according to claim 12, wherein the alteration preventing layer is made of any one of tungsten nitride, cobalt-tungsten-phosphorus alloy, cobalt-tungsten-boron alloy, and palladium.
  14. 　前記抵抗変化層は、遷移金属酸化物又はアルミニウム酸化物で構成されている
    　請求項１～１３のいずれか１項に記載の不揮発性記憶素子。     The nonvolatile memory element according to claim 1, wherein the variable resistance layer is made of a transition metal oxide or an aluminum oxide.
  15. 　前記抵抗変化層は、酸素不足型タンタル酸化物、酸素不足型ハフニウム酸化物及び酸素不足型ジルコニウム酸化物のうちの１つ以上の遷移金属酸化物で構成されている
    　請求項１４に記載の不揮発性記憶素子。     The nonvolatile memory according to claim 14, wherein the variable resistance layer is made of one or more transition metal oxides selected from oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, and oxygen-deficient zirconium oxide. Memory element.
  16. 　前記抵抗変化層は、第１の金属酸化物で構成される第１の抵抗変化層と、前記第１の金属酸化物より酸素不足度が小さい第２の金属酸化物で構成される第２の抵抗変化層と、を有する
    　請求項１～１３のいずれか１項に記載の不揮発性記憶素子。     The variable resistance layer includes a first variable resistance layer composed of a first metal oxide, and a second metal oxide composed of a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide. The nonvolatile memory element according to claim 1, further comprising a resistance change layer.
  17. 　第１の配線を形成する工程と、
    　前記第１の配線上に、前記第１の配線に電気的に接続されるプラグを形成する工程と、
    　前記プラグの上面の全域を覆い且つ導電性を有する変質防止層を形成する工程と、
    　前記変質防止層の上面の一部を覆い且つ前記変質防止層を介して前記プラグに電気的に接続される積層体を形成する工程と、
    　前記積層体上に配置され且つ前記積層体に電気的に接続される第２の配線を形成する工程と、を含み、
    　前記変質防止層を形成する工程では、前記変質防止層の下面の水平断面積が前記プラグの上面の水平断面積と等しくなるように前記変質防止層を形成し、
    　前記積層体を形成する工程では、前記変質防止層の上面の一部が前記積層体で覆われないように前記積層体を形成し、前記積層体は、与えられる電気的信号に基づいて抵抗状態が可逆的に変化する抵抗変化層を含む
    　不揮発性記憶素子の製造方法。     Forming a first wiring;
    Forming a plug electrically connected to the first wiring on the first wiring;
    Forming an alteration preventing layer that covers the entire upper surface of the plug and has conductivity;
    Forming a laminate that covers a part of the upper surface of the alteration preventing layer and is electrically connected to the plug via the alteration preventing layer;
    Forming a second wiring disposed on the laminate and electrically connected to the laminate,
    In the step of forming the alteration preventing layer, the alteration preventing layer is formed so that a horizontal sectional area of the lower surface of the alteration preventing layer is equal to a horizontal sectional area of the upper surface of the plug,
    In the step of forming the laminate, the laminate is formed such that a part of the upper surface of the alteration preventing layer is not covered with the laminate, and the laminate is in a resistance state based on an applied electrical signal. A method for manufacturing a non-volatile memory element, including a resistance change layer in which reversibly changes.
  18. 　前記積層体を形成する工程は、さらに、前記変質防止層を介して前記プラグに電気的に接続される第１電極を形成する工程と、前記第１電極上に前記抵抗変化層を形成する工程と、前記抵抗変化層上に第２電極を形成する工程と、を含み、
    　前記第２の配線を形成する工程では、前記第２電極と電気的に接続される前記第２の配線を形成する
    　請求項１７に記載の不揮発性記憶素子の製造方法。     The step of forming the stacked body further includes a step of forming a first electrode electrically connected to the plug via the alteration preventing layer, and a step of forming the resistance change layer on the first electrode. And forming a second electrode on the variable resistance layer,
    The method for manufacturing a nonvolatile memory element according to claim 17, wherein in the step of forming the second wiring, the second wiring electrically connected to the second electrode is formed.
  19. 　前記変質防止層を形成する工程では、前記プラグに電気的に接続される第１電極として機能する前記変質防止層を形成し、
    　前記積層体を形成する工程では、前記変質防止層上に前記抵抗変化層を形成する工程と、前記抵抗変化層上に第２電極を形成する工程と、を含み、
    　前記第２の配線を形成する工程では、前記第２電極と電気的に接続される前記第２の配線を形成する
    　請求項１７に記載の不揮発性記憶素子の製造方法。     In the step of forming the alteration preventing layer, the alteration preventing layer functioning as a first electrode electrically connected to the plug is formed,
    The step of forming the laminate includes a step of forming the resistance change layer on the alteration preventing layer, and a step of forming a second electrode on the resistance change layer,
    The method for manufacturing a nonvolatile memory element according to claim 17, wherein in the step of forming the second wiring, the second wiring electrically connected to the second electrode is formed.
  20. 　前記変質防止層を形成する工程では、前記プラグの上面の全域を窒化することにより前記変質防止層を形成する
    　請求項１７～１９のいずれか１項に記載の不揮発性記憶素子の製造方法。     The method for manufacturing a nonvolatile memory element according to any one of claims 17 to 19, wherein, in the step of forming the alteration preventing layer, the alteration preventing layer is formed by nitriding the entire upper surface of the plug.
  21. 　前記変質防止層を形成する工程では、無電解めっきによって前記変質防止層を形成する
    　請求項１７～１９のいずれか１項に記載の不揮発性記憶素子の製造方法。     The method for manufacturing a nonvolatile memory element according to any one of claims 17 to 19, wherein in the step of forming the alteration preventing layer, the alteration preventing layer is formed by electroless plating.
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