WO2013042504A1 - Substrate having buffer layer structure for growing nitride semiconductor layer - Google Patents

Substrate having buffer layer structure for growing nitride semiconductor layer Download PDF

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WO2013042504A1
WO2013042504A1 PCT/JP2012/071170 JP2012071170W WO2013042504A1 WO 2013042504 A1 WO2013042504 A1 WO 2013042504A1 JP 2012071170 W JP2012071170 W JP 2012071170W WO 2013042504 A1 WO2013042504 A1 WO 2013042504A1
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layer
substrate
buffer layer
aln
nitride semiconductor
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Japanese (ja)
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伸之 伊藤
信明 寺口
大輔 本田
暢行 布袋田
雅和 松林
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シャープ株式会社
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning

Definitions

  • the present invention relates to improvement of a substrate having a buffer layer structure for growing a nitride semiconductor layer, and more particularly to improvement of a buffer layer structure of the substrate.
  • An epitaxial wafer including a plurality of nitride semiconductor layers stacked on such an improved substrate can be preferably used for manufacturing a nitride semiconductor device such as a heterojunction field effect transistor.
  • a GaN substrate is expensive, so that it is on a substrate of a different material such as sapphire, SiC, or Si Conventionally, these nitride semiconductor layers have been crystal-grown.
  • a nitride semiconductor layer is grown by MOCVD (Metal Organic Vapor Deposition) on a substrate of a different material, strain based on the difference in crystal structure, lattice mismatch, thermal expansion coefficient, etc. between the substrate and the semiconductor layer Various buffer layer structures are used for relaxation.
  • MOCVD Metal Organic Vapor Deposition
  • Japanese Patent Laid-Open No. 2-229476 of Patent Document 1 teaches that an AlN layer is deposited as a buffer layer on a sapphire substrate at a relatively low substrate temperature of 400 ° C. or higher and 900 ° C. or lower.
  • Such a buffer layer deposited at a relatively low temperature is also called a low-temperature buffer layer.
  • the low-temperature buffer layer contains microcrystals and polycrystals in the amorphous matrix. Therefore, when the substrate temperature is increased to about 1000 ° C. or higher in order to grow a nitride semiconductor layer for a semiconductor device on the low-temperature buffer layer, the amorphous parent phase in the buffer layer is polycrystallized. It will contain a relatively large amount of dislocations inside. In the nitride semiconductor multilayer structure for devices grown on the buffer layer, a large amount of dislocations are introduced, the crystal quality varies, and cracks tend to occur.
  • Japanese Patent Application Laid-Open No. 2002-367917 of Patent Document 2 teaches that an AlN crystal layer is deposited on a sapphire substrate as a buffer layer at a relatively high substrate temperature of 1100 ° C. or more and 1250 ° C. or less.
  • a buffer layer deposited at a relatively high temperature is also referred to as a high temperature buffer layer.
  • Patent Document 3 also states that if the thickness of the buffer layer is increased, the substrate is likely to warp due to the difference in lattice constant between the substrate and the buffer layer, and the deposition temperature of the AlN buffer layer is further increased. It also states that if the height is increased, the surface of the buffer layer is more likely to become cloudy. In view of such a problem, Patent Document 3 discloses that the temperature during the deposition of the high-temperature AlN buffer layer in order to suppress the occurrence of white turbidity even if the high-temperature AlN buffer layer is formed thin on the sapphire substrate, It teaches changing at least one of the MOCVD conditions such as pressure and source gas flow rate.
  • Patent Document 4 points out problems in growing a nitride semiconductor crystal layer on a single crystal silicon substrate. Specifically, when a nitride semiconductor crystal layer is grown after depositing a nitride low-temperature buffer layer on a silicon substrate, amorphous silicon nitride is formed on random regions of the silicon substrate surface during the deposition of the nitride low-temperature buffer layer. It has been pointed out that this causes deterioration in the flatness of the interface between the substrate and the nitride semiconductor crystal layer, or causes defects in the nitride semiconductor crystal layer. In order to improve this problem, Patent Document 4 proposes that the silicon substrate surface is covered with a silicon nitride layer having a uniform thickness by nitriding before the nitride low-temperature buffer layer is deposited.
  • JP-A-2-229476 Japanese Patent Laid-Open No. 2002-367917 JP 2007-59850 A JP 2009-152627 A
  • An AlN crystal having a hexagonal wurtzite structure is a polar crystal in which Al atoms and N atoms are arranged asymmetrically along the c-axis.
  • Al polarity group III element polarity
  • N polarity in which N atoms exist stably Grows in any orientation of (group V element polarity).
  • This difference in polarity appears characteristically in the morphology of the crystal growth surface, while the Al polar surface is a highly flat surface, whereas the N polar surface is a remarkably uneven surface having hexagonal facets. Tend to be.
  • the AlN crystal layer is grown as a buffer layer without considering the polar face as in Patent Document 3, the surface of the AlN crystal layer in which the Al polar face and the N polar face are mixed is generated, and high surface flatness is obtained. I can't get it.
  • the mixture of the Al polar face and the N polar face is inherited into the nitride semiconductor multilayer structure for devices grown on the AlN buffer layer, and further deteriorates the surface flatness of the semiconductor multilayer structure.
  • the main object of the present invention is to provide a substrate having an improved buffer layer structure for growing a semiconductor laminated structure for a nitride semiconductor device.
  • the present inventors have not formed a high-temperature AlN buffer layer directly on the surface of the silicon nitride layer formed on the silicon substrate, but rather a conventional high-temperature by interposing an Al layer. It has been found that a novel buffer layer structure with a significantly improved surface flatness compared to the AlN buffer layer can be obtained.
  • a substrate having a buffer layer structure for growing a nitride semiconductor layer has a silicon nitride layer formed on the (111) main surface of the Si single crystal substrate, and on the silicon nitride layer. It has an Al layer and an AlN crystal layer or an AlGaN crystal layer that are sequentially stacked, and the surface of the AlN crystal layer or the AlGaN crystal layer has a (0001) plane orientation and a group III element polar surface. It is a feature.
  • the substrate according to the present invention may further include an additional AlGaN crystal layer stacked on the AlN crystal layer or the AlGaN layer.
  • the additional AlGaN crystal layer may include a plurality of sub-layers in which the Al composition ratio is sequentially reduced.
  • the AlN or AlGaN crystal buffer layer is uniformly formed on the silicon nitride layer before the AlN or AlGaN crystal buffer layer is grown.
  • a family polar face is obtained. That is, the surface of the AlN or AlGaN crystal buffer layer substantially includes only the group III polar surface, and thus has high flatness.
  • FIG. 5 is a Nomarski optical micrograph for showing the surface state of a nitride semiconductor device wafer produced using a substrate according to the production method of the present invention in comparison with FIG. 4.
  • FIG. 1 is a schematic cross-sectional view showing an example of a laminated structure of heterojunction field effect transistors that can be manufactured using a substrate according to the present invention.
  • a Si substrate having a (111) main surface is used as the substrate 1.
  • the substrate is set in a nitrogen atmosphere chamber of an MOCVD (metal organic chemical vapor deposition) apparatus.
  • MOCVD metal organic chemical vapor deposition
  • a silicon nitride layer 1 a is formed on the surface of the Si substrate 1.
  • An Al 0.7 Ga 0.3 N layer 3 is deposited to a thickness of 400 nm.
  • the deposition pressure is low, carbon contained in TMG is easily doped into the GaN layer, and when the deposition pressure is high, carbon tends to be hardly doped from TMG into the GaN layer.
  • the pressure is again increased to 13.3 kPa, and the AlN characteristic improving layer 8 (1 nm thickness), the Al 0.2 Ga 0.8 N barrier layer 9 (25 nm thickness), and the GaN cap.
  • An electron supply layer including layer 10 (1 nm thick) is deposited.
  • the Al composition ratio of the AlGaN layers 3, 4 and 5 was changed in the order of 0.7, 0.4 and 0.1.
  • the combination of composition ratios is not limited to this combination.
  • the number of AlGaN layers included in the composition gradient buffer layer structure and having different Al composition ratios is not limited to three, and can be any number. What is important is that the Al composition ratio gradually decreases from the lower surface to the upper surface of the composition gradient buffer layer structure.
  • a substrate as a comparative example was fabricated using the prior art.
  • the substrate of this comparative example has the AlN crystal buffer layer 2b and the composition gradient buffer layer structure 3-5 on the silicon nitride layer 1a of the Si substrate 1 in FIG. 1, but does not have the Al layer 2a. .
  • the AlN crystal buffer layer 2a is formed on the silicon nitride layer 1a obtained by nitriding the surface of the Si substrate 1 as in the above-described embodiment.
  • a plurality of nitride semiconductor layers 3-10 were stacked on the AlN crystal buffer layer 2a in the same manner as in the above-described embodiment, thereby obtaining an epitaxial wafer for nitride semiconductor devices.
  • FIG. 2 shows a Nomarski optical microscope photograph on the top surface of the epitaxial wafer of the comparative example thus obtained.
  • the white line segment in this micrograph has shown the scale of 200 micrometers.
  • the surface of the epitaxial wafer manufactured using the substrate of the comparative example includes many fine convex defects.
  • an epitaxial wafer including a substrate according to an embodiment of the present invention includes an Al layer 2a and an AlN crystal buffer layer on the silicon nitride layer 1a of the Si substrate 1 as described with reference to FIG. 2b was produced.
  • FIG. 3 shows a Nomarski optical micrograph on the top surface of the epitaxial wafer of the example obtained in this way.
  • the white line segment in this micrograph also shows a scale of 200 ⁇ m.
  • FIG. 3 shows the surface of the epitaxial wafer for nitride semiconductor devices manufactured using the substrate of the present invention, convex defects as observed in FIG. It turns out that it has disappeared. That is, it is understood that the surface of the epitaxial wafer for nitride semiconductor devices manufactured using the substrate of the present invention has significantly improved flatness and can be preferably used for manufacturing semiconductor devices.
  • the surface of the epitaxial wafer for nitride semiconductor devices manufactured using the substrate of the present invention has significantly improved flatness and can be preferably used for manufacturing semiconductor devices.
  • FIG. 4 is a Nomarski optical micrograph showing a magnified part of the region other than the convex defect in FIG. 2, and the white line segment in this photo shows a scale of 10 ⁇ m. Although it is a little difficult to see in the photograph of FIG. 4 attached here, a rough surface background like an orange peel can be observed in the original photograph.
  • FIG. 5 is an enlarged micrograph showing a partial region of FIG. 3, and the white line segment in this photograph also shows a scale of 10 ⁇ m as in FIG.
  • FIG. 5 it can be seen that even when the image of FIG. 3 is enlarged, the contrast indicating the orange peel-like rough surface as in FIG. 4 is not observed, and the surface is extremely smooth.
  • the surface smoothness of the AlN crystal buffer layer is remarkably improved by covering the silicon nitride layer with the Al layer before growing the AlN crystal buffer layer on the silicon nitride layer on the Si substrate surface.
  • the smoothness of the surface of the nitride semiconductor layer grown on the AlN crystal buffer layer can also be improved.
  • the reason for this is that the silicon nitride layer is covered with an Al layer, so that the AlN crystal buffer layer grown thereon has a uniform Al polar face, thereby improving the surface flatness. It is thought that.
  • the example in which the AlN crystal buffer layer is deposited on the Al layer has been described. However, the same effect can be obtained by depositing the AlGaN crystal buffer layer instead of the AlN crystal buffer layer. It is done.
  • the example in which the silicon nitride layer 1a is formed by nitriding the silicon substrate 1 has been described. However, in some cases, the silicon nitride layer is utilized by using another method such as MOCVD or sputtering. It is also possible to form 1a.
  • the AlN or AlGaN crystal buffer layer is grown on the silicon nitride layer formed on the Si substrate by covering the silicon nitride layer with the Al layer, thereby forming the AlN layer.
  • the smoothness of the surface of the AlGaN crystal buffer layer can be remarkably improved, and as a result, the smoothness of the surface of the nitride semiconductor layer grown on the AlN or AlGaN crystal buffer layer can also be improved. .

Abstract

This substrate having a buffer structure for growing a nitride semiconductor layer has a silicon nitride layer (1a) formed on the (111) main surface of an Si single-crystal substrate (1) and further has both an Al layer (2a) and an AlN or AlGaN crystal layer (2b) which are successively laminated on the silicon nitride layer (1a), said AlN or AlGaN crystal layer (2b) having a (0001) group III element polar surface.

Description

窒化物半導体層を成長させるためのバッファ層構造を有する基板Substrate having a buffer layer structure for growing a nitride semiconductor layer
　本発明は、窒化物半導体層を成長させるためのバッファ層構造を有する基板の改善に関し、特にその基板が有するバッファ層構造の改善に関する。そのように改善された基板上に積層された複数の窒化物半導体層を含むエピタキシャルウエハは、例えばヘテロ接合電界効果トランジスタのような窒化物半導体デバイスの作製に好ましく利用され得るものである。 The present invention relates to improvement of a substrate having a buffer layer structure for growing a nitride semiconductor layer, and more particularly to improvement of a buffer layer structure of the substrate. An epitaxial wafer including a plurality of nitride semiconductor layers stacked on such an improved substrate can be preferably used for manufacturing a nitride semiconductor device such as a heterojunction field effect transistor.
　ヘテロ接合電界効果トランジスタに必要な例えばＧａＮチャネル層とＡｌＧａＮ障壁層との積層構造を含むエピタキシャルウエハを作製する場合、ＧａＮ基板が高価であることから、サファイア、ＳｉＣ、Ｓｉなどの異種材料の基板上にそれらの窒化物半導体層を結晶成長させることが従来から行なわれている。 When an epitaxial wafer including a laminated structure of, for example, a GaN channel layer and an AlGaN barrier layer required for a heterojunction field effect transistor is manufactured, a GaN substrate is expensive, so that it is on a substrate of a different material such as sapphire, SiC, or Si Conventionally, these nitride semiconductor layers have been crystal-grown.
　異種材料の基板上に窒化物半導体層をＭＯＣＶＤ（有機金属気相堆積）で成長させる場合、基板と半導体層との間における結晶構造の相違、格子不整合、熱膨張係数差などに基づく歪を緩和するために、種々のバッファ層構造が用いられている。 When a nitride semiconductor layer is grown by MOCVD (Metal Organic Vapor Deposition) on a substrate of a different material, strain based on the difference in crystal structure, lattice mismatch, thermal expansion coefficient, etc. between the substrate and the semiconductor layer Various buffer layer structures are used for relaxation.
　例えば特許文献１の特開平２－２２９４７６号公報は、サファイア基材上に４００℃以上９００℃以下の比較的低い基板温度でＡｌＮ層をバッファ層として堆積させることを教示している。このように比較的低温で堆積されたバッファ層は、低温バッファ層とも呼ばれる。 For example, Japanese Patent Laid-Open No. 2-229476 of Patent Document 1 teaches that an AlN layer is deposited as a buffer layer on a sapphire substrate at a relatively low substrate temperature of 400 ° C. or higher and 900 ° C. or lower. Such a buffer layer deposited at a relatively low temperature is also called a low-temperature buffer layer.
　しかし、低温バッファ層は、非晶質の母相中に微結晶や多結晶を含んでいる。したがって、半導体デバイス用の窒化物半導体層を低温バッファ層上に結晶成長させるために基板温度を１０００℃程度以上まで上昇させたとき、そのバッファ層内の非晶質の母相が多結晶化して内部に比較的多量の転位を含むことになる。そして、そのバッファ層上に成長させたデバイス用の窒化物半導体積層構造において、多量の転位が導入されると共に、結晶品質がばらついて、クラックが入りやすくなる傾向がある。 However, the low-temperature buffer layer contains microcrystals and polycrystals in the amorphous matrix. Therefore, when the substrate temperature is increased to about 1000 ° C. or higher in order to grow a nitride semiconductor layer for a semiconductor device on the low-temperature buffer layer, the amorphous parent phase in the buffer layer is polycrystallized. It will contain a relatively large amount of dislocations inside. In the nitride semiconductor multilayer structure for devices grown on the buffer layer, a large amount of dislocations are introduced, the crystal quality varies, and cracks tend to occur.
　他方、例えば特許文献２の特開２００２－３６７９１７号公報は、サファイア基板上に１１００℃以上１２５０℃以下の比較的高い基板温度でＡｌＮ結晶層をバッファ層として堆積させることを教示している。このように比較的高温で堆積されたバッファ層は、高温バッファ層とも呼ばれる。 On the other hand, for example, Japanese Patent Application Laid-Open No. 2002-367917 of Patent Document 2 teaches that an AlN crystal layer is deposited on a sapphire substrate as a buffer layer at a relatively high substrate temperature of 1100 ° C. or more and 1250 ° C. or less. Such a buffer layer deposited at a relatively high temperature is also referred to as a high temperature buffer layer.
　しかし、特許文献３の特開２００７－５９８５０号公報は、高温バッファ層上に成長させた窒化物半導体積層構造においてはクラックが発生しにくくなるが、そのバッファ層の表面において原子レベルでの平坦性を確保するためには、バッファ層の厚さを大きくしなければならないと述べている。実際に、特許文献２は、その発明の実施例において高温ＡｌＮバッファ層をかなり大きな２μｍの厚さに堆積することを教示している。特許文献３はまた、バッファ層の厚さを大きくすれば基板とバッファ層との格子定数差に起因して基板に反りが発生しやすくなることも述べており、さらにＡｌＮバッファ層の堆積温度を高くすればそのバッファ層の表面に白濁が発生しやすくなることも述べている。このような問題に鑑み、特許文献３は、サファイア基板上に高温ＡｌＮバッファ層を薄く形成してもその表面に白濁が生じることを抑制するために、高温ＡｌＮバッファ層の堆積の途中で温度、圧力、原料ガス流量などのＭＯＣＶＤ条件の少なくともいずれかを変化させることを教示している。 However, in Japanese Patent Application Laid-Open No. 2007-59850 of Patent Document 3, cracks are less likely to occur in a nitride semiconductor multilayer structure grown on a high-temperature buffer layer, but flatness at the atomic level on the surface of the buffer layer. In order to ensure this, it is stated that the thickness of the buffer layer must be increased. In fact, U.S. Patent No. 6,057,031 teaches that in the embodiment of the invention, a high temperature AlN buffer layer is deposited to a fairly large 2 .mu.m thickness. Patent Document 3 also states that if the thickness of the buffer layer is increased, the substrate is likely to warp due to the difference in lattice constant between the substrate and the buffer layer, and the deposition temperature of the AlN buffer layer is further increased. It also states that if the height is increased, the surface of the buffer layer is more likely to become cloudy. In view of such a problem, Patent Document 3 discloses that the temperature during the deposition of the high-temperature AlN buffer layer in order to suppress the occurrence of white turbidity even if the high-temperature AlN buffer layer is formed thin on the sapphire substrate, It teaches changing at least one of the MOCVD conditions such as pressure and source gas flow rate.
　一方、特許文献４の特開２００９－１５２６２７号公報は、単結晶シリコン基板上に窒化物半導体結晶層を成長させる場合の問題点を指摘している。具体的には、シリコン基板上に窒化物低温バッファ層を堆積してから窒化物半導体結晶層を成長させる場合、窒化物低温バッファ層の堆積時にシリコン基板表面のランダムな領域に非晶質窒化ケイ素を生じ、これが基板と窒化物半導体結晶層との界面の平坦度を悪化させたり、窒化物半導体結晶層に欠陥を生じさせる原因となると指摘している。そして、この問題を改善するために、特許文献４は窒化物低温バッファ層の堆積前にシリコン基板表面を窒化処理によって均一厚さの窒化ケイ素層で覆うことを提案している。 On the other hand, Japanese Patent Application Laid-Open No. 2009-152627 of Patent Document 4 points out problems in growing a nitride semiconductor crystal layer on a single crystal silicon substrate. Specifically, when a nitride semiconductor crystal layer is grown after depositing a nitride low-temperature buffer layer on a silicon substrate, amorphous silicon nitride is formed on random regions of the silicon substrate surface during the deposition of the nitride low-temperature buffer layer. It has been pointed out that this causes deterioration in the flatness of the interface between the substrate and the nitride semiconductor crystal layer, or causes defects in the nitride semiconductor crystal layer. In order to improve this problem, Patent Document 4 proposes that the silicon substrate surface is covered with a silicon nitride layer having a uniform thickness by nitriding before the nitride low-temperature buffer layer is deposited.
特開平２－２２９４７６号公報JP-A-2-229476 特開２００２－３６７９１７号公報Japanese Patent Laid-Open No. 2002-367917 特開２００７－５９８５０号公報JP 2007-59850 A 特開２００９－１５２６２７号公報JP 2009-152627 A
　六方晶系のウルツ鉱型構造を有するＡｌＮ結晶は、ｃ軸に沿ってＡｌ原子とＮ原子が非対称に配列した極性結晶である。無極性の基板上にＡｌＮ結晶層の厚さをｃ軸方向に成長させる場合、表面にＡｌ原子が安定して存在するＡｌ極性（III族元素極性）とＮ原子が安定して存在するＮ極性（Ｖ族元素極性）のいずれかの方位で成長する。このような極性の相違は結晶成長表面のモフォロジーに特徴的に表れ、Ａｌ極性面は平坦性の高い表面であるのに対して、Ｎ極性面は六角形状のファセットを有する凹凸の顕著な表面になる傾向にある。 An AlN crystal having a hexagonal wurtzite structure is a polar crystal in which Al atoms and N atoms are arranged asymmetrically along the c-axis. When the thickness of the AlN crystal layer is grown in the c-axis direction on a nonpolar substrate, Al polarity (group III element polarity) in which Al atoms exist stably on the surface and N polarity in which N atoms exist stably Grows in any orientation of (group V element polarity). This difference in polarity appears characteristically in the morphology of the crystal growth surface, while the Al polar surface is a highly flat surface, whereas the N polar surface is a remarkably uneven surface having hexagonal facets. Tend to be.
　したがって、特許文献３におけるように極性面を考慮せずにＡｌＮ結晶層をバッファ層として成長させれば、Ａｌ極性面とＮ極性面が混在したＡｌＮ結晶層の表面を生じ、高い表面平坦性が得られない。そして、そのＡｌ極性面とＮ極性面の混在は、ＡｌＮバッファ層上に成長させられるデバイス用窒化物半導体積層構造内まで引き継がれ、半導体積層構造のさらなる表面平坦性の悪化を招く。 Therefore, if the AlN crystal layer is grown as a buffer layer without considering the polar face as in Patent Document 3, the surface of the AlN crystal layer in which the Al polar face and the N polar face are mixed is generated, and high surface flatness is obtained. I can't get it. The mixture of the Al polar face and the N polar face is inherited into the nitride semiconductor multilayer structure for devices grown on the AlN buffer layer, and further deteriorates the surface flatness of the semiconductor multilayer structure.
　また、特許文献４におけるようにＳｉ基板表面を窒化処理した窒化ケイ素層上にＡｌＮ結晶バッファ層を成長させる場合にも、Ａｌ極性面とＮ極性面の混在したＡｌＮ結晶バッファ層が成長しやすい傾向にある。 In addition, when an AlN crystal buffer layer is grown on a silicon nitride layer obtained by nitriding the Si substrate surface as in Patent Document 4, an AlN crystal buffer layer having a mixture of Al polar faces and N polar faces tends to grow. It is in.
　上述のような課題に鑑み、本願発明は、窒化物半導体デバイス用の半導体積層構造を成長させるために改善されたバッファ層構造を有する基板を提供することを主要な目的としている。 In view of the problems as described above, the main object of the present invention is to provide a substrate having an improved buffer layer structure for growing a semiconductor laminated structure for a nitride semiconductor device.
　本発明者達は、鋭意検討を重ねた結果、シリコン基板に形成された窒化ケイ素層の表面上に直接に高温ＡｌＮバッファ層を形成するのではなくて、Ａｌ層を介在させることによって従来の高温ＡｌＮバッファ層に比べて表面平坦性が顕著に改善された新規なバッファ層構造が得られることを見出すに至った。 As a result of extensive studies, the present inventors have not formed a high-temperature AlN buffer layer directly on the surface of the silicon nitride layer formed on the silicon substrate, but rather a conventional high-temperature by interposing an Al layer. It has been found that a novel buffer layer structure with a significantly improved surface flatness compared to the AlN buffer layer can be obtained.
　本発明によれば、窒化物半導体層を成長させるためのバッファ層構造を有する基板は、Ｓｉ単結晶基板の（１１１）主面に形成された窒化ケイ素層を有し、この窒化ケイ素層上に順次積層されたＡｌ層とＡｌＮ結晶層またはＡｌＧａＮ結晶層とを有し、このＡｌＮ結晶層またはＡｌＧａＮ結晶層の表面は（０００１）の面方位とIII族元素極性の表面を有していることを特徴としている。 According to the present invention, a substrate having a buffer layer structure for growing a nitride semiconductor layer has a silicon nitride layer formed on the (111) main surface of the Si single crystal substrate, and on the silicon nitride layer. It has an Al layer and an AlN crystal layer or an AlGaN crystal layer that are sequentially stacked, and the surface of the AlN crystal layer or the AlGaN crystal layer has a (0001) plane orientation and a group III element polar surface. It is a feature.
　なお、本発明による基板は、ＡｌＮ結晶層またはＡｌＧａＮ層上に積層された付加的なＡｌＧａＮ結晶層をさらに有してもよい。この付加的なＡｌＧａＮ結晶層は、Ａｌ組成比が順次低減された複数のサブ層を含むこともできる。 The substrate according to the present invention may further include an additional AlGaN crystal layer stacked on the AlN crystal layer or the AlGaN layer. The additional AlGaN crystal layer may include a plurality of sub-layers in which the Al composition ratio is sequentially reduced.
　上記のような本発明によれば、ＡｌＮまたはＡｌＧａＮの結晶バッファ層を成長させる前に窒化ケイ素層上にＡｌ層を均一に形成することによって、ＡｌＮまたはＡｌＧａＮの結晶バッファ層の表面に良質なIII族極性面が得られる。すなわち、そのＡｌＮまたはＡｌＧａＮの結晶バッファ層の表面は、実質的にIII族極性面のみを含んでいるので、高い平坦性を有している。 According to the present invention as described above, the AlN or AlGaN crystal buffer layer is uniformly formed on the silicon nitride layer before the AlN or AlGaN crystal buffer layer is grown. A family polar face is obtained. That is, the surface of the AlN or AlGaN crystal buffer layer substantially includes only the group III polar surface, and thus has high flatness.
本発明による基板を用いて作製し得るヘテロ接合電界効果トランジスタの積層構造の一例を示す模式的断面図である。It is typical sectional drawing which shows an example of the laminated structure of the heterojunction field effect transistor which can be produced using the board | substrate by this invention. 従来技術を利用して形成された基板を用いて作製された窒化物半導体デバイス用ウエハの表面における微小な凸状欠陥の分布を示すノマルスキー光学顕微鏡写真である。It is a Nomarski optical microscope photograph which shows distribution of the micro convex defect in the surface of the wafer for nitride semiconductor devices produced using the board | substrate formed using the prior art. 本発明の製造方法による基板を用いて作製された窒化物半導体デバイス用ウエハの表面状態を示すノマルスキー光学顕微鏡写真である。It is a Nomarski optical microscope photograph which shows the surface state of the wafer for nitride semiconductor devices produced using the board | substrate by the manufacturing method of this invention. 従来技術を利用して形成された基板を用いて作製された窒化物半導体デバイス用ウエハの表面における凸状欠陥以外の領域の状態を拡大して示すノマルスキー光学顕微鏡写真である。It is a Nomarski optical micrograph which expands and shows the state of the area | regions other than a convex defect in the surface of the wafer for nitride semiconductor devices produced using the board | substrate formed using the prior art. 本発明の製造方法による基板を用いて作製された窒化物半導体デバイス用ウエハの表面状態を図４と対比して示すためのノマルスキー光学顕微鏡写真である。FIG. 5 is a Nomarski optical micrograph for showing the surface state of a nitride semiconductor device wafer produced using a substrate according to the production method of the present invention in comparison with FIG. 4.
　（実施形態）
　図１は、本発明による基板を用いて作製し得るヘテロ接合電界効果トランジスタの積層構造の一例を模式的断面図で示している。このようなヘテロ接合電界効果トランジスタの積層構造の作製方法の一例が、以下において説明される。基板１としては、（１１１）主面を有するＳｉ基板が用いられる。まず、フッ酸系のエッチャントでＳｉ基板１の表面酸化膜を除去した後に、ＭＯＣＶＤ（有機金属気相堆積）装置の窒素雰囲気のチャンバ内にその基板がセットされる。 (Embodiment)
FIG. 1 is a schematic cross-sectional view showing an example of a laminated structure of heterojunction field effect transistors that can be manufactured using a substrate according to the present invention. An example of a method for manufacturing such a stacked structure of heterojunction field effect transistors will be described below. As the substrate 1, a Si substrate having a (111) main surface is used. First, after removing the surface oxide film of the Si substrate 1 with a hydrofluoric acid-based etchant, the substrate is set in a nitrogen atmosphere chamber of an MOCVD (metal organic chemical vapor deposition) apparatus.
　基板１がセットされた後には、チャンバ内の窒素雰囲気が水素雰囲気に入れ替えられる。そして、チャンバ内圧力１３．３ｋＰａの下で、Ｈ２流量＝５０ｓｌｍと基板温度１１００℃の条件にてＳｉ基板１の表面の熱クリーニングが行なわれる。 After the substrate 1 is set, the nitrogen atmosphere in the chamber is replaced with a hydrogen atmosphere. Then, thermal cleaning of the surface of the Si substrate 1 is performed under the conditions of an H 2 flow rate = 50 slm and a substrate temperature of 1100 ° C. under a chamber internal pressure of 13.3 kPa.
　その後、チャンバ内圧力と基板温度を維持したまま、ＮＨ３流量＝１２．５ｓｌｍとＨ２流量＝３７．５ｓｌｍの条件下でＳｉ基板１の表面が４０秒間窒化処理される。これによって、Ｓｉ基板１の表面に窒化ケイ素層１ａが形成される。 Thereafter, the surface of the Si substrate 1 is nitrided for 40 seconds under the conditions of NH 3 flow rate = 12.5 slm and H 2 flow rate = 37.5 slm while maintaining the chamber pressure and the substrate temperature. As a result, a silicon nitride layer 1 a is formed on the surface of the Si substrate 1.
　引続いて、ＮＨ３の供給を停止し、Ｈ２流量＝５０ｓｌｍとＴＭＡ（トリメチルアルミニウム）流量＝５４ｓｃｃｍの条件下でＡｌ層を６秒間堆積させる。これによって、Ｓｉ基板１の窒化ケイ素層１ａの表面が、Ａｌ層２ａによって覆われる。 Subsequently, the supply of NH 3 is stopped, and an Al layer is deposited for 6 seconds under the conditions of H 2 flow rate = 50 slm and TMA (trimethylaluminum) flow rate = 54 sccm. Thereby, the surface of the silicon nitride layer 1a of the Si substrate 1 is covered with the Al layer 2a.
　さらに、ＴＭＡ流量＝１０８．５ｓｃｃｍ、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で、Ａｌ層２ａ上に厚さ２００ｎｍのＡｌＮ層２ｂを堆積させる。 Furthermore, an AlN layer 2b having a thickness of 200 nm is deposited on the Al layer 2a under the conditions of a TMA flow rate = 108.5 sccm, an NH 3 flow rate = 12.5 slm, and an H 2 flow rate = 37.5 slm.
　その後、基板温度を１１５０℃に上昇させ、ＴＭＡ流量＝９０．０ｓｃｃｍ、ＴＭＧ（トリメチルガリウム）流量＝１２．７ｓｃｃｍ、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で、Ａｌ０．７Ｇａ０．３Ｎ層３が４００ｎｍの厚さに堆積される。続いて、ＴＭＡ流量＝５０．９ｓｃｃｍ、ＴＭＧ流量＝２２．１ｓｃｃｍ、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で、Ａｌ０．４Ｇａ０．６Ｎ層４が４００ｎｍの厚さに堆積され、さらにＴＭＡ流量＝１６．４ｓｃｃｍ、ＴＭＧ流量＝３０．４、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で、Ａｌ０．１Ｇａ０．９Ｎ層５が４００ｎｍの厚さに堆積される。これによって、組成傾斜バッファ層構造３－５が形成される。 Thereafter, the substrate temperature is raised to 1150 ° C., under the conditions of TMA flow rate = 90.0 sccm, TMG (trimethylgallium) flow rate = 12.7 sccm, NH 3 flow rate = 12.5 slm, and H 2 flow rate = 37.5 slm, An Al 0.7 Ga 0.3 N layer 3 is deposited to a thickness of 400 nm. Subsequently, the Al 0.4 Ga 0.6 N layer 4 was formed under the conditions of TMA flow rate = 50.9 sccm, TMG flow rate = 22.1 sccm, NH 3 flow rate = 12.5 slm, and H 2 flow rate = 37.5 slm. Al 0.1 Ga 0 deposited at a thickness of 400 nm and further under conditions of TMA flow rate = 16.4 sccm, TMG flow rate = 30.4, NH 3 flow rate = 12.5 slm, and H 2 flow rate = 37.5 slm. .9 N layer 5 is deposited to a thickness of 400 nm. Thereby, the composition gradient buffer layer structure 3-5 is formed.
　その後、１３．３ｋＰａの圧力と１１５０℃の基板温度を維持したままで、ＴＭＧ流量＝４９．８ｓｃｃｍ、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で、ＧａＮ層６が３００ｎｍの厚さに堆積される。続いて、ＧａＮ層６の堆積条件から圧力のみが９０ｋＰａに下げられ、ＧａＮ層７が７００ｎｍの厚さに堆積される。ここで、堆積圧力が低い場合にはＴＭＧに含まれるカーボンがＧａＮ層内にドープされやすく、堆積圧力が高い場合にはＴＭＧからＧａＮ層内にカーボンがドープされにくい傾向にある。 Thereafter, while maintaining the pressure of 13.3 kPa and the substrate temperature of 1150 ° C., the GaN layer 6 under the conditions of TMG flow rate = 49.8 sccm, NH 3 flow rate = 12.5 slm, and H 2 flow rate = 37.5 slm. Is deposited to a thickness of 300 nm. Subsequently, only the pressure is lowered to 90 kPa from the deposition condition of the GaN layer 6, and the GaN layer 7 is deposited to a thickness of 700 nm. Here, when the deposition pressure is low, carbon contained in TMG is easily doped into the GaN layer, and when the deposition pressure is high, carbon tends to be hardly doped from TMG into the GaN layer.
　そして、ＧａＮ層７の堆積後には、圧力が再度１３．３ｋＰａに上げられて、ＡｌＮ特性改善層８（１ｎｍ厚）、Ａｌ０．２Ｇａ０．８Ｎ障壁層９（２５ｎｍ厚）およびＧａＮキャップ層１０（１ｎｍ厚）を含む電子供給層が堆積される。このとき、ＡｌＮ層８はＴＭＡ流量＝４７ｓｃｃｍ、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で堆積され、ＡｌＧａＮ層９はＴＭＧ流量＝１０．２ｓｃｃｍ、ＴＭＡ流量＝６．２ｓｃｃｍ、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で堆積され、そしてＧａＮ層１０はＴＭＧ流量＝１３ｓｃｃｍ、ＮＨ３流量＝１２．５ｓｌｍ、およびＨ２流量＝３７．５ｓｌｍの条件下で堆積され得る。 After the GaN layer 7 is deposited, the pressure is again increased to 13.3 kPa, and the AlN characteristic improving layer 8 (1 nm thickness), the Al 0.2 Ga 0.8 N barrier layer 9 (25 nm thickness), and the GaN cap. An electron supply layer including layer 10 (1 nm thick) is deposited. At this time, the AlN layer 8 is deposited under the conditions of TMA flow rate = 47 sccm, NH 3 flow rate = 12.5 slm, and H 2 flow rate = 37.5 slm, and the AlGaN layer 9 is TMG flow rate = 10.2 sccm, TMA flow rate = 6. .2 sccm, NH 3 flow rate = 12.5 slm, and H 2 flow rate = 37.5 slm, and the GaN layer 10 is TMG flow rate = 13 sccm, NH 3 flow rate = 12.5 slm, and H 2 flow rate = 37. Can be deposited under conditions of .5 slm.
　なお、以上の実施形態ではＡｌＧａＮ層３、４および５のＡｌ組成比が０．７、０．４および０．１の順に変化させられたが、組成傾斜バッファ層構造に含まれるＡｌＧａＮ層におけるＡｌ組成比の組合せはこの組合せに限定されるものではない。また、組成傾斜バッファ層構造に含まれて異なるＡｌ組成比を有するＡｌＧａＮ層の数も３層に限定されず、任意の数とすることができる。重要なことは、組成傾斜バッファ層構造の下面から上面に向かうにしたがってＡｌ組成比が徐々に減少していくことである。 In the above embodiment, the Al composition ratio of the AlGaN layers 3, 4 and 5 was changed in the order of 0.7, 0.4 and 0.1. The combination of composition ratios is not limited to this combination. Also, the number of AlGaN layers included in the composition gradient buffer layer structure and having different Al composition ratios is not limited to three, and can be any number. What is important is that the Al composition ratio gradually decreases from the lower surface to the upper surface of the composition gradient buffer layer structure.
　（比較例と実施例）
　本発明の基板による改善効果を調べるために、従来技術を利用して比較例としての基板が作製された。この比較例の基板は、図１におけるＳｉ基板１の窒化ケイ素層１ａ上に、ＡｌＮ結晶バッファ層２ｂおよび組成傾斜バッファ層構造３－５を有しているが、Ａｌ層２ａを有していない。 (Comparative examples and examples)
In order to investigate the improvement effect of the substrate of the present invention, a substrate as a comparative example was fabricated using the prior art. The substrate of this comparative example has the AlN crystal buffer layer 2b and the composition gradient buffer layer structure 3-5 on the silicon nitride layer 1a of the Si substrate 1 in FIG. 1, but does not have the Al layer 2a. .
　すなわち、比較例においては、上述の実施形態と同様にＳｉ基板１の表面が窒化処理されたことによる窒化ケイ素層１ａ上に、ＡｌＮ結晶バッファ層２ａが、１１００℃の基板温度、１３．３ｋＰａの圧力、１０８．５ｓｃｃｍのＴＭＡ流量、１２．５ｓｌｍのＮＨ３、およびＨ２流量＝３７．５ｓｌｍのＭＯＣＶＤ条件下で２００ｎｍの厚さに成長させられた。その後、ＡｌＮ結晶バッファ層２ａ上に上述の実施形態と同様に複数の窒化物半導体層３－１０が積層され、これによって窒化物半導体デバイス用のエピタキシャルウエハを得た。 That is, in the comparative example, the AlN crystal buffer layer 2a is formed on the silicon nitride layer 1a obtained by nitriding the surface of the Si substrate 1 as in the above-described embodiment. The film was grown to a thickness of 200 nm under MOCVD conditions of pressure, 108.5 sccm TMA flow rate, 12.5 slm NH 3 , and H 2 flow rate = 37.5 slm. Thereafter, a plurality of nitride semiconductor layers 3-10 were stacked on the AlN crystal buffer layer 2a in the same manner as in the above-described embodiment, thereby obtaining an epitaxial wafer for nitride semiconductor devices.
　図２は、こうして得られた比較例のエピタキシャルウエハの最上面におけるノマルスキー光学顕微鏡写真を示している。なお、この顕微鏡写真中の白い線分は、２００μｍのスケールを示している。図２の写真から明らかなように、比較例の基板を利用して作製されたエピタキシャルウエハの表面は多くの微細な凸状欠陥を含んでいることが分かる。 FIG. 2 shows a Nomarski optical microscope photograph on the top surface of the epitaxial wafer of the comparative example thus obtained. In addition, the white line segment in this micrograph has shown the scale of 200 micrometers. As is apparent from the photograph of FIG. 2, it can be seen that the surface of the epitaxial wafer manufactured using the substrate of the comparative example includes many fine convex defects.
　他方、本発明の実施例による基板を含むエピタキシャルウエハは、上述の実施形態において図１を参照して説明されたように、Ｓｉ基板１の窒化ケイ素層１ａ上のＡｌ層２ａおよびＡｌＮ結晶バッファ層２ｂを含んで作製された。 On the other hand, an epitaxial wafer including a substrate according to an embodiment of the present invention includes an Al layer 2a and an AlN crystal buffer layer on the silicon nitride layer 1a of the Si substrate 1 as described with reference to FIG. 2b was produced.
　図３は、こうして得られた実施例のエピタキシャルウエハの最上面におけるノマルスキー光学顕微鏡写真を示している。この顕微鏡写真中の白い線分も、２００μｍのスケールを示している。図２と対比から明らかなように、本発明の基板を利用して作製された窒化物半導体デバイス用のエピタキシャルウエハの表面を示す図３においては、図２において観察されるような凸状欠陥が消失していることが分かる。すなわち、本発明の基板を利用して作製された窒化物半導体デバイス用のエピタキシャルウエハの表面は顕著に改善された平坦性を有しており、半導体デバイスの作製に好ましく用いられ得ることが理解されよう。 FIG. 3 shows a Nomarski optical micrograph on the top surface of the epitaxial wafer of the example obtained in this way. The white line segment in this micrograph also shows a scale of 200 μm. As is clear from comparison with FIG. 2, in FIG. 3 showing the surface of the epitaxial wafer for nitride semiconductor devices manufactured using the substrate of the present invention, convex defects as observed in FIG. It turns out that it has disappeared. That is, it is understood that the surface of the epitaxial wafer for nitride semiconductor devices manufactured using the substrate of the present invention has significantly improved flatness and can be preferably used for manufacturing semiconductor devices. Like.
　図４は図２における凸状欠陥以外の一部領域を拡大して示すノマルスキー光学顕微鏡写真であり、この写真中の白い線分は１０μｍのスケールを示している。ここに添付の図４の写真では少し見づらいが、原写真ではオレンジピールのように荒れた表面地肌が観察され得る。 FIG. 4 is a Nomarski optical micrograph showing a magnified part of the region other than the convex defect in FIG. 2, and the white line segment in this photo shows a scale of 10 μm. Although it is a little difficult to see in the photograph of FIG. 4 attached here, a rough surface background like an orange peel can be observed in the original photograph.
　他方、図５は図３一部領域を拡大して示す顕微鏡写真であり、この写真中の白い線分も図４と同様に１０μｍのスケールを示している。図５においては、図３を拡大して観察しても図４におけるようなオレンジピール状の肌荒れ表面を示すコントラストが観察されず、極めて平滑な表面を示していることが分かる。 On the other hand, FIG. 5 is an enlarged micrograph showing a partial region of FIG. 3, and the white line segment in this photograph also shows a scale of 10 μm as in FIG. In FIG. 5, it can be seen that even when the image of FIG. 3 is enlarged, the contrast indicating the orange peel-like rough surface as in FIG. 4 is not observed, and the surface is extremely smooth.
　以上のように、Ｓｉ基板表面の窒化ケイ素層上にＡｌＮ結晶バッファ層を成長させる前に窒化ケイ素層をＡｌ層で覆うことによって、そのＡｌＮ結晶バッファ層の表面の平滑性を顕著に改善することができ、その結果としてＡｌＮ結晶バッファ層上に成長する窒化物半導体層の表面の平滑性をも改善することができる。この理由としては、窒化ケイ素層がＡｌ層で覆われたことによって、その上に成長するＡｌＮ結晶バッファ層が均一なＡｌ極性面を有することとなって、それによって改善された表面平坦性が得られると考えられる。 As described above, the surface smoothness of the AlN crystal buffer layer is remarkably improved by covering the silicon nitride layer with the Al layer before growing the AlN crystal buffer layer on the silicon nitride layer on the Si substrate surface. As a result, the smoothness of the surface of the nitride semiconductor layer grown on the AlN crystal buffer layer can also be improved. The reason for this is that the silicon nitride layer is covered with an Al layer, so that the AlN crystal buffer layer grown thereon has a uniform Al polar face, thereby improving the surface flatness. It is thought that.
　なお、上述の実施形態および実施例においてはＡｌ層上にＡｌＮ結晶バッファ層を堆積する例について説明されたが、ＡｌＮ結晶バッファ層の代わりにＡｌＧａＮ結晶バッファ層を堆積しても同様な効果が得られる。また、上述の実施形態および実施例では窒化ケイ素層１ａがシリコン基板１の窒化処理で形成される例が説明されたが、場合によってはＭＯＣＶＤまたはスパッタリングなどの他の方法を利用して窒化ケイ素層１ａを形成することも可能である。 In the above-described embodiments and examples, the example in which the AlN crystal buffer layer is deposited on the Al layer has been described. However, the same effect can be obtained by depositing the AlGaN crystal buffer layer instead of the AlN crystal buffer layer. It is done. In the above-described embodiments and examples, the example in which the silicon nitride layer 1a is formed by nitriding the silicon substrate 1 has been described. However, in some cases, the silicon nitride layer is utilized by using another method such as MOCVD or sputtering. It is also possible to form 1a.
　以上から明らかなように、本発明によれば、Ｓｉ基板上に形成された窒化ケイ素層上にＡｌＮまたはＡｌＧａＮの結晶バッファ層を成長させる前に窒化ケイ素層をＡｌ層で覆うことによって、そのＡｌＮまたはＡｌＧａＮの結晶バッファ層の表面の平滑性を顕著に改善することができ、その結果としてＡｌＮまたはＡｌＧａＮの結晶バッファ層上に成長する窒化物半導体層の表面の平滑性をも改善することができる。 As is apparent from the above, according to the present invention, the AlN or AlGaN crystal buffer layer is grown on the silicon nitride layer formed on the Si substrate by covering the silicon nitride layer with the Al layer, thereby forming the AlN layer. Alternatively, the smoothness of the surface of the AlGaN crystal buffer layer can be remarkably improved, and as a result, the smoothness of the surface of the nitride semiconductor layer grown on the AlN or AlGaN crystal buffer layer can also be improved. .
　そして、そのように改善された表面平滑性を有する基板を利用することによって、その基板上に改善された特性を有する種々の窒化物半導体デバイスを作製することができる。 Then, by using a substrate having such improved surface smoothness, various nitride semiconductor devices having improved characteristics can be fabricated on the substrate.
　１　Ｓｉ基板、１ａ　窒化ケイ素層、２ａ　Ａｌ層、２ｂ　ＡｌＮ結晶層、３　Ａｌ０．７Ｇａ０．３Ｎ層、４　Ａｌ０．４Ｇａ０．６Ｎ層、５　Ａｌ０．１Ｇａ０．９Ｎ層、６　カーボンドープＧａＮ層、７　アンドープＧａＮチャネル層、８　ＡｌＮ特性改善層、９　Ａｌ０．２Ｇａ０．８Ｎ障壁層、１０　ＧａＮキャップ層。 1 Si substrate, 1a silicon nitride layer, 2a Al layer, 2b AlN crystal layer, 3 Al 0.7 Ga 0.3 N layer, 4 Al 0.4 Ga 0.6 N layer, 5 Al 0.1 Ga 0. 9 N layer, 6 carbon-doped GaN layer, 7 undoped GaN channel layer, 8 AlN characteristic improving layer, 9 Al 0.2 Ga 0.8 N barrier layer, 10 GaN cap layer.

Claims (3)

  1. 　窒化物半導体層を成長させるためのバッファ層構造を有する基板であって、
    　Ｓｉ単結晶基板（１）の（１１１）主面に形成された窒化ケイ素層（１ａ）を有し、
    　前記窒化ケイ素層上に順次積層されたＡｌ層（２ａ）とＡｌＮ結晶層またはＡｌＧａＮ結晶層（２ｂ）とを有し、
    　前記ＡｌＮ結晶層またはＡｌＧａＮ結晶層の表面は（０００１）の面方位とIII族元素極性の表面を有していることを特徴とする基板。     A substrate having a buffer layer structure for growing a nitride semiconductor layer,
    Having a silicon nitride layer (1a) formed on the (111) main surface of the Si single crystal substrate (1);
    An Al layer (2a) and an AlN crystal layer or an AlGaN crystal layer (2b) sequentially stacked on the silicon nitride layer;
    The substrate characterized in that the surface of the AlN crystal layer or AlGaN crystal layer has a surface of (0001) plane orientation and a group III element polarity.
  2. 　前記ＡｌＮ結晶層またはＡｌＧａＮ結晶層（２ｂ）上に積層された付加的なＡｌＧａＮ結晶層（３－５）をさらに有することを特徴とする請求項１に記載の基板。 The substrate according to claim 1, further comprising an additional AlGaN crystal layer (3-5) laminated on the AlN crystal layer or the AlGaN crystal layer (2b).
  3. 　前記付加的なＡｌＧａＮ結晶層はＡｌ組成比が順次低減された複数のサブ層（３、４、５）を含むことを特徴とする請求項２に記載の基板。 The substrate according to claim 2, wherein the additional AlGaN crystal layer includes a plurality of sub-layers (3, 4, 5) in which the Al composition ratio is sequentially reduced.
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