WO2013023530A1 - Implementation method and device for automatically detecting asymmetry time delay of 1588 link - Google Patents

Implementation method and device for automatically detecting asymmetry time delay of 1588 link Download PDF

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Publication number
WO2013023530A1
WO2013023530A1 PCT/CN2012/079570 CN2012079570W WO2013023530A1 WO 2013023530 A1 WO2013023530 A1 WO 2013023530A1 CN 2012079570 W CN2012079570 W CN 2012079570W WO 2013023530 A1 WO2013023530 A1 WO 2013023530A1
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time
time synchronization
delay
timestamp
clock
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PCT/CN2012/079570
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French (fr)
Chinese (zh)
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文林
张君辉
陈恺
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中兴通讯股份有限公司
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Publication of WO2013023530A1 publication Critical patent/WO2013023530A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H04L43/0858—One way delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Definitions

  • the present invention relates to the field of communications, and in particular, to a method and apparatus for automatically detecting 1588 link asymmetry delay. Background technique
  • the 1588 time synchronization protocol has received more and more attention and application in communication networks. Domestic and foreign operators continue to use the 1588 protocol for time synchronization and gradually replace GPS for time synchronization.
  • the synchronization method is shown in Figure 1.
  • the basis of the 1588 time synchronization is the symmetry of the uplink and downlink transmission delays. If the uplink and downlink transmission delays are asymmetric, that is, the uplink and downlink transmission delays are not equal, as shown in Figure 2, the time offset is calculated using the 1588 time synchronization protocol, and the error value of half of the asymmetry is not calculated. The value is removed, so that the time deviation is not corrected correctly, and the time synchronization quality is reduced. In the case of severe asymmetry delays, even the time is basically impossible to synchronize.
  • the main object of the present invention is to provide an automatic method for automatically detecting 1588 link asymmetric delay, which aims to realize automatic detection of 1588 link asymmetric delay without additional cost.
  • the present invention provides an implementation method for detecting an asymmetric delay of a 1588 link, which includes the following steps:
  • the running 1588 time synchronization protocol, calculating the time offset value includes:
  • the time stamp T 1 for transmitting the Sync message and the time stamp T2 for receiving the Sync message are recorded;
  • the time-stamp is calculated according to the time deviation value
  • the time stamp of the time synchronization is recorded
  • the time synchronization deviation value is calculated according to the time synchronization timestamp.
  • the primary clock sends the synchronous Sync message to the slave clock, and records the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message;
  • the synchronous Sync message includes a time offset value to enable the slave The clock corrects its time according to the time deviation value;
  • the method further includes:
  • the running 1588 time synchronization protocol further includes: configuring a time synchronization deviation threshold, that is, a delay in the absence of an asymmetry, and an accuracy of time synchronization of the device.
  • a time synchronization deviation threshold that is, a delay in the absence of an asymmetry, and an accuracy of time synchronization of the device.
  • the present invention also provides an apparatus for detecting an asymmetric delay of a 1588 link, including:
  • the 1588 protocol processing module is configured to: run a 1588 time synchronization protocol, and calculate a time difference value;
  • Correcting the deviation module the setting is: correcting the slave clock time according to the time deviation value, recording the time stamp of the 1588 time synchronization, and calculating the time synchronization deviation value according to the time synchronization time stamp;
  • the asymmetry detection module is configured to: determine whether the time synchronization deviation value is greater than a preset The time synchronization deviation threshold; if yes, the 1588 link asymmetric delay alarm is performed; to automatically detect the 1588 link asymmetric delay.
  • the 1588 protocol processing module is configured to:
  • the time stamp T 1 for transmitting the Sync message and the time stamp T2 for receiving the Sync message are recorded;
  • the correction deviation module is set to:
  • the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message are recorded;
  • the synchronous Sync message includes a time offset value to enable the slave clock Correcting the time according to the time deviation value;
  • the correction deviation module is further configured to:
  • the device further includes:
  • the parameter configuration module is set to: Configure the time synchronization deviation threshold, that is, the accuracy of the device time synchronization when there is no asymmetric delay.
  • the embodiment of the invention compares the time synchronization deviation value after detecting the deviation correction with the pre-configured time synchronization deviation threshold, thereby automatically detecting the uplink and downlink delay asymmetry of the 1588 time synchronization, and solving the manual detection by the special test instrument. At the same time, when the link changes, it is necessary to re-check.
  • BRIEF abstract 1 is a schematic flowchart of calculating a time deviation of a 1588 protocol in the related art
  • FIG. 2 is a schematic flowchart of a time synchronization deviation of a 1588 protocol affected by an asymmetry in the related art
  • FIG. 3 is a schematic flow chart of an embodiment of an implementation method for automatically detecting 1588 link asymmetry delay according to the present invention
  • FIG. 4 is a schematic structural diagram of an embodiment of an apparatus for automatically detecting 1588 link asymmetric delay in the present invention.
  • FIG. 3 is a schematic flow chart of an embodiment of an embodiment of the present invention for automatically detecting 1588 link asymmetry delay.
  • the method for automatically detecting 1588 link asymmetry delay of the present invention includes the following steps:
  • Step S101 Run a 1588 time synchronization protocol, and calculate a time offset value.
  • the operation process is:
  • Step S102 according to the time deviation value ⁇ positive slave clock time, record 1588 time synchronization time stamp;
  • the slave clock time is corrected according to the time offset value, and the correction process is:
  • the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message are recorded;
  • the synchronous Sync message includes a time offset value to enable the slave clock Correcting the time according to the time deviation value;
  • Step S103 Calculate a time synchronization deviation value according to a time synchronization time stamp
  • Step S104 determining whether the time synchronization deviation value is greater than a preset time synchronization deviation threshold, if yes, executing step S106; otherwise, performing step S105; if the time synchronization deviation value is greater than the time synchronization deviation threshold, indicating that the 1588 link transmission delay is not Symmetric; otherwise, it indicates that the 1588 link transmission delay is symmetric.
  • the time synchronization deviation threshold is pre-configured, that is, the accuracy of the device time synchronization in the absence of an asymmetric delay, in nanoseconds.
  • Step S105 continuing 1588 normal time synchronization, waiting for the next asymmetry detection period, performing step S101;
  • step S101 When the time synchronization deviation value is less than or equal to the preset time synchronization deviation threshold, the 1588 normal time synchronization is continued, and when the next asymmetric detection period comes, the process proceeds to step S101.
  • Step S106 Perform an alarm of 1588 link asymmetric delay.
  • time synchronization deviation value is greater than the preset time synchronization deviation threshold, an alarm is generated, so that the maintenance personnel can be notified to detect the link in time, correct the asymmetric delay, and ensure the quality of the 1588 time synchronization.
  • Offset ( (T2-T 1 )-(T4-T3))/2+(D2-D 1 )12 Equation ( 2 )
  • D1 is the downlink delay
  • D2 is the uplink delay
  • the time deviation calculated in step S101 is less (D2-Dl) /2. Therefore, there is also a deviation in the slave clock time corrected based on the time offset value.
  • the synchronization time deviation calculated in step S103 is greater than the preset synchronization deviation threshold, the uplink and downlink delays are symmetric; otherwise, the uplink and downlink delays are asymmetric.
  • the method for automatically detecting the 1588 link asymmetric delay is automatically compared with the pre-configured time synchronization deviation threshold by detecting the offset corrected time synchronization deviation value, thereby automatically detecting the 1588 time synchronization uplink and downlink delay
  • Asymmetry solves the problem of manual inspection by special test instruments and re-inspection when the link changes.
  • FIG. 4 is a schematic structural diagram of an embodiment of an apparatus for automatically detecting 1588 link asymmetric delay of the present invention, which can implement the above method.
  • the apparatus for automatically detecting 1588 link asymmetric delay of the present invention includes:
  • the 1588 protocol processing module 101 is configured to run the 1588 time synchronization protocol to calculate a time offset value.
  • the correction deviation module 102 is configured to correct the slave clock time according to the time offset value, record the time stamp of the 1588 time synchronization, and time stamp according to the time synchronization. , calculating the time synchronization deviation value;
  • the asymmetry detection module 103 is configured to determine whether the time synchronization deviation value is greater than a preset time synchronization deviation threshold, and if yes, perform an alarm of 1588 link asymmetry delay; if not, continue 1588 normal time synchronization Waiting for the next asymmetry detection cycle.
  • the correction deviation module 102 corrects the slave clock time according to the time deviation value calculated by the 1588 protocol processing module, and records the timestamp T1 of the synchronous Sync message, the timestamp ⁇ 2 of the received Sync message, and the Delay-req message of the delay request. Timestamp T3, receiving the timestamp T4 of the Delay-req message.
  • the time synchronization deviation threshold preset in the asymmetry detection module 103 is pre-configured by the parameter configuration module, that is, the accuracy of the device time synchronization in the absence of an asymmetric delay, in nanoseconds.
  • the time synchronization deviation value is greater than the preset time synchronization deviation threshold, an alarm is generated, so that the maintenance personnel can notify the link to detect the link in time, correct the asymmetric delay, and ensure the quality of the 1588 time synchronization.
  • the device for automatically detecting 1588 link asymmetry delay in the embodiment of the present invention compares the time synchronization deviation value after detecting the deviation correction with a pre-configured time synchronization deviation threshold, thereby automatically detecting 1588 time synchronization.
  • the asymmetry of the uplink and downlink delays solves the problem of manual detection by special test instruments and re-inspection when the link changes.
  • the embodiment of the present invention is implemented by adding a corresponding software program on the basis of the existing hardware device, so that the cost of the software is not increased without adding additional hardware costs, but effectively solving the 1588 time synchronization.
  • the problem of asymmetry saves the human and material costs of the 1588 time synchronization project.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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  • General Health & Medical Sciences (AREA)
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Abstract

An implementation method and device for automatically detecting the asymmetry time delay of a 1588 link. The implementation method includes: operating a 1588 time synchronization protocol and calculating a time deviation value; amending the time of a slave clock according to the time deviation value, recording a time stamp of 1588 time synchronization, and calculating a time synchronization deviation value according to the time stamp of time synchronization; judging whether the time synchronization deviation value is greater than a pre-configured time synchronization deviation threshold; and if it is yes, then raising a 1588 link asymmetry time delay alarm, realizing the automatic detection of the asymmetry time delay of the 1588 link. The above solution can automatically detect the uplink and downlink time delay asymmetry of 1588 time synchronization by detecting the deviation amended time synchronization deviation value and comparing same with a pre-configured time synchronization deviation threshold, solving the problems that the detection is manually performed by means of specific testing instruments, and when the link is changed, re-detection is required.

Description

自动侦测 1588链路非对称性时延的实现方法及装置  Method and device for automatically detecting 1588 link asymmetric delay
技术领域 Technical field
本发明涉及通讯领域，尤其涉及一种自动侦测 1588链路非对称性时延的 实现方法及装置。 背景技术  The present invention relates to the field of communications, and in particular, to a method and apparatus for automatically detecting 1588 link asymmetry delay. Background technique
随着 3G网络的高速发展， 1588时间同步协议在通讯网络中得到越来越 多的重视和应用。 国内外运营商不断的使用 1588协议进行时间同步， 逐步替 换 GPS进行时间同步。  With the rapid development of 3G networks, the 1588 time synchronization protocol has received more and more attention and application in communication networks. Domestic and foreign operators continue to use the 1588 protocol for time synchronization and gradually replace GPS for time synchronization.
1588时间同步协议中， 同步方法如图 1所示。 该 1588时间同步的基础 为上下行链路传输时延对称。 如果上下行链路传输时延非对称， 即上下行链 路的传输延时不相等，如图 2所示，则使用 1588时间同步协议计算时间偏差， 非对称性一半的误差值没有计算到偏差值中去， 使得时间偏差得不到正确的 修正， 降低时间同步质量。 在非对称性时延严重的情况下， 甚至导致时间基 本上无法同步。  In the 1588 time synchronization protocol, the synchronization method is shown in Figure 1. The basis of the 1588 time synchronization is the symmetry of the uplink and downlink transmission delays. If the uplink and downlink transmission delays are asymmetric, that is, the uplink and downlink transmission delays are not equal, as shown in Figure 2, the time offset is calculated using the 1588 time synchronization protocol, and the error value of half of the asymmetry is not calculated. The value is removed, so that the time deviation is not corrected correctly, and the time synchronization quality is reduced. In the case of severe asymmetry delays, even the time is basically impossible to synchronize.
目前针对非对称性时延的情况， 基本上都是使用专用测试仪器测量 1588 上下行链路的时延， 以便发现时延的非对称性。 这种方法不但耗费人力物力， 同时当链路发生变化时， 设备无法自动侦测出是否有非对称性时延存在。 发明内容  For the case of asymmetric delay, it is basically the use of dedicated test instruments to measure the delay of the 1588 uplink and downlink, in order to find the asymmetry of the delay. This method not only consumes manpower and resources, but also when the link changes, the device cannot automatically detect whether there is an asymmetric delay. Summary of the invention
本发明的主要目的是提供一种自动侦测 1588链路非对称时延的实现方 法， 旨在不增加额外成本的情况下实现 1588链路非对称时延的自动侦测。  The main object of the present invention is to provide an automatic method for automatically detecting 1588 link asymmetric delay, which aims to realize automatic detection of 1588 link asymmetric delay without additional cost.
本发明提供了一种侦测 1588链路非对称时延的实现方法， 包括以下步 骤：  The present invention provides an implementation method for detecting an asymmetric delay of a 1588 link, which includes the following steps:
运行 1588时间同步协议， 计算时间偏差值；  Run the 1588 time synchronization protocol to calculate the time offset value;
根据时间偏差值修正从时钟时间， 记录 1588时间同步的时间戳， 并根据 时间同步的时间戳， 计算时间同步偏差值； 判断所述时间同步偏差值是否大于预置的时间同步偏差门限； 如果是， 则进行 1588链路非对称性时延的告警， 实现自动侦测 1588链路非对称时延。 Correcting the slave clock time according to the time offset value, recording the time stamp of the 1588 time synchronization, and calculating the time synchronization offset value according to the time synchronization time stamp; Determining whether the time synchronization deviation value is greater than a preset time synchronization deviation threshold; if yes, performing an alarm of 1588 link asymmetric delay to automatically detect 1588 link asymmetric delay.
优选地， 所述运行 1588时间同步协议， 计算时间偏差值包括：  Preferably, the running 1588 time synchronization protocol, calculating the time offset value includes:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T 1及接收 Sync报文的时间戳 T2；  When the master clock sends the synchronous Sync message to the slave clock, the time stamp T 1 for transmitting the Sync message and the time stamp T2 for receiving the Sync message are recorded;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间偏差值， 其计算公式为： ( ( T2-T1 ) - ( T4-T3 ) ) /2。  Calculate the time deviation value, which is calculated as: ( ( T2-T1 ) - ( T4-T3 ) ) /2.
优选地， 所述才艮据时间偏差值爹正从时钟时间， 记录 1588时间同步的时 间戳， 并根据时间同步的时间戳， 计算时间同步偏差值包括：  Preferably, the time-stamp is calculated according to the time deviation value, the time stamp of the time synchronization is recorded, and the time synchronization deviation value is calculated according to the time synchronization timestamp.
在主时钟发送同步 Sync报文至从时钟时， 并记录发送所述 Sync报文的 时间戳 T1及接收 Sync报文的时间戳 T2; 所述同步 Sync报文中包括时间偏 差值， 以使从时钟根据所述时间偏差值对其时间进行修正；  When the primary clock sends the synchronous Sync message to the slave clock, and records the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message; the synchronous Sync message includes a time offset value to enable the slave The clock corrects its time according to the time deviation value;
在从时钟发送延时请求 Delay— req报文至主时钟时，并记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4；  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间同步偏差值， 其计算公式为： （T2-T1 ) - ( T4-T3 ) 。  Calculate the time synchronization deviation value, which is calculated as: (T2-T1) - (T4-T3).
优选地， 所述计算时间同步偏差值后还包括：  Preferably, after the calculating the time synchronization deviation value, the method further includes:
暂停 1588时间同步及时间偏差的修正。  Pause 1588 time synchronization and time offset correction.
优选地， 所述运行 1588时间同步协议， 计算时间偏差值之前还包括： 配置时间同步偏差门限， 即在没有非对称时延时，设备时间同步的精度。  Preferably, the running 1588 time synchronization protocol further includes: configuring a time synchronization deviation threshold, that is, a delay in the absence of an asymmetry, and an accuracy of time synchronization of the device.
本发明还提供了一种侦测 1588链路非对称时延的实现装置， 包括：The present invention also provides an apparatus for detecting an asymmetric delay of a 1588 link, including:
1588协议处理模块， 其设置为： 运行 1588时间同步协议， 计算时间偏 差值； The 1588 protocol processing module is configured to: run a 1588 time synchronization protocol, and calculate a time difference value;
修正偏差模块， 其设置为： 根据时间偏差值修正从时钟时间， 记录 1588 时间同步的时间戳， 并根据时间同步的时间戳， 计算时间同步偏差值；  Correcting the deviation module, the setting is: correcting the slave clock time according to the time deviation value, recording the time stamp of the 1588 time synchronization, and calculating the time synchronization deviation value according to the time synchronization time stamp;
非对称性检测模块， 其设置为： 判断所述时间同步偏差值是否大于预置 的时间同步偏差门限； 如果是， 则进行 1588链路非对称性时延的告警； 以实现自动侦测 1588链路非对称时延。 The asymmetry detection module is configured to: determine whether the time synchronization deviation value is greater than a preset The time synchronization deviation threshold; if yes, the 1588 link asymmetric delay alarm is performed; to automatically detect the 1588 link asymmetric delay.
优选地， 所述 1588协议处理模块设置为：  Preferably, the 1588 protocol processing module is configured to:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T 1及接收 Sync报文的时间戳 T2；  When the master clock sends the synchronous Sync message to the slave clock, the time stamp T 1 for transmitting the Sync message and the time stamp T2 for receiving the Sync message are recorded;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间偏差值， 其计算公式为： ( ( T2-T1 ) - ( T4-T3 ) ) /2。  Calculate the time deviation value, which is calculated as: ( ( T2-T1 ) - ( T4-T3 ) ) /2.
优选地， 所述修正偏差模块设置为：  Preferably, the correction deviation module is set to:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T1及接收 Sync报文的时间戳 T2; 所述同步 Sync报文中包括时间偏差 值， 以使从时钟根据所述时间偏差值对其时间进行修正；  When the primary clock sends the synchronous Sync message to the slave clock, the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message are recorded; the synchronous Sync message includes a time offset value to enable the slave clock Correcting the time according to the time deviation value;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间同步偏差值， 其计算公式为： （T2-T1 ) - ( T4-T3 ) 。  Calculate the time synchronization deviation value, which is calculated as: (T2-T1) - (T4-T3).
优选地， 所述修正偏差模块还设置为：  Preferably, the correction deviation module is further configured to:
暂停 1588时间同步及时间偏差的修正。  Pause 1588 time synchronization and time offset correction.
优选地， 所述装置还包括：  Preferably, the device further includes:
参数配置模块， 设置为： 配置时间同步偏差门限， 即在没有非对称时延 时， 设备时间同步的精度。  The parameter configuration module is set to: Configure the time synchronization deviation threshold, that is, the accuracy of the device time synchronization when there is no asymmetric delay.
本发明实施例通过检测偏差修正后的时间同步偏差值与预先配置的时间 同步偏差门限进行比较，从而可以自动检测 1588时间同步的上下链路时延非 对称性， 解决了人工通过特殊测试仪器检测， 同时在链路发生变化时， 又要 重新进行检查的问题。 附图概述 图 1是相关技术中 1588协议计算时间偏差的流程示意图； 图 2是相关技术中受非对称影响的 1588协议时间同步出现偏差的流程示 意图； The embodiment of the invention compares the time synchronization deviation value after detecting the deviation correction with the pre-configured time synchronization deviation threshold, thereby automatically detecting the uplink and downlink delay asymmetry of the 1588 time synchronization, and solving the manual detection by the special test instrument. At the same time, when the link changes, it is necessary to re-check. BRIEF abstract 1 is a schematic flowchart of calculating a time deviation of a 1588 protocol in the related art; FIG. 2 is a schematic flowchart of a time synchronization deviation of a 1588 protocol affected by an asymmetry in the related art;
图 3是本发明自动侦测 1588链路非对称性时延的实现方法一实施例的流 程示意图；  3 is a schematic flow chart of an embodiment of an implementation method for automatically detecting 1588 link asymmetry delay according to the present invention;
图 4是本发明自动侦测 1588链路非对称时延的实现装置一实施例的结构 示意图。  4 is a schematic structural diagram of an embodiment of an apparatus for automatically detecting 1588 link asymmetric delay in the present invention.
本发明目的的实现、 功能特点及优点将结合实施例， 参照附图做进一步 说明。 本发明的较佳实施方式  The implementation, functional features, and advantages of the present invention will be further described with reference to the accompanying drawings. Preferred embodiment of the invention
以下结合说明书附图及具体实施例进一步说明本发明的技术方案。 应当 理解， 此处所描述的具体实施例仅仅用以解释本发明， 并不用于限定本发明。  The technical solutions of the present invention are further described below in conjunction with the drawings and specific embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
图 3是本发明自动侦测 1588链路非对称性时延的实现方法一实施例的流 程示意图。  FIG. 3 is a schematic flow chart of an embodiment of an embodiment of the present invention for automatically detecting 1588 link asymmetry delay.
参照图 3 , 本发明自动侦测 1588链路非对称性时延的实现方法包括以下 步骤：  Referring to FIG. 3, the method for automatically detecting 1588 link asymmetry delay of the present invention includes the following steps:
步骤 S101、 运行 1588时间同步协议， 计算时间偏差值；  Step S101: Run a 1588 time synchronization protocol, and calculate a time offset value.
根据图 1所示的 1588协议同步过程， 其运行过程为：  According to the 1588 protocol synchronization process shown in Figure 1, the operation process is:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T1及接收 Sync报文的时间戳 T2;  When the master clock sends the synchronous Sync message to the slave clock, the time stamp T1 for sending the Sync message and the timestamp T2 for receiving the Sync message are recorded;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间偏差值， 其计算公式为：  Calculate the time deviation value, which is calculated as:
Offset = ( ( T2-T1 ) - ( T4-T3 ) ) 12 公式 ( 1 ) 步骤 S102、 才艮据时间偏差值爹正从时钟时间， 记录 1588时间同步的时 间戳； 根据时间偏差值修正从时钟时间， 其修正过程为： Offset = ( ( T2-T1 ) - ( T4-T3 ) ) 12 Equation ( 1 ) Step S102, according to the time deviation value 爹 positive slave clock time, record 1588 time synchronization time stamp; The slave clock time is corrected according to the time offset value, and the correction process is:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T1及接收 Sync报文的时间戳 T2; 所述同步 Sync报文中包括时间偏差 值， 以使从时钟根据所述时间偏差值对其时间进行修正；  When the primary clock sends the synchronous Sync message to the slave clock, the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message are recorded; the synchronous Sync message includes a time offset value to enable the slave clock Correcting the time according to the time deviation value;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4。  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded.
在时间偏差修正之前还包括： 暂停 1588时间同步及时间偏差的修正。 步骤 S103、 根据时间同步的时间戳， 计算时间同步偏差值；  Before the time deviation correction, it also includes: Pause 1588 time synchronization and correction of time deviation. Step S103: Calculate a time synchronization deviation value according to a time synchronization time stamp;
根据步骤 S102 中记录的时间同步的时间戳， 计算时间同步偏差值， 即 ( T2-T1 ) - ( T4-T3 ) ；  Calculating the time synchronization deviation value according to the time synchronization time stamp recorded in step S102, that is, ( T2-T1 ) - ( T4-T3 ) ;
步骤 S104、 判断时间同步偏差值是否大于预置的时间同步偏差门限， 是 则执行步骤 S106; 否则执行步骤 S105; 果该时间同步偏差值大于时间同步偏差门限，则表示 1588链路传输时延非对 称； 否则表示 1588链路传输时延对称。 该时间同步偏差门限为预先配置的， 即在没有非对称时延的情况下， 设备时间同步的精度， 单位为纳秒。  Step S104: determining whether the time synchronization deviation value is greater than a preset time synchronization deviation threshold, if yes, executing step S106; otherwise, performing step S105; if the time synchronization deviation value is greater than the time synchronization deviation threshold, indicating that the 1588 link transmission delay is not Symmetric; otherwise, it indicates that the 1588 link transmission delay is symmetric. The time synchronization deviation threshold is pre-configured, that is, the accuracy of the device time synchronization in the absence of an asymmetric delay, in nanoseconds.
步骤 S105、 继续 1588正常时间同步， 等待下一个非对称性检测周期时， 执行步骤 S101 ;  Step S105, continuing 1588 normal time synchronization, waiting for the next asymmetry detection period, performing step S101;
当时间同步偏差值小于或等于预置的时间同步偏差门限内， 则继续 1588 正常时间同步， 并等待下一个非对称检测周期到来时， 执行步骤 S101。  When the time synchronization deviation value is less than or equal to the preset time synchronization deviation threshold, the 1588 normal time synchronization is continued, and when the next asymmetric detection period comes, the process proceeds to step S101.
步骤 S106、 进行 1588链路非对称性时延的告警。  Step S106: Perform an alarm of 1588 link asymmetric delay.
当时间同步偏差值大于预置的时间同步偏差门限， 则进行告警， 从而可 以通知维护人员及时检测链路， 修正非对称性时延， 确保 1588时间同步的质 量。  When the time synchronization deviation value is greater than the preset time synchronization deviation threshold, an alarm is generated, so that the maintenance personnel can be notified to detect the link in time, correct the asymmetric delay, and ensure the quality of the 1588 time synchronization.
由于上述公式（ 1 )的假设是上行链路时延与下行链路时延对称。 而实际 的计算公式是：  The assumption of the above formula (1) is that the uplink delay is symmetric with the downlink delay. The actual calculation formula is:
Offset=( (T2-T 1 )-(T4-T3))/2+(D2-D 1 )12 公式 ( 2 ) 其中 Dl为下行链路时延， D2为上行链路时延， 所以该步骤 S101计算 出来的时间偏差少了 （D2-Dl ) /2。 因此， 根据该时间偏差值修正的从时钟时 间也存在偏差。 步骤 S103 中计算的同步时间偏差大于预置的同步偏差门限 时， 则上下行链路时延对称； 否则上下行链路时延不对称。 Offset=( (T2-T 1 )-(T4-T3))/2+(D2-D 1 )12 Equation ( 2 ) Where D1 is the downlink delay and D2 is the uplink delay, so the time deviation calculated in step S101 is less (D2-Dl) /2. Therefore, there is also a deviation in the slave clock time corrected based on the time offset value. When the synchronization time deviation calculated in step S103 is greater than the preset synchronization deviation threshold, the uplink and downlink delays are symmetric; otherwise, the uplink and downlink delays are asymmetric.
本发明自动侦测 1588链路非对称性时延的实现方法通过检测偏差修正 后的时间同步偏差值与预先配置的时间同步偏差门限进行比较， 从而可以自 动检测 1588时间同步的上下链路时延非对称性，解决了人工通过特殊测试仪 器检测， 同时在链路发生变化时， 又要重新进行检查的问题。  The method for automatically detecting the 1588 link asymmetric delay is automatically compared with the pre-configured time synchronization deviation threshold by detecting the offset corrected time synchronization deviation value, thereby automatically detecting the 1588 time synchronization uplink and downlink delay Asymmetry solves the problem of manual inspection by special test instruments and re-inspection when the link changes.
参照图 4, 图 4是本发明自动侦测 1588链路非对称时延的实现装置一实 施例的结构示意图， 该装置可实现上述方法。 Referring to FIG. 4, FIG. 4 is a schematic structural diagram of an embodiment of an apparatus for automatically detecting 1588 link asymmetric delay of the present invention, which can implement the above method.
如图 4所示， 本发明自动侦测 1588链路非对称时延的实现装置包括： As shown in FIG. 4, the apparatus for automatically detecting 1588 link asymmetric delay of the present invention includes:
1588协议处理模块 101 ,用于运行 1588时间同步协议，计算时间偏差值； 修正偏差模块 102, 用于根据时间偏差值修正从时钟时间， 记录 1588时 间同步的时间戳， 并根据时间同步的时间戳， 计算时间同步偏差值； The 1588 protocol processing module 101 is configured to run the 1588 time synchronization protocol to calculate a time offset value. The correction deviation module 102 is configured to correct the slave clock time according to the time offset value, record the time stamp of the 1588 time synchronization, and time stamp according to the time synchronization. , calculating the time synchronization deviation value;
非对称性检测模块 103 , 用于判断该时间同步偏差值是否大于预置的时 间同步偏差门限， 如果是， 则进行 1588链路非对称性时延的告警； 如果否， 则继续 1588正常时间同步， 等待下一个非对称性检测周期时。  The asymmetry detection module 103 is configured to determine whether the time synchronization deviation value is greater than a preset time synchronization deviation threshold, and if yes, perform an alarm of 1588 link asymmetry delay; if not, continue 1588 normal time synchronization Waiting for the next asymmetry detection cycle.
修正偏差模块 102根据 1588协议处理模块计算的时间偏差值修正从时钟 时间， 并记录发送同步 Sync报文的时间戳 Tl、 接收 Sync报文的时间戳 Τ2 及发送延时请求 Delay— req报文的时间戳 T3、 接收 Delay— req报文的时间戳 T4。  The correction deviation module 102 corrects the slave clock time according to the time deviation value calculated by the 1588 protocol processing module, and records the timestamp T1 of the synchronous Sync message, the timestamp Τ2 of the received Sync message, and the Delay-req message of the delay request. Timestamp T3, receiving the timestamp T4 of the Delay-req message.
非对称性检测模块 103中预置的时间同步偏差门限通过参数配置模块预 先配置， 即在没有非对称时延的情况下， 设备时间同步的精度， 单位为纳秒。 当时间同步偏差值大于预置的时间同步偏差门限， 则进行告警， 从而可以通 知维护人员及时检测链路， 修正非对称性时延， 确保 1588时间同步的质量。  The time synchronization deviation threshold preset in the asymmetry detection module 103 is pre-configured by the parameter configuration module, that is, the accuracy of the device time synchronization in the absence of an asymmetric delay, in nanoseconds. When the time synchronization deviation value is greater than the preset time synchronization deviation threshold, an alarm is generated, so that the maintenance personnel can notify the link to detect the link in time, correct the asymmetric delay, and ensure the quality of the 1588 time synchronization.
以上所述仅为本发明的优选实施例， 并非因此限制其专利范围， 凡是利 用本发明说明书及附图内容所作的等效结构或等效流程变换， 直接或间接运 用在其他相关的技术领域， 均同理包括在本发明的专利保护范围内。 The above description is only a preferred embodiment of the present invention, and thus does not limit the scope of the patent, The equivalent structure or equivalent flow transformation made by the specification and the drawings of the present invention is directly or indirectly applied to other related technical fields, and is included in the scope of patent protection of the present invention.
工业实用性 本发明实施例自动侦测 1588链路非对称性时延的实现装置通过检测偏 差修正后的时间同步偏差值与预先配置的时间同步偏差门限进行比较， 从而 可以自动检测 1588时间同步的上下链路时延非对称性，解决了人工通过特殊 测试仪器检测， 同时在链路发生变化时， 又要重新进行检查的问题。 而且， 本发明实施例是在现有的硬件设备基础上增加相应的软件程序而实现的， 故 不增加额外的硬件成本， 软件的成本增加也不大， 但却有效地达到解决 1588 时间同步的非对称性问题， 节约了开通 1588 时间同步工程上的人力物力成 本。 INDUSTRIAL APPLICABILITY The device for automatically detecting 1588 link asymmetry delay in the embodiment of the present invention compares the time synchronization deviation value after detecting the deviation correction with a pre-configured time synchronization deviation threshold, thereby automatically detecting 1588 time synchronization. The asymmetry of the uplink and downlink delays solves the problem of manual detection by special test instruments and re-inspection when the link changes. Moreover, the embodiment of the present invention is implemented by adding a corresponding software program on the basis of the existing hardware device, so that the cost of the software is not increased without adding additional hardware costs, but effectively solving the 1588 time synchronization. The problem of asymmetry saves the human and material costs of the 1588 time synchronization project.

Claims

权 利 要 求 书 Claim
1、 一种侦测 1588链路非对称时延的实现方法， 包括：  1. An implementation method for detecting an asymmetric delay of a 1588 link, including:
运行 1588时间同步协议， 计算时间偏差值；  Run the 1588 time synchronization protocol to calculate the time offset value;
才艮据所述时间偏差值爹正从时钟时间， 记录 1588时间同步的时间戳， 并 根据时间同步的时间戳， 计算时间同步偏差值；  According to the time deviation value, the clock time is recorded, the time stamp of the time synchronization is recorded, and the time synchronization deviation value is calculated according to the time synchronization time stamp;
判断所述时间同步偏差值是否大于预置的时间同步偏差门限； 如果是， 则进行 1588链路非对称性时延的告警， 实现自动侦测 1588链路非对称时延。  And determining whether the time synchronization deviation value is greater than a preset time synchronization deviation threshold; if yes, performing an alarm of 1588 link asymmetric delay to automatically detect 1588 link asymmetric delay.
2、 根据权利要求 1所述的方法， 其中， 所述运行 1588时间同步协议， 计算时间偏差值包括：  2. The method according to claim 1, wherein the running 1588 time synchronization protocol, calculating a time offset value comprises:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T1及接收 Sync报文的时间戳 T2;  When the master clock sends the synchronous Sync message to the slave clock, the time stamp T1 for sending the Sync message and the timestamp T2 for receiving the Sync message are recorded;
在从时钟发送延时请求（ Delay— req )报文至主时钟时，记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  The timestamp T3 of the Delay-req message and the timestamp T4 of the Receive Delay-req message are recorded when the delay-req message is sent from the clock to the master clock.
计算时间偏差值， 其计算公式为： ( ( T2-T1 ) - ( T4-T3 ) ) /2。  Calculate the time deviation value, which is calculated as: ( ( T2-T1 ) - ( T4-T3 ) ) /2.
3、 根据权利要求 1所述的方法， 其中， 所述根据时间偏差值修正从时钟 时间， 记录 1588时间同步的时间戳， 并才艮据时间同步的时间戳， 计算时间同 步偏差值包括：  3. The method according to claim 1, wherein the correcting the slave clock time according to the time offset value, recording the time stamp of the 1588 time synchronization, and calculating the time synchronization time value according to the time synchronization time stamp includes:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T1及接收 Sync报文的时间戳 T2; 所述同步 Sync报文中包括时间偏差 值， 以使从时钟根据所述时间偏差值对其时间进行修正；  When the primary clock sends the synchronous Sync message to the slave clock, the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message are recorded; the synchronous Sync message includes a time offset value to enable the slave clock Correcting the time according to the time deviation value;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间同步偏差值， 计算公式为： （T2-T1 ) - ( T4-T3 ) 。  Calculate the time synchronization deviation value, which is calculated as: (T2-T1 ) - ( T4-T3 ).
4、 根据权利要求 3所述的方法， 其中， 所述计算时间同步偏差值后还包 括： 暂停 1588时间同步及时间偏差的修正。  4. The method according to claim 3, wherein the calculating the time synchronization deviation value further comprises: suspending 1588 time synchronization and correction of time offset.
5、 根据权利要求 1至 4中任一项所述的方法， 其中， 所述运行 1588时 间同步协议， 计算时间偏差值之前还包括： 配置时间同步偏差门限， 即在没有非对称时延时，设备时间同步的精度。The method according to any one of claims 1 to 4, wherein the running 1588 time synchronization protocol further comprises: before calculating the time deviation value: Configure the time synchronization deviation threshold, that is, the delay in the absence of asymmetry, the accuracy of the device time synchronization.
6、 一种侦测 1588链路非对称时延的实现装置， 包括： 6. An apparatus for detecting an asymmetric delay of a 1588 link, comprising:
1588协议处理模块， 其设置为： 运行 1588时间同步协议， 计算时间偏 差值；  The 1588 protocol processing module is configured to: run a 1588 time synchronization protocol, and calculate a time difference value;
修正偏差模块， 其设置为： 根据时间偏差值修正从时钟时间， 记录 1588 时间同步的时间戳， 并根据时间同步的时间戳， 计算时间同步偏差值；  Correcting the deviation module, the setting is: correcting the slave clock time according to the time deviation value, recording the time stamp of the 1588 time synchronization, and calculating the time synchronization deviation value according to the time synchronization time stamp;
非对称性检测模块， 其设置为： 判断所述时间同步偏差值是否大于预置 的时间同步偏差门限； 如果是， 则进行 1588链路非对称性时延的告警；  The asymmetry detection module is configured to: determine whether the time synchronization deviation value is greater than a preset time synchronization deviation threshold; if yes, perform an alarm of 1588 link asymmetry delay;
以实现自动侦测 1588链路非对称时延。  To achieve automatic detection of 1588 link asymmetric delay.
7、 根据权利要求 6所述的装置， 其中， 所述 1588协议处理模块设置为： 在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T1及接收 Sync报文的时间戳 T2;  The device according to claim 6, wherein the 1588 protocol processing module is configured to: when the primary clock sends the synchronous Sync message to the slave clock, record the timestamp T1 of the Sync message and receive the Sync message. Timestamp T2 of the text;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间偏差值， 计算公式为： （ （ T2-T1 ) - ( T4-T3 ) 、 11。  Calculate the time deviation value, which is calculated as: ( ( T2-T1 ) - ( T4-T3 ) , 11.
8、 根据权利要求 6的装置， 其中， 所述修正偏差模块设置为：  8. The apparatus according to claim 6, wherein the correction deviation module is configured to:
在主时钟发送同步 Sync报文至从时钟时， 记录发送所述 Sync报文的时 间戳 T1及接收 Sync报文的时间戳 T2; 所述同步 Sync报文中包括时间偏差 值， 以使从时钟根据所述时间偏差值对其时间进行修正；  When the primary clock sends the synchronous Sync message to the slave clock, the timestamp T1 of sending the Sync message and the timestamp T2 of receiving the Sync message are recorded; the synchronous Sync message includes a time offset value to enable the slave clock Correcting the time according to the time deviation value;
在从时钟发送延时请求 Delay— req报文至主时钟时， 记录发送 Delay— req 报文的时间戳 T3及接收 Delay— req报文的时间戳 T4;  When the delay-req message is sent from the clock to the master clock, the timestamp T3 of the Delay-req message and the timestamp T4 of the Delay-req message are recorded;
计算时间同步偏差值， 计算公式为： （T2-T1 ) - ( T4-T3 ) 。  Calculate the time synchronization deviation value, which is calculated as: (T2-T1 ) - ( T4-T3 ).
9、 根据权利要求 8所述的装置， 其中， 所述修正偏差模块还设置为： 暂停 1588时间同步及时间偏差的修正。  9. The apparatus according to claim 8, wherein the correction deviation module is further configured to: suspend 1588 time synchronization and correction of time offset.
10、 根据权利要求 6至 9中任一项所述的装置， 其中， 还包括： 参数配置模块， 设置为： 配置时间同步偏差门限， 即在没有非对称时延 时， 设备时间同步的精度。  The device according to any one of claims 6 to 9, further comprising: a parameter configuration module, configured to: configure a time synchronization deviation threshold, that is, an accuracy of time synchronization of the device when there is no asymmetric delay.
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