WO2013016989A1

WO2013016989A1 - Test stimuli compression and test response compaction in low-power scan testing

Info

Publication number: WO2013016989A1
Application number: PCT/CN2012/077512
Authority: WO
Inventors: Dong Xiang; Zhen Chen
Original assignee: Tsinghua University
Priority date: 2011-07-29
Filing date: 2012-06-26
Publication date: 2013-02-07
Also published as: CN102305912B; CN102305912A

Abstract

It is essential to propose a new scan testing scheme that efficiently compresses stimulus data and compacts test responses, provides low-power feature, and reduces test application cost significantly. A new test response compaction scheme called selective test response collection is proposed to reduce test response data, which is combined with a structure-analysis-based test response compactor by using a new coordination measure. The scan architecture is also established considering the coordination relationship between scan flip-flops. A new low-power test application scheme is proposed, which is able to compress test data very well and the test application time remains at the level of multiple scan chain designs. A combination of a scan architecture and an existent test compression scheme can greatly compress test data.

Description

Test stimuli compression and test response compaction in

low-power scan testing

Technical Field

The present invention relates to digital system testing, particularly to test stimuli compression and test response compaction in the low-power testing scheme.

Background Art

Scan testing method is widely used in the very large scale integrated (VLSI) circuits testing. In the scan testing scheme, each flip-flop is transformed to a scan cell that has two inputs, and one is the normal D input while the other is feed by the output of another flip-flop. In this way, the scan cells can be connected as a line, referred to as a scan chain. In the test application, the test vector is shifted into the scan chain, and then applied to the circuit under test. Finally, the test response is shifted out of the scan chain.

With the ever increasing integration density, nowadays large integrated circuits (ICs) contain more scan cells and faults, which require an increasing amount of data to test them. At the same time, ICs' power dissipation in scan-based testing can be significantly higher than that during normal operations, in both shift mode and capture mode.

Many compression strategies were proposed to reduce the test stimuli data volume stored in the ATE. They can be categorized into three kinds: (1) code-based methods; (2) linear decompressor-based compression (LDC) methods; and (3) broadcast-based methods. Coding-based methods are based on the coding theory, using some encoding methods to compress the test stimuli. LDC methods use the linear decompressor circuit to compress the test stimuli and its basis theory is the linear equation systems. Broadcast-based methods explore the compatibility between different bits in a test vector, in order to feed multiple scan cells with the same input bit.

Test response compaction is another important issue to reduce test data volume. It can be divided into time compaction and space compaction. Time compaction methods generate output signature using the output bits among multiple test cycles, while space compaction methods use the test response from multiple outputs in the same cycle to generate signature. Aliasing and unknown are two important factors during the compaction since they can destroy the observed response.

Many methods have been proposed to solve the shift and/or capture power. They can be categorized into two kinds: (1) DFT-based methods that rely on design techniques such as clock disabling, scan-in disabling, and scan chain partitioning; (2) ATPG-based methods that are based on X-filling or the modification of the ATPG algorithm. Some methods are filling the X bits to reduce test power. Other pattern based methods use the modified test generation procedure to generate test patterns with low power in test application.

Many methods were proposed to reduce test data volume and test power. However, they cannot solve the test stimuli, test response and test power at the same time. A new test application scheme with test stimuli compression and response compaction is proposed to solve the problems simultaneously.

Contents of the Invention

A new test application scheme based on scan forest was proposed to reduce test power and compress test data. A combination of the scan architecture and a test data compression scheme can more effectively compress test data. The new test application scheme was implemented by combining a clock disabling technique and the repetition function of the ATE, which significantly reduces both shift power and capture power. Test response data were compacted effectively by using the structure information of the circuit. A new scheme called selective test response collection was proposed to compact test response data further, which can be easily implemented by the current ATEs. A simple graph theoretic model and an approximate procedure were proposed to establish the new test response compactor based on the selective response collection scheme and the coordination measure. The test response compactor to tolerate unknowns was further proposed based on selective test response collection.

Brief Description of Figures

Fig. 1 illustrates the basis theory for selective test response compaction.

Fig. 2 - Fig. 4 illustrate the procedure to construct test response compactor.

Fig. 5 illustrates the test compression scheme.

Fig. 6 illustrates the scan architecture with selective test response compactor.

Fig. 7 illustrates the low power test application scheme.

Specific Mode for Carrying out the Invention

Fault effects of any detected fault can be propagated to multiple sites. However, it is enough if one of the sites can be observed. This idea is used to establish a new test response compactor. As shown in Fig. 1, all scan chains are partitioned into three subsets G , G₂, and G₃. Two faults fi and f₂ are detected by a test vector. Let fault effects of fi and f₂ be propagated to scan flip-flops (A, B, F, H , and (C, E, I), respectively. Only test responses captured by scan flip-flops in G are enough to detect both faults. This can significantly reduce test response data volume.

We would like to assign a coordination measure for any pair of scan flip-flops according to the generated test set. A table is established for each test vector based on the fault simulation information as presented in Fig. 2(a). Let the circuit have eighteen scan flip-flops c_\ _ig, i 5 be five faults, and vi ₆ be six test vectors. The test vector vi covers faults f_\,f₂, fo, f₄ and /5. We set the corresponding bit to one when the fault effect of a fault is propagated to the scan flip-flop. As shown in Fig. 2(a), fault effects of /i are propagated to c₂, c₉, and en, while fault effects of the fault f₂ are propagated to c_\, c₃, C5, and en. Totally, the fault effects of the five faults are propagated to eight scan flip-flops. It is enough to observe test responses at c₂ and c₃ for test vector vi.

Selection of the smallest number of scan flip-flops to observe the fault effects of all detected faults can be formulated into a minimum covering problem. The minimum covering problem is a known NP-hard problem. We would like to find an approximate procedure to get the minimum number of necessary observation scan flip-flops for each test vector: (1) Our method first finds the scan flip-flop c_\, where the most number of faults detected by the test vector can be observed; (2) we select the next scan flip-flop c₂, where the most number of faults, that are not observed at c_\, can be observed from c₂; (3) this process continues until all faults detected by the test vector can be observed from at least one flip-flop.

As shown in Fig. 2(a), c₃ is chosen first as the necessary observation scan flip-flops for test vector v_1? where the most number of faults can be observed at c₃. Our method then selects c₂, where two new faults can be observed from c₂. That is, c₂ and c₃ are the necessary observation scan flip-flops for the test vector vi.

Our method would like to cluster scan flip-flops that are required observing test responses by the most test vectors into the same subset of scan chains, so that the test response data volume can be well- compacted and the test application cost can be reduced efficiently. Fig. 2(b) presents the table for six test vectors and eighteen scan flip-flops. Let us introduce a new measure p_v(i, j) to estimate the coordination relation between any pair of scan flip-flops i and j for test vector v. We have p_v(i, j) = 1 if scan flip-flops i and j must be observed for the test vector v, otherwise, p_v(i, j) = 0.

Let (ci, <¾, . . . , Cd) be a scan flip-flop group G, and V and S be the test set and the scan flip-flop set. Our method selects another group Gi of scan flip-flops (c , c , . . . , c'_<*). Our method connects the scan flip-flops c'i, c'₂, . . . , c' d to any of c <¾, . . . , c_d. The summation of the coordination measures for each pair of scan flip-flops placed in the same scan chain zed as presented in Equation (1):

where p_v(i, j) is the coordination measure corresponding to the test vector v, and C_k is any one of the scan chains in the scan tree. The above process continues until the first scan tree has been constructed. All other scan trees can be established similarly.

An example is given to show the procedure for constructing scan trees. Assume that there are nine scan flip-flop groups (1,2), (3,4), (5,6), (7,8), (9,10), (11,12), (13,14), (15,16), and (17,18), where scan flip-flops in each group do not have any common combinational successor. The procedure is as follow:

(1) Let group (1, 2) be selected and placed at the first level of the first scan tree. The coordination measures as presented in Equation (1) between (1,2) and any other group are {2,1,2,0,2,2,2,3 }, the scan flip-flop group (17,18) is selected and placed at the second level of the scan tree.

(2) The measures between the constructed partial scan tree and any other seven scan flip-flop groups are {5, 3, 6, 0, 5, 6, 5 }. The group (7, 8) is selected to be placed at the third level of the scan tree.

(3) Let the scan flip-flop group (3, 4) be selected as the first level for the second scan tree. The measure between (3,4) and any one of (5,6), (9,10), (11,12), (13,14), (15,16) as presented in Equation (1) are {2,2,3,2,1 }. The group (11, 12) is selected and placed at the second level of the second tree. The coordination measures between the second tree and any pair of (5, 6), (9, 10), (13, 14), and (15, 16) are { 8, 7, 5, 4}. That is, the group (5, 6) is selected and placed at the third level of the second tree.

(4) Similarly, the third tree is established as presented in Fig. 4. After constructing the scan trees, we should focus on how to connect scan trees with different XOR outputs. In order to construct the test response compactor, we would like to establish a chain connected graph CCG (N, E). A heuristic algorithm is proposed to construct the test response compactor based on selective test response collection. The node set of the CCG includes all scan chains. Any pair of scan chains C_\ (c_1? <¾, . . . , Cd) and C₂ (c , c , . . . , c'_<*) can be connected to the same XOR gate in the test response compactor if none of the scan flip-flop pairs (cl, c' i), (c2, c'₂), . . . , (cd, c'd) meets the following condition, that is, one scan flip-flop of the pair is selected as the necessary observation scan flip-flop and fault effect of the detected fault by the same test vector is also propagated to the other scan flip-flop of the pair.

Each node C in the CCG is assigned a weight, while each edge is also assigned another weight. The weight w_\ assigned to a node C represents the corresponding summation of the coordination measures for any pair of scan flip-flops in the same chain for all test vectors. Estimation of w_\ for a scan chain is presented in Equation (2). The weight w₂ given by Equation (3) assigned to an edge (C_1? C₂) in the CCG represents summation of the coordination measures between any pair of scan flip-flops in both scan chains C_\ and C₂, where both scan flip-flops do not need to be at the same level. vzV c CjZC 2₎

The test response compactor can be established after the CCG has been generated. Our method first selects the node vi with the most weight. An edge with the most weight, which connects the node Vi and v₂, is chosen. The node with the most weight is selected when multiple edges connected to Vi have the same most weight. The third node v₃, which is connected to both vi and v₂, is further selected similarly if the given number of scan chain in one subset of scan chain driven by the same clock signal still has not been chosen. The node v₃ must have the most weight summation for the edges (v_1? v₃) and (v₂, v₃). The node with the most weight is selected when multiple nodes connected to Vi and v₂ have the most edge weight summation.

The above process continues until the given number of scan chains has been selected or no scan chain can be connected to the XOR tree. The similar scheme is used to construct the second XOR tree when the number of scan chains is no more than the given number for a single subset. This process continues until the number of scan chains has been chosen. The above process continues until all scan chain subsets have been selected.

The CCG for the scan chains as presented in Fig. 3 is established as presented in Fig. 4, where weights for the edges and the nodes are provided. A pair of nodes in the CCG is not connected if connection of two scan chains introduces some aliasing faults. First, the node C₄ with the most weight is selected. The chain C₂ has the most coordination measure with C₄, which is selected and connected to the same XOR tree 0_\. The nodes C₂ and C are deleted from the CCG. The node C_\ is selected, and the other node 5 is connected to the same XOR tree 0₂. The remaining scan chains C₃ and C₆ are connected to the third OR tree 0₃.

Selective encoding is a cost-effective test compression scheme that supports multiple scan chains. The general architecture of the compression method is shown in Fig. 5. A scan slice is a set of test data applied to the multiple scan chain inputs in a cycle. During the compression process, obit slice is decoded into «-bit scan slice, where c

1. In the obit encoded test data, it contains two control bits and c -2 bits of test data, and the control bits dominate the encoding mode of the slice. The number of scan-in pins is an important factor that has impact on the performance of the selective encoding scheme.

The proposed method may introduce high test power, since it only concerns the bits in a scan slice and pays no attention to the adjacent bits in a scan chain. Our scan architecture and test application scheme are quite suitable for this compression method. The proposed low-power scan testing scheme can be compatible with the selective encoding scheme.

A DFT based clock disabling scheme is proposed to reduce test power when the test compression feature is still guaranteed. The proposed clock disabling scheme needs to apply each test vector multiple times. The test application scheme can be implemented by using the repetition function of the ATE. ATE memory includes two parts: one for vector memory and the other for instruction. Usually, the first part dominates the ATE memory. The ATE repetition function requires a little extra amount of ATE memory, which is much less than the vector memory. We shall focus on the details of the scan architecture, test application scheme and test response compaction scheme.

A new test application scheme is proposed based on the scan forest architecture with a clock disabling scheme as presented in Fig. 6, which can effectively compress test data and reduce test power. The new technique compacts test responses very well at the same time. Our method makes the test application cost no more than that of the multiple scan chain designed circuit. In the new test application scheme, the scan trees are partitioned into multiple subsets by finding a trade-off between test application time and test power.

An extra register with reg bits is used, where each bit of the register drives a subset of scan trees. All scan flip-flops in the same scan tree are driven by the same clock signal. Only one bit of the extra register is set to value 1, and all other bits are set to 0. This makes only one subset of scan trees activated in any clock cycle. Let d be the length of the longest scan tree. As shown in Fig. 6, a test vector is shifted into the first subset of scan trees that are driven by the clock signal R'i in d clock cycles. The extra register is then set to the next status. The test vector is continually loaded to the scan trees subset by subset until it has been loaded to all scan trees.

Test responses are captured in the following way. Scan flip-flops in each subset of scan trees capture test response separately. The scan flip-flops keep the test responses after they have captured test responses. The test vector must be loaded to the subset of scan trees again, and the captured test responses are shifted out simultaneously before the next subset of scan trees capture test responses. The above process continues until all subsets of scan trees have captured test responses. The last subset of scan trees shift in the next test vector when shifting out the captured test responses. It is not necessary to refill the last subset of scan trees with the test vector at this point.

In shift cycles, a test vector is shifted into the scan chains subset by subset. Only a subset of scan chains is activated, and all other scan chains are deactivated. Therefore, shift power can be reduced significantly. The scan trees that belong to the same subset capture their test responses in a single capture cycle when other scan trees are deactivated. This reduces the capture power greatly.

A new test application scheme is proposed for the new test response compactor as presented in Fig. 7 based on the selective test response collection, according to which only the necessary subsets of scan chains capture test responses. The scan chain subset that does not need to capture test responses does not need to refill the test vector. Therefore, test application time and test response data can be reduced significantly. The scan chains are partitioned into multiple subsets according to the approximate procedure, where each subset of scan chains is driven by the same clock signal. The test response compactor is established according to the weighted CCG and the approximate procedure.

The scan chain subsets are swept for each test vector by recording the subsets of scan chains that must be observed. A subset of scan chains must capture test responses if at least one of the scan flip-flops in the scan chains is the necessary observation scan flip-flop of any fault detected by the test vector. The compacted test responses from the outputs of the test response compactor must be sent back to the ATE.

We use two extra vectors for each test vector to record whether the corresponding subset of scan chains need to be filled with the test vector, and capture test responses. That is, 4=1 if the test vector must be shifted into the k-th subset of scan chains, otherwise 4=0; ¾=1 if the k-th subset of scan chains must capture test responses. The ordering for the bits is the same as that of the extra register as presented in Fig. 7. The test vector is applied into a subset of scan chains when disabling all other scan chains. The process continues until all scan flip-flops have received the test vector. Each subset of scan chains, which must be observed for the test vector, captures test responses. The test data is again applied into this subset of scan chains when shifting out the captured test responses if at least one more subset of scan chains must capture test responses. The process continues until all recorded subsets of scan chains have captured test responses. The last subset of scan chains, which capture test responses, shift out the test responses when shifting in the next test vector.

We would like to reduce the test application cost by using common part of consecutive test vectors. The common part between the test responses of the previous test vector and the current vector is explored to reduce test application cost, which was combined with a parity-tree-based scan testing scheme. There is an interesting feature for the proposed test application scheme. All scan flip-flops, except the ones in the last subset of scan chains that capture test responses, keep the test data. The scan flip-flops in the last subset of scan chains, that captured test responses of the previous test vector, keep the test responses. It is nice if test vectors can be ordered to utilize the common parts between any consecutive pair of test vectors for test application time reduction.

For each subset of scan chains, it is not necessary to apply the test vector if the previous test vector has the same values as those for the current test vector. Test vectors are ordered after the scan trees and the test response compactor have been established. The test vectors are ordered as follows: a test vector is randomly selected first; the second vector should have the most number of scan chain subsets, whose scan flip-flops are assigned the same values as the first vector; continue the above process until all test vectors are ordered.

The test responses may contain enough unknowns. They may originate from un-initialized memory elements, floating bus drivers, false and multi-cycle paths and other sources that are found in real designs. In this section, we would like to extend the technique to test response compactor construction when the responses contain some unknowns based on the selective test response collection scheme.

Our method clusters scan flip-flops, which are necessary observation scan flip-flops for most test vectors, into the same subset of scan chains. Our method also groups scan flip-flops that produce unknowns into the same groups to tolerate unknowns. We still use the coordination measure to estimate the possibility for any pair of scan flip-flops to produce unknowns. We still use p_v(i, j) to evaluate the possibility for simultaneous observation of any pair of scan flip-flops i and j for test vector v. Determination of the necessary observation scan flip-flops is the same as that presented in Section III.

Another coordination measure uk_v(i, j) is used to cluster the scan flip-flops that produce unknowns in order to avoid aliasing for the test response compactor based on selective test response collection. Each scan chain is still driven by the same clock signal. Let (C_1? C₂, . . . , C_g) be the scan chains in the scan tree, and V be the test set. Our method selects another group G of scan flip-flops (c , c'₂, . . . , c'_g). Our method tries to connect the scan flip-flops c , c'₂, . . . , c'_g to any of C , C₂, . . . , C_g. The summation of the coordination measures for each pair of scan flip-flops placed in the same scan chain should be maximized as presented in Equation(4).

Equation(4) is used to evaluate the coordination measure for test response compactor with unknowns when constructing the scan trees.

In Equation(4), the definition of p_v(i, j) is the same as before, and uk_v(i, j) is the coordination measure to cluster the scan flip-flops that generate unknowns. In Equation(4), C is any one of the scan chains in the scan tree, and c_{ is a scan flip-flop in C . We have uk_v(i, j)=l if both scan Ci C_k and c'_g ε i capture the unknown signal by the vector v £ V. Our method tries to evaluate the coordination measures for a number of scan flip-flop groups, and the scan flip-flop group G with the maximal summation of coordination measures is selected. Our method sets a larger weight for the unknown coordination measure because the unknowns must be avoided in order to deliver the valuable response signals back to the ATE.

A new technique is proposed to establish the test response compactor with unknowns based on the selective test response collection scheme after the scan trees have been constructed. The principle to construct the test response compactor is to minimize the total number of scan chain subsets that are necessary to collect test responses for all test vectors, while the unknowns do not produce any aliasing. Assume that each subset of scan chains is driven by a separate clock signal. We cluster scan chains, which capture test responses of the most common faults for the same test vectors, into the same subset. Simultaneously, the new method also groups the scan flip-flops that simultaneously produce unknowns into the same scan chain subsets. The test response compactor does not need any more extra logic to eliminate unknowns compared to the one with no unknown.

Our method still establishes a chain connected graph CCG (N, E) to construct the test response compactor. The node set of the CCG includes all scan chains. Any pair of scan chains C_\ (c_1? <¾, . . . , Q) and C₂ (c , c , . . . , c'_d) can be connected to the same XOR gate in the test response compactor if none of the scan flip-flop pairs (cl, c ), (c2, c'₂), . . . , (Q, c'_d) meets the following condition, one scan flip-flop of the pair is selected as the necessary observation scan flip-flop and fault effect of the detected fault by any test vector is also propagated to the other scan flip-flop. Any necessary observation scan flip-flop will not be eliminated by any unknowns for any test vector. That is, no unknown test response occurs in the scan chain subset that contains at least one necessary observation scan flip-flop for the test vector. Each node C in the CCG is assigned a weight to construct a test response compactor that tolerates unknowns, while each edge is also assigned another weight. The weight w₃ assigned to a node C represents the corresponding summation of the coordination measures for any pair of scan flip-flops in the same chain for all test vectors. Estimation of w₃ for a scan chain is presented in Equation (5).

The weight w₄ given by Equation (6) assigned to an edge (C_1? C₂) in the CCG represents summation of the coordination measures between any pair of scan flip-flops in both scan chains C , and C₂, where both scan flip-flops do not need to be at the same level.

Claims

1. A method for selective test response collection in digital system testing, comprising:

distributing different scan flip-flops into different scan chains;

constructing a graph model to represent the relationship between scan chains; and,

connecting scan chains with XOR network to do test response compaction.

2. The method according to claim 1, wherein in the step of distributing different scan flip-flops into different scan chains, comprising:

scan cells in the same level within a scan tree have no common predecessor; and,

a summation of coordination measures for each pair of scan flip-flops placed in the same scan chain is maximized.

3. The method according to claim 2, wherein the summation of coordination measure for each pair of scan flip-flops placed in the same scan chain is maximized as presented in the following Equation:

^M =∑∑ ∑ ∑ /V /. J . where p_v(i, j) is the coordination measure corresponding to the test vector v, and C_k is any one of the scan chains in the scan tree.

4. The method according to claim 1, wherein in the step of constructing a graph model to represent the relationship between scan chains, comprising

establishing a chain connected graph CCG (N, E), a node set of the CCG includes all scan chains;

any pair of scan chains C_\ (c_1? <¾, . . . , Q) and C₂ (c , c'₂, . . . , c'_<*) can be connected to the same XOR gate in a test response compactor if none of the scan flip-flop pairs (cl, c ), (c2, c'₂), . . . , (Q, C'_<*) meets the following condition: one scan flip-flop of the pair is selected as a necessary observation scan flip-flop and fault effect of the detected fault by the same test vector is also propagated to the other scan flip-flop of the pair.

5. The method according to claim 4, wherein the chain connected graph CCG (N, E) comprises:

each node C in the CCG is assigned a weight w_\ to represent the corresponding summation of the coordination measures for any pair of scan flip-flops in the same scan chain for all test vectors;

weight w₂ assigned to an edge (C_1? C₂) in the CCG represents a summation of the coordination measures between any pair of scan flip-flops in both scan chains C_\ and C₂, where both scan flip-flops do not need to be at the same level.

6. The method according to claim 1, wherein the step of connecting scan chains with XOR network to do test response compaction comprises:

a node vi with the most weight is selected and an edge with the most weight, which connects the node Vi and v₂, is chosen;

the node with the most weight is selected when multiple edges connected to vi have the same most weight, noted as v_2;

the third node v₃that is connected to both vi and v₂, is further selected similarly if the given number of scan chain in one subset of scan chain driven by the same clock signal still has not been chosen;

wherein the node v₃ has the most weight summation for the edges (vi, v₃) and (v₂, v₃).

7. A method for low-power testing scheme in digital system testing, comprising:

partitioning scan trees into different subsets by finding a trade-off between test application time and test power;

using an extra register with reg bits and each bit of the register drives a subset of scan trees;

capturing responses of scan flip-flops in each subset of scan trees separately;

shifting a test vector into the scan chains subset by subset.

8. The method according to claim 7, wherein in the step of using an extra register with reg bits and each bit of the register drives a subset of scan trees, comprising:

all scan flip-flops in the same scan tree are driven by the same clock signal;

only one bit of the extra register is set to value 1, and all other bits are set to 0; and,

a test vector is continually loaded to the scan trees subset by subset until it has been loaded to all scan trees.

9. The method according to claim 7, wherein in the step of capturing responses of scan flip-flops in each subset of scan trees separately, comprising:

the scan flip-flops keep the test responses after they have captured test responses; and,

the test vector must be loaded to the subset of scan trees again, and the captured test responses are shifted out simultaneously before the next subset of scan trees capture test responses.

10. A method for constructing unknown test response compactor in digital system testing, comprising:

constructing a test response compactor by minimizing a total number of scan chain subsets that are necessary to collect test responses for all test vectors, while the unknowns do not produce any aliasing; and

a coordination measure uk_v(i, j) is used to cluster scan flip-flops that produce unknowns in order to avoid aliasing for the test response compactor based on selective test response collection.

11. The method according to claim 10, wherein in the step of a coordination measure uk_v(i, j) is used to cluster the scan flip-flops, comprising:

a summation of the coordination measures for each pair of scan flip-flops placed in the same scan chain is maximized;

establishing a chain connected graph CCG (N, E), each node C in the CCG is assigned a weight to construct a test response compactor that tolerates unknowns, while each edge is also assigned another weight; a weight w₃ assigned to a node C represents the corresponding summation of the coordination measures for any pair of scan flip-flops in the same chain for all test vectors;

a weight w₄ assigned to an edge (C_1? C₂) in the CCG represents summation of the coordination measures between any pair of scan flip-flops in both scan chains C , and C₂, where both scan flip-flops do not need to be at the same level.