WO2013015573A2 - Field-effect transistor using graphene oxide and method for manufacturing same - Google Patents

Field-effect transistor using graphene oxide and method for manufacturing same Download PDF

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WO2013015573A2
WO2013015573A2 PCT/KR2012/005809 KR2012005809W WO2013015573A2 WO 2013015573 A2 WO2013015573 A2 WO 2013015573A2 KR 2012005809 W KR2012005809 W KR 2012005809W WO 2013015573 A2 WO2013015573 A2 WO 2013015573A2
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graphene oxide
effect transistor
thin film
layer
field effect
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Korean (ko)
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WO2013015573A3 (en
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이상욱
강태원
파닌겐나디
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동국대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Definitions

  • the present invention relates to a field effect transistor, and more particularly, the field effect transistor using a conventional silicon material can be fabricated only on a rigid substrate, while the present invention can be fabricated on a flexible substrate, and particularly used as a channel layer.
  • the graphene oxide that has undergone the reduction process is well dispersed in water, and thus can be manufactured as a suspension, and thus relates to a field effect transistor using graphene oxide and a method for manufacturing the thin film using a printing method.
  • RFID Radio Frequency Identification
  • RFID Radio Frequency Identification
  • RFID technology If RFID technology is widely used, the efficient management of production and logistics will be virtuous cycle by the convergence between information and communication technology and manufacturing industry, which will have a positive effect on the economy and the environment and improve convenience in real life such as health management and disaster relief. It is expected to develop technologies such as manufacturing low-cost RFID tags for RFID distribution.
  • the process of producing RFID tags is divided into antenna manufacturing, chip manufacturing, antenna and chip mounting process, and converting process of attaching double-sided tape for convenient use by consumers.
  • a thin film transistor (TFT) constituting a logic circuit In order to manufacture an RFID tag chip using a printing method, first, a thin film transistor (TFT) constituting a logic circuit must be developed.
  • a widely used device for a thin film transistor is a field effect transistor (FET).
  • FETs used in existing industries have used crystalline silicon or amorphous silicon thin films.
  • the silicon thin film can be manufactured only on a rigid substrate such as glass due to the use of equipment such as vacuum deposition equipment and rigidity, so that the mass production of the roll-to-roll method on the flexible plastic substrate is impossible.
  • the first problem to be solved by the present invention is to provide a field effect transistor that can be fabricated on a flexible substrate, a thin film can be produced using a printing method.
  • the second problem to be solved by the present invention is to provide a field effect transistor manufacturing method capable of manufacturing a flexible and inexpensive electronic products by manufacturing a logic circuit by a printing method on a thin plastic substrate.
  • the present invention in order to achieve the first object, a substrate; A gate electrode formed on the substrate; A dielectric layer formed on the gate electrode; A source electrode and a drain electrode formed on the dielectric layer; And a channel layer connecting the source electrode and the drain electrode to provide a field effect transistor including graphene oxide that has undergone a reduction process.
  • the dielectric layer may be formed of a BaTiO 3 layer or a graphene oxide layer.
  • the present invention a substrate; A graphene oxide layer that has undergone a reduction process formed on the substrate; A source electrode and a drain electrode formed on the graphene oxide layer subjected to the reduction process; A dielectric layer formed on the source electrode and the drain electrode; It provides a field effect transistor including a gate electrode formed on the dielectric layer, using a graphene oxide layer subjected to a reduction process connecting the source electrode and the drain electrode as a channel layer.
  • the present invention comprises the steps of producing a graphene oxide suspension using a graphene oxide powder to achieve the second object; Generating a graphene oxide thin film from the graphene oxide suspension; And heating the generated graphene oxide thin film to reduce the graphene oxide thin film, thereby producing graphene oxide that has undergone a reduction process, wherein the graphene oxide that has undergone the reduction process is formed between a source electrode and a drain electrode.
  • a field effect transistor manufacturing method is provided, which is used as a channel layer.
  • ascorbic acid may be added to the graphene oxide suspension.
  • the method may further include oxidizing graphite to produce the graphene oxide powder.
  • the conductivity of the graphene oxide subjected to the reduction process may be controlled by the degree of reduction determined by the temperature or time of heating the graphene oxide thin film.
  • the graphene oxide thin film may be generated from the graphene oxide suspension using inkjet printing or spin coating.
  • the graphene oxide thin film is heat-treated in an argon atmosphere at 130 to 140 ° C. for 24 hours to reduce the graphene oxide thin film, thereby producing graphene oxide through the reduction process. can do.
  • the field effect transistor using a conventional silicon material can be fabricated only on a rigid substrate, but the present invention can be fabricated on a flexible substrate.
  • the reduced graphene oxide used as a channel layer is dispersed in water. It is possible to manufacture a suspension so that it is possible to produce a thin film using the printing method.
  • a logic circuit is manufactured by a printing method on a thin plastic substrate, flexible and inexpensive electronic products can be manufactured.
  • the charge mobility of the graphene oxide after reduction is currently 200 cm 2 / Vs, but the theoretical charge mobility of graphene reaches 200,000 cm 2 / Vs.
  • the degree of reduction to bring the charge mobility close to the graphene's theory, an ultrafast FET using a graphene oxide thin film as a channel layer can be developed.
  • the semiconductor process can be used to manufacture ultra-high speed devices, and the industrial ripple effect will be great.
  • FIG. 1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a field effect transistor according to another embodiment of the present invention.
  • FIG. 3 is a flowchart illustrating a method of generating a graphene oxide layer that has undergone a reduction process according to an embodiment of the present invention.
  • Field effect transistor is a substrate; A gate electrode formed on the substrate; A dielectric layer formed on the gate electrode; A source electrode and a drain electrode formed on the dielectric layer; And a graphene oxide having a reduction process as a channel layer connecting the source electrode and the drain electrode.
  • the present invention provides a field effect transistor using a reduced graphene oxide thin film having a high charge mobility (50 cm 2 / Vs or more) and excellent dispersibility in water and printing and high chemical stability as a channel layer. It is the content regarding a manufacturing method.
  • FIG. 1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention.
  • the field effect transistor includes a substrate 100, a gate electrode 110, a dielectric layer 120, a source electrode 130, a drain electrode 140, and graphene that have undergone a reduction process. It is composed of an oxide layer 150.
  • the substrate 100 may be a thin plastic substrate such as polyester (PET), polycarbonate (PC), polyvinyl chloride (PVC), poly acrylate (PAR), polyimide (PI), paper, or fiber. .
  • PET polyester
  • PC polycarbonate
  • PVC polyvinyl chloride
  • PAR poly acrylate
  • PI polyimide
  • the gate electrode 110, the source electrode 130, and the drain electrode 140 may be formed of any one of gold, silver, copper, nickel, or aluminum powder in an ink or paste state, such as inkjet printing, offset printing, or screen printing. It can be formed using one of the methods. Drying and curing takes place in the range of 100-140 ° C.
  • the dielectric layer 120 may be formed using one of inkjet printing, offset printing, screen printing, or spin coating by preparing BaTiO 3 powder in ink or paste, or preparing graphene oxide powder in suspension. have. Drying and curing takes place in the range of 100-140 ° C.
  • graphene oxide is an insulator, it can be used as a dielectric layer of FETs, but it is limited to use as a channel layer. However, when graphene oxide is reduced to remove oxygen in the thin film, it becomes conductive and can operate as a channel layer of the FET.
  • the graphene oxide layer 150 subjected to the reduction process may be a channel layer between the source electrode 130 and the drain electrode 140.
  • the gate electrode 110 is formed on the substrate 100, the dielectric layer 120 is formed on the gate electrode 110, and two electrodes are formed on the dielectric layer 120.
  • the graphene oxide layer 150 is formed on the source electrode 130 and the drain electrode 140 through the reduction process, and serves as the electrode 130 and the drain electrode 140. 140) Connect the two electrodes.
  • a voltage is applied to the gate electrode 110 to control the opening and closing of the channel layer while applying a voltage to the source electrode and the drain electrode to flow a current.
  • FIG. 2 is a cross-sectional view of a field effect transistor according to another embodiment of the present invention.
  • the graphene oxide layer 150 which has undergone a reduction process is formed on the substrate 100, and two electrodes are formed on the graphene oxide layer 150 which have undergone the reduction process. 130 and the drain electrode 140, and the dielectric layer 120 is formed on the source electrode 130 and the drain electrode 140 to insulate the two electrodes, and then the gate electrode 110 on the dielectric layer 120. To form.
  • the field effect transistor type shown in FIG. 1 is referred to as a bottom-gate type FET because the gate electrode is formed at the bottom of the FET structure, and the field effect transistor type type shown in FIG. It is called FET of -gate type.
  • the shape can be determined in an advantageous manner depending on the fabrication environment and the state of the peripheral elements formed together on the integrated circuit, respectively.
  • FIG. 3 is a flowchart illustrating a method of generating a graphene oxide layer that has undergone a reduction process according to an embodiment of the present invention.
  • step 310 a graphene oxide suspension is generated using the graphene oxide powder.
  • the graphene oxide powder may be produced by oxidizing graphite.
  • ascorbic acid may be added to the graphene oxide suspension.
  • a graphene oxide thin film is formed from the graphene oxide suspension.
  • the graphene oxide thin film may be formed using the method of inkjet printing or spin coating the graphene oxide suspension.
  • the graphene oxide thin film is heated to reduce the graphene oxide thin film.
  • the graphene oxide thin film generated in step 320 is heat-treated in an argon atmosphere at 130 to 140 ° C. for 24 hours to reduce the graphene oxide thin film, thereby producing graphene oxide that has undergone a reduction process.
  • the conductivity of the graphene oxide subjected to the reduction process is controlled by the degree of reduction determined by the temperature or time of heating the graphene oxide thin film. Further, the degree of reduction may be determined according to the gap between the source electrode and the drain electrode of the field effect transistor.
  • the field effect transistor using the graphene oxide having undergone the reduction process may be manufactured. will be.
  • the present invention is a technique for a thin film transistor (TFT).
  • TFT thin film transistor
  • FET field effect transistor
  • Field effect transistors using a graphene oxide layer that has undergone a reduction process have a wide range of applications, such as RFID-Tag, TFT-LCD, and disposable cell phones.

Abstract

The present invention relates to a field-effect transistor (FET) including a graphene oxide on which a reducing process has been performed, the field-effect transistor comprising: a substrate; a gate electrode formed on the substrate; a dielectric layer formed on the gate electrode; a source electrode and a drain electrode formed on the dielectric layer; and the reduced graphene oxide as a channel layer for connecting the source electrode to the drain electrode. The field-effect transistor of the present invention can be manufactured on a flexible substrate, whereas a conventional FET using silicon material can be manufactured only on a hard substrate. In particular, the reduced graphene oxide used as the channel layer disperses well in water and can thus be manufactured as a suspension, thereby enabling the manufacture of a thin film using a printing method.

Description

그라핀 옥사이드를 이용한 전계효과 트랜지스터 및 그 제조방법Field effect transistor using graphene oxide and its manufacturing method
본 발명은 전계효과 트랜지스터에 관한 것으로서, 더욱 상세하게는 기존의 실리콘 물질을 이용한 전계효과 트랜지스터가 단단한 기판 상에만 제작이 가능한 반면, 본 발명은 유연한 기판상에 제작이 가능하고, 특히 채널층으로 사용되는 환원 과정을 거친 그라핀 옥사이드는 물에 분산이 잘 되어서 현탁액으로 제조가 가능하므로 인쇄법을 이용한 박막 제작이 가능한 그라핀 옥사이드를 이용한 전계효과 트랜지스터 및 그 제조방법에 관한 것이다.The present invention relates to a field effect transistor, and more particularly, the field effect transistor using a conventional silicon material can be fabricated only on a rigid substrate, while the present invention can be fabricated on a flexible substrate, and particularly used as a channel layer. The graphene oxide that has undergone the reduction process is well dispersed in water, and thus can be manufactured as a suspension, and thus relates to a field effect transistor using graphene oxide and a method for manufacturing the thin film using a printing method.
RFID(Radio Frequency Identification) 기술은 개별 물품에 태그를 부착하여 전파를 통해 개별 물품의 정보를 수집, 저장, 및 가공함으로써 사용자에게 다양한 서비스를 제공하는 기술이다. 특히 네트워크와 연동되어 상품의 유통, 재고, 보안, 및 생산관리의 효율성을 증진시키는 등 지능화된 정보 관리에 선도적인 혁신기술로 평가받고 있다.RFID (Radio Frequency Identification) technology is a technology that provides a variety of services to users by tagging individual items to collect, store, and process information on individual items through radio waves. In particular, it is regarded as a leading innovation in intelligent information management by increasing the efficiency of distribution, inventory, security, and production management in conjunction with the network.
대형 물품 단위의 팰릿이나 컨테이너 단위 수준으로 이용되던 것이 최근에는개별 물품 단위의 RFID 서비스로 발전하고 있다. 일반 물류뿐 아니라 의약품, 의류, 도서 등 특수분야까지 시장성이 확대되어 RFID의 성장잠재력은 대단히 커지고 있다.Recently, pallets or container units of large items have been developed to RFID services of individual items. In addition to general logistics, the market potential has expanded to special fields such as pharmaceuticals, clothing, and books.
그러나 RFID 기술에 대한 산업적 기대감이 크고, 시장 또한 매우 큰 것으로 예측되지만 그 보급은 저조하다. 동작 환경에 따라 인식률이 차이 나고, 내구성이 낮다는 단점이 있지만, 특히 바코드에 비해 RFID-태그(Tag)의 가격이 높다는 점이 시장 확산이 느린 가장 큰 이유가 된다. However, while industrial expectations for RFID technology are high and the market is expected to be very large, its penetration is low. The recognition rate is different and the durability is low depending on the operating environment. However, the price of the RFID tag is higher than that of the barcode.
RFID 기술이 널리 보급된다면 정보통신기술과 제조업간의 융합으로 생산과 물류의 효율적인 관리가 선순환되어 경제, 환경 전반에 걸쳐 긍정적인 영향을 주고, 건강관리, 재난구조 등 실생활에 편리성을 증진시킬 수 있을 것으로 기대되므로 RFID 보급을 위해 저렴한 RFID 태그를 제조하는 등의 기술 개발이 필요하다.If RFID technology is widely used, the efficient management of production and logistics will be virtuous cycle by the convergence between information and communication technology and manufacturing industry, which will have a positive effect on the economy and the environment and improve convenience in real life such as health management and disaster relief. It is expected to develop technologies such as manufacturing low-cost RFID tags for RFID distribution.
일반적으로 RFID 태그를 생산하는 공정은 크게 안테나 제조, 칩 제조, 안테나와 칩의 실장 공정, 그리고 소비자가 편리하게 사용할 수 있도록 양면테이프를 붙이는 가공(converting) 공정으로 나뉜다. In general, the process of producing RFID tags is divided into antenna manufacturing, chip manufacturing, antenna and chip mounting process, and converting process of attaching double-sided tape for convenient use by consumers.
칩을 제조하기 위해서는 반도체 공정이 쓰이므로 비용이 많이 소요될 뿐더러, 안테나와 결합하는 실장 공정을 거쳐야만 한다. 그러나 반도체 공정 대신 인쇄법을 이용하여 안테나와 칩을 제조하면 전체적인 공정이 간략화되고, 안테나와 칩의 실장공정을 생략할 수 있으며, 최종적으로 포장가공 공정 또한 간략화되어 그 생산 비용이 매우 절감될 수 있는 장점이 있다.In order to manufacture a chip, a semiconductor process is used, which is expensive and requires a mounting process combined with an antenna. However, if the antenna and chip are manufactured using printing instead of the semiconductor process, the overall process can be simplified, and the mounting process of the antenna and chip can be omitted. Finally, the packaging process can be simplified and the production cost can be greatly reduced. There is an advantage.
인쇄법을 이용해 RFID 태그 칩을 제조하기 위해서는 우선적으로 논리회로를 구성하는 박막형 트랜지스터(Thin Film Transistor, TFT)를 개발해야 한다. 박막형 트랜지스터로 널리 쓰이는 소자는 전계효과 트랜지스터(Field Effect Transistor FET)이다. 기존 산업체에서 사용되는 TFT는 결정형 실리콘 또는 비정질 실리콘 박막 등을 이용해왔다. 그러나 실리콘 박막은 진공 증착 장비 등의 설비를 이용해야 하는 점과 단단한 성질로 인해 유리 등의 단단한 기판상에서만 제작이 가능해서, 유연한 플라스틱 기판 상에 Roll-to-Roll 방식의 대량 생산은 불가능하다.In order to manufacture an RFID tag chip using a printing method, first, a thin film transistor (TFT) constituting a logic circuit must be developed. A widely used device for a thin film transistor is a field effect transistor (FET). TFTs used in existing industries have used crystalline silicon or amorphous silicon thin films. However, the silicon thin film can be manufactured only on a rigid substrate such as glass due to the use of equipment such as vacuum deposition equipment and rigidity, so that the mass production of the roll-to-roll method on the flexible plastic substrate is impossible.
인쇄법을 이용해서 전자제품를 제작하는 사례는 이미 있어왔다. 유기물 또는 카본나노튜브(Carbon Nano Tube, CNT)를 사용해서 인쇄공정으로 TFT를 제작하고, 그 제작한 TFT를 이용하여 논리회로를 구성하여 RFID Tag 등의 전자제품을 만들 수는 있으나, 유기물의 경우 전하 이동도가 낮고(~1 cm2/Vs) 신뢰성이 떨어지는 단점이 지적되고, CNT의 경우는 용매에 대한 분산특성이 저조해 인쇄성이 떨어지는 단점이 있다. 따라서, 유연한 기판상에 제작이 가능하고, 특히 인쇄법을 이용한 박막 제작이 가능한 전계효과 트랜지스터 제조방법이 필요한 실정이다.There has already been an example of manufacturing electronic products using the printing method. Although organic materials or carbon nanotubes (CNT) can be used to produce TFTs in a printing process, and the manufactured TFTs can be used to form logic circuits to make electronic products such as RFID tags. The disadvantage of low charge mobility (~ 1 cm 2 / Vs) and low reliability is pointed out, and in the case of CNTs, there is a disadvantage in that printability is poor due to poor dispersion characteristics in a solvent. Accordingly, there is a need for a method for manufacturing a field effect transistor that can be fabricated on a flexible substrate, and in particular, that a thin film can be fabricated using a printing method.
따라서, 본 발명이 해결하고자 하는 첫 번째 과제는 유연한 기판상에 제작이 가능하고, 인쇄법을 이용한 박막 제작이 가능한 전계효과 트랜지스터를 제공하는 것이다.Therefore, the first problem to be solved by the present invention is to provide a field effect transistor that can be fabricated on a flexible substrate, a thin film can be produced using a printing method.
본 발명이 해결하고자 하는 두 번째 과제는 얇은 플라스틱 기판상에 인쇄법으로 논리회로를 제작함으로써, 유연하고 저렴한 전자제품 제작이 가능한 전계효과 트랜지스터 제조 방법을 제공하는 것이다.The second problem to be solved by the present invention is to provide a field effect transistor manufacturing method capable of manufacturing a flexible and inexpensive electronic products by manufacturing a logic circuit by a printing method on a thin plastic substrate.
본 발명은 상기 첫 번째 과제를 달성하기 위하여, 기판; 상기 기판상에 형성된 게이트 전극; 상기 게이트 전극 상에 형성된 유전체층; 상기 유전체층 상에 형성된 소스 전극과 드레인 전극; 및 상기 소스 전극과 상기 드레인 전극을 잇는 채널층으로써, 환원 과정을 거친 그라핀 옥사이드를 포함하는 전계효과 트랜지스터를 제공한다.The present invention, in order to achieve the first object, a substrate; A gate electrode formed on the substrate; A dielectric layer formed on the gate electrode; A source electrode and a drain electrode formed on the dielectric layer; And a channel layer connecting the source electrode and the drain electrode to provide a field effect transistor including graphene oxide that has undergone a reduction process.
본 발명의 일 실시예에 의하면, 상기 유전체층은 BaTiO3 층 또는 그라핀 옥사이드 층으로 이루어질 수 있다.According to an embodiment of the present invention, the dielectric layer may be formed of a BaTiO 3 layer or a graphene oxide layer.
또한, 본 발명은 상기 첫 번째 과제를 달성하기 위하여, 기판; 상기 기판상에 형성된 환원 과정을 거친 그라핀 옥사이드층; 상기 환원 과정을 거친 그라핀 옥사이드층 상에 형성된 소스 전극과 드레인 전극; 상기 소스 전극과 상기 드레인 전극 상에 형성된 유전체층; 상기 유전체층 상에 형성된 게이트 전극을 포함하고, 상기 소스 전극과 상기 드레인 전극을 잇는 환원 과정을 거친 그라핀 옥사이드층을 채널층으로 이용하는 전계효과 트랜지스터를 제공한다.In addition, the present invention, a substrate; A graphene oxide layer that has undergone a reduction process formed on the substrate; A source electrode and a drain electrode formed on the graphene oxide layer subjected to the reduction process; A dielectric layer formed on the source electrode and the drain electrode; It provides a field effect transistor including a gate electrode formed on the dielectric layer, using a graphene oxide layer subjected to a reduction process connecting the source electrode and the drain electrode as a channel layer.
본 발명은 상기 두 번째 과제를 달성하기 위하여, 그라핀 옥사이드 분말을 이용하여 그라핀 옥사이드 현탁액을 생성하는 단계; 상기 그라핀 옥사이드 현탁액으로부터 그라핀 옥사이드 박막을 생성하는 단계; 및 상기 생성된 그라핀 옥사이드 박막을 가열하여 상기 그라핀 옥사이드 박막을 환원시킴으로써, 환원과정을 거친 그라핀 옥사이드를 생성하는 단계를 포함하고, 상기 환원 과정을 거친 그라핀 옥사이드를 소스 전극과 드레인 전극 사이의 채널층으로 이용하는 것을 특징으로 하는 전계효과 트랜지스터 제조 방법을 제공한다.The present invention comprises the steps of producing a graphene oxide suspension using a graphene oxide powder to achieve the second object; Generating a graphene oxide thin film from the graphene oxide suspension; And heating the generated graphene oxide thin film to reduce the graphene oxide thin film, thereby producing graphene oxide that has undergone a reduction process, wherein the graphene oxide that has undergone the reduction process is formed between a source electrode and a drain electrode. A field effect transistor manufacturing method is provided, which is used as a channel layer.
본 발명의 일 실시예에 의하면, 상기 그라핀 옥사이드 현탁액에 아스크로브산을 첨가할 수 있다.According to one embodiment of the present invention, ascorbic acid may be added to the graphene oxide suspension.
또한, 그라파이트를 산화시켜 상기 그라핀 옥사이드 분말을 생성하는 단계를 더 포함할 수 있다.The method may further include oxidizing graphite to produce the graphene oxide powder.
본 발명의 다른 실시예에 의하면, 상기 환원과정을 거친 그라핀 옥사이드의 전도성은 상기 그라핀 옥사이드 박막을 가열하는 온도 또는 시간에 따라 결정되는 환원정도에 의해 제어될 수 있다. According to another embodiment of the present invention, the conductivity of the graphene oxide subjected to the reduction process may be controlled by the degree of reduction determined by the temperature or time of heating the graphene oxide thin film.
또한, 상기 그라핀 옥사이드 현탁액으로부터 잉크젯 인쇄 또는 스핀코팅의 방법을 이용하여 상기 그라핀 옥사이드 박막을 생성할 수 있다.In addition, the graphene oxide thin film may be generated from the graphene oxide suspension using inkjet printing or spin coating.
본 발명의 또 다른 실시예에 의하면, 상기 생성된 그라핀 옥사이드 박막을 아르곤 분위기에서 130~140 ℃ 범위에서 24시간 열처리하여 상기 그라핀 옥사이드 박막을 환원시킴으로써, 상기 환원과정을 거친 그라핀 옥사이드를 생성할 수 있다.According to another embodiment of the present invention, the graphene oxide thin film is heat-treated in an argon atmosphere at 130 to 140 ° C. for 24 hours to reduce the graphene oxide thin film, thereby producing graphene oxide through the reduction process. can do.
본 발명에 따르면, 기존의 실리콘 물질을 이용한 전계효과 트랜지스터는 단단한 기판 상에만 제작이 가능했지만 본 발명은 유연한 기판상에 제작이 가능하고, 특히 채널층으로 사용되는 환원된 그라핀 옥사이드는 물에 분산이 잘 되어서 현탁액으로 제조가 가능하므로 인쇄법을 이용한 박막 제작이 가능하다.According to the present invention, the field effect transistor using a conventional silicon material can be fabricated only on a rigid substrate, but the present invention can be fabricated on a flexible substrate. In particular, the reduced graphene oxide used as a channel layer is dispersed in water. It is possible to manufacture a suspension so that it is possible to produce a thin film using the printing method.
또한, 본 발명에 따르면, 얇은 플라스틱 기판상에 인쇄법으로 논리회로를 제작한다면 유연하고 저렴한 전자제품 제작이 가능하다. In addition, according to the present invention, if a logic circuit is manufactured by a printing method on a thin plastic substrate, flexible and inexpensive electronic products can be manufactured.
나아가, 본 발명에 따르면, 환원 과정을 거친 그라핀 옥사이드의 전하이동도는 현재 200 cm2/Vs를 기록하지만, 그라핀의 이론적 전하이동도는 200,000 cm2/Vs에 이른다. 환원 정도를 제어하여 전하이동도를 그라핀의 이론치에 근접시킨다면, 환원 과정을 거친 그라핀 옥사이드 박막을 채널층으로 사용한 초고속 FET를 개발할 수 있다. 이 경우 인쇄법뿐 아니라 반도체 공정을 이용하여 초고속 소자를 제작할 수 있어서 그 산업적 파급 효과는 클 것이다.Furthermore, according to the present invention, the charge mobility of the graphene oxide after reduction is currently 200 cm 2 / Vs, but the theoretical charge mobility of graphene reaches 200,000 cm 2 / Vs. By controlling the degree of reduction to bring the charge mobility close to the graphene's theory, an ultrafast FET using a graphene oxide thin film as a channel layer can be developed. In this case, not only the printing method but also the semiconductor process can be used to manufacture ultra-high speed devices, and the industrial ripple effect will be great.
도 1은 본 발명의 일 실시예에 따른 전계효과 트랜지스터의 단면도이다.1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention.
도 2는 본 발명의 다른 실시예에 따른 전계효과 트랜지스터의 단면도이다.2 is a cross-sectional view of a field effect transistor according to another embodiment of the present invention.
도 3은 본 발명의 일 실시예에 따른 환원 과정을 거친 그라핀 옥사이드층을 생성하는 방법을 나타낸 흐름도이다.3 is a flowchart illustrating a method of generating a graphene oxide layer that has undergone a reduction process according to an embodiment of the present invention.
본 발명에 관한 구체적인 내용의 설명에 앞서 이해의 편의를 위해 본 발명이 해결하고자 하는 과제의 해결 방안의 개요 혹은 기술적 사상의 핵심을 우선 제시한다.Prior to the description of the specific contents of the present invention, for the convenience of understanding, the outline of the solution of the problem to be solved by the present invention or the core of the technical idea will be presented first.
본 발명의 일 실시예에 따른 전계효과 트랜지스터는 기판; 상기 기판상에 형성된 게이트 전극; 상기 게이트 전극 상에 형성된 유전체층; 상기 유전체층 상에 형성된 소스 전극과 드레인 전극; 및 상기 소스 전극과 상기 드레인 전극을 잇는 채널층으로써, 환원 과정을 거친 그라핀 옥사이드를 포함한다.Field effect transistor according to an embodiment of the present invention is a substrate; A gate electrode formed on the substrate; A dielectric layer formed on the gate electrode; A source electrode and a drain electrode formed on the dielectric layer; And a graphene oxide having a reduction process as a channel layer connecting the source electrode and the drain electrode.
이하 첨부된 도면을 참조하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있는 바람직한 실시 예를 상세히 설명한다. 그러나 이들 실시예는 본 발명을 보다 구체적으로 설명하기 위한 것으로, 본 발명의 범위가 이에 의하여 제한되지 않는다는 것은 당업계의 통상의 지식을 가진 자에게 자명할 것이다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, these examples are intended to illustrate the present invention in more detail, it will be apparent to those skilled in the art that the scope of the present invention is not limited thereby.
본 발명이 해결하고자 하는 과제의 해결 방안을 명확하게 하기 위한 발명의 구성을 본 발명의 바람직한 실시예에 근거하여 첨부 도면을 참조하여 상세히 설명하되, 도면의 구성요소들에 참조번호를 부여함에 있어서 동일 구성요소에 대해서는 비록 다른 도면상에 있더라도 동일 참조번호를 부여하였으며 당해 도면에 대한 설명시 필요한 경우 다른 도면의 구성요소를 인용할 수 있음을 미리 밝혀둔다. 아울러 본 발명의 바람직한 실시 예에 대한 동작 원리를 상세하게 설명함에 있어 본 발명과 관련된 공지 기능 혹은 구성에 대한 구체적인 설명 그리고 그 이외의 제반 사항이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우, 그 상세한 설명을 생략한다.The configuration of the invention for clarifying the solution to the problem to be solved by the present invention will be described in detail with reference to the accompanying drawings based on the preferred embodiment of the present invention, the same in the reference numerals to the components of the drawings The same reference numerals are given to the components even though they are on different drawings, and it is to be noted that in the description of the drawings, components of other drawings may be cited if necessary. In addition, in describing the operation principle of the preferred embodiment of the present invention in detail, when it is determined that the detailed description of the known function or configuration and other matters related to the present invention may unnecessarily obscure the subject matter of the present invention, The detailed description is omitted.
덧붙여, 명세서 전체에서, 어떤 부분이 다른 부분과 '연결'되어 있다고 할때, 이는 '직접적으로 연결'되어 있는 경우뿐만 아니라, 그 중간에 다른 소자를 사이에 두고 '간접적으로 연결'되어 있는 경우도 포함한다. 본 명세서에서, 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함한다. 명세서에서 사용되는 "포함한다(comprises)" 및/또는 "포함하는(comprising)"은 언급된 구성요소, 단계, 동작 및/또는 소자는 하나 이상의 다른 구성요소, 단계, 동작 및/또는 소자의 존재 또는 추가를 배제하지 않는다.In addition, throughout the specification, when a part is 'connected' to another part, it is not only 'directly connected' but also 'indirectly connected' with another element in between. Include. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.
본 발명은 전하 이동도가 비교적 높으며(50 cm2/Vs 이상) 물에 대한 분산 특성이 우수하여 인쇄가 가능하고, 화학적 안정성이 높은 환원된 그라핀 옥사이드 박막을 채널층으로 사용한 전계효과 트랜지스터와 그 제조 방법에 관한 내용이다.The present invention provides a field effect transistor using a reduced graphene oxide thin film having a high charge mobility (50 cm 2 / Vs or more) and excellent dispersibility in water and printing and high chemical stability as a channel layer. It is the content regarding a manufacturing method.
도 1은 본 발명의 일 실시예에 따른 전계효과 트랜지스터의 단면도이다.1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention.
도 1을 참조하면, 본 실시예에 따른 전계효과 트랜지스터는 기판(100), 게이트 전극(110), 유전체층(120), 소스 전극(130), 드레인 전극(140), 및 환원 과정을 거친 그라핀 옥사이드층(150)으로 구성된다.Referring to FIG. 1, the field effect transistor according to the present embodiment includes a substrate 100, a gate electrode 110, a dielectric layer 120, a source electrode 130, a drain electrode 140, and graphene that have undergone a reduction process. It is composed of an oxide layer 150.
기판(100)은 폴리에스테르(PET), 폴리카보네이트(PC), 폴리비닐클로라이드(PVC), 폴리 아크릴레이트(PAR), 폴리이미드(PI)와 같이 얇은 플라스틱 기판, 종이, 또는 섬유 등이 가능하다.The substrate 100 may be a thin plastic substrate such as polyester (PET), polycarbonate (PC), polyvinyl chloride (PVC), poly acrylate (PAR), polyimide (PI), paper, or fiber. .
게이트 전극(110), 소스 전극(130), 드레인 전극(140)은 금, 은, 구리, 니켈, 또는 알루미늄 분말 중 어느 하나를 잉크 또는 페이스트 상태로 제조하여 잉크젯 인쇄, 오프셋 인쇄, 또는 스크린 인쇄법 중 하나의 방법을 이용하여 형성할 수 있다. 건조 및 경화는 100~140 ℃ 범위에서 이루어진다.The gate electrode 110, the source electrode 130, and the drain electrode 140 may be formed of any one of gold, silver, copper, nickel, or aluminum powder in an ink or paste state, such as inkjet printing, offset printing, or screen printing. It can be formed using one of the methods. Drying and curing takes place in the range of 100-140 ° C.
유전체층(120)은 BaTiO3 분말을 잉크 또는 페이스트로 제조하거나 또는 그라핀 옥사이드 분말을 현탁액 상태로 제조하여 잉크젯 인쇄, 오프셋 인쇄, 스크린 인쇄법, 또는 스핀 코팅법 중 하나의 방법을 이용하여 형성할 수 있다. 건조 및 경화는 100~140 ℃ 범위에서 이루어진다. The dielectric layer 120 may be formed using one of inkjet printing, offset printing, screen printing, or spin coating by preparing BaTiO 3 powder in ink or paste, or preparing graphene oxide powder in suspension. have. Drying and curing takes place in the range of 100-140 ° C.
그라핀 옥사이드는 절연체이므로 FET의 유전체층으로 적용이 가능하지만, 채널층으로 사용하기에는 제한이 따른다. 그러나 그라핀 옥사이드를 환원시켜서 박막내 산소를 제거하면 전도성을 띠게 되며 FET의 채널층으로 동작이 가능하다. Since graphene oxide is an insulator, it can be used as a dielectric layer of FETs, but it is limited to use as a channel layer. However, when graphene oxide is reduced to remove oxygen in the thin film, it becomes conductive and can operate as a channel layer of the FET.
따라서, 환원 과정을 거친 그라핀 옥사이드층(150)은 소스 전극(130)과 드레인 전극(140) 사이의 채널층이 될 수 있다.Therefore, the graphene oxide layer 150 subjected to the reduction process may be a channel layer between the source electrode 130 and the drain electrode 140.
이상에서 살펴본 내용을 종합하면, 기판(100) 상에 게이트 전극(110)을 형성하고, 게이트 전극(110) 상에 유전체층(120)이 있으며, 유전체층(120) 상에 2 개의 전극이 형성되어 소스 전극(130)과 드레인 전극(140) 역할을 하며, 소스 전극(130)과 드레인 전극(140) 상에 환원 과정을 거친 그라핀 옥사이드층(150)이 형성되어 소스 전극(130)과 드레인 전극(140) 두 전극을 잇는다. 전계효과 트랜지스터 소자의 동작은 게이트 전극(110)에 전압을 인가하여 채널층의 개폐를 제어하면서 소스전극과 드레인 전극에 전압을 인가하여 전류를 흐르게 된다. In summary, the gate electrode 110 is formed on the substrate 100, the dielectric layer 120 is formed on the gate electrode 110, and two electrodes are formed on the dielectric layer 120. The graphene oxide layer 150 is formed on the source electrode 130 and the drain electrode 140 through the reduction process, and serves as the electrode 130 and the drain electrode 140. 140) Connect the two electrodes. In the operation of the field effect transistor device, a voltage is applied to the gate electrode 110 to control the opening and closing of the channel layer while applying a voltage to the source electrode and the drain electrode to flow a current.
도 2는 본 발명의 다른 실시예에 따른 전계효과 트랜지스터의 단면도이다.2 is a cross-sectional view of a field effect transistor according to another embodiment of the present invention.
도 2를 참조하면, 기판(100) 상에 환원 과정을 거친 그라핀 옥사이드층(150)을 형성하고, 환원 과정을 거친 그라핀 옥사이드층(150) 상에 2 개의 전극을 형성하여 각각 소스 전극(130)과 드레인 전극(140) 역할을 하며, 소스 전극(130)과 드레인 전극(140) 상에 유전체층(120)을 형성하여 두 전극을 절연시킨 후, 유전체층(120) 상에 게이트 전극(110)을 형성한다.Referring to FIG. 2, the graphene oxide layer 150 which has undergone a reduction process is formed on the substrate 100, and two electrodes are formed on the graphene oxide layer 150 which have undergone the reduction process. 130 and the drain electrode 140, and the dielectric layer 120 is formed on the source electrode 130 and the drain electrode 140 to insulate the two electrodes, and then the gate electrode 110 on the dielectric layer 120. To form.
도 1과 같은 전계효과 트랜지스터 형태는 게이트 전극이 FET 구조의 맨 아래에 형성되어 bottom-gate 형식의 FET라 부르며, 도 2와 같은 전계효과 트랜지스터 형태는 게이트 전극이 FET 구조의 가장 상부에 위치하여 Top-gate 형식의 FET라 일컫는다. 각각 제작 환경과 직접회로 상에 같이 형성되는 주변 소자의 상태에 따라 유리한 방식으로 형태가 결정될 수 있다.The field effect transistor type shown in FIG. 1 is referred to as a bottom-gate type FET because the gate electrode is formed at the bottom of the FET structure, and the field effect transistor type type shown in FIG. It is called FET of -gate type. The shape can be determined in an advantageous manner depending on the fabrication environment and the state of the peripheral elements formed together on the integrated circuit, respectively.
도 3은 본 발명의 일 실시예에 따른 환원 과정을 거친 그라핀 옥사이드층을 생성하는 방법을 나타낸 흐름도이다.3 is a flowchart illustrating a method of generating a graphene oxide layer that has undergone a reduction process according to an embodiment of the present invention.
310 단계에서 그라핀 옥사이드 분말을 이용하여 그라핀 옥사이드 현탁액을 생성한다. In step 310, a graphene oxide suspension is generated using the graphene oxide powder.
상기 그라핀 옥사이드 분말은 그라파이트를 산화시켜 생성할 수 있다. 또한, 상기 그라핀 옥사이드 현탁액에 아스크로브산을 첨가할 수 있다.The graphene oxide powder may be produced by oxidizing graphite. In addition, ascorbic acid may be added to the graphene oxide suspension.
320 단계에서 그라핀 옥사이드 현탁액으로부터 그라핀 옥사이드 박막을 생성한다. In operation 320, a graphene oxide thin film is formed from the graphene oxide suspension.
상기 그라핀 옥사이드 박막은 상기 그라핀 옥사이드 현탁액을 잉크젯 인쇄 또는 스핀코팅의 방법을 이용하여 형성할 수 있다.The graphene oxide thin film may be formed using the method of inkjet printing or spin coating the graphene oxide suspension.
330 단계에서 생성된 그라핀 옥사이드 박막을 가열하여 그라핀 옥사이드 박막을 환원시킨다.The graphene oxide thin film is heated to reduce the graphene oxide thin film.
이때의 환원과정에서 탄소의 sp2 결합이 이루어지면서 전도성을 보이게 된다. 보다 상세하게 살펴보면, 320 단계에서 생성된 그라핀 옥사이드 박막을 아르곤 분위기에서 130~140 ℃ 범위에서 24시간 열처리하여 상기 그라핀 옥사이드 박막을 환원시킴으로써, 환원과정을 거친 그라핀 옥사이드를 생성할 수 있다.At this time, sp 2 bonds of carbon are made in the reduction process, thereby showing conductivity. In more detail, the graphene oxide thin film generated in step 320 is heat-treated in an argon atmosphere at 130 to 140 ° C. for 24 hours to reduce the graphene oxide thin film, thereby producing graphene oxide that has undergone a reduction process.
상기 환원 과정을 거친 그라핀 옥사이드의 전도성은 상기 그라핀 옥사이드 박막을 가열하는 온도 또는 시간에 따라 결정되는 환원정도에 의해 제어된다. 또한, 전계효과 트랜지스터의 소스 전극과 드레인 전극 간격에 맞추어 환원 정도를 결정할 수도 있을 것이다.The conductivity of the graphene oxide subjected to the reduction process is controlled by the degree of reduction determined by the temperature or time of heating the graphene oxide thin film. Further, the degree of reduction may be determined according to the gap between the source electrode and the drain electrode of the field effect transistor.
330 단계에서, 환원 과정을 거친 그라핀 옥사이드를 전계효과 트랜지스터의 소스 전극과 드레인 전극 사이에 배치시켜 채널층으로 이용할 수 있도록 하면, 환원 과정을 거친 그라핀 옥사이드를 이용한 전계효과 트랜지스터를 제조할 수 있을 것이다.In operation 330, if the graphene oxide having been reduced is disposed between the source electrode and the drain electrode of the field effect transistor to be used as a channel layer, the field effect transistor using the graphene oxide having undergone the reduction process may be manufactured. will be.
이상과 같이 본 발명에서는 구체적인 구성 요소 등과 같은 특정 사항들과 한정된 실시예 및 도면에 의해 설명되었으나 이는 본 발명의 보다 전반적인 이해를 돕기 위해서 제공된 것일 뿐, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상적인 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다. In the present invention as described above has been described by the specific embodiments, such as specific components and limited embodiments and drawings, but this is provided to help a more general understanding of the present invention, the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations are possible from these descriptions.
따라서, 본 발명의 사상은 설명된 실시예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐 아니라 이 특허청구범위와 균등하거나 등가적 변형이 있는 모든 것들은 본 발명 사상의 범주에 속한다고 할 것이다.Therefore, the spirit of the present invention should not be limited to the described embodiments, and all the things that are equivalent to or equivalent to the claims as well as the following claims will belong to the scope of the present invention. .
본 발명은 박막형 트랜지스터(Thin Film Transistor, TFT)에 대한 기술이다. 전계효과 트랜지스터(Field Effect Transistor, FET)의 채널층으로써 그라핀 옥사이드 박막을 사용하면 인쇄법 등 간단한 방법을 이용하여 저온 영역에서 유연한 기판상에 트랜지스터의 제조가 가능하다. The present invention is a technique for a thin film transistor (TFT). Using a graphene oxide thin film as a channel layer of a field effect transistor (FET), it is possible to manufacture a transistor on a flexible substrate in a low temperature region using a simple method such as a printing method.
환원 과정을 거친 그라핀 옥사이드층을 이용한 전계효과 트랜지스터는 RFID-Tag, TFT-LCD, 1회용 핸드폰 등 그 적용되는 범위가 넓다.Field effect transistors using a graphene oxide layer that has undergone a reduction process have a wide range of applications, such as RFID-Tag, TFT-LCD, and disposable cell phones.

Claims (9)

  1. 기판 상에 절연체층이 형성되고, 상기 절연체층 상에 금속층이 형성되어 있는 상태에서 상기 금속층 상에 감광제를 형성하는 단계;Forming a photoresist on the metal layer in a state in which an insulator layer is formed on the substrate and a metal layer is formed on the insulator layer;
    상기 형성된 감광제를 노광하고 현상하여 감광제 패턴을 형성하는 단계;Exposing and developing the formed photosensitizer to form a photosensitizer pattern;
    상기 형성된 감광제 패턴을 가열하는 단계; 및Heating the formed photoresist pattern; And
    상기 가열 결과 상기 감광제 패턴을 구성하는 탄소 원자가 상기 금속층을 투과하여 상기 금속층과 상기 절연체층 사이에 그래핀을 형성하는 단계를 포함하는 절연체층 상에 그래핀 박막을 형성하는 방법.Forming a graphene thin film on an insulator layer, wherein the carbon atoms constituting the photoresist pattern as a result of the heating pass through the metal layer to form graphene between the metal layer and the insulator layer.
  2. 제1 항에 있어서,The method of claim 1,
    상기 유전체층은 BaTiO3 또는 그라핀 옥사이드로 이루어진 것을 특징으로 하는 전계효과 트랜지스터.The dielectric layer is a field effect transistor, characterized in that consisting of BaTiO 3 or graphene oxide.
  3. 기판;Board;
    상기 기판 상에 형성된 환원 과정을 거친 그라핀 옥사이드층;A graphene oxide layer that has undergone a reduction process formed on the substrate;
    상기 환원 과정을 거친 그라핀 옥사이드층 상에 형성된 소스 전극과 드레인 전극;A source electrode and a drain electrode formed on the graphene oxide layer subjected to the reduction process;
    상기 소스 전극과 상기 드레인 전극 상에 형성된 유전체층;A dielectric layer formed on the source electrode and the drain electrode;
    상기 유전체층 상에 형성된 게이트 전극을 포함하고,A gate electrode formed on the dielectric layer,
    상기 소스 전극과 상기 드레인 전극을 잇는 환원 과정을 거친 그라핀 옥사이드층을 채널층으로 이용하는 전계효과 트랜지스터.A field effect transistor using a graphene oxide layer that has undergone a reduction process connecting the source electrode and the drain electrode as a channel layer.
  4. 그라핀 옥사이드 분말을 이용하여 그라핀 옥사이드 현탁액을 생성하는 단계;Producing a graphene oxide suspension using the graphene oxide powder;
    상기 그라핀 옥사이드 현탁액으로부터 그라핀 옥사이드 박막을 생성하는 단계; 및 Generating a graphene oxide thin film from the graphene oxide suspension; And
    상기 생성된 그라핀 옥사이드 박막을 가열하여 상기 그라핀 옥사이드 박막을 환원시킴으로써, 환원과정을 거친 그라핀 옥사이드를 생성하는 단계를 포함하고,And heating the generated graphene oxide thin film to reduce the graphene oxide thin film, thereby producing graphene oxide subjected to a reduction process.
    상기 환원 과정을 거친 그라핀 옥사이드를 소스 전극과 드레인 전극 사이의 채널층으로 이용하는 것을 특징으로 하는 전계효과 트랜지스터 제조 방법.The method of manufacturing a field effect transistor comprising using the graphene oxide subjected to the reduction process as a channel layer between a source electrode and a drain electrode.
  5. 제4 항에 있어서,The method of claim 4, wherein
    상기 그라핀 옥사이드 현탁액에 아스크로브산을 첨가하는 단계를 더 포함하는 것을 특징으로 하는 전계효과 트랜지스터 제조 방법.And adding ascorbic acid to the graphene oxide suspension.
  6. 제4 항에 있어서,The method of claim 4, wherein
    그라파이트를 산화시켜 상기 그라핀 옥사이드 분말을 생성하는 단계를 더 포함하는 전계효과 트랜지스터 제조 방법.The method of manufacturing a field effect transistor further comprising the step of oxidizing graphite to produce the graphene oxide powder.
  7. 제4 항에 있어서,The method of claim 4, wherein
    상기 환원과정을 거친 그라핀 옥사이드의 전도성은 상기 그라핀 옥사이드 박막을 가열하는 온도 또는 시간에 따라 결정되는 환원정도에 의해 제어되는 것을 특징으로 하는 전계효과 트랜지스터 제조 방법.The conductivity of the graphene oxide subjected to the reduction process is a field effect transistor manufacturing method characterized in that it is controlled by the degree of reduction determined by the temperature or time of heating the graphene oxide thin film.
  8. 제4 항에 있어서,The method of claim 4, wherein
    상기 그라핀 옥사이드 박막을 생성하는 단계는,Generating the graphene oxide thin film,
    상기 그라핀 옥사이드 현탁액을 잉크젯 인쇄 또는 스핀코팅의 방법을 이용하여 형성하는 것을 특징으로 하는 전계효과 트랜지스터 제조 방법.The graphene oxide suspension is formed by the method of inkjet printing or spin coating method of manufacturing a field effect transistor.
  9. 제4 항에 있어서,The method of claim 4, wherein
    상기 환원과정을 거친 그라핀 옥사이드를 생성하는 단계는,Generating the graphene oxide after the reduction process,
    상기 생성된 그라핀 옥사이드 박막을 아르곤 분위기에서 130~140 ℃ 범위에서 24시간 열처리하여 상기 그라핀 옥사이드 박막을 환원시킴으로써, 환원과정을 거친 그라핀 옥사이드를 생성하는 특징으로 하는 전계효과 트랜지스터 제조방법.The graphene oxide thin film is heat-treated in an argon atmosphere at 130 to 140 ° C. for 24 hours to reduce the graphene oxide thin film, thereby producing a field effect transistor.
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