WO2013013480A1 - 伪随机数生成装置和方法 - Google Patents

伪随机数生成装置和方法 Download PDF

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Publication number
WO2013013480A1
WO2013013480A1 PCT/CN2011/083697 CN2011083697W WO2013013480A1 WO 2013013480 A1 WO2013013480 A1 WO 2013013480A1 CN 2011083697 W CN2011083697 W CN 2011083697W WO 2013013480 A1 WO2013013480 A1 WO 2013013480A1
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shift register
linear feedback
feedback shift
random number
register
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PCT/CN2011/083697
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English (en)
French (fr)
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孙云刚
孙才
陈曦
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中国科学院计算机网络信息中心
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Publication of WO2013013480A1 publication Critical patent/WO2013013480A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/583—Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs

Definitions

  • the present invention relates to communication technologies, and in particular, to a pseudo random number generating apparatus and method. Background technique
  • FIG. 1 is a schematic diagram of a structure of a binary pseudo-random sequence generated by a LFSR in the prior art.
  • the LFSR has an M-order, only A binary pseudo-random sequence 0 and 1 capable of generating a single bit can be formed by splicing the outputs of M mutually independent LFSRs, that is, a single bit of binary random numbers into a vector, thereby forming a random number in the range of 0 - 2M-1, but The complexity of the hardware is greatly increased.
  • FIG. 1 is a schematic diagram of a structure of a binary pseudo-random sequence generated by a LFSR in the prior art.
  • the LFSR has an M-order, only A binary pseudo-random sequence 0 and 1 capable of generating a single bit can be formed by splicing the outputs of M mutually independent LFSRs, that is, a single bit of binary random numbers into a vector, thereby forming a random number in the range of 0 - 2M
  • FIG. 2 is a schematic diagram of the structure of the M-bit pseudo-random number generated by the LFSR in the prior art.
  • the value of the M registers in the LFSR is directly output as a random number vector, but the adjacent clock
  • the data inside the period register has strong correlation, and the uniformity of uniform distribution is poor. It is necessary to use a specific method to remove this correlation before use. For example, complex data is used to interleave the output data to remove correlation. This also greatly increases the complexity of the hardware circuit, therefore, a simple method is needed. Uniformly distributed random numbers independence better. Summary of the invention
  • An embodiment of the present invention provides a pseudo random number generating apparatus, including:
  • first linear feedback shift register and a second linear feedback shift register wherein the first linear feedback shift register and the second linear feedback shift register have opposite displacement directions, and the first linear feedback shift register is used Generating a first register value of k bits at each clock cycle, the second linear feedback shift register for generating a second of the k bits in each clock cycle a register value, according to a direction of displacement of the first linear feedback shift register, respectively, the first register value of the k bits and the k in a direction opposite to a direction of displacement of the second linear feedback shift register
  • the second register values of the bits are connected and logically operated to generate a k-bit random number.
  • An embodiment of the present invention provides a method for generating a pseudo random number by using a pseudo random number generating apparatus provided by the present invention, including:
  • the first register value of the k bits generated by the first linear feedback shift register is respectively according to the second linearity
  • the reverse direction of the shift direction of the feedback shift register, the second register value of the k bits generated by the second linear feedback shift register are connected, and logical operations are respectively performed to generate a k-bit random number.
  • FIG. 1 is a schematic structural diagram of a LFSR generating a binary pseudo-random sequence in the prior art
  • FIG. 2 is a schematic diagram showing a structure of an M-bit pseudo-random number generated by an LFSR in the prior art
  • FIG. 3 is a schematic structural diagram of an embodiment of a pseudo random number generating apparatus according to the present invention.
  • FIG. 5 is a noise autocorrelation curve obtained by the MATLAB simulation using the pseudo random number method provided by the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is directed to directly outputting a value of a register in an LFSR as a random number vector in the prior art, so that data inside the adjacent clock cycle register has strong correlation, and uniformity of uniformity is poor, and the like.
  • a solution that is, a pseudo-random number generating apparatus and method, which logically operates each other by using values of two reverse-shifted linear feedback shift register registers Calculated, the correlation of the internal register values of the LFSR between adjacent clock cycles is removed, and a uniformly distributed random number is generated by a very simple circuit.
  • the apparatus includes: a first linear feedback shift register and a second linear feedback shift register, a first linear feedback shift register and a first
  • the linear feedback shift register has the opposite direction of displacement.
  • the first linear feedback shift register is used to generate a first register value of k bits in each clock cycle
  • the second linear feedback shift register is used to generate at each clock cycle.
  • a second register value of k bits according to the displacement direction of the first linear feedback shift register, the first register value of k bits and the k bits in the opposite direction of the displacement direction of the second linear feedback shift register, respectively
  • the second register value is connected and logically operated to generate a k-bit random number.
  • the first linear feedback shift register is an M-th order shift register, specifically including M flip-flops, an AND gate circuit, and an X0R gate circuit.
  • M DFFs D flip-flops
  • DFF example for explanation
  • the clock terminal is not shown), the generation of the first linear feedback shift register
  • each AND gate of the register is the tap coefficient of the first linear feedback shift register.
  • the first linear feedback shift register is At least one initial value of the flip-flop is set to "1". As shown in FIG. 3, in the first linear feedback shift register in this embodiment, the displacement direction is shifted from left to right in each clock cycle, but not Limited to this.
  • the second linear feedback shift register is an N-th order shift register, and specifically includes N flip-flops and an AND gate circuit and an X0R gate circuit.
  • N DFFs are taken as an example (the clock end of the DFF is not shown)
  • the tap coefficient in order to make the output of the shift register not always "0", set at least one initial value of the flip-flop in the second linear feedback shift register to "1", as shown in FIG. 3, this embodiment
  • the second linear feedback shift register shifts from right to left in each clock cycle, and the first linear feedback shift register and the second linear feedback shift register form two independent, reverse shifted linearities. Feedback shift register.
  • the first register value of k bits can be obtained from the flip-flop of the first linear feedback shift register.
  • Output and obtains an output of a k-bit second register value from a flip-flop of the second linear feedback shift register, and then sequentially sets k bits according to a first linear feedback shift register from left to right displacement direction
  • the output of the first register value is respectively connected to the output of the second register value of k bits in the opposite direction of the direction of the right-to-left displacement of the second linear feedback shift register, and is logically operated to generate k bits.
  • the pseudo-random number which constitutes a 0 ⁇ 2 -1 pseudo-random number that is uniformly distributed and independent of each other. Performing logical operations such as the same OR, XOR, or the like on the output of the flip-flops in the first linear feedback shift register and the second linear feedback shift register, removing the pseudo-random number generated by the prior art Correlation of linear feedback shift register internal register values between adjacent clock cycles.
  • the first linear feedback shift register has 5 D
  • the triggers are DA1, DA2, DA3, DA4, and DA5 from left to right according to the direction of displacement.
  • the second linear feedback shift register has 7 D flip-flops, which are DB1, DB2, and DB3 from right to left according to the direction of displacement.
  • the output of the register value can be taken continuously or at intervals, if the values of 0, 1, and 0 of the three flip-flops of DAI, DA2, and DA4 are respectively obtained, and obtained from the trigger of the second linear feedback shift register.
  • the output of the second register value of 3 bits can be taken continuously or at intervals, if the values of the three triggers DB2, DB3, and DB6 are respectively obtained, 1 0, then, according to the displacement direction of the first linear feedback shift register from left to right, the output of the first register value of 3 bits is respectively and the direction of the displacement from the right to the left according to the second linear feedback shift register
  • the output of the second register value of the three bits in the opposite direction is connected, that is, DA1 is connected to DB6, DA2 is connected to DB3, DA4 is connected to DB2, and an exclusive OR operation is performed to generate a pseudo-random number of 3 bits, that is,
  • the pseudo random number generating apparatus provided in this embodiment has a simple structure, and only needs two sets of reversely shifted linear feedback shift registers and a small amount of combinational logic, and the bit width of the generated pseudo random number can be flexibly changed within a certain range without causing resources.
  • the increment of the pseudo random number generated by the pseudo random number generating device provided by the embodiment is the least common multiple of the run of the two shift registers, and the run of the shift register can be selected to be the longest (2M-1).
  • (2N-1) in the case of a qualitative relationship
  • the following can make the random number generator cycle reach (2M-1) * (2N-1) « 2M+N , and the speed of the generated pseudo-random number is the speed of the clock that drives the trigger displacement, at today's device level. , can reach hundreds of megahertz per second.
  • the pseudo random number generating apparatus removes the correlation of the internal register values of the LFS R between adjacent clock cycles by performing logical operations on the values of the registers of the two linear shift shift registers that are reversely shifted.
  • the generation of uniformly distributed random numbers is achieved with a very simple circuit.
  • the method for generating a pseudo random number by using the above pseudo random number generating apparatus includes: first, at each clock cycle, according to a displacement direction of the first linear feedback shift register, a first bit of k bits generated by the first linear feedback shift register The register values are respectively connected to the second register value of the k bits generated by the second linear feedback shift register in the reverse direction of the displacement direction of the second linear feedback shift register, and respectively perform logical operations to generate k bits. Random number.
  • the embodiment of the method is implemented based on the pseudo-random number generating device provided by the foregoing embodiment.
  • the specific processing procedure refer to the foregoing device embodiment, and details are not described herein again.
  • FIG. 4 is a statistical histogram of the pseudo random number generated by the pseudo random number generating device provided by the present invention, as shown in FIG. 4 .
  • the pseudo random number generating apparatus provided by the present invention generates 100,000 pseudo random numbers, and the abscissa has a data of 100,000, which has been normalized to between -0.5 and 0.5, and the ordinate is each The number of occurrences of the pseudo-random number can be seen from the statistical histogram, and the 100,000 pseudo-random numbers generated by the pseudo-random number generating device provided by the present invention are independent of each other and evenly distributed.
  • the pseudo random number generated by the pseudo random number generating apparatus provided in this embodiment is based on the LFSRs which are mutually reversely shifted, and the correlation of the data of the adjacent clock cycles of the shift register is removed, and the ground noise independence is output.
  • FIG. 5 is a noise autocorrelation curve obtained by the MATLAB simulation using the pseudo random number method provided by the present invention. As shown in FIG. 5, the ordinate on the abscissa is 0, and the remaining abscissa The vertical coordinate corresponding to the upper point is 0, indicating that the independence of the noise is good (the autocorrelation function is the impact function), and the autocorrelation performance of the pseudo random number generated by the pseudo random number generating device provided by the embodiment is verified.
  • the pseudo random number generating apparatus removes the adjacent clock cycles by performing logical operations on the values of the registers of the two linear shift shift registers that are reversely shifted.
  • the correlation of the internal register values of the LFSR enables the generation of independent and evenly distributed random numbers in a very simple circuit.
  • the foregoing method includes the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种伪随机数生成装置和方法，其中该装置包括：第一线性反馈移位寄存器（Linear Feedback Shift Register，LFSR）和第二线性反馈移位寄存器，第一线性反馈移位寄存器和第二线性反馈移位寄存器的位移方向相反，第一线性反馈移位寄存器用于在每个时钟周期产生k个比特的第一寄存器值，第二线性反馈移位寄存器用于在每个时钟周期产生k个比特的第二寄存器值，按照第一线性反馈移位寄存器的位移方向，将k个比特的第一寄存器值分别与按照第二线性反馈移位寄存器的位移方向的反方向的k个比特的第二寄存器值相连接，并分别进行逻辑运算产生k个比特的随机数。通过所提供的伪随机数生成装置和方法，去除了相邻时钟周期之间线性反馈移位寄存器内部寄存器值的相关性，以简单的电路实现了独立均匀分布的随机数的产生。

Description

伪随机数生成装置和方法 技术领域 本发明属于通信技术， 尤其涉及一种伪随机数生成装置和方法。 背景技术
在通信领域， 信号的调制解调、 信号的传输、 信号的加扰和解扰、 信道 模拟等都需要用到随机数， 通常生成随机数的方法有物理方法、 查表法和迭 代法。
迭代法中利用线性反馈移位寄存器 （Linear Feedback Shift Register , LFSR )产生随机数的方法最为常用， 例如图 1为现有技术中 LFSR产生二进 制伪随机序列的结构示意图， 该 LFSR有 M阶， 只能产生单个比特的二进制 伪随机序列 0和 1 , 可以通过将 M个互相独立的 LFSR的输出即单个比特的 二进制随机数拼接成一个向量， 从而形成 0 - 2M-1范围的随机数， 但这样大 大增加了硬件的复杂度， 图 2为现有技术中 LFSR产生 M比特伪随机数结构 示意图，如图 2所示，直接将 LFSR中 M个寄存器的值作为随机数矢量输出， 但相邻时钟周期寄存器内部的数据有着很强的相关性， 均匀分布的独立性较 差， 需要采用特定的方法去除这种相关性才可使用， 例如采用复杂的图样对 输出的数据进行交织来去除相关性， 这也大大增加了硬件电路的复杂度， 因 此， 需要一种简单的方法产生均匀分布的独立性较好的随机数。 发明内容
针对现有技术的上述缺陷， 本发明实施例提供一种伪随机数生成装置和 方法。
本发明实施例提供一种伪随机数生成装置， 包括：
第一线性反馈移位寄存器和第二线性反馈移位寄存器， 所述第一线性反 馈移位寄存器和所述第二线性反馈移位寄存器的位移方向相反， 所述第一线 性反馈移位寄存器用于在每个时钟周期产生 k个比特的第一寄存器值， 所述 第二线性反馈移位寄存器用于在所述每个时钟周期产生所述 k个比特的第二 寄存器值， 按照所述第一线性反馈移位寄存器的位移方向， 将所述 k个比特 的第一寄存器值分别与按照所述第二线性反馈移位寄存器的位移方向的反方 向的所述 k个比特的第二寄存器值相连接， 并分别进行逻辑运算产生 k个比 特的随机数。
本发明实施例提供一种应用本发明提供的伪随机数生成装置产生伪随机 数的方法， 包括：
在所述每个时钟周期， 按照所述第一线性反馈移位寄存器的位移方向， 将所述第一线性反馈移位寄存器产生的 k个比特的第一寄存器值分别与按照 所述第二线性反馈移位寄存器的位移方向的反方向、 所述第二线性反馈移位 寄存器产生的所述 k个比特的第二寄存器值相连接， 并分别进行逻辑运算产 生 k个比特的随机数。
本发明实施例提供的伪随机数生成装置和方法， 通过采用两个逆向移位 的线性反馈移位寄存器的寄存器的值互相进行逻辑运算， 去除了相邻时钟周 期之间 LFSR内部寄存器值的相关性， 以非常简单的电路实现了独立均匀分 布的随机数的产生。 附图说明 图 1为现有技术中 LFSR产生二进制伪随机序列的结构示意图； 图 2为现有技术中 LFSR产生 M比特伪随机数结构示意图；
图 3为本发明伪随机数生成装置实施例结构示意图；
图 4为应用本发明提供的伪随机数生成装置产生的伪随机数的统计直方 图；
图 5为通过 MATLAB模拟利用本发明提供的产生伪随机数方法获取的 噪声自相关曲线。 具体实施方式 本发明针对现有技术中直接将 LFSR中寄存器的值作为随机数矢量输 出， 使得相邻时钟周期寄存器内部的数据有着很强的相关性， 均匀分布的 独立性较差等缺陷， 提供一种解决方案即伪随机数生成装置和方法， 通过 采用两个逆向移位的线性反馈移位寄存器的寄存器的值互相进行逻辑运 算， 去除了相邻时钟周期之间 LFSR内部寄存器值的相关性， 以非常简单 的电路实现了均匀分布的随机数的产生。
图 3为本发明伪随机数生成装置实施例结构示意图， 如图 3所示， 该 装置包括： 第一线性反馈移位寄存器和第二线性反馈移位寄存器， 第一线 性反馈移位寄存器和第二线性反馈移位寄存器的位移方向相反， 第一线性 反馈移位寄存器用于在每个时钟周期产生 k个比特的第一寄存器值， 第二 线性反馈移位寄存器用于在每个时钟周期产生 k个比特的第二寄存器值， 按照第一线性反馈移位寄存器的位移方向， 将 k个比特的第一寄存器值分 别与按照第二线性反馈移位寄存器的位移方向的反方向的 k个比特的第二 寄存器值相连接， 并分别进行逻辑运算产生 k个比特的随机数。
具体地， 第一线性反馈移位寄存器是 M阶移位寄存器， 具体包括 M个 触发器以及 AND门电路和 X0R门电路， 本实施例以 M个 DFF ( D触发器） 为例进行说明 （DFF的时钟端未示出） ， 第一线性反馈移位寄存器的生成
M-1
多项式为 G。(x) = , 其中， 分别位于第一线性反馈移位
0
寄存器的各 AND门电路中为第一线性反馈移位寄存器的抽头系数， 根据移 位寄存器本身的特点， 为了使移位寄存器的输出不总为 " 0" , 将第一线 性反馈移位寄存器中的触发器的初始值至少一个设置为 " 1 " , 如图 3所 示， 本实施例中第一线性反馈移位寄存器在每一个时钟周期， 位移方向为 从左向右移位， 但并不限于此。
第二线性反馈移位寄存器是 N阶移位寄存器， 具体包括 N个触发器以 及 AND门电路和 X0R门电路， 本实施例以 N个 DFF为例进行说明 （ DFF的 时钟端未示出） , 第二线性反馈移位寄存器的生成多项式为 <¾(χ) = ^χ' , 其中， 、 A—i分别位于第二线性反馈移位寄存器的各 AND门电路中 为第二线性反馈移位寄存器的抽头系数， 为了使移位寄存器的输出不总为 " 0" , 将第二线性反馈移位寄存器中的触发器的初始值至少一个设置为 " 1 " ， 如图 3所示， 本实施例中第二线性反馈移位寄存器在每一个时钟 周期， 位移方向为从右向左移位， 第一线性反馈移位寄存器与第二线性反 馈移位寄存器构成两个独立的、 逆向移位的线性反馈移位寄存器。
基于图 3所示的伪随机数生成装置结构示意图， 在每一个时钟周期， 可以从第一线性反馈移位寄存器的触发器中获取 k个比特的第一寄存器值 的输出， 并从第二线性反馈移位寄存器的触发器中获取 k个比特的第二寄 存器值的输出， 然后， 按照第一线性反馈移位寄存器从左向右的位移方向 依次将 k个比特的第一寄存器值的输出 , 分别与按照第二线性反馈移位寄 存器从右向左的位移方向的反方向的 k个比特的第二寄存器值的输出相连 并进行逻辑运算， 产生出 k个比特的伪随机数， 即构成了一个 0~2 -1的服 从均勾分布的且彼此独立的伪随机数。 对第一线性反馈移位寄存器和第二 线性反馈移位寄存器中触发器的输出进行上述连接所进行的逻辑运算比 如同或、 异或等逻辑运算， 去除了现有技术所产生的伪随机数中相邻时钟 周期之间线性反馈移位寄存器内部寄存器值的相关性。
为了更清楚的说明如何利用两个独立的、 逆向移位的线性反馈移位寄 存器产生没有相关性、 均勾分布的伪随机数， 进行举例说明， 假如第一线 性反馈移位寄存器具有 5个 D触发器，按照位移方向自左向右分别为 DA1、 DA2、 DA3、 DA4、 DA5, 第二线性反馈移位寄存器具有 7个 D触发器， 按照 位移方向自右向左分别为 DB1、 DB2、 DB3、 DB4、 DB5、 DB6、 DB7, 假设每 个时钟周期要产生 3个比特的伪随机数， 那么在每一个时钟周期， 从第一 线性反馈移位寄存器的触发器中获取 3个比特的第一寄存器值的输出， 可 以连续取， 也可以间隔的取， 假如分别获取 DAI、 DA2、 DA4三个触发器中 的值 0、 1、 0, 并从第二线性反馈移位寄存器的触发器中获取 3个比特的 第二寄存器值的输出， 可以连续取， 也可以间隔的取， 假如分别获取 DB2、 DB3、 DB6三个触发器中的值 1、 1、 0, 然后， 按照第一线性反馈移位寄存 器从左向右的位移方向依次将 3个比特的第一寄存器值的输出， 分别与按 照第二线性反馈移位寄存器从右向左的位移方向的反方向的 3个比特的第 二寄存器值的输出相连， 即将 DA1与 DB6相连、 DA2与 DB3相连、 DA4与 DB2相连， 分别进行异或运算后产生 3个比特的伪随机数， 即
0®0 = 0,1®1 = 0,0®1 = 1? 所产生的伪随机数为 "0、 0、 1" 。
本实施例提供的伪随机数生成装置结构简单， 只需要两组逆向移位的 线性反馈移位寄存器和少量组合逻辑， 生成伪随机数的位宽在一定范围内 可灵活变化， 而不导致资源的增加， 利用本实施例提供的伪随机数生成装 置产生的伪随机数的周期为两个移位寄存器的游程的最小公倍数， 通常可 以选择移位寄存器的游程达到最长即（2M-1)和（2N-1) , 在游程互质的情况 下可以使得随机数发生器的周期达到（2M- 1) * (2N-1 ) « 2M+N , 并且产生的 伪随机数的速度为驱动触发器位移的时钟的速度， 在当今的器件水平下， 能达到数百兆赫兹每秒。
本实施例提供的伪随机数生成装置， 通过采用两个逆向移位的线性反 馈移位寄存器的寄存器的值互相进行逻辑运算， 去除了相邻时钟周期之间 LFS R内部寄存器值的相关性，以非常简单的电路实现了均匀分布的随机数 的产生。
应用上述伪随机数生成装置产生伪随机数的方法， 包括： 在每个时钟 周期， 按照第一线性反馈移位寄存器的位移方向， 将第一线性反馈移位寄 存器产生的 k个比特的第一寄存器值分别与按照所述第二线性反馈移位寄 存器的位移方向的反方向、 第二线性反馈移位寄存器产生的 k个比特的第 二寄存器值相连接， 并分别进行逻辑运算产生 k个比特的随机数。
本方法实施例是基于上述实施例提供的伪随机数生成装置实现的， 具 体处理流程可以参见上述装置实施例， 此处不再赘述。
利用本实施例提供的伪随机数生成装置产生的伪随机数满足了均匀 分布的统计特征， 图 4为应用本发明提供的伪随机数生成装置产生的伪随 机数的统计直方图， 如图 4所示， 应用本发明提供的伪随机数生成装置产 生 1 00000个伪随机数， 横坐标为 1 00000个数据已被归一化到 - 0. 5 ~ 0. 5 之间， 纵坐标为每个伪随机数出现的次数， 可以从该统计直方图看出， 利 用本发明提供的伪随机数生成装置产生的 1 00000个伪随机数彼此独立， 均匀分布。
利用本实施例提供的伪随机数生成装置产生的伪随机数， 通过采用了 两个互相逆向位移的 LFSR为基础， 去除了移位寄存器相邻时钟周期的数 据的相关性， 输出地噪声独立性极佳， 图 5为通过 MATLAB模拟利用本发 明提供的产生伪随机数方法获取的噪声自相关曲线， 如图 5所示， 在横坐 标为 0的点所对应的纵坐标为 1 , 其余横坐标上的点所对应的纵坐标都为 0 , 说明噪声的独立性好 （自相关函数为冲击函数） ， 经检验利用本实施 例提供的伪随机数生成装置产生的伪随机数的自相关性能很好， 该装置产 生的伪随机序列其自相关性能与 MATLAB中 rand函数产生的噪声的自相关 性无明显差异。 本实施例提供的伪随机数生成装置， 通过采用两个逆向移位的线性反 馈移位寄存器的寄存器的值互相进行逻辑运算， 去除了相邻时钟周期之间
LFSR内部寄存器值的相关性，以非常简单的电路实现了独立均匀分布的随 机数的产生。
本领域普通技术人员可以理解： 实现上述方法实施例的全部或部分步 骤可以通过程序指令相关的硬件来完成， 前述的程序可以存储于一计算机 可读取存储介质中， 该程序在执行时， 执行包括上述方法实施例的步骤； 而前述的存储介质包括： R0M、 RAM , 磁碟或者光盘等各种可以存储程序代 码的介质。
最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对 其限制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通 技术人员应当理解： 其依然可以对前述各实施例所记载的技术方案进行修 改， 或者对其中部分技术特征进行等同替换； 而这些修改或者替换， 并不 使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims

权 利 要 求 书
1、 一种伪随机数生成装置， 其特征在于， 包括：
第一线性反馈移位寄存器和第二线性反馈移位寄存器， 所述第一线性反 馈移位寄存器和所述第二线性反馈移位寄存器的位移方向相反， 所述第一线 性反馈移位寄存器用于在每个时钟周期产生 k个比特的第一寄存器值， 所述 第二线性反馈移位寄存器用于在所述每个时钟周期产生所述 k个比特的第二 寄存器值， 按照所述第一线性反馈移位寄存器的位移方向， 将所述 k个比特 的第一寄存器值分别与按照所述第二线性反馈移位寄存器的位移方向的反方 向的所述 k个比特的第二寄存器值相连接， 并分别进行逻辑运算产生 k个比 特的随机数。
2、 根据权利要求 1所述的伪随机数生成装置， 其特征在于， 所述逻辑运 算包括： 异或运算或者同或运算。
3、 根据权利要求 1或 2所述的伪随机数生成装置， 其特征在于， 所述第 一线性反馈移位寄存器包括 M阶移位寄存器， 所述第二线性反馈移位寄存器 包括 N阶移位寄存器。
4、一种应用如权利要求 1至 3任一所述的伪随机数生成装置产生伪随机 数的方法， 其特征在于， 包括：
在所述每个时钟周期， 按照所述第一线性反馈移位寄存器的位移方向， 将所述第一线性反馈移位寄存器产生的 k个比特的第一寄存器值分别与按照 所述第二线性反馈移位寄存器的位移方向的反方向、 所述第二线性反馈移位 寄存器产生的所述 k个比特的第二寄存器值相连接， 并分别进行逻辑运算产 生 k个比特的随机数。
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