WO2013011848A1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
WO2013011848A1
WO2013011848A1 PCT/JP2012/067302 JP2012067302W WO2013011848A1 WO 2013011848 A1 WO2013011848 A1 WO 2013011848A1 JP 2012067302 W JP2012067302 W JP 2012067302W WO 2013011848 A1 WO2013011848 A1 WO 2013011848A1
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Prior art keywords
data
address
selection
signal
external clock
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PCT/JP2012/067302
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French (fr)
Japanese (ja)
Inventor
佐藤　正幸
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太陽誘電株式会社
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Publication of WO2013011848A1 publication Critical patent/WO2013011848A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Definitions

  • the present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of switching between synchronous and asynchronous in a memory cell.
  • synchronous SRAM Static Random Access Memory
  • asynchronous SRAM asynchronous SRAM
  • asynchronous SRAM does not require consideration of clock control, and is not synchronized with the clock signal. Therefore, compared with synchronous SRAM, it can be accessed without considering clock sharing and the like, and data access is easy. It is used as a main storage device for devices such as control devices and measurement systems. However, since the word line can always be accessed from the outside, the reliability is inferior to that of the synchronous SRAM. *
  • a waiting time called latency occurs between the time when a CPU (Central Processing Unit) makes an access request to the memory and when data is sent to the CPU or when writing is completed, and the processing speed of the CPU decreases. It becomes a factor.
  • memory access requests have high locality in the short term, and reading and writing are often performed sequentially in consecutive areas. Using this feature, consecutive addresses are allocated alternately across multiple memory banks, and an access request is issued to the next address during the delay time for accessing certain data, thereby effectively using the time.
  • the technology is called “memory interleaving”. By increasing the number of memory cell blocks (also referred to as “memory banks”) that can be accessed in parallel from the CPU, the latency can be lowered. *
  • Patent Document 1 discloses an interleave type memory that can operate two memory banks each constituting a cell array block as a synchronous SRAM or an asynchronous SRAM.
  • data to be stored is distributed according to the least significant bit (A0) of the address according to “EVEN” or “ODD”.
  • the disclosed interleaved memory uses an ATD (address transition detection) circuit to recognize access by an external address, and a read signal and an address latch enable (ALE) signal indicating "synchronous" or "asynchronous” It recognizes whether the mode requested by the CPU to the memory is asynchronous mode data reading by random access or data reading in synchronous mode by burst access.
  • ATD address transition detection
  • ALE address latch enable
  • the internal address counter uses the ATD signal and the address to be subjected to burst access to generate a sequential internal address by the increment operation, thereby enabling reading of data for the burst access in the synchronous mode.
  • the disclosed interleaved memory enables data reading in either a synchronous mode or an asynchronous mode for a memory bank, and cannot perform synchronous or asynchronous allocation for each data. Therefore, when only certain data is read synchronously or asynchronously, the entire memory bank has to be synchronous or asynchronous.
  • An object of the semiconductor memory according to the embodiment of the present invention is to enable synchronous or asynchronous data reading for each data.
  • a plurality of memory cells each storing data, and an address signal that identifies the memory cell, and 1 of word lines connected to a part of the plurality of memory cells based on the decoded address
  • An address decoder that outputs a word line selection signal for selecting one, a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data, and the external clock is selected
  • the plurality of memory cells selected based on the word line selection signal without being synchronized with the external clock in synchronization with the selected external clock or when the external clock is not selected.
  • a semiconductor memory device comprising: a data reading unit that reads data from a part of the semiconductor memory device.
  • An address change detection unit that detects a change in an address signal and a clock generation circuit that generates an internal clock are further provided, and the address decoder detects the change in address when the address change detection unit detects an address change.
  • the selection unit outputs a selection signal, the selection unit selects the internal clock based on the selection data, and the data reading unit synchronizes with the internal clock when the external clock is not selected,
  • the semiconductor memory device according to (1), wherein data is read from a part of the plurality of memory cells selected based on the word line selection signal.
  • the address decoder includes: an X address decoder that outputs the word line selection signal; a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address;
  • the semiconductor memory device according to (2) comprising: (4) The selection data is held in some memory cells of the memory cell array, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell.
  • the semiconductor memory device according to any one of (1) to (3).
  • An address decoder that outputs a word line selection signal for selecting a signal, a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data, and the external clock is selected The external clock is synchronized with the selected external clock or when the external clock is not selected.
  • the semiconductor device characterized by without synchronization, and a data reading unit for reading the data for some of the plurality of memory cells selected on the basis of said word line selection signal.
  • An address change detection unit that detects a transition of an address signal and a clock generation circuit that generates an internal clock are further provided.
  • the address decoder selects the word line when the address change detection unit detects an address change.
  • the selection unit selects the internal clock based on the selection data, and the data reading unit synchronizes with the internal clock when the external clock is not selected.
  • the semiconductor device according to (5) wherein data is read from a part of the plurality of memory cells selected based on a word line selection signal.
  • the address decoder includes: an X address decoder that outputs the word line selection signal; a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address;
  • the semiconductor device according to (5) or (6).
  • the selection data is held in some memory cells of the memory cell array, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell.
  • the selection data is set to be synchronized with an internal clock when the logic unit operates as a combinational circuit or wiring logic, and is synchronized with an external clock when the logic unit operates as a sequential circuit.
  • the semiconductor device according to (8).
  • the semiconductor memory device can perform synchronous or asynchronous data reading for each data. Since specific data in the SRAM does not make the entire memory cell synchronous or asynchronous, the reliability of the synchronous SRAM and the high speed of the asynchronous SRAM can be provided at the same time.
  • FIG. 1 is a diagram illustrating a first example of a semiconductor memory device according to the present embodiment.
  • FIG. 2 is a detailed example of the memory element.
  • FIG. 3 is a detailed example of the address decoder.
  • FIG. 4 is a diagram illustrating a second example of the semiconductor memory device according to the present embodiment.
  • FIG. 5 is a diagram illustrating a detailed example of the precharge circuit.
  • FIG. 6A is a detailed example of an ATD circuit.
  • FIG. 6B is a time chart of signals flowing through the ATD circuit.
  • FIG. 7 is a diagram illustrating a third example of the semiconductor memory device according to the present embodiment. These are figures which show an example of MPLD which used the semiconductor memory device as MLUT.
  • FIG. 9A is a diagram illustrating an example of an MPLD.
  • FIG. 9B is a diagram illustrating an example of an MPLD memory operation.
  • FIG. 9C is a diagram illustrating an example of the logical operation of the MLUT.
  • FIG. 10 is a diagram illustrating an example of an MLUT.
  • FIG. 11 is a diagram illustrating an example of an MLUT that operates as a logical element.
  • FIG. 12 is a diagram illustrating an example of an MLUT that operates as a logic circuit.
  • FIG. 13 is a diagram showing a truth table of the logic circuit shown in FIG.
  • FIG. 14 is a diagram illustrating an example of an MLUT that operates as a connection element.
  • FIG. 15 is a diagram showing a truth table of the connection elements shown in FIG. FIG.
  • FIG. 16 is a diagram illustrating an example of a connection element realized by an MLUT having four AD pairs.
  • FIG. 17 is a diagram illustrating an example in which one MLUT operates as a logical element and a connection element.
  • FIG. 18 shows a truth table of the logic elements and connection elements shown in FIG.
  • FIG. 19 is a diagram illustrating an example of logical operations and connection elements realized by an MLUT having an AD pair.
  • FIG. 1 is a diagram illustrating a first example of a semiconductor memory device.
  • a semiconductor memory device 100 shown in FIG. 1 includes a memory cell array 110 including memory cells each storing data, an address decoder 120, a selection unit 130 for selecting an external clock supplied from the outside, and selection of an external clock.
  • the data input / output unit 140 is configured to read data from or write data to the memory cell array 110 in accordance with the presence or absence of data.
  • the memory cell array has m ⁇ 2 m memory elements, and the m ⁇ 2 n memory elements are arranged at a connection portion between 2 n word lines and m bit lines.
  • FIG. 2 is a detailed example of the memory element.
  • the storage element 40 shown in FIG. 2 includes pMOS transistors 161 and 162 and nMOS transistors 163, 164, 165, and 166.
  • the source of the pMOS transistor 161 and the source of the pMOS transistor 162 are connected to VDD (power supply voltage terminal).
  • the drain of the nMOS transistor 163 and the drain of the nMOS transistor 164 are connected to VSS (ground voltage terminal).
  • the drain of the nMOS transistor 165 is connected to the bit line b.
  • the gate of the nMOS transistor 165 is connected to the word line WL.
  • the drain of the nMOS transistor 166 is connected to the bit line / b.
  • the gate of the nMOS transistor 166 is connected to the word line WL.
  • the storage element 40 changes the signal level transmitted from the bit line b and the bit line / b according to the signal level “H (High)” of the word line WL to the pMOS transistors 161 and 162 and the nMOS. This is held in the transistors 163 and 164.
  • the memory element 40 causes the signal levels held in the pMOS transistors 161 and 162 and the nMOS transistors 163 and 164 to be applied to the bit line b and the bit line / b according to the signal level “H” of the word line WL. Tell. *
  • FIG. 3 is a diagram showing a detailed example of the address decoder.
  • the address decoder 120 shown in FIG. 3 includes an inverter circuit 120-1, an AND circuit 120-2, and an AND circuit 120-3. There are n inverter circuits 120-1 for every n address signal lines. There are 2 n AND circuits 120-2 and 120-3, respectively. *
  • the inverter circuit 120-1 inverts the logic of the address signal received from the n address signal lines and outputs the inverted address signal to the AND circuit 120-2.
  • the AND circuit 120-2 receives the address signal and the inverted address signal as input signals. When the signal levels of all input values are “H”, the AND circuit 120-2 outputs the signal level “H” to the second AND by the AND operation. Output to the circuit.
  • the AND circuit 120-3 receives the output of the AND circuit 120-2 and an internal clock (described later) as input signals. When the signal levels of all the input values are “H”, the signal level “H” is obtained by a logical product operation. Is output. *
  • the word line selection signal has a signal level “H”, and the word line non-selection signal has a signal level “L (Low)”.
  • the address decoder 120 is configured to output a word line selection signal having a signal level “H” to one word line out of 2 n word lines.
  • the address decoder 120 decodes an address signal received from n address signal lines, and outputs a word line selection signal as a decode signal to 2 n word lines WL.
  • the selection unit 130 is a selection circuit that transmits an external clock supplied from the outside to the data input / output unit 140 based on selection data supplied from the outside.
  • the selection unit 130 is a plurality of selection circuits provided individually for each data output line, and each selection circuit holds selection data supplied from the outside.
  • the selection data may be supplied from the memory cell array 110.
  • each selection circuit is connected to a specific memory cell (selection data memory cell) in the memory cell array 110.
  • selection data memory cell When the signal level of the selection data memory cell is “H”, the signal level of the selection data When the signal level of the memory cell for selected data is “L”, the signal level of the selected data is also “L”.
  • the selection circuit When the signal level of the selection data is “L”, the selection circuit transmits the external clock to the data input / output unit 140, and the read data Q corresponding to the selection circuit is read in synchronization with the external clock.
  • the signal level of the selection data is “H”, the selection circuit does not transmit the external clock to the data input / output unit 140, and the read data Q corresponding to the selection circuit is read asynchronously with the external clock.
  • the data input / output unit 140 When the data input / output unit 140 receives the write enable (WE) edge timing and the write data from the outside, the data input / output unit 140 transmits the signal level of the write data to the m bit lines b and / b, and writes it to the memory cell. Write data.
  • the data input / output unit 140 outputs read data by outputting the signal levels of the m bit lines b and / b to the outside.
  • the semiconductor memory device 100 can perform data reading synchronously or asynchronously for each data. Since specific data in the SRAM does not make the entire memory cell synchronous or asynchronous, the reliability of the synchronous SRAM and the accessibility of the asynchronous SRAM can be provided at the same time. *
  • FIG. 4 is a diagram illustrating a second example of the semiconductor memory device.
  • a semiconductor memory device 100A shown in FIG. 3 includes a memory cell array 110, address decoders 120A and 120B, a selection unit 130A, a bit line precharge circuit 135, and a data input / output unit 140A. *
  • the X column has 2 5 word lines
  • the Y column has 2 squares ⁇ 7 and 1 prepared for reading and writing, respectively.
  • the bit lines are formed in a grid pattern vertically and horizontally, and the memory cells are arranged at the intersections of the word lines and the bit lines. Therefore, it has 2 7 ⁇ 7 (7 + 1) memory cells, of which 7 memory cells are the memory cells for selection data described above. *
  • the address decoder 120 described in FIG. 1 includes an X address decoder 120A for the X column and a Y address decoder 120B for the Y column in FIG. 4, and the X address decoder 120A and the Y address decoder 120B include the address signal lines A0 to A0. A4 and address signal lines A5 to A6 are respectively connected. When the number of address signal lines increases, the memory cell shape can be extended in the X-axis direction by dividing into X-column and Y-column decoders as shown in FIG. *
  • the memory cell for selection data holds selection data, and signals of the selection data are set as control signals for the selection circuit as S0, S1,..., S6. *
  • the X address decoder 120A includes an ATD circuit (Address Transition Detect) 121 as an address change detection unit.
  • the ATD circuit is a circuit that is provided at an address input terminal, detects a change in an address input signal applied to the address input terminal, and outputs the changed address signal. A detailed example of the ATD circuit will be described later with reference to FIGS. *
  • the ATD circuit Since the ATD circuit outputs the changed address signal to the X address decoder 120A only when it detects a change in the address signal, the X address decoder 120A outputs a word line selection signal only when the address signal changes, When the signal does not change, the word line selection signal is not output. In this way, when there is no address change, the word line selection signal is not output, so that a write malfunction due to disturbance noise can be prevented. Further, the X address decoder 120A reduces the number of address lines for activating word lines as compared with the address decoder 120 shown in FIG. 1, so that when an address change occurs, noise is mixed into the memory cell via the word line. Can reduce the possibility of *
  • the X address decoder 120A has a clock generation circuit 122 for generating an internal clock.
  • the internal clock is also used as a flip-flop of the data input / output unit 140 and a synchronization signal of the ATD circuit 121.
  • the output variation of the word line selection signal can be suppressed in synchronization with the internal clock.
  • the high speed of the asynchronous SRAM can be achieved.
  • the internal clock may have a different period from that of the external clock, and the internal clock may have a shorter period than the external clock in order to obtain the high speed of the asynchronous SRAM that can be accessed without being synchronized with the external clock as an asynchronous SRAM. preferable.
  • the example in which the ATD circuit 121 and the clock generation circuit 122 are provided in the X address decoder 120A has been described.
  • the ATD circuit 121 and the clock generation circuit 122 may be provided separately from the X address decoder 120A.
  • the ATD circuit 121 needs to be provided in the upper stage of the X address decoder 120A in order to detect address transition.
  • the Y address decoder 120B is a plurality of selection circuits, each of which may be provided for every seven data lines. In that case, each selection circuit selects one bit pair b, / b as an output or input data line from the four bit pairs according to the address signals A5, A6. *
  • the bit line precharge circuit 135 precharges both the bit line b and the bit line / b to “1”. *
  • FIG. 5 shows a detailed example of a bit line precharge circuit for one bit line pair.
  • the bit line precharge circuit 135a for one bit line pair has two PMOSs, and the input of the bit line precharge circuit 135a is connected to the memory cell via the bit line b and the bit line / b.
  • the output of the bit line precharge circuit 135a is connected to the Y address decoder via the bit line b and the bit line / b.
  • the bit line precharge circuit 135a precharges the signal level of the bit line pair b, / b to “H” according to the internal clock.
  • Such a bit line precharge circuit 135 a for one bit line pair is provided for each bit line pair b, / b of the memory cell array 110. *
  • the PMOS When the clock is input and the signal level becomes “H”, the PMOS is turned off, so that the connection with VDD is cut off, and the bit line outputs the level based on the information of the memory cell.
  • the signal level of the clock becomes “L”
  • the PMOS When the signal level of the clock becomes “L”, the PMOS is turned on and the bit line is pulled up to the potential of VDD. In this manner, the bit line is connected to the memory cell only when the clock is input, thereby preventing a write malfunction due to disturbance noise to the memory cell.
  • the selection unit 130A is a plurality of selection circuits provided for each data output line, like the selection unit 130 shown in FIG. 1, and each of the selection circuits holds selection data. To do.
  • the selection unit 130A differs from the selection unit 130 in that when the selection circuit has a signal level “H” of the selection data, the external clock is not transmitted to the data input / output unit 140 but the internal clock is transmitted to the data input / output unit 140.
  • One bit line is added to the memory cell array 110 as D7.
  • the internal signal of the memory cell at address D7 is S0
  • the internal signal of the memory cell at address 2 is S1
  • the signals up to the internal signal S7 of the memory cell at address 7 are the internal and external clocks of the output latch clock. Select signal. *
  • the memory cell array 110 can be downsized. Further, an existing memory cell may be used for storing selection data without newly providing a memory cell for storing selection data. *
  • a register for receiving external data is required. Further, externally, write control for registers is required. If the selection data is written in the memory cell, the selection circuit can be controlled from the outside without requiring new writing control.
  • the output does not change even if the address changes, but asynchronous operation operates according to the internal clock if the address changes. In this way, if the internal clock has a shorter period than the external clock, data access is possible with higher immediacy. Therefore, as in the case of asynchronous SRAM, when high speed is required when not synchronizing with an external clock, the internal clock needs to have a shorter cycle than the external clock.
  • the data input / output unit 140 has a plurality of flip-flops (F / F) provided for each output data line (D-type flip-flop in the example shown in FIG. 3), and D at the rising edge of the C (CLOCK) terminal.
  • the input value is held as the Q output. That is, the output is changed only at the clock, and the information is held otherwise.
  • the bit line can be set to the “H” state, and a margin can be ensured when the device voltage is lowered.
  • the sense amplifier since there are 32 word lines and the signal level is less deteriorated, the sense amplifier is not shown. However, when the number of word lines increases due to an increase in addresses and memory cells, the bit line precharge is performed. A sense amplifier or a write amplifier may be provided between the circuit 135 and the Y address decoder 120B. *
  • the memory cell shown in FIG. 2 is a single-port memory cell, but may be a double-port memory cell when a high-speed memory cell that performs reading and writing simultaneously is used. *
  • the semiconductor memory device 100A since the semiconductor memory device 100A does not output a word line selection signal when there is no address change, it can prevent a write malfunction due to disturbance noise, and can provide an external clock and an internal clock for each data line. Can be switched. *
  • FIG. 6A is a diagram illustrating an example of an ATD circuit.
  • the ATD circuit 121 shown in FIG. 6A includes, as indicated by 121-1, a flip-flop (F / F), a delay circuit (DC), an AND circuit that performs a logical product operation, an XOR circuit that performs an exclusive logical sum operation, An OR circuit that performs a logical sum operation and a transmission gate (TG) are included.
  • the AND circuit, XOR circuit, and OR circuit are indicated by MIL symbols. *
  • the ATD circuit 121 detects an address change by a combination of the XOR circuit and the delay circuit.
  • FIG. 6B shows a time chart of the ATD circuit shown in FIG. 6A.
  • 6A and 6B corresponds to an address signal input from the outside
  • ai corresponds to a signal input branched from the upper stage of the inverter circuit 120-1 shown in FIG. 3, and ai with an overline is shown in FIG.
  • An output signal of the inverter circuit 120-1 shown ⁇ 1 is a feedback signal input from the TG to the flip-flop clock, and ⁇ 2 is a feedback signal input to the AND circuit. *
  • the flip-flop receives ⁇ 1 synchronized with the internal clock as a clock and holds the address signal at the rising edge of the clock.
  • the XOR circuit When the address of the previous cycle is different from the address of the current cycle, the XOR circuit outputs a signal level “H”, and the signal is output from the TG as ⁇ 2.
  • the flip-flop that receives ⁇ 2 as a clock outputs the address held in the cycle ⁇ 1.
  • the AND circuit outputs the address of ⁇ 1 cycle as the address ai when the signal level of the address of ⁇ 1 cycle output from the flip-flop in the cycle of ⁇ 2 is the same as the signal level of ⁇ 2. In this way, the ATD circuit outputs the changed address signal to the address decoder only when detecting an address change.
  • FIG. 7 is a diagram illustrating a third example of the semiconductor memory device.
  • the semiconductor memory 100B shown in FIG. 7 is the same as the semiconductor memory 100A shown in FIG. 3 in other configurations, except that the ATD circuit 121A detects changes in all address signals.
  • the ATD circuit 121A detects changes in all address signals.
  • the ATD circuit 121A detects changes in the signals A0 to A4, it outputs a word line selection signal for the memory cell array 110, and changes the signals in A5 and A6.
  • a signal is output to Y address decoder 120B.
  • the address change detected by the ATD circuit 121A is the addresses A5 and A6 shown in FIG. 7, the address is supplied to the Y address decoder 120B, and is not supplied when there is no address change. *
  • the word line is selected only by the X address and the Y address only selects the data output by the bit line, it is not directly related to noise countermeasures for the data stored in the memory cell array 110.
  • the Y address is also used by the Y address decoder 120B to select output data, a malfunction may occur in which data is output from a non-target memory cell due to an address mutated by external noise. Therefore, the malfunction of data output due to external noise can be prevented by inputting the Y address via the ATD circuit 121A.
  • MPLD Memory Based Programmable Logic Device
  • MPLD is also a reconfigurable device that uses SRAM
  • MLUT Multi Look-Up-Table
  • MLUT Multi Look-Up-Table
  • the MLUT is used as the logic as the wiring
  • the delay with the synchronous clock in the MLUT is a big problem
  • the asynchronous SRAM is used.
  • Asynchronous SRAMs output in accordance with address switching, so that they are good structures for solving the delay problem as MPLD MLUTs.
  • the bit line is driven by the memory cell, the size of the transistor tends to be large.
  • the word line is always selected, the data is rewritten due to noise at the time of reading, causing a malfunction of the MPLD.
  • future semiconductor miniaturization semiconductor process after 90 nm
  • the problem is that in the case of a synchronous SRAM, writing and reading can be performed only during clock operation, and in other states, the word line can be deselected to protect the memory cell state.
  • the bit line can be set to Hi level except during reading, so that the memory cell state can be maintained even when the voltage of the device is lowered, and the voltage is reduced by miniaturization. It can correspond to.
  • the synchronous SRAM is read / write only with the synchronous clock, and the clock stage number delay for each number of MLUT stages such as wiring cannot be seen and used.
  • MPLD in a conventional asynchronous SRAM can express wiring and combinational circuits, but cannot express sequential circuits.
  • a sequential circuit can be configured by adding F / F to the AD pair 7 of the MLUT with a limited number of MPLDs (AD pair not connected to the surrounding MPLD among the seven AD pairs).
  • the F / F is insufficient in the sequential circuit representation and the wiring MLUT must be provided between the F / Fs, the operation speed is limited.
  • the number of F / Fs used is limited because the limited AD pairs have F / Fs, and in the prior art (for example, Japanese Patent Application Laid-Open No. 2010-239325), F / Fs are limited. Since the output of F is returned to its own MLUT, when a sequential circuit is configured, a signal is returned to its own MLUT (MLUT ⁇ F / F), and the MLUT is wired by MLUT, which adversely affects mounting efficiency.
  • the AD pair of the MLUT must have a built-in F / F and a general F / F connection state such as MLUT ⁇ F / F ⁇ MLUT must be established.
  • This can be realized by using a synchronous SRAM, but it is detrimental in MLUT representation with wiring and combinational circuits.
  • the asynchronous SRAM cannot operate at a low voltage corresponding to miniaturization, synchronization corresponding to miniaturization is necessary.
  • FIG. 8 is a diagram illustrating an example of an MPLD using a semiconductor memory device as an MLUT.
  • the MPLD 20 shown in FIG. 8 has a plurality of MLUTs 30.
  • the rectangle in the MLUT 30 is an F / F provided for each data output line that can be switched by the selection signal described in the semiconductor memory device. This F / F corresponds to the F / F of the data input / output unit 140.
  • 6-way MLUT (Six MLUTs are arranged around one MLUT, and the MLUT in the center and the six MLUTs in the periphery are each connected by one AD pair.
  • six MLUTs Address lines are connected to the other six MLUT data lines arranged in the periphery, and the six MLUT data lines are connected to the other MLUT address lines of the MLUT, respectively.
  • Is capable of providing a uniform connection to the AD pair but a circuit having two CLA (carrier look-ahead) circuits such as a multiplier circuit can implement the circuit within its own MLUT.
  • the logical configuration efficiency is poor.
  • alternating arrangement (eight MLUTs are arranged around one MLUT, and four MLUTs in the periphery are connected to an AD pair, and two MLUTs are connected by two AD pairs. 1 (disclosed in FIG. 1 of 2010-239325) can have two AD pairs in adjacent MLUTs, and in this case, the alternate arrangement is advantageous.
  • the MLUT arranged in 6 directions can reduce the number of MLUTs operating as connection elements, so that the total amount of storage element blocks constituting a desired logic circuit can be reduced, so that an MLUT arranged in 6 directions is possible. It is preferable to use as much as possible.
  • the separated wiring is an AD pair wiring that connects MLUTs that are not short-distance wiring.
  • the MLUT can be saved in the long distance wiring.
  • the AD pair 7 is used and the necessary F / F is connected to the sequential circuit, the F / F has a structure that returns to its own MLUT.
  • the separated wiring and the F / F are mixed at a certain ratio. If a sequential circuit is configured in this relationship, an MLUT as a connection element is required, and the logical configuration efficiency is poor. *
  • the semiconductor memory device shown in FIG. 1, 4 or 7 is used as the MLUT.
  • the MLUT shown in FIG. 8 is an example in which the semiconductor memory device shown in FIG. 1, 4 or 7 is used as a MLUT arranged in six directions. Since the MLUT (semiconductor memory device) itself has an F / F and there is no need to use an AD pair to connect to an external F / F, the AD pair 7 can all be used for separated wiring. . *
  • the selection data can be defined by the memory cell for selection data in the memory cell array 110. Therefore, the circuit realized by the MLUT needs to be synchronized.
  • the MLUT can be divided into a circuit and a circuit that does not require synchronization, or a single MLUT can be used separately for a circuit that requires dynamic synchronization and a circuit that does not require synchronization.
  • MLUT is set for each data line so that it is synchronized for each data line as an internal clock when asynchronous is required in the combinational circuit or wiring logic, and is synchronized for each data line with an external clock when it is a sequential circuit. can do.
  • FIG. 9A is a diagram showing a detailed example of MPLD.
  • Reference numeral 20 shown in FIG. 9A denotes an MPLD as a semiconductor device.
  • the MPLD 20 includes a plurality of MLUTs 30 serving as storage element blocks and an MLUT decoder 12. As will be described later, the MPLD 20 operates as a logic unit connected to the arithmetic processing unit. *
  • the MPLD 20 includes a plurality of storage elements. Since the data constituting the truth table is stored in the memory element, the MPLD 20 performs a logic operation that operates as a logic element, a connection element, or a logic element and a connection element. *
  • the MPLD 20 further performs a memory operation.
  • the memory operation refers to writing or reading of data to / from a storage element included in the MLUT 30. Therefore, the MPLD 20 can operate as a main storage device or a cache memory.
  • FIG. 9B is a diagram illustrating an example of the MPLD memory operation.
  • the MPLD 20 uses any one of the memory operation address, MLUT address, write data WD, and read data RD indicated by the solid line in the memory operation, and the logical operation address LA indicated by the broken line and the logic operation Data LD is not used.
  • the memory operation address, the MLUT address, and the write data are output by, for example, an arithmetic processing device outside the MPLD 20, and the read data WD is output to the arithmetic processing device.
  • the MPLD 20 receives the memory operation address and the MLUT address as addresses for specifying the storage element, receives write data at the time of writing, and outputs read data LD at the time of reading.
  • the MLUT address is an address that specifies one MLUT included in the MPLD 20.
  • the MLUT address is output to the MPLD 20 via l signal lines.
  • l is the number of selected address signal lines that specify the MLUT.
  • the number of MLUTs of 2 to the power of 1 can be specified by l signal lines.
  • the MLUT decoder 12 receives the MLUT address via one signal line, decodes the MLUT address, and selects and specifies the MLUT 30 that is the target of the memory operation.
  • the memory operation address is decoded by an address decoder, which will be described later with reference to FIG. 11, via l signal lines, and a memory cell to be subjected to the memory operation is selected. *
  • the MPLD 20 receives, for example, the MLUT address, write data, and read data all via n signal lines.
  • n is the number of selected address signal lines for MLUT memory operation or logic operation, as will be described later with reference to FIG.
  • the MPLD 20 supplies the MLUT address, write data, and read data to each MLUT via n signal lines.
  • FIG. 9C is a diagram illustrating an example of the MPLD 20 logic operation.
  • the logic operation of the MPLD 20 uses a logic operation address and a logic operation data signal indicated by solid lines. *
  • the logic operation address is output from an external device and used as an input signal of a logic circuit configured by the truth table of the MLUT 30.
  • the logic operation data signal is an output signal of the logic circuit, and is output to the external device as an output signal of the logic circuit.
  • the MLUT arranged outside the MPLD 20 operates as an MLUT that receives an apparatus for external operation of the MPLD 20 and the logical operation address LA and outputs the logical operation data LD.
  • the MLUTs 30a and 30b illustrated in FIG. 9A receive the logic operation address LA from the outside of the semiconductor device 100, and output the logic operation data LD to the other MLUTs 30d around.
  • the MLUTs 30e and 30f shown in FIG. 9A receive the logical operation address LA from the other MLUTs 30c and 30d and output the logical operation data LD to the outside of the MPLD 20.
  • the address line of the logical operation address LA of the MLUT is connected to the data line of the logical operation data LD of the adjacent MLUT.
  • the MLUT 30c converts the logical operation data output from the MLUT 30a into the logical operation address.
  • the MLUT logical operation address or the logical operation data is different from the MLUT address to which each MLUT is uniquely connected, in that the MLUT logical operation address or logical operation data is obtained by input / output with the surrounding MLUT.
  • the logic realized by the logic operation of the MPLD 20 is realized by truth table data stored in the MLUT 30.
  • Some MLUTs 30 operate as logic elements as combinational circuits such as AND circuits and adders.
  • the other MLUTs operate as connection elements that connect the MLUTs 30 that realize the combinational circuit. Rewriting of truth table data for realizing the logic element and the connection element is performed by reconfiguration by the above-described memory operation. *
  • FIG. 10 is a diagram illustrating a first example of the MLUT.
  • the MLUT 30 shown in FIG. 10 includes an address switching circuit 10a, an address decoder 9, a storage element 40, and an output data switching circuit 10b.
  • the operation switching signal indicates a logical operation
  • the MLUT 30 illustrated in FIG. 10 operates to output logical operation data according to the logical operation address.
  • the operation switching signal indicates a memory operation
  • the MLUT 30 operates to accept write data or output read data according to a memory operation address.
  • the address switching circuit 10a includes n memory operation address signal lines to which a memory operation address is input, n logic operation address input signal lines to which a logic operation address signal is input, and an operation switching signal. Connect the input operation switching signal line.
  • the address switching circuit 10a operates so as to output either the memory operation address or the logic operation address to the n selected address signal lines based on the operation switching signal. As described above, the address switching circuit 10a selects the address signal line because the storage element 40 is a one-port type storage element that accepts either a read operation or a write operation. *
  • the address decoder 9 decodes the selected address signal received from the n address signal lines supplied from the address switching circuit 10a, and outputs a decode signal to 2 n word lines.
  • n ⁇ 2 n memory elements are arranged at a connection portion of 2 n word lines, n write data lines, and n output bit lines.
  • the output data switching circuit 10b When the output data switching circuit 10b receives signals from the n output bit lines, the output data switching circuit 10b outputs read data to the n read data signal lines in accordance with the input operation switching signal, or outputs the read data to the logic operation signal. Operates to output on a line.
  • FIG. 11 is a diagram illustrating an example of an MLUT that operates as a logical element.
  • the MLUT illustrated in FIG. 11 is a circuit similar to the MLUT illustrated in FIG. 10 or the semiconductor memory device illustrated in FIG. In FIG. 11, the description of the address switching circuit 10a and the output data switching circuit 10b is omitted to simplify the description.
  • the logic operation data lines D0 to D3 connect 24 memory elements 40 in series, respectively.
  • the address decoder 9 is configured to select four storage elements connected to any of the 24 word lines based on signals input to the logic operation address lines A0 to A3. These four storage elements are connected to logic operation data lines D0 to D3, respectively, and output data stored in the storage elements to logic operation data lines D0 to D3. For example, when an appropriate signal is input to the logic operation address lines A0 to A3, the four memory elements 40a, 40b, 40c, and 40d can be selected.
  • the storage element 40a is connected to the logic operation data line D0
  • the storage element 40b is connected to the logic operation data line D1
  • the storage element 40d is connected to the logic operation data line D2.
  • 40d is connected to the logic operation data line D3.
  • signals stored in the storage elements 40a to 40d are output to the logic operation data lines D0 to D3.
  • the MLUTs 30a and 30b receive the logical operation addresses from the logical operation address lines A0 to A3, and the values stored in the four storage elements 40 selected by the address decoder 9 based on the logical operation addresses are logically converted.
  • the data is output to the operation data lines D0 to D3 as logic operation data.
  • the logical operation address line A2 of the MLUT 30a is connected to the logical operation data line D0 of the adjacent MLUT 30b, and the MLUT 30a receives the logical operation data output from the MLUT 30b as the logical operation address.
  • the logical operation data line D2 of the MLUT 30a is connected to the logical operation address line A0 of the MLUT 30b, and the logical operation data output from the MLUT 30a is received as a logical operation address by the MLUT 30b.
  • the logic operation data line D2 of the MLUT 30a is one of 24 storage elements connected to the logic operation data line D2 based on signals input to the logic operation address lines A0 to A3 of the MLUT 30a. Is output to the logic operation address A0 of the MLUT 30b.
  • the logic operation data line D0 of the MLUT 30b is one of 24 storage elements connected to the logic operation data line D0 based on signals input to the logic operation address lines A0 to A3 of the MLUT 30b.
  • the signal stored in one is output to the logic operation address A2 of the MLUT 30a.
  • the MPLDs are connected by using a pair of address lines and data lines.
  • a pair of address lines and data lines used for MLUT connection such as the logic operation address line A2 and the logic operation data line D2 of the MLUT 30a, is referred to as an "AD pair". *
  • the AD pairs included in the MLUTs 30a and 30b are 4, but the number of AD pairs is not limited to 4 as will be described later. *
  • FIG. 12 is a diagram illustrating an example of an MLUT that operates as a logic circuit.
  • the logic operation address lines A 0 and A 1 are input to the 2-input NOR circuit 701
  • the logic operation address lines A 2 and A 3 are input to the 2-input NAND circuit 702.
  • the output of the 2-input NOR circuit and the output of the 2-input NAND circuit 702 are input to the 2-input NAND circuit 703, and a logic circuit is configured to output the output of the 2-input NAND circuit 703 to the logic operation data line D0. . *
  • FIG. 13 is a diagram showing a truth table of the logic circuit shown in FIG. Since the logic circuit of FIG. 12 has four inputs, all the inputs A0 to A3 are used as inputs. On the other hand, since there is only one output, only the output D0 is used as an output. “*” Is written in the columns of outputs D1 to D3 of the truth table. This indicates that any value of “0” or “1” may be used. However, when the truth table data is actually written into the MLUT for reconstruction, it is necessary to write either “0” or “1” in these fields. *
  • FIG. 14 is a diagram illustrating an example of an MLUT that operates as a connection element.
  • the MLUT as a connection element outputs a signal of the logic operation address line A0 to the logic operation data line D1, and outputs a signal of the logic operation address line A1 to the logic operation data line D2. It operates so as to output the signal of the operation address line A2 to the logic operation data line D3.
  • the MLUT as the connection element further operates to output the signal of the logic operation address line A3 to the logic operation data line D1.
  • FIG. 15 is a diagram showing a truth table of the connection elements shown in FIG.
  • the connection element shown in FIG. 14 has 4 inputs and 4 outputs. Therefore, all inputs A0-A3 and all outputs D0-D3 are used.
  • the MLUT outputs the signal of the input A0 to the output D1, outputs the signal of the input A1 to the output D2, outputs the signal of the input A2 to the output D3, and outputs the signal of the input A3. It operates as a connection element that outputs to the output D0. *
  • FIG. 16 is a diagram illustrating an example of a connection element realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3.
  • AD0 has a logic operation address line A0 and a logic operation data line D0.
  • AD1 has a logic operation address line A1 and a logic operation data line D1.
  • AD2 has a logic operation address line A2 and a logic operation data line D2.
  • AD3 has a logic operation address line A3 and a logic operation data line D3.
  • a one-dot chain line indicates a signal flow in which a signal input to the logic operation address line A0 of the AD pair 0 is output to the logic operation data line D1 of the AD pair 1.
  • a two-dot chain line indicates a signal flow in which a signal input to the logic operation address line A1 of the second AD pair 1 is output to the logic operation data line D2 of the AD pair 2.
  • a broken line indicates a flow of a signal that is input to the logic operation address line A2 of the AD pair 2 and output to the logic operation data line D3 of the AD pair 3.
  • a solid line indicates a flow of a signal that is input to the logical operation address line A3 of the AD pair 3 and is output to the logical operation data line D0 of the AD pair 0.
  • the MLUT 30 has four AD pairs, but the number of AD pairs is not particularly limited to four. *
  • FIG. 17 is a diagram illustrating an example in which one MLUT operates as a logic element and a connection element.
  • the logic operation address lines A0 and A1 are input to the 2-input NOR circuit 171
  • the output of the 2-input NOR circuit 171 and the logic operation address line A2 are input to the 2-input NAND circuit 172.
  • a logic circuit is configured to output the output of the 2-input NAND circuit 172 to the logic operation data line D0.
  • a connection element for outputting the signal of the logic operation address line A3 to the logic operation data line D2 is formed. *
  • FIG. 18 shows a truth table of the logic elements and connection elements shown in FIG.
  • the logic operation of FIG. 17 uses three inputs D0 to D3 and uses one output D0 as an output.
  • the connection element in FIG. 18 is a connection element that outputs the signal of the input A3 to the output D2. *
  • FIG. 19 is a diagram illustrating an example of logical operations and connection elements realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3.
  • AD0 has a logic operation address line A0 and a logic operation data line D0.
  • AD1 has a logic operation address line A1 and a logic operation data line D1.
  • AD2 has a logic operation address line A2 and a logic operation data line D2.
  • AD3 has a logic operation address line A3 and a logic operation data line D3.
  • the MLUT 30 realizes two operations, ie, a logic operation with three inputs and one output and a connection element with one input and one output, with one MLUT 30.
  • the logic operation uses the logic operation address line A0 of AD pair 0, the logic operation address line A1 of AD pair 1, and the logic operation address line A2 of AD pair 2 as inputs. Then, the address line of the logic operation data line D0 of AD pair 0 is used as an output. Further, the connection element outputs a signal input to the logic operation address line A3 of the AD pair 3 to the logic operation data line D2 of the AD pair 2 as indicated by a broken line.

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Abstract

[Problem] The purpose of the invention is to enable, in a semiconductor memory device, synchronous or asynchronous data readout to be performed for each piece of data. [Solution] Provided is a semiconductor memory device provided with: a plurality of memory cells each storing data; an address decoder which decodes address signals which specify the memory cells, and outputs a word line selection signal which is based on the decoded addresses and is used to select one of the word lines connected to a portion of the plurality of memory cells; a selection unit which holds selection data, and selects an external clock which is externally supplied, on the basis of the selection data; and a data read-out unit which reads out data from a portion of the plurality of memory cells selected on the basis of the work line selection signal, said data read-out unit performing read-out synchronously with the external clock when the external clock is selected, or asynchronously with the external clock when the external clock is not selected.

Description

半導体メモリ装置Semiconductor memory device
本発明は、半導体メモリ装置に関し、特に、メモリセル内部において、同期、非同期の切り替えが可能な半導体メモリ装置に関する。 The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of switching between synchronous and asynchronous in a memory cell.
半導体メモリにおいては、同期ＳＲＡＭ（Static Random Access Memory）と非同期ＳＲＡＭがあり、その使用状況により使い分けられている。同期ＳＲＡＭは、外部クロックに同期して利用されるので、クロック動作時のみ書き込み読み出しを行い、その他の状態ではワード線を非選択としメモリセルの状態を保護することができるので、信頼性が高い。　 In the semiconductor memory, there are a synchronous SRAM (Static Random Access Memory) and an asynchronous SRAM, which are properly used depending on the usage situation. Since the synchronous SRAM is used in synchronization with the external clock, writing and reading can be performed only during the clock operation, and in other states, the word line can be deselected and the memory cell state can be protected, thus providing high reliability. . *
それに対して非同期ＳＲＡＭはクロック制御の配慮が必要ないため、クロック信号に同期しないため、同期ＳＲＡＭと比して、クロックの共有等を考慮することなくアクセス可能なため、データアクセスが容易であり、制御装置や、計測システム等の機器の主記憶装置として利用されている。しかし、ワード線が常に外部からアクセス可能であるため、信頼性において、同期ＳＲＡＭに劣る。　 On the other hand, asynchronous SRAM does not require consideration of clock control, and is not synchronized with the clock signal. Therefore, compared with synchronous SRAM, it can be accessed without considering clock sharing and the like, and data access is easy. It is used as a main storage device for devices such as control devices and measurement systems. However, since the word line can always be accessed from the outside, the reliability is inferior to that of the synchronous SRAM. *
このように、同期ＳＲＡＭの信頼性と、非同期ＳＲＡＭのデータアクセス容易性という互いに異なる長所に応じて、それらの使用用途は異なる。　 As described above, their usages are different according to the different merits of the reliability of the synchronous SRAM and the data accessibility of the asynchronous SRAM. *
ＣＰＵ（Central Processing Unit）が、メモリに、アクセス要求を行ってから、データがＣＰＵに送られてくる、又は書き込みが完了する、までにはレイテンシと呼ばれる待ち時間が生じ、ＣＰＵの処理速度が下がる要因となる。一方、メモリへのアクセス要求は短期的には局所性が高く、連続した領域に順番に読み書きを行うことが多い。この特徴を利用して、複数のメモリバンクにまたがって連続したアドレスを交互に振っておき、あるデータにアクセスする遅延時間の最中に次のアドレスへアクセス要求を発行して時間を有効利用する技術が「メモリインターリーブ」と呼ばれている。ＣＰＵから並列にアクセス可能なメモリセルブロック（「メモリバンク」とも言われる）を増やせば、レイテンシを下げることができる。　 A waiting time called latency occurs between the time when a CPU (Central Processing Unit) makes an access request to the memory and when data is sent to the CPU or when writing is completed, and the processing speed of the CPU decreases. It becomes a factor. On the other hand, memory access requests have high locality in the short term, and reading and writing are often performed sequentially in consecutive areas. Using this feature, consecutive addresses are allocated alternately across multiple memory banks, and an access request is issued to the next address during the delay time for accessing certain data, thereby effectively using the time. The technology is called “memory interleaving”. By increasing the number of memory cell blocks (also referred to as “memory banks”) that can be accessed in parallel from the CPU, the latency can be lowered. *
下記に示す特許文献１では、各々がセルアレイブロックを構成する２つのメモリバンクを、同期ＳＲＡＭ又は非同期ＳＲＡＭとして動作可能なインターリーブ型メモリを開示されている。２つのメモリバンクには、アドレスの最小桁ビット（Ａ０）が、「ＥＶＥＮ」か「ＯＤＤ」によって、格納するデータを振り分けている。　 Patent Document 1 shown below discloses an interleave type memory that can operate two memory banks each constituting a cell array block as a synchronous SRAM or an asynchronous SRAM. In the two memory banks, data to be stored is distributed according to the least significant bit (A0) of the address according to “EVEN” or “ODD”. *
開示のインターリーブ型メモリは、外部アドレスによるアクセスを認識するためのＡＴＤ（address transition detection）回路の使用、及び、読出信号及び「同期」か「非同期」かを示すアドレスラッチイネーブル（ＡＬＥ）信号によって、ＣＰＵがメモリに要求したモードが、ランダムアクセスによる非同期モードのデータ読出しか、又は、バーストアクセスによる同期モードでのデータ読出しかを認識する。ＡＬＥ信号により同期モードを認識し、且つ、ＡＴＤ回路があるアドレスに対する外部からのバーストアクセスを検出すると、ＡＴＤ信号を生成する。ＡＴＤ信号と、バーストアクセス対象となるアドレスを用いて、内部アドレスカウンタが、シーケンシャルな内部アドレスをインクリメント動作により生成することで、同期モードのバーストアクセスに対するデータの読出しを可能にする。 The disclosed interleaved memory uses an ATD (address transition detection) circuit to recognize access by an external address, and a read signal and an address latch enable (ALE) signal indicating "synchronous" or "asynchronous" It recognizes whether the mode requested by the CPU to the memory is asynchronous mode data reading by random access or data reading in synchronous mode by burst access. When the synchronous mode is recognized by the ALE signal and burst access from the outside to a certain address is detected, the ATD signal is generated. The internal address counter uses the ATD signal and the address to be subjected to burst access to generate a sequential internal address by the increment operation, thereby enabling reading of data for the burst access in the synchronous mode.
特開２００１－２４３７７８号公報JP 2001-243778 A
上記したように、開示のインターリーブ型メモリは、メモリバンクを対象として同期モード、非同期モードの何れのデータ読出しを可能にするものであり、データ毎に同期又は非同期の割り当てをすることはできない。そのため、ある特定のデータだけを同期又は非同期で読み出すとき、メモリバンク全体を同期又は非同期にしなければならなかった。　 As described above, the disclosed interleaved memory enables data reading in either a synchronous mode or an asynchronous mode for a memory bank, and cannot perform synchronous or asynchronous allocation for each data. Therefore, when only certain data is read synchronously or asynchronously, the entire memory bank has to be synchronous or asynchronous. *
本発明の実施形態に係る半導体メモリは、同期又は非同期のデータ読出しを、データ毎に行うことを可能にすることを目的とする。 An object of the semiconductor memory according to the embodiment of the present invention is to enable synchronous or asynchronous data reading for each data.
上記課題を解決する形態は、下記の（１）～（９）に記載のようなものである。　（１）各々がデータを記憶する複数のメモリセルと、　前記メモリセルを特定するアドレス信号をデコードし、前記デコードされたアドレスに基づいた複数のメモリセルの一部に接続されるワード線の１つを選択するワード線選択信号を出力するアドレスデコーダと、　選択データを保持するとともに、前記選択データに基いて、外部から供給される外部クロックを選択する選択部と、　前記外部クロックが選択された場合、前記選択された外部クロックに同期して、又は、前記外部クロックが選択されなかった場合、前記外部クロックに同期せずに、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出すデータ読出部と、　を備えることを特徴とする半導体メモリ装置。　（２）アドレス信号の変化を検出するアドレス変化検出部と、　内部クロックを発生するクロック発生回路をさらに備え、　前記アドレスデコーダは、前記アドレス変化検出部がアドレスの変化を検出したとき、前記ワード線選択信号の出力を行い、　前記選択部は、前記選択データに基づいて、前記内部クロックを選択し、　前記データ読出部は、前記外部クロックが選択されなかった場合、前記内部クロックに同期して、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出す、（１）に記載の半導体メモリ装置。　（３）前記アドレスデコーダは、前記ワード線選択信号を出力するＸアドレスデコーダと、前記アドレス信号をデコードし、前記デコードされたアドレスに基づいて、前記データを読み出すビット線を選択するＹアドレスデコーダとを有する、（２）に記載の半導体メモリ装置。　（４）前記メモリセルアレイの一部のメモリセルには、前記選択データを保持し、　前記選択部は、前記メモリセルに保持される選択データに基づいて、外部から供給される外部クロックを選択する、（１）～（３）の何れか１項に記載の半導体メモリ装置。　（５）各々が複数のメモリセルアレイを有し、且つ、前記メモリセルアレイに真理値表データを書き込むと、論理要素又は接続要素として動作する複数の論理部を有する半導体装置であって、　前記論理部は、　各々がデータを記憶する複数のメモリセルと、　前記メモリセルを特定するアドレス信号をデコードし、前記デコードされたアドレスに基づいた複数のメモリセルの一部に接続されるワード線の１つを選択するワード線選択信号を出力するアドレスデコーダと、　選択データを保持するとともに、前記選択データに基いて、外部から供給される外部クロックを選択する選択部と、　前記外部クロックが選択された場合、前記選択された外部クロックに同期して、又は、前記外部クロックが選択されなかった場合、前記外部クロックに同期せずに、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出すデータ読出部と、を備えることを特徴とする半導体装置。　（６）アドレス信号の遷移を検出するアドレス変化検出部と、　内部クロックを発生するクロック発生回路をさらに備え、　前記アドレスデコーダは、前記アドレス変化検出部がアドレス変化を検出したとき、前記ワード線選択信号の出力を行い、　前記選択部は、前記選択データに基づいて、前記内部クロックを選択し、　前記データ読出部は、前記外部クロックが選択されなかった場合、前記内部クロックに同期して、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出す、（５）に記載の半導体装置。　（７）前記アドレスデコーダは、前記ワード線選択信号を出力するＸアドレスデコーダと、前記アドレス信号をデコードし、前記デコードされたアドレスに基づいて、前記データを読み出すビット線を選択するＹアドレスデコーダとを有する、（５）又は（６）に記載の半導体装置。　（８）前記メモリセルアレイの一部のメモリセルには、前記選択データを保持し、　前記選択部は、前記メモリセルに保持される選択データに基づいて、外部から供給される外部クロックを選択する、（５）～（７）の何れか１項に記載の半導体装置。　（９）前記選択データは、前記論理部が組み合わせ回路や配線ロジックとして動作する場合は内部クロックに同期化して、前記論理部が順序回路として動作する場合は外部クロックに同期化するように設定される（８）に記載の半導体装置。 Forms for solving the above problems are as described in the following (1) to (9). (1) A plurality of memory cells each storing data, and an address signal that identifies the memory cell, and 1 of word lines connected to a part of the plurality of memory cells based on the decoded address An address decoder that outputs a word line selection signal for selecting one, a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data, and the external clock is selected The plurality of memory cells selected based on the word line selection signal without being synchronized with the external clock in synchronization with the selected external clock or when the external clock is not selected. A semiconductor memory device comprising: a data reading unit that reads data from a part of the semiconductor memory device. (2) An address change detection unit that detects a change in an address signal and a clock generation circuit that generates an internal clock are further provided, and the address decoder detects the change in address when the address change detection unit detects an address change. The selection unit outputs a selection signal, the selection unit selects the internal clock based on the selection data, and the data reading unit synchronizes with the internal clock when the external clock is not selected, The semiconductor memory device according to (1), wherein data is read from a part of the plurality of memory cells selected based on the word line selection signal. (3) The address decoder includes: an X address decoder that outputs the word line selection signal; a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address; The semiconductor memory device according to (2), comprising: (4) The selection data is held in some memory cells of the memory cell array, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell. The semiconductor memory device according to any one of (1) to (3). (5) A semiconductor device having a plurality of memory cell arrays each having a plurality of logic units that operate as logic elements or connection elements when truth table data is written into the memory cell array. Is one of a plurality of memory cells each storing data, and one of word lines connected to a part of the plurality of memory cells based on the decoded address by decoding an address signal specifying the memory cell. An address decoder that outputs a word line selection signal for selecting a signal, a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data, and the external clock is selected The external clock is synchronized with the selected external clock or when the external clock is not selected. The semiconductor device characterized by without synchronization, and a data reading unit for reading the data for some of the plurality of memory cells selected on the basis of said word line selection signal. (6) An address change detection unit that detects a transition of an address signal and a clock generation circuit that generates an internal clock are further provided. The address decoder selects the word line when the address change detection unit detects an address change. The selection unit selects the internal clock based on the selection data, and the data reading unit synchronizes with the internal clock when the external clock is not selected. The semiconductor device according to (5), wherein data is read from a part of the plurality of memory cells selected based on a word line selection signal. (7) The address decoder includes: an X address decoder that outputs the word line selection signal; a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address; The semiconductor device according to (5) or (6). (8) The selection data is held in some memory cells of the memory cell array, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell. (5) The semiconductor device according to any one of (7) to (7). (9) The selection data is set to be synchronized with an internal clock when the logic unit operates as a combinational circuit or wiring logic, and is synchronized with an external clock when the logic unit operates as a sequential circuit. The semiconductor device according to (8).
本発明の実施形態に係る半導体メモリ装置は、同期又は非同期のデータ読出しを、データ毎に行うことができる。ＳＲＡＭ内の特定のデータのために、メモリセル全体を同期又は非同期にすることがないので、同期ＳＲＡＭの信頼性と、非同期ＳＲＡＭの高速性を同時に提供することができる。 The semiconductor memory device according to the embodiment of the present invention can perform synchronous or asynchronous data reading for each data. Since specific data in the SRAM does not make the entire memory cell synchronous or asynchronous, the reliability of the synchronous SRAM and the high speed of the asynchronous SRAM can be provided at the same time.
図１は、本実施形態に係る半導体メモリ装置の第１例を示す図である。FIG. 1 is a diagram illustrating a first example of a semiconductor memory device according to the present embodiment. 図２は、記憶素子の詳細例である。FIG. 2 is a detailed example of the memory element. 図３は、アドレスデコーダの詳細例である。FIG. 3 is a detailed example of the address decoder. 図４は、本実施形態に係る半導体メモリ装置の第２例を示す図である。FIG. 4 is a diagram illustrating a second example of the semiconductor memory device according to the present embodiment. 図５は、プリチャージ回路の詳細例を示す図である。FIG. 5 is a diagram illustrating a detailed example of the precharge circuit. 図６Ａは、ＡＴＤ回路の詳細例である。FIG. 6A is a detailed example of an ATD circuit. 図６Ｂは、ＡＴＤ回路を流れる信号のタイムチャートである。FIG. 6B is a time chart of signals flowing through the ATD circuit. 図７は、本実施形態に係る半導体メモリ装置の第３例を示す図である。FIG. 7 is a diagram illustrating a third example of the semiconductor memory device according to the present embodiment. は、半導体メモリ装置をＭＬＵＴとして用いたＭＰＬＤの一例を示す図である。These are figures which show an example of MPLD which used the semiconductor memory device as MLUT. 図９Ａは、ＭＰＬＤの一例を示す図である。FIG. 9A is a diagram illustrating an example of an MPLD. 図９Ｂは、ＭＰＬＤのメモリ動作の一例を示す図である。FIG. 9B is a diagram illustrating an example of an MPLD memory operation. 図９Ｃは、ＭＬＵＴの論理動作の一例を示す図である。FIG. 9C is a diagram illustrating an example of the logical operation of the MLUT. 図１０は、ＭＬＵＴの一例を示す図である。FIG. 10 is a diagram illustrating an example of an MLUT. 図１１は、論理要素として動作するＭＬＵＴの一例を示す図である。FIG. 11 is a diagram illustrating an example of an MLUT that operates as a logical element. 図１２は、論理回路として動作するＭＬＵＴの一例を示す図である。FIG. 12 is a diagram illustrating an example of an MLUT that operates as a logic circuit. 図１３は、図１２に示す論理回路の真理値表を示す図である。FIG. 13 is a diagram showing a truth table of the logic circuit shown in FIG. 図１４は、接続要素として動作するＭＬＵＴの一例を示す図である。FIG. 14 is a diagram illustrating an example of an MLUT that operates as a connection element. 図１５は、図１４に示す接続要素の真理値表を示す図である。FIG. 15 is a diagram showing a truth table of the connection elements shown in FIG. 図１６は、４つのＡＤ対を有するＭＬＵＴによって実現される接続要素の一例を示す図である。FIG. 16 is a diagram illustrating an example of a connection element realized by an MLUT having four AD pairs. 図１７は、１つのＭＬＵＴが、論理要素及び接続要素として動作する一例を示す図である。FIG. 17 is a diagram illustrating an example in which one MLUT operates as a logical element and a connection element. 図１８に、図１７に示す論理要素及び接続要素の真理値表を示す。FIG. 18 shows a truth table of the logic elements and connection elements shown in FIG. 図１９に、ＡＤ対を有するＭＬＵＴによって実現される論理動作及び接続要素の一例を示す図である。FIG. 19 is a diagram illustrating an example of logical operations and connection elements realized by an MLUT having an AD pair.
以下、図面を参照して、〔１〕半導体メモリ装置、〔２〕ＭＰＬＤ、〔３〕半導体メモリ装置を用いたＭＰＬＤ、〔４〕ＭＰＬＤの詳細、〔５〕ＭＬＵＴの詳細について順に説明する。　 Hereinafter, [1] semiconductor memory device, [2] MPLD, [3] MPLD using the semiconductor memory device, [4] details of MPLD, and [5] details of MLUT will be described in order. *
〔１〕半導体メモリ装置　図１は、半導体メモリ装置の第１例を示す図である。図１に示される半導体メモリ装置１００は、各々がデータを記憶するメモリセルからなるメモリセルアレイ１１０と、アドレスデコーダ１２０と、外部から供給される外部クロックを選択する選択部１３０と、外部クロックの選択の有無に応じて、メモリセルアレイ１１０へのデータ読出し又はデータ書き込みを行うデータ入出力部１４０を有する。　 [1] Semiconductor Memory Device FIG. 1 is a diagram illustrating a first example of a semiconductor memory device. A semiconductor memory device 100 shown in FIG. 1 includes a memory cell array 110 including memory cells each storing data, an address decoder 120, a selection unit 130 for selecting an external clock supplied from the outside, and selection of an external clock. The data input / output unit 140 is configured to read data from or write data to the memory cell array 110 in accordance with the presence or absence of data. *
メモリセルアレイは、ｍ×２ｍ個の記憶素子を有し、ｍ×２ｎ個の記憶素子は、２のｎ乗本のワード線と、ｍ本のビット線の接続部分に配置される。図２は、記憶素子の詳細例である。図２に示される記憶素子４０では、ｐＭＯＳトランジスタ１６１、１６２、及び、ｎＭＯＳトランジスタ１６３、１６４、１６５、１６６を備える。ｐＭＯＳトランジスタ１６１のソースと、ｐＭＯＳトランジスタ１６２のソースとは、ＶＤＤ（電源電圧端）に接続する。ｎＭＯＳトランジスタ１６３のドレーンと、ｎＭＯＳトランジスタ１６４のドレーンは、ＶＳＳ（接地電圧端）に接続される。　 The memory cell array has m × 2 m memory elements, and the m × 2 n memory elements are arranged at a connection portion between 2 n word lines and m bit lines. FIG. 2 is a detailed example of the memory element. The storage element 40 shown in FIG. 2 includes pMOS transistors 161 and 162 and nMOS transistors 163, 164, 165, and 166. The source of the pMOS transistor 161 and the source of the pMOS transistor 162 are connected to VDD (power supply voltage terminal). The drain of the nMOS transistor 163 and the drain of the nMOS transistor 164 are connected to VSS (ground voltage terminal).
　ｎＭＯＳトランジスタ１６５のドレーンは、ビット線ｂに接続される。ｎＭＯＳトランジスタ１６５のゲートは、ワード線ＷＬに接続される。ｎＭＯＳトランジスタ１６６のドレーンは、ビット線/ｂに接続される。ｎＭＯＳトランジスタ１６６のゲートは、ワード線ＷＬに接続される。　 The drain of the nMOS transistor 165 is connected to the bit line b. The gate of the nMOS transistor 165 is connected to the word line WL. The drain of the nMOS transistor 166 is connected to the bit line / b. The gate of the nMOS transistor 166 is connected to the word line WL. *
上記構成により、書き込み動作では、記憶素子４０は、ワード線ＷＬの信号レベル「Ｈ（Ｈｉｇｈ）」により、ビット線ｂ及びビット線/ｂから伝えられた信号レベルを、ｐＭＯＳトランジスタ１６１、１６２、ｎＭＯＳトランジスタ１６３、１６４に保持する。読み出し動作では、記憶素子４０は、ワード線ＷＬの信号レベル「Ｈ」により、ｐＭＯＳトランジスタ１６１、１６２、ｎＭＯＳトランジスタ１６３、１６４に保持された信号レベルを、ビット線ｂ、及び、ビット線/ｂに伝える。　 With the above configuration, in the write operation, the storage element 40 changes the signal level transmitted from the bit line b and the bit line / b according to the signal level “H (High)” of the word line WL to the pMOS transistors 161 and 162 and the nMOS. This is held in the transistors 163 and 164. In the read operation, the memory element 40 causes the signal levels held in the pMOS transistors 161 and 162 and the nMOS transistors 163 and 164 to be applied to the bit line b and the bit line / b according to the signal level “H” of the word line WL. Tell. *
図３は、アドレスデコーダの詳細例を示す図である。図３に示されるアドレスデコーダ１２０は、インバータ回路１２０－１、ＡＮＤ回路１２０－２、及びＡＮＤ回路１２０－３を有する。インバータ回路１２０－１は、ｎ本のアドレス信号線毎に、ｎ個ある。ＡＮＤ回路１２０－２、１２０－３は、それぞれ２のｎ乗個ある。　 FIG. 3 is a diagram showing a detailed example of the address decoder. The address decoder 120 shown in FIG. 3 includes an inverter circuit 120-1, an AND circuit 120-2, and an AND circuit 120-3. There are n inverter circuits 120-1 for every n address signal lines. There are 2 n AND circuits 120-2 and 120-3, respectively. *
インバータ回路１２０－１は、ｎ本のアドレス信号線から受け取ったアドレス信号の論理を反転し、反転したアドレス信号を、ＡＮＤ回路１２０－２に出力する。ＡＮＤ回路１２０－２は、アドレス信号、及び、反転アドレス信号を入力信号として受け取り、全ての入力値の信号レベルが「Ｈ」のとき、論理積演算により、信号レベル「Ｈ」の出力を第２ＡＮＤ回路に出力する。ＡＮＤ回路１２０－３は、ＡＮＤ回路１２０－２の出力と、内部クロック（後述）を入力信号として受け取り、全ての入力値の信号レベルが「Ｈ」のとき、論理積演算により、信号レベル「Ｈ」の出力を出力する。　 The inverter circuit 120-1 inverts the logic of the address signal received from the n address signal lines and outputs the inverted address signal to the AND circuit 120-2. The AND circuit 120-2 receives the address signal and the inverted address signal as input signals. When the signal levels of all input values are “H”, the AND circuit 120-2 outputs the signal level “H” to the second AND by the AND operation. Output to the circuit. The AND circuit 120-3 receives the output of the AND circuit 120-2 and an internal clock (described later) as input signals. When the signal levels of all the input values are “H”, the signal level “H” is obtained by a logical product operation. Is output. *
ワード線選択信号は、信号レベルが「Ｈ」であり、ワード線非選択信号は、信号レベル「Ｌ（Ｌｏｗ）」である。このようにして、アドレスデコーダ１２０は、２のｎ乗本のワード線のうち１つのワード線に、信号レベル「Ｈ」のワード線選択信号を出力するように構成される。　 The word line selection signal has a signal level “H”, and the word line non-selection signal has a signal level “L (Low)”. In this manner, the address decoder 120 is configured to output a word line selection signal having a signal level “H” to one word line out of 2 n word lines. *
なお、図３の例では、内部クロックを用いる例を示したが、内部クロックに同期しないデコーダであってもよい。その場合、ＡＮＤ回路１２０－３は不要となり、ＡＮＤ回路１２０－２の出力が、メモリセルのワード線と接続する。　 In the example of FIG. 3, an example using the internal clock is shown, but a decoder that is not synchronized with the internal clock may be used. In that case, the AND circuit 120-3 becomes unnecessary, and the output of the AND circuit 120-2 is connected to the word line of the memory cell. *
図１を参照すると、アドレスデコーダ１２０は、ｎ本のアドレス信号線から受け取ったアドレス信号をデコードし、２のｎ乗本のワード線ＷＬにデコード信号であるワード線選択信号を出力する。　 Referring to FIG. 1, the address decoder 120 decodes an address signal received from n address signal lines, and outputs a word line selection signal as a decode signal to 2 n word lines WL. *
選択部１３０は、外部から供給される選択データに基いて、外部から供給される外部クロックを、データ入出力部１４０に伝える選択回路である。選択部１３０は、データ出力線毎に個々に設けられる複数の選択回路であり、選択回路は、それぞれ外部から供給される選択データを保持する。選択データは、メモリセルアレイ１１０から供給されてもよい。その場合、各選択回路は、メモリセルアレイ１１０内の特定のメモリセル（選択データ用メモリセル）に各々接続しており、選択データ用メモリセルの信号レベル「Ｈ」の場合、選択データの信号レベルも「Ｈ」になり、選択データ用メモリセルの信号レベル「Ｌ」の場合、選択データの信号レベルも「Ｌ」になる。選択回路は、選択データの信号レベル「Ｌ」の場合、外部クロックをデータ入出力部１４０に伝え、その選択回路に対応する読出データＱは、外部クロックに同期して、読み出される。選択回路は、選択データの信号レベル「Ｈ」の場合、外部クロックをデータ入出力部１４０に伝えず、その選択回路に対応する読出データＱは外部クロックに非同期で、読み出される。　 The selection unit 130 is a selection circuit that transmits an external clock supplied from the outside to the data input / output unit 140 based on selection data supplied from the outside. The selection unit 130 is a plurality of selection circuits provided individually for each data output line, and each selection circuit holds selection data supplied from the outside. The selection data may be supplied from the memory cell array 110. In this case, each selection circuit is connected to a specific memory cell (selection data memory cell) in the memory cell array 110. When the signal level of the selection data memory cell is “H”, the signal level of the selection data When the signal level of the memory cell for selected data is “L”, the signal level of the selected data is also “L”. When the signal level of the selection data is “L”, the selection circuit transmits the external clock to the data input / output unit 140, and the read data Q corresponding to the selection circuit is read in synchronization with the external clock. When the signal level of the selection data is “H”, the selection circuit does not transmit the external clock to the data input / output unit 140, and the read data Q corresponding to the selection circuit is read asynchronously with the external clock. *
データ入出力部１４０は、外部からライトイネーブル（ＷＥ）のエッジタイミング及び書込データを受け取ると、ｍ本のビット線ｂ、/ｂにその書込データの信号レベルを伝えて、メモリセルに書込データを書き込む。また、データ入出力部１４０は、ｍ本のビット線ｂ、/ｂの信号レベルを外部に出力することで、読出データを出力する。　 When the data input / output unit 140 receives the write enable (WE) edge timing and the write data from the outside, the data input / output unit 140 transmits the signal level of the write data to the m bit lines b and / b, and writes it to the memory cell. Write data. The data input / output unit 140 outputs read data by outputting the signal levels of the m bit lines b and / b to the outside. *
以上のように、半導体メモリ装置１００は、データ読出しを、データ毎に同期又は非同期で行うことができる。ＳＲＡＭ内の特定のデータのために、メモリセル全体を同期又は非同期にすることがないので、同期ＳＲＡＭの信頼性と、非同期ＳＲＡＭのアクセス容易性を同時に提供することができる。　 As described above, the semiconductor memory device 100 can perform data reading synchronously or asynchronously for each data. Since specific data in the SRAM does not make the entire memory cell synchronous or asynchronous, the reliability of the synchronous SRAM and the accessibility of the asynchronous SRAM can be provided at the same time. *
図４は、半導体メモリ装置の第２例を示す図である。図３に示す半導体メモリ装置１００Ａは、メモリセルアレイ１１０、アドレスデコーダ１２０Ａ、１２０Ｂ、選択部１３０Ａ、ビットラインプリチャージ回路１３５、データ入出力部１４０Ａを備える。　 FIG. 4 is a diagram illustrating a second example of the semiconductor memory device. A semiconductor memory device 100A shown in FIG. 3 includes a memory cell array 110, address decoders 120A and 120B, a selection unit 130A, a bit line precharge circuit 135, and a data input / output unit 140A. *
図４に示す例では、メモリセルアレイ１１０において、Ｘ列が、２の５乗本のワード線と、Ｙ列が、読出し用と、書込み用にそれぞれ用意される２の２乗×７本と１本のビット線が縦横に格子状に形成され、メモリセルは、ワード線とビット線の交差点に配置されている。よって、２の７乗×（７個＋１個）のメモリセルを有し、そのうち７個のメモリセルは、上記した選択データ用メモリセルである。　 In the example shown in FIG. 4, in the memory cell array 110, the X column has 2 5 word lines, and the Y column has 2 squares × 7 and 1 prepared for reading and writing, respectively. The bit lines are formed in a grid pattern vertically and horizontally, and the memory cells are arranged at the intersections of the word lines and the bit lines. Therefore, it has 2 7 × 7 (7 + 1) memory cells, of which 7 memory cells are the memory cells for selection data described above. *
図１で説明したアドレスデコーダ１２０は、図４では、Ｘ列用のＸアドレスデコーダ１２０Ａ及びＹ列用のＹアドレスデコーダ１２０Ｂからなり、Ｘアドレスデコーダ１２０Ａ及びＹアドレスデコーダ１２０Ｂは、アドレス信号線Ａ０～Ａ４、及び、アドレス信号線Ａ５～Ａ６にそれぞれ接続する。アドレス信号線の数が増える場合、図４に示すように、Ｘ列と、Ｙ列のデコーダに分けることで、メモリセル形状をＸ軸方向に伸ばすことができる。　 The address decoder 120 described in FIG. 1 includes an X address decoder 120A for the X column and a Y address decoder 120B for the Y column in FIG. 4, and the X address decoder 120A and the Y address decoder 120B include the address signal lines A0 to A0. A4 and address signal lines A5 to A6 are respectively connected. When the number of address signal lines increases, the memory cell shape can be extended in the X-axis direction by dividing into X-column and Y-column decoders as shown in FIG. *
選択データ用メモリセルは、選択データを保持し、選択データの信号を、Ｓ０，Ｓ１、・・・、Ｓ６として選択回路の制御信号とする。　 The memory cell for selection data holds selection data, and signals of the selection data are set as control signals for the selection circuit as S0, S1,..., S6. *
Ｘアドレスデコーダ１２０Ａは、アドレス変化検出部としてのＡＴＤ回路(Address Transition Detect)１２１を備える。ＡＴＤ回路は、アドレス入力端子に設けられ、アドレス入力端子に印加されるアドレス入力信号の変化を検知して、変化したアドレス信号を出力する回路である。ＡＴＤ回路の詳細例は、図５及び図６を用いて後述する。　 The X address decoder 120A includes an ATD circuit (Address Transition Detect) 121 as an address change detection unit. The ATD circuit is a circuit that is provided at an address input terminal, detects a change in an address input signal applied to the address input terminal, and outputs the changed address signal. A detailed example of the ATD circuit will be described later with reference to FIGS. *
ＡＴＤ回路はアドレス信号の変化を検出したときだけ、変化したアドレス信号を、Ｘアドレスデコーダ１２０Ａに出力するので、Ｘアドレスデコーダ１２０Ａは、アドレス信号が変化したときだけワード線選択信号を出力し、アドレス信号が変化しないときはワード線選択信号を出力しない。このようにすることで、アドレス変化がない時は、ワード線選択信号が出力されないので、外乱ノイズによる書き込み誤動作を防止することができる。また、Ｘアドレスデコーダ１２０Ａは、図１に示すアドレスデコーダ１２０より、ワード線を活性化するアドレス線の数を減らすので、アドレスの変化が生じた場合にメモリセルへのワード線を介したノイズ混入の可能性を減らすことができる。　 Since the ATD circuit outputs the changed address signal to the X address decoder 120A only when it detects a change in the address signal, the X address decoder 120A outputs a word line selection signal only when the address signal changes, When the signal does not change, the word line selection signal is not output. In this way, when there is no address change, the word line selection signal is not output, so that a write malfunction due to disturbance noise can be prevented. Further, the X address decoder 120A reduces the number of address lines for activating word lines as compared with the address decoder 120 shown in FIG. 1, so that when an address change occurs, noise is mixed into the memory cell via the word line. Can reduce the possibility of *
さらに、Ｘアドレスデコーダ１２０Ａは、内部クロックを発生させるためのクロック発生回路１２２を有する。後述されるように、内部クロックは、データ入出力部１４０のフリップフロップ及びＡＴＤ回路１２１の同期信号にも利用される。アドレスデコーダにおいてこの内部クロックに同期して、ワード線選択信号の出力バラツキを抑制することもできる。一方、内部クロック周期を、外部クロック周期より短くすることで、非同期ＳＲＡＭの高速性も両立させることができる。　 Furthermore, the X address decoder 120A has a clock generation circuit 122 for generating an internal clock. As will be described later, the internal clock is also used as a flip-flop of the data input / output unit 140 and a synchronization signal of the ATD circuit 121. In the address decoder, the output variation of the word line selection signal can be suppressed in synchronization with the internal clock. On the other hand, by making the internal clock cycle shorter than the external clock cycle, the high speed of the asynchronous SRAM can be achieved. *
内部クロックは、外部クロックと異なる周期としてもよく、非同期ＳＲＡＭとして外部クロックに同期せずに、アクセス可能という非同期ＳＲＡＭの高速性を得るために、内部クロックは、外部クロックより短周期であることが好ましい。　 The internal clock may have a different period from that of the external clock, and the internal clock may have a shorter period than the external clock in order to obtain the high speed of the asynchronous SRAM that can be accessed without being synchronized with the external clock as an asynchronous SRAM. preferable. *
なお、上記説明では、Ｘアドレスデコーダ１２０Ａ内にＡＴＤ回路１２１及びクロック発生回路１２２を設ける例を説明したが、ＡＴＤ回路１２１及びクロック発生回路１２２は、Ｘアドレスデコーダ１２０Ａと別個に設けてもよい。ただし、ＡＴＤ回路１２１は、アドレスの変遷を検出するために、Ｘアドレスデコーダ１２０Ａの上段に設ける必要がある。　 In the above description, the example in which the ATD circuit 121 and the clock generation circuit 122 are provided in the X address decoder 120A has been described. However, the ATD circuit 121 and the clock generation circuit 122 may be provided separately from the X address decoder 120A. However, the ATD circuit 121 needs to be provided in the upper stage of the X address decoder 120A in order to detect address transition. *
Ｙアドレスデコーダ１２０Ｂは、複数の選択回路であり、各々は７本のデータ線毎に複数個設けられてもよい。その場合、各々の選択回路は、４つのビット対から、アドレス信号Ａ５、Ａ６に従って、１つのビット対ｂ、／ｂを、出力用又は入力用データ線として選択する。　 The Y address decoder 120B is a plurality of selection circuits, each of which may be provided for every seven data lines. In that case, each selection circuit selects one bit pair b, / b as an output or input data line from the four bit pairs according to the address signals A5, A6. *
ビットラインプリチャージ回路１３５は、ビット線ｂ及びビット線／ｂを共に「１」にプリチャージする。　 The bit line precharge circuit 135 precharges both the bit line b and the bit line / b to “1”. *
図５は、１ビット線対のためのビットラインプリチャージ回路の詳細例を示す。１ビット線対のためのビットラインプリチャージ回路１３５ａは、２つのＰＭＯＳを有し、ビットラインプリチャージ回路１３５ａの入力は、ビット線ｂ及びビット線／ｂを介して、メモリセルと接続する。そして、ビットラインプリチャージ回路１３５ａの出力は、ビット線ｂ及びビット線／ｂを介してＹアドレスデコーダと接続する。また、ビットラインプリチャージ回路１３５ａは、内部クロックに従ってビット線対ｂ、／ｂの信号レベルを「Ｈ」にプリチャージする。このような、１ビット線対のためのビットラインプリチャージ回路１３５ａが、メモリセルアレイ１１０の各ビット線対ｂ、／ｂ毎に設けられる。　 FIG. 5 shows a detailed example of a bit line precharge circuit for one bit line pair. The bit line precharge circuit 135a for one bit line pair has two PMOSs, and the input of the bit line precharge circuit 135a is connected to the memory cell via the bit line b and the bit line / b. The output of the bit line precharge circuit 135a is connected to the Y address decoder via the bit line b and the bit line / b. The bit line precharge circuit 135a precharges the signal level of the bit line pair b, / b to “H” according to the internal clock. Such a bit line precharge circuit 135 a for one bit line pair is provided for each bit line pair b, / b of the memory cell array 110. *
クロックが入り、信号レベルが「Ｈ」になると、ＰＭＯＳがオフになるので、ＶＤＤとの接続も切れて、ビット線はメモリセルの情報でレベルを出力する。クロックの信号レベルが「Ｌ」になるとＰＭＯＳがオンになり、ビット線はＶＤＤの電位に引き上げられる。このように、クロックが入るときだけ、ビット線がメモリセルと接続することで、メモリセルへの外乱ノイズによる書き込み誤動作を防ぐ。　 When the clock is input and the signal level becomes “H”, the PMOS is turned off, so that the connection with VDD is cut off, and the bit line outputs the level based on the information of the memory cell. When the signal level of the clock becomes “L”, the PMOS is turned on and the bit line is pulled up to the potential of VDD. In this manner, the bit line is connected to the memory cell only when the clock is input, thereby preventing a write malfunction due to disturbance noise to the memory cell. *
再び、図４に戻ると、選択部１３０Ａは、図１に示した選択部１３０と同様に、データ出力線毎に個々に設けられる複数の選択回路であり、選択回路は、それぞれ選択データを保持する。選択部１３０Ａは、選択回路が選択データの信号レベル「Ｈ」の場合、外部クロックをデータ入出力部１４０に伝えず、内部クロックをデータ入出力部１４０に伝える点において、選択部１３０と異なる。メモリセルアレイ１１０には、１ビットラインを追加してＤ７とする。Ｄ７の１番地のメモリセルの内部信号をＳ０、２番地のメモリセルの内部信号をＳ１として、７番地のメモリセルの内部信号Ｓ７までの信号を、出力ラッチのクロックの内部クロック及び外部クロックの選択信号とする。　 Referring back to FIG. 4, the selection unit 130A is a plurality of selection circuits provided for each data output line, like the selection unit 130 shown in FIG. 1, and each of the selection circuits holds selection data. To do. The selection unit 130A differs from the selection unit 130 in that when the selection circuit has a signal level “H” of the selection data, the external clock is not transmitted to the data input / output unit 140 but the internal clock is transmitted to the data input / output unit 140. One bit line is added to the memory cell array 110 as D7. The internal signal of the memory cell at address D7 is S0, the internal signal of the memory cell at address 2 is S1, and the signals up to the internal signal S7 of the memory cell at address 7 are the internal and external clocks of the output latch clock. Select signal. *
１ビット内に、選択データを保持できるので、メモリセルアレイ１１０の小型化できる。また、新たに選択データ格納用のメモリセルを設けることなく、既存のメモリセルを選択データを格納するために使用してもよい。　 Since selection data can be held in one bit, the memory cell array 110 can be downsized. Further, an existing memory cell may be used for storing selection data without newly providing a memory cell for storing selection data. *
なお、外部から、選択データにデータを直接書き込むためには、外部データを受けるためのレジスタが必要になる。さらに、外部は、レジスタ用の書き込み制御が要求される。選択データをメモリセルに書き込みようにすれば、新たな書き込み制御を要することなく、外部から選択回路を制御可能になる。　 In order to directly write data to the selected data from the outside, a register for receiving external data is required. Further, externally, write control for registers is required. If the selection data is written in the memory cell, the selection circuit can be controlled from the outside without requiring new writing control. *
外部クロックは一定の周期で入ってくるので、アドレスが変わっても出力は変わらないが、非同期はアドレスが変われば内部クロックに従って動作する。このように、内部クロックが外部クロックよりも短周期であれば、より高い即時性でデータアクセスが可能になる。したがって、非同期ＳＲＡＭと同様に、外部クロックと同期させないときの高速性が要求される場合は、内部クロックは、外部クロックより短周期にする必要がある。　 Since the external clock comes in at a fixed period, the output does not change even if the address changes, but asynchronous operation operates according to the internal clock if the address changes. In this way, if the internal clock has a shorter period than the external clock, data access is possible with higher immediacy. Therefore, as in the case of asynchronous SRAM, when high speed is required when not synchronizing with an external clock, the internal clock needs to have a shorter cycle than the external clock. *
データ入出力部１４０は、出力データ線毎に設けられる複数のフリップフロップ（Ｆ／Ｆ）を有し（図３に示す例では、Ｄ型フリップフロップ）、C(CLOCK)端子の立ち上がりエッジでD入力の値がQ出力として保持される。つまり、クロック時のみ出力変化をさせて、それ以外は情報を保持する。このことにより、ビット線を「Ｈ」状態にでき、デバイ
スの低電圧化におけるマージン確保を図ることができる。　 The data input / output unit 140 has a plurality of flip-flops (F / F) provided for each output data line (D-type flip-flop in the example shown in FIG. 3), and D at the rising edge of the C (CLOCK) terminal. The input value is held as the Q output. That is, the output is changed only at the clock, and the information is held otherwise. As a result, the bit line can be set to the “H” state, and a margin can be ensured when the device voltage is lowered.
上記の例では、ワード線が３２本であり、信号レベルの劣化が少ないので、センスアンプは、示していないが、アドレス、及びメモリセルの増加により、ワード線が増える場合は、ビットラインプリチャージ回路１３５と、Ｙアドレスデコーダ１２０Ｂの間に、センスアンプやライトアンプを設けてもよい。　 In the above example, since there are 32 word lines and the signal level is less deteriorated, the sense amplifier is not shown. However, when the number of word lines increases due to an increase in addresses and memory cells, the bit line precharge is performed. A sense amplifier or a write amplifier may be provided between the circuit 135 and the Y address decoder 120B. *
また、図２に示したメモリセルは、シングルポートのものであるが、読出し及び書込みを同時に行う高速型のメモリセルを使用する場合は、ダブルポートのメモリセルであってもよい。　 The memory cell shown in FIG. 2 is a single-port memory cell, but may be a double-port memory cell when a high-speed memory cell that performs reading and writing simultaneously is used. *
以上説明したように、半導体メモリ装置１００Ａは、アドレス変化がない時は、ワード線選択信号が出力されないので、外乱ノイズによる書き込み誤動作を防止することができるとともに、データ線毎に外部クロック及び内部クロックの切り替えを行うことができる。　 As described above, since the semiconductor memory device 100A does not output a word line selection signal when there is no address change, it can prevent a write malfunction due to disturbance noise, and can provide an external clock and an internal clock for each data line. Can be switched. *
図６Ａは、ＡＴＤ回路の一例を示す図である。図６Ａに示すＡＴＤ回路１２１は、１２１－１に示されるように、フリップフロップ（Ｆ／Ｆ）、遅延回路（ＤＣ）、論理積演算を行うＡＮＤ回路、排他的論理和演算を行うＸＯＲ回路、論理和演算を行うＯＲ回路、トランスミッションゲート（ＴＧ）から構成される。ＡＮＤ回路、ＸＯＲ回路及びＯＲ回路は、ＭＩＬ記号で示される。　 FIG. 6A is a diagram illustrating an example of an ATD circuit. The ATD circuit 121 shown in FIG. 6A includes, as indicated by 121-1, a flip-flop (F / F), a delay circuit (DC), an AND circuit that performs a logical product operation, an XOR circuit that performs an exclusive logical sum operation, An OR circuit that performs a logical sum operation and a transmission gate (TG) are included. The AND circuit, XOR circuit, and OR circuit are indicated by MIL symbols. *
ＸＯＲ回路の入力は、アドレス信号と、そのアドレス信号を遅延させた信号であるので、遅延させている間に、アドレス信号に変化があれば、アドレス信号の変化を検出し、信号レベル「Ｈ」を出力する。このように、ＡＴＤ回路１２１は、ＸＯＲ回路と遅延回路の組み合わせでアドレス変化を検出する。　 Since the input of the XOR circuit is an address signal and a signal obtained by delaying the address signal, if there is a change in the address signal during the delay, the change in the address signal is detected and the signal level “H” is detected. Is output. Thus, the ATD circuit 121 detects an address change by a combination of the XOR circuit and the delay circuit. *
図６Ｂは、図６Ａに示すＡＴＤ回路のタイムチャートを示す。図６Ａ及び図６ＢのＡｉは、外部からのアドレス信号入力に相当し、ａｉは図３に示すインバータ回路１２０－１の上段から分岐する信号入力に相当し、オーバーライン付きａｉは、図３に示すインバータ回路１２０－１の出力信号、φ１は、ＴＧからフリップフロップのクロックに入力する帰還信号、φ２は、ＡＮＤ回路に入力する帰還信号である。　 FIG. 6B shows a time chart of the ATD circuit shown in FIG. 6A. 6A and 6B corresponds to an address signal input from the outside, ai corresponds to a signal input branched from the upper stage of the inverter circuit 120-1 shown in FIG. 3, and ai with an overline is shown in FIG. An output signal of the inverter circuit 120-1 shown, φ1 is a feedback signal input from the TG to the flip-flop clock, and φ2 is a feedback signal input to the AND circuit. *
フリップフロップは、内部クロックに同期したφ１をクロックとして受け取り、クロックのエッジの立ち上がりで、アドレス信号を保持する。　 The flip-flop receives φ1 synchronized with the internal clock as a clock and holds the address signal at the rising edge of the clock. *
ＸＯＲ回路は、前サイクルのアドレスと現在サイクルのアドレスが相違する場合、信号レベル「Ｈ」の信号を出力し、その信号が、φ２として、ＴＧから出力される。φ２をクロックとして受け取るフリップフロップは、φ１のサイクルで保持していたアドレスを出力する。ＡＮＤ回路は、φ２のサイクルでフリップフロップから出力されたφ１サイクルのアドレスの信号レベルと、φ２の信号レベルが同じである場合、φ１サイクルのアドレスを、アドレスａｉとして出力する。このように、ＡＴＤ回路は、アドレス変化を検出したときだけ、変化したアドレス信号をアドレスデコーダに出力する。　 When the address of the previous cycle is different from the address of the current cycle, the XOR circuit outputs a signal level “H”, and the signal is output from the TG as φ2. The flip-flop that receives φ2 as a clock outputs the address held in the cycle φ1. The AND circuit outputs the address of φ1 cycle as the address ai when the signal level of the address of φ1 cycle output from the flip-flop in the cycle of φ2 is the same as the signal level of φ2. In this way, the ATD circuit outputs the changed address signal to the address decoder only when detecting an address change. *
図７は、半導体メモリ装置の第３例を示す図である。図７に示す半導体メモリ１００Ｂは、ＡＴＤ回路１２１Ａが、全アドレス信号の変化を検出する点において異なるが、その他の構成において、図３に示す半導体メモリ１００Ａと同じである。図７に示すように、ＡＴＤ回路１２１Ａは、全アドレス信号の変化を検出し、Ａ０～Ａ４の信号変化を検出すると、メモリセルアレイ１１０のワード線選択信号を出力し、Ａ５、Ａ６の信号変化を検出すると、Ｙアドレスデコータ１２０Ｂに、信号を出力する。ＡＴＤ回路１２１Ａでアドレス変化が検出されたアドレスが、図７に示すアドレスＡ５、Ａ６の場合、Ｙアドレスデコータ１２０Ｂにそのアドレスが供給され、アドレス変化がない時は、供給されない。　 FIG. 7 is a diagram illustrating a third example of the semiconductor memory device. The semiconductor memory 100B shown in FIG. 7 is the same as the semiconductor memory 100A shown in FIG. 3 in other configurations, except that the ATD circuit 121A detects changes in all address signals. As shown in FIG. 7, the ATD circuit 121A detects changes in all address signals. When the ATD circuit 121A detects changes in the signals A0 to A4, it outputs a word line selection signal for the memory cell array 110, and changes the signals in A5 and A6. When detected, a signal is output to Y address decoder 120B. When the address change detected by the ATD circuit 121A is the addresses A5 and A6 shown in FIG. 7, the address is supplied to the Y address decoder 120B, and is not supplied when there is no address change. *
ワード線を選択するのはＸアドレスだけでＹアドレスはビット線で出てきたデータをセレクトするだけであるため、メモリセルアレイ１１０の格納データに対するノイズ対策に、直接関係しない。しかしながら、Ｙアドレスも、Ｙアドレスデコーダ１２０Ｂにより、出力データを選択するために使用されるので、外部ノイズにより変異したアドレスにより、対象ではないメモリセルからデータを出力するという誤動作が起こり得る。そこで、Ｙアドレスの入力にもＡＴＤ回路１２１Ａを介することで、外部ノイズによるデータ出力という誤動作を防ぐことができる。　 Since the word line is selected only by the X address and the Y address only selects the data output by the bit line, it is not directly related to noise countermeasures for the data stored in the memory cell array 110. However, since the Y address is also used by the Y address decoder 120B to select output data, a malfunction may occur in which data is output from a non-target memory cell due to an address mutated by external noise. Therefore, the malfunction of data output due to external noise can be prevented by inputting the Y address via the ATD circuit 121A. *
〔２〕ＭＰＬＤの概要　ＭＰＬＤ（Ｍｅｍｏｒｙｂａｓｅｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｌｏｇｉｃ　Ｄｅｖｉｃｅ）は、ＬＵＴベースのＰＬＤと同様に、メモリセルアレイで回路構成を実現する。ＭＰＬＤは、真理値表データが書き込まれるメモリセルアレイが、論理要素として機能する点で、ＬＵＴベースのＰＬＤと同じであるが、ＬＵＴ同士の接続要素としても機能する点で、メモリセルアレイ間の接続に専用の切り替え回路を有するＬＵＴベースのＰＬＤと異なる。　 [2] Outline of MPLD MPLD (Memory Based Programmable Logic Device) realizes a circuit configuration with a memory cell array, similar to an LUT-based PLD. MPLD is the same as LUT-based PLD in that the memory cell array to which the truth table data is written functions as a logical element, but it also functions as a connection element between the LUTs. Different from the LUT-based PLD having a dedicated switching circuit. *
ＭＰＬＤもＳＲＡＭを使う再構成デバイスであり、ＭＰＬＤを構成するＭＬＵＴ（Ｍｕｌｔｉ　Ｌｏｏｋ－Ｕｐ－Ｔａｂｌｅ）はＳＲＡＭ構造である。従来のＭＰＬＤの場合は、配線も論理としてＭＬＵＴを使うために、ＭＬＵＴでの同期クロックでの遅延は大きな問題として、非同期ＳＲＡＭを使っていた。非同期ＳＲＡＭは、アドレスの切り替えに従い出力するので、ＭＰＬＤのＭＬＵＴとして、遅延の問題を解決する構造としては、は良い構造であった。ただ、メモリセルでビット線を駆動するために、トランジスタの寸法が大きくなりやすかった。また、必ずワード線が選択されているので読み出し時のノイズによりデータが書き換わりＭＰＬＤの誤動作の要因となっていた。また、今後の半導体微細化（９０ｎｍ以降の半導体プロセス）では、電源電圧の低下と共にメモリへの書き込みが出来なくなる問題がある。　 MPLD is also a reconfigurable device that uses SRAM, and MLUT (Multi Look-Up-Table) that constitutes MPLD has SRAM structure. In the case of the conventional MPLD, since the MLUT is used as the logic as the wiring, the delay with the synchronous clock in the MLUT is a big problem, and the asynchronous SRAM is used. Asynchronous SRAMs output in accordance with address switching, so that they are good structures for solving the delay problem as MPLD MLUTs. However, since the bit line is driven by the memory cell, the size of the transistor tends to be large. In addition, since the word line is always selected, the data is rewritten due to noise at the time of reading, causing a malfunction of the MPLD. Further, in future semiconductor miniaturization (semiconductor process after 90 nm), there is a problem that writing to the memory becomes impossible as the power supply voltage decreases. *
この問題は、同期方式のＳＲＡＭであれば、クロック動作時のみ書き込み読み出しを行い、その他の状態ではワード線を非選択としメモリセルの状態を保護することができる。また、出力にＦ／Ｆを持たせて論理を保持させることにより、読み出し時以外はビット線をHiレベルにして、デバイスの低電圧化でもメモリセル状態が保持でき、微細化での低電圧化に対応できる。　 The problem is that in the case of a synchronous SRAM, writing and reading can be performed only during clock operation, and in other states, the word line can be deselected to protect the memory cell state. In addition, by holding the logic by providing an F / F to the output, the bit line can be set to Hi level except during reading, so that the memory cell state can be maintained even when the voltage of the device is lowered, and the voltage is reduced by miniaturization. It can correspond to. *
しかし、同期ＳＲＡＭでは冒頭でも述べたように、同期クロックでのみの読み出し書き込みであり、配線などのＭＬＵＴの段数ごとのクロック段数遅延が見えて使うことができない。従来の非同期ＳＲＡＭでのＭＰＬＤでは配線や組み合わせ回路の表現は出来るが、順序回路の表現ができない。その対応としては、ＭＰＬＤの限られたＭＬＵＴのＡＤ対７（７つのＡＤ対のうち、周囲にあるＭＰＬＤと接続しないＡＤ対）にＦ／Ｆを付けて順序回路を構成できるようにした。しかし、順序回路表現でのＦ／Ｆ不足やＦ／Ｆ間に配線ＭＬＵＴを持たせなければならいので、動作速度の限界を持っていた。順序回路の表現には限られたＡＤ対にＦ／Ｆを持たせていたためにＦ／Ｆの使用数に限りがあり、且つ、先行技術（例えば、特開２０１０－２３９３２５号公報）ではＦ／Ｆの出力が自ＭＬＵＴに戻っているために、順序回路構成時、自ＭＬＵＴに信号が戻り（ＭＬＵＴ⇔Ｆ/Ｆ）、それをＭＬＵＴで配線する構造になり、搭載効率の弊害となる。　 However, as described at the beginning, the synchronous SRAM is read / write only with the synchronous clock, and the clock stage number delay for each number of MLUT stages such as wiring cannot be seen and used. MPLD in a conventional asynchronous SRAM can express wiring and combinational circuits, but cannot express sequential circuits. In order to cope with this, a sequential circuit can be configured by adding F / F to the AD pair 7 of the MLUT with a limited number of MPLDs (AD pair not connected to the surrounding MPLD among the seven AD pairs). However, since the F / F is insufficient in the sequential circuit representation and the wiring MLUT must be provided between the F / Fs, the operation speed is limited. In order to express sequential circuits, the number of F / Fs used is limited because the limited AD pairs have F / Fs, and in the prior art (for example, Japanese Patent Application Laid-Open No. 2010-239325), F / Fs are limited. Since the output of F is returned to its own MLUT, when a sequential circuit is configured, a signal is returned to its own MLUT (MLUT⇔F / F), and the MLUT is wired by MLUT, which adversely affects mounting efficiency. *
これを解決するために、ＭＬＵＴのＡＤ対各自にＦ／Ｆを内蔵させ、ＭＬＵＴ→Ｆ／Ｆ→ＭＬＵＴと一般的なＦ／Ｆ接続状態にしなければならない。これは同期ＳＲＡＭを使えば実現できるが、配線や組み合わせ回路でのＭＬＵＴ表現では弊害となる。また、非同期ＳＲＡＭでは微細化に対応する低電圧化では動作ができなくなるので、微細化対応の同期化が必要であった。　 In order to solve this problem, the AD pair of the MLUT must have a built-in F / F and a general F / F connection state such as MLUT → F / F → MLUT must be established. This can be realized by using a synchronous SRAM, but it is detrimental in MLUT representation with wiring and combinational circuits. In addition, since the asynchronous SRAM cannot operate at a low voltage corresponding to miniaturization, synchronization corresponding to miniaturization is necessary. *
〔３〕半導体メモリ装置を用いたＭＰＬＤ　そこで、上記した半導体メモリ装置を、ＭＬＵＴとして用いるＭＰＬＤを提案する。図８は、半導体メモリ装置を、ＭＬＵＴとして用いたＭＰＬＤの一例を示す図である。図８に示すＭＰＬＤ２０は、複数のＭＬＵＴ３０を有する。ＭＬＵＴ３０内の矩形は、半導体メモリ装置で説明した選択信号で切り替え可能なデータ出力線毎に設けられるＦ／Ｆである。この、Ｆ／Ｆは、データ入出力部１４０のＦ／Ｆに相当する。　 [3] MPLD using a semiconductor memory device Therefore, an MPLD using the semiconductor memory device described above as an MLUT is proposed. FIG. 8 is a diagram illustrating an example of an MPLD using a semiconductor memory device as an MLUT. The MPLD 20 shown in FIG. 8 has a plurality of MLUTs 30. The rectangle in the MLUT 30 is an F / F provided for each data output line that can be switched by the selection signal described in the semiconductor memory device. This F / F corresponds to the F / F of the data input / output unit 140. *
６方向配置のＭＬＵＴ（１つのＭＬＵＴの周囲に、６つのＭＬＵＴが配置され、中心にあるＭＬＵＴと周囲にある６つのＭＬＵＴが、それぞれ１つのＡＤ対で接続される。言い換えれば、ＭＬＵＴの６本のアドレス線は、周囲に配置されるの他の６個のＭＬＵＴのデータ線に、それぞれ接続され、ＭＬＵＴの６本のデータ線は、ＭＬＵＴの他の６個のＭＬＵＴのアドレス線に、それぞれ接続する）は、ＡＤ対に対して均一な接続を持たせることが出来るが、乗算回路などのようにＣＬＡ（キャリア・ルック・アヘッド）回路を２つ持つ回路では、自ＭＬＵＴ内で回路を実現できず、ＭＬＵＴをひとつ多く使用するので論理構成効率が悪い。一方、交互配置（１つのＭＬＵＴの周囲に、８つのＭＬＵＴが配置され、周囲にある４つのＭＬＵＴとＡＤ対と接続し、そのうち２つのＭＬＵＴとは２つのＡＤ対で接続する。例えば、特開２０１０－２３９３２５号公報の図１に開示されている）は隣接するＭＬＵＴに２つのＡＤ対を持たせ得るのでこの場合は交互配置が優位である。　 6-way MLUT (Six MLUTs are arranged around one MLUT, and the MLUT in the center and the six MLUTs in the periphery are each connected by one AD pair. In other words, six MLUTs Address lines are connected to the other six MLUT data lines arranged in the periphery, and the six MLUT data lines are connected to the other MLUT address lines of the MLUT, respectively. Is capable of providing a uniform connection to the AD pair, but a circuit having two CLA (carrier look-ahead) circuits such as a multiplier circuit can implement the circuit within its own MLUT. In addition, since one MLUT is used, the logical configuration efficiency is poor. On the other hand, alternating arrangement (eight MLUTs are arranged around one MLUT, and four MLUTs in the periphery are connected to an AD pair, and two MLUTs are connected by two AD pairs. 1 (disclosed in FIG. 1 of 2010-239325) can have two AD pairs in adjacent MLUTs, and in this case, the alternate arrangement is advantageous. *
しかしながら、６方向配置のＭＬＵＴは、接続要素として動作するＭＬＵＴの数を減らすことができるので、所望の論理回路を構成する記憶素子ブロックの総量を減らすことができるため、６方向配置のＭＬＵＴを可能な限り用いるのが好ましい。　 However, the MLUT arranged in 6 directions can reduce the number of MLUTs operating as connection elements, so that the total amount of storage element blocks constituting a desired logic circuit can be reduced, so that an MLUT arranged in 6 directions is possible. It is preferable to use as much as possible. *
また、従来方式のＭＬＵＴ間接続では、離間配線（離間配線は、近距離配線でないＭＬＵＴ間を結線するＡＤ対の配線をいう。例えば、特開２０１０－２３９３２５号公報の図１６に開示されている）が、ＡＤ対７でＭＬＵＴを飛んで配線させているので、長距離の配線においてＭＬＵＴを節約できる。ＡＤ対７を使い順序回路に必要なＦ／Ｆを接続すると、Ｆ／Ｆは自分のＭＬＵＴに戻る構造を持っている。また、離間配線とＦ／Ｆはある程度の比率で混在させている。この関係で順序回路を構成すると接続要素としてのＭＬＵＴが必要になり、論理構成効率が悪い。　 Further, in the conventional connection between MLUTs, the separated wiring (the separated wiring is an AD pair wiring that connects MLUTs that are not short-distance wiring. For example, it is disclosed in FIG. 16 of Japanese Patent Application Laid-Open No. 2010-239325. However, since the MLUT is jumped and wired in the AD pair 7, the MLUT can be saved in the long distance wiring. When the AD pair 7 is used and the necessary F / F is connected to the sequential circuit, the F / F has a structure that returns to its own MLUT. Further, the separated wiring and the F / F are mixed at a certain ratio. If a sequential circuit is configured in this relationship, an MLUT as a connection element is required, and the logical configuration efficiency is poor. *
そこで、図１、４又は７に示す半導体メモリ装置を、ＭＬＵＴとして用いる。図８に示すＭＬＵＴは、図１、４又は７に示す半導体メモリ装置を、６方向配置のＭＬＵＴとして用いた例である。ＭＬＵＴ（半導体メモリ装置）自体が、Ｆ／Ｆを持っており、外部にあるＦ／Ｆと接続するためにＡＤ対を使用する必要がないので、ＡＤ対７は全て離間配線に使うことができる。　 Therefore, the semiconductor memory device shown in FIG. 1, 4 or 7 is used as the MLUT. The MLUT shown in FIG. 8 is an example in which the semiconductor memory device shown in FIG. 1, 4 or 7 is used as a MLUT arranged in six directions. Since the MLUT (semiconductor memory device) itself has an F / F and there is no need to use an AD pair to connect to an external F / F, the AD pair 7 can all be used for separated wiring. . *
図１、４又は７に示す半導体メモリ装置を、ＭＬＵＴとして用いることで、選択データは、メモリセルアレイ１１０の選択データ用メモリセルで規定可能であるので、ＭＬＵＴが実現する回路も、同期が必要な回路と、同期が不要な回路に、ＭＬＵＴ内部で分けたり、１つのＭＬＵＴを動的に同期が必要な回路と、同期が不要な回路に使い分けることができる。例えば、組み合わせ回路や配線ロジックで非同期が必要な時は内部クロックとしてデータ線毎に非同期化して、順序回路のときは外部クロックでデータ線毎に同期化するように、ＭＬＵＴをデータ線毎に設定することができる。　 By using the semiconductor memory device shown in FIG. 1, 4 or 7 as the MLUT, the selection data can be defined by the memory cell for selection data in the memory cell array 110. Therefore, the circuit realized by the MLUT needs to be synchronized. The MLUT can be divided into a circuit and a circuit that does not require synchronization, or a single MLUT can be used separately for a circuit that requires dynamic synchronization and a circuit that does not require synchronization. For example, MLUT is set for each data line so that it is synchronized for each data line as an internal clock when asynchronous is required in the combinational circuit or wiring logic, and is synchronized for each data line with an external clock when it is a sequential circuit. can do. *
〔４〕ＭＰＬＤの詳細　図９Ａは、ＭＰＬＤの詳細例を示す図である。図９Ａに示す２０は、半導体装置としてのＭＰＬＤである。ＭＰＬＤ２０は、記憶素子ブロックとしてのＭＬＵＴ３０を複数有するとともに、ＭＬＵＴデコーダ１２を有する。また、後述するように、ＭＰＬＤ２０は、演算処理装置と接続する論理部として動作する。　 [4] Details of MPLD FIG. 9A is a diagram showing a detailed example of MPLD. Reference numeral 20 shown in FIG. 9A denotes an MPLD as a semiconductor device. The MPLD 20 includes a plurality of MLUTs 30 serving as storage element blocks and an MLUT decoder 12. As will be described later, the MPLD 20 operates as a logic unit connected to the arithmetic processing unit. *
ＭＰＬＤ２０は、複数の記憶素子を含む。記憶素子には、真理値表を構成するデータがそれぞれ記憶されることで、ＭＰＬＤ２０は、論理要素、又は、接続要素、又は、論理要素及び接続要素として動作する論理動作を行う。　 The MPLD 20 includes a plurality of storage elements. Since the data constituting the truth table is stored in the memory element, the MPLD 20 performs a logic operation that operates as a logic element, a connection element, or a logic element and a connection element. *
ＭＰＬＤ２０はさらに、メモリ動作を行う。メモリ動作とは、ＭＬＵＴ３０に含まれる記憶素子へのデータの書き込みや読み出しをいう。よって、ＭＰＬＤ２０は、主記憶装置や、キャッシュメモリとして動作することができる。　 The MPLD 20 further performs a memory operation. The memory operation refers to writing or reading of data to / from a storage element included in the MLUT 30. Therefore, the MPLD 20 can operate as a main storage device or a cache memory. *
ＭＬＵＴ
３０へのデータの書き込みは、真理値表データの書き換えにもなるため、メモリ動作は、真理値表データの再構成を生じる。なお、再構成のうち、ＭＰＬＤ内の特定の１つ又は複数のＭＬＵＴ、又はＭＬＵＴを構成する特定の１つ又は複数の記憶素子に記憶された真理値表データを書き換えることを「部分再構成」という。　 MLUT
Since writing data to 30 also rewrites truth table data, the memory operation causes reconstruction of the truth table data. In the reconfiguration, rewriting the truth table data stored in one or more specific MLUTs in the MPLD or one or more specific storage elements constituting the MLUT is “partial reconfiguration”. That's it.
〔４．１〕ＭＰＬＤのメモリ動作　図９Ｂは、ＭＰＬＤのメモリ動作の一例を示す図である。ＭＰＬＤ２０は、メモリ動作で、実線で示されるメモリ動作用アドレス、ＭＬＵＴアドレス、書き込みデータＷＤ、及び読み出しデータＲＤの何れかの信号を使用し、破線で示される論理動作用アドレスＬＡ、及び論理動作用データＬＤは使用しない。なお、メモリ動作用アドレス、ＭＬＵＴアドレス、及び書き込みデータは、例えば、ＭＰＬＤ２０の外部にある演算処理装置によって出力され、読み出しデータＷＤは、演算処理装置に出力される。　 [4.1] MPLD Memory Operation FIG. 9B is a diagram illustrating an example of the MPLD memory operation. The MPLD 20 uses any one of the memory operation address, MLUT address, write data WD, and read data RD indicated by the solid line in the memory operation, and the logical operation address LA indicated by the broken line and the logic operation Data LD is not used. Note that the memory operation address, the MLUT address, and the write data are output by, for example, an arithmetic processing device outside the MPLD 20, and the read data WD is output to the arithmetic processing device. *
メモリ動作では、ＭＰＬＤ２０は、記憶素子を特定するアドレスとして、メモリ動作用アドレス及びＭＬＵＴアドレスを受け取るとともに、書き込みのときは書き込みデータを受け取り、読み出しのときは読み出しデータＬＤを出力する。　 In the memory operation, the MPLD 20 receives the memory operation address and the MLUT address as addresses for specifying the storage element, receives write data at the time of writing, and outputs read data LD at the time of reading. *
ＭＬＵＴアドレスとは、ＭＰＬＤ２０内に含まれる１つのＭＬＵＴを特定するアドレスである。ＭＬＵＴアドレスは、ｌ本の信号線を介してＭＰＬＤ２０に出力される。なお、ｌとは、ＭＬＵＴを特定する選択アドレス信号線の数である。ｌ本の信号線で、２のｌ乗の数のＭＬＵＴを特定することができる。ＭＬＵＴデコーダ１２は、ｌ本の信号線を介してＭＬＵＴアドレスを受け取るとともに、ＭＬＵＴアドレスをデコードして、メモリ動作の対象となるＭＬＵＴ３０を選択し特定する。メモリ動作用アドレスは、ｌ本の信号線を介して、図１１を用いて後述するアドレスデコーダでデコードされて、メモリ動作の対象となるメモリセルを選択する。　 The MLUT address is an address that specifies one MLUT included in the MPLD 20. The MLUT address is output to the MPLD 20 via l signal lines. Note that l is the number of selected address signal lines that specify the MLUT. The number of MLUTs of 2 to the power of 1 can be specified by l signal lines. The MLUT decoder 12 receives the MLUT address via one signal line, decodes the MLUT address, and selects and specifies the MLUT 30 that is the target of the memory operation. The memory operation address is decoded by an address decoder, which will be described later with reference to FIG. 11, via l signal lines, and a memory cell to be subjected to the memory operation is selected. *
なお、ＭＰＬＤ２０は、例えば、ＭＬＵＴアドレス、書き込みデータ及び読み出しデータは、全てｎ本の信号線を介して受け取る。なお、ｎとは、図１０を用いて後述されるように、ＭＬＵＴのメモリ動作用又は論理動作用の選択アドレス信号線の数である。ＭＰＬＤ２０は、ｎ本の信号線を介して、ＭＬＵＴアドレス、書き込みデータ及び読み出しデータを各ＭＬＵＴに供給する。　 Note that the MPLD 20 receives, for example, the MLUT address, write data, and read data all via n signal lines. Note that n is the number of selected address signal lines for MLUT memory operation or logic operation, as will be described later with reference to FIG. The MPLD 20 supplies the MLUT address, write data, and read data to each MLUT via n signal lines. *
〔４．２〕ＭＰＬＤの論理動作　図９Ｃは、ＭＰＬＤ２０の論理動作の一例を示す図である。図９Ｃにおいて、ＭＰＬＤ２０の論理動作では、実線で示される論理動作用アドレス、及び論理動作用データの信号を使用する。　 [4.2] MPLD Logic Operation FIG. 9C is a diagram illustrating an example of the MPLD 20 logic operation. In FIG. 9C, the logic operation of the MPLD 20 uses a logic operation address and a logic operation data signal indicated by solid lines. *
ＭＰＬＤ２０の論理動作では、論理動作用アドレスは、外部装置から出力され、ＭＬＵＴ３０の真理値表によって構成される論理回路の入力信号として使用される。そして、論理動作用データ信号は、上記論理回路の出力信号であり、論理回路の出力信号として、外部装置に出力される。　 In the logic operation of the MPLD 20, the logic operation address is output from an external device and used as an input signal of a logic circuit configured by the truth table of the MLUT 30. The logic operation data signal is an output signal of the logic circuit, and is output to the external device as an output signal of the logic circuit. *
複数のＭＬＵＴのうち、ＭＰＬＤ２０の外延に配置されるＭＬＵＴは、ＭＰＬＤ２０の外部の装置と、論理動作用アドレスＬＡを受け取り、論理動作用データＬＤを出力するＭＬＵＴとして動作する。例えば、図９Ａに示すＭＬＵＴ３０ａ、３０ｂは、半導体装置１００の外部から論理動作用アドレスＬＡを受け取り、周囲にある他のＭＬＵＴ３０ｄに論理動作用データＬＤを出力する。また、図９Ａに示すＭＬＵＴ３０ｅ、３０ｆは、他のＭＬＵＴ３０ｃ、３０ｄから論理動作用アドレスＬＡを受け取り、ＭＰＬＤ２０の外部に論理動作用データＬＤを出力する。　 Among the plurality of MLUTs, the MLUT arranged outside the MPLD 20 operates as an MLUT that receives an apparatus for external operation of the MPLD 20 and the logical operation address LA and outputs the logical operation data LD. For example, the MLUTs 30a and 30b illustrated in FIG. 9A receive the logic operation address LA from the outside of the semiconductor device 100, and output the logic operation data LD to the other MLUTs 30d around. Also, the MLUTs 30e and 30f shown in FIG. 9A receive the logical operation address LA from the other MLUTs 30c and 30d and output the logical operation data LD to the outside of the MPLD 20. *
ＭＬＵＴの論理動作用アドレスＬＡのアドレス線は、隣接するＭＬＵＴの論理動作用データＬＤのデータ線と接続しており、例えば、ＭＬＵＴ３０ｃは、ＭＬＵＴ３０ａから出力された論理動作用データを、論理動作用アドレスとして受け取る。このように、ＭＬＵＴの論理動作用アドレス又は論理動作用データは、周囲にあるＭＬＵＴとの入出力により得られる点で、各々のＭＬＵＴが独自に接続するＭＬＵＴアドレスと異なる。　 The address line of the logical operation address LA of the MLUT is connected to the data line of the logical operation data LD of the adjacent MLUT. For example, the MLUT 30c converts the logical operation data output from the MLUT 30a into the logical operation address. Receive as. As described above, the MLUT logical operation address or the logical operation data is different from the MLUT address to which each MLUT is uniquely connected, in that the MLUT logical operation address or logical operation data is obtained by input / output with the surrounding MLUT. *
ＭＰＬＤ２０の論理動作により実現される論理は、ＭＬＵＴ３０に記憶される真理値表データにより実現される。いくつかのＭＬＵＴ３０は、ＡＮＤ回路、加算器などの組み合わせ回路としての論理要素として動作する。他のＭＬＵＴは、組み合わせ回路を実現するＭＬＵＴ３０間を接続する接続要素として動作する。論理要素、及び接続要素を実現するための真理値表データの書き換えは、上述のメモリ動作による再構成によりなされる。　 The logic realized by the logic operation of the MPLD 20 is realized by truth table data stored in the MLUT 30. Some MLUTs 30 operate as logic elements as combinational circuits such as AND circuits and adders. The other MLUTs operate as connection elements that connect the MLUTs 30 that realize the combinational circuit. Rewriting of truth table data for realizing the logic element and the connection element is performed by reconfiguration by the above-described memory operation. *
〔５〕ＭＬＵＴの詳細　以下に、ＭＬＵＴについて説明する。　図１０は、ＭＬＵＴの第１例を示す図である。図１０に示すＭＬＵＴ３０は、アドレス切替回路１０ａと、アドレスデコーダ９と、記憶素子４０と、出力データ切替回路１０ｂとを有する。図１０に示すＭＬＵＴ３０は、動作切替信号が論理動作を示す場合、論理動作用アドレスに従って、論理動作用データを出力するように動作する。また、ＭＬＵＴ３０は、動作切替信号がメモリ動作を示す場合、メモリ動作用アドレスに従って、書き込みデータを受け入れ、又は、読み出しデータを出力するように動作する。　 [5] Details of MLUT The MLUT will be described below. FIG. 10 is a diagram illustrating a first example of the MLUT. The MLUT 30 shown in FIG. 10 includes an address switching circuit 10a, an address decoder 9, a storage element 40, and an output data switching circuit 10b. When the operation switching signal indicates a logical operation, the MLUT 30 illustrated in FIG. 10 operates to output logical operation data according to the logical operation address. In addition, when the operation switching signal indicates a memory operation, the MLUT 30 operates to accept write data or output read data according to a memory operation address. *
アドレス切替回路１０ａは、メモリ動作用アドレスが入力されるｎ本のメモリ動作用アドレス信号線と、論理動作用アドレス信号が入力されるｎ本の論理動作用アドレス入力信号線と、動作切替信号が入力される動作切替信号線とを接続する。アドレス切替回路１０ａは、動作切替信号に基づいて、メモリ動作用アドレス、又は論理動作用アドレスのいずれかをｎ本の選択アドレス信号線に出力するように動作する。このように、アドレス切替回路１０ａが、アドレス信号線を選択するのは、記憶素子４０が読み出し動作と書き込み動作の何れかを受け付ける１ポート型の記憶素子であるからである。　 The address switching circuit 10a includes n memory operation address signal lines to which a memory operation address is input, n logic operation address input signal lines to which a logic operation address signal is input, and an operation switching signal. Connect the input operation switching signal line. The address switching circuit 10a operates so as to output either the memory operation address or the logic operation address to the n selected address signal lines based on the operation switching signal. As described above, the address switching circuit 10a selects the address signal line because the storage element 40 is a one-port type storage element that accepts either a read operation or a write operation. *
アドレスデコーダ９は、アドレス切替回路１０ａから供給されるｎ本のアドレス信号線から受け取った選択アドレス信号をデコードし、２のｎ乗本のワード線にデコード信号を出力する。　 The address decoder 9 decodes the selected address signal received from the n address signal lines supplied from the address switching circuit 10a, and outputs a decode signal to 2 n word lines. *
ｎ×２ｎ個の記憶素子は、２のｎ乗本のワード線と、ｎ本の書き込みデータ線と、ｎ個の出力ビット線の接続部分に配置される。　 n × 2 n memory elements are arranged at a connection portion of 2 n word lines, n write data lines, and n output bit lines.
出力データ切替回路１０ｂは、ｎ本の出力ビット線から信号を受け取ると、入力される動作切替信号に従って、読み出しデータをｎ本の読み出しデータ信号線に出力し、又は、読み出しデータを論理動作用信号線に出力するように動作する。　 When the output data switching circuit 10b receives signals from the n output bit lines, the output data switching circuit 10b outputs read data to the n read data signal lines in accordance with the input operation switching signal, or outputs the read data to the logic operation signal. Operates to output on a line. *
〔５．１〕ＭＬＵＴの論理動作　Ａ．論理要素　図１１は、論理要素として動作するＭＬＵＴの一例を示す図である。図１１に示すＭＬＵＴは、図１０に示すＭＬＵＴ又は図１、４又は７に示す半導体メモリ装置と同様な回路である。図１１では、説明を簡単にするために、アドレス切替回路１０ａ、及び出力データ切替回路１０ｂの記載は、省略される。図１１に示すＭＬＵＴ３０ａ、３０ｂは、４つの論理動作用アドレス線Ａ０～Ａ３と、４つの論理動作用データ線Ｄ０～Ｄ３と、４×１６＝６４個の記憶素子４０と、アドレスデコーダ９とをそれぞれ有する。論理動作用データ線Ｄ０～Ｄ３は、２４個の記憶素子４０をそれぞれ直列に接続する。アドレスデコーダ９は、論理動作用アドレス線Ａ０～Ａ３に入力される信号に基づき、２４本のワード線のいずれかに接続される４つの記憶素子を選択するように構成される。この４つの記憶素子はそれぞれ、論理動作用データ線Ｄ０～Ｄ３に接続され、記憶素子に記憶されるデータを論理動作用データ線Ｄ０～Ｄ３に出力する。例えば、論理動作用アドレス線Ａ０～Ａ３に適当な信号が入力される場合は、４つの記憶素子４０ａ、４０ｂ、４０ｃ、及び４０ｄを選択するように構成することができる。ここで、記憶素子４０ａは、論理動作用データ線Ｄ０に接続され、記憶素子４０ｂは、論理動作用データ線Ｄ１に接続され、記憶素子４０ｄは、論理動作用データ線Ｄ２に接続され、記憶素子４０ｄは、論理動作用データ線Ｄ３に接続される。そして、論理動作用データ線Ｄ０～Ｄ３には、記憶素子４０ａ～４０ｄに記憶される信号が出力される。このように、ＭＬＵＴ３０ａ、３０ｂは、論理動作用アドレス線Ａ０～Ａ３から論理動作用アドレスを受け取り、その論理動作用アドレスによってアドレスデコーダ９が選択する４つの記憶素子４０に記憶される値を、論理動作用データ線Ｄ０～Ｄ３に論理動作用データとしてそれぞれ出力する。なお、ＭＬＵＴ３０ａの論理動作用アドレス線Ａ２は、隣接するＭＬＵＴ３０ｂの論理動作用データ線Ｄ０と接続しており、ＭＬＵＴ３０ａは、ＭＬＵＴ３０ｂから出力される論理動作用データを、論理動作用アドレスとして受け取る。また、ＭＬＵＴ３０ａの論理動作用データ線Ｄ２は、ＭＬＵＴ３０ｂの論理動作用アドレス線Ａ０と接続しており、ＭＬＵＴ３０ａが出力する論理動作用データは、ＭＬＵＴ３０ｂで論理動作用アドレスとして受け取られる。例えば、ＭＬＵＴ３０ａの論理動作用データ線Ｄ２は、ＭＬＵＴ３０ａの論理動作用アドレス線Ａ０～Ａ３に入力される信号に基づき、論理動作用データ線Ｄ２に接続される２４個の記憶素子のいずれか１つに記憶される信号をＭＬＵＴ３０ｂの論理動作用アドレスＡ０に出力する。同様に、ＭＬＵＴ３０ｂの論理動作用データ線Ｄ０は、ＭＬＵＴ３０ｂの論理動作用アドレス線Ａ０～Ａ３に入力される信号に基づき、論理動作用データ線Ｄ０に接続される２４個の記憶素子のいずれか１つに記憶される信号をＭＬＵＴ３０ａの論理動作用アドレスＡ２に出力する。このように、ＭＰＬＤ同士の連結は、１対のアドレス線とデータ線とを用いる。以下、ＭＬＵＴ３０ａの論理動作用アドレス線Ａ２と、論理動作用データ線Ｄ２のように、ＭＬＵＴの連結に使用されるアドレス線とデータ線の対を「ＡＤ対」という。　 [5.1] Logic operation of MLUT Logical Element FIG. 11 is a diagram illustrating an example of an MLUT that operates as a logical element. The MLUT illustrated in FIG. 11 is a circuit similar to the MLUT illustrated in FIG. 10 or the semiconductor memory device illustrated in FIG. In FIG. 11, the description of the address switching circuit 10a and the output data switching circuit 10b is omitted to simplify the description. The MLUTs 30a and 30b shown in FIG. 11 include four logical operation address lines A0 to A3, four logical operation data lines D0 to D3, 4 × 16 = 64 storage elements 40, and an address decoder 9. Have each. The logic operation data lines D0 to D3 connect 24 memory elements 40 in series, respectively. The address decoder 9 is configured to select four storage elements connected to any of the 24 word lines based on signals input to the logic operation address lines A0 to A3. These four storage elements are connected to logic operation data lines D0 to D3, respectively, and output data stored in the storage elements to logic operation data lines D0 to D3. For example, when an appropriate signal is input to the logic operation address lines A0 to A3, the four memory elements 40a, 40b, 40c, and 40d can be selected. Here, the storage element 40a is connected to the logic operation data line D0, the storage element 40b is connected to the logic operation data line D1, and the storage element 40d is connected to the logic operation data line D2. 40d is connected to the logic operation data line D3. Then, signals stored in the storage elements 40a to 40d are output to the logic operation data lines D0 to D3. As described above, the MLUTs 30a and 30b receive the logical operation addresses from the logical operation address lines A0 to A3, and the values stored in the four storage elements 40 selected by the address decoder 9 based on the logical operation addresses are logically converted. The data is output to the operation data lines D0 to D3 as logic operation data. Note that the logical operation address line A2 of the MLUT 30a is connected to the logical operation data line D0 of the adjacent MLUT 30b, and the MLUT 30a receives the logical operation data output from the MLUT 30b as the logical operation address. The logical operation data line D2 of the MLUT 30a is connected to the logical operation address line A0 of the MLUT 30b, and the logical operation data output from the MLUT 30a is received as a logical operation address by the MLUT 30b. For example, the logic operation data line D2 of the MLUT 30a is one of 24 storage elements connected to the logic operation data line D2 based on signals input to the logic operation address lines A0 to A3 of the MLUT 30a. Is output to the logic operation address A0 of the MLUT 30b. Similarly, the logic operation data line D0 of the MLUT 30b is one of 24 storage elements connected to the logic operation data line D0 based on signals input to the logic operation address lines A0 to A3 of the MLUT 30b. The signal stored in one is output to the logic operation address A2 of the MLUT 30a. As described above, the MPLDs are connected by using a pair of address lines and data lines. Hereinafter, a pair of address lines and data lines used for MLUT connection, such as the logic operation address line A2 and the logic operation data line D2 of the MLUT 30a, is referred to as an "AD pair". *
なお、図１１では、ＭＬＵＴ３０ａ、３０ｂが有するＡＤ対は４であるが、ＡＤ対の数は、特に後述するように４に限定されない。　 In FIG. 11, the AD pairs included in the MLUTs 30a and 30b are 4, but the number of AD pairs is not limited to 4 as will be described later. *
図１２は、論理回路として動作するＭＬＵＴの一例を示す図である。本例では、論理動作用アドレス線Ａ０及びＡ１を２入力ＮＯＲ回路７０１の入力とし、論理動作用アドレス線Ａ２及びＡ３を２入力ＮＡＮＤ回路７０２の入力とする。そして、２入力ＮＯＲ回路の出力と、２入力ＮＡＮＤ回路７０２の出力を、２入力ＮＡＮＤ回路７０３に入力し、２入力ＮＡＮＤ回路７０３の出力を論理動作用データ線Ｄ０に出力する論理回路を構成する。　 FIG. 12 is a diagram illustrating an example of an MLUT that operates as a logic circuit. In this example, the logic operation address lines A 0 and A 1 are input to the 2-input NOR circuit 701, and the logic operation address lines A 2 and A 3 are input to the 2-input NAND circuit 702. Then, the output of the 2-input NOR circuit and the output of the 2-input NAND circuit 702 are input to the 2-input NAND circuit 703, and a logic circuit is configured to output the output of the 2-input NAND circuit 703 to the logic operation data line D0. . *
図１３は、図１２に示す論理回路の真理値表を示す図である。図１２の論理回路は、４入力のため、入力Ａ０～Ａ３の全ての入力を入力として使用する。一方、出力は、１つのみなので、出力Ｄ０のみを出力として使用する。真理値表の出力Ｄ１～Ｄ３の欄には「＊」が記載されている。これは、「０」又は「１」のいずれの値でもよいことを示す。しかしながら、実際に再構成のために真理値表データをＭＬＵＴに書き込むときには、これらの欄には、「０」又は「１」のいずれかの値を書き込む必要がある。　 FIG. 13 is a diagram showing a truth table of the logic circuit shown in FIG. Since the logic circuit of FIG. 12 has four inputs, all the inputs A0 to A3 are used as inputs. On the other hand, since there is only one output, only the output D0 is used as an output. “*” Is written in the columns of outputs D1 to D3 of the truth table. This indicates that any value of “0” or “1” may be used. However, when the truth table data is actually written into the MLUT for reconstruction, it is necessary to write either “0” or “1” in these fields. *
Ｂ．接続要素　図１４は、接続要素として動作するＭＬＵＴの一例を示す図である。図１４では、接続要素としてのＭＬＵＴは、論理動作用アドレス線Ａ０の信号を論理動作用データ線Ｄ１に出力し、論理動作用アドレス線Ａ１の信号を論理動作用データ線Ｄ２に出力し、論理動作用アドレス線Ａ２の信号を論理動作用データ線Ｄ３に出力するように動作する。接続要素としてのＭＬＵＴはさらに、論理動作用アドレス線Ａ３の信号を論理動作用データ線Ｄ１に出力するように動作する。　 B. Connection Element FIG. 14 is a diagram illustrating an example of an MLUT that operates as a connection element. In FIG. 14, the MLUT as a connection element outputs a signal of the logic operation address line A0 to the logic operation data line D1, and outputs a signal of the logic operation address line A1 to the logic operation data line D2. It operates so as to output the signal of the operation address line A2 to the logic operation data line D3. The MLUT as the connection element further operates to output the signal of the logic operation address line A3 to the logic operation data line D1. *
図１５は、図１４に示す接続要素の真理値表を示す図である。図１４に示す接続要素は、４入力４出力である。したがって、入力Ａ０～Ａ３の全ての入力と、出力Ｄ０～Ｄ３の全ての出力が使用される。図１５に示す真理値表によって、ＭＬＵＴは、入力Ａ０の信号を出力Ｄ１に出力し、入力Ａ１の信号を出力Ｄ２に出力し、入力Ａ２の信号を出力Ｄ３に出力し、入力Ａ３の信号を出力Ｄ０に出力する接続要素として動作する。　 FIG. 15 is a diagram showing a truth table of the connection elements shown in FIG. The connection element shown in FIG. 14 has 4 inputs and 4 outputs. Therefore, all inputs A0-A3 and all outputs D0-D3 are used. According to the truth table shown in FIG. 15, the MLUT outputs the signal of the input A0 to the output D1, outputs the signal of the input A1 to the output D2, outputs the signal of the input A2 to the output D3, and outputs the signal of the input A3. It operates as a connection element that outputs to the output D0. *
図１６は、ＡＤ０、ＡＤ１、ＡＤ２、及びＡＤ３の４つのＡＤ対を有するＭＬＵＴによって実現される接続要素の
一例を示す図である。ＡＤ０は、論理動作用アドレス線Ａ０と論理動作用データ線Ｄ０とを有する。ＡＤ１は、論理動作用アドレス線Ａ１と論理動作用データ線Ｄ１とを有する。ＡＤ２は、論理動作用アドレス線Ａ２と論理動作用データ線Ｄ２とを有する。そして、ＡＤ３は、論理動作用アドレス線Ａ３と論理動作用データ線Ｄ３とを有する。図１６において、１点鎖線は、ＡＤ対０の論理動作用アドレス線Ａ０に入力された信号がＡＤ対１の論理動作用データ線Ｄ１に出力される信号の流れを示す。２点鎖線は、第２のＡＤ対１の論理動作用アドレス線Ａ１に入力された信号がＡＤ対２の論理動作用データ線Ｄ２に出力される信号の流れを示す。破線は、ＡＤ対２の論理動作用アドレス線Ａ２に入力された信号がＡＤ対３の論理動作用データ線Ｄ３に出力される信号の流れを示す。実線は、ＡＤ対３の論理動作用アドレス線Ａ３に入力された信号がＡＤ対０の論理動作用データ線Ｄ０に出力される信号の流れを示す。　 FIG. 16 is a diagram illustrating an example of a connection element realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3. AD0 has a logic operation address line A0 and a logic operation data line D0. AD1 has a logic operation address line A1 and a logic operation data line D1. AD2 has a logic operation address line A2 and a logic operation data line D2. AD3 has a logic operation address line A3 and a logic operation data line D3. In FIG. 16, a one-dot chain line indicates a signal flow in which a signal input to the logic operation address line A0 of the AD pair 0 is output to the logic operation data line D1 of the AD pair 1. A two-dot chain line indicates a signal flow in which a signal input to the logic operation address line A1 of the second AD pair 1 is output to the logic operation data line D2 of the AD pair 2. A broken line indicates a flow of a signal that is input to the logic operation address line A2 of the AD pair 2 and output to the logic operation data line D3 of the AD pair 3. A solid line indicates a flow of a signal that is input to the logical operation address line A3 of the AD pair 3 and is output to the logical operation data line D0 of the AD pair 0.
なお、図１６では、ＭＬＵＴ３０が有するＡＤ対は４であるが、ＡＤ対の数は、特に４に限定されない。　 In FIG. 16, the MLUT 30 has four AD pairs, but the number of AD pairs is not particularly limited to four. *
Ｃ．論理要素と接続要素の組合せ機能　図１７は、１つのＭＬＵＴが、論理要素及び接続要素として動作する一例を示す図である。図１７に示す例では、論理動作用アドレス線Ａ０及びＡ１を２入力ＮＯＲ回路１７１の入力とし、２入力ＮＯＲ回路１７１の出力と、論理動作用アドレス線Ａ２とを２入力ＮＡＮＤ回路１７２の入力とし、２入力ＮＡＮＤ回路１７２の出力を論理動作用データ線Ｄ０に出力する論理回路を構成する。また同時に、論理動作用アドレス線Ａ３の信号を論理動作用データ線Ｄ２に出力する接続要素を構成する。　 C. Combination Function of Logic Element and Connection Element FIG. 17 is a diagram illustrating an example in which one MLUT operates as a logic element and a connection element. In the example shown in FIG. 17, the logic operation address lines A0 and A1 are input to the 2-input NOR circuit 171, and the output of the 2-input NOR circuit 171 and the logic operation address line A2 are input to the 2-input NAND circuit 172. A logic circuit is configured to output the output of the 2-input NAND circuit 172 to the logic operation data line D0. At the same time, a connection element for outputting the signal of the logic operation address line A3 to the logic operation data line D2 is formed. *
図１８に、図１７に示す論理要素及び接続要素の真理値表を示す。図１７の論理動作は、入力Ｄ０～Ｄ３の３つの入力を使用し、１つの出力Ｄ０を出力として使用する。一方、図１８の接続要素は、入力Ａ３の信号を出力Ｄ２に出力する接続要素が構成される。　 FIG. 18 shows a truth table of the logic elements and connection elements shown in FIG. The logic operation of FIG. 17 uses three inputs D0 to D3 and uses one output D0 as an output. On the other hand, the connection element in FIG. 18 is a connection element that outputs the signal of the input A3 to the output D2. *
図１９は、ＡＤ０、ＡＤ１、ＡＤ２、及びＡＤ３の４つのＡＤ対を有するＭＬＵＴによって実現される論理動作及び接続要素の一例を示す図である。図１６に示すＭＬＵＴと同様に、ＡＤ０は、論理動作用アドレス線Ａ０と論理動作用データ線Ｄ０とを有する。ＡＤ１は、論理動作用アドレス線Ａ１と論理動作用データ線Ｄ１とを有する。ＡＤ２は、論理動作用アドレス線Ａ２と論理動作用データ線Ｄ２とを有する。そして、ＡＤ３は、論理動作用アドレス線Ａ３と論理動作用データ線Ｄ３とを有する。上述のように、ＭＬＵＴ３０は、３入力１出力の論理動作と、１入力１出力の接続要素との２つの動作を１つのＭＬＵＴ３０で実現する。具体的には、論理動作は、ＡＤ対０の論理動作用アドレス線Ａ０と、ＡＤ対１の論理動作用アドレス線Ａ１と、ＡＤ対２の論理動作用アドレス線Ａ２とを入力として使用する。そして、ＡＤ対０の論理動作用データ線Ｄ０のアドレス線を出力と使用する。また、接続要素は、破線で示すようにＡＤ対３の論理動作用アドレス線Ａ３に入力された信号をＡＤ対２の論理動作用データ線Ｄ２に出力する。　 FIG. 19 is a diagram illustrating an example of logical operations and connection elements realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3. Similarly to the MLUT shown in FIG. 16, AD0 has a logic operation address line A0 and a logic operation data line D0. AD1 has a logic operation address line A1 and a logic operation data line D1. AD2 has a logic operation address line A2 and a logic operation data line D2. AD3 has a logic operation address line A3 and a logic operation data line D3. As described above, the MLUT 30 realizes two operations, ie, a logic operation with three inputs and one output and a connection element with one input and one output, with one MLUT 30. Specifically, the logic operation uses the logic operation address line A0 of AD pair 0, the logic operation address line A1 of AD pair 1, and the logic operation address line A2 of AD pair 2 as inputs. Then, the address line of the logic operation data line D0 of AD pair 0 is used as an output. Further, the connection element outputs a signal input to the logic operation address line A3 of the AD pair 3 to the logic operation data line D2 of the AD pair 2 as indicated by a broken line. *
上記したように、ＭＰＬＤ内のＭＬＵＴは、複数のアドレス線を介して互いに接続しているので、ワード線選択信号を介して、外部ノイズがメモリセルに書き込まれる御動作が生じやすい。そのため、ＭＬＵＴにＡＴＤ回路があることにより、アドレスが変化したときだけ、メモリセルへの書き込みが行われるので、外部ノイズの書き込み誤動作を回避できる。　 As described above, since the MLUTs in the MPLD are connected to each other via a plurality of address lines, an operation in which external noise is written to the memory cells easily occurs via the word line selection signal. Therefore, since there is an ATD circuit in the MLUT, writing to the memory cell is performed only when the address changes, so that it is possible to avoid a malfunction in writing external noise. *
以上説明した実施形態は典型例として挙げたに過ぎず、その各実施形態の構成要素の組合せ、変形及びバリエーションは当業者にとって明らかであり、当業者であれば本発明の原理及び請求の範囲に記載した発明の範囲を逸脱することなく上述の実施形態の種々の変形を行えることは明らかである。 The embodiments described above are merely given as typical examples, and combinations, modifications, and variations of the components of each embodiment will be apparent to those skilled in the art, and those skilled in the art will understand the principles and claims of the present invention. Obviously, various modifications may be made to the embodiments described above without departing from the scope of the described invention.
２０　　ＭＰＬＤ　３０　　ＭＬＵＴ　１００　　半導体メモリ装置　１１０　　メモリセルアレイ　１２０　　アドレスデコーダ　１２１　　ＡＴＤ回路　１２２　　クロック発生回路　１３０　　選択部　１３５　　ビットラインプリチャージ回路　１４０　　データ入出力部 20 MPLD 30 MLUT 100 Semiconductor memory device 110 Memory cell array 120 Address decoder 121 ATD circuit 122 Clock generation circuit 130 Selection unit 135 Bit line precharge circuit 140 Data input / output unit

Claims (9)

  1. 各々がデータを記憶する複数のメモリセルと、　前記メモリセルを特定するアドレス信号をデコードし、前記デコードされたアドレスに基づいた複数のメモリセルの一部に接続されるワード線の１つを選択するワード線選択信号を出力するアドレスデコーダと、　選択データを保持するとともに、前記選択データに基いて、外部から供給される外部クロックを選択する選択部と、　前記外部クロックが選択された場合、前記選択された外部クロックに同期して、又は、前記外部クロックが選択されなかった場合、前記外部クロックに同期せずに、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出すデータ読出部と、　を備えることを特徴とする半導体メモリ装置。 A plurality of memory cells each storing data, and an address signal specifying the memory cell are decoded, and one of the word lines connected to a part of the plurality of memory cells based on the decoded address is selected. An address decoder that outputs a word line selection signal, a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data, and when the external clock is selected, A part of the plurality of memory cells selected based on the word line selection signal without being synchronized with the external clock in synchronization with the selected external clock or when the external clock is not selected A semiconductor memory device comprising: a data reading unit that reads data from
  2. アドレス信号の変化を検出するアドレス変化検出部と、　内部クロックを発生するクロック発生回路をさらに備え、　前記アドレスデコーダは、前記アドレス変化検出部がアドレスの変化を検出したとき、前記ワード線選択信号の出力を行い、　前記選択部は、前記選択データに基づいて、前記内部クロックを選択し、　前記データ読出部は、前記外部クロックが選択されなかった場合、前記内部クロックに同期して、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出す、請求項１に記載の半導体メモリ装置。 An address change detection unit that detects a change in the address signal and a clock generation circuit that generates an internal clock are further provided. When the address change detection unit detects a change in the address, the address decoder detects the change in the word line selection signal. The selection unit selects the internal clock based on the selection data, and the data read unit synchronizes with the internal clock when the external clock is not selected. The semiconductor memory device according to claim 1, wherein data is read from a part of the plurality of memory cells selected based on a selection signal.
  3. 前記アドレスデコーダは、前記ワード線選択信号を出力するＸアドレスデコーダと、前記アドレス信号をデコードし、前記デコードされたアドレスに基づいて、前記データを読み出すビット線を選択するＹアドレスデコーダとを有する、請求項２に記載の半導体メモリ装置。 The address decoder has an X address decoder that outputs the word line selection signal, and a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address. The semiconductor memory device according to claim 2.
  4. 前記メモリセルアレイの一部のメモリセルには、前記選択データを保持し、　前記選択部は、前記メモリセルに保持される選択データに基づいて、外部から供給される外部クロックを選択する、請求項１～３の何れか１項に記載の半導体メモリ装置。 The memory cell of the memory cell array includes the selection data held in the memory cell, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell. 4. The semiconductor memory device according to any one of 1 to 3.
  5. 各々が複数のメモリセルアレイを有し、且つ、前記メモリセルアレイに真理値表データを書き込むと、論理要素又は接続要素として動作する複数の論理部を有する半導体装置であって、　前記論理部は、　各々がデータを記憶する複数のメモリセルと、　前記メモリセルを特定するアドレス信号をデコードし、前記デコードされたアドレスに基づいた複数のメモリセルの一部に接続されるワード線の１つを選択するワード線選択信号を出力するアドレスデコーダと、　選択データを保持するとともに、前記選択データに基いて、外部から供給される外部クロックを選択する選択部と、　前記外部クロックが選択された場合、前記選択された外部クロックに同期して、又は、前記外部クロックが選択されなかった場合、前記外部クロックに同期せずに、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出すデータ読出部と、を備えることを特徴とする半導体装置。 Each of the semiconductor devices has a plurality of memory cell arrays and has a plurality of logic units that operate as logic elements or connection elements when truth table data is written into the memory cell array. Decodes an address signal specifying the memory cell and selects one of the word lines connected to a part of the plurality of memory cells based on the decoded address. An address decoder that outputs a word line selection signal; a selection unit that holds selection data and selects an external clock supplied from the outside based on the selection data; and the selection when the external clock is selected Synchronized with the external clock, or if the external clock is not selected, synchronized with the external clock Not, a semiconductor device characterized by and a data reading unit for reading the data for some of the plurality of memory cells selected on the basis of said word line selection signal.
  6. アドレス信号の遷移を検出するアドレス信号遷移検出部と、　内部クロックを発生するクロック発生回路をさらに備え、　前記アドレスデコーダは、前記アドレス変化検出部がアドレス変化を検出したとき、前記ワード線選択信号の出力を行い、　前記選択部は、前記選択データに基づいて、前記内部クロックを選択し、　前記データ読出部は、前記外部クロックが選択されなかった場合、前記内部クロックに同期して、前記ワード線選択信号に基づいて選択される前記複数のメモリセルの一部に対してデータを読み出す、請求項５に記載の半導体装置。 An address signal transition detection unit for detecting a transition of the address signal and a clock generation circuit for generating an internal clock are further provided. When the address change detection unit detects an address change, the address decoder detects the word line selection signal. The selection unit selects the internal clock based on the selection data, and the data read unit synchronizes with the internal clock when the external clock is not selected. 6. The semiconductor device according to claim 5, wherein data is read from a part of the plurality of memory cells selected based on a selection signal.
  7. 前記アドレスデコーダは、前記ワード線選択信号を出力するＸアドレスデコーダと、前記アドレス信号をデコードし、前記デコードされたアドレスに基づいて、前記データを読み出すビット線を選択するＹアドレスデコーダとを有する、請求項５又は６に記載の半導体装置。 The address decoder has an X address decoder that outputs the word line selection signal, and a Y address decoder that decodes the address signal and selects a bit line from which the data is read based on the decoded address. The semiconductor device according to claim 5.
  8. 前記メモリセルアレイの一部のメモリセルには、前記選択データを保持し、　前記選択部は、前記メモリセルに保持される選択データに基づいて、外部から供給される外部クロックを選択する、請求項５～７の何れか１項に記載の半導体装置。 The memory cell of the memory cell array includes the selection data held in the memory cell, and the selection unit selects an external clock supplied from the outside based on the selection data held in the memory cell. 8. The semiconductor device according to any one of 5 to 7.
  9. 前記選択データは、前記論理部が組み合わせ回路や配線ロジックとして動作する場合は内部クロックに同期化して、前記論理部が順序回路として動作する場合は外部クロックに同期化するように設定される請求項８に記載の半導体装置。 The selection data is set to be synchronized with an internal clock when the logic unit operates as a combinational circuit or wiring logic, and is synchronized with an external clock when the logic unit operates as a sequential circuit. 8. The semiconductor device according to 8.
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WO2013153850A1 (en) * 2012-04-11 2013-10-17 太陽誘電株式会社 Reconfigurable semiconductor device
US9425798B2 (en) 2012-04-11 2016-08-23 Taiyo Yuden Co., Ltd. Reconfigurable semiconductor device
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