WO2013008967A1 - Led driver - Google Patents

Led driver Download PDF

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Publication number
WO2013008967A1
WO2013008967A1 PCT/KR2011/005133 KR2011005133W WO2013008967A1 WO 2013008967 A1 WO2013008967 A1 WO 2013008967A1 KR 2011005133 W KR2011005133 W KR 2011005133W WO 2013008967 A1 WO2013008967 A1 WO 2013008967A1
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WIPO (PCT)
Prior art keywords
voltage
led
channel
driving
gate
Prior art date
Application number
PCT/KR2011/005133
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French (fr)
Korean (ko)
Inventor
김진혁
김종선
정해양
배성호
Original Assignee
(주)실리콘인사이드
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Application filed by (주)실리콘인사이드 filed Critical (주)실리콘인사이드
Priority to KR1020117017785A priority Critical patent/KR101255176B1/en
Priority to PCT/KR2011/005133 priority patent/WO2013008967A1/en
Publication of WO2013008967A1 publication Critical patent/WO2013008967A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix
    • H05B45/46—Details of LED load circuits with an active control inside an LED matrix having LEDs disposed in parallel lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • H05B45/54—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits in a series array of LEDs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/10—Controlling the intensity of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/347—Dynamic headroom control [DHC]

Definitions

  • the present invention relates to a driving driver of a light emitting diode (LED), and relates to an LED driving driver that can be controlled even by detecting only a gate end and a source end of an LED channel transistor. That is, according to the present invention, since the LED is driven by the 2-PIN detecting method rather than the conventional 3-PIN detecting method, the number of pins allocated to one channel is reduced, so that the manufacturing cost is low and the LED can be efficiently controlled. Provide a driver.
  • LED light emitting diode
  • LEDs have high brightness overall and can be used in many applications, including backlighting of liquid crystal displays (LCDs).
  • LCDs liquid crystal displays
  • a backlight for an LCD monitor i) use one or more channels of white LEDs, including blue LEDs with phosphors (materials), to absorb blue light by the phosphors, Or ii) one or more individual channels of colored LEDs are placed adjacent to each other so that the light combined with each other looks like white light.
  • the LED channels made of the same type of LEDs also exhibit electrical characteristics such as different voltage drops. Because of this feature, in order to allow the same current to flow through each of the LED channels, a controllable element or the like connected in series to each LED channel to compensate for different voltage drops is required.
  • the driver for driving the LEDs must generate enough DC current to drive a series of LEDs, and its input voltage must be stepped up to a voltage sufficient to drive the LEDs.
  • the operation state of the LED has been controlled by using the 3-PIN method, that is, bias information of each of the drain, gate, and source of the transistor in the LED channel.
  • the 3-PIN method that is, bias information of each of the drain, gate, and source of the transistor in the LED channel.
  • the 3-PIN method since three pins are required for one channel, the number of pins of a chip required for a driving driver increases, thereby increasing the manufacturing cost and complicating the system.
  • the present invention has been made to solve the above-mentioned problems of the prior art, LED drive driver for driving the LED by the 2-PIN detection method away from the conventional 3-PIN detection method applied to the driver for driving the LED.
  • the purpose is to provide.
  • the present invention is another object to provide a LED drive driver to reduce the manufacturing cost, simplifying the system by reducing the number of pins of the LED chip per channel provided in the LED drive driver.
  • the driving voltage (V LED ) is input, LED channel unit having a plurality of LED channels connected to the at least one LED (Light Emitting Diode), the field effect transistor and the channel resistance in series ; A channel irradiator connected to the field effect transistor to control a constant current to flow in each LED channel, and determine whether the LED channel is open or short; And a driving voltage V LED that is connected to a gate terminal of the field effect transistor and compares a maximum gate voltage V G_MAX and a control voltage V CTL among a plurality of gate voltages V G.
  • V X Voltage; V X) is adjusted to be minimized in size and the power control channel to be supplied to the LED unit part; Including but, the channel irradiator provides an LED driving driver is connected to the gate terminal and the source terminal excluding the drain terminal of the field effect transistor.
  • the channel irradiation unit, the first OP-AMP and the output terminal is connected to the source terminal, the (-) terminal is connected to the source terminal, the (+) terminal is input to the reference voltage (V REF ) It is preferable to include a short circuit determination unit for comparing and outputting the source voltage V S and the open voltage V OPEN of the field effect transistor.
  • the channel irradiator further includes an analog-to-digital converter (AD converter) for analog-to-digital conversion of the gate voltage (V G ) value of each of the LED channel and stored in a predetermined registry.
  • AD converter analog-to-digital converter
  • the power control unit the gate voltage input terminal for receiving the gate voltage (V G ) of the plurality of LED channels to filter the maximum gate voltage (V G_MAX ); A control voltage input terminal to which a control voltage V CTL is input; GM-AMP comparing the maximum gate voltage (V G_MAX ) and the control voltage (V CTL ) to generate and output a current difference between the voltages; An inversion unit for inverting the output of the GM-AMP using the headroom voltage V X ; And a DC-DC converter that generates an optimized driving voltage (V LED.OPT ) by controlling a feedback loop using the output of the inverting unit.
  • the gate voltages V G and the control voltage V CTL are voltage-dropped by a diode and input to the GM-AMP.
  • the optimized driving voltage (V LED.OPT ) is preferably a voltage of which the headroom voltage of the LED channel is minimized in order to maximize power efficiency while all LED channels operate in a saturated state.
  • the field effect transistor is preferably an NMOS transistor.
  • the driving voltage increases linearly to a voltage at which all the LED channels can enter a saturation state. It is desirable to determine that the LED channel with no response even after the time t MAX elapses to open is open.
  • whether or not the LED channel is opened during normal operation increases linearly the driving voltage (V LED ) to a voltage at which all the LED channels can enter a saturation state. after the time taken (t MAX) last, it is preferable that it is determined that the source voltage (V S) by said irradiation unit is an open channel is detected as a voltage lower than an open voltage (V oPEN).
  • V MAX.VAR is the difference between the maximum drain voltage (V D.MAX ) and the minimum drain voltage (V D.MIN ) of the LED channel in a steady state
  • t R is the channel voltage increased by X ⁇ V REF .
  • X is a constant
  • t TOT is the time taken for the channel voltage to rise by V MAX.VAR .
  • the driving voltage (V LED.OPT ) optimized through headroom voltage control during a calibration period Is increased by a predetermined value and the gate voltage (V G ) of each channel is converted to analog-digital value and stored in the registry, and then the optimized driving voltage (V LED.OPT ) is decreased by the predetermined value in the normal operation section.
  • the gate voltage (V G) after collecting the value the gate voltage is collected in the normal operation period (V G) if the value is less than the calibration (calibration) gate voltage (V G) are stored in the interval value paragraph (short) It is preferable to determine that it is.
  • V G Gate voltage (V G) values in the calibration region a gate voltage (V G) value or a normal operation time period in the present invention, is periodically collected and it is desirable to determine whether short circuit (short).
  • the LED drive driver according to the present invention there is an effect of driving and controlling the LED by the 2-PIN detection method, away from the conventional 3-PIN detection method applied to the driver for driving the LED.
  • the present invention by reducing the number of pins of the LED chip required for each channel provided in the LED driver, it is possible to reduce the manufacturing cost of the LED driver and simplify the system.
  • FIG 1 is an illustration of an LED drive driver according to the prior art.
  • Figure 2 is an exemplary view of an LED drive driver according to an embodiment of the present invention.
  • FIG 3 is a graph showing a relationship between a gate voltage and a drain voltage according to an embodiment of the present invention.
  • 4 to 5 is a configuration diagram of the LED drive driver according to an embodiment of the present invention.
  • FIG. 6 is a configuration diagram of an LED channel according to an embodiment of the present invention.
  • FIG. 7 is a configuration diagram of a power control unit according to an embodiment of the present invention.
  • FIG. 8 is a graph showing a relationship between a control voltage and a drain voltage according to an embodiment of the present invention.
  • FIG 9 is a graph illustrating a relationship between a driving voltage and a source voltage at the start of driving an LED channel according to an embodiment of the present invention.
  • FIG 10 is an exemplary view of an LED channel unit including an open LED channel according to an embodiment of the present invention.
  • 11 is a graph showing a relationship between a driving voltage and a source voltage for each channel when one channel is opened at the start of driving the LED channel according to an embodiment of the present invention.
  • FIG. 12 is an exemplary view of a channel irradiation unit according to an embodiment of the present invention.
  • Figure 13 is an exemplary view of an LED channel unit including a shorted LED channel according to an embodiment of the present invention.
  • FIG. 14 is a graph showing a relationship between a driving voltage and a source voltage for each channel when one channel is shorted at the start of driving the LED channel according to an embodiment of the present invention.
  • 15 is a graph illustrating a short circuit determination reference voltage obtained during a calibration period and a gate voltage obtained during a normal period according to an embodiment of the present invention.
  • FIG. 16 is a graph illustrating a change in an optimized driving voltage according to a driving start section, a calibration section, and a normal operation section of an LED channel according to an embodiment of the present invention.
  • Figure 17 is an exemplary view showing the front end of the inverting portion provided with a power control unit according to an embodiment of the present invention.
  • FIG. 1 is an exemplary view of a LED driving driver according to the prior art.
  • Conventional LED drivers generally use a 3-PIN detection scheme that controls the LEDs outside the driver using all of the information of the drain 150, gate 160 and source 170 of the transistor of the LED channel.
  • FIG 2 is an exemplary view of a LED driving driver according to an embodiment of the present invention.
  • the main point is to reduce the number of pins of the chip allocated to the driver, headroom voltage control is performed using only the information of the gate G and the source S, and the LED channel is opened. Or it is configured to be able to determine whether short (short).
  • the voltage V S of the source terminal 170 may be set to the reference voltage V using the virtual short property of the OP-AMP. REF ).
  • a structure in which the change in the drain voltage V D is inferred and judged using the change in the gate voltage V G is obtained.
  • FIG 3 is a graph illustrating a relationship between a gate voltage and a drain voltage according to an embodiment of the present invention.
  • the gate voltage V G is changed and the state of the drain voltage V D is inferred using the change.
  • the distribution of the LED or the distribution of the transistor is represented by a change in the drain voltage (V D ).
  • V D drain voltage
  • V G gate voltage
  • 4 to 5 is a configuration diagram of the LED driving driver according to an embodiment of the present invention.
  • the driving voltage (V LED ) is input, LED channel unit 100 having a plurality of LED channels connected to the at least one diode, the field effect transistor and the channel resistance in series, the electric field It is connected to the effect transistor to control the constant current flow through each LED channel, and is connected to the channel irradiation unit 200 and the gate terminal of the field effect transistor to determine whether the LED channel open or short (short).
  • the driving voltage (V LED ) may be compared with the maximum gate voltage (V G_MAX ) and the control voltage (V CTL ) among the plurality of gate voltages (V G ) to minimize the headroom voltage (V X ). It may be configured to include a power control unit 300 to adjust the supply to the LED channel unit.
  • the present invention employs a 2-PIN detecting method, the channel irradiator 200 is connected to the gate terminal and the source terminal excluding the drain terminal of the field effect transistor, LED A constant current flows through the channel, and headroom voltage control and whether each LED channel is open or short is determined.
  • the channel irradiator includes a first OP having a positive terminal connected to a reference voltage V REF input terminal 210, a negative terminal connected to a source terminal of a transistor, and an output terminal thereof connected to a gate terminal of a transistor.
  • An AMP 220 and a short circuit determination unit 230 for comparing and outputting the source voltage V S and the open voltage V OPEN of the field effect transistor may be provided.
  • the short circuit determination unit 230 may be formed of a second OP-AMP to receive the source voltage V S and the open voltage V OPEN , and output a comparison value thereof.
  • the source voltage V S at the (+) terminal of the second OP-AMP, the open voltage V OPEN at the (-) terminal, or the source voltage It is possible to determine whether a short circuit by inputting the open voltage (V OPEN ) to the V S ), (+) terminal.
  • the reference voltage V REF serves to determine the magnitude of the current flowing through each channel by fixing the source voltage V S by the abnormal shorting property of the first OP-AMP.
  • the channel irradiator 200 may further include an analog-to-digital converter (AD converter) for analog-to-digital converting a gate voltage (V G ) value of each LED channel and storing it in a predetermined registry.
  • AD converter analog-to-digital converter
  • the power control unit 300 receives a gate voltage V G of the plurality of LED channels and filters a maximum gate voltage V G_MAX , and a control voltage terminal to which a control voltage V CTL is input.
  • GM-AMP 350 and headroom voltage V X 360 that compare the maximum gate voltage V G_MAX and the control voltage V CTL to generate and output the current difference;
  • Inverter 380 for inverting the output of the GM-AMP and DC-DC converter 370 for controlling the feedback loop using the output of the inverter to generate an optimized driving voltage (V LED.OPT ) It may be configured to include).
  • the optimized driving voltage may be a voltage of which the headroom voltage of the LED channel is minimized to maximize power efficiency while all LED channels operate in a saturated state.
  • the gate voltages V G and the control voltage V CTL are dropped by the diodes 310 and 320 and input to the GM-AMP 350.
  • the field effect transistor is an NMOS transistor. Is preferably.
  • FIG. 6 is a configuration diagram of an LED channel according to an embodiment of the present invention.
  • the LED channel of the present invention is connected to the driving voltage input terminal 110, the at least one LED (light emitting diode) 120, and the field effect transistor and the channel resistance 140 are sequentially connected to the driving voltage (V LED ) in sequence. It takes a structure to become.
  • the reference voltage V REF is input to a (+) terminal, a ( ⁇ ) terminal is connected to the source terminal 170, and an output terminal thereof is connected to the gate terminal 160. 1 shows OP-AMP 220 together.
  • the current I R passing through the channel resistor R 140 is determined by the voltage V a of the node a , that is, the source terminal voltage V S and the channel resistance R.
  • the voltage V a is equal to the reference voltage V REF due to the virtual short characteristic of the OP-AMP.
  • Equation 1 the current I R penetrating through the channel resistance R 140 may be expressed by Equation 1 below.
  • the forward current I F of the same LED as the current I R penetrating through the channel resistance R 140 may also be expressed by Equation 2 below.
  • the forward current (I F) of the LED will be able to because it is proportional to the reference voltage (V REF), by adjusting the reference voltage (V REF) to adjust the luminance (Brightness) of the LED.
  • the voltage V a of the node a (source terminal) is the same as the reference voltage V REF due to the abnormal shorting characteristic of the first OP-AMP, the voltage V a may be represented by Equation 3 below.
  • the voltage V b of the node (drain end) is equal to the driving voltage V LED minus the number of forward voltages (V F ) of n (the number of diodes), and is represented by Equation 4 below. Can be.
  • Equation 5 the condition for the NMOS transistor to operate in the saturation region is shown in Equation 5 below. That is, to be less than the drain voltage (V b) and the source voltage (V a), the saturation (saturation) the drain voltage (V DSAT) difference.
  • Equation 6 may be represented.
  • equation (6) can be summarized as shown in equation (7).
  • Equation 7 if the NMOS transistor is operating in the saturation region even though the driving voltage V LED increases, the forward current I F is determined by the reference voltage V REF and the channel resistance R. As determined, the brightness of the LED does not change. However, the V DS of the NMOS transistor is increased, and this V DS is called a headroom voltage, and can be expressed as Equation 8 below.
  • the LED driving driver of the present invention adjusts the driving voltage (V LED ) so that the headroom voltage is as small as possible when the transistors of all the LED channels operate in the saturation region, and the headroom voltage control It is called (Headroom Voltage Control). This will be described later.
  • FIG. 7 is a configuration diagram of a power control unit according to an embodiment of the present invention.
  • the power supply control unit the gate voltage input terminal for filtering the maximum gate voltage (V G_MAX ) by receiving the gate voltage (V G ) of the plurality of LED channels
  • the control voltage input terminal 340 is input the control voltage (V CTL ) GM-AMP 350 that compares the maximum gate voltage V G_MAX with the control voltage V CTL and generates and outputs a difference between the voltages as a current and a voltage V X between the source and drain terminals.
  • the gate voltage input terminal preferably includes a diode 310 to filter out the maximum gate voltage V G_MAX among the gate voltages V G input from each LED channel. That is, the maximum gate voltage V G_MAX is dropped by a predetermined value (for example, 0.7 V) by the diode 310 of the gate voltage input terminal, and accordingly, the control voltage input terminal diode 320 is provided to control the voltage V CTL. ) Is inputted to GM-AMP by a voltage drop to a predetermined degree.
  • the headroom voltage can be minimized by directly monitoring the drain voltage V D of the transistor.
  • the 2-PIN detecting method since the 2-PIN detecting method is used, the state of the drain voltage V D of the transistor must be inferred from the gate voltage V G.
  • the level of the gate voltage (V G ) when the transistor operates in a saturation region is set in advance.
  • the control voltage (V CTL ) which is a preset level value, is selected among the gate voltages (V G ) of each LED channel.
  • the feedback loop of the Dc-DC converter 370 is controlled in comparison with the maximum gate voltage V G_MAX , which is the highest gate voltage V G.
  • the maximum gate voltage V G_MAX and the control voltage V CTL are input to the GM-AMP 350 so that a difference is generated and outputted as a current, and the output of the Gm-AMP is a predetermined inversion.
  • the output is inverted by the voltage V Z.
  • the output of the inverting unit 380 controls the feedback loop of the DC-DC converter 370 to generate the optimized driving voltage V LED_OPT and then resupply the driving voltage input terminal of each LED channel.
  • the inverting unit 380 has a third OP-AMP having an output of Gm-AMP input to a (+) terminal, a (-) terminal connected to an output terminal thereof, and a predetermined inversion voltage (V) at a (+) terminal.
  • Z may be configured to include a fourth OP-AMP input, and may be formed such that the output of the Gm-AMP is inverted and output by appropriately disposing a resistor.
  • the DC-DC converter 370 adjusts a voltage fed back to the DC-DC converter 370 by the output of the inverting unit 380, thereby generating a driving voltage (V LED) generated by the DC-DC converter. Will be adjusted. That is, when the voltage fed back to the DC-DC converter 370 decreases, the DC-DC converter 370 generates a higher driving voltage V LED . On the contrary, when the voltage fed back increases, the driven output is increased. It will lower the voltage (V LED ).
  • FIG. 8 is a graph illustrating a relationship between a control voltage and a drain voltage according to an embodiment of the present invention.
  • a structure in which the drain voltage is inferred and determined by the gate voltage is used to determine the minimum drain voltage (V D.MIN ) for the NMOS transistor to operate in the saturation region.
  • V D.MIN minimum drain voltage
  • FIG. 9 is a graph showing a relationship between a driving voltage and a source voltage at the start of driving an LED channel according to an embodiment of the present invention.
  • V LED driving voltage
  • the field effect transistor operates in the linear region when the driving voltage V LED is low, the transistor at this time has a resistance component, and when the driving voltage V LED is linearly increased, the source of the transistor is Voltage V S also increases linearly. At this time, the current of the channel determined by the channel resistance (R) and the source voltage (V S ) also increases linearly.
  • the source voltage V S becomes equal to the fixed reference voltage V REF in accordance with the amount of current to flow in the channel in advance. Accordingly, it is possible when the source voltage (V S) is turned the same as the reference voltage (V REF) LED channel can be determined deuleogatdago in saturation.
  • the reference voltage V REF is fixed to a limit for optimizing the driving voltage V LED to saturate all channels, and thus may be used as a constant current source.
  • FIG 10 is an exemplary view of an LED channel unit including an open LED channel according to an embodiment of the present invention.
  • 11 is a graph illustrating a relationship between a driving voltage and a source voltage for each channel when one channel is opened at the start of driving the LED channel according to an embodiment of the present invention.
  • the LED drive driver of the present invention linearly increases the drive voltage (V LED ) to a sufficient voltage for all LED channels to enter the saturation region at the start-up of the drive. That is, when the time for increasing the driving voltage (V LED) linearly to a sufficient voltage in all the LED channel is getting into the saturation region t MAX la, after the t MAX last response (eg, a source voltage (V S) The channel without the increase of is determined to be open.
  • FIG. 12 is an exemplary view of a channel irradiator according to an embodiment of the present invention.
  • the channel irradiator includes a first OP ⁇ connected to the reference voltage V REF at a positive terminal, a negative terminal connected to the source terminal 170, and an output terminal connected to the gate terminal.
  • the AMP 220 and the short-circuit determination unit 230 comparing the source voltage V S and the open voltage V OPEN of the field effect transistor may be output.
  • the channel irradiator controls i) a constant current to flow through the channel by fixing the source voltage V S of the transistor to the reference voltage V REF , and ii) controlling the LED channel through the short circuit determination unit 230. investigate the opening and, iii) by using a short-circuit whether research and iv) a source voltage (V S) of the transistor during normal operation via the AD converter and performs a function to check whether the short circuit at the start of driving.
  • the short circuit determination unit 230 is a source voltage (V S ) of the field effect transistor (FET) is input to the (+) terminal, open voltage (V OPEN ) to the (-) terminal This may be configured as the input 2OP-AMP. On the contrary, the source voltage V S of the field effect transistor FET is input to the negative terminal and the open voltage V OPEN is input to the positive terminal.
  • V S source voltage
  • V OPEN open voltage
  • the channel irradiator By using the channel irradiator, it is possible to detect whether the LED channel is open in the normal operation.
  • the source voltage V S is the gate voltage V G. ) so down to ground level, regardless of, upon detecting a source voltage (V S) by using the first OP-AMP 2, it will be able to determine whether the open (open).
  • FIG. 13 is an exemplary view of an LED channel unit including a shorted LED channel according to an embodiment of the present invention
  • FIG. 14 is a case where one channel is shorted at the start of driving an LED channel according to an embodiment of the present invention. Is a graph showing the relationship between driving voltage and source voltage for each channel.
  • the drain voltage V D2 of the shorted channel is smaller than the drain voltages V D1 , V D3 and V D4 of another channel (eg, 2.5 V). Will rise by.
  • V MAX.VAR for determining whether or not a short circuit for each channel is defined by Equation 9 below, where V MAX.VAR is a difference between drain voltages allowed when all LED channels are saturated, in other words, It may be defined as the difference between the maximum drain voltage (V D.MAX ) and the minimum drain voltage (V D.MIN ) of the LED channel in a normal state.
  • the V MAX.VAR may be referred to as the variation range of the drain voltage (V D ) that is permitted in various applications to which the LED driving driver of the present invention is applied, and V MAX.VAR from the minimum value of the drain voltage (V D.MIN ). It is determined that the LED channel having the above drain voltage V D is bad.
  • Equation 9 is that V MAX.VAR means an allowable maximum value of the nV F difference caused by the forward voltage (V F ) of the LED when the LED is normally connected to the channel. can do. Therefore, when the drain voltage of each channel exceeds 2.0 V when the channel is normally connected, the channel having the highest drain voltage may be determined to be defective.
  • t TOT may be expressed as in the following equation.
  • the first driving voltage (V LED) is X ⁇ V REF for the time it takes to rise measured by using a counter as a t R, and the above equation V MAX.VAR (2.0V) and the X ⁇ V REF and t Substituting R makes t TOT easy to find.
  • X represents a constant.
  • 0.5V REF can be substituted, and it is preferable to select from the range of 0.25V REF to 0.75V REF .
  • each LED channel is saturated.
  • t TOT is reversely substituted from the last saturated channel as time passes, and it is determined that a channel saturated before t TOT is shorted. That is, the short-circuit since it is possible the drain voltage of the first channel than the saturated T TOT (V D) is more than V MAX.VAR higher than the drain voltage in the saturation channels to the last (V D) is determined from the calculated channel is saturated at the end It can be judged.
  • t TOT is divided from four channels, which are the last saturated channels, to short-circuit two channels, which are previously saturated channels.
  • 15 is a graph illustrating a short circuit determination reference voltage obtained during a calibration period and a gate voltage obtained during a normal period according to an embodiment of the present invention.
  • FIG. 15 illustrates a change in the gate voltage V G that can be monitored in the 2-PIN detecting method of the present invention according to the change of the drain voltage V D during the calibration period and the normal operation period.
  • a predetermined procedure is performed to determine whether the LED channel is short-circuited during normal operation.
  • the gate voltage of each channel obtained by artificially raising the driving voltage V LED by a predetermined value during a calibration period is provided.
  • the (V G ) values become the short-circuit determination reference voltage V SHT .
  • the calibration artificially raises the driving voltage (V LED ) by the drain voltage (V D ) which will increase when any one of the LED channels is short-circuited, thereby raising the driving voltage (V LED ).
  • the purpose is to obtain the gate voltage V G in the quasi-section. As will be described later, if the gate voltage V G obtained in the normal operation period is lower than the gate voltage V G obtained during the calibration period, it is determined that a short circuit has occurred in the channel.
  • the gate voltage V G should be repeatedly obtained in the normal operation section in order to determine whether the channel is shorted.
  • the acquisition of the gate voltage V G value in the calibration period is also preferably performed periodically.
  • the drain voltage V D should be inferred by using the gate voltage V G.
  • the short-circuit determination reference voltage V SHT is used. The short circuit determination reference voltage V SHT is periodically checked and used.
  • 16 is a graph illustrating a change in an optimized driving voltage according to a driving start section, a calibration section and a normal operation section of an LED channel according to an embodiment of the present invention.
  • the driving voltage V LED increases linearly until the optimized driving voltage V LED .OPT is achieved .
  • V LED.OPT drive voltage
  • V G gate voltage
  • V MAX.VAR is a difference between the drain voltages allowed when all the LED channels are saturated.
  • V MAX.VAR is the difference between the maximum value of each channel's drain voltage (V D.MAX ) and the minimum value of the drain voltage (V D.MIN ). It's a car.
  • V V MAX.VAR MAX.VAR from the drain voltage (V D) the minimum value (V D.MIN) can be described as the variation range, and the drain voltage of which is allowed by the various applications to be applied to the LED drive driver of the present invention It is determined that the LED channel having the above drain voltage V D is bad.
  • V LED.OPT a method of increasing the optimized driving voltage (V LED.OPT ) by V MAX.VAR (about 2.5V), if the voltage input to the inverting part is increased for a necessary time, the inverting output is DC-DC. The feedback voltage of the converter will drop, resulting in an easy way to increase the optimized drive voltage (V LED.OPT ).
  • T R is a time required to increase V S by 0.5 V
  • T TOT is a time required to increase channel voltage by V MAX_VAR
  • the T DC is driven by the DCDC converter of the power control unit during the time of T TOT .
  • voltage (V LED) give the information has not been optimized (optimize), driving voltage (V LED) will be raised by V MAX_VAR.
  • the power controller when the voltage output to the inverter is adjusted through the first switch SW1, the power controller performs a normal headroom voltage control operation to optimize the driving voltage V LED_OPT . Will be supplied.
  • V LED driving voltage
  • V LED_OPT optimized driving voltage
  • V LED_OPT V LED_OPT
  • the current entering the capacitance through the second switch SW2 has a 1 / Gm value which is an inverse value of the Gm value of Gm-AMP.
  • the gate voltage V G of each LED channel is converted into a digital value by using an AD converter in the optimized driving voltage V LED.OPT section and stored in the registry.
  • the data based on the stored gate voltage V G values becomes a short-circuit determination reference voltage V SHT for determining whether a short circuit occurs.
  • V LED.OPT driving voltage
  • V LED.OPT headroom Voltage Control
  • the gate voltage V G of each channel is periodically collected in the normal operation period.
  • the gate voltage (V G ) of each channel is converted into a digital value through analog-to-digital conversion, and the gate voltage is higher than the value of the data stored in the registry, that is, the short-circuit determination reference voltage (V SHT ), during the calibration period 520. If the (V G ) value is small, it is determined that it is short.

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Abstract

The present invention relates to an LED (light emitting diode) driver, and more particularly, to an LED driver capable of performing a control even when detecting only a gate terminal and a source terminal of an LED channel transistor.

Description

LED 구동 드라이버LED drive driver
본 발명은 LED(Light Emitting Diode)의 구동 드라이버에 관한 것으로서, LED 채널 트랜지스터의 게이트(gate)단 및 소스(source)단만을 디텍팅(Detecting)하여도 제어가 가능한 LED 구동 드라이버에 관한 것이다. 즉, 본 발명에 의하면, 종래의 3-PIN 디텍팅 방식이 아니라 2-PIN 디텍팅 방식에 의해 LED를 구동하게 되므로, 하나의 채널별로 할당되는 핀수가 줄어들어 제조비용이 저렴하면서도 효율적인 제어가 가능한 LED 구동 드라이버를 제공한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving driver of a light emitting diode (LED), and relates to an LED driving driver that can be controlled even by detecting only a gate end and a source end of an LED channel transistor. That is, according to the present invention, since the LED is driven by the 2-PIN detecting method rather than the conventional 3-PIN detecting method, the number of pins allocated to one channel is reduced, so that the manufacturing cost is low and the LED can be efficiently controlled. Provide a driver.
최근, 다수개의 LED 채널 또는 LED 스트링으로 이루어진 LED 광원 장치는 LCD 패널의 백라이트 또는 각종 조명 응용기기 등을 위한 용도로 신속하게 보급되고 있다. LED는 전체적으로 고광도를 가지며, 액정 디스플레이(LCD)의 백라이트를 포함한 많은 응용기기에서 사용될 수 있다. Recently, an LED light source device composed of a plurality of LED channels or LED strings is rapidly being used for a backlight of LCD panels or various lighting applications. LEDs have high brightness overall and can be used in many applications, including backlighting of liquid crystal displays (LCDs).
예를 들어, LCD 모니터에 대한 백라이트를 공급하기 위해서는, i) 형광체(물질)를 가지는 청색 LED를 포함하는 백색 LED로 구성된 하나 이상의 채널을 사용하여, 상기 형광체에 의해 청색광을 흡수하며, 백색 광을 방출하는 방식을 이용하거나, ii) 유색 LED로 구성된 하나 이상의 개별적인 채널이 인접하게 배치되어, 서로 조합된 광이 백색 광처럼 보이도록 하는 방식을 취할 수 있다. For example, to supply a backlight for an LCD monitor, i) use one or more channels of white LEDs, including blue LEDs with phosphors (materials), to absorb blue light by the phosphors, Or ii) one or more individual channels of colored LEDs are placed adjacent to each other so that the light combined with each other looks like white light.
그런데, LED 채널을 이루는 각 LED 소자들간의 특성 편차, 즉 순방향 전압강하 등의 편차로 인하여, 동종의 LED들로 이루어진 LED 채널들도 서로 다른 전압 강하 등의 전기적 특성을 나타낸다. 이와 같은 특성 때문에, LED 채널 각각을 통해 동일한 전류가 흐르도록 하기 위해, 서로 다른 전압 강하를 보상할 각각의 LED 채널에 직렬로 연결된 제어 가능한 소자 등을 필요로 하게 된다. However, due to the characteristic deviation between the LED elements constituting the LED channel, that is, the forward voltage drop, the LED channels made of the same type of LEDs also exhibit electrical characteristics such as different voltage drops. Because of this feature, in order to allow the same current to flow through each of the LED channels, a controllable element or the like connected in series to each LED channel to compensate for different voltage drops is required.
즉, LED를 구동하기 위한 드라이버는 일련의 LED들을 구동하기에 충분한 DC 전류를 생성해야 하고, 그 입력 전압은 LED들을 구동하기에 충분한 전압까지 스텝 업(step up)되어야 한다.That is, the driver for driving the LEDs must generate enough DC current to drive a series of LEDs, and its input voltage must be stepped up to a voltage sufficient to drive the LEDs.
종래기술에 의하면, 3-PIN 방식, 즉 LED 채널내의 트랜지스터의 드레인, 게이트 및 소스 각각의 바이어스 정보를 이용하여 LED의 작동상태를 제어하여 왔다. 그러나, 이와 같은 3-PIN 방식에 의하면, 하나의 채널당 3개의 핀수가 필요한 바, 구동 드라이버에 소요되는 칩의 핀수가 많아져서 제조비용이 상승하고, 또한 시스템이 복잡해 지는 문제점이 있었다. According to the prior art, the operation state of the LED has been controlled by using the 3-PIN method, that is, bias information of each of the drain, gate, and source of the transistor in the LED channel. However, according to such a 3-PIN method, since three pins are required for one channel, the number of pins of a chip required for a driving driver increases, thereby increasing the manufacturing cost and complicating the system.
따라서, 이와 같은 3-PIN 방식의 문제점을 해결하여, 제조비용이 저렴하고, 시스템이 단순해지더라도 LED 제어의 효율이 좋은 LED 구동드라이버가 요구되고 있다. Accordingly, there is a need for an LED driving driver having a low manufacturing cost and good efficiency of LED control even if the system is simplified by solving such a problem of the 3-PIN method.
본 발명은 전술한 종래기술의 문제점을 해결하기 위해 안출된 것으로서, LED를 구동시키는 드라이버에 적용되는 종래의 3-PIN 디텍팅 방식에서 벗어나 2-PIN 디텍팅 방식에 의해 LED를 구동시키는 LED 구동드라이버를 제공하는데 그 목적이 있다. The present invention has been made to solve the above-mentioned problems of the prior art, LED drive driver for driving the LED by the 2-PIN detection method away from the conventional 3-PIN detection method applied to the driver for driving the LED. The purpose is to provide.
또한, 본 발명은 LED 구동드라이버에 제공되는 하나의 채널당 소요되는 LED 칩의 핀수를 절감함으로써 제조비용을 절감하고, 시스템을 단순화한 LED 구동드라이버를 제공하는데 또 다른 목적이 있다.In addition, the present invention is another object to provide a LED drive driver to reduce the manufacturing cost, simplifying the system by reducing the number of pins of the LED chip per channel provided in the LED drive driver.
본 발명이 이루고자 하는 기술적 과제들은 이상에서 언급한 기술적 과제들로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 본 발명의 기재로부터 당해 분야에서 통상의 지식을 가진 자에게 명확하게 이해될 수 있을 것이다. Technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description of the present invention. .
본 발명의 LED 구동드라이버에 의하면, 구동전압(VLED)이 입력되며, 적어도 하나 이상의 LED(Light Emitting Diode)와, 전계효과 트랜지스터 및 채널저항이 직렬로 연결되는 LED 채널을 다수 구비하는 LED 채널부; 상기 전계효과 트랜지스터에 연결되어 각 LED채널에 일정한 전류가 흐르도록 제어하고, 상기 LED 채널의 개방(open)여부 또는 단락(short)여부를 판정하는 채널조사부; 및 상기 전계효과 트랜지스터의 게이트단과 연결되며, 다수의 게이트 전압(VG) 중 최대 게이트 전압(VG_MAX) 및 컨트롤 전압(VCTL)을 비교하여 상기 구동전압(VLED)을 헤드룸 전압(Headroom Voltage; VX)이 최소화되는 크기로 조절하여 상기 LED 채널부에 공급하는 전원조절부; 를 포함하되, 상기 채널조사부는 상기 전계효과 트랜지스터의 드레인(drain)단을 제외한 게이트(gate)단과 소스(source)단에 연결되는 것을 특징으로 하는 LED 구동 드라이버를 제공한다. According to the LED driving driver of the present invention, the driving voltage (V LED ) is input, LED channel unit having a plurality of LED channels connected to the at least one LED (Light Emitting Diode), the field effect transistor and the channel resistance in series ; A channel irradiator connected to the field effect transistor to control a constant current to flow in each LED channel, and determine whether the LED channel is open or short; And a driving voltage V LED that is connected to a gate terminal of the field effect transistor and compares a maximum gate voltage V G_MAX and a control voltage V CTL among a plurality of gate voltages V G. Voltage; V X) is adjusted to be minimized in size and the power control channel to be supplied to the LED unit part; Including but, the channel irradiator provides an LED driving driver is connected to the gate terminal and the source terminal excluding the drain terminal of the field effect transistor.
본 발명에서 상기 채널조사부는, (+)단에 상기 기준전압(VREF)이 입력되고, (-)단이 상기 소스단과 연결되며, 그 출력단이 상기 게이트단과 연결되는 제1 OP-AMP 및 상기 전계효과 트랜지스터의 소스전압(VS)과 오픈전압(VOPEN)을 비교하여 출력하는 단락판단부를 구비하는 것이 바람직하다.In the present invention, the channel irradiation unit, the first OP-AMP and the output terminal is connected to the source terminal, the (-) terminal is connected to the source terminal, the (+) terminal is input to the reference voltage (V REF ) It is preferable to include a short circuit determination unit for comparing and outputting the source voltage V S and the open voltage V OPEN of the field effect transistor.
본 발명에서 상기 채널조사부는, 상기 각각의 LED 채널의 게이트 전압(VG)값을 아날로그-디지털 변환하여 소정의 레지스트리에 저장하는 AD 컨버터(Analog-Digital Converter)를 더 포함하는 것이 바람직하다.In the present invention, the channel irradiator further includes an analog-to-digital converter (AD converter) for analog-to-digital conversion of the gate voltage (V G ) value of each of the LED channel and stored in a predetermined registry.
본 발명에서 상기 전원조절부는, 상기 다수의 LED 채널의 게이트 전압(VG)들을 입력받아 최대 게이트전압(VG_MAX)을 걸러내는 게이트 전압 입력단; 컨트롤 전압(VCTL)이 입력되는 컨트롤 전압입력단; 상기 최대 게이트전압(VG_MAX)과 상기 컨트롤 전압(VCTL)을 비교하여 그 전압의 차이를 전류로 생성하여 출력하는 GM-AMP; 상기 헤드룸 전압(VX)을 이용하여 상기 GM-AMP의 출력을 반전시키는 반전부; 및 상기 반전부의 출력을 이용하여 피드백 루프를 제어하여 최적화된 구동전압(VLED.OPT)를 생성하는 DC-DC 컨버터;를 포함하는 것이 바람직하다. In the present invention, the power control unit, the gate voltage input terminal for receiving the gate voltage (V G ) of the plurality of LED channels to filter the maximum gate voltage (V G_MAX ); A control voltage input terminal to which a control voltage V CTL is input; GM-AMP comparing the maximum gate voltage (V G_MAX ) and the control voltage (V CTL ) to generate and output a current difference between the voltages; An inversion unit for inverting the output of the GM-AMP using the headroom voltage V X ; And a DC-DC converter that generates an optimized driving voltage (V LED.OPT ) by controlling a feedback loop using the output of the inverting unit.
본 발명에서 상기 게이트 전압(VG)들과 컨트롤 전압(VCTL)은 다이오드에 의해 전압강하되어 상기 GM-AMP에 입력되는 것이 바람직하다.In the present invention, it is preferable that the gate voltages V G and the control voltage V CTL are voltage-dropped by a diode and input to the GM-AMP.
본 발명에서 상기 최적화된 구동전압(VLED.OPT)은, 모든 LED 채널이 포화상태에서 동작하면서 전력효율을 최대화하기 위해 LED채널의 헤드룸 전압이 최소화되는 크기의 전압인 것이 바람직하다. In the present invention, the optimized driving voltage (V LED.OPT ) is preferably a voltage of which the headroom voltage of the LED channel is minimized in order to maximize power efficiency while all LED channels operate in a saturated state.
본 발명에서 상기 헤드룸 전압(Headroom Voltage)의 조절은, 상기 전계효과 트랜지스터가 포화영역에서 동작할 때의 게이트 전압(VG)의 레벨을 미리 설정하여 컨트롤 전압(VCTL)을 정한 후, 상기 최대 게이트 전압(VG_MAX)과 컨트롤 전압(VCTL)을 비교하여 상기 구동전압(VLED)의 크기를 조절하는 것이 바람직하다. In the present invention, the adjustment of the headroom voltage (Headroom Voltage), after setting the level of the gate voltage (V G ) when the field effect transistor is operating in a saturation region in advance to determine the control voltage (V CTL ), It is preferable to adjust the magnitude of the driving voltage V LED by comparing the maximum gate voltage V G_MAX with the control voltage V CTL .
본 발명에서 상기 전계효과 트랜지스터는 NMOS 트랜지스터인 것이 바람직하다.In the present invention, the field effect transistor is preferably an NMOS transistor.
본 발명에서 상기 LED채널이 구동시작(strat-up)시에 개방(open)되었는지 여부는, 상기 구동전압(VLED)을 다수의 LED채널 모두가 포화상태로 들어갈 수 있는 전압까지 선형적으로 증가하는데 걸리는 시간(tMAX)이 지난 후에도 응답이 없는 LED채널은 개방된 것으로 판정하는 것이 바람직하다.In the present invention, whether the LED channel is opened at the start of driving (strat-up), the driving voltage (V LED ) increases linearly to a voltage at which all the LED channels can enter a saturation state. It is desirable to determine that the LED channel with no response even after the time t MAX elapses to open is open.
본 발명에서 상기 LED 채널이 정상동작(normal operation)시에 개방(open)되었는지 여부는, 상기 구동전압(VLED)을 다수의 LED채널 모두가 포화상태로 들어갈 수 있는 전압까지 선형적으로 증가하는데 걸리는 시간(tMAX)이 지난 후에도, 상기 채널조사부에 의해 소스전압(VS)이 오픈전압(VOPEN)보다 낮은 전압으로 감지되면 개방된 것으로 판정하는 것이 바람직하다.In the present invention, whether or not the LED channel is opened during normal operation increases linearly the driving voltage (V LED ) to a voltage at which all the LED channels can enter a saturation state. after the time taken (t MAX) last, it is preferable that it is determined that the source voltage (V S) by said irradiation unit is an open channel is detected as a voltage lower than an open voltage (V oPEN).
본 발명에서 상기 LED 채널이 구동시작(star-up)시에 단락(short)되었는지 여부는 하기의 수학식을 이용하여 판단하되, In the present invention, whether the LED channel is shorted at the start of driving (star-up) is determined using the following equation,
[규칙 제26조에 의한 보정 20.10.2011]　
Figure WO-DOC-MATHS-26
[Revision 20.10.2011 under Rule 26]
Figure WO-DOC-MATHS-26
구동전압(VLED)을 선형적으로 증가시킬 때 가장 늦게 포화(saturation)되는 채널을 기준으로 역으로 계산하여, 상기 tTOT보다 먼저 포화되는 LED채널은 단락된 것으로 판정하는 것이 바람직하다.When the driving voltage V LED is linearly increased, it is preferable to calculate the LED channel that saturates before the t TOT as short-circuit by calculating the inverse of the latest saturated channel.
(여기서 상기 VMAX.VAR은 정상 상태인 LED채널의 최대 드레인 전압(VD.MAX)과 최소 드레인 전압(VD.MIN)의 차이이고, 상기 tR은 채널 전압이 X·VREF 만큼 상승하는데 소요된 시간이며, 상기 VREF는 기준전압이고, 상기 X는 상수이며, 상기 tTOT은 채널전압이 VMAX.VAR만큼 상승하는데 소요된 시간이다.) Where V MAX.VAR is the difference between the maximum drain voltage (V D.MAX ) and the minimum drain voltage (V D.MIN ) of the LED channel in a steady state, and t R is the channel voltage increased by X · V REF . Is the time taken for the V REF to be a reference voltage, X is a constant, and t TOT is the time taken for the channel voltage to rise by V MAX.VAR .)
본 발명에서 상기 LED 채널이 정상동작(normal operation)시에 단락(short)되었는지 여부는, 캘리브레이션(Calibration) 구간동안 헤드룸 전압 컨트롤(Headroom Voltage Control)을 통해 최적화된 구동전압(VLED.OPT)을 소정값만큼 증가시키고 각 채널의 게이트 전압(VG)값을 아날로그-디지털 변환하여 레지스트리에 저장한 후, 상기 최적화된 구동전압(VLED.OPT)을 상기 소정값만큼 감소시켜 정상동작구간에서 게이트 전압 (VG)값을 수집한 후, 상기 정상동작구간에서 수집된 게이트 전압(VG)값이 상기 캘리브레이션(Calibration)구간에서 저장된 게이트 전압(VG)값보다 작을 경우 단락(short)된 것으로 판정하는 것이 바람직하다. In the present invention, whether or not the LED channel is shorted during a normal operation, the driving voltage (V LED.OPT ) optimized through headroom voltage control during a calibration period . Is increased by a predetermined value and the gate voltage (V G ) of each channel is converted to analog-digital value and stored in the registry, and then the optimized driving voltage (V LED.OPT ) is decreased by the predetermined value in the normal operation section. the gate voltage (V G) after collecting the value, the gate voltage is collected in the normal operation period (V G) if the value is less than the calibration (calibration) gate voltage (V G) are stored in the interval value paragraph (short) It is preferable to determine that it is.
여기서 상기 소정값은, 모든 LED 채널이 포화되었을 때 허용되는 드레인 전압의 차이로서, 각 LED채널별 드레인 전압의 최대값 (VD.MAX)과 드레인 전압의 최소값(VD.MIN)의 차이(VMAX.VAR)인 것이 바람직하다.Wherein a difference between the predetermined value, a difference between the drain voltage to be permitted when all the LED channel is saturated, each LED channel the maximum value of the drain voltage (V D.MAX) and the minimum drain voltage (V D.MIN) of ( V MAX.VAR ).
본 발명에서 상기 캘리브레이션 구간에서의 게이트 전압(VG)값 또는 정상동작구간에서의 게이트 전압(VG)값은, 주기적으로 수집되어 단락(short) 여부를 판정하는 것이 바람직하다.Gate voltage (V G) values in the calibration region a gate voltage (V G) value or a normal operation time period in the present invention, is periodically collected and it is desirable to determine whether short circuit (short).
본 발명에 의한 LED 구동 드라이버에 의하면, LED를 구동시키는 드라이버에 적용되는 종래의 3-PIN 디텍팅 방식에서 벗어나 2-PIN 디텍팅 방식에 의해 LED를 구동·제어하는 효과가 있다. According to the LED drive driver according to the present invention, there is an effect of driving and controlling the LED by the 2-PIN detection method, away from the conventional 3-PIN detection method applied to the driver for driving the LED.
또한, 본 발명에 의하면, LED 구동드라이버에 제공되는 하나의 채널당 소요되는 LED 칩의 핀수를 절감함으로써 LED 구동드라이버의 제조비용을 절감하고, 시스템을 단순화하는 효과가 있다. In addition, according to the present invention, by reducing the number of pins of the LED chip required for each channel provided in the LED driver, it is possible to reduce the manufacturing cost of the LED driver and simplify the system.
다만, 본 발명에 의하면, 2-PIN 디텍팅 방식에 의해 시스템을 단순화하더라도 3-PIN 디텍팅 방식에 뒤지지 않는 효율을 담보하는 LED 구동드라이버를 제공하는 효과가 있다. However, according to the present invention, even if the system is simplified by the 2-PIN detecting method, there is an effect of providing an LED driver that ensures efficiency that is not comparable to the 3-PIN detecting method.
도 1은 종래기술에 따른 LED 구동 드라이버의 예시도.1 is an illustration of an LED drive driver according to the prior art.
도 2는 본 발명의 일실시예에 따른 LED 구동 드라이버의 일예시도.Figure 2 is an exemplary view of an LED drive driver according to an embodiment of the present invention.
도 3은 본 발명의 일실시예에 따른 게이트 전압과 드레인 전압간의 관계를 나타낸 그래프.3 is a graph showing a relationship between a gate voltage and a drain voltage according to an embodiment of the present invention.
도 4 내지 도 5는 본 발명의 일실시예에 따른 LED 구동 드라이버의 일구성도.4 to 5 is a configuration diagram of the LED drive driver according to an embodiment of the present invention.
도 6은 본 발명의 일실시예에 따른 LED 채널의 일구성도. 6 is a configuration diagram of an LED channel according to an embodiment of the present invention.
도 7은 본 발명의 일실시예에 따른 전원조절부의 일구성도. 7 is a configuration diagram of a power control unit according to an embodiment of the present invention.
도 8은 본 발명의 일실시예에 따른 컨트롤 전압과 드레인 전압간의 관계를 나타낸 그래프. 8 is a graph showing a relationship between a control voltage and a drain voltage according to an embodiment of the present invention.
도 9는 본 발명의 일실시예에 따른 LED 채널의 구동시작시 구동전압과 소스전압의 관계를 나타낸 그래프. 9 is a graph illustrating a relationship between a driving voltage and a source voltage at the start of driving an LED channel according to an embodiment of the present invention.
도 10은 본 발명의 일실시예에 따른 개방된 LED 채널이 포함된 LED 채널부의 일예시도. 10 is an exemplary view of an LED channel unit including an open LED channel according to an embodiment of the present invention.
도 11은 본 발명의 일실시예에 따른 LED 채널의 구동시작시 하나의 채널이 개방되었을 경우의 채널별 구동전압과 소스전압의 관계를 나타낸 그래프. 11 is a graph showing a relationship between a driving voltage and a source voltage for each channel when one channel is opened at the start of driving the LED channel according to an embodiment of the present invention.
도 12는 본 발명의 일실시예에 따른 채널조사부의 일예시도. 12 is an exemplary view of a channel irradiation unit according to an embodiment of the present invention.
도 13은 본 발명의 일실시예에 따른 단락된 LED 채널이 포함된 LED 채널부의 일예시도. Figure 13 is an exemplary view of an LED channel unit including a shorted LED channel according to an embodiment of the present invention.
도 14는 본 발명의 일실시예에 따른 LED 채널의 구동시작시 하나의 채널이 단락 되었을 경우의 채널별 구동전압과 소스전압의 관계를 나타낸 그래프.14 is a graph showing a relationship between a driving voltage and a source voltage for each channel when one channel is shorted at the start of driving the LED channel according to an embodiment of the present invention.
도 15는 본 발명의 일실시예에 따른 캘리브레이션 구간동안 획득되는 단락판단 기준전압과 정상구간동안 획득되는 게이트 전압을 나타낸 그래프. 15 is a graph illustrating a short circuit determination reference voltage obtained during a calibration period and a gate voltage obtained during a normal period according to an embodiment of the present invention.
도 16은 본 발명의 일실시예에 따른 LED 채널의 구동시작 구간, 캘리브레이션 구간 및 정상동작 구간에 따른 최적화된 구동전압의 변화를 나타낸 그래프. FIG. 16 is a graph illustrating a change in an optimized driving voltage according to a driving start section, a calibration section, and a normal operation section of an LED channel according to an embodiment of the present invention. FIG.
도 17은 본 발명의 일실시예에 따른 전원조절부가 구비하는 반전부의 앞단을 나타낸 일예시도. Figure 17 is an exemplary view showing the front end of the inverting portion provided with a power control unit according to an embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 이에 앞서, 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이거나 사전적인 의미로 한정해서 해석되어서는 아니되며, 발명자는 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한다. 따라서, 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장 바람직한 일실시예에 불과할 뿐이고 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only one of the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.
도 1은 종래기술에 따른 LED 구동 드라이버의 예시도이다.1 is an exemplary view of a LED driving driver according to the prior art.
종래의 LED 드라이버는, 일반적으로LED 채널의 트랜지스터의 드레인(150), 게이트(160) 및 소스(170)의 정보를 모두 이용하여 드라이버 외부의 LED를 컨트롤하는 3-PIN 디텍팅 방식을 취하고 있었다. Conventional LED drivers generally use a 3-PIN detection scheme that controls the LEDs outside the driver using all of the information of the drain 150, gate 160 and source 170 of the transistor of the LED channel.
예컨대, 모든 LED 채널의 드레인 전압(VD) 중 가장 낮은 드레인 전압(VD)의 트랜지스터가 포화영역에서 동작하기 위한 전압보다 높게 유지시켜 구동전압(VLED)을 조절하였고, 상기 드레인 전압(VD)의 고저에 따라 LED 채널의 개방(open) 또는 단락(short)를 판단하는 방식을 취하고 있었다. For example, all the LED of the drain voltage (V D) of the channels of the low drain voltage (V D) transistor keeps higher than the voltage to operate in a saturation region was adjusted to the driving voltage (V LED), the drain voltage (V According to the height of D ), the LED channel was opened or shorted.
즉, 종래기술에 의할 때, LED 채널의 트랜지스터의 드레인(D), 게이트(G), 소스(S)의 정보가 모두 필요하였고, 따라서, 드라이버에 할당되는 칩의 핀수가 3개가 필요하였고, 이와 같이 드라이버를 구성하면, 시스템이 복잡해지고, 하나의 칩으로 형성할 수 있는 드라이버의 개수가 적어지므로, 제조비용이 현저히 증가하는 문제점이 있었다. That is, according to the prior art, all the information of the drain (D), the gate (G), the source (S) of the transistor of the LED channel was needed, and therefore, the number of pins of the chip allocated to the driver was required, The configuration of the driver as described above has a problem that the system becomes complicated and the number of drivers that can be formed by one chip decreases, thereby significantly increasing the manufacturing cost.
도 2는 본 발명의 일실시예에 따른 LED 구동 드라이버의 일예시도이다.2 is an exemplary view of a LED driving driver according to an embodiment of the present invention.
따라서, 본 발명에서는 드라이버에 할당되는 칩의 핀수를 줄이고자 하는데 주안점이 있으므로, 게이트(G) 및 소스(S)의 정보만을 이용하여, 헤드룸 전압 컨트롤을 수행하고, LED 채널의 개방(open) 또는 단락(short)여부를 판단 가능하도록 구성되었다. Therefore, in the present invention, since the main point is to reduce the number of pins of the chip allocated to the driver, headroom voltage control is performed using only the information of the gate G and the source S, and the LED channel is opened. Or it is configured to be able to determine whether short (short).
즉, 본 발명에 의하면, 드레인 전압(VD)을 직접 획득하지 아니하므로, 소스단(170)의 전압(VS)를 OP-AMP의 이상단락(Virtual short) 성질을 이용하여 기준전압(VREF)로 고정한다. 그리고, 게이트 전압(VG)의 변화를 이용하여 드레인 전압(VD)의 변화를 유추해서 판단하는 구조를 취하게 되었다. That is, according to the present invention, since the drain voltage V D is not directly obtained, the voltage V S of the source terminal 170 may be set to the reference voltage V using the virtual short property of the OP-AMP. REF ). In addition, a structure in which the change in the drain voltage V D is inferred and judged using the change in the gate voltage V G is obtained.
도 3은 본 발명의 일실시예에 따른 게이트 전압과 드레인 전압간의 관계를 나타낸 그래프이다.3 is a graph illustrating a relationship between a gate voltage and a drain voltage according to an embodiment of the present invention.
본 발명이 취하는 2-Pin 디텍팅 방식의 LED 구동 드라이버의 경우에는 게이트 전압(VG)의 변화를 보고, 이를 이용하여 드레인 전압(VD)의 상태를 유추해서 판단하게 된다. In the case of the 2-pin detecting LED driving driver according to the present invention, the gate voltage V G is changed and the state of the drain voltage V D is inferred using the change.
예를 들면, LED의 산포 또는 트랜지스터의 산포는 드레인 전압(VD)의 변화로 나타나게 되는데, 상술한 바대로 채널에 흐르는 전류의 크기가 일정하기 때문에, 게이트 전압(VG)의 변화 등을 이용하여 드레인 전압(VD)을 유추할 수 있을 것이다. For example, the distribution of the LED or the distribution of the transistor is represented by a change in the drain voltage (V D ). As described above, since the magnitude of the current flowing through the channel is constant, a change in the gate voltage (V G ) is used. The drain voltage V D may be inferred.
도 4 내지 도 5는 본 발명의 일실시예에 따른 LED 구동 드라이버의 일구성도이다.4 to 5 is a configuration diagram of the LED driving driver according to an embodiment of the present invention.
본 발명의 LED 구동드라이버는, 구동전압(VLED)이 입력되며, 적어도 하나 이상의 다이오드와, 전계효과 트랜지스터 및 채널저항이 직렬로 연결되는 LED 채널을 다수 구비하는 LED 채널부(100), 상기 전계효과 트랜지스터에 연결되어 각 LED채널에 일정한 전류가 흐르도록 제어하고, 상기 LED 채널의 개방(open)여부 또는 단락(short)여부를 판정하는 채널조사부(200) 및 상기 전계효과 트랜지스터의 게이트단과 연결되며, 다수의 게이트 전압(VG) 중 최대 게이트 전압(VG_MAX) 및 컨트롤 전압(VCTL)을 비교하여 상기 구동전압(VLED)을 헤드룸 전압(Headroom Voltage; VX)이 최소화되는 크기로 조절하여 상기 LED 채널부에 공급하는 전원조절부(300)를 포함하여 구성될 수 있다. LED driving driver of the present invention, the driving voltage (V LED ) is input, LED channel unit 100 having a plurality of LED channels connected to the at least one diode, the field effect transistor and the channel resistance in series, the electric field It is connected to the effect transistor to control the constant current flow through each LED channel, and is connected to the channel irradiation unit 200 and the gate terminal of the field effect transistor to determine whether the LED channel open or short (short). In addition, the driving voltage (V LED ) may be compared with the maximum gate voltage (V G_MAX ) and the control voltage (V CTL ) among the plurality of gate voltages (V G ) to minimize the headroom voltage (V X ). It may be configured to include a power control unit 300 to adjust the supply to the LED channel unit.
또한 본 발명은 2-PIN 디텍팅 방식을 채용하고 있는바, 상기 채널조사부(200)는 상기 전계효과 트랜지스터의 드레인(drain)단을 제외한 게이트(gate)단과 소스(source)단에 연결되어, LED 채널에 일정한 전류가 흐르도록 제어하고, 헤드룸 전압 컨트롤 및 각 LED 채널의 개방(open) 또는 단락(short)여부를 판별하게 된다. In addition, the present invention employs a 2-PIN detecting method, the channel irradiator 200 is connected to the gate terminal and the source terminal excluding the drain terminal of the field effect transistor, LED A constant current flows through the channel, and headroom voltage control and whether each LED channel is open or short is determined.
즉, 상기 채널조사부는, (+)단이 기준전압(VREF) 입력단(210)과 연결되고, (-)단이 트랜지스터의 소스단과 연결되며, 그 출력단이 트랜지스터의 게이트단과 연결되는 제1 OP-AMP(220) 및 상기 전계효과 트랜지스터의 소스전압(VS)과 오픈전압(VOPEN)을 비교하여 출력하는 단락판단부(230)를 구비할 수 있다. 상기 단락판단부(230)는 제 2OP-AMP로 형성되어 상기 소스전압(VS)과 오픈전압(VOPEN)를 입력받아 그 비교치를 출력할 수 있을 것이다. That is, the channel irradiator includes a first OP having a positive terminal connected to a reference voltage V REF input terminal 210, a negative terminal connected to a source terminal of a transistor, and an output terminal thereof connected to a gate terminal of a transistor. An AMP 220 and a short circuit determination unit 230 for comparing and outputting the source voltage V S and the open voltage V OPEN of the field effect transistor may be provided. The short circuit determination unit 230 may be formed of a second OP-AMP to receive the source voltage V S and the open voltage V OPEN , and output a comparison value thereof.
또한, 발명의 필요에 따라, 상기 제 2OP-AMP의 (+)단에 소스전압(VS), (-)단에 오픈전압(VOPEN)을 입력하거나, 또는 (-)단에 소스전압(VS), (+)단에 오픈전압(VOPEN)을 입력하여 단락여부를 판정할 수 있을 것이다. In addition, according to the necessity of the invention, the source voltage V S at the (+) terminal of the second OP-AMP, the open voltage V OPEN at the (-) terminal, or the source voltage ( It is possible to determine whether a short circuit by inputting the open voltage (V OPEN ) to the V S ), (+) terminal.
후술하겠지만, 상기 기준전압(VREF)은 제 1OP-AMP의 이상단락 성질을 의해 소스전압(VS)를 고정하여 각 채널에 흐르는 전류의 크기를 결정하는 역할을 수행한다. As will be described later, the reference voltage V REF serves to determine the magnitude of the current flowing through each channel by fixing the source voltage V S by the abnormal shorting property of the first OP-AMP.
상기 채널조사부(200)는, 상기 각각의 LED 채널의 게이트 전압(VG)값을 아날로그-디지털 변환하여 소정의 레지스트리에 저장하는 AD 컨버터(Analog-Digital Converter)를 더 구비할 수 있다.The channel irradiator 200 may further include an analog-to-digital converter (AD converter) for analog-to-digital converting a gate voltage (V G ) value of each LED channel and storing it in a predetermined registry.
상기 전원조절부(300)는, 상기 다수의 LED 채널의 게이트 전압(VG)들을 입력받아 최대 게이트전압(VG_MAX)을 걸러내는 게이트 전압 입력단, 컨트롤 전압(VCTL)이 입력되는 컨트롤 전압단(340), 상기 최대 게이트전압(VG_MAX)과 상기 컨트롤 전압(VCTL)을 비교하여 그 전압의 차이를 전류로 생성하여 출력하는 GM-AMP(350), 헤드룸 전압(VX)(360)을 이용하여 상기 GM-AMP의 출력을 반전시키는 반전부(380) 및 상기 반전부의 출력을 이용하여 피드백 루프를 제어하여 최적화된 구동전압(VLED.OPT)를 생성하는 DC-DC 컨버터(370)를 포함하여 구성될 수 있다. The power control unit 300 receives a gate voltage V G of the plurality of LED channels and filters a maximum gate voltage V G_MAX , and a control voltage terminal to which a control voltage V CTL is input. GM-AMP 350 and headroom voltage V X 360 that compare the maximum gate voltage V G_MAX and the control voltage V CTL to generate and output the current difference; Inverter 380 for inverting the output of the GM-AMP and DC-DC converter 370 for controlling the feedback loop using the output of the inverter to generate an optimized driving voltage (V LED.OPT ) It may be configured to include).
이 때, 상기 최적화된 구동전압(VLED.OPT)은, 모든 LED 채널이 포화상태에서 동작하면서 전력효율을 최대화하기 위해 LED채널의 헤드룸 전압이 최소화되는 크기의 전압이라고 할 수 있다. In this case, the optimized driving voltage (V LED.OPT ) may be a voltage of which the headroom voltage of the LED channel is minimized to maximize power efficiency while all LED channels operate in a saturated state.
또한, 상기 게이트 전압(VG)들과 컨트롤 전압(VCTL)은 다이오드(310,320)에 의해 전압강하되어 GM-AMP(350)에 입력되는 것이 바람직하며, 본 발명에서 상기 전계효과 트랜지스터는 NMOS 트랜지스터인 것이 바람직하다. In addition, the gate voltages V G and the control voltage V CTL are dropped by the diodes 310 and 320 and input to the GM-AMP 350. In the present invention, the field effect transistor is an NMOS transistor. Is preferably.
도 6은 본 발명의 일실시예에 따른 LED 채널의 일구성도이다. 6 is a configuration diagram of an LED channel according to an embodiment of the present invention.
본 발명의 LED 채널은 구동전압(VLED)이 입력되는 구동전압 입력단(110), 적어도 하나 이상의 LED(발광 다이오드)(120)와, 전계효과 트랜지스터 및 채널저항(140)이 순차적으로 직렬로 연결되는 구조를 취하고 있다. 도 6을 참조하면, (+)단에 상기 기준전압(VREF)이 입력되고, (-)단이 상기 소스단(170)과 연결되며, 그 출력단이 상기 게이트단(160)과 연결되는 제1 OP-AMP(220)을 함께 도시하고 있다. The LED channel of the present invention is connected to the driving voltage input terminal 110, the at least one LED (light emitting diode) 120, and the field effect transistor and the channel resistance 140 are sequentially connected to the driving voltage (V LED ) in sequence. It takes a structure to become. Referring to FIG. 6, the reference voltage V REF is input to a (+) terminal, a (−) terminal is connected to the source terminal 170, and an output terminal thereof is connected to the gate terminal 160. 1 shows OP-AMP 220 together.
이와 같은 구조의 LED 채널에 있어서는, 다수의 다이오드(120)를 관통하는 전류(IF), 즉 LED의 포워드 전류(Forward-Current)는 채널저항(R)(140)을 관통하는 전류(IR )와 같게 된다.In this LED channels of the structure, the plurality of current (I F), that is forward of the LED current (Forward-Current) passing through the diode 120, the current passing through the channel resistance (R) (140) (I R Becomes equal to).
채널저항(R)(140)을 관통하는 전류(IR )는 a노드의 전압(Va), 즉 소스단 전압(VS)과 채널저항(R)에 의해 정해지게 되는데, 상기 a노드의 전압(Va)은 OP-AMP의 이상단락(virtual short) 특성에 의해 기준전압(VREF) 과 같아진다.The current I R passing through the channel resistor R 140 is determined by the voltage V a of the node a , that is, the source terminal voltage V S and the channel resistance R. The voltage V a is equal to the reference voltage V REF due to the virtual short characteristic of the OP-AMP.
즉, 채널저항(R)(140)을 관통하는 전류(IR )는 하기의 수학식 1과 같이 표현될 수 있다. That is, the current I R penetrating through the channel resistance R 140 may be expressed by Equation 1 below.
수학식 1
Figure PCTKR2011005133-appb-M000001
 Equation 1
Figure PCTKR2011005133-appb-M000001
따라서, 채널저항(R)(140)을 관통하는 전류(IR )와 동일한 LED의 포워드 전류(IF)도 하기의 수학식 2와 같이 표현될 수 있다. Therefore, the forward current I F of the same LED as the current I R penetrating through the channel resistance R 140 may also be expressed by Equation 2 below.
수학식 2
Figure PCTKR2011005133-appb-M000002
 Equation 2
Figure PCTKR2011005133-appb-M000002
따라서, LED의 포워드 전류(IF)는 기준전압(VREF) 과 비례하기 때문에, 기준전압(VREF)을 조정하여 LED의 휘도(Brightness)를 조정할 수 있을 것이다. Thus, the forward current (I F) of the LED will be able to because it is proportional to the reference voltage (V REF), by adjusting the reference voltage (V REF) to adjust the luminance (Brightness) of the LED.
이어서, 헤드룸 전압 컨트롤(Headroom Voltage Control)에 대해 설명하기로 한다. a 노드(소스단)의 전압(Va)은 제1 OP-AMP의 이상단락 특성에 의해 기준전압(VREF)과 동일하므로 하기의 수학식 3과 같이 나타낼 수 있다. Next, headroom voltage control will be described. Since the voltage V a of the node a (source terminal) is the same as the reference voltage V REF due to the abnormal shorting characteristic of the first OP-AMP, the voltage V a may be represented by Equation 3 below.
수학식 3
Figure PCTKR2011005133-appb-M000003
 Equation 3
Figure PCTKR2011005133-appb-M000003
b노드(드레인단)의 전압(Vb)는 구동전압(VLED)에서 n개(다이오드의 개수)의 포워드 전압(Forword Vias; VF)을 뺀 것과 동일하므로 하기의 수학식 4와 같이 나타낼 수 있다. The voltage V b of the node (drain end) is equal to the driving voltage V LED minus the number of forward voltages (V F ) of n (the number of diodes), and is represented by Equation 4 below. Can be.
수학식 4
Figure PCTKR2011005133-appb-M000004
 Equation 4
Figure PCTKR2011005133-appb-M000004
이 때, NMOS 트랜지스터가 포화영역에서 동작하기 위한 조건은 하기의 수학식 5와 같다. 즉, 드레인 전압(Vb)과 소스전압(Va)의 차이가 포화(saturation)된 드레인 전압(VDSAT) 이상이어야 한다. At this time, the condition for the NMOS transistor to operate in the saturation region is shown in Equation 5 below. That is, to be less than the drain voltage (V b) and the source voltage (V a), the saturation (saturation) the drain voltage (V DSAT) difference.
수학식 5
Figure PCTKR2011005133-appb-M000005
 Equation 5
Figure PCTKR2011005133-appb-M000005
여기서, 상기 수학식 5에 상기 수학식 3과 수학식 4를 대입하면, 하기의 수학식 6과 같이 나타낼 수 있다.In this case, when Equation 3 and Equation 4 are substituted into Equation 5, Equation 6 may be represented.
수학식 6
Figure PCTKR2011005133-appb-M000006
 Equation 6
Figure PCTKR2011005133-appb-M000006
그리고, 상기 수학식 6을 정리하면, 하기의 수학식 7과 같이 나타낼 수 있다. In addition, the equation (6) can be summarized as shown in equation (7).
수학식 7
Figure PCTKR2011005133-appb-M000007
 Equation 7
Figure PCTKR2011005133-appb-M000007
즉, 수학식 7을 참조하면, 구동전압(VLED)이 증가하여도 NMOS 트랜지스터가 포화영역에서 동작하고 있다면, 포워드 전류(IF)는 기준전압(VREF)와 채널저항(R)에 의해 결정되기 때문에 LED의 휘도는 변하지 않는다. 다만, NMOS 트랜지스터의 VDS가 커지게 되는데, 이러한 VDS를 헤드룸 전압(Headroom Voltage)이라고 하며, 하기의 수학식 8과 같이 나타낼 수 있다. That is, referring to Equation 7, if the NMOS transistor is operating in the saturation region even though the driving voltage V LED increases, the forward current I F is determined by the reference voltage V REF and the channel resistance R. As determined, the brightness of the LED does not change. However, the V DS of the NMOS transistor is increased, and this V DS is called a headroom voltage, and can be expressed as Equation 8 below.
수학식 8
Figure PCTKR2011005133-appb-M000008
 Equation 8
Figure PCTKR2011005133-appb-M000008
즉, 본 발명의 LED 구동드라이버는 모든 LED 채널의 트랜지스터가 포화영역에서 동작할 때, 헤드룸 전압(Headroom Voltage)이 가능한 한 작아지도록 구동전압(VLED)을 조정하게 되는데, 이를 헤드룸 전압 컨트롤(Headroom Voltage Control)이라 한다. 이에 대해서는 아래에서 후술하기로 한다. That is, the LED driving driver of the present invention adjusts the driving voltage (V LED ) so that the headroom voltage is as small as possible when the transistors of all the LED channels operate in the saturation region, and the headroom voltage control It is called (Headroom Voltage Control). This will be described later.
도 7은 본 발명의 일실시예에 따른 전원조절부의 일구성도이다. 7 is a configuration diagram of a power control unit according to an embodiment of the present invention.
본 발명에서 전원조절부는, 다수의 LED 채널의 게이트 전압(VG)들을 입력받아 최대 게이트전압(VG_MAX)을 걸러내는 게이트 전압 입력단, 컨트롤 전압(VCTL)이 입력되는 컨트롤 전압입력단(340), 상기 최대 게이트전압(VG_MAX)과 상기 컨트롤 전압(VCTL)을 비교하여 그 전압의 차이를 전류로 생성하여 출력하는 GM-AMP(350), 상기 소스단과 드레인단 사이의 전압(VX)을 이용하여 상기 GM-AMP의 출력을 반전시키는 반전부(360) 및 상기 반전부의 출력을 이용하여 피드백 루프를 제어하여 최적화된 구동전압(VLED.OPT)를 생성하는 DC-DC 컨버터 (370)를 포함하여 구성될 수 있다. In the present invention, the power supply control unit, the gate voltage input terminal for filtering the maximum gate voltage (V G_MAX ) by receiving the gate voltage (V G ) of the plurality of LED channels, the control voltage input terminal 340 is input the control voltage (V CTL ) GM-AMP 350 that compares the maximum gate voltage V G_MAX with the control voltage V CTL and generates and outputs a difference between the voltages as a current and a voltage V X between the source and drain terminals. An inverter 360 for inverting the output of the GM-AMP and a DC-DC converter 370 for generating an optimized driving voltage V LED.OPT by controlling a feedback loop using the output of the inverter. It may be configured to include.
또한, 각각의 LED 채널로부터 입력되는 게이트 전압(VG)들 중 최대 게이트전압(VG_MAX)을 걸러내기 위해 게이트 전압 입력단은 다이오드(310)를 포함하는 것이 바람직하다. 즉 게이트 전압 입력단의 다이오드(310)에 의해 최대 게이트전압(VG_MAX)은 소정값(예: 0.7V)이 떨어지게 되는데, 이에 비례하여 컨트롤 전압 입력단도 다이오드(320)를 구비하여 컨트롤 전압(VCTL)을 소정정도 전압강하시켜 GM-AMP에 입력시키는게 바람직하다. In addition, the gate voltage input terminal preferably includes a diode 310 to filter out the maximum gate voltage V G_MAX among the gate voltages V G input from each LED channel. That is, the maximum gate voltage V G_MAX is dropped by a predetermined value (for example, 0.7 V) by the diode 310 of the gate voltage input terminal, and accordingly, the control voltage input terminal diode 320 is provided to control the voltage V CTL. ) Is inputted to GM-AMP by a voltage drop to a predetermined degree.
헤드룸 전압 컨트롤과 관련하여, 종래의 3-Pin 디텍팅 방식의 경우에서는, 트랜지스터의 드레인 전압(VD)을 직접 모니터링하여 헤드룸 전압을 최소화할 수 있다. 다만, 본 발명에서는 2-PIN 디텍팅 방식을 취하고 있으므로, 게이트 전압(VG)으로 트랜지스터의 드레인 전압(VD)의 상태를 유추하여야 한다. With respect to headroom voltage control, in the case of the conventional 3-pin detecting method, the headroom voltage can be minimized by directly monitoring the drain voltage V D of the transistor. However, in the present invention, since the 2-PIN detecting method is used, the state of the drain voltage V D of the transistor must be inferred from the gate voltage V G.
즉, 먼저 트랜지스터가 포화영역에서 동작할 때의 게이트 전압(VG)의 레벨을 미리 설정하게 되는데, 이와 같이 미리 설정된 레벨 값인 컨트롤 전압(VCTL)을 각 LED채널의 게이트 전압(VG) 중, 가장 높은 게이트 전압(VG)인 최대 게이트전압(VG_MAX)과 비교하여 Dc-DC컨버터(370)의 피드백 루프를 제어하게 된다. That is, first, the level of the gate voltage (V G ) when the transistor operates in a saturation region is set in advance. The control voltage (V CTL ), which is a preset level value, is selected among the gate voltages (V G ) of each LED channel. The feedback loop of the Dc-DC converter 370 is controlled in comparison with the maximum gate voltage V G_MAX , which is the highest gate voltage V G.
이 때, 최대 게이트전압(VG_MAX)이 컨트롤 전압(VCTL)보다 작으면, 모든 전계효과 트랜지스터는 포화영역에서 동작하고 있다고 판단하게 된다. At this time, if the maximum gate voltage V G_MAX is smaller than the control voltage V CTL , it is determined that all the field effect transistors are operating in the saturation region.
종합하면, 상기 최대 게이트전압(VG_MAX)과 상기 컨트롤 전압(VCTL)은 GM-AMP(350)에 입력되어 그 차이가 전류로 생성되어 출력되게 되고, 상기 Gm-AMP의 출력은 소정의 반전 전압(VZ)에 의해 반전되어 출력되게 된다. 이와 같은 반전부(380)의 출력으로 DC-DC 컨버터(370)의 피드백 루프를 제어하여 최적화된 구동전압(VLED_OPT)를 생성한 후, 각 LED 채널의 구동전압 입력단으로 재공급하게 된다. In sum, the maximum gate voltage V G_MAX and the control voltage V CTL are input to the GM-AMP 350 so that a difference is generated and outputted as a current, and the output of the Gm-AMP is a predetermined inversion. The output is inverted by the voltage V Z. The output of the inverting unit 380 controls the feedback loop of the DC-DC converter 370 to generate the optimized driving voltage V LED_OPT and then resupply the driving voltage input terminal of each LED channel.
상기 반전부(380)는, (+) 단자에 Gm-AMP의 출력이 입력되며, (-) 단자가 그 출력단과 연결되는 제3 OP-AMP와, (+) 단자에 소정의 반전 전압(VZ)이 입력되는 제4 OP-AMP를 포함하여 구성될 수 있고, 저항을 적절히 배치하여 Gm-AMP의 출력이 반전되어 출력되도록 형성할 수 있을 것이다. The inverting unit 380 has a third OP-AMP having an output of Gm-AMP input to a (+) terminal, a (-) terminal connected to an output terminal thereof, and a predetermined inversion voltage (V) at a (+) terminal. Z ) may be configured to include a fourth OP-AMP input, and may be formed such that the output of the Gm-AMP is inverted and output by appropriately disposing a resistor.
상기 DC-DC 컨버터(370)는 상기 반전부(380)의 출력으로 DC-DC 컨버터(370)에 피드백(feed-back)되는 전압을 조절함으로써, DC-DC 컨버터가 생성하는 구동전압(VLED)를 조절하게 된다. 즉, 상기 DC-DC 컨버터(370)에 피드백되는 전압이 작아지면, DC-DC 컨버터(370)는 더 높은 구동전압(VLED)을 생성하게 되고, 이와 반대로 피드백되는 전압이 커지면, 출력되는 구동전압(VLED)을 낮추게 된다. The DC-DC converter 370 adjusts a voltage fed back to the DC-DC converter 370 by the output of the inverting unit 380, thereby generating a driving voltage (V LED) generated by the DC-DC converter. Will be adjusted. That is, when the voltage fed back to the DC-DC converter 370 decreases, the DC-DC converter 370 generates a higher driving voltage V LED . On the contrary, when the voltage fed back increases, the driven output is increased. It will lower the voltage (V LED ).
도 8은 본 발명의 일실시예에 따른 컨트롤 전압과 드레인 전압간의 관계를 나타낸 그래프이다.8 is a graph illustrating a relationship between a control voltage and a drain voltage according to an embodiment of the present invention.
즉, 2-PIN 디텍팅 방식을 취하는 본 발명에 있어서, 게이트 전압으로 드레인 전압을 유추하여 판단하는 구조를 취하고 있는 바, NMOS 트랜지스터가 포화영역에서 동작하기 위한 최소 드레인 전압(VD.MIN)을 컨트롤 전압(VCTL)으로 미리 설정한 후, 최대 게이트전압(VG_MAX)과 비교하여 Dc-DC컨버터의 피드백 루프를 제어하는 것이 바람직할 것이다. In other words, in the present invention using the 2-PIN detecting method, a structure in which the drain voltage is inferred and determined by the gate voltage is used to determine the minimum drain voltage (V D.MIN ) for the NMOS transistor to operate in the saturation region. After setting the control voltage V CTL in advance, it may be desirable to control the feedback loop of the Dc-DC converter in comparison with the maximum gate voltage V G_MAX .
도 9는 본 발명의 일실시예에 따른 LED 채널의 구동시작시 구동전압과 소스전압의 관계를 나타낸 그래프이다. 9 is a graph showing a relationship between a driving voltage and a source voltage at the start of driving an LED channel according to an embodiment of the present invention.
LED 채널의 구동시작(start-up)시에 낮은 구동전압(VLED)으로 채널을 구동하게 되면, 헤드룸 전압이 모자르다라는 정보가 들어오게 된다. 따라서, 구동전압(VLED)을 선형적으로 증가시켜서 구동전압 입력단에 공급하게 된다. When the channel is driven with a low driving voltage (V LED ) at the start-up of the LED channel, information is received that the headroom voltage is insufficient. Therefore, the driving voltage V LED is linearly increased to be supplied to the driving voltage input terminal.
즉, 구동전압(VLED)이 낮을 경우에는 전계효과 트랜지스터가 선형영역에서 동작하기 때문에 이 때의 트랜지스터는 저항성분을 갖으며, 구동전압(VLED)을 선형적으로 증가시킬 때, 트랜지스터의 소스전압(VS) 또한 선형적으로 증가하게 된다. 이 때 채널저항(R)과 소스전압(VS) 에 의해 결정되는 채널의 전류도 선형적으로 증가하게 된다. That is, since the field effect transistor operates in the linear region when the driving voltage V LED is low, the transistor at this time has a resistance component, and when the driving voltage V LED is linearly increased, the source of the transistor is Voltage V S also increases linearly. At this time, the current of the channel determined by the channel resistance (R) and the source voltage (V S ) also increases linearly.
따라서, 구동전압(VLED)이 충분히 증가하여 전계효과 트랜지스터가 포화상태가 되면 소스전압(VS)이 미리 채널에 흐르게 할 전류의 양에 따라 고정된 기준전압(VREF)과 동일해 진다. 따라서, 소스전압(VS)이 기준전압(VREF)과 같아졌을 때에는 LED채널이 포화상태에 들어갔다고 판단할 수 있게 된다. Therefore, when the driving voltage V LED is sufficiently increased and the field effect transistor is saturated, the source voltage V S becomes equal to the fixed reference voltage V REF in accordance with the amount of current to flow in the channel in advance. Accordingly, it is possible when the source voltage (V S) is turned the same as the reference voltage (V REF) LED channel can be determined deuleogatdago in saturation.
도 9에서 볼 수 있듯이, 구동전압(VLED)이 n개의 LED가 순방향 턴온(Turn-ON)될 수 있는 nVF만큼 증가하기 전, 즉 'VLED<nVF'의 관계를 만족할 때에는, 오프(OFF)된 LED의 저항값이 매우 크게 나타나므로 트랜지스터의 소스전압(VS)이 '0'이 된다. As can be seen in Figure 9, when the driving voltage (V LED ) is increased by nV F where n LEDs can be turned forward (Turn-ON), that is, when the relationship of 'V LED <nV F ' is satisfied, it is off. Since the resistance value of the (OFF) LED is very large, the source voltage (V S ) of the transistor becomes '0'.
그러다가, 구동전압(VLED)이 nVF보다 커지면, 즉 'VF<VLED< nVF+VDsat+VREF'의 관계를 만족할 때에는, 트랜지스터가 포화상태로 들어가기 전까지는 채널저항(R)과 선형동작을 하는 트랜지스터의 관계 때문에 소스전압(VS)은 선형적으로 증가한다. Then, when the driving voltage (V LED ) is greater than nV F , that is, when the relationship of 'V F <V LED <nV F + V Dsat + V REF ' is satisfied, the channel resistance (R) until the transistor enters saturation state. The source voltage V S increases linearly due to the relationship between the transistor and linear transistor.
이후, 구동전압(VLED)이 더욱 증가하여 소스전압(VS)이 기준전압(VREF)으로 고정되고 트랜지스터가 포화영역에서 동작할 수 있는 포화된 드레인전압(VDsat)을 확보하게 되면, 즉 'VF<VLED< nVF+VDsat+VREF'의 관계를 만족하게 되면, 채널은 포화상태가 되어 구동전압(VLED)이 계속 증가하여도 소스전압(VS)은 기준전압(VREF)으로 고정된다. Thereafter, when the driving voltage V LED is further increased so that the source voltage V S is fixed to the reference voltage V REF and the transistor has a saturated drain voltage V Dsat capable of operating in the saturation region, That is, when the relationship between 'V F <V LED <nV F + V Dsat + V REF ' is satisfied, the channel becomes saturated and the source voltage (V S ) remains the reference voltage even if the driving voltage (V LED ) continues to increase. Is fixed to (V REF ).
즉, 상기 기준전압(VREF)은 모든 채널을 포화시키기 위해 구동전압(VLED)을 최적화 시키기 위한 한계까지 고정되어 컨스턴트 커런트 소스(constant current source)로 활용된다고 할 수 있다. That is, the reference voltage V REF is fixed to a limit for optimizing the driving voltage V LED to saturate all channels, and thus may be used as a constant current source.
도 10은 본 발명의 일실시예에 따른 개방된 LED 채널이 포함된 LED 채널부의 일예시도이다. 10 is an exemplary view of an LED channel unit including an open LED channel according to an embodiment of the present invention.
도 11은 본 발명의 일실시예에 따른 LED 채널의 구동시작시 하나의 채널이 개방되었을 경우의 채널별 구동전압과 소스전압의 관계를 나타낸 그래프이다.11 is a graph illustrating a relationship between a driving voltage and a source voltage for each channel when one channel is opened at the start of driving the LED channel according to an embodiment of the present invention.
본 발명의 LED 구동드라이버는, 그 구동시작(start-up)시 모든 LED 채널이 포화영역으로 들어갈 수 있는 충분한 전압까지 구동전압 (VLED)을 선형적으로 증가시키게 된다. 즉, 모든 LED 채널이 포화영역으로 들어갈 수 있는 충분한 전압까지 구동전압 (VLED)을 선형적으로 증가시키는 시간을 tMAX라 할 때, tMAX가 지난 후에도 응답(예; 소스전압(VS) 의 증가여부)이 없는 채널은 개방(open)되었다고 판단하게 된다. The LED drive driver of the present invention linearly increases the drive voltage (V LED ) to a sufficient voltage for all LED channels to enter the saturation region at the start-up of the drive. That is, when the time for increasing the driving voltage (V LED) linearly to a sufficient voltage in all the LED channel is getting into the saturation region t MAX la, after the t MAX last response (eg, a source voltage (V S) The channel without the increase of is determined to be open.
도 11을 참조하면, 구동전압 (VLED)을 동안 tMAX증가시키는 동안 1채널, 3채널, 4채널의 소스전압이 기준전압까지 증가한 반면, 2채널의 소스전압(VS)은 변함이 없으므로 개방(open)된 것으로 판단하게 된다. Referring to FIG. 11, while increasing the driving voltage (V LED ) during t MAX , the source voltages of one channel, three channels, and four channels increase to the reference voltage, while the source voltages of two channels (V S ) do not change. It is determined that it is open.
도 12는 본 발명의 일실시예에 따른 채널조사부의 일예시도이다. 12 is an exemplary view of a channel irradiator according to an embodiment of the present invention.
본 발명에서 채널조사부는, (+)단에 상기 기준전압(VREF)이 입력되고, (-)단이 상기 소스단(170)과 연결되며, 그 출력단이 상기 게이트단과 연결되는 제1 OP-AMP(220) 및 상기 전계효과 트랜지스터의 소스전압(VS)과 오픈전압(VOPEN)을 비교하여 출력하는 단락판단부(230)를 포함하여 형성할 수 있다. In the present invention, the channel irradiator includes a first OP− connected to the reference voltage V REF at a positive terminal, a negative terminal connected to the source terminal 170, and an output terminal connected to the gate terminal. The AMP 220 and the short-circuit determination unit 230 comparing the source voltage V S and the open voltage V OPEN of the field effect transistor may be output.
상기 채널조사부는, i) 트랜지스터의 소스전압(VS)이 기준전압(VREF)에 고정되게 함으로서 채널에 일정한 전류가 흐르도록 제어하며, ii) 상기 단락판단부(230)를 통한 LED 채널의 개방여부를 조사하고, iii) AD 컨버터를 통한 정상동작 중 단락여부 조사 및 iv) 트랜지스터의 소스전압(VS)을 이용하여 구동시작시 단락여부를 조사하는 기능을 수행한다. The channel irradiator controls i) a constant current to flow through the channel by fixing the source voltage V S of the transistor to the reference voltage V REF , and ii) controlling the LED channel through the short circuit determination unit 230. investigate the opening and, iii) by using a short-circuit whether research and iv) a source voltage (V S) of the transistor during normal operation via the AD converter and performs a function to check whether the short circuit at the start of driving.
본 발명의 일실시예로, 상기 단락판단부(230)는 (+)단에 상기 전계효과 트랜지스터(FET)의 소스전압(VS)이 입력되며, (-)단에 오픈전압(VOPEN)이 입력되는 제 2OP-AMP로 구성될 수 있다. 또한, 이와 반대로 (-)단에 상기 전계효과 트랜지스터(FET)의 소스전압(VS)이 입력되며, (+)단에 오픈전압(VOPEN)이 입력되도록 형성할 수도 있을 것이다. In one embodiment of the present invention, the short circuit determination unit 230 is a source voltage (V S ) of the field effect transistor (FET) is input to the (+) terminal, open voltage (V OPEN ) to the (-) terminal This may be configured as the input 2OP-AMP. On the contrary, the source voltage V S of the field effect transistor FET is input to the negative terminal and the open voltage V OPEN is input to the positive terminal.
이와 같은 채널조사부를 이용하여, 정상동작시의 LED 채널의 개방(open) 여부를 감지할 수 있는데, 정상동작시 LED 채널이 개방(open)되면, 소스전압(VS)은 게이트 전압(VG)에 관계없이 그라운드 레벨로 내려가므로, 상기 제2 OP-AMP를 이용하여 소스전압(VS)을 감지하면, 개방(open)여부를 판단할 수 있을 것이다. By using the channel irradiator, it is possible to detect whether the LED channel is open in the normal operation. When the LED channel is opened in the normal operation, the source voltage V S is the gate voltage V G. ) so down to ground level, regardless of, upon detecting a source voltage (V S) by using the first OP-AMP 2, it will be able to determine whether the open (open).
도 13은 본 발명의 일실시예에 따른 단락된 LED 채널이 포함된 LED 채널부의 일예시도이고, 도 14는 본 발명의 일실시예에 따른 LED 채널의 구동시작시 하나의 채널이 단락되었을 경우의 채널별 구동전압과 소스전압의 관계를 나타낸 그래프이다.FIG. 13 is an exemplary view of an LED channel unit including a shorted LED channel according to an embodiment of the present invention, and FIG. 14 is a case where one channel is shorted at the start of driving an LED channel according to an embodiment of the present invention. Is a graph showing the relationship between driving voltage and source voltage for each channel.
도 13에서 볼 수 있듯이, 하나의 LED 채널이 단락되면, 단락된 채널의 드레인 전압(VD2)는 타채널의 드레인 전압(VD1, VD3, VD4)보다 소정값(예; 2.5V)만큼 상승하게 된다. As shown in FIG. 13, when one LED channel is shorted, the drain voltage V D2 of the shorted channel is smaller than the drain voltages V D1 , V D3 and V D4 of another channel (eg, 2.5 V). Will rise by.
이 때, 하기의 수학식 9에 의해 채널별 단락여부를 판정하기 위한 VMAX.VAR을 정의하게 되는데, 상기 VMAX.VAR은 모든 LED 채널이 포화되었을 때 허용되는 드레인 전압의 차이로서, 바꾸어 말하면, 정상 상태인 LED채널의 최대 드레인 전압(VD.MAX)과 최소 드레인 전압(VD.MIN)의 차이라고 정의할 수 있다. In this case, V MAX.VAR for determining whether or not a short circuit for each channel is defined by Equation 9 below, where V MAX.VAR is a difference between drain voltages allowed when all LED channels are saturated, in other words, It may be defined as the difference between the maximum drain voltage (V D.MAX ) and the minimum drain voltage (V D.MIN ) of the LED channel in a normal state.
즉, 상기 VMAX.VAR는 본 발명의 LED 구동드라이버가 적용되는 다양한 어플리케이션에서 허용되는 드레인 전압(VD)의 변화폭이라고 할 수 있으며, 드레인 전압의 최소값(VD.MIN)으로부터 VMAX.VAR 이상의 드레인 전압(VD)을 갖는 LED 채널은 불량한 것으로 판단하게 된다. That is, the V MAX.VAR may be referred to as the variation range of the drain voltage (V D ) that is permitted in various applications to which the LED driving driver of the present invention is applied, and V MAX.VAR from the minimum value of the drain voltage (V D.MIN ). It is determined that the LED channel having the above drain voltage V D is bad.
수학식 9
Figure PCTKR2011005133-appb-M000009
 Equation 9
Figure PCTKR2011005133-appb-M000009
상기 수학식 9에 대해 부연설명하자면, 상기 VMAX.VAR은 LED가 채널에 정상적으로 연결이 되었을 때, LED의 포워드 전압(VF) 산포에 의해 발생하는 nVF 차이의 허용 가능한 최대값을 의미한다고 할 수 있다. 따라서, 채널에 정상적으로 연결되었을 때, 각 채널의 드레인 전압의 차이가 2.0V가 넘으면, 가장 높은 드레인 전압을 갖는 채널을 불량한 것으로 판단할 수 있다. In detail, Equation 9 is that V MAX.VAR means an allowable maximum value of the nV F difference caused by the forward voltage (V F ) of the LED when the LED is normally connected to the channel. can do. Therefore, when the drain voltage of each channel exceeds 2.0 V when the channel is normally connected, the channel having the highest drain voltage may be determined to be defective.
또한, LED 채널의 구동전압(VLED)이 X·VREF만큼 상승하는데 걸리는 시간을 tR이라 정의하고, LED 채널의 구동전압(VLED)이 VMAX.VAR만큼 상승하는데 걸리는 시간을 tTOT 이라 정의하면, tTOT 을 하기의 수학식과 같이 나타낼 수 있다. In addition, the X · V REF by the time it takes to rise as long as the V t MAX.VAR driving voltage (V LED) of, LED channel and defined as t R of the time required for rising TOT driving voltage (V LED) of the LED channels In this case, t TOT may be expressed as in the following equation.
[규칙 제26조에 의한 보정 20.10.2011]　
Figure WO-DOC-MATHS-133
[Revision 20.10.2011 under Rule 26]
Figure WO-DOC-MATHS-133
즉, 먼저 구동전압(VLED)이 X·VREF만큼 상승하는데 걸리는 시간을 tR을 카운터를 이용하여 측정하고, 상기의 수학식에 VMAX.VAR(2.0V)과 X·VREF및 tR을 대입하면 tTOT 을 쉽게 구할 수 있게 된다. 상기 X는 상수를 나타내는데, 예를 들면, 0.5VREF 를 대입할 수 있는 등, 바람직하게는 0.25VREF 내지 0.75VREF의 범위에서 선택하는 것이 좋을 것이다.That is, the first driving voltage (V LED) is X · V REF for the time it takes to rise measured by using a counter as a t R, and the above equation V MAX.VAR (2.0V) and the X · V REF and t Substituting R makes t TOT easy to find. X represents a constant. For example, 0.5V REF can be substituted, and it is preferable to select from the range of 0.25V REF to 0.75V REF .
도 14를 참조하면, 포화상태가 되는 전압(VREF)보다 낮은 범위에서 구동전압(VLED)을 선형적으로 증가시킴에 따라, 각 LED 채널이 포화되는 모습을 도시하고 있다. Referring to FIG. 14, as the driving voltage V LED is linearly increased in a range lower than the voltage V REF to be saturated, each LED channel is saturated.
이 때, 시간의 흐름에 따라 가장 마지막에 포화상태가 된 채널로부터 tTOT 을 역으로 대입하여, 상기 tTOT보다 먼저 포화(saturation)된 채널은 단락(short)된 것으로 판단하게 된다. 즉, 마지막에 포화가 된 채널로부터 계산된 TTOT보다 먼저 포화된 채널의 드레인 전압(VD)은 마지막에 포화된 채널의 드레인 전압(VD) 보다 VMAX.VAR 이상의 높다고 판단 가능하기 때문에 단락된 것으로 판단할 수 있다. At this time, t TOT is reversely substituted from the last saturated channel as time passes, and it is determined that a channel saturated before t TOT is shorted. That is, the short-circuit since it is possible the drain voltage of the first channel than the saturated T TOT (V D) is more than V MAX.VAR higher than the drain voltage in the saturation channels to the last (V D) is determined from the calculated channel is saturated at the end It can be judged.
도 14에서는 가장 마지막에 포화상태가 된 채널인 4채널로부터 tTOT 을 구획하여 이전에 포화된 채널인 2채널이 단락되었음을 알 수 있다. In FIG. 14, it can be seen that t TOT is divided from four channels, which are the last saturated channels, to short-circuit two channels, which are previously saturated channels.
도 15는 본 발명의 일실시예에 따른 캘리브레이션 구간동안 획득되는 단락판단 기준전압과 정상구간동안 획득되는 게이트 전압을 나타낸 그래프이다.15 is a graph illustrating a short circuit determination reference voltage obtained during a calibration period and a gate voltage obtained during a normal period according to an embodiment of the present invention.
바꾸어 말하자면, 도 15는 캘리브레이션 구간 및 정상동작 구간동안 드레인 전압(VD)의 변화에 따른 본 발명의 2-PIN 디텍팅 방식에서 모니터링 가능한 게이트 전압(VG)의 변화를 도시하고 있다.In other words, FIG. 15 illustrates a change in the gate voltage V G that can be monitored in the 2-PIN detecting method of the present invention according to the change of the drain voltage V D during the calibration period and the normal operation period.
본 발명에서는 LED 채널의 정상동작시의 단락여부를 판정하기 위하여, 소정의 절차를 거치게 되는데, 캘리브레이션(calibration) 구간동안 구동전압(VLED)을 인위적으로 소정값만큼 올려서 획득되는 각 채널의 게이트 전압(VG)값들이 단락판단 기준전압(VSHT)이 된다. In the present invention, a predetermined procedure is performed to determine whether the LED channel is short-circuited during normal operation. The gate voltage of each channel obtained by artificially raising the driving voltage V LED by a predetermined value during a calibration period is provided. The (V G ) values become the short-circuit determination reference voltage V SHT .
즉, 본 발명에서, 상기 캘리브레이션은 LED 채널 중 어느 하나의 LED가 단락되면, 증가하게 될 드레인전압(VD)만큼 인위적으로 구동전압(VLED)을 올려주어, 구동전압(VLED)을 올려준 구간에서의 게이트 전압(VG)을 획득하는데 그 목적이 있다. 후술하겠지만, 정상동작 구간에서 획득한 게이트 전압(VG)이 캘리브레이션 구간 동안에서 획득한 게이트 전압(VG)보다 낮아진다면 그 채널에 단락이 발생했다고 판단하게 된다. That is, in the present invention, the calibration artificially raises the driving voltage (V LED ) by the drain voltage (V D ) which will increase when any one of the LED channels is short-circuited, thereby raising the driving voltage (V LED ). The purpose is to obtain the gate voltage V G in the quasi-section. As will be described later, if the gate voltage V G obtained in the normal operation period is lower than the gate voltage V G obtained during the calibration period, it is determined that a short circuit has occurred in the channel.
이와 같이 2-PIN디텍팅 방식을 채용하고 있는 본 발명에서는 보다 효율적인 채널의 단락여부 판단을 위해, 정상동작 구간에서의 게이트 전압(VG)값의 획득이 반복적으로 이루어져야 한다. 또한, 본 발명의 LED 구동드라이버가 적용될 다양할 어플리케이션과, 온도, 열 등 환경변화를 반영하기 위해 캘리브레이션 구간에서의 게이트 전압(VG)값의 획득도 주기적으로 시행됨이 바람직하다. As described above, in the present invention employing the 2-PIN detecting method, the gate voltage V G should be repeatedly obtained in the normal operation section in order to determine whether the channel is shorted. In addition, in order to reflect various applications to which the LED driving driver of the present invention is to be applied and environmental changes such as temperature and heat, the acquisition of the gate voltage V G value in the calibration period is also preferably performed periodically.
즉, 본 발명에서는 게이트 전압(VG)을 이용하여 드레인 전압(VD)을 유추판단해야 하는데, LED 채널의 정상동작시 단락여부의 판단에 있어서, 상기 단락판단 기준전압(VSHT)을 이용하게 되며, 단락판단 기준전압(VSHT)은 주기적으로 체크하여 이용하게 된다. That is, in the present invention, the drain voltage V D should be inferred by using the gate voltage V G. In determining whether the LED channel is short-circuited during normal operation of the LED channel, the short-circuit determination reference voltage V SHT is used. The short circuit determination reference voltage V SHT is periodically checked and used.
도 16은 본 발명의 일실시예에 따른 LED 채널의 구동시작 구간, 캘리브레이션 구간 및 정상동작 구간에 따른 최적화된 구동전압의 변화를 나타낸 그래프이다.16 is a graph illustrating a change in an optimized driving voltage according to a driving start section, a calibration section and a normal operation section of an LED channel according to an embodiment of the present invention.
도 16을 참조하여 정상동작시 LED 채널의 단락여부를 판정하는 방법을 설명하기로 한다. A method of determining whether a LED channel is shorted in normal operation will be described with reference to FIG. 16.
먼저, 구동시작구간(510) 동안 구동전압(VLED)은 최적화된 구동전압(VLED.OPT)이 될 때까지 선형적으로 증가하게 된다. First, during the driving start section 510, the driving voltage V LED increases linearly until the optimized driving voltage V LED .OPT is achieved .
이후, 단락여부를 판정하기 위한 게이트 전압(VG)을 얻기 위한 캘리브레이션 구간(520)동안 최적화된 구동전압(VLED.OPT)을 VMAX.VAR만큼 증가시킨다. Then, by increasing the drive voltage (V LED.OPT) optimized for the calibration period 520, to obtain a gate voltage (V G) for judging whether or not short circuit V MAX.VAR.
상기 VMAX.VAR은 모든 LED 채널이 포화되었을 때 허용되는 드레인 전압의 차이로서, 바꾸어 말하면, 각 채널별 드레인 전압의 최대값 (VD.MAX)과 드레인 전압의 최소값(VD.MIN)의 차이라고 할 수 있다. V MAX.VAR is a difference between the drain voltages allowed when all the LED channels are saturated. In other words, V MAX.VAR is the difference between the maximum value of each channel's drain voltage (V D.MAX ) and the minimum value of the drain voltage (V D.MIN ). It's a car.
즉, 상기 VMAX.VAR는 본 발명의 LED 구동드라이버가 적용되는 다양한 어플리케이션에서 허용되는 드레인 전압(VD)의 변화폭이라고 할 수 있으며, 드레인 전압의 최소값(VD.MIN)으로부터 VMAX.VAR 이상의 드레인 전압(VD)을 갖는 LED 채널은 불량한 것으로 판단하게 된다. That is, the V is V MAX.VAR MAX.VAR from the drain voltage (V D) the minimum value (V D.MIN) can be described as the variation range, and the drain voltage of which is allowed by the various applications to be applied to the LED drive driver of the present invention It is determined that the LED channel having the above drain voltage V D is bad.
한편, 최적화된 구동전압(VLED.OPT)을 VMAX.VAR(약 2.5V)만큼 증가시키는 방법의 일례를 들면, 반전부에 입력되는 전압을 필요한 시간동안 증가시키면 그 반전 출력인 DC-DC 컨버터의 피드백 전압은 떨어지게 되어, 결과적으로 최적화된 구동전압(VLED.OPT)을 용이하게 증가시킬 방식을 채택할 수 있을 것이다.On the other hand, for example, a method of increasing the optimized driving voltage (V LED.OPT ) by V MAX.VAR (about 2.5V), if the voltage input to the inverting part is increased for a necessary time, the inverting output is DC-DC. The feedback voltage of the converter will drop, resulting in an easy way to increase the optimized drive voltage (V LED.OPT ).
즉, 도 14를 참조하면, TR은 VS를 0.5V만큼 상승시키는데 걸리는 시간이고, TTOT은 채널전압을 VMAX_VAR만큼 상승시키는데 걸리는 시간이므로, TTOT의 시간동안 전원조절부의 DCDC 컨버터에 구동전압(VLED)이 최적화(Optimize) 되지 않았다는 정보를 주면, 구동전압(VLED)은 VMAX_VAR만큼 상승될 것이다. That is, referring to FIG. 14, since T R is a time required to increase V S by 0.5 V, and T TOT is a time required to increase channel voltage by V MAX_VAR , the T DC is driven by the DCDC converter of the power control unit during the time of T TOT . voltage (V LED) give the information has not been optimized (optimize), driving voltage (V LED) will be raised by V MAX_VAR.
또한, 도 17을 참조하면, 제 1스위치(SW1)를 통해 반전부로 출력되는 전압이 조정되면, 전원조절부는 정상적인 헤드룸 전압 컨트롤(Headroom Voltage Control) 동작을 수행하여 최적화된 구동전압(VLED_OPT )을 공급하게 된다. In addition, referring to FIG. 17, when the voltage output to the inverter is adjusted through the first switch SW1, the power controller performs a normal headroom voltage control operation to optimize the driving voltage V LED_OPT . Will be supplied.
구동전압(VLED)을 캘리브레이션을 하기 위한 전압, 즉 최적화된 구동전압(VLED_OPT )보다 약 2.5V 높은 전압까지 올리기 위해서는 TTOT의 시간동안 제 1스위치(SW1)를 열고, 제 2 스위치(SW2)를 닫으면, 구동전압(VLED)은 '최적화된 구동전압(VLED_OPT)보다 VMAX_VAR만큼 높은 전압'으로 상승하게 된다. To raise the driving voltage (V LED ) to the voltage for calibrating, that is, to about 2.5 V higher than the optimized driving voltage (V LED_OPT ), open the first switch SW1 during the time of T TOT and the second switch SW2. ), The driving voltage (V LED ) is raised to 'voltage higher by V MAX_VAR than the optimized driving voltage (V LED_OPT )'.
이어서, TTOT 이 지난 시간후에 제 2스위치(SW2)를 열면, 커패시턴스에 의해 반전부로 출력되는 전압은 '최적화된 구동전압(VLED_OPT)보다 VMAX_VAR만큼 높은 전압'으로 일정하게 공급되게 된다. Subsequently, when the second switch SW2 is opened after the time T TOT passes, the voltage output to the inverting unit by the capacitance is constantly supplied as 'voltage higher by V MAX_VAR than the optimized driving voltage V LED_OPT '.
이어서, 캘리브레이션(Calibration) 구간이 끝나고, 정상동작(Normal Operation) 구간에 진입할 때는 제 1스위치(SW1)를 닫으면, 전원조절부는 다시 정상적인 헤드룸 전압 컨트롤 동작을 수행하여 공급전압은 최적화된 구동전압(VLED_OPT)이 되게 된다. Subsequently, when the calibration section ends and the first switch SW1 is closed when entering the normal operation section, the power control unit performs a normal headroom voltage control operation so that the supply voltage is optimized drive voltage. (V LED_OPT ) becomes.
본 발명에서, 상기 제 2스위치(SW2)를 통해 커패시턴스로 들어가는 전류는, Gm-AMP의 Gm값의 역수값인 1/Gm 값을 갖는 게 바람직할 것이다.In the present invention, it is preferable that the current entering the capacitance through the second switch SW2 has a 1 / Gm value which is an inverse value of the Gm value of Gm-AMP.
이후, 최적화된 구동전압(VLED.OPT)이 증가된 구간에서 각각의 LED 채널의 게이트 전압(VG)값들을 AD컨버터를 이용하여 디지털로 변환하여 레지스트리에 저장하게 된다. 이와 같이 저장된 게이트 전압(VG)값들에 근거한 데이터(data)가 단락여부를 판단하는 단락판단 기준전압 (VSHT)이 된다Subsequently, the gate voltage V G of each LED channel is converted into a digital value by using an AD converter in the optimized driving voltage V LED.OPT section and stored in the registry. In this way, the data based on the stored gate voltage V G values becomes a short-circuit determination reference voltage V SHT for determining whether a short circuit occurs.
이후, 상기 증가된 최적화된 구동전압(VLED.OPT)을 헤드룸 전압 컨트롤(Headroom Voltage Control)을 통해 본래의 최적화된 구동전압(VLED.OPT)으로 환원시킨다. 즉, 약 2.5V만큼 증가시킨 최적화된 구동전압(VLED.OPT)을 다시 2.5V 감소시킨다. Then, thereby reducing the driving voltage (V LED.OPT) optimizing the increased cost to the original driving voltage (V LED.OPT) through the optimization of the headroom voltage control (Headroom Voltage Control). That is, the optimized driving voltage (V LED.OPT ), which is increased by about 2.5V, is reduced by 2.5V again.
이후, 정상동작 구간에서 주기적으로 각 채널의 게이트 전압(VG)값들을 수집하게 된다. 물론 각 채널의 게이트 전압(VG)값들은 아날로그-디지털 컨버팅을 통해 디지털 값으로 변환되며, 상기 캘리브레이션 구간(520) 동안 레지스트리에 저장된 데이터, 즉 단락판단 기준전압 (VSHT)의 값보다 게이트 전압(VG)값이 작을 경우에는 단락(short)된 것으로 판정하게 된다. Thereafter, the gate voltage V G of each channel is periodically collected in the normal operation period. Of course, the gate voltage (V G ) of each channel is converted into a digital value through analog-to-digital conversion, and the gate voltage is higher than the value of the data stored in the registry, that is, the short-circuit determination reference voltage (V SHT ), during the calibration period 520. If the (V G ) value is small, it is determined that it is short.
이상 본 발명의 구체적 실시형태와 관련하여 본 발명을 설명하였으나 이는 예시에 불과하며 본 발명은 이에 제한되지 않는다. 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 범위를 벗어나지 않고 설명된 실시형태를 변경 또는 변형할 수 있으며, 본 발명의 기술사상과 아래에 기재될 특허청구범위의 균등범위 내에서 다양한 수정 및 변형이 가능하다.The present invention has been described above in connection with specific embodiments of the present invention, but this is only an example and the present invention is not limited thereto. Those skilled in the art can change or modify the described embodiments without departing from the scope of the present invention, and within the equivalent scope of the technical spirit of the present invention and the claims to be described below. Various modifications and variations are possible.

Claims (14)

  1. 구동전압(VLED)이 입력되며, 적어도 하나 이상의 LED(Light Emitting Diode)와, 전계효과 트랜지스터 및 채널저항이 직렬로 연결되는 LED 채널을 다수 구비하는 LED 채널부;A driving channel (V LED ) is input, the LED channel unit including at least one LED (Light Emitting Diode) and a plurality of LED channels connected in series with the field effect transistor and the channel resistance;
    상기 전계효과 트랜지스터에 연결되어 각 LED채널에 일정한 전류가 흐르도록 제어하고, 상기 LED 채널의 개방(open)여부 또는 단락(short)여부를 판정하는 채널조사부; 및A channel irradiator connected to the field effect transistor to control a constant current to flow in each LED channel, and determine whether the LED channel is open or short; And
    상기 전계효과 트랜지스터의 게이트단과 연결되며, 다수의 게이트 전압(VG) 중 최대 게이트 전압(VG_MAX) 및 컨트롤 전압(VCTL)을 비교하여 상기 구동전압(VLED)을 헤드룸 전압(Headroom Voltage; VX)이 최소화되는 크기로 조절하여 상기 LED 채널부에 공급하는 전원조절부; 를 포함하되, It is connected to the gate terminal of the field effect transistor, and compares the maximum gate voltage (V G_MAX ) and the control voltage (V CTL ) of the plurality of gate voltage (V G ) to the driving voltage (V LED ) to the headroom voltage (Headroom Voltage A power control unit for supplying the LED channel unit to a size that minimizes V X ); Including,
    상기 채널조사부는 상기 전계효과 트랜지스터의 드레인(drain)단을 제외한 게이트(gate)단과 소스(source)단에 연결되는 것을 특징으로 하는 LED 구동 드라이버.And the channel irradiator is connected to a gate terminal and a source terminal except for a drain terminal of the field effect transistor.
  2. 제 1항에 있어서, 상기 채널조사부는,The method of claim 1, wherein the channel irradiation unit,
    (+)단에 상기 기준전압(VREF)이 입력되고, (-)단이 상기 소스단과 연결되며, 그 출력단이 상기 게이트단과 연결되는 제1 OP-AMP; 및(+) The reference voltage (V REF) is input to the stage, (-) terminal is connected the source end, the output end a second OP-AMP 1 is connected the gate end; And
    상기 전계효과 트랜지스터의 소스전압(VS)과 오픈전압(VOPEN)을 비교하여 출력하는 단락판단부;A short circuit determination unit configured to compare the source voltage V S and the open voltage V OPEN of the field effect transistor and output the comparison voltage;
    를 구비하는 것을 특징으로 하는 LED 구동 드라이버.LED driving driver comprising the.
  3. 제 1항에 있어서, 상기 채널조사부는,The method of claim 1, wherein the channel irradiation unit,
    상기 각각의 LED 채널의 게이트 전압(VG)값을 아날로그-디지털 변환하여 소정의 레지스트리에 저장하는 AD 컨버터(Analog-Digital Converter)를 더 포함하는 것을 특징으로 하는 LED 구동 드라이버.And an analog-to-digital converter (AD converter) for analog-to-digital converting the gate voltage (V G ) value of each LED channel and storing the same in a predetermined registry.
  4. 제 1항에 있어서, 상기 전원조절부는,The method of claim 1, wherein the power control unit,
    상기 다수의 LED 채널의 게이트 전압(VG)들을 입력받아 최대 게이트전압(VG_MAX)을 걸러내는 게이트 전압 입력단;A gate voltage input terminal configured to receive gate voltages V G of the plurality of LED channels and filter a maximum gate voltage V G_MAX ;
    컨트롤 전압(VCTL)이 입력되는 컨트롤 전압입력단;A control voltage input terminal to which a control voltage V CTL is input;
    상기 최대 게이트전압(VG_MAX)과 상기 컨트롤 전압(VCTL)을 비교하여 그 전압의 차이를 전류로 생성하여 출력하는 GM-AMP;GM-AMP comparing the maximum gate voltage (V G_MAX ) and the control voltage (V CTL ) to generate and output a current difference between the voltages;
    상기 헤드룸 전압(VX)을 이용하여 상기 GM-AMP의 출력을 반전시키는 반전부; 및An inversion unit for inverting the output of the GM-AMP using the headroom voltage V X ; And
    상기 반전부의 출력을 이용하여 피드백 루프를 제어하여 최적화된 구동전압(VLED.OPT)를 생성하는 DC-DC 컨버터;A DC-DC converter generating an optimized driving voltage (V LED.OPT ) by controlling a feedback loop using the output of the inverting unit;
    를 포함하는 것을 특징으로 하는 LED 구동 드라이버.LED driving driver comprising a.
  5. 제 4항에 있어서, 상기 게이트 전압(VG)들과 컨트롤 전압(VCTL)은 다이오드에 의해 전압강하되어 상기 GM-AMP에 입력되는 것을 특징으로 하는 LED 구동 드라이버.5. The LED driving driver of claim 4, wherein the gate voltages (V G ) and the control voltage (V CTL ) are dropped by a diode and input to the GM-AMP.
  6. 제 4항에 있어서, 상기 최적화된 구동전압(VLED.OPT)은, The method of claim 4, wherein the optimized driving voltage (V LED.OPT ),
    모든 LED 채널이 포화상태에서 동작하면서 전력효율을 최대화하기 위해 LED채널의 헤드룸 전압이 최소화되는 크기의 전압인 것을 특징으로 하는 LED 구동드라이버. LED driving driver, characterized in that all the LED channels are operating at saturation state and the headroom voltage of the LED channel is minimized to maximize power efficiency.
  7. 제 1항에 있어서, 상기 헤드룸 전압(Headroom Voltage)의 조절은,The method of claim 1, wherein the adjustment of the headroom voltage (Headroom Voltage),
    상기 전계효과 트랜지스터가 포화영역에서 동작할 때의 게이트 전압(VG)의 레벨을 미리 설정하여 컨트롤 전압(VCTL)을 정한 후, 상기 최대 게이트 전압(VG_MAX)과 컨트롤 전압(VCTL)을 비교하여 상기 구동전압(VLED)의 크기를 조절하는 것을 특징으로 하는 LED 구동 드라이버.After setting the level of the gate voltage (V G ) when the field effect transistor operates in the saturation region, the control voltage (V CTL ) is determined, and the maximum gate voltage (V G_MAX ) and the control voltage (V CTL ) are determined. Compared to adjust the size of the drive voltage (V LED ) LED drive driver.
  8. 제 1항에 있어서, The method of claim 1,
    상기 전계효과 트랜지스터는 NMOS 트랜지스터인 것을 특징으로 하는 LED 구동 드라이버.And the field effect transistor is an NMOS transistor.
  9. 제 1항에 있어서, 상기 LED채널이 구동시작(strat-up)시에 개방(open)되었는지 여부는, The method of claim 1, wherein whether the LED channel is opened at the start of driving (strat-up),
    상기 구동전압(VLED)을 다수의 LED채널 모두가 포화상태로 들어갈 수 있는 전압까지 선형적으로 증가하는데 걸리는 시간(tMAX)이 지난 후에도 응답이 없는 LED채널은 개방된 것으로 판정하는 것을 특징으로 하는 LED 구동 드라이버.After the time (t MAX ) for linearly increasing the driving voltage (V LED ) to a voltage at which all the LED channels can enter a saturation state, the LED channel without a response is determined to be open. LED driven driver.
  10. 제 1항에 있어서, 상기 LED 채널이 정상동작(normal operation)시에 개방(open)되었는지 여부는, The method of claim 1, wherein the LED channel is opened during normal operation.
    상기 구동전압(VLED)을 다수의 LED채널 모두가 포화상태로 들어갈 수 있는 전압까지 선형적으로 증가하는데 걸리는 시간(tMAX)이 지난 후에도, 상기 채널조사부에 의해 소스전압(VS)이 오픈전압(VOPEN)보다 낮은 전압으로 감지되면 개방된 것으로 판정하는 것을 특징으로 하는 LED 구동 드라이버.The source voltage V S is opened by the channel irradiator even after a time t MAX for linearly increasing the driving voltage V LED to a voltage at which all the LED channels can be saturated. The LED driving driver, characterized in that determined to be open when the voltage is detected lower than the voltage (V OPEN ).
  11. [규칙 제26조에 의한 보정 20.10.2011]
    제 1항에 있어서, 상기 LED 채널이 구동시작(star-up)시에 단락(short)되었는지 여부는 하기의 수학식을 이용하여 판단하되,
    Figure WO-DOC-MATHS-C11
    구동전압(VLED)을 선형적으로 증가시킬 때 가장 늦게 포화(saturation)되는 채널을 기준으로 역으로 계산하여, 상기 tTOT보다 먼저 포화되는 LED채널은 단락된 것으로 판정하는 것을 특징으로 하는 LED 구동 드라이버.
    (여기서 상기 VMAX.VAR은 정상 상태인 LED채널의 최대 드레인 전압(VD.MAX)과 최소 드레인 전압(VD.MIN)의 차이이고, 상기 tR은 채널 전압이 X·VREF 만큼 상승하는데 소요된 시간이며, 상기 VREF는 기준전압이고, 상기 X는 상수이며, 상기 tTOT은 채널전압이 VMAX.VAR만큼 상승하는데 소요된 시간이다.)
    [Revision 20.10.2011 under Rule 26]
    The method of claim 1, wherein whether the LED channel is shorted at start-up is determined by using the following equation.
    Figure WO-DOC-MATHS-C11
    LED driving, characterized in that the LED channel that is saturated before the t TOT is determined to be short-circuited by inversely calculating the driving voltage (V LED ) based on the channel that is saturated most recently. driver.
    Where V MAX.VAR is the difference between the maximum drain voltage (V D.MAX ) and the minimum drain voltage (V D.MIN ) of the LED channel in a steady state, and t R is the channel voltage increased by X · V REF . Is the time taken for the V REF to be a reference voltage, X is a constant, and t TOT is the time taken for the channel voltage to rise by V MAX.VAR .)
  12. 제 1항에 있어서, 상기 LED 채널이 정상동작(normal operation)시에 단락(short)되었는지 여부는,The method of claim 1, wherein whether the LED channel is shorted during normal operation
    캘리브레이션(Calibration) 구간동안 헤드룸 전압 컨트롤(Headroom Voltage Control)을 통해 최적화된 구동전압(VLED.OPT)을 소정값만큼 증가시키고 각 채널의 게이트 전압(VG)값을 아날로그-디지털 변환하여 레지스트리에 저장한 후,During the calibration period, the optimized drive voltage (V LED.OPT ) is increased by a predetermined value through headroom voltage control and the analog-to-digital conversion of the gate voltage (V G ) of each channel After saving to
    상기 최적화된 구동전압(VLED.OPT)을 상기 소정값만큼 감소시켜 정상동작구간에서 게이트 전압 (VG)값을 수집한 후, After the optimized driving voltage (V LED.OPT ) is reduced by the predetermined value to collect the gate voltage (V G ) in the normal operation period,
    상기 정상동작구간에서 수집된 게이트 전압(VG)값이 상기 캘리브레이션(Calibration)구간에서 저장된 게이트 전압(VG)값보다 작을 경우 단락(short)된 것으로 판정하는 것을 특징으로 하는 LED 구동 드라이버.And determining that the gate voltage (V G ) collected in the normal operation section is short when the gate voltage (V G ) value is less than the stored gate voltage (V G ) in the calibration section.
  13. 제 12항에 있어서, 상기 소정값은,The method of claim 12, wherein the predetermined value is,
    정상 상태인 LED채널의 최대 드레인 전압(VD.MAX)과 최소 드레인 전압(VD.MIN)의 차이, 즉 VMAX.VAR인 것을 특징으로 하는 LED 구동 드라이버.The difference between the maximum drain voltage (V D.MAX ) and the minimum drain voltage (V D.MIN ) of the LED channel in the normal state, that is, V MAX.VAR .
  14. 제 12항에 있어서, 상기 캘리브레이션 구간에서의 게이트 전압(VG)값 또는 정상동작구간에서의 게이트 전압(VG)값은, 주기적으로 수집되어 단락(short) 여부를 판정하는 것을 특징으로 하는 LED 구동 드라이버.Of claim 12, wherein the gate voltage (V G) value or a gate voltage (V G) values in the steady operation period in the calibration interval, LED, characterized in that which is periodically collected and determines whether or not short-circuit (short) Driven driver.
PCT/KR2011/005133 2011-07-13 2011-07-13 Led driver WO2013008967A1 (en)

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