WO2013004289A1

WO2013004289A1 - Method for obtaining a long-term short-circuit in a power electronics module

Info

Publication number: WO2013004289A1
Application number: PCT/EP2011/061215
Authority: WO
Inventors: Jürgen Häfner; Didier Cottet; Iulian Nistor; Liutauras Storasta; Munaf Rahimo; Nicola Schulz; Thorsten STRASSEL; Raffael Schnell
Original assignee: Abb Technology Ag
Priority date: 2011-07-04
Filing date: 2011-07-04
Publication date: 2013-01-10

Abstract

A method for simplifying short circuit failure mode (SCFM) transitions in a power electronics module. The method includes keeping at least one switch (101, 102, 103, 104) in closed position by means of a signal (109) supplied by a gate unit (110). Upon a failure of a first semiconductor chip (105) during which the failed chip enters an SCFM, the switch (102, 103, 104) is opened, wherein the gates of the second semiconductor chips (106, 107, 108) become floating. Thereby the blocking voltage of the semiconductor chips is reduced.

Description

Method for obtaining a long-term short-circuit in a power electronics module

TECHNICAL FIELD

The present invention relates to the technical field of power electronics (PE). In particular, it concerns a method for reducing the blocking voltage of a semiconductor chip in a power electronics module.

BACKGROUND

Voltage source converters (VSC) are power switches comprising a plurality of semiconductor chips such as e.g. insulated gate bipolar transistor (IGBT) power modules. They are often used in high-voltage direct current (HVDC) applications for converting direct current to alternating current and vice-versa or in static var compensators (SVC) for reactive power compensation in power transmission systems. Semiconductor chips such as IGBTs and gate turnoff (GTO) thyristors are suitable for high power applications. IGBTs are often preferable as they combine great power handling ability with features that make them well suited for connection in series.

Short circuit situations may occur in semiconductor circuits. In such situations it is necessary to be able to handle the effect of the short circuit. When a semiconductor breaks down, e.g. as a result of an over current or over voltage, the semiconductor cannot hold a voltage any longer. A damaged semiconductor cannot be controlled. It may hold only a small voltage difference and when conducting its resistance can have a value within a broad range. In the worst case, forcing a current through a damaged semiconductor with high resistance can generate an arc that will generate extensive power dissipation.

One example of a power electronics module is ABBs StakPak module. StakPak modules are used as power switches. They have the ability to go into a stable short circuit failure mode (SCFM) in case of an IGBT or diode failure. These modules are connected in series to obtain a valve with high blocking voltage. The blocking capability is taken over by the remaining modules in the stack in case of a short circuit in a module. The SCFM capability in StakPak modules is achieved by placing a plate made of a suitable metal on top of the IGBT and diode chips. A failure usually leads to a break-through and subsequently melts the metal plate and the silicon chip which then forms a conductive metal-silicon alloy. The lifetime of a conductive alloy, i.e. the time during it maintains its low-ohmic state, is limited, and is usually shorter than the targeted maintenance interval of a typical HVDC or SVC system. At the end-of-life of an SCFM its electrical resistance increases due to e.g. material oxidation and a subsequent chip then gets damaged and melts and forms the next low-ohmic alloy. This process is called the SCFM transition. These transitions can continue until all chips have been consumed.

For a subsequent chip to get damaged, it has to be exposed to e.g. a certain voltage. When the lifetime of a SCFM at a chip comes to an end it would be desirable to simplify the SCFM transition to the next chip, especially when using chips having an increased nominal blocking voltage, e.g. from 4,5 to 6,5 kV.

A possible solution to this is the so called "kill-switch" principle. The idea with this principle is to extend the total lifetime of the PE module in an electrical short-circuit mode by keeping the undamaged IGBTs actively in on-state. WO 2006/104430 A1 describes the procedure of detecting a semiconductor element failure in a converter valve of an electric power converter. The converter valve comprises a first and second group of parallel connected semiconducting elements and a current sensing device which senses the current flow of both groups. The converter valve further comprises a control unit which provides a signal for assuming a closed circuit after detecting a difference in the current flow of the first and second group of

semiconducting elements.

However, a problem with this solution is that in case of a gate-emitter short, a high current is drawn from the gate voltage supply which will put the whole unit out of operation.

SUMMARY

It is an object of the present invention to provide an improved alternative to the above techniques and prior art. More specifically, it is an object of the present invention to simplify SCFM transitions at an increased blocking voltage of a PE module.

To achieve these and other objects, a method and a PE module in accordance with the independent claims are provided.

The invention is based on the insight that the blocking voltage of typical gate-controlled semiconductor chips used in PE modules is reduced when the chips' gates are floating. In the case of an SCFM transition, a lower breakdown voltage would trigger the SCFM transition earlier and thus facilitate the use of chips with a higher blocking voltage. According to a first aspect of the invention, a method for simplifying SCFM transitions after a first semiconductor chip failure in a PE module is provided as defined in claim 1 .

According to a second aspect of the invention, a PE module for simplifying SCFM transitions is provided as defined in claim 7.

The blocking voltage of a gate-controlled semiconductor chip is reduced when the chip's gate is floating. Lower blocking voltage simplifies the SCFM transition for a chip when the lifetime of the SCFM for a previously failed chip comes to an end. An implementation for obtaining floating gates after a first failure is achieved by disconnecting the gates of individual chips or certain sub-sections of the PE module (sub-modules) from the gate unit (GU). This is done by implementing one or several switches into the gate lines of the individual chips or sub-sections, where the switches are controlled by the GU. In accordance with an embodiment of the invention, a PE module comprises a first

semiconductor chip, a plurality of second semiconductor chips, and at least one switch located between the gates of at least one of the plurality of second semiconductor chips and a GU. The at least one switch is controlled by the GU. During normal operation the at least one switch is configured to be closed, in response to a signal provided by the GU. The signal could be e.g. a voltage, a current or an optical signal. After a failure of the first semiconductor chip, the failed chip enters an SCFM. As the GU applies no more signals to the control terminal of the at least one switch it changes to an open position, wherein the gates of at least one of the plurality of second semiconductor chips become floating. The SCFM will be aging and finally it will lead to an SCFM transition. The SCFM transition will move to the chip with the lowest blocking voltage, which will be the at least one of the plurality of second semiconductor chips with a floating gate.

In accordance with another embodiment of the invention, a PE module comprises a first semiconductor chip, a plurality of second semiconductor chips, and at least one switch is located between at least one of the plurality of second semiconductor chips and a GU. The at least one switch, which is controlled by the GU, is kept in a closed position until a chip failure. When a failure of the first semiconductor chip occurs, the at least one switch will be opened as the GU will not supply any more signals and the failed chip will enter an SCFM. The blocking capability of the at least one of the plurality of second semiconductor chips is reduced which means that the at least one of the plurality of second semiconductor chips is the one with the lowest breakdown voltage. The difference between the at least one of the plurality of second semiconductor chips and the other semiconductor chips or sub-modules is that this specific at least one of the plurality of second semiconductor chips is not intended for switching under normal operating conditions like the other chips. This specific chip stays in blocking mode (i.e. with a defined gate voltage) all the time until a chip fails somewhere. Then this specific chip's gate is set to floating by opening the switch and its blocking voltage is reduced. The SCFM will be aging and finally it will lead to an SCFM transition. The SCFM transition will then go with certainty to this specific chip since it has the lowest blocking voltage. The at least one of the plurality of second semiconductor chips can be designed in a particular way so that its SCFM lifetime is much longer than the SCFM lifetime of a normal chip, e.g. the it can have a much larger area (it could e.g. be a whole wafer) or a more elaborate mechanical construction, more expensive materials etc. could be used to obtain a very long SCFM lifetime, in particular longer than the service interval of the converter station.

One advantage with the concept of the present invention is that it does not need to be powered after an initial failure and SCFM event. It will be acting completely passively and will ease SCFM transitions which become more difficult when up-scaling the module's blocking voltage. Another advantage and benefit is that new solutions for a stable long-term electrical bypass become possible. This, along with that the SCFM transitions will happen more smoothly, results in a higher reliability of the StakPak module and the potential to up-scale the StakPak with respect to higher currents/voltages. BRIEF DESCRIPTION OF THE DRAWINGS

Further characteristics and advantages of the present invention will emerge more clearly to a person skilled in the art from the following non-limited detailed description when considered in connection with the attached drawings, wherein:

Figure 1 shows a schematic drawing of a PE module in accordance with an exemplifying embodiment of the invention. Figure 2 shows a schematic flowchart of method steps in accordance with an exemplifying embodiment of the present invention.

Figure 3 shows a schematic drawing of a PE module in accordance with another exemplifying embodiment of the invention.

DETAILED DESCRIPTION

An embodiment for simplifying SCFM transitions after a first semiconductor chip failure in a PE module 100, is shown in figure 1 . The PE module 100 comprises switches 101 -104 and a first semiconductor chip or sub-module 105 and a plurality of second semiconductor chips or sub- modules 106-108. Further, the PE module 100 comprises a gate unit terminal 109 for connection to a gate unit (GU) 1 10. During normal operation the switches 101 -104 are in a closed state which allows the GU 1 10 to control the first- and second semiconductor chips 105- 108. With reference to figure 2, the operation according to an embodiment is shown. At step 200, the switches connecting the first- and second semiconductor chips or sub-modules to the GU are permanently on, e.g. by applying a voltage to the control terminal of the switches. All gates are connected to the GU. When the first semiconductor chip fails for some reason, step 201 , a SCFM is formed at the failed first semiconductor chip's position which may lead to a gate- emitter short within this chip, step 202. This leads to a shorted gate of all other gates within the PE module. At step 203, the GU then detects the failure, by e.g. a voltage measurement, and subsequently powers down or it fails to operate. As the GU applies no more signals to the control terminal of the switches, the switches are opened, step 204, and the gates of the second semiconductor chips, i.e. the non-failed chips, become floating. The applied signal from the GU to control the switches could include a voltage, a current or an optical signal. The switches can be e.g. voltage-controlled semiconductor switches (e.g. MOSFETs). In the case of normally-off switches, the switches are closed when a voltage is applied to their control terminal and they are open when zero voltage is applied which happens after a GU power-down. Further possibilities for switches are mechanical switches, relays or fuses.

Now the second semiconductor chips are not any more connected to the failed first

semiconductor chip which may contain a gate-emitter short. The initial SCFM is aging and it will eventually lead to an SCFM transition, step 205. At step 206, the SCFM transition will move to the chip with the lowest blocking capability. As the blocking voltage of a chip is reduced when the chip's gate is floating, the SCFM transition will move to a chip with a floating gate. Thus, the SCFM transition will move to one of the plurality of second semiconductor chips. At step 207, a new SCFM is formed at the newly failed second semiconductor chip. When all chips within the PE module are used up by the individual SCFMs, the PE module needs to be replaced, step 208. Otherwise, if all chips within the PE module are not used up by the SCFM, the cycle of forming a SCFM at a failed chip which eventually will lead to a transition is repeated again, starting from step 205.

Another embodiment for simplifying SCFM transitions after a first semiconductor chip failure in a PE module 300, is shown in figure 3. The PE module 300 comprises a switch 301 , a first semiconductor chip or sub-module 302 and a plurality of second semiconductor chips or sub- modules 303-305. Further, the PE module 300 comprises a gate unit terminal 306 for connection to a GU 307.

One of the plurality of second semiconductor chips 308, which is electrically blocking with an applied gate voltage, is connected in parallel to the first- and second semiconductor chips or sub-modules 302-304 of the PE module 300. The second semiconductor chip 305 is connected to the GU 307 via a gate unit terminal 306 containing a disconnection switch 301 , which is controlled by the GU 307. Alternatively, the one of the plurality of semiconductor chips 305 can be placed outside the PE module but still connected in parallel to the first- and second semiconductor chips or sub- modules 302-304, and be connected to the GU 307 via a gate unit terminal 306. The disconnection switch 301 , which is controlled by the GU, could be placed either inside or outside the PE module 300.

When the switch disconnects the second semiconductor chip 305 from the GU 307 after an initial failure of the first semiconductor chip 302 in the PE module 300, making its gate floating, the blocking capability of the second semiconductor chip 305 is reduced, similar to the process described in figure 2. At a SCFM transition, the second semiconductor chip 305 will fail with certainty since it is the only one with a floating gate. The second semiconductor chip 305 can be optimised to possess specific properties, e.g. a high current carrying capability.

Under normal operating conditions, the second semiconductor chip 305 and the parallel connected first- and second semiconductor chips or sub-modules 302-304 should have a comparable blocking voltage since the second semiconductor chip 305 has to withstand the voltages occurring during normal operation. It should just be made sure that after a failure, the second semiconductor chip 305 is the one with the lowest breakdown voltage.

The second semiconductor chip 305 could be e.g. a semiconductor device such as an IGBT, MOSFET or a thyristor.

The person skilled in the art realises that that the present invention is not in any way restricted to the embodiments described above. On the contrary, several modifications and variations are possible within the scope of the invention as defined in the appended claims.

Claims

1 . A method for simplifying short circuit failure mode, SCFM, transitions in a power electronics, PE, module, the module including a first semiconductor chip, a plurality of second

semiconductor chips, and at least one switch located between the gates of at least one of the plurality of second semiconductor chips and a gate unit, GU, the method including:

keeping the at least one switch in closed position by means of a signal supplied by the GU, and

opening the at least one switch, upon a failure of the first semiconductor chip, wherein the gates of the at least one of the plurality of second semiconductor chips become floating, thereby reducing the blocking voltage of such second semiconductor chips.

2. A method according to claim 1 , wherein the method includes detecting that the first semiconductor chip, following a chip failure, has entered an SCFM.

3. A method according to claim 1 or 2, wherein the first and plurality of second semiconductor chips of the PE module are arranged within a plurality of sub-modules.

4. A method according to any of claims 1 -3, wherein the PE module includes a plurality of switches, wherein each of the plurality of switches connects one semiconductor chip or sub- module to the GU.

5. A method according to any one of claims 1 -3, wherein said at least one of the plurality of second semiconductor chips is a chip which always stays in blocking mode under normal operation, and which upon a floating gate provides a blocking voltage which is substantially less than the blocking voltage of the other chips of the second semiconductor chips.

6. A method according to any one of claims 1 -5, wherein the semiconductor chips are included in the group of IGBT, BIGT, MOSFET, JFET and thyristors.

7. A power electronics, PE, module including a first semiconductor chip, a plurality of second semiconductor chips, and at least one switch located between the gates of at least one of the plurality of second semiconductor chips and a gate unit terminal for connection to a gate unit, GU, wherein the at least one switch is adapted to, under normal operation, have a closed position in response to a signal provided by the GU, and, upon a failure of the first semiconductor chip, change to an open position, wherein the gates of the at least one of the plurality of second semiconductor chips become floating.

8. A PE module according to claim 7, wherein the PE module is adapted to detect that the first semiconductor chip, following a chip failure, has entered an SCFM.

9. A PE module according to claim 7 or 8, wherein the first and plurality of second

semiconductor chips are arranged within a plurality of sub-modules.

10. A PE module according to any of claims 7-9, including a plurality of switches, wherein each of the plurality of switches connects one semiconductor chip or sub-module to the GU.

1 1 . A PE module according to any one of claims 7-9, wherein said at least one of the plurality of second semiconductor chips is a chip which is adapted to always stay in blocking mode under normal operation, and upon a floating gate provide a blocking voltage which is substantially less than the blocking voltage of the other chips of the second semiconductor chips.

12. A PE module according to any one of claims 7-1 1 , wherein the semiconductor chips are included in the group of IGBT, BIGT, MOSFET, JFET and thyristors.