WO2013001692A1 - Electronic device and noise suppression method - Google Patents

Electronic device and noise suppression method Download PDF

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Publication number
WO2013001692A1
WO2013001692A1 PCT/JP2012/002526 JP2012002526W WO2013001692A1 WO 2013001692 A1 WO2013001692 A1 WO 2013001692A1 JP 2012002526 W JP2012002526 W JP 2012002526W WO 2013001692 A1 WO2013001692 A1 WO 2013001692A1
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WO
WIPO (PCT)
Prior art keywords
conductor
wiring board
conductor pattern
electronic device
external connection
Prior art date
Application number
PCT/JP2012/002526
Other languages
French (fr)
Japanese (ja)
Inventor
石田　尚志
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Publication of WO2013001692A1 publication Critical patent/WO2013001692A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q15/00—Devices for reflection, refraction, diffraction or polarisation of waves radiated from an antenna, e.g. quasi-optical devices
    • H01Q15/0006—Devices acting selectively as reflecting surface, as diffracting or as refracting device, e.g. frequency filtering or angular spatial filtering devices
    • H01Q15/006—Selective devices having photonic band gap materials or materials of which the material properties are frequency dependent, e.g. perforated substrates, high-impedance surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0236—Electromagnetic band-gap structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Definitions

  • the present invention relates to an electronic device having two wiring boards that overlap each other and a noise suppression method.
  • a semiconductor device such as a large scale integrated circuit (LSI: Large Scale Integration) is usually mounted on a mother board or the like in a form mounted on a package wiring board which is a dedicated wiring board.
  • LSI Large Scale Integration
  • EBG Electromagnetic Band Band Gap
  • the EBG forms a band gap that suppresses propagation of electromagnetic waves in a specific frequency band inside or on a plane by taking a structure in which dielectrics or metals are periodically arranged in two or three dimensions. .
  • Patent Document 1 describes that by providing an EBG pattern inside a motherboard having a multilayer wiring structure, it is possible to suppress interference between connectors on the motherboard.
  • Patent Document 2 describes that an EBG structure is provided in a region located below the semiconductor device in the interposer.
  • connection between two wiring boards that overlap each other is often made with a connection terminal provided between these two wiring boards.
  • noise may be generated from the connection terminal due to a signal transmitted through the connection terminal.
  • the EBG described in the above-mentioned document is formed inside the wiring board. For this reason, it was not possible to block noise propagating in the space between the two wiring boards overlapping each other, such as noise generated from the connection terminal.
  • An object of the present invention is to provide an electronic device and a noise suppression method that can block noise propagating in a space between two wiring boards that overlap each other.
  • a first wiring board A second wiring board connected to the first wiring board; With The first wiring board has a first conductor; The second wiring board has a second conductor at least partially formed in a region facing the first conductor, and a third conductor connected to the second conductor, A repeating structure of the conductor is formed using the second conductor, The first wiring board and the second wiring board are connected to an area where the first conductor and the second conductor overlap in a space between the first wiring board and the second wiring board.
  • An electronic device is provided in which no member is located.
  • the first conductor is provided on the first wiring board on which the electrical component is mounted, A second conductor and a third conductor connected to the second conductor in at least a part of a region facing the first conductor of the second wiring board on which the first wiring board and the electrical component are mounted.
  • a noise suppression method is provided that suppresses the propagation of noise in the space between the first wiring board and the second wiring board by forming a portion.
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 1st Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 2nd Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked up from the AA 'cross section of ().
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 3rd Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 4th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 5th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked up from the AA 'cross section of ().
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 6th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 7th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked up from the AA 'cross section of ().
  • FIG. 1A is a cross-sectional view showing the configuration of the electronic device according to the first embodiment.
  • FIG. 1B is a bottom view of the AA ′ cross section of FIG. 1A and shows the configuration of the surface of the mother board 13.
  • FIG. 1C is a top view of the AA ′ cross section of FIG. 1A, and shows the configuration of the surface of the package wiring board 300.
  • FIG. 1A is a cross-sectional view showing the configuration of the electronic device according to the first embodiment.
  • FIG. 1B is a bottom view of the AA ′ cross section of FIG. 1A and shows the configuration of the surface of the mother board 13.
  • FIG. 1C is a top view of the AA ′ cross section of FIG. 1A, and shows the configuration of the surface of the package wiring board 300.
  • This electronic device includes a package 12 and a mother board 13.
  • the package 12 includes a package wiring board 300 and a semiconductor chip 10.
  • the semiconductor chip 10 is mounted on the package wiring board 300.
  • the semiconductor chip 10 is flip-chip mounted on the package wiring board 300, but may be mounted by other mounting formats.
  • a package 12 is mounted on the mother board 13.
  • the package wiring board 300 is an example of a first wiring board
  • the mother board 13 is an example of a second wiring board.
  • the package wiring board 300 has a first conductor pattern 14 as a first conductor, and the mother board 13 has a second conductor pattern 15 as a second conductor.
  • the second conductor pattern 15 is formed in a region facing at least a part of the first conductor pattern, that is, a region at least partially overlapping the first conductor pattern 14 in plan view.
  • a repeating structure of the conductor is formed using at least one of the first conductor pattern 14 and the second conductor pattern 15.
  • at least one of the first conductor pattern 14 and the second conductor pattern 15 has a repeating structure, for example, a periodic structure in a region facing each other.
  • the first conductor pattern 14 and the second conductor pattern 15 constitute at least a part of an EBG (Electromagnetic Band Band Gap) structure 20.
  • the second conductor pattern 15 is electrically connected to other conductors of the mother board 13.
  • the first conductor pattern 14 is a sheet-like conductor pattern
  • the second conductor pattern 15 is a plurality of island-like conductor patterns that are separated from each other.
  • the mother board 13 has a fourth conductor pattern 17 in the wiring layer immediately below the second conductor pattern 15.
  • the fourth conductor pattern 17 is an example of a third conductor.
  • the fourth conductor pattern 17 is one of a ground plane and a power plane, for example, a ground plane, and extends in a region where the second conductor pattern 15 is formed in plan view.
  • the package wiring board 300 has an external connection terminal 320
  • the motherboard 13 has an external connection terminal 220.
  • the external connection terminal 320 is, for example, an electrode pad, and is formed on the surface 302 of the package wiring board 300 that faces the mother board 13.
  • the external connection terminal 220 is, for example, an electrode pad, and is formed on the surface 202 of the mother board 13 that faces the package wiring board 300.
  • the external connection terminals 220 and 320 are connected to each other by the connection member 111.
  • the EBG structure 20 is formed so as to surround the external connection terminals 220 and 320 and the connection member 111 in plan view.
  • a plurality of second conductor patterns 15 and external connection terminals 220 are formed.
  • the first conductor pattern 14 is formed on the surface 302 and is formed using the same conductor layer as the external connection terminal 320.
  • the second conductor pattern 15 is formed on the surface 202 and is formed of the same conductor layer as the external connection terminal 220.
  • the second conductor pattern 15 and the external connection terminals 220 are arranged in a grid pattern.
  • the arrangement period of the second conductor pattern 15 is shorter than the arrangement period of the external connection terminals 220.
  • the area of the second conductor pattern 15 is smaller than that of the external connection terminal 220.
  • the planar shape of both is a square, for example.
  • connection member 111 is a solder ball, and electrically connects the external connection terminal 320 of the package wiring board 300 and the external connection terminal 220 of the motherboard 13.
  • the periphery where the package wiring board 300 and the mother board 13 are connected by the connecting member 111 is sealed with a resin 112. That is, the resin 112 is filled in the space between the first conductor pattern 14 and the second conductor pattern 15.
  • the external connection terminal 320 of the package wiring board 300 is connected to the semiconductor chip 10 via the internal wiring and vias of the package wiring board 300. For this reason, the semiconductor chip 10 is connected to the external connection terminals 220 of the mother board 13 via the internal wiring, vias, and external connection terminals 320 of the package wiring board 300 and the connection member 111. In the semiconductor chip 10, each of the power supply line, the ground line, and the signal line is connected to the mother board 13.
  • the package wiring board 300 and the mother board 13 are multilayer wiring boards, and are formed by alternately laminating dielectric layers and conductor layers.
  • the sheet-like first conductor pattern 14 formed on the package wiring board 300 includes the multilayer wiring (including the third conductor pattern 16 on the inner side of the first conductor pattern 14) and vias of the package wiring board 300, and external connection.
  • the terminal 320, the connecting member 111, and the external connection terminal 220 are connected to the opposite type of the fourth conductor pattern 17, for example, the power plane.
  • the first conductor pattern 14 may be connected to a plane of the same type as the plane to which the above-described fourth conductor pattern 17 is connected among the power plane and the ground plane of the motherboard 13.
  • the second conductor pattern 15 formed on the mother board 13 is connected to the fourth conductor pattern 17 through the through hole 18.
  • the through hole 18 is formed at an arbitrary position in the planar shape of the second conductor pattern 15, and does not need to be formed at the center of the second conductor pattern 15.
  • a resist layer 304 is formed on the surface 302 of the package wiring board 300, and a resist layer 204 is formed on the surface 202 of the mother board 13.
  • the resist layer 304 has an opening 305 for exposing the external connection terminal 320 and the first conductor pattern 14, and the resist layer 204 has an opening 205 for exposing the external connection terminal 220.
  • the size of each capacitor is controlled by the distance between the package wiring board 300 and the mother board 13, the material of the resin 112, the size and arrangement of the island-like second conductor patterns 15, and the material of the mother board 13.
  • the inductance component is controlled by the material of the mother board 13 and the material, length, and thickness of the through hole 18.
  • the distance between the package wiring board 300 and the mother board 13 can be controlled by the shape of the connection member 111. By adjusting these, the band gap band of the EBG structure 20 can be adjusted.
  • the EBG structure 20 is a so-called mushroom type EBG
  • the unit cell 50 includes a fourth conductor pattern 17, an island-like second conductor pattern 15, a through hole 18, a resin 112, and a sheet-like first.
  • the conductive pattern 14 is constituted by a region facing the island-shaped second conductive pattern 15.
  • the first conductor pattern 14 corresponds to the upper conductor plane
  • the fourth conductor pattern 17 corresponds to the lower conductor plane.
  • the through hole 18 corresponds to an inductance portion of the mushroom
  • the second conductor pattern 15 corresponds to a head portion of the mushroom.
  • the unit cells 50 are repeatedly arranged, for example, periodically, whereby the EBG structure 20 is formed.
  • a capacitance is formed between the second conductor pattern 15 and the first conductor pattern 14, thereby suppressing noise propagation between the fourth conductor pattern 17 and the first conductor pattern 14.
  • the second conductor pattern 15 is formed on the mother board 13, and the first conductor pattern 14 is formed on the package wiring board 300.
  • the EBG structure 20 is formed in the space between the mother board 13 and the package wiring board 300. Therefore, noise is prevented from propagating through the space and radiated to the outside.
  • this noise for example, there is a connecting member 111.
  • the EBG structure 20 is designed so that the frequency of noise radiated from the connection member 111 is included in the band gap of the EBG structure 20, the noise radiated from the connection member 111 is a space between the package 12 and the motherboard 13. Leaking from is suppressed.
  • the first conductor pattern 14 is formed on the surface 302 of the package wiring board 300 that faces the mother board 13. For this reason, the distance between the first conductor pattern 14 and the second conductor pattern 15 can be reduced, and the capacitance component of the EBG structure 20 can be increased.
  • the second conductor pattern 15 is also formed on the surface 202 of the mother board 13 facing the package wiring board 300, the distance between the first conductor pattern 14 and the second conductor pattern 15 is further reduced. The capacitance component of the EBG structure 20 can be further increased.
  • the capacitance component can be controlled by adjusting the material characteristics of the resin 112 inserted between the first conductor pattern 14 and the second conductor pattern 15.
  • the resin 112 is inserted between the package 12 and the mother board 13 after assembling. Even after the package 12 is assembled on the mother board 13, the frequency characteristics of the EBG structure 20 can be controlled by adjusting the material characteristics of the resin to be inserted.
  • the interval between the same vias and connection members is within 1 ⁇ 2 of the wavelength ⁇ of the electromagnetic wave assumed as noise. It is preferable that “repetition” includes a case where a part of the configuration is missing in any unit cell 50. When the unit cell 50 has a two-dimensional array, “repetition” includes a case where the unit cell 50 is partially missing. Further, “periodic” includes a case where some of the constituent elements are deviated in some unit cells 50 and a case where the arrangement of some unit cells 50 themselves is deviated.
  • FIG. 2A is a cross-sectional view showing the configuration of the electronic device according to the second embodiment.
  • FIG. 2B is a bottom view of the AA ′ cross section of FIG. 2A and shows the configuration of the surface of the mother board 13.
  • FIG. 2C is a top view of the AA ′ cross section of FIG. 2A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
  • the second conductor pattern 15 and the external connection terminal 220 are arranged to constitute the same lattice. That is, the arrangement period of the second conductor pattern 15 and the arrangement period of the external connection terminal 220 are the same, and the distance between the second conductor pattern 15 and the external connection terminal 220 closest to the external connection terminal 220 is the mutual interval of the external connection terminals 220. Equal to the interval.
  • the second conductor pattern 15 has the same planar shape as the external connection terminal 220, and is, for example, a square.
  • the resin 112 is not inserted between the package wiring board 300 and the mother board 13. In this embodiment, the resin 112 can be added.
  • FIG. 3A is a cross-sectional view showing a configuration of an electronic device according to the third embodiment.
  • FIG. 3B is a bottom view of the AA ′ cross section of FIG. 3A and shows the configuration of the surface of the mother board 13.
  • FIG. 3C is a top view of the AA ′ cross section of FIG. 3A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
  • the semiconductor chip 10 is mounted on the package wiring board 300 using the bonding wires 11.
  • the first conductor pattern 14 is a plurality of island-like conductor patterns that are separated from each other, and the second conductor pattern 15 is a sheet-like conductor pattern.
  • the mother board 13 has a fourth conductor pattern 17 in the wiring layer immediately below the second conductor pattern 15.
  • the fourth conductor pattern 17 is one of a ground plane and a power plane, for example, a ground plane.
  • the first conductor pattern 14 and the external connection terminal 320 are arranged to constitute the same lattice. That is, the arrangement cycle of the first conductor pattern 14 and the arrangement cycle of the external connection terminal 320 are the same, and the distance between the first conductor pattern 14 and the external connection terminal 320 closest to the external connection terminal 320 is the mutual interval of the external connection terminals 320. Equal to the interval.
  • the first conductor pattern 14 has the same planar shape as the external connection terminal 320, and is, for example, a square. However, the first conductor pattern 14 and the external connection terminal 320 may be arranged to form different grids.
  • the connection member 111 is a solder ball, and electrically connects the external connection terminal 320 of the package wiring board 300 and the external connection terminal 220 of the motherboard 13.
  • the periphery where the package wiring board 300 and the mother board 13 are connected by the connecting member 111 is solidified by the resin 116, and the outer periphery thereof is solidified by the resin 117.
  • the space between the first conductor pattern 14 and the second conductor pattern 15 includes a region filled with the resin 116 and a region filled with the resin 117. Resin 116 and resin 117 have different material properties.
  • the package wiring board 300 and the mother board 13 are multilayer wiring boards, and are formed by alternately laminating dielectric layers and conductor layers.
  • the island-shaped first conductor pattern 14 formed on the package wiring board 300 includes the multilayer wiring (including the third conductor pattern 16 on the inner side of the first conductor pattern 14) and vias of the package wiring board 300, and external connection.
  • the terminal 320, the connecting member 111, and the external connection terminal 220 are connected to the opposite type of the fourth conductor pattern 17, for example, the power plane.
  • the first conductor pattern 14 may be connected to a plane of the same type as the plane to which the above-described fourth conductor pattern 17 is connected among the power plane and the ground plane of the motherboard 13.
  • the first conductor pattern 14 formed on the package wiring board 300 is connected to the third conductor pattern 16 through the through hole 19.
  • the through hole 19 is formed at an arbitrary position in the planar shape of the first conductor pattern 14, and does not need to be formed at the center of the first conductor pattern 14.
  • each capacitor of the EBG structure 20 depends on the distance between the package wiring board 300 and the mother board 13, the size and arrangement of the resin 116 and the resin 117, and the island-shaped first conductor pattern 14, and the material of the package wiring board 300.
  • the inductance component is controlled by the material of the package wiring board 300 and the material, length, and thickness of the through hole 19.
  • the distance between the package wiring board 300 and the mother board 13 can be controlled by the shape of the connection member 111. By adjusting these, the band gap band of the EBG structure 20 can be adjusted.
  • the EBG structure 20 is formed so as to surround the external connection terminals 220 and 320 and the connection member 111 with a double structure.
  • an EBG structure 21 surrounding the external connection terminals 220 and 320 and the connection member 111 and an EBG structure 22 surrounding the periphery thereof are formed.
  • the EBG structure 21 is a so-called mushroom type EBG, and has a unit cell 50.
  • the EBG structure 22 is also a so-called mushroom type EBG, and includes a unit cell 51.
  • the unit cells 50 and 51 are opposed to the island-like first conductor pattern 14 among the third conductor pattern 16, the island-like first conductor pattern 14, the through hole 19, and the sheet-like second conductor pattern 15. It is constituted by the area that is.
  • the second conductor pattern 15 corresponds to the upper conductor plane
  • the third conductor pattern 16 corresponds to the lower conductor plane.
  • the through hole 19 corresponds to an inductance portion of the mushroom
  • the first conductor pattern 14 corresponds to a head portion of the mushroom.
  • the unit cells 50 are repeatedly arranged, for example, periodically to form the EBG structure 21, and the unit cells 51 are repeatedly arranged, for example, to periodically form the EBG structure 22.
  • a difference in characteristics between the unit cell 50 and the unit cell 51 appears due to a difference in characteristics between the resin 116 and the resin 117.
  • the same effect as that of the first embodiment can be obtained also by this embodiment.
  • the characteristics of the resin 116 different from the dielectric constant of the resin 117 the capacity components of the unit cells 50 and 51 can be made different from each other.
  • the band gap band of the EBG structure 21 and the band gap band of the EBG structure 22 can be made different from each other. Therefore, it is possible to suppress noise in a plurality of different frequency bands.
  • the resins 116 and 117 can be inserted between the package 12 and the motherboard 13 after being assembled, the frequency characteristics of the EBG structure 20 can be controlled even after the package 12 is assembled on the motherboard 13. Can do.
  • FIG. 4A is a cross-sectional view showing a configuration of an electronic device according to the fourth embodiment.
  • FIG. 4B is a bottom view of the AA ′ cross section of FIG. 4A and shows the configuration of the surface of the mother board 13.
  • FIG. 4C is a top view of the AA ′ cross section of FIG. 4A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the third embodiment except for the following points.
  • the arrangement periods of the first conductor pattern 14 and the external connection terminal 220 are different. Even in the first conductor pattern 14, the size of the island-like planar shape and the arrangement period are different.
  • the resin 112 inserted between the package wiring board 300 and the mother board 13 is one kind.
  • the same effect as that of the third embodiment can be obtained. That is, by arranging multiple first conductor patterns 14 of different sizes, the unit cells 50 and 51 of the EBG structures 21 and 22 having different characteristics can be used without using a plurality of types of resins as the sealing resin. Can be formed. This makes it possible to suppress noise in a plurality of different frequency bands.
  • FIG. 5A is a cross-sectional view showing a configuration of an electronic device according to the fifth embodiment.
  • FIG. 5B is a bottom view of the AA ′ cross section of FIG. 5A and shows the configuration of the surface of the mother board 13.
  • FIG. 5C is a top view of the AA ′ cross section of FIG. 5A, and shows the configuration of the surface of the package wiring board 300.
  • FIG. This electronic device has the same configuration as the electronic device according to the third embodiment except for the following points.
  • the first conductor pattern 14 is formed of a stub instead of an island-like planar shape.
  • the first conductor pattern 14 is an open stub, but may be a short stub.
  • the resin 112 inserted between the package wiring board 300 and the mother board 13 is one kind.
  • the same effect as that of the third embodiment can be obtained.
  • the first conductor pattern 14 is formed of a stub, and the degree of freedom in designing to obtain the characteristics of the unit cell 50 of the EBG structure 20 can be improved.
  • FIG. 6A is a cross-sectional view showing the configuration of the electronic device according to the sixth embodiment.
  • FIG. 6B is a bottom view of the AA ′ cross section of FIG. 6A and shows the configuration of the surface of the mother board 13.
  • FIG. 6C is a top view of the AA ′ cross section of FIG. 6A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
  • the second conductor pattern 15 formed on the mother board 13 is a plurality of island-shaped conductor patterns spaced apart from each other.
  • the package wiring board 300 is not mounted with a semiconductor chip.
  • the package wiring board 300 has the first conductor pattern 14.
  • the first conductor pattern 14 is connected to the conductor pattern 501 of the motherboard 13 through the connection member 111, the external connection layer 502 on the motherboard 13 side, and the through hole 18 in the motherboard 13.
  • the conductor pattern 501 is connected to a power plane or a ground plane, for example, a ground plane.
  • the external connection layer 502 and the first conductor pattern 14 are sheet-like patterns on which two solder terminals are formed.
  • the second conductor pattern 15 is connected to the fourth conductor pattern 17 located in the internal wiring layer of the motherboard 13 through the through hole 18 formed in the motherboard 13.
  • the fourth conductor pattern 17 is the same type of plane as the plane to which the above-described conductor pattern 501 is not connected among the power plane and the ground plane, for example, the power plane.
  • the fourth conductor pattern 17 may be the same type of plane as the plane to which the conductor pattern 501 is connected among the power plane and the ground plane.
  • the unit cell 50 of the EBG structure 20 is configured by a region of the second conductor pattern 15, the through hole 18, the resin 112, and the first conductor pattern 14 facing the second conductor pattern 15.
  • the fourth conductor pattern 17 corresponds to the lower conductor plane
  • the first conductor pattern 14 corresponds to the upper conductor plane.
  • the through hole 18 corresponds to an inductance portion of the mushroom
  • the second conductor pattern 15 corresponds to a head portion of the mushroom.
  • the same effect as that of the first embodiment can be obtained.
  • the package wiring board 300 since the package wiring board 300 is not mounted with a semiconductor chip, the package wiring board 300 can be handled as a noise suppression component. In order to suppress noise generated from the mother board 13, there is an effect that the package wiring board 300 can be mounted at a predetermined location on the mother board 13. It is also possible to mount a plurality of package wiring boards 300 on the mother board 13 side by side.
  • the second conductor pattern 15 may be formed of a stub as shown in the fifth embodiment instead of the island-like planar shape.
  • the control range of the inductor component and the capacitance component of the unit cell 50 of the EBG structure 20 can be expanded.
  • the connection terminals between the package wiring board 300 and the mother board 13 are two places, and the island-like second conductor pattern 15 is also a matrix of two places.
  • the present invention is not limited to this. There is no.
  • the connection member 111 and the island-shaped second conductor pattern 15 may be a pair, or may form more matrices, and can be assembled in an arbitrary arrangement.
  • the EBG structure to comprise was a mushroom structure was shown, it is possible to apply arbitrary EBG structures, without being restricted by this.
  • FIG. 7A is a cross-sectional view showing the configuration of the electronic device according to the seventh embodiment.
  • 7A is a cross-sectional view taken along the line BB ′ of FIG. 7B
  • FIG. 7B is a view looking down from the cross-section AA ′ of FIG.
  • the structure of 13 surfaces is shown.
  • FIG. 7C is a top view of the AA ′ cross section of FIG. 7A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the second embodiment except for the following points.
  • the EBG structure 20 does not surround the external connection terminals 220 and 320 and the connection member 111. Instead, the unit cell 50 and the connecting member 111 constituting the EBG structure 20 are arranged in a confused manner.
  • the first conductor pattern 14 includes an opening 603 in a portion where the external connection terminal 320 is disposed. By providing the opening 603, it is possible to prevent the EBG structure 20 and the connection member 111 from being short-circuited. Thereby, the unit cell 50 and the connection member 111 can be arrange
  • the same effect as that of the second embodiment can be obtained. Furthermore, since the external connection terminals 220 and 320 and the EBG unit cell 50 can be mixed and arranged, the degree of freedom in designing the pin assignment of the external connection terminal 320 of the package 13 and the external connection terminal 220 of the motherboard 13 is increased. Can be improved.
  • the first conductor pattern 14 is formed on the surface 302 of the package wiring board 300 that faces the mother board 13, but the first conductor pattern 14 is formed on the internal wiring layer of the package wiring board 300. You may do it.
  • the second conductor pattern 15 is formed on the surface 202 of the mother board 13 facing the package wiring board 300, but the second conductor pattern 15 may be formed on the internal wiring layer of the mother board 13.
  • the configuration of the EBG structures 20, 21, and 22 is not limited to the above-described embodiment, and any structure that exhibits characteristics as an EBG can be applied as the EBG structures 20, 21, and 22.
  • the semiconductor chip is exemplified as the electronic element mounted on the package wiring board.
  • an electrical component other than the semiconductor chip may be used.
  • the structure shown in each of the above embodiments may be applied to a structure that obtains an electrical connection by mechanically pressing a package against a board, such as a land used in a land grid array.
  • the location of the EBG structure 20 is not limited to the above example.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

A package wiring substrate (300) has a first conductor pattern (14), and a motherboard (13) has a second conductor pattern (15). The second conductor pattern (15) is formed in a region that faces at least part of the first conductor pattern (14), in other words, in a region on which, in a plane view, at least part of the first conductor pattern (14) is overlapped. A repeated conductor structure is formed using either or both of the first conductor pattern (14) and the second conductor pattern (15). The first conductor pattern (14) and the second conductor pattern (15) constitute at least part of an EBG structure (20). The second conductor pattern (15) is electrically connected to another conductor that the motherboard (13) has.

Description

電子装置及びノイズ抑制方法Electronic device and noise suppression method
　本発明は、互いに重なる２つの配線基板を有する電子装置及びノイズ抑制方法に関する。 The present invention relates to an electronic device having two wiring boards that overlap each other and a noise suppression method.
　コンピュータ等に代表される電子機器の多くは、複数の配線基板を用いて構成されている。例えば大規模集積回路（LSI：Large Scale Integration）等の半導体装置は、通常、専用の配線基板であるパッケージ配線基板に搭載された形態でマザーボード等に実装される。近年の半導体装置の高周波化に伴い、高周波回路から発生する電磁雑音が電子機器内部の他の電子回路に電磁干渉し、電子機器の動作に支障をきたすケースが見られるようになった。 Many electronic devices such as computers are composed of a plurality of wiring boards. For example, a semiconductor device such as a large scale integrated circuit (LSI: Large Scale Integration) is usually mounted on a mother board or the like in a form mounted on a package wiring board which is a dedicated wiring board. With the recent increase in the frequency of semiconductor devices, there have been cases where electromagnetic noise generated from a high-frequency circuit interferes with other electronic circuits inside the electronic device and interferes with the operation of the electronic device.
　一方、近年はメタマテリアルの一種であるＥＢＧ（Electromagnetic Band Gap）の開発が進んでいる。ＥＢＧは、誘電体または金属等を二次元または三次元で周期的に配置した構造をとることにより、その内部または平面上で特定周波数帯の電磁波の伝搬を抑制するバンドギャップを形成するものである。 On the other hand, in recent years, development of EBG (Electromagnetic Band Band Gap) which is a kind of metamaterial is progressing. The EBG forms a band gap that suppresses propagation of electromagnetic waves in a specific frequency band inside or on a plane by taking a structure in which dielectrics or metals are periodically arranged in two or three dimensions. .
　例えば特許文献１には、多層配線構造を有するマザーボードの内部にＥＢＧパターンを設けることにより、マザーボードのコネクタ間で干渉が生じることが抑制できる、と記載されている。 For example, Patent Document 1 describes that by providing an EBG pattern inside a motherboard having a multilayer wiring structure, it is possible to suppress interference between connectors on the motherboard.
　また特許文献２には、インターポーザにおいて半導体装置の下方に位置する領域にＥＢＧ構造を設けることが記載されている。 Patent Document 2 describes that an EBG structure is provided in a region located below the semiconductor device in the interposer.
特開２００６－３０２９８６号公報JP 2006-302986 A 特開２００８－２７０３６３号公報JP 2008-270363 A
　マザーボードとパッケージ配線基板など、互いに重なる２つの配線基板間の接続は、これら２つの配線基板の間に設けられた接続端子で行われることが多い。このような場合において、接続端子を伝達する信号によって、接続端子からノイズが発生することがある。しかし上記した文献に記載のＥＢＧは、配線基板の内部に形成されている。このため、接続端子から発生するノイズのように、互いに重なる２つの配線基板の間の空間を伝播するノイズを遮断することはできなかった。 The connection between two wiring boards that overlap each other, such as a mother board and a package wiring board, is often made with a connection terminal provided between these two wiring boards. In such a case, noise may be generated from the connection terminal due to a signal transmitted through the connection terminal. However, the EBG described in the above-mentioned document is formed inside the wiring board. For this reason, it was not possible to block noise propagating in the space between the two wiring boards overlapping each other, such as noise generated from the connection terminal.
　本発明の目的は、互いに重なる２つの配線基板の間の空間を伝播するノイズを遮断することができる電子装置及びノイズ抑制方法を提供することにある。 An object of the present invention is to provide an electronic device and a noise suppression method that can block noise propagating in a space between two wiring boards that overlap each other.
　本発明によれば、第１配線基板と、
　前記第１配線基板に接続している第２配線基板と、
を備え、
　前記第１配線基板は第１導体を有し、
　前記第２配線基板は、前記第１導体と対向する領域に少なくとも一部が形成されている第２導体と、前記第２導体に接続している第３導体を有し、
　前記第２導体を用いて、導体の繰り返し構造が形成されており、
　前記第１配線基板と前記第２配線基板の間の空間のうち前記第１導体と前記第２導体とが重なっている領域には、前記第１配線基板と前記第２配線基板とを接続する部材が位置していない電子装置が提供される。 According to the present invention, a first wiring board;
A second wiring board connected to the first wiring board;
With
The first wiring board has a first conductor;
The second wiring board has a second conductor at least partially formed in a region facing the first conductor, and a third conductor connected to the second conductor,
A repeating structure of the conductor is formed using the second conductor,
The first wiring board and the second wiring board are connected to an area where the first conductor and the second conductor overlap in a space between the first wiring board and the second wiring board. An electronic device is provided in which no member is located.
　本発明によれば、電気部品が実装される第１配線基板に第１導体を設け、
　前記第１配線基板及び前記電気部品が実装される第２配線基板のうち前記第１導体に対向する領域の少なくとも一部に、第２導体と、前記第２導体に接続している第３導体を設け、
　前記第１導体及び前記第２導体の少なくとも一方に、繰り返し構造を持たせることにより、前記第１導体、前記第２導体、及び前記第３導体を用いて ＥＢＧ（Electromagnetic Band Gap）構造の少なくとも一部を形成して、前記第１配線基板と前記第２配線基板の間の空間においてノイズが伝播することを抑制するノイズ抑制方法が提供される。 According to the present invention, the first conductor is provided on the first wiring board on which the electrical component is mounted,
A second conductor and a third conductor connected to the second conductor in at least a part of a region facing the first conductor of the second wiring board on which the first wiring board and the electrical component are mounted. Provided,
By providing at least one of the first conductor and the second conductor with a repeating structure, at least one of an EBG (Electromagnetic Band Gap) structure using the first conductor, the second conductor, and the third conductor. A noise suppression method is provided that suppresses the propagation of noise in the space between the first wiring board and the second wiring board by forming a portion.
　本発明によれば、互いに重なる２つの配線基板の間の空間を伝播するノイズを遮断することができる。 According to the present invention, it is possible to block noise that propagates in the space between two wiring boards that overlap each other.
　上述した目的、およびその他の目的、特徴および利点は、以下に述べる好適な実施の形態、およびそれに付随する以下の図面によってさらに明らかになる。 The above-described object and other objects, features, and advantages will be further clarified by a preferred embodiment described below and the following drawings attached thereto.
（ａ）は第１の実施形態に係る電子装置の構成を示す断面図であり、（ｂ）は（ａ）のＡ－Ａ´断面から下を見た図であり、（ｃ）は（ａ）のＡ－Ａ´断面から上を見た図である。(A) is sectional drawing which shows the structure of the electronic device which concerns on 1st Embodiment, (b) is the figure which looked down from the AA 'cross section of (a), (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of). （ａ）は第２の実施形態に係る電子装置の構成を示す断面図であり、（ｂ）は（ａ）のＡ－Ａ´断面から下を見た図であり、（ｃ）は（ａ）のＡ－Ａ´断面から上を見た図である。(A) is sectional drawing which shows the structure of the electronic device which concerns on 2nd Embodiment, (b) is the figure which looked down from the AA 'cross section of (a), (c) is (a) It is the figure which looked up from the AA 'cross section of (). （ａ）は第３の実施形態に係る電子装置の構成を示す断面図であり、（ｂ）は（ａ）のＡ－Ａ´断面から下を見た図であり、（ｃ）は（ａ）のＡ－Ａ´断面から上を見た図である。(A) is sectional drawing which shows the structure of the electronic device which concerns on 3rd Embodiment, (b) is the figure which looked down from the AA 'cross section of (a), (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of). （ａ）は第４の実施形態に係る電子装置の構成を示す断面図であり、（ｂ）は（ａ）のＡ－Ａ´断面から下を見た図であり、（ｃ）は（ａ）のＡ－Ａ´断面から上を見た図である。(A) is sectional drawing which shows the structure of the electronic device which concerns on 4th Embodiment, (b) is the figure which looked down from the AA 'cross section of (a), (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of). （ａ）は第５の実施形態に係る電子装置の構成を示す断面図であり、（ｂ）は（ａ）のＡ－Ａ´断面から下を見た図であり、（ｃ）は（ａ）のＡ－Ａ´断面から上を見た図である。(A) is sectional drawing which shows the structure of the electronic device which concerns on 5th Embodiment, (b) is the figure which looked down from the AA 'cross section of (a), (c) is (a) It is the figure which looked up from the AA 'cross section of (). （ａ）は第６の実施形態に係る電子装置の構成を示す断面図であり、（ｂ）は（ａ）のＡ－Ａ´断面から下を見た図であり、（ｃ）は（ａ）のＡ－Ａ´断面から上を見た図である。(A) is sectional drawing which shows the structure of the electronic device which concerns on 6th Embodiment, (b) is the figure which looked down from the AA 'cross section of (a), (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of). （ａ）は第７の実施形態に係る電子装置の構成を示す断面図であり、（ｂ）は（ａ）のＡ－Ａ´断面から下を見た図であり、（ｃ）は（ａ）のＡ－Ａ´断面から上を見た図である。(A) is sectional drawing which shows the structure of the electronic device which concerns on 7th Embodiment, (b) is the figure which looked down from the AA 'cross section of (a), (c) is (a) It is the figure which looked up from the AA 'cross section of ().
　以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
　図１（ａ）は、第１の実施形態に係る電子装置の構成を示す断面図である。図１（ｂ）は、図１（ａ）のＡ－Ａ´断面から下を見た図であり、マザーボード１３の表面の構成を示している。図１（ｃ）は、図１（ａ）のＡ－Ａ´断面から上を見た図であり、パッケージ配線基板３００の表面の構成を示している。 FIG. 1A is a cross-sectional view showing the configuration of the electronic device according to the first embodiment. FIG. 1B is a bottom view of the AA ′ cross section of FIG. 1A and shows the configuration of the surface of the mother board 13. FIG. 1C is a top view of the AA ′ cross section of FIG. 1A, and shows the configuration of the surface of the package wiring board 300. FIG.
　この電子装置は、パッケージ１２及びマザーボード１３を備える。パッケージ１２は、パッケージ配線基板３００及び半導体チップ１０を備える。半導体チップ１０はパッケージ配線基板３００に実装されている。本図に示す例では、半導体チップ１０はパッケージ配線基板３００にフリップチップ実装されているが、他の実装形式により実装されていても良い。マザーボード１３には、パッケージ１２が実装されている。パッケージ配線基板３００は第１配線基板の一例であり、マザーボード１３は第２配線基板の一例である。 This electronic device includes a package 12 and a mother board 13. The package 12 includes a package wiring board 300 and a semiconductor chip 10. The semiconductor chip 10 is mounted on the package wiring board 300. In the example shown in the figure, the semiconductor chip 10 is flip-chip mounted on the package wiring board 300, but may be mounted by other mounting formats. A package 12 is mounted on the mother board 13. The package wiring board 300 is an example of a first wiring board, and the mother board 13 is an example of a second wiring board.
　パッケージ配線基板３００は第１導体としての第１導体パターン１４を有しており、マザーボード１３は第２導体としての第２導体パターン１５を有している。第２導体パターン１５は、第１導体パターンの少なくとも一部に対向する領域、すなわち平面視において第１導体パターン１４と少なくとも一部が重なる領域に形成されている。そして第１導体パターン１４及び第２導体パターン１５の少なくとも一方を用いて、導体の繰り返し構造が形成されている。本実施形態では、第１導体パターン１４及び第２導体パターン１５は、少なくとも一方は、互いに対向している領域に繰り返し構造、例えば周期構造を有している。そして第１導体パターン１４及び第２導体パターン１５は、ＥＢＧ（Electromagnetic Band Gap）構造体２０の少なくとも一部を構成している。そして第２導体パターン１５は、マザーボード１３が有する他の導体と電気的に接続している。 The package wiring board 300 has a first conductor pattern 14 as a first conductor, and the mother board 13 has a second conductor pattern 15 as a second conductor. The second conductor pattern 15 is formed in a region facing at least a part of the first conductor pattern, that is, a region at least partially overlapping the first conductor pattern 14 in plan view. A repeating structure of the conductor is formed using at least one of the first conductor pattern 14 and the second conductor pattern 15. In the present embodiment, at least one of the first conductor pattern 14 and the second conductor pattern 15 has a repeating structure, for example, a periodic structure in a region facing each other. The first conductor pattern 14 and the second conductor pattern 15 constitute at least a part of an EBG (Electromagnetic Band Band Gap) structure 20. The second conductor pattern 15 is electrically connected to other conductors of the mother board 13.
　本図に示す例では、第１導体パターン１４はシート状の導体パターンであり、第２導体パターン１５は、互いに離間している複数の島状の導体パターンである。 In the example shown in the figure, the first conductor pattern 14 is a sheet-like conductor pattern, and the second conductor pattern 15 is a plurality of island-like conductor patterns that are separated from each other.
　またマザーボード１３は、第２導体パターン１５の一つ下の配線層に、第４導体パターン１７を有している。第４導体パターン１７は、第３導体の一例である。第４導体パターン１７は、グラウンドプレーン及び電源プレーンの一方、例えばグラウンドプレーンであり、平面視において第２導体パターン１５が形成されている領域に延在している。 The mother board 13 has a fourth conductor pattern 17 in the wiring layer immediately below the second conductor pattern 15. The fourth conductor pattern 17 is an example of a third conductor. The fourth conductor pattern 17 is one of a ground plane and a power plane, for example, a ground plane, and extends in a region where the second conductor pattern 15 is formed in plan view.
　本図に示す例では、パッケージ配線基板３００は外部接続端子３２０を有しており、マザーボード１３は外部接続端子２２０を有している。外部接続端子３２０は、例えば電極パッドであり、パッケージ配線基板３００のうちマザーボード１３に対向する面３０２に形成されている。外部接続端子２２０は、例えば電極パッドであり、マザーボード１３のうちパッケージ配線基板３００に対向する面２０２に形成されている。外部接続端子２２０，３２０は、接続部材１１１により互いに接続されている。そして平面視においてＥＢＧ構造体２０は、外部接続端子２２０，３２０及び接続部材１１１を取り囲むように形成されている。 In the example shown in the figure, the package wiring board 300 has an external connection terminal 320, and the motherboard 13 has an external connection terminal 220. The external connection terminal 320 is, for example, an electrode pad, and is formed on the surface 302 of the package wiring board 300 that faces the mother board 13. The external connection terminal 220 is, for example, an electrode pad, and is formed on the surface 202 of the mother board 13 that faces the package wiring board 300. The external connection terminals 220 and 320 are connected to each other by the connection member 111. The EBG structure 20 is formed so as to surround the external connection terminals 220 and 320 and the connection member 111 in plan view.
　第２導体パターン１５及び外部接続端子２２０はそれぞれ複数形成されている。そして第１導体パターン１４は面３０２に形成されており、外部接続端子３２０と同一の導体層を用いて形成されている。また第２導体パターン１５は面２０２に形成されており、外部接続端子２２０と同一の導体層により形成されている。 A plurality of second conductor patterns 15 and external connection terminals 220 are formed. The first conductor pattern 14 is formed on the surface 302 and is formed using the same conductor layer as the external connection terminal 320. The second conductor pattern 15 is formed on the surface 202 and is formed of the same conductor layer as the external connection terminal 220.
　第２導体パターン１５及び外部接続端子２２０は格子状に配置されている。第２導体パターン１５の配置周期は、外部接続端子２２０の配置周期より短く配置されている。第２導体パターン１５の面積は、外部接続端子２２０よりも小さい。両者の平面形状は例えば正方形である。 The second conductor pattern 15 and the external connection terminals 220 are arranged in a grid pattern. The arrangement period of the second conductor pattern 15 is shorter than the arrangement period of the external connection terminals 220. The area of the second conductor pattern 15 is smaller than that of the external connection terminal 220. The planar shape of both is a square, for example.
　接続部材１１１はハンダボールであり、パッケージ配線基板３００の外部接続端子３２０とマザーボード１３の外部接続端子２２０間を電気的に接続している。パッケージ配線基板３００とマザーボード１３が接続部材１１１により接続された周辺は、樹脂１１２で封止されている。すなわち樹脂１１２は、第１導体パターン１４と第２導体パターン１５の間の空間に充填されている。 The connection member 111 is a solder ball, and electrically connects the external connection terminal 320 of the package wiring board 300 and the external connection terminal 220 of the motherboard 13. The periphery where the package wiring board 300 and the mother board 13 are connected by the connecting member 111 is sealed with a resin 112. That is, the resin 112 is filled in the space between the first conductor pattern 14 and the second conductor pattern 15.
　パッケージ配線基板３００の外部接続端子３２０は、パッケージ配線基板３００の内部配線やビアを介して、半導体チップ１０に接続している。このため半導体チップ１０は、パッケージ配線基板３００の内部配線、ビア、及び外部接続端子３２０、並びに接続部材１１１を介してマザーボード１３の外部接続端子２２０に接続している。半導体チップ１０は、電源ライン、グラウンドライン、及び信号ラインそれぞれがマザーボード１３に接続している。 The external connection terminal 320 of the package wiring board 300 is connected to the semiconductor chip 10 via the internal wiring and vias of the package wiring board 300. For this reason, the semiconductor chip 10 is connected to the external connection terminals 220 of the mother board 13 via the internal wiring, vias, and external connection terminals 320 of the package wiring board 300 and the connection member 111. In the semiconductor chip 10, each of the power supply line, the ground line, and the signal line is connected to the mother board 13.
　パッケージ配線基板３００及びマザーボード１３はそれぞれ多層配線基板であり、誘電層及び導体層を交互に積層することにより形成されている。そしてパッケージ配線基板３００に形成されたシート状の第１導体パターン１４は、パッケージ配線基板３００の多層配線（第１導体パターン１４より一層内側の第３導体パターン１６を含む）及びビア、並びに外部接続端子３２０、接続部材１１１、及び外部接続端子２２０を介して、マザーボード１３の電源プレーン及びグラウンドプレーンのうち、上記した第４導体パターン１７とは逆の種類、例えば電源プレーンに接続している。ただし第１導体パターン１４は、マザーボード１３の電源プレーン及びグラウンドプレーンのうち、上記した第４導体パターン１７が接続しているプレーンと同じ種類のプレーンに接続しても良い。またマザーボード１３に形成された第２導体パターン１５は、スルーホール１８を介して第４導体パターン１７に接続している。スルーホール１８は、第２導体パターン１５の平面形状において任意の位置に形成され、第２導体パターン１５の中心に形成する必要は無い。 The package wiring board 300 and the mother board 13 are multilayer wiring boards, and are formed by alternately laminating dielectric layers and conductor layers. The sheet-like first conductor pattern 14 formed on the package wiring board 300 includes the multilayer wiring (including the third conductor pattern 16 on the inner side of the first conductor pattern 14) and vias of the package wiring board 300, and external connection. Of the power plane and ground plane of the mother board 13, the terminal 320, the connecting member 111, and the external connection terminal 220 are connected to the opposite type of the fourth conductor pattern 17, for example, the power plane. However, the first conductor pattern 14 may be connected to a plane of the same type as the plane to which the above-described fourth conductor pattern 17 is connected among the power plane and the ground plane of the motherboard 13. The second conductor pattern 15 formed on the mother board 13 is connected to the fourth conductor pattern 17 through the through hole 18. The through hole 18 is formed at an arbitrary position in the planar shape of the second conductor pattern 15, and does not need to be formed at the center of the second conductor pattern 15.
　なお、パッケージ配線基板３００の面３０２にはレジスト層３０４が形成されており、マザーボード１３の面２０２にはレジスト層２０４が形成されている。レジスト層３０４は、外部接続端子３２０及び第１導体パターン１４を露出するための開口３０５を有しており、レジスト層２０４は外部接続端子２２０を露出するための開口２０５を有している。 Note that a resist layer 304 is formed on the surface 302 of the package wiring board 300, and a resist layer 204 is formed on the surface 202 of the mother board 13. The resist layer 304 has an opening 305 for exposing the external connection terminal 320 and the first conductor pattern 14, and the resist layer 204 has an opening 205 for exposing the external connection terminal 220.
　ＥＢＧ構造体２０は、パッケージ配線基板３００とマザーボード１３の間隔、樹脂１１２の材料、並びに島状の第２導体パターン１５の大きさ、配列、マザーボード１３の材料によって各容量の大きさが制御され、マザーボード１３の材料、スルーホール１８の材料、長さ、及び太さによってインダクタンス成分が制御される。パッケージ配線基板３００とマザーボード１３の間隔は、接続部材１１１の形状によって制御することができる。これらを調節することにより、ＥＢＧ構造体２０のバンドギャップ帯を調節することができる。 In the EBG structure 20, the size of each capacitor is controlled by the distance between the package wiring board 300 and the mother board 13, the material of the resin 112, the size and arrangement of the island-like second conductor patterns 15, and the material of the mother board 13. The inductance component is controlled by the material of the mother board 13 and the material, length, and thickness of the through hole 18. The distance between the package wiring board 300 and the mother board 13 can be controlled by the shape of the connection member 111. By adjusting these, the band gap band of the EBG structure 20 can be adjusted.
　次に、本実施形態の作用及び効果について説明する。本実施形態においてＥＢＧ構造体２０はいわゆるマッシュルーム型のＥＢＧであり、その単位セル５０は、第４導体パターン１７、島状の第２導体パターン１５、スルーホール１８、樹脂１１２、シート状の第１導体パターン１４のうち島状の第２導体パターン１５に対向している領域により構成される。詳細には、第１導体パターン１４が上側の導体プレーンに相当し、第４導体パターン１７が下側の導体プレーンに相当する。またスルーホール１８がマッシュルームのインダクタンス部分に相当し、第２導体パターン１５がマッシュルームのヘッド部分に相当している。そして単位セル５０が繰返し、例えば周期的に配列されることにより、ＥＢＧ構造体２０が形成される。 Next, functions and effects of this embodiment will be described. In this embodiment, the EBG structure 20 is a so-called mushroom type EBG, and the unit cell 50 includes a fourth conductor pattern 17, an island-like second conductor pattern 15, a through hole 18, a resin 112, and a sheet-like first. The conductive pattern 14 is constituted by a region facing the island-shaped second conductive pattern 15. Specifically, the first conductor pattern 14 corresponds to the upper conductor plane, and the fourth conductor pattern 17 corresponds to the lower conductor plane. The through hole 18 corresponds to an inductance portion of the mushroom, and the second conductor pattern 15 corresponds to a head portion of the mushroom. The unit cells 50 are repeatedly arranged, for example, periodically, whereby the EBG structure 20 is formed.
　このような構成において、第２導体パターン１５と第１導体パターン１４の間で容量が形成されることにより、第４導体パターン１７と第１導体パターン１４の間をノイズが伝播することを抑制する。第２導体パターン１５はマザーボード１３に形成され、第１導体パターン１４はパッケージ配線基板３００に形成されている。このため、ＥＢＧ構造体２０はマザーボード１３とパッケージ配線基板３００の間の空間に形成されていることになる。従って、この空間内をノイズが伝播して外部に放射されることが抑制される。 In such a configuration, a capacitance is formed between the second conductor pattern 15 and the first conductor pattern 14, thereby suppressing noise propagation between the fourth conductor pattern 17 and the first conductor pattern 14. . The second conductor pattern 15 is formed on the mother board 13, and the first conductor pattern 14 is formed on the package wiring board 300. For this reason, the EBG structure 20 is formed in the space between the mother board 13 and the package wiring board 300. Therefore, noise is prevented from propagating through the space and radiated to the outside.
　このノイズの発生源としては、例えば接続部材１１１がある。接続部材１１１から放射されるノイズの周波数が、ＥＢＧ構造体２０のバンドギャップに含まれるようにＥＢＧ構造体２０を設計すると、接続部材１１１から放射されたノイズがパッケージ１２とマザーボード１３の間の空間から漏れることが抑制される。 As a source of this noise, for example, there is a connecting member 111. When the EBG structure 20 is designed so that the frequency of noise radiated from the connection member 111 is included in the band gap of the EBG structure 20, the noise radiated from the connection member 111 is a space between the package 12 and the motherboard 13. Leaking from is suppressed.
　また本実施形態では、第１導体パターン１４はパッケージ配線基板３００のうちマザーボード１３に対向する面３０２に形成されている。このため、第１導体パターン１４と第２導体パターン１５の距離を狭くして、ＥＢＧ構造体２０の容量成分を大きくすることができる。特に本実施形態では、第２導体パターン１５もマザーボード１３のうちパッケージ配線基板３００に対向する面２０２に形成されているため、第１導体パターン１４と第２導体パターン１５の距離をさらに狭くして、ＥＢＧ構造体２０の容量成分をさらに大きくすることができる。 In the present embodiment, the first conductor pattern 14 is formed on the surface 302 of the package wiring board 300 that faces the mother board 13. For this reason, the distance between the first conductor pattern 14 and the second conductor pattern 15 can be reduced, and the capacitance component of the EBG structure 20 can be increased. In particular, in the present embodiment, since the second conductor pattern 15 is also formed on the surface 202 of the mother board 13 facing the package wiring board 300, the distance between the first conductor pattern 14 and the second conductor pattern 15 is further reduced. The capacitance component of the EBG structure 20 can be further increased.
　さらに、本実施形態では、第１導体パターン１４と第２導体パターン１５の間に挿入される樹脂１１２の材料特性を調節することで容量成分を制御することができる。樹脂１１２は、パッケージ１２をマザーボード１３上に組み立て後に、両者の間に挿入するものである。パッケージ１２をマザーボード１３上に組み立て後においても、挿入する樹脂の材料特性を調節することで、ＥＢＧ構造体２０の周波数特性を制御することができる。 Furthermore, in this embodiment, the capacitance component can be controlled by adjusting the material characteristics of the resin 112 inserted between the first conductor pattern 14 and the second conductor pattern 15. The resin 112 is inserted between the package 12 and the mother board 13 after assembling. Even after the package 12 is assembled on the mother board 13, the frequency characteristics of the EBG structure 20 can be controlled by adjusting the material characteristics of the resin to be inserted.
　また「繰り返し」単位セル５０を配置する場合、互いに隣り合う単位セル５０において、同一のビアや接続部材の間隔（中心間距離）が、ノイズとして想定している電磁波の波長λの１／２以内となるようにするのが好ましい。また「繰り返し」には、いずれかの単位セル５０において構成の一部が欠落している場合も含まれる。また単位セル５０が２次元配列を有している場合には、「繰り返し」には単位セル５０が部分的に欠落している場合も含まれる。また「周期的」には、一部の単位セル５０において構成要素の一部がずれている場合や、一部の単位セル５０そのものの配置がずれている場合も含まれる。すなわち厳密な意味での周期性が崩れた場合においても、単位セル５０が繰り返し配置されている場合には、メタマテリアルとしての特性を得ることができるため、「周期性」にはある程度の欠陥が許容される。なおこれらの欠陥が生じる要因としては、単位セル間に配線やビア、接続部材を通す場合、既存の配線レイアウトや基板間接続構造にメタマテリアル構造を追加する場合において既存のビアやパターン、接続部材によって単位セルが配置できない場合、製造誤差、及び既存のビアやパターン、接続部材を単位セルの一部として用いる場合などが考えられる。 When “repetitive” unit cells 50 are arranged, in the unit cells 50 adjacent to each other, the interval between the same vias and connection members (center-to-center distance) is within ½ of the wavelength λ of the electromagnetic wave assumed as noise. It is preferable that In addition, “repetition” includes a case where a part of the configuration is missing in any unit cell 50. When the unit cell 50 has a two-dimensional array, “repetition” includes a case where the unit cell 50 is partially missing. Further, “periodic” includes a case where some of the constituent elements are deviated in some unit cells 50 and a case where the arrangement of some unit cells 50 themselves is deviated. In other words, even when the periodicity in the strict sense collapses, if the unit cells 50 are repeatedly arranged, the characteristics as a metamaterial can be obtained, so that “periodicity” has a certain amount of defects. Permissible. The cause of these defects is that when wiring, vias, and connection members are passed between unit cells, or when a metamaterial structure is added to the existing wiring layout or inter-board connection structure, existing vias, patterns, or connection members When the unit cell cannot be arranged due to the above, there may be a manufacturing error and a case where an existing via, pattern, or connection member is used as a part of the unit cell.
　図２（ａ）は、第２の実施形態に係る電子装置の構成を示す断面図である。図２（ｂ）は、図２（ａ）のＡ－Ａ´断面から下を見た図であり、マザーボード１３の表面の構成を示している。図２（ｃ）は、図２（ａ）のＡ－Ａ´断面から上を見た図であり、パッケージ配線基板３００の表面の構成を示している。この電子装置は、以下の点を除いて、第１の実施形態に係る電子装置と同様の構成である。 FIG. 2A is a cross-sectional view showing the configuration of the electronic device according to the second embodiment. FIG. 2B is a bottom view of the AA ′ cross section of FIG. 2A and shows the configuration of the surface of the mother board 13. FIG. 2C is a top view of the AA ′ cross section of FIG. 2A and shows the configuration of the surface of the package wiring board 300. This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
　まず、第２導体パターン１５及び外部接続端子２２０は同一の格子を構成するように配置されている。すなわち第２導体パターン１５の配置周期と外部接続端子２２０の配置周期は同一であり、かつ最も外部接続端子２２０に近い第２導体パターン１５と外部接続端子２２０の間隔は、外部接続端子２２０の相互間隔に等しい。第２導体パターン１５は外部接続端子２２０と平面形状が同じであり、例えば正方形である。 First, the second conductor pattern 15 and the external connection terminal 220 are arranged to constitute the same lattice. That is, the arrangement period of the second conductor pattern 15 and the arrangement period of the external connection terminal 220 are the same, and the distance between the second conductor pattern 15 and the external connection terminal 220 closest to the external connection terminal 220 is the mutual interval of the external connection terminals 220. Equal to the interval. The second conductor pattern 15 has the same planar shape as the external connection terminal 220, and is, for example, a square.
　また、パッケージ配線基板３００とマザーボード１３の間に樹脂１１２が挿入されていない。なお、本実施形態において樹脂１１２を加えることも可能である。 Further, the resin 112 is not inserted between the package wiring board 300 and the mother board 13. In this embodiment, the resin 112 can be added.
　本実施形態によっても、第１の実施形態と同様の効果を得ることができる。 Also in this embodiment, the same effect as that of the first embodiment can be obtained.
　図３（ａ）は、第３の実施形態に係る電子装置の構成を示す断面図である。図３（ｂ）は、図３（ａ）のＡ－Ａ´断面から下を見た図であり、マザーボード１３の表面の構成を示している。図３（ｃ）は、図３（ａ）のＡ－Ａ´断面から上を見た図であり、パッケージ配線基板３００の表面の構成を示している。この電子装置は、以下の点を除いて、第１の実施形態に係る電子装置と同様の構成である。 FIG. 3A is a cross-sectional view showing a configuration of an electronic device according to the third embodiment. FIG. 3B is a bottom view of the AA ′ cross section of FIG. 3A and shows the configuration of the surface of the mother board 13. FIG. 3C is a top view of the AA ′ cross section of FIG. 3A and shows the configuration of the surface of the package wiring board 300. This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
　本図に示す例では、半導体チップ１０は、ボンディングワイヤー１１を用いてパッケージ配線基板３００上に搭載されている。第１導体パターン１４は互いに離間している複数の島状の導体パターンであり、第２導体パターン１５はシート状の導体パターンである。 In the example shown in the figure, the semiconductor chip 10 is mounted on the package wiring board 300 using the bonding wires 11. The first conductor pattern 14 is a plurality of island-like conductor patterns that are separated from each other, and the second conductor pattern 15 is a sheet-like conductor pattern.
　またマザーボード１３は、第２導体パターン１５の一つ下の配線層に、第４導体パターン１７を有している。第４導体パターン１７は、グラウンドプレーン及び電源プレーンの一方、例えばグラウンドプレーンである。 The mother board 13 has a fourth conductor pattern 17 in the wiring layer immediately below the second conductor pattern 15. The fourth conductor pattern 17 is one of a ground plane and a power plane, for example, a ground plane.
　第１導体パターン１４及び外部接続端子３２０は同一の格子を構成するように配置されている。すなわち第１導体パターン１４の配置周期と外部接続端子３２０の配置周期は同一であり、かつ最も外部接続端子３２０に近い第１導体パターン１４と外部接続端子３２０の間隔は、外部接続端子３２０の相互間隔に等しい。第１導体パターン１４は外部接続端子３２０と平面形状が同じであり、例えば正方形である。ただし、第１導体パターン１４及び外部接続端子３２０は、互いに異なる格子を形成するように配置されていても良い。 The first conductor pattern 14 and the external connection terminal 320 are arranged to constitute the same lattice. That is, the arrangement cycle of the first conductor pattern 14 and the arrangement cycle of the external connection terminal 320 are the same, and the distance between the first conductor pattern 14 and the external connection terminal 320 closest to the external connection terminal 320 is the mutual interval of the external connection terminals 320. Equal to the interval. The first conductor pattern 14 has the same planar shape as the external connection terminal 320, and is, for example, a square. However, the first conductor pattern 14 and the external connection terminal 320 may be arranged to form different grids.
　接続部材１１１はハンダボールであり、パッケージ配線基板３００の外部接続端子３２０とマザーボード１３の外部接続端子２２０間を電気的に接続している。パッケージ配線基板３００とマザーボード１３が接続部材１１１により接続された周辺は、樹脂１１６で固められ、さらにその外周は樹脂１１７で固められている。すなわち第１導体パターン１４と第２導体パターン１５の間の空間には、樹脂１１６が充填されている領域と、樹脂１１７が充填されている領域がある。樹脂１１６と樹脂１１７は、異なる材料特性を備える。 The connection member 111 is a solder ball, and electrically connects the external connection terminal 320 of the package wiring board 300 and the external connection terminal 220 of the motherboard 13. The periphery where the package wiring board 300 and the mother board 13 are connected by the connecting member 111 is solidified by the resin 116, and the outer periphery thereof is solidified by the resin 117. In other words, the space between the first conductor pattern 14 and the second conductor pattern 15 includes a region filled with the resin 116 and a region filled with the resin 117. Resin 116 and resin 117 have different material properties.
　パッケージ配線基板３００及びマザーボード１３はそれぞれ多層配線基板であり、誘電層及び導体層を交互に積層することにより形成されている。そしてパッケージ配線基板３００に形成された島状の第１導体パターン１４は、パッケージ配線基板３００の多層配線（第１導体パターン１４より一層内側の第３導体パターン１６を含む）及びビア、並びに外部接続端子３２０、接続部材１１１、及び外部接続端子２２０を介して、マザーボード１３の電源プレーン及びグラウンドプレーンのうち、上記した第４導体パターン１７とは逆の種類、例えば電源プレーンに接続している。ただし第１導体パターン１４は、マザーボード１３の電源プレーン及びグラウンドプレーンのうち、上記した第４導体パターン１７が接続しているプレーンと同じ種類のプレーンに接続しても良い。またパッケージ配線基板３００に形成された第１導体パターン１４は、スルーホール１９を介して第３導体パターン１６に接続している。スルーホール１９は、第１導体パターン１４の平面形状において任意の位置に形成され、第１導体パターン１４の中心に形成する必要は無い。 The package wiring board 300 and the mother board 13 are multilayer wiring boards, and are formed by alternately laminating dielectric layers and conductor layers. The island-shaped first conductor pattern 14 formed on the package wiring board 300 includes the multilayer wiring (including the third conductor pattern 16 on the inner side of the first conductor pattern 14) and vias of the package wiring board 300, and external connection. Of the power plane and ground plane of the mother board 13, the terminal 320, the connecting member 111, and the external connection terminal 220 are connected to the opposite type of the fourth conductor pattern 17, for example, the power plane. However, the first conductor pattern 14 may be connected to a plane of the same type as the plane to which the above-described fourth conductor pattern 17 is connected among the power plane and the ground plane of the motherboard 13. The first conductor pattern 14 formed on the package wiring board 300 is connected to the third conductor pattern 16 through the through hole 19. The through hole 19 is formed at an arbitrary position in the planar shape of the first conductor pattern 14, and does not need to be formed at the center of the first conductor pattern 14.
　ＥＢＧ構造体２０は、パッケージ配線基板３００とマザーボード１３の間隔、樹脂１１６及び樹脂１１７、並びに島状の第１導体パターン１４の大きさ、配列、パッケージ配線基板３００の材料によって各容量の大きさが制御され、パッケージ配線基板３００の材料、スルーホール１９の材料、長さ、及び太さによってインダクタンス成分が制御される。パッケージ配線基板３００とマザーボード１３の間隔は、接続部材１１１の形状によって制御することができる。これらを調節することにより、ＥＢＧ構造体２０のバンドギャップ帯を調節することができる。 The size of each capacitor of the EBG structure 20 depends on the distance between the package wiring board 300 and the mother board 13, the size and arrangement of the resin 116 and the resin 117, and the island-shaped first conductor pattern 14, and the material of the package wiring board 300. The inductance component is controlled by the material of the package wiring board 300 and the material, length, and thickness of the through hole 19. The distance between the package wiring board 300 and the mother board 13 can be controlled by the shape of the connection member 111. By adjusting these, the band gap band of the EBG structure 20 can be adjusted.
　また、ＥＢＧ構造体２０は、外部接続端子２２０，３２０及び接続部材１１１を２重構造で取り囲むように形成されている。本実施の形態では、外部接続端子２２０，３２０及び接続部材１１１の周りを取り囲むＥＢＧ構造体２１と、さらにその周辺を取り囲むＥＢＧ構造体２２が形成されている。 The EBG structure 20 is formed so as to surround the external connection terminals 220 and 320 and the connection member 111 with a double structure. In the present embodiment, an EBG structure 21 surrounding the external connection terminals 220 and 320 and the connection member 111 and an EBG structure 22 surrounding the periphery thereof are formed.
　本実施形態の作用及び効果について説明する。本実施形態においてＥＢＧ構造体２１はいわゆるマッシュルーム型のＥＢＧであり、単位セル５０を有している。またＥＢＧ構造体２２も、いわゆるマッシュルーム型のＥＢＧであり、単位セル５１を有している。単位セル５０，５１は、いずれも、第３導体パターン１６、島状の第１導体パターン１４、スルーホール１９、シート状の第２導体パターン１５のうち島状の第１導体パターン１４に対向している領域により構成される。詳細には、第２導体パターン１５が上側の導体プレーンに相当し、第３導体パターン１６が下側の導体プレーンに相当する。またスルーホール１９がマッシュルームのインダクタンス部分に相当し、第１導体パターン１４がマッシュルームのヘッド部分に相当している。そして単位セル５０が繰返し、例えば周期的に配列されることにより、ＥＢＧ構造体２１が形成され、単位セル５１が繰返し、例えば周期的に配列されることにより、ＥＢＧ構造体２２が形成される。単位セル５０と単位セル５１の特性の差は、樹脂１１６の特性と樹脂１１７の特性の差に起因して現れる。 The operation and effect of this embodiment will be described. In the present embodiment, the EBG structure 21 is a so-called mushroom type EBG, and has a unit cell 50. The EBG structure 22 is also a so-called mushroom type EBG, and includes a unit cell 51. The unit cells 50 and 51 are opposed to the island-like first conductor pattern 14 among the third conductor pattern 16, the island-like first conductor pattern 14, the through hole 19, and the sheet-like second conductor pattern 15. It is constituted by the area that is. Specifically, the second conductor pattern 15 corresponds to the upper conductor plane, and the third conductor pattern 16 corresponds to the lower conductor plane. The through hole 19 corresponds to an inductance portion of the mushroom, and the first conductor pattern 14 corresponds to a head portion of the mushroom. The unit cells 50 are repeatedly arranged, for example, periodically to form the EBG structure 21, and the unit cells 51 are repeatedly arranged, for example, to periodically form the EBG structure 22. A difference in characteristics between the unit cell 50 and the unit cell 51 appears due to a difference in characteristics between the resin 116 and the resin 117.
　このため、本実施形態によっても、第１の実施形態と同様の効果を得ることができる。また、樹脂１１６の特性と樹脂１１７の誘電率を異ならせることにより、単位セル５０，５１の容量成分を互いに異ならせることができる。このため、ＥＢＧ構造体２１のバンドギャップ帯域と、ＥＢＧ構造体２２のバンドギャップ帯域を互いに異ならせることができる。従って、互いに異なる複数の周波数帯のノイズを抑制することが可能になる。また、樹脂１１６，１１７は、パッケージ１２をマザーボード１３上に組み立てた後に、これらの間に挿入できるため、パッケージ１２をマザーボード１３上に組み立て後においても、ＥＢＧ構造体２０の周波数特性を制御することができる。 For this reason, the same effect as that of the first embodiment can be obtained also by this embodiment. Further, by making the characteristics of the resin 116 different from the dielectric constant of the resin 117, the capacity components of the unit cells 50 and 51 can be made different from each other. For this reason, the band gap band of the EBG structure 21 and the band gap band of the EBG structure 22 can be made different from each other. Therefore, it is possible to suppress noise in a plurality of different frequency bands. Further, since the resins 116 and 117 can be inserted between the package 12 and the motherboard 13 after being assembled, the frequency characteristics of the EBG structure 20 can be controlled even after the package 12 is assembled on the motherboard 13. Can do.
　図４（ａ）は、第４の実施形態に係る電子装置の構成を示す断面図である。図４（ｂ）は、図４（ａ）のＡ－Ａ´断面から下を見た図であり、マザーボード１３の表面の構成を示している。図４（ｃ）は、図４（ａ）のＡ－Ａ´断面から上を見た図であり、パッケージ配線基板３００の表面の構成を示している。この電子装置は、以下の点を除いて、第３の実施形態に係る電子装置と同様の構成である。 FIG. 4A is a cross-sectional view showing a configuration of an electronic device according to the fourth embodiment. FIG. 4B is a bottom view of the AA ′ cross section of FIG. 4A and shows the configuration of the surface of the mother board 13. FIG. 4C is a top view of the AA ′ cross section of FIG. 4A and shows the configuration of the surface of the package wiring board 300. This electronic device has the same configuration as the electronic device according to the third embodiment except for the following points.
　まず、第１導体パターン１４及び外部接続端子２２０の配置周期が異なっている。第１導体パターン１４内においても、島状の平面形状の大きさ、及び配置周期が異なっている。 First, the arrangement periods of the first conductor pattern 14 and the external connection terminal 220 are different. Even in the first conductor pattern 14, the size of the island-like planar shape and the arrangement period are different.
　また、パッケージ配線基板３００とマザーボード１３の間に挿入する樹脂１１２は、一種類としている。 Further, the resin 112 inserted between the package wiring board 300 and the mother board 13 is one kind.
本実施形態によっても、第３の実施形態と同様の効果を得ることができる。つまり、異なる大きさの第１導体パターン１４を多重に配置することで、封止用樹脂として複数種類の樹脂を用いなくても、互いに異なる特性のＥＢＧ構造体２１，２２の単位セル５０，５１を形成できる。これにより、複数の異なる周波数帯のノイズを抑制することが可能になる。 According to this embodiment, the same effect as that of the third embodiment can be obtained. That is, by arranging multiple first conductor patterns 14 of different sizes, the unit cells 50 and 51 of the EBG structures 21 and 22 having different characteristics can be used without using a plurality of types of resins as the sealing resin. Can be formed. This makes it possible to suppress noise in a plurality of different frequency bands.
　図５（ａ）は、第５の実施形態に係る電子装置の構成を示す断面図である。図５（ｂ）は、図５（ａ）のＡ－Ａ´断面から下を見た図であり、マザーボード１３の表面の構成を示している。図５（ｃ）は、図５（ａ）のＡ－Ａ´断面から上を見た図であり、パッケージ配線基板３００の表面の構成を示している。この電子装置は、以下の点を除いて、第３の実施形態に係る電子装置と同様の構成である。 FIG. 5A is a cross-sectional view showing a configuration of an electronic device according to the fifth embodiment. FIG. 5B is a bottom view of the AA ′ cross section of FIG. 5A and shows the configuration of the surface of the mother board 13. FIG. 5C is a top view of the AA ′ cross section of FIG. 5A, and shows the configuration of the surface of the package wiring board 300. FIG. This electronic device has the same configuration as the electronic device according to the third embodiment except for the following points.
　まず、第１導体パターン１４が、島状の平面形状ではなくスタブ（stub）で形成されている。本図に示す例において、第１導体パターン１４は、オープンスタブであるが、ショートスタブであっても良い。 First, the first conductor pattern 14 is formed of a stub instead of an island-like planar shape. In the example shown in the figure, the first conductor pattern 14 is an open stub, but may be a short stub.
　また、パッケージ配線基板３００とマザーボード１３の間に挿入する樹脂１１２は、一種類としている。 Further, the resin 112 inserted between the package wiring board 300 and the mother board 13 is one kind.
　本実施形態によっても、第３の実施形態と同様の効果を得ることができる。さらに第１導体パターン１４をスタブで形成しており、よりＥＢＧ構造体２０の単位セル５０の特性を得る設計自由度を向上することができる。 Also according to this embodiment, the same effect as that of the third embodiment can be obtained. Further, the first conductor pattern 14 is formed of a stub, and the degree of freedom in designing to obtain the characteristics of the unit cell 50 of the EBG structure 20 can be improved.
　図６（ａ）は、第６の実施形態に係る電子装置の構成を示す断面図である。図６（ｂ）は、図６（ａ）のＡ－Ａ´断面から下を見た図であり、マザーボード１３の表面の構成を示している。図６（ｃ）は、図６（ａ）のＡ－Ａ´断面から上を見た図であり、パッケージ配線基板３００の表面の構成を示している。この電子装置は、以下の点を除いて、第１の実施形態に係る電子装置と同様の構成である。 FIG. 6A is a cross-sectional view showing the configuration of the electronic device according to the sixth embodiment. FIG. 6B is a bottom view of the AA ′ cross section of FIG. 6A and shows the configuration of the surface of the mother board 13. FIG. 6C is a top view of the AA ′ cross section of FIG. 6A and shows the configuration of the surface of the package wiring board 300. This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
　まず、マザーボード１３に形成された第２導体パターン１５は、互いに離間している複数の島状の導体パターンになっている。パッケージ配線基板３００は、半導体チップを搭載していない。パッケージ配線基板３００は、第１導体パターン１４を有している。 First, the second conductor pattern 15 formed on the mother board 13 is a plurality of island-shaped conductor patterns spaced apart from each other. The package wiring board 300 is not mounted with a semiconductor chip. The package wiring board 300 has the first conductor pattern 14.
　第１導体パターン１４は、接続部材１１１、マザーボード１３側の外部接続層５０２、マザーボード１３内のスルーホール１８を介して、マザーボード１３の導体パターン５０１に接続している。導体パターン５０１は、電源プレーン又はグラウンドプレーン、例えばグラウンドプレーンに接続している。外部接続層５０２、および第１導体パターン１４はシート状のパターンで、その上には、２つのハンダ端子が形成される構造である。 The first conductor pattern 14 is connected to the conductor pattern 501 of the motherboard 13 through the connection member 111, the external connection layer 502 on the motherboard 13 side, and the through hole 18 in the motherboard 13. The conductor pattern 501 is connected to a power plane or a ground plane, for example, a ground plane. The external connection layer 502 and the first conductor pattern 14 are sheet-like patterns on which two solder terminals are formed.
　本実施形態において第２導体パターン１５は、マザーボード１３に形成されたスルーホール１８を介して、マザーボード１３の内部配線層に位置している第４導体パターン１７に接続している。第４導体パターン１７は、電源プレーン及びグラウンドプレーンのうち上記した導体パターン５０１が接続していないプレーンと同じ種類のプレーン、例えば電源プレーンである。ただし第４導体パターン１７は、電源プレーン及びグラウンドプレーンのうち導体パターン５０１が接続しているプレーンと同じ種類のプレーンであっても良い。 In the present embodiment, the second conductor pattern 15 is connected to the fourth conductor pattern 17 located in the internal wiring layer of the motherboard 13 through the through hole 18 formed in the motherboard 13. The fourth conductor pattern 17 is the same type of plane as the plane to which the above-described conductor pattern 501 is not connected among the power plane and the ground plane, for example, the power plane. However, the fourth conductor pattern 17 may be the same type of plane as the plane to which the conductor pattern 501 is connected among the power plane and the ground plane.
　本実施形態においてＥＢＧ構造体２０の単位セル５０は、第２導体パターン１５、スルーホール１８、樹脂１１２、第１導体パターン１４のうち第２導体パターン１５に対向している領域により構成される。詳細には、第４導体パターン１７が下側の導体プレーンに相当し、第１導体パターン１４が上側の導体プレーンに相当する。またスルーホール１８がマッシュルームのインダクタンス部分に相当し、第２導体パターン１５がマッシュルームのヘッド部分に相当している。 In this embodiment, the unit cell 50 of the EBG structure 20 is configured by a region of the second conductor pattern 15, the through hole 18, the resin 112, and the first conductor pattern 14 facing the second conductor pattern 15. Specifically, the fourth conductor pattern 17 corresponds to the lower conductor plane, and the first conductor pattern 14 corresponds to the upper conductor plane. The through hole 18 corresponds to an inductance portion of the mushroom, and the second conductor pattern 15 corresponds to a head portion of the mushroom.
　本実施形態によっても、第１の実施形態と同様の効果を得ることができる。さらにパッケージ配線基板３００は、半導体チップを搭載していないため、パッケージ配線基板３００単体をノイズ抑制用部品として取り扱うことができる。マザーボード１３から発生するノイズを抑制するために、パッケージ配線基板３００をマザーボード１３上の所定の箇所に搭載することができるという効果がある。パッケージ配線基板３００を複数個並べてマザーボード１３上に搭載することも可能である。 Also in this embodiment, the same effect as that of the first embodiment can be obtained. Further, since the package wiring board 300 is not mounted with a semiconductor chip, the package wiring board 300 can be handled as a noise suppression component. In order to suppress noise generated from the mother board 13, there is an effect that the package wiring board 300 can be mounted at a predetermined location on the mother board 13. It is also possible to mount a plurality of package wiring boards 300 on the mother board 13 side by side.
　なお、第２導体パターン１５は、島状の平面形状ではなく、第５の実施形態で示したようにスタブで形成してもよい。この場合は、ＥＢＧ構造体２０の単位セル５０のインダクタ成分、容量成分の制御範囲が拡大できる。なお、本実施例では、パッケージ配線基板３００とマザーボード１３との接続端子は、２箇所で、島状の第２導体パターン１５も２箇所のマトリックスの場合を示したが、これに限定される必要はない。例えば、接続部材１１１と島状の第２導体パターン１５は一対でも良く、またさらに多くのマトリックスを形成しても良く、任意の配列に組み上げることが可能である。また、構成するＥＢＧ構造はマッシュルーム構造の場合を示したが、これにとらわれることなく任意のＥＢＧ構造を適用することが可能である。 Note that the second conductor pattern 15 may be formed of a stub as shown in the fifth embodiment instead of the island-like planar shape. In this case, the control range of the inductor component and the capacitance component of the unit cell 50 of the EBG structure 20 can be expanded. In the present embodiment, the connection terminals between the package wiring board 300 and the mother board 13 are two places, and the island-like second conductor pattern 15 is also a matrix of two places. However, the present invention is not limited to this. There is no. For example, the connection member 111 and the island-shaped second conductor pattern 15 may be a pair, or may form more matrices, and can be assembled in an arbitrary arrangement. Moreover, although the case where the EBG structure to comprise was a mushroom structure was shown, it is possible to apply arbitrary EBG structures, without being restricted by this.
　図７（ａ）は、第７の実施形態に係る電子装置の構成を示す断面図である。図７（ａ）は、図７（ｂ）のＢ－Ｂ´断面図であり、図７（ｂ）は、図７（ａ）のＡ－Ａ´断面から下を見た図であり、マザーボード１３の表面の構成を示している。図７（ｃ）は、図７（ａ）のＡ－Ａ´断面から上を見た図であり、パッケージ配線基板３００の表面の構成を示している。この電子装置は、以下の点を除いて、第２の実施形態に係る電子装置と同様の構成である。 FIG. 7A is a cross-sectional view showing the configuration of the electronic device according to the seventh embodiment. 7A is a cross-sectional view taken along the line BB ′ of FIG. 7B, and FIG. 7B is a view looking down from the cross-section AA ′ of FIG. The structure of 13 surfaces is shown. FIG. 7C is a top view of the AA ′ cross section of FIG. 7A and shows the configuration of the surface of the package wiring board 300. This electronic device has the same configuration as the electronic device according to the second embodiment except for the following points.
　本実施形態において、ＥＢＧ構造体２０は、外部接続端子２２０，３２０及び接続部材１１１を取り囲んではいない。その代わり、ＥＢＧ構造体２０を構成する単位セル５０と接続部材１１１が、互いに入り乱れて配置されている。第１導体パターン１４は、外部接続端子３２０が配置される部分に開口部６０３を備えている。開口部６０３を設けることにより、ＥＢＧ構造体２０と接続部材１１１とが短絡することを防止できる。これにより、単位セル５０と接続部材１１１とを、任意の位置に配置することができる。 In the present embodiment, the EBG structure 20 does not surround the external connection terminals 220 and 320 and the connection member 111. Instead, the unit cell 50 and the connecting member 111 constituting the EBG structure 20 are arranged in a confused manner. The first conductor pattern 14 includes an opening 603 in a portion where the external connection terminal 320 is disposed. By providing the opening 603, it is possible to prevent the EBG structure 20 and the connection member 111 from being short-circuited. Thereby, the unit cell 50 and the connection member 111 can be arrange | positioned in arbitrary positions.
　本実施形態によっても、第２の実施形態と同様の効果を得ることができる。さらに、外部接続端子２２０，３２０とＥＢＧの単位セル５０を混在させて配置することが可能なため、パッケージ１３の外部接続端子３２０、及びマザーボード１３の外部接続端子２２０のピンアサインの設計自由度を向上することができる。 Also in this embodiment, the same effect as that of the second embodiment can be obtained. Furthermore, since the external connection terminals 220 and 320 and the EBG unit cell 50 can be mixed and arranged, the degree of freedom in designing the pin assignment of the external connection terminal 320 of the package 13 and the external connection terminal 220 of the motherboard 13 is increased. Can be improved.
　以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。例えば上記した各実施形態において、第１導体パターン１４をパッケージ配線基板３００のうちマザーボード１３に対向している面３０２に形成したが、パッケージ配線基板３００の内部配線層に第１導体パターン１４を形成しても良い。また第２導体パターン１５をマザーボード１３のうちパッケージ配線基板３００に対向している面２０２に形成したが、マザーボード１３の内部配線層に第２導体パターン１５を形成しても良い。 As described above, the embodiments of the present invention have been described with reference to the drawings. However, these are exemplifications of the present invention, and various configurations other than the above can be adopted. For example, in each of the embodiments described above, the first conductor pattern 14 is formed on the surface 302 of the package wiring board 300 that faces the mother board 13, but the first conductor pattern 14 is formed on the internal wiring layer of the package wiring board 300. You may do it. In addition, the second conductor pattern 15 is formed on the surface 202 of the mother board 13 facing the package wiring board 300, but the second conductor pattern 15 may be formed on the internal wiring layer of the mother board 13.
　またＥＢＧ構造体２０，２１，２２の構成は上記した実施形態に限定されず、ＥＢＧとしての特性を示す任意の構造体をＥＢＧ構造体２０，２１，２２として適用することができる。 Further, the configuration of the EBG structures 20, 21, and 22 is not limited to the above-described embodiment, and any structure that exhibits characteristics as an EBG can be applied as the EBG structures 20, 21, and 22.
　また上記実施形態では、半導体チップをパッケージ配線基板に実装される電子素子として半導体チップを例示したが、半導体チップ以外の電気部品を用いても良い。またランドグリッドアレイで用いるランドのように、パッケージをボードに機械的に押し付けて電気的接続を得る構造に、上記した各実施形態に示した構造を適用しても良い。またＥＢＧ構造体２０の配置場所は上記した例に限定されない。 In the above embodiment, the semiconductor chip is exemplified as the electronic element mounted on the package wiring board. However, an electrical component other than the semiconductor chip may be used. Further, the structure shown in each of the above embodiments may be applied to a structure that obtains an electrical connection by mechanically pressing a package against a board, such as a land used in a land grid array. Further, the location of the EBG structure 20 is not limited to the above example.
　この出願は、２０１１年６月２８日に出願された日本出願特願２０１１－１４３０９７を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2011-143097 filed on June 28, 2011, the entire disclosure of which is incorporated herein.

Claims (10)

  1. 　第１配線基板と、
    　前記第１配線基板に接続している第２配線基板と、
    を備え、
    　前記第１配線基板は第１導体を有し、
    　前記第２配線基板は、前記第１導体と対向する領域に少なくとも一部が形成されている第２導体と、前記第２導体に接続している第３導体を有し、
    　前記第２導体を用いて、導体の繰り返し構造が形成されており、
    　前記第１配線基板と前記第２配線基板の間の空間のうち前記第１導体と前記第２導体とが重なっている領域には、前記第１配線基板と前記第２配線基板とを接続する部材が位置していない電子装置。     A first wiring board;
    A second wiring board connected to the first wiring board;
    With
    The first wiring board has a first conductor;
    The second wiring board has a second conductor at least partially formed in a region facing the first conductor, and a third conductor connected to the second conductor,
    A repeating structure of the conductor is formed using the second conductor,
    The first wiring board and the second wiring board are connected to an area where the first conductor and the second conductor overlap in a space between the first wiring board and the second wiring board. An electronic device in which no member is located.
  2. 　請求項１に記載の電子装置において、
    　前記第１配線基板のうち前記第２配線基板に対向する面に形成された第１外部接続端子と、
    　前記第２配線基板のうち前記第１配線基板に対向する面に形成された第２外部接続端子と、
    　前記第１外部接続端子と前記第２外部接続端子を接続する接続部材と、
    をさらに備え、
    　平面視において前記第１導体及び前記第２導体は、前記第１外部接続端子、前記第２外部接続端子、及び前記接続部材を取り囲むように形成されている電子装置。     The electronic device according to claim 1,
    A first external connection terminal formed on a surface of the first wiring board facing the second wiring board;
    A second external connection terminal formed on a surface of the second wiring board facing the first wiring board;
    A connection member connecting the first external connection terminal and the second external connection terminal;
    Further comprising
    The electronic device, wherein the first conductor and the second conductor are formed so as to surround the first external connection terminal, the second external connection terminal, and the connection member in plan view.
  3. 　請求項１又は２に記載の電子装置において、
    　前記第１導体は、前記第１配線基板のうち前記第２配線基板に対向する面に形成されている電子装置。     The electronic device according to claim 1 or 2,
    The first conductor is an electronic device formed on a surface of the first wiring board facing the second wiring board.
  4. 　請求項１～３のいずれか一つに記載の電子装置において、
    　前記第２導体は、前記第２配線基板のうち前記第１配線基板に対向する面に形成されている電子装置。     The electronic device according to any one of claims 1 to 3,
    The second conductor is an electronic device formed on a surface of the second wiring board facing the first wiring board.
  5. 　請求項１～４のいずれか一つに記載の電子装置において、
    　前記第１配線基板と前記第２配線基板の間の空間のうち、前記第１導体と前記第２導体が対向している領域を充填している樹脂を有する電子装置。     The electronic device according to any one of claims 1 to 4,
    An electronic device having a resin filling a region between the first wiring board and the second wiring board in which the first conductor and the second conductor are opposed to each other.
  6. 　請求項５に記載の電子装置において、
    　前記第１導体と前記第２導体が対向している領域は、第１の前記樹脂によって充填されている領域と、第２の前記樹脂によって充填されている領域を有している電子装置。     The electronic device according to claim 5.
    The area where the first conductor and the second conductor face each other includes an area filled with the first resin and an area filled with the second resin.
  7. 　請求項１～６のいずれか一つに記載の電子装置において、
    　前記第１導体及び前記第２導体は、ＥＢＧ（Electromagnetic Band Gap）構造の少なくとも一部を構成している電子装置。     The electronic device according to any one of claims 1 to 6,
    The electronic device in which the first conductor and the second conductor constitute at least a part of an EBG (Electromagnetic Band Gap) structure.
  8. 　請求項１～７のいずれか一つに記載の電子装置において、
    　前記第１配線基板又は前記第２配線基板上に実装された電子部品をさらに備える電子装置。     The electronic device according to any one of claims 1 to 7,
    An electronic device further comprising an electronic component mounted on the first wiring board or the second wiring board.
  9. 　請求項１～８のいずれか一つに記載の電子装置において、
    　前記第１導体及び前記第２導体の一方は、シート状の導体であり、
    　前記第１導体及び前記第２導体の他方は互いに離間している複数の島状の導体である電子装置。     The electronic device according to any one of claims 1 to 8,
    One of the first conductor and the second conductor is a sheet-like conductor,
    The electronic device, wherein the other of the first conductor and the second conductor is a plurality of island-shaped conductors separated from each other.
  10. 　電気部品が実装される第１配線基板に第１導体を設け、
    　前記第１配線基板及び前記電気部品が実装される第２配線基板のうち前記第１導体に対向する領域の少なくとも一部に、第２導体と、前記第２導体に接続している第３導体を設け、
    　前記第１導体及び前記第２導体の少なくとも一方に、繰り返し構造を持たせることにより、前記第１導体、前記第２導体、及び前記第３導体を用いて ＥＢＧ（Electromagnetic Band Gap）構造の少なくとも一部を形成して、前記第１配線基板と前記第２配線基板の間の空間においてノイズが伝播することを抑制するノイズ抑制方法。     Providing a first conductor on a first wiring board on which an electrical component is mounted;
    A second conductor and a third conductor connected to the second conductor in at least a part of a region facing the first conductor in the second wiring board on which the first wiring board and the electrical component are mounted. Provided,
    By providing at least one of the first conductor and the second conductor with a repetitive structure, at least one of an EBG (Electromagnetic Band Gap) structure using the first conductor, the second conductor, and the third conductor. A noise suppressing method for suppressing noise from being propagated in a space between the first wiring board and the second wiring board by forming a portion.
PCT/JP2012/002526 2011-06-28 2012-04-12 Electronic device and noise suppression method WO2013001692A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020040230A1 (en) * 2018-08-24 2020-02-27 京セラ株式会社 Structure, antenna, wireless communication module, and wireless communication device
WO2022019148A1 (en) * 2020-07-21 2022-01-27 ソニーセミコンダクタソリューションズ株式会社 Antenna device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245193A (en) * 2005-03-02 2006-09-14 Matsushita Electric Ind Co Ltd Board-to-board connector and mounting structure using board-to-board connector
JP2007531253A (en) * 2004-03-11 2007-11-01 レイセオン・カンパニー Electromagnetic bandgap structure to suppress electromagnetic coupling in microstrip and flip chip on circuit board applications
WO2009082003A1 (en) * 2007-12-26 2009-07-02 Nec Corporation Electromagnetic band gap element, and antenna and filter using the same
JP2011124503A (en) * 2009-12-14 2011-06-23 Nec Corp Electronic device, and noise suppression method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007531253A (en) * 2004-03-11 2007-11-01 レイセオン・カンパニー Electromagnetic bandgap structure to suppress electromagnetic coupling in microstrip and flip chip on circuit board applications
JP2006245193A (en) * 2005-03-02 2006-09-14 Matsushita Electric Ind Co Ltd Board-to-board connector and mounting structure using board-to-board connector
WO2009082003A1 (en) * 2007-12-26 2009-07-02 Nec Corporation Electromagnetic band gap element, and antenna and filter using the same
JP2011124503A (en) * 2009-12-14 2011-06-23 Nec Corp Electronic device, and noise suppression method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020040230A1 (en) * 2018-08-24 2020-02-27 京セラ株式会社 Structure, antenna, wireless communication module, and wireless communication device
WO2022019148A1 (en) * 2020-07-21 2022-01-27 ソニーセミコンダクタソリューションズ株式会社 Antenna device

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