WO2013001131A1 - Method and system for testing integrated radio-frequency circuits at the wafer level and the use thereof - Google Patents

Method and system for testing integrated radio-frequency circuits at the wafer level and the use thereof Download PDF

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Publication number
WO2013001131A1
WO2013001131A1 PCT/ES2012/070484 ES2012070484W WO2013001131A1 WO 2013001131 A1 WO2013001131 A1 WO 2013001131A1 ES 2012070484 W ES2012070484 W ES 2012070484W WO 2013001131 A1 WO2013001131 A1 WO 2013001131A1
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Prior art keywords
test
integrated circuits
sequence
integrated
integrated circuit
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PCT/ES2012/070484
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Spanish (es)
French (fr)
Inventor
José Luis HUERTAS DÍAZ
Manuel José BARRAGÁN ASIÁN
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Consejo Superior De Investigaciones Científicas (Csic)
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Publication of WO2013001131A1 publication Critical patent/WO2013001131A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/3025—Wireless interface with the DUT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the present invention refers to a method and a system for testing radiofrequency integrated circuits at the wafer level, that is, integrated circuits that are integrated precisely into electronic wafers. Furthermore, the present invention also relates to the use of said method and system.
  • the invention is based on exploiting the ability to establish wireless communications between the devices under test (DUT). Wafer level.
  • the objective of this test is to provide a fast and reliable method to identify defective transceivers.
  • Such a test method would greatly reduce the cost associated with the production test, since this early failure detection avoids running a significant fraction of traditional tests, saves packaging costs of the integrated circuit, and avoids the use of expensive test equipment.
  • RF dedicated the detection of a defective device can be used to activate specific test circuitry (internal self-test circuitry, or BIST in its English acronym) for diagnosis, and in addition the information obtained in the tests can be used to guide process optimization of manufacturing and to improve process performance.
  • testing an RF subsystem included in an on-chip (SoC) system represents a major challenge.
  • the difficulty is that each radiofrequency (RF) block has a specific set of specifications, which usually require specific test strategies for its measurement. It can be said that the RF test has inherited all the difficulties of the analog test, but adding the problem of handling very high frequency signals.
  • testing these systems means measuring a set of specifications functionally, while fault-based tests, very successful in the digital domain, are impossible to standardize in the field of radio frequency, since each circuit requires a specific fault model. Reducing the complexity and cost of the radiofrequency circuit test is still an open line of research.
  • loopback solutions consist of reinjecting the transmitter's output to the reception path inside the transceiver. This allows the transmitter D / A converter to load the receiver A / D converter, completing a completely digital test.
  • the loopback scheme involves disturbing the normal operation of the system: to accommodate the transmitter output to the receiver input it is necessary to disconnect some components of the transmitter from the signal path and / or introduce an attenuator to the receiver input.
  • KGD test solutions known-good-die
  • the invention consists of a method and a system for carrying out the test of integrated circuits that are part of electronic wafers and the use of the method and system.
  • the main objective of this invention is to provide a reliable and fast method to rule out defective integrated transceivers at the wafer level by establishing wireless links between different dice in the wafer, so that the signals necessary to test a particular transceiver are provided or read by another of the transceivers of the same wafer.
  • These wireless links allow a complete system level test of the transmission and reception functions for each device in the wafer, without the need for expensive RF test equipment to generate or read high frequency signals, and without disturbing normal operation. of the devices under test.
  • the reported invention reduces the costs associated with the production test, and the early detection of defective circuits avoids running a significant fraction of traditional tests. It also has the advantage of detecting failures at the wafer level, so that packaging costs are reduced, which usually represent approximately 25% of the total system cost.
  • test results can be mapped onto the wafer to obtain distributions of intra-wafer and inter-wafer failure. These distributions can be used to detect and correct systematic or non-systematic deviations from the process, or to guide other test strategies such as screening techniques.
  • Detection of a defective transceiver can also be used to activate internal test functions during transmission and reception operations. In this way, the defective internal blocks within the transceiver can be identified.
  • the method of testing of radio frequency integrated circuits at the wafer level object of the present invention makes use of a low frequency digital test equipment comprising at least two test needles.
  • the Two needles which we will call as the first test needle and second test needle, are for sending and receiving sequences of test data that are exchanged between the test equipment and the integrated circuits of an electronic wafer.
  • at least one pair of integrated circuits of the electronic wafer will have been selected by a test head integrated in the test equipment.
  • the method comprises the following phases: i) sending from the first test needle a sequence of test data to a first integrated circuit of the at least one previously selected pair;
  • the method when comparing the data sequences sent and received by the test equipment in phases vi) and xii) of the first embodiment of the invention the sequence of test data is the same, the method comprises :
  • the method when comparing the data sequences sent and received by the test equipment in phases vi) and xii) of the first embodiment of the invention the sequence of test data is different, the method comprises:
  • each of the two integrated circuits forming the at least one pair of integrated circuits is paired with an integrated neighborhood circuit and the procedure described in the first embodiment of the invention is carried out.
  • the procedure described in the first embodiment of the invention is applied again and when comparing the data sequences in phases vi) and xii) the sequence of test data sent and received by the test equipment is the same, the procedure comprises:
  • the procedure described in the first embodiment of the invention is applied again and when when comparing the data sequences in phases vi) and xii) the sequence of test data sent and received by the test equipment is different, the procedure comprises:
  • the method comprises monitoring the operation of each module that integrates the integrated circuit by means of conventional test sensors integrated in the wafers.
  • each of the integrated circuits integrates a test antenna
  • the sending and receiving of the test data sequence of phases iii) and ix) is performed directly between the test antennas of the first and Second integrated circuit.
  • each of the integrated circuits does not integrate a test antenna
  • the sending and receiving of the test data sequence of phases iii) and ix) is performed by external test antennas positioned by the test head on the first and second integrated circuit.
  • the present invention also aims at a radio frequency integrated circuit testing system at the wafer level.
  • This system makes use of a low frequency digital test equipment that comprises at least two test needles, a first test needle and a second test needle for sending and receiving test data sequences between the test equipment. and the integrated circuits of a wafer and at least one electronic wafer composed of at least two integrated circuits. Additionally, the system at least comprises:
  • the transmission means of the test data streams between the integrated circuits comprise being selected between a test antenna integrated in each of the integrated circuits and an external antenna integrated in the test head for each One of the integrated circuits.
  • the test antennas and the test needles are both deposited by the test head over the circuits in their respective positions.
  • the system comprises integrated test sensors together with the integrated circuits under test to monitor the operation of the internal blocks of said circuits under test.
  • the present invention also contemplates the use of the device and method described above for obtaining erroneous integrated circuit distribution maps, the maps being selected between an inter-wafer fault map and an intra-wafer fault map.
  • erroneous integrated circuit distribution maps are also contemplated for the implementation of selected techniques among screening techniques and deviation detection techniques in the wafer manufacturing process. These erroneous integrated circuit distribution maps are useful for determining if there is any correlation between the position and the time of manufacture of a circuit in each wafer with the probability of failure of that circuit. If this exists correlation, screening techniques can be used to eliminate the probably defective circuits, and, in parallel, it is possible to look for the cause of deviation of the manufacturing process to correct it, thus increasing the performance of the process. If this correlation does not exist, the maps serve to monitor the performance of the process and its evolution over time, so they are useful for detecting deviations in the manufacturing process and trying to correct them.
  • a test at the integrated transceiver system level based on exploiting the capacity of wireless links established between the wafer-integrated circuits is described herein.
  • This RF test is carried out with low frequency digital test equipment.
  • the test antenna that enables the wireless link can be implemented on-chip or added to the head of the test equipment.
  • the described procedure allows the identification of defective transceivers integrated in complex on-chip systems at the production line level, before the chip packaging process.
  • the operation of the transceiver during the test is not different from its normal operation.
  • a mapping of the test results in distributions of inter-wafer and intra-wafer failure is carried out, allowing easy identification of defective chips without carrying out a complete test.
  • Circuit fault distributions can be used to guide other test strategies, such as screening techniques. Fault distributions are also used to detect deviations from the manufacturing process, whether systematic or non-systematic. Transceiver internal test functions may be included for diagnosis High frequency test signals are provided or read by another of the transceivers in the same wafer.
  • Figure 1. Shows the most general scheme of the invention in which the digital test equipment tests 3 pairs of integrated circuits in a wafer.
  • Figure 2. Shows a diagram of the test method object of the present invention applied to a pair of integrated circuits, in which both circuits comprise test antennas.
  • Figure 3. Shows a detailed block diagram of a pair of integrated circuits under test.
  • Figure 4. Shows examples of erroneous integrated circuit distribution maps in wafers.
  • Figure 1 represents a general outline of the proposed test strategy.
  • the wafer integrated circuits are grouped in pairs (1), and are digitally controlled by a low frequency digital test equipment (2).
  • the digital test equipment (2) has 3 pairs of test needles (3) each of the needle pairs (3) being in charge of exchanging the test sequence with each of the circuit pairs integrated (1).
  • the integrated circuits that make up the wafer have integrated test antennas to make wireless connections (4) between them.
  • Figure 2 shows a block diagram of the proposed test scheme for one of these couples under test, composed in the figure by the integrated circuits Die 1 (5) and Die 2 (6).
  • the digital test equipment (2) writes an optimized digital sequence to the REGI register (7).
  • This digital sequence is transmitted by the TI transceiver (8) (which incorporates a test antenna) and received by the T2 transceiver (9) (which also incorporates a test antenna).
  • the received signal is stored in the REG2 register (10) and compared to the original sequence to check the functionality of the transmission-reception functions.
  • the process is then reversed (T2 (9) transmits and TI (8) listens) to complete the test. If the sequence received is identical to the one sent, the functionality of both transceivers has been correct.
  • Multiple test pairs can be tested in parallel to speed up the process. The maximum number of test pairs is limited by the number of available transmission channels and by the number of test needles on the head of the digital test equipment.
  • Figure 3 shows the complete test scheme for a given couple under test in a wafer, including on-chip and external resources.
  • the operation of the system is no different from its normal operation, so very little circuitry has been added on-chip.
  • digital records (20,21) are required to store the test sequences, and test antennas (22,23) to perform wireless communication.
  • test antennas (22,23) can be integrated on-chip or added to the head of the test equipment.
  • the signal has to travel only a few millimeters (typical size of a dice) in a fixed direction (rows and / or wafer columns), which simplifies the implementation of the antenna.
  • the external digital test equipment (24) provides the power supply (29) and the reference clock (27) (low frequency) to the pairs of integrated circuits under test, sets the appropriate communication channel for each circuit (25,26) , and write / read the exchanged test sequences. Finally, the extracted information is stored in a conventional computer for processing.
  • the test head randomly selects a number of test pairs in the wafer.
  • the number of pairs under simultaneous tests is determined by the number of communication channels available and by the number of test needles available on the head of the test equipment.
  • Each pair has to transmit / receive on a different channel to avoid interference, and each circuit needs at least two needles for power (29), one for the low frequency reference clock (27) (necessary for the frequency synthesizer), and one for digital input / output (28) to load / read the test sequence and set the desired transmission / reception channel.
  • the structure of this digital sequence is:
  • test data N bits
  • Each pair of transceivers is tested at the system level.
  • One of the circuits transmits in a given channel while the other circuit of the couple receives on the same channel.
  • an optimized digital sequence is written to the REGi (20) register in the Die i (25) die. This sequence can contain all the significant transitions between symbols to test the wireless link (the number and definition of the symbols depends on the communications protocol implemented in the transceiver).
  • This test sequence is transmitted to die Die i + 1 (26).
  • the received sequence is stored in the REG i + 1 register (21).
  • the contents of the records are read by the digital test equipment (24) and compared to check the functionality of the transmission-reception system level.
  • the process is repeated in reverse, that is, the circuit Die i + 1 (26) transmits while Die i (25) receives. If the second comparison is also positive, then the circuits Die i (25) and Die i + 1 (26) are labeled as KGT, and their positions are stored in the wafer.
  • Step 2 Detect defective transceivers
  • each of the KGTs is wirelessly linked to one of the circuits not tested around it and the process described in "step 1" is repeated with the resulting pair. If the test fails, the circuit linked to the KGT is labeled as defective and its position is stored in the wafer. If the test is successful, the circuit linked to the KGT is labeled as KGT and can be used to test other dice in your neighborhood.
  • Step 3 Mapping and processing fault information
  • the process described in steps 1 and 2 continues until all the circuits integrated in the wafer have been tested Next, the process is repeated with the following wafers.
  • the obtained fault information can be mapped into intra-wafer and inter-wafer fault distributions.
  • a statistical analysis of these distributions to find correlations between the test result, the position in the wafer and the time of manufacture offers valuable information to detect and correct deviations in the manufacturing process.
  • Figure 4 shows examples of these distributions in the case of systematic and non-systematic deviations. Additionally, these maps can be used to guide other test strategies, such as screening techniques, which would provide better process performance.
  • Step 4 (optional): activate internal test structures in faulty circuits for diagnosis
  • the system-level test performed in steps 1 and 2 checks the functionality of the transmission and reception of data in the transceiver, but if the test fails, it does not provide information to identify which element in the transceiver is failing. Diagnostic functions can be added including on-chip test sensors to monitor the operation of each of the internal blocks shown in Figure 3. Multiple implementations for these sensors are well known in the state of the art.
  • the defective die can be linked to one of the KGTs to provide the necessary test stimulus, or read the response, while the digital output of the test sensors can be acquired with the external digital test equipment to diagnose the defective elements.

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  • Computer Networks & Wireless Communication (AREA)
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Abstract

The main objective of this invention is to provide a system and a reliable and rapid method for rejecting defective integrated transceivers at the wafer level by establishing wireless links between different circuits in the wafer such that the signals needed to test a particular transceiver are provided or read by another one of the transceivers in the same wafer. For this purpose, the system uses a low-frequency digital test apparatus which at least comprises two test needles for sending, receiving and comparing test data sequences which are interchanged between the test apparatus and the integrated circuits in the wafer.

Description

MÉTODO Y SISTEMA DE TESTADO DE CIRCUITOS INTEGRADOS DE RADIOFRECUENCIA A NIVEL DE OBLEA Y SU USO  METHOD AND TEST SYSTEM OF INTEGRATED RADIOFREQUENCY CIRCUITS AT THE LEVEL OF OBLEA AND ITS USE
OBJE TO DE LA INVENCIÓN OBJECT OF THE INVENTION
La presente invención, tal y como se expresa en el enunciado de esta memoria descriptiva se refiere a un método y un sistema de testado de circuitos integrados de radiofrecuencia a nivel de oblea, es decir, circuitos integrados que se integran precisamente en obleas electrónicas. Además la presente invención se refiere también al uso del mencionado método y sistema.  The present invention, as expressed in the statement of this specification refers to a method and a system for testing radiofrequency integrated circuits at the wafer level, that is, integrated circuits that are integrated precisely into electronic wafers. Furthermore, the present invention also relates to the use of said method and system.
La demanda creciente de sistemas on-chip con capacidad para comunicaciones inalámbricas ha llevado a un primer plano el problema de testar estos sistemas de manera eficiente. El test de sistemas de radiofrecuencia se ha realizado tradicionalmente mediante la verificación de especificaciones. Estos procedimientos son costosos en términos de recursos de test. Este invento intenta facilitar la identificación rápida de circuitos o transceptores integrados defectuosos, haciendo posible la identificación a nivel de oblea, y proporcionando además información que se puede usar para mejorar el rendimiento del proceso de fabricación. Las consideraciones económicas son sólo una de las ventajas ofrecidas por el invento presentado. Otras ventajas incluyen un aumento de la detección de fallos, un control mejorado del proceso de fabricación, capacidades diagnósticas, una reducción en la duración del ciclo de testado de un circuito integrado, y una simplificación del desarrollo de los programas de test.  The growing demand for on-chip systems with capacity for wireless communications has brought to the fore the problem of testing these systems efficiently. The radiofrequency system test has traditionally been performed by verifying specifications. These procedures are expensive in terms of test resources. This invention attempts to facilitate the rapid identification of defective integrated circuits or transceivers, making possible the identification at the wafer level, and also providing information that can be used to improve the performance of the manufacturing process. Economic considerations are only one of the advantages offered by the presented invention. Other advantages include an increase in the detection of failures, an improved control of the manufacturing process, diagnostic capabilities, a reduction in the duration of the testing cycle of an integrated circuit, and a simplification of the development of the test programs.
Asi pues, la invención se basa en explotar la capacidad de establecer comunicaciones inalámbricas entre los dispositivos bajo test (DUT, en sus siglas en inglés) a nivel de oblea. El objetivo de este test es proporcionar un método rápido y fiable para identificar transceptores defectuosos. Tal método de test reduciría en gran medida el coste asociado al test de producción, dado que esta detección temprana de fallos evita ejecutar una fracción importante de test tradicionales, ahorra costes de empaquetado del circuito integrado, y evita el uso de costosos equipos de test de RF dedicados. Adicionalmente, la detección de un dispositivo defectuoso se puede usar para activar circuitería de test específica (circuitería de autotest interno, o BIST en sus siglas inglesas) para diagnóstico, y además la información obtenida en los test se puede usar para guiar la optimización del proceso de fabricación y para mejorar el rendimiento del proceso. Thus, the invention is based on exploiting the ability to establish wireless communications between the devices under test (DUT). Wafer level. The objective of this test is to provide a fast and reliable method to identify defective transceivers. Such a test method would greatly reduce the cost associated with the production test, since this early failure detection avoids running a significant fraction of traditional tests, saves packaging costs of the integrated circuit, and avoids the use of expensive test equipment. RF dedicated. Additionally, the detection of a defective device can be used to activate specific test circuitry (internal self-test circuitry, or BIST in its English acronym) for diagnosis, and in addition the information obtained in the tests can be used to guide process optimization of manufacturing and to improve process performance.
ANTECEDENTES DE LA INVENCIÓN  BACKGROUND OF THE INVENTION
Actualmente, sistemas electrónicos completos muy complejos se integran en un solo circuito integrado. La mayor parte de estos sistemas es circuitería digital, que usualmente comprende procesadores multinúcleo, memorias, procesadores dedicados de señal, etc. Se pueden encontrar múltiples ejemplos en aplicaciones de consumo como teléfonos móviles, reproductores de DVD, reproductores multimedia, etc.  Currently, very complex complete electronic systems are integrated into a single integrated circuit. Most of these systems are digital circuitry, which usually includes multicore processors, memories, dedicated signal processors, etc. Multiple examples can be found in consumer applications such as mobile phones, DVD players, media players, etc.
Desde el punto de vista de un ingeniero de test, testar un subsistema de RF incluido en un sistema on-chip (SoC) representa un desafío importante. La dificultad está en que cada bloque de radiofrecuencia (RF) tiene un conjunto determinado de especificaciones, que usualmente requieren estrategias de test específicas para su medida. Se puede decir que el test de RF ha heredado todas las dificultades del test analógico, pero añadiendo el problema de manejar señales de muy alta frecuencia. Este marco de trabajo lleva al mismo problema fundamental para los tests analógicos y de RF: testar estos sistemas significa medir funcionalmente un conjunto de especificaciones, mientras que los tests basados en fallos, muy exitosos en el dominio digital, son imposibles de estandarizar en el campo de radiofrecuencia, dado que cada circuito requiere un modelo de fallo especifico. Reducir la complejidad y el coste del test de circuitos de radiofrecuencia es todavía una línea de investigación abierta. Trabajos recientes en esta área incluyen modelado de defectos y diagnóstico de fallos, altérnate test, Diseño para Test (DfT) y técnicas BIST, etc (M. J. Barragán, G. Huertas, A. Rueda, J. L. Huertas, " (Some) open problems to incorpórate BIST in complex heterogeneous itegrated systems" in Proceedings of the Fifth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2010, pp . 8-13) . From the point of view of a test engineer, testing an RF subsystem included in an on-chip (SoC) system represents a major challenge. The difficulty is that each radiofrequency (RF) block has a specific set of specifications, which usually require specific test strategies for its measurement. It can be said that the RF test has inherited all the difficulties of the analog test, but adding the problem of handling very high frequency signals. This The framework leads to the same fundamental problem for analog and RF tests: testing these systems means measuring a set of specifications functionally, while fault-based tests, very successful in the digital domain, are impossible to standardize in the field of radio frequency, since each circuit requires a specific fault model. Reducing the complexity and cost of the radiofrequency circuit test is still an open line of research. Recent work in this area includes defect modeling and fault diagnosis, test yourself, Test Design (DfT) and BIST techniques, etc. (MJ Barragan, G. Huertas, A. Rueda, JL Huertas, "(Some) open problems to incorporate BIST in complex heterogeneous itegrated systems "in Proceedings of the Fifth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2010, pp. 8-13).
Los métodos tradicionales para test de circuitos de RF están basados en especificaciones, es decir, comprueban que algunas o todas las características del sistema están de acuerdo con las especificaciones de diseño. Esta aproximación requiere la aplicación y/o adquisición de señales de alta frecuencia, para lo cual es necesario emplear equipos de test de alta frecuencia y, para dispositivos integrados, es necesario también disponer de un acceso adecuado a los nudos internos del sistema. No obstante, el incremento de la frecuencia de operación de estos sistemas y el aumento de la capacidad de integración hacen muy difícil cumplir con estos requerimientos. El acceso a nodos internos para test es normalmente imposible, e incluso cuando estos nodos son alcanzables puede haber pérdidas importantes de señal en el transporte de éstas hacia o desde el exterior debido a su alta frecuencia. Las soluciones de test BIST serian muy interesantes en este sentido. Las manipulaciones de señal serian internas, eliminando el problema del transporte. Sin embargo, la generación interna de estímulos de test de RF es complicada. Para mitigar este problema se han propuesto las soluciones loopback, que consisten en reinyectar la salida del transmisor al camino de recepción dentro del transceptor. Esto permite que el conversor D/A del transmisor cargue al conversor A/D del receptor, completando un test completamente digital. No obstante, el esquema loopback implica perturbar el funcionamiento normal del sistema: para acomodar la salida del transmisor a la entrada del receptor es necesario desconectar algunos componentes del transmisor del camino de señal y/o introducir un atenuador a la entrada del receptor. Traditional methods for testing RF circuits are based on specifications, that is, they verify that some or all of the system features are in accordance with the design specifications. This approach requires the application and / or acquisition of high frequency signals, for which it is necessary to use high frequency test equipment and, for integrated devices, it is also necessary to have adequate access to the internal nodes of the system. However, the increase in the frequency of operation of these systems and the increase in integration capacity make it very difficult to meet these requirements. Access to internal nodes for testing is normally impossible, and even when these nodes are attainable, there may be significant signal losses in transporting them to or from the outside due to its high frequency BIST test solutions would be very interesting in this regard. The signal manipulations would be internal, eliminating the transport problem. However, the internal generation of RF test stimuli is complicated. To alleviate this problem, loopback solutions have been proposed, which consist of reinjecting the transmitter's output to the reception path inside the transceiver. This allows the transmitter D / A converter to load the receiver A / D converter, completing a completely digital test. However, the loopback scheme involves disturbing the normal operation of the system: to accommodate the transmitter output to the receiver input it is necessary to disconnect some components of the transmitter from the signal path and / or introduce an attenuator to the receiver input.
Adicionalmente hay una gran demanda de soluciones de test KGD ( known-good-die ) que se puedan implementar a nivel de oblea, debido principalmente al incremento de coste que supone el empaquetado de circuitos defectuosos.  Additionally, there is a high demand for KGD test solutions (known-good-die) that can be implemented at the wafer level, mainly due to the increased cost of defective circuit packaging.
DESCRIPCIÓN DE LA INVENCIÓN  DESCRIPTION OF THE INVENTION
Para lograr los objetivos y evitar los inconvenientes indicados anteriormente, la invención consiste en un método y un sistema para llevar a cabo el test de circuitos integrados que forman parte de obleas electrónicas y el uso del método y sistema.  To achieve the objectives and avoid the drawbacks indicated above, the invention consists of a method and a system for carrying out the test of integrated circuits that are part of electronic wafers and the use of the method and system.
El objetivo principal de este invento es proporcionar un método fiable y rápido para descartar transceptores integrados defectuosos a nivel de oblea mediante el establecimiento de enlaces inalámbricos entre diferentes dados en la oblea, de tal forma que las señales necesarias para testar un determinado transceptor son proporcionadas o leídas por otro de los transceptores de la misma oblea. Estos enlaces inalámbricos permiten un test completo a nivel de sistema de las funciones de transmisión y recepción para cada dispositivo en la oblea, sin la necesidad de costosos equipos de test de RF para generar o leer señales de alta frecuencia, y sin perturbar el funcionamiento normal de los dispositivos bajo test. La invención que se reporta reduce los costes asociados al test de producción, y la detección temprana de circuitos defectuosos evita ejecutar una fracción importante de test tradicionales. Tiene también la ventaja de detectar fallos a nivel de oblea, de forma que se reducen los costes de empaquetado, que usualmente suponen aproximadamente el 25% del coste total del sistema . The main objective of this invention is to provide a reliable and fast method to rule out defective integrated transceivers at the wafer level by establishing wireless links between different dice in the wafer, so that the signals necessary to test a particular transceiver are provided or read by another of the transceivers of the same wafer. These wireless links allow a complete system level test of the transmission and reception functions for each device in the wafer, without the need for expensive RF test equipment to generate or read high frequency signals, and without disturbing normal operation. of the devices under test. The reported invention reduces the costs associated with the production test, and the early detection of defective circuits avoids running a significant fraction of traditional tests. It also has the advantage of detecting failures at the wafer level, so that packaging costs are reduced, which usually represent approximately 25% of the total system cost.
La posibilidad de testar la funcionalidad de un transceptor a nivel de oblea proporciona además información sobre el proceso de fabricación. Los resultados del test se pueden mapear sobre la oblea para obtener distribuciones de fallo intra-oblea e inter- oblea. Estas distribuciones se pueden usar para detectar y corregir desviaciones del proceso sistemáticas o no sistemáticas, o para guiar otras estrategias de test como las técnicas de screening.  The possibility of testing the functionality of a transceiver at the wafer level also provides information on the manufacturing process. The test results can be mapped onto the wafer to obtain distributions of intra-wafer and inter-wafer failure. These distributions can be used to detect and correct systematic or non-systematic deviations from the process, or to guide other test strategies such as screening techniques.
La detección de un transceptor defectuoso se puede usar también para activar funciones de test internas durante las operaciones de transmisión y recepción. De esta forma se pueden identificar los bloques internos defectuosos dentro del transceptor.  Detection of a defective transceiver can also be used to activate internal test functions during transmission and reception operations. In this way, the defective internal blocks within the transceiver can be identified.
Asi en una primera realización de la invención, el método de testado de circuitos integrados de radiofrecuencia a nivel de oblea objeto de la presente invención hace uso de un equipo de test digital de baja frecuencia que al menos comprende dos agujas de test. Las dos agujas, que denominaremos como primera aguja de test y segunda aguja de test, son para enviar y recibir unas secuencias de datos de test que se intercambian entre el equipo de test y los circuitos integrados de una oblea electrónica. Previamente se habrá seleccionado por parte de una cabeza de test integrada en el equipo de test al menos una pareja de circuitos integrados de la oblea electrónica. El método comprende las siguientes fases: i) enviar desde la primera aguja de test una secuencia de datos de test hasta un primer circuito integrado de la al menos una pareja previamente seleccionada; Thus, in a first embodiment of the invention, the method of testing of radio frequency integrated circuits at the wafer level object of the present invention makes use of a low frequency digital test equipment comprising at least two test needles. The Two needles, which we will call as the first test needle and second test needle, are for sending and receiving sequences of test data that are exchanged between the test equipment and the integrated circuits of an electronic wafer. Previously, at least one pair of integrated circuits of the electronic wafer will have been selected by a test head integrated in the test equipment. The method comprises the following phases: i) sending from the first test needle a sequence of test data to a first integrated circuit of the at least one previously selected pair;
ii) almacenar la secuencia de datos de test en un registro de datos del primer circuito integrado; iii) enviar desde el primer circuito integrado la secuencia de datos de test hasta un segundo circuito integrado de la pareja previamente seleccionada;  ii) storing the test data sequence in a data record of the first integrated circuit; iii) send from the first integrated circuit the sequence of test data to a second integrated circuit of the previously selected pair;
iv) almacenar la secuencia de datos de test en un registro de datos del segundo circuito integrado; v) enviar desde el segundo circuito integrado la secuencia de datos de test hasta el equipo digital de test a través de la segunda aguja de test ;  iv) storing the test data sequence in a data record of the second integrated circuit; v) send from the second integrated circuit the sequence of test data to the digital test equipment through the second test needle;
vi) comparar la secuencia de datos enviada por el equipo de test en la fase i) con la secuencia de datos recibida por el equipo de test en la fase v) ;  vi) compare the sequence of data sent by the test team in phase i) with the sequence of data received by the test team in phase v);
vii) enviar desde la segunda aguja de test una secuencia de datos de test hasta el segundo circuito integrado;  vii) send from the second test needle a sequence of test data to the second integrated circuit;
viii) almacenar la secuencia de datos de test en el registro de datos del segundo circuito; ix) enviar desde el segundo circuito integrado la secuencia de datos de test hasta el primer circuito integrado; viii) store the test data sequence in the data record of the second circuit; ix) send from the second integrated circuit the sequence of test data to the first integrated circuit;
x) almacenar la secuencia de datos de test en el registro de datos del primer circuito;  x) store the sequence of test data in the data record of the first circuit;
xi) enviar desde el primer circuito integrado la secuencia de datos hasta el equipo de test a través de la primera aguja de test; y,  xi) send the data stream to the test equipment from the first integrated circuit through the first test needle; Y,
xii) comparar la secuencia de datos de test enviada por el equipo de test en la fase vii) con la secuencia de datos recibida por el equipo de test en la fase xi ) .  xii) compare the sequence of test data sent by the test team in phase vii) with the sequence of data received by the test team in phase xi).
En otra realización de la invención, cuando al comparar las secuencias de datos enviada y recibida por el equipo de test en las fases vi) y xii) de la primera realización de la invención la secuencia de datos de test es la misma, el método comprende:  In another embodiment of the invention, when comparing the data sequences sent and received by the test equipment in phases vi) and xii) of the first embodiment of the invention the sequence of test data is the same, the method comprises :
• etiquetar la al menos una pareja de circuitos integrados como correcta; y,  • label the at least one pair of integrated circuits as correct; Y,
· almacenar las posiciones de la al menos una pareja de circuitos integrados.  · Store the positions of the at least one pair of integrated circuits.
En otra realización de la invención, cuando al comparar las secuencias de datos enviada y recibida por el equipo de test en las fases vi) y xii) de la primera realización de la invención la secuencia de datos de test es diferente, el método comprende:  In another embodiment of the invention, when comparing the data sequences sent and received by the test equipment in phases vi) and xii) of the first embodiment of the invention the sequence of test data is different, the method comprises:
• etiquetar la al menos una pareja de circuitos integrados como errónea; y,  • label the at least one pair of integrated circuits as erroneous; Y,
• almacenar las posiciones de la al menos una pareja de circuitos integrados.  • store the positions of the at least one pair of integrated circuits.
En otra realización de la invención cuando se ha etiquetado la al menos una pareja de circuitos integrados como correcta, cada uno de los dos circuitos integrados que forman la al menos una pareja de circuitos integrados se empareja con un circuito integrado de la vecindad y se lleva a cabo el procedimiento descrito en la primera realización de la invención. In another embodiment of the invention when at least one pair of integrated circuits has been labeled as correct, each of the two integrated circuits forming the at least one pair of integrated circuits is paired with an integrated neighborhood circuit and the procedure described in the first embodiment of the invention is carried out.
Asi en otra realización de la invención, una vez se tiene un circuito integrado que se sabe que funciona correctamente y se ha seleccionado otro circuito integrado de su vecindad, se aplica nuevamente el procedimiento descrito en la primera realización de la invención y cuando al comparar las secuencias de datos en las fases vi) y xii) la secuencia de datos de test enviada y recibida por el equipo de test es la misma, el procedimiento comprende:  Thus, in another embodiment of the invention, once there is an integrated circuit that is known to work correctly and another integrated circuit in its vicinity has been selected, the procedure described in the first embodiment of the invention is applied again and when comparing the data sequences in phases vi) and xii) the sequence of test data sent and received by the test equipment is the same, the procedure comprises:
• etiquetar el circuito integrado de la vecindad como correcto; y,  • label the neighborhood integrated circuit as correct; Y,
• almacenar la posición del circuito integrado de la vecindad .  • store the position of the neighborhood integrated circuit.
Por otro lado, en otra realización de la invención, una vez se tiene un circuito integrado que se sabe que funciona correctamente y se ha seleccionado otro circuito integrado de su vecindad, se aplica nuevamente el procedimiento descrito en la primera realización de la invención y cuando al comparar las secuencias de datos en las fases vi) y xii) la secuencia de datos de test enviada y recibida por el equipo de test es diferente, el procedimiento comprende:  On the other hand, in another embodiment of the invention, once there is an integrated circuit that is known to work correctly and another integrated circuit in its vicinity has been selected, the procedure described in the first embodiment of the invention is applied again and when when comparing the data sequences in phases vi) and xii) the sequence of test data sent and received by the test equipment is different, the procedure comprises:
• etiquetar el circuito integrado de la vecindad como erróneo; y,  • label the neighborhood integrated circuit as erroneous; Y,
• almacenar la posición del circuito integrado de la vecindad.  • store the position of the neighborhood integrated circuit.
Este procedimiento de emparejar circuitos integrados que se sabe que funcionan correctamente con otros circuitos integrados de su vecindad, se repite hasta que se ha testado la totalidad de los circuitos integrados que componen la oblea obteniéndose asi un mapa completo con los circuitos o transductores que no funcionan correctamente . This procedure of pairing integrated circuits that are known to work correctly with other integrated circuits in your neighborhood, is repeated until All of the integrated circuits that make up the wafer have been tested, thus obtaining a complete map with circuits or transducers that do not work properly.
En otra realización de la invención, el método comprende monitorizar el funcionamiento de cada módulo que integra el circuito integrado mediante unos sensores de test convencionales integrados en las obleas.  In another embodiment of the invention, the method comprises monitoring the operation of each module that integrates the integrated circuit by means of conventional test sensors integrated in the wafers.
En otra realización de la invención, cuando cada uno de los circuitos integrados integra una antena de test, el envío y recepción de la secuencia de datos de test de las fases iii) y ix) se realiza directamente entre las antenas de test del primer y segundo circuito integrado.  In another embodiment of the invention, when each of the integrated circuits integrates a test antenna, the sending and receiving of the test data sequence of phases iii) and ix) is performed directly between the test antennas of the first and Second integrated circuit.
En otra realización de la invención, cuando cada uno de los circuitos integrados no integra una antena de test, el envío y recepción de la secuencia de datos de test de las fases iii) y ix) se realiza mediante unas antenas de test externas posicionadas por la cabeza de test sobre el primer y el segundo circuito integrado.  In another embodiment of the invention, when each of the integrated circuits does not integrate a test antenna, the sending and receiving of the test data sequence of phases iii) and ix) is performed by external test antennas positioned by the test head on the first and second integrated circuit.
Por otra parte, la presente invención también tiene por objeto un sistema de testado de circuitos integrados de radiofrecuencia a nivel de oblea. Este sistema hace uso de un equipo de test digital de baja frecuencia que al menos comprende dos agujas de test, una primera aguja de test y una segunda aguja de test para el envío y recepción de unas secuencias de datos de test entre el equipo de test y los circuitos integrados de una oblea y de al menos una oblea electrónica compuesta de al menos dos circuitos integrados. Adicionalmente, el sistema al menos comprende:  On the other hand, the present invention also aims at a radio frequency integrated circuit testing system at the wafer level. This system makes use of a low frequency digital test equipment that comprises at least two test needles, a first test needle and a second test needle for sending and receiving test data sequences between the test equipment. and the integrated circuits of a wafer and at least one electronic wafer composed of at least two integrated circuits. Additionally, the system at least comprises:
• medios de transmisión de las secuencias de datos de test entre los circuitos integrados; y, • un registro de datos integrado en cada circuito integrado donde se almacena la secuencia de datos de test que intercambian los al menos dos circuitos integrados y el equipo de test de baja frecuencia. En otra realización de la invención, los medios de transmisión de las secuencias de datos de test entre los circuitos integrados comprenden estar seleccionados entre una antena de test integrada en cada uno de los circuitos integrados y una antena externa integrada en la cabeza de test para cada uno de los circuitos integrados. Las antenas de test y las agujas de test son ambas depositadas por la cabeza de test sobre los circuitos en sus repectivas posiciones. • means of transmission of test data sequences between integrated circuits; Y, • an integrated data record in each integrated circuit where the sequence of test data that the at least two integrated circuits exchange and the low frequency test equipment are stored. In another embodiment of the invention, the transmission means of the test data streams between the integrated circuits comprise being selected between a test antenna integrated in each of the integrated circuits and an external antenna integrated in the test head for each One of the integrated circuits. The test antennas and the test needles are both deposited by the test head over the circuits in their respective positions.
En otra realización de la invención, el sistema comprende sensores de test integrados junto con los circuitos integrados bajo test para monitorizar el funcionamiento de los bloques internos de dichos circuitos bajo test.  In another embodiment of the invention, the system comprises integrated test sensors together with the integrated circuits under test to monitor the operation of the internal blocks of said circuits under test.
La presente invención también contempla el uso del dispositivo y procedimiento descrito anteriormente para la obtención de mapas de distribución de circuitos integrados erróneos, estando los mapas seleccionados entre un mapa de fallos inter-oblea y un mapa de fallos intra-oblea .  The present invention also contemplates the use of the device and method described above for obtaining erroneous integrated circuit distribution maps, the maps being selected between an inter-wafer fault map and an intra-wafer fault map.
También se contempla el uso los mapas de distribución de circuitos integrados erróneos para la implementación de técnicas seleccionadas entre técnicas de screening Y técnicas de detección de desviaciones en el proceso de fabricación de las obleas. Estos mapas de distribución de circuitos integrados erróneos son útiles para determinar si existe alguna correlación entre la posición y el momento de fabricación de un circuito en cada oblea con la probabilidad de fallo de ese circuito. Si existe esta correlación, se pueden emplear técnicas de screening para eliminar los circuitos probablemente defectuosos, y, paralelamente, se puede buscar cual es la causa de desviación del proceso de fabricación para corregirla, aumentando asi el rendimiento del proceso. Si no existe esta correlación, los mapas sirven para monitorizar el rendimiento del proceso y su evolución en el tiempo, por lo que son útiles para detectar desviaciones en el proceso de fabricación e intentar corregirlas. The use of erroneous integrated circuit distribution maps is also contemplated for the implementation of selected techniques among screening techniques and deviation detection techniques in the wafer manufacturing process. These erroneous integrated circuit distribution maps are useful for determining if there is any correlation between the position and the time of manufacture of a circuit in each wafer with the probability of failure of that circuit. If this exists correlation, screening techniques can be used to eliminate the probably defective circuits, and, in parallel, it is possible to look for the cause of deviation of the manufacturing process to correct it, thus increasing the performance of the process. If this correlation does not exist, the maps serve to monitor the performance of the process and its evolution over time, so they are useful for detecting deviations in the manufacturing process and trying to correct them.
A modo de resumen, se describe en la presente memoria un test a nivel de sistema de transceptores integrados basado en explotar la capacidad de unos enlaces inalámbricos establecidos entre los circuitos integrados a nivel de oblea. Este test de RF se lleva a cabo con equipos de test digital de baja frecuencia. La antena de test que posibilita el enlace inalámbrico puede ser implementada on-chip o añadida a la cabeza del equipo de test. El procedimiento descrito permite la identificación de transceptores defectuosos integrados en sistemas on-chip complejos a nivel de linea de producción, antes del proceso de empaquetado de los chips. Además la operación del transceptor durante el test no es diferente de su operación normal. Se lleva a cabo un mapeo de los resultados del test en distribuciones de fallo inter-oblea e intra-oblea lo que permite una fácil identificación de chips defectuosos sin llevar a cabo un testado completo. Las distribuciones de fallos en los circuitos se pueden usar para guiar otras estrategias de test, como por ejemplo técnicas de screening. También se usan las distribuciones de fallos para detectar desviaciones del proceso de fabricación, ya sean éstas sistemáticas o no sistemáticas. Se pueden incluir funciones de test interno a los transceptores para diagnóstico. Las señales de test de alta frecuencia son proporcionadas o leídas por otro de los transceptores en la misma oblea. As a summary, a test at the integrated transceiver system level based on exploiting the capacity of wireless links established between the wafer-integrated circuits is described herein. This RF test is carried out with low frequency digital test equipment. The test antenna that enables the wireless link can be implemented on-chip or added to the head of the test equipment. The described procedure allows the identification of defective transceivers integrated in complex on-chip systems at the production line level, before the chip packaging process. In addition, the operation of the transceiver during the test is not different from its normal operation. A mapping of the test results in distributions of inter-wafer and intra-wafer failure is carried out, allowing easy identification of defective chips without carrying out a complete test. Circuit fault distributions can be used to guide other test strategies, such as screening techniques. Fault distributions are also used to detect deviations from the manufacturing process, whether systematic or non-systematic. Transceiver internal test functions may be included for diagnosis High frequency test signals are provided or read by another of the transceivers in the same wafer.
BREVE DESCRIPCIÓN DE LAS FIGURAS  BRIEF DESCRIPTION OF THE FIGURES
Figura 1.- Muestra el esquema más general de la invención en el que el equipo de test digital testa 3 parejas de circuitos integrados en una oblea.  Figure 1.- Shows the most general scheme of the invention in which the digital test equipment tests 3 pairs of integrated circuits in a wafer.
Figura 2.- Muestra un diagrama del método de testado objeto de la presente invención aplicado a una pareja de circuitos integrados, en el que ambos circuitos comprenden antenas de test.  Figure 2.- Shows a diagram of the test method object of the present invention applied to a pair of integrated circuits, in which both circuits comprise test antennas.
Figura 3.- Muestra un diagrama de bloques detallado de una pareja de circuitos integrados bajo test.  Figure 3.- Shows a detailed block diagram of a pair of integrated circuits under test.
Figura 4.- Muestra ejemplos de mapas de distribución de circuitos integrados erróneos en obleas.  Figure 4.- Shows examples of erroneous integrated circuit distribution maps in wafers.
DESCRIPCIÓN DE VARIOS EJEMPLOS DE REALIZACIÓN DE LA DESCRIPTION OF VARIOUS EXAMPLES OF REALIZATION OF THE
INVENCIÓN INVENTION
Seguidamente se realizan, con carácter ilustrativo y no limitativo, una descripción de varios ejemplos de realización de la invención, haciendo referencia a la numeración adoptada en las figuras.  Next, a description of several embodiments of the invention is made, by way of illustration and not limitation, with reference to the numbering adopted in the figures.
La figura 1 representa un esquema general de la estrategia de test propuesta. Los circuitos integrados de la oblea se agrupan por parejas (1), y son controlados digitalmente por un equipo de test digital de baja frecuencia (2) . Concretamente en esta realización el equipo digital de test (2) dispone de 3 parejas de agujas de test (3) estando encargadas cada una de las parejas de agujas (3) del intercambio de la secuencia de test con cada una de las parejas de circuitos integrados (1) . En esta realización los circuitos integrados que componen la oblea disponen de antenas de test integradas para realizar conexiones inalámbricas (4) entre ellos. La Figura 2 muestra un diagrama de bloques del esquema de test propuesto para una de estas parejas bajo test, compuesta en la figura por los circuitos integrados Die 1 (5) y Die 2 (6) . En primer lugar, el equipo de test digital (2) escribe una secuencia digital optimizada al registro REGI (7) . Esta secuencia digital es transmitida por el transceptor TI (8) (que incorpora una antena de test) y recibida por el transceptor T2 (9) (que también incorpora una antena de test) . La señal recibida es almacenada en el registro REG2 (10) y comparada con la secuencia original para comprobar la funcionalidad de las funciones de transmisión-recepción. A continuación, se invierte el proceso (T2 (9) transmite y TI (8) escucha) para completar el test. Si la secuencia recibida es idéntica a la enviada, la funcionalidad de ambos transceptores ha sido correcta. Múltiples parejas de test se pueden probar en paralelo para acelerar el proceso. El número máximo de parejas de test está limitado por el número de canales de transmisión disponibles y por el número de agujas de test en la cabeza del equipo de test digital . Figure 1 represents a general outline of the proposed test strategy. The wafer integrated circuits are grouped in pairs (1), and are digitally controlled by a low frequency digital test equipment (2). Specifically in this embodiment the digital test equipment (2) has 3 pairs of test needles (3) each of the needle pairs (3) being in charge of exchanging the test sequence with each of the circuit pairs integrated (1). In this embodiment the integrated circuits that make up the wafer have integrated test antennas to make wireless connections (4) between them. Figure 2 shows a block diagram of the proposed test scheme for one of these couples under test, composed in the figure by the integrated circuits Die 1 (5) and Die 2 (6). First, the digital test equipment (2) writes an optimized digital sequence to the REGI register (7). This digital sequence is transmitted by the TI transceiver (8) (which incorporates a test antenna) and received by the T2 transceiver (9) (which also incorporates a test antenna). The received signal is stored in the REG2 register (10) and compared to the original sequence to check the functionality of the transmission-reception functions. The process is then reversed (T2 (9) transmits and TI (8) listens) to complete the test. If the sequence received is identical to the one sent, the functionality of both transceivers has been correct. Multiple test pairs can be tested in parallel to speed up the process. The maximum number of test pairs is limited by the number of available transmission channels and by the number of test needles on the head of the digital test equipment.
La figura 3 muestra el esquema de test completo para una determinada pareja bajo test en una oblea, incluyendo recursos on-chip y externos. La operación del sistema no es diferente de su operación normal, por lo que muy poca circuiteria se ha añadido on-chip. Básicamente, son necesarios registros digitales (20,21) para almacenar las secuencias de test, y antenas de test (22,23) para realizar la comunicación inalámbrica. Estas antenas de test (22,23) pueden ser integradas on-chip o añadidas a la cabeza del equipo de test. En cualquier caso, la señal tiene que viajar sólo unos cuantos milímetros (tamaño típico de un dado) en una dirección fija (filas y/o columnas en la oblea) , lo que simplifica la implementación de la antena. El equipo de test digital externo (24) proporciona la alimentación (29) y el reloj de referencia (27) (baja frecuencia) a las parejas de circuitos integrados bajo test, fija el canal de comunicación adecuado para cada circuito (25,26), y escribe/lee las secuencias de test intercambiadas. Finalmente, la información extraída se almacena en un ordenador convencional para su procesado. Figure 3 shows the complete test scheme for a given couple under test in a wafer, including on-chip and external resources. The operation of the system is no different from its normal operation, so very little circuitry has been added on-chip. Basically, digital records (20,21) are required to store the test sequences, and test antennas (22,23) to perform wireless communication. These test antennas (22,23) can be integrated on-chip or added to the head of the test equipment. In any case, the signal has to travel only a few millimeters (typical size of a dice) in a fixed direction (rows and / or wafer columns), which simplifies the implementation of the antenna. The external digital test equipment (24) provides the power supply (29) and the reference clock (27) (low frequency) to the pairs of integrated circuits under test, sets the appropriate communication channel for each circuit (25,26) , and write / read the exchanged test sequences. Finally, the extracted information is stored in a conventional computer for processing.
Un ejemplo de realización del procedimiento objeto de la presente invención es el siguiente:  An example of embodiment of the process object of the present invention is the following:
Pasol: Encontrar un conjunto de transceptores con funcionamiento correcto comprobado (Known Good Transceivers , KGTs por sus siglas en inglés) .  Pasol: Find a set of transceivers with proven correct operation (Known Good Transceivers, KGTs).
En primer lugar, la cabeza de test selecciona aleatoriamente un número de parejas de test en la oblea. El número de parejas bajo test simultáneas se determina por el número de canales de comunicación disponibles y por el número de agujas de test disponibles en la cabeza del equipo de test. Cada pareja tiene que transmitir/recibir en un canal diferente para evitar interferencias, y cada circuito necesita al menos dos agujas para alimentación (29), una para el reloj (27) de referencia de baja frecuencia (necesario para el sintetizador de frecuencia) , y una para entrada/salida digital (28) para cargar/leer la secuencia de test y fijar el canal de transmisión /recepción deseado. La estructura de esta secuencia digital es:  First, the test head randomly selects a number of test pairs in the wafer. The number of pairs under simultaneous tests is determined by the number of communication channels available and by the number of test needles available on the head of the test equipment. Each pair has to transmit / receive on a different channel to avoid interference, and each circuit needs at least two needles for power (29), one for the low frequency reference clock (27) (necessary for the frequency synthesizer), and one for digital input / output (28) to load / read the test sequence and set the desired transmission / reception channel. The structure of this digital sequence is:
\ y \ \__y \ y \ \ __ and
datos de test (N bits) Selección de selección de  test data (N bits) Selection of selection of
canal transmisión/recepción  transmission / reception channel
(k bits) <1 bit)  (k bits) <1 bit)
Cada pareja de transceptores se prueba a nivel de sistema. Uno de los circuitos transmite en un determinado canal mientras que el otro circuito de la pareja recibe en el mismo canal. En primer lugar, se escribe una secuencia digital optimizada al registro REGi (20) en el dado Die i (25) . Esta secuencia puede contener todas las transiciones significativas entre símbolos para testar el enlace inalámbrico (el número y la definición de los símbolos depende del protocolo de comunicaciones implementado en el transceptor) . Esta secuencia de test es transmitida al dado Die i+1 (26) . La secuencia recibida se almacena en el registro REG i+ 1 (21) . El contenido de los registros es leído por el equipo de test digital (24) y comparado para comprobar la funcionalidad de la transmisión-recepción a nivel de sistema. Si la comparación es positiva el proceso se repite a la inversa, es decir, el circuito Die i+1 (26) transmite mientras que Die i (25) recibe. Si la segunda comparación también es positiva, entonces los circuitos Die i (25) y Die i+ 1 (26) se etiquetan como KGT, y se almacenan sus posiciones en la oblea. Each pair of transceivers is tested at the system level. One of the circuits transmits in a given channel while the other circuit of the couple receives on the same channel. First, an optimized digital sequence is written to the REGi (20) register in the Die i (25) die. This sequence can contain all the significant transitions between symbols to test the wireless link (the number and definition of the symbols depends on the communications protocol implemented in the transceiver). This test sequence is transmitted to die Die i + 1 (26). The received sequence is stored in the REG i + 1 register (21). The contents of the records are read by the digital test equipment (24) and compared to check the functionality of the transmission-reception system level. If the comparison is positive, the process is repeated in reverse, that is, the circuit Die i + 1 (26) transmits while Die i (25) receives. If the second comparison is also positive, then the circuits Die i (25) and Die i + 1 (26) are labeled as KGT, and their positions are stored in the wafer.
Paso 2: Detectar transceptores defectuosos  Step 2: Detect defective transceivers
Una vez que se ha obtenido un conjunto de KGTs, cada uno de los KGT se enlaza de forma inalámbrica a uno de los circuitos no testados a su alrededor y se repite el proceso descrito en el "paso 1" con la pareja resultante. Si el test falla, el circuito enlazado con el KGT se etiqueta como defectuoso y se almacena su posición en la oblea. Si el test tiene éxito, el circuito enlazado con el KGT se etiqueta como KGT y puede ser usado para testar otros dados en su vecindad.  Once a set of KGTs has been obtained, each of the KGTs is wirelessly linked to one of the circuits not tested around it and the process described in "step 1" is repeated with the resulting pair. If the test fails, the circuit linked to the KGT is labeled as defective and its position is stored in the wafer. If the test is successful, the circuit linked to the KGT is labeled as KGT and can be used to test other dice in your neighborhood.
Paso 3: Mapeo y procesado de la información de fallos  Step 3: Mapping and processing fault information
El proceso descrito en los pasos 1 y 2 continúa hasta que todos los circuitos integrados en la oblea han sido testados. Seguidamente, el proceso se repite con las siguientes obleas. La información de fallo obtenida se puede mapear en distribuciones de fallo intra-oblea e inter-oblea. Un análisis estadístico de estas distribuciones para encontrar correlaciones entre el resultado del test, la posición en la oblea y el momento de fabricación ofrece información valiosa para detectar y corregir desviaciones en el proceso de fabricación. La figura 4 muestra ejemplos de estas distribuciones para el caso de desviaciones sistemáticas y no sistemáticas. Adicionalmente, estos mapas se pueden usar para guiar otras estrategias de test, como por ejemplo las técnicas de screening, lo que proporcionaría un mejor rendimiento del proceso. The process described in steps 1 and 2 continues until all the circuits integrated in the wafer have been tested Next, the process is repeated with the following wafers. The obtained fault information can be mapped into intra-wafer and inter-wafer fault distributions. A statistical analysis of these distributions to find correlations between the test result, the position in the wafer and the time of manufacture offers valuable information to detect and correct deviations in the manufacturing process. Figure 4 shows examples of these distributions in the case of systematic and non-systematic deviations. Additionally, these maps can be used to guide other test strategies, such as screening techniques, which would provide better process performance.
Paso 4: (opcional) : activar estructuras de test internas en circuitos defectuosos para diagnóstico  Step 4: (optional): activate internal test structures in faulty circuits for diagnosis
El test a nivel de sistema realizado en los pasos 1 y 2 comprueba la funcionalidad de la transmisión y recepción de datos en el transceptor, pero si el test falla, no proporciona información para identificar qué elemento en el transceptor está fallando. Se pueden añadir funciones de diagnóstico incluyendo sensores de test on-chip para monitorizar el funcionamiento de cada uno de los bloques internos mostrados en la figura 3. Son sobradamente conocidos en el estado de la técnica múltiples implementaciones para estos sensores. El dado defectuoso se puede enlazar a uno de lo KGT para proporcionar el estímulo de test necesario, o leer la respuesta, mientras que la salida digital de los sensores de test se puede adquirir con el equipo de test digital externo para diagnosticar los elementos defectuosos.  The system-level test performed in steps 1 and 2 checks the functionality of the transmission and reception of data in the transceiver, but if the test fails, it does not provide information to identify which element in the transceiver is failing. Diagnostic functions can be added including on-chip test sensors to monitor the operation of each of the internal blocks shown in Figure 3. Multiple implementations for these sensors are well known in the state of the art. The defective die can be linked to one of the KGTs to provide the necessary test stimulus, or read the response, while the digital output of the test sensors can be acquired with the external digital test equipment to diagnose the defective elements.

Claims

RE IVI DICACIONES RE IVI DICATIONS
1.- Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, que hace uso de un equipo de test digital de baja frecuencia que al menos comprende dos agujas de test, una primera aguja de test y una segunda aguja de test, para enviar y recibir unas secuencias de datos de test entre el equipo de test y los circuitos integrados de una oblea electrónica, y habiéndose seleccionado previamente por parte de una cabeza de test integrada en el equipo de test al menos una pareja de circuitos integrados de la oblea electrónica, se caracteriza porque comprende las siguientes fases: 1.- Method of testing of radio frequency integrated circuits at the wafer level, which makes use of a low frequency digital test equipment comprising at least two test needles, a first test needle and a second test needle, to send and receive test data sequences between the test equipment and the integrated circuits of an electronic wafer, and at least one pair of integrated wafer circuits having been previously selected by a test head integrated in the test equipment electronic, is characterized in that it comprises the following phases:
i) enviar desde la primera aguja de test una secuencia de datos de test hasta un primer circuito integrado de la al menos una pareja previamente seleccionada;  i) send from the first test needle a sequence of test data to a first integrated circuit of the at least one previously selected pair;
ii) almacenar la secuencia de datos de test en un registro de datos del primer circuito integrado; iii) enviar desde el primer circuito integrado la secuencia de datos de test hasta un segundo circuito integrado de la pareja previamente seleccionada;  ii) storing the test data sequence in a data record of the first integrated circuit; iii) send from the first integrated circuit the sequence of test data to a second integrated circuit of the previously selected pair;
iv) almacenar la secuencia de datos de test en un registro de datos del segundo circuito integrado; v) enviar desde el segundo circuito integrado la secuencia de datos de test hasta el equipo digital de test a través de la segunda aguja de test ;  iv) storing the test data sequence in a data record of the second integrated circuit; v) send from the second integrated circuit the sequence of test data to the digital test equipment through the second test needle;
vi) comparar la secuencia de datos enviada por el equipo de test en la fase i) con la secuencia de datos recibida por el equipo de test en la fase v) ; vi) compare the sequence of data sent by the test team in phase i) with the sequence of data received by the test team in phase v);
vii) enviar desde la segunda aguja de test una secuencia de datos de test hasta el segundo circuito integrado;  vii) send from the second test needle a sequence of test data to the second integrated circuit;
viii) almacenar la secuencia de datos de test en el registro de datos del segundo circuito; ix) enviar desde el segundo circuito integrado la secuencia de datos de test hasta el primer circuito integrado;  viii) store the test data sequence in the data record of the second circuit; ix) send from the second integrated circuit the sequence of test data to the first integrated circuit;
x) almacenar la secuencia de datos de test en el registro de datos del primer circuito;  x) store the sequence of test data in the data record of the first circuit;
xi) enviar desde el primer circuito integrado la secuencia de datos hasta el equipo de test a través de la primera aguja de test; y,  xi) send the data stream to the test equipment from the first integrated circuit through the first test needle; Y,
xii) comparar la secuencia de datos de test enviada por el equipo de test en la fase vii) con la secuencia de datos recibida por el equipo de test en la fase xi ) .  xii) compare the sequence of test data sent by the test team in phase vii) with the sequence of data received by the test team in phase xi).
2.- Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación 1, caracterizado porque comprende 2. Method of testing of radio frequency integrated circuits at the wafer level, according to claim 1, characterized in that it comprises
• etiquetar la al menos una pareja de circuitos integrados como correcta; y,  • label the at least one pair of integrated circuits as correct; Y,
• almacenar las posiciones de la al menos una pareja de circuitos integrados,  • store the positions of the at least one pair of integrated circuits,
cuando al comparar las secuencias de datos enviada y recibida por el equipo de test en las fases vi) y xii), la secuencia de datos de test es la misma. when comparing the data sequences sent and received by the test team in phases vi) and xii), the sequence of test data is the same.
3. - Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación3. - Method of testing of radio frequency integrated circuits at the wafer level, according to claim
1, caracterizado porque comprende: 1, characterized in that it comprises:
• etiquetar la al menos una pareja de circuitos integrados como errónea; y,  • label the at least one pair of integrated circuits as erroneous; Y,
• almacenar las posiciones de la al menos una pareja de circuitos integrados,  • store the positions of the at least one pair of integrated circuits,
cuando al comparar las secuencias de datos enviada y recibida por el equipo digital de test en las fases vi) y xii), la secuencia de datos es diferente. when comparing the data sequences sent and received by the digital test equipment in phases vi) and xii), the data sequence is different.
4. - Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación4. - Method of testing of radio frequency integrated circuits at the wafer level, according to claim
2, caracterizado porque cuando se ha etiquetado la al menos una pareja de circuitos integrados como correcta, cada uno de los dos circuitos integrados que forman la al menos una pareja de circuitos integrados se empareja con un circuito integrado de la vecindad y se lleva a cabo el procedimiento descrito en las reivindicación 1. 2, characterized in that when the at least one pair of integrated circuits has been labeled as correct, each of the two integrated circuits that form the at least one pair of integrated circuits is paired with a neighborhood integrated circuit and is carried out The method described in claim 1.
5. - Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación 4, caracterizado porque comprende 5. - Method of testing of radio frequency integrated circuits at the wafer level, according to claim 4, characterized in that it comprises
• etiquetar el circuito integrado de la vecindad como correcto; y,  • label the neighborhood integrated circuit as correct; Y,
• almacenar la posición del circuito integrado de la vecindad,  • store the position of the neighborhood integrated circuit,
cuando al comparar las secuencias de datos en las fases vi) y xii) la secuencia de datos de test enviada y recibida por el equipo de test es la misma. when comparing the data sequences in phases vi) and xii) the sequence of test data sent and received by the test equipment is the same.
6. - Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación 4, caracterizado porque comprende 6. - Method of testing of radio frequency integrated circuits at the wafer level, according to claim 4, characterized in that it comprises
• etiquetar el circuito integrado de la vecindad como erróneo; y,  • label the neighborhood integrated circuit as erroneous; Y,
• almacenar la posición del circuito integrado de la vecindad,  • store the position of the neighborhood integrated circuit,
cuando al comparar las secuencias de datos en las fases vi) y xii) la secuencia de datos de test enviada y recibida por el equipo de test es diferente. when comparing the data sequences in phases vi) and xii) the test data sequence sent and received by the test equipment is different.
7. - Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación 1, caracterizado porque comprende monitorizar el funcionamiento de cada módulo que integra el circuito integrado mediante unos sensores de test convencionales integrados en las obleas. 7. - Method of testing of radio frequency integrated circuits at the wafer level, according to claim 1, characterized in that it comprises monitoring the operation of each module that integrates the integrated circuit by means of conventional test sensors integrated in the wafers.
8. - Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación8. - Method of testing of radio frequency integrated circuits at the wafer level, according to claim
1, caracterizado porque cuando cada uno de los circuitos integrados integra una antena de test, el envío y recepción de la secuencia de datos de test de las fases iii) y ix) se realiza directamente entre las antenas de test del primer y segundo circuito integrado. 1, characterized in that when each of the integrated circuits integrates a test antenna, the sending and receiving of the test data sequence of phases iii) and ix) is carried out directly between the test antennas of the first and second integrated circuit .
9. -Método de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación 1, caracterizado porque cuando cada uno de los circuitos integrados no integra una antena de test, el envío y recepción de la secuencia de datos de test de las fases iii) y ix) se realiza mediante unas antenas de test externas posicionadas por la cabeza de test sobre el primer y el segundo circuito integrado. 9. - Method of testing of radio frequency integrated circuits at the wafer level, according to claim 1, characterized in that when each of the integrated circuits does not integrate a test antenna, the sending and receiving of the test data sequence of the phases iii) and ix) is carried out by means of test antennas external positions positioned by the test head on the first and the second integrated circuit.
10.- Sistema de testado de circuitos integrados de radiofrecuencia a nivel de oblea, que hace uso de un equipo de test digital de ba a frecuencia que al menos comprende dos agujas de test, una primera aguja de test y una segunda aguja de test para el envío y recepción de unas secuencias de datos de test entre el equipo de test y los circuitos integrados de una oblea y de al menos una oblea electrónica compuesta de al menos dos circuitos integrados, caracterizado porque al menos comprende: 10.- System for testing of radio frequency integrated circuits at the wafer level, which makes use of a digital frequency test equipment that includes at least two test needles, a first test needle and a second test needle for sending and receiving test data sequences between the test equipment and the integrated circuits of a wafer and at least one electronic wafer composed of at least two integrated circuits, characterized in that it comprises at least:
• medios de transmisión de las secuencias de datos de test entre los circuitos integrados; y,  • means of transmission of test data sequences between integrated circuits; Y,
· un registro de datos integrado en cada circuito integrado donde se almacena la secuencia de datos de test que intercambian los al menos dos circuitos integrados y el equipo de test de baja frecuencia.  · An integrated data record in each integrated circuit where the sequence of test data that the at least two integrated circuits exchange and the low frequency test equipment are stored.
11.- Sistema de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación 10, caracterizado porque los medios de transmisión de las secuencias de datos de test entre los circuitos integrados comprenden estar seleccionados entre una antena de test integrada en cada uno de los circuitos integrados y una antena externa integrada en la cabeza de test para cada uno de los circuitos integrados. 11. Wafer-level radiofrequency integrated circuit testing system, according to claim 10, characterized in that the transmission means of the test data sequences between the integrated circuits comprise being selected from a test antenna integrated in each of integrated circuits and an external antenna integrated in the test head for each of the integrated circuits.
12.- Sistema de testado de circuitos integrados de radiofrecuencia a nivel de oblea, según la reivindicación 10, caracterizado porque comprende sensores de test integrados en la oblea para monitorizar el funcionamiento de unos bloques internos de la oblea. 12. System for testing of radio frequency integrated circuits at the wafer level, according to claim 10, characterized in that it comprises test sensors integrated in the wafer to monitor the operation of internal wafer blocks.
13.- Uso del dispositivo y procedimiento descrito en una cualquiera de las reivindicaciones anteriores para la obtención de mapas de distribución de circuitos integrados erróneos, estando los mapas seleccionados entre un mapa de fallos inter-oblea y un mapa de fallos intra-oblea . 13. Use of the device and method described in any one of the preceding claims for obtaining erroneous integrated circuit distribution maps, the maps being selected between an inter-wafer fault map and an intra-wafer fault map.
14.- Uso del dispositivo y procedimiento descrito en una cualquiera de las reivindicaciones 1 a 12, según la reivindicación 13, caracterizado porque comprende emplear los mapas de distribución de circuitos integrados erróneos para la implementación de técnicas seleccionadas entre técnicas de screening Y técnicas de detección de desviaciones en el proceso de fabricación de las obleas. 14. Use of the device and method described in any one of claims 1 to 12, according to claim 13, characterized in that it comprises using the erroneous integrated circuit distribution maps for the implementation of selected techniques among screening techniques and detection techniques of deviations in the wafer manufacturing process.
PCT/ES2012/070484 2011-06-30 2012-06-29 Method and system for testing integrated radio-frequency circuits at the wafer level and the use thereof WO2013001131A1 (en)

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Citations (2)

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Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US20090152546A1 (en) * 2005-09-27 2009-06-18 Nxp B.V. Wafer with scribe lanes comprising active circuits for die testing of complementary signal processing parts
US20100237891A1 (en) * 2009-03-20 2010-09-23 Shanghai XinHao (BraveChips) Micro Electronics Co. Ltd. Method, apparatus and system of parallel IC test

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