WO2012163599A1 - Semiconductor component and corresponding production method - Google Patents

Semiconductor component and corresponding production method Download PDF

Info

Publication number
WO2012163599A1
WO2012163599A1 PCT/EP2012/057370 EP2012057370W WO2012163599A1 WO 2012163599 A1 WO2012163599 A1 WO 2012163599A1 EP 2012057370 W EP2012057370 W EP 2012057370W WO 2012163599 A1 WO2012163599 A1 WO 2012163599A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
metallization layer
layer
semiconductor chip
semiconductor device
Prior art date
Application number
PCT/EP2012/057370
Other languages
German (de)
French (fr)
Inventor
Thomas Suenner
Thomas Kaden
Michael Guenther
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2012163599A1 publication Critical patent/WO2012163599A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Definitions

  • the invention relates to a semiconductor device and a corresponding
  • a vertical power semiconductor component which has a full-surface backside metallization, which extends to the chip edge.
  • Such vertical power semiconductor components are applied, for example, by bonding, soldering or sintering or bonding to a substrate, for example a DCB substrate or an IMS substrate or an AMB substrate or a stamped grid. Under load, z. B. by thermo-mechanical cycling, this compound often form cracks from the edge of the semiconductor chip. These cracks expand, leading to
  • the invention provides a semiconductor device according to claim 1 and corresponding manufacturing method according to claim 10, 11 and 12. Preferred developments are the subject of the respective subclaims. Advantages of the invention
  • the metallization layer is completely removed in the circumferential region, for example by means of an etching process.
  • the metallization layer is only thinned at the edge, preferably in a stepped manner, such that the thick metallization region is
  • the removed or thinned circumferential area is compensated with a circumferential insulating layer so that it with the rest
  • Metallization layer is substantially planar.
  • the material of the insulating layer of the material of the connecting layer is poorly or not wettable, whereby the bonding layer in the processing poor or not at the insulating layer adheres and thus no forces are exerted on the edge of the semiconductor chip in this variant. It can also be provided a sequence of layers in which a missing
  • wetting or adhesion of the bonding material is introduced at the edge of at least the last layer facing the semiconductor chip.
  • the semiconductor can also be provided on both sides with such metallization layers, if, for example, a sandwich construction between two substrates is desired.
  • a further advantage is that controlled wetting avoids squeezing out of the material of the connecting layer, which minimizes the risk of a short circuit of the top and bottom sides of the semiconductor chip during manufacture.
  • FIG. 1 a is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention
  • Fig. 1b is a section along the line A-A 'in Fig. 1a;
  • FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention;
  • 6a-c are schematic cross-sectional views for explaining a
  • Fig. 7a-c are schematic cross-sectional views for explaining a
  • FIG. 8a-c are schematic cross-sectional views for explaining a
  • FIG. 1 a shows a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention and FIG. 1 b shows a section along the line A-A 'in FIG. 1 a.
  • reference numeral 1 denotes a semiconductor chip in the form of a vertical power semiconductor device, for example, an IGBT, which has a front side VS, a back side RS, and an edge R.
  • Reference symbol AR denotes a rear contact area provided in the semiconductor chip 1, for example a corresponding diffusion area. Further details of the semiconductor chip are not shown for reasons of clarity.
  • a metallization layer MR which is connected in a planar manner to a substrate S, for example a DCB substrate, via a connection layer VR.
  • the rear metallization layer MR is completely removed from a circumferential annular region B along the edge R, so that a gap SP arises between the connection layer VR and the rear side RS of the semiconductor chip 1 during assembly in the region B.
  • the width d of the circumferential annular region B can be determined application-specific and is usually a few percent of the diameter of the semiconductor chip 1.
  • FIG. 2 shows a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
  • the construction is identical to that of the first one
  • Connection layer VR and the back side RS of the semiconductor chip 1 no gap, but an insulating layer I is provided, which is not wettable by the material of the bonding layer VR, for example solder, so that it is also in this second
  • Embodiment no force coupling on the sawing defective edge R of the semiconductor chip 1 are.
  • the insulating layer is superficially flush with the rear metallization MR.
  • FIG. 3 shows a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
  • the backside metallization layer MR ' is not completely removed in the annular region B, but only thinned stepwise, so that here too a gap SP' arises between the connection layer VR and the backside RS of the semiconductor chip 1 during assembly.
  • this gap SP ' is smaller than the gap of the above-described first embodiment, it can still be dimensioned so that it receives a force input to the edge R of the
  • the electrical coupling is improved if the backside metallization layer MR lies flat on the wafer back side RS.
  • the contact resistance and the current load per area decrease.
  • FIG. 4 shows a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.
  • the semiconductor chip 1 additionally has a front-side contact area AV, which has a front-side contact area AV
  • Metallization layer MV and a connection layer W is connected to a further substrate S ', so that a sandwich structure between the substrates S, S ⁇ is achieved.
  • the annular region B on the back side R of the semiconductor chip 1 is filled with an insulating layer I as in the second embodiment, whereas the annular region B on the front side VS of the semiconductor chip has a gap SP as in the first embodiment.
  • the sandwich structure in this regard can also be symmetrical, ie either front side and rear side, a gap SP can be provided or front and back an insulating layer I can be provided.
  • FIG. 5 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.
  • a corresponding stepped front side metallization MV is provided and wherein the front side and rear side, a corresponding gap SP 'between the connection layer VR or VS and the back side RS and the front side VS of the semiconductor chip for force decoupling is provided.
  • Figs. 6a-c are schematic cross-sectional views for explaining one
  • a manufacturing method of a semiconductor device according to the first embodiment of the present invention is a manufacturing method of a semiconductor device according to the first embodiment of the present invention.
  • the rear side metallization layer MR is first applied over the full area on the rear side RS of the semiconductor chip 1. This can be done for example by sputtering or vapor deposition and with or without additional galvanic reinforcement.
  • the metallization layer MR can then be removed from the annular region B using the structured resist mask LM.
  • FIGS. 7a-c are schematic cross-sectional views for explaining a manufacturing method of a semiconductor device according to the second embodiment of the present invention.
  • first of all the insulating layer I is provided over the whole area on the rear side RS of the semiconductor chip 1, for example by depositing a corresponding silicon oxide.
  • annular resist mask LM ' is then provided on the insulating layer I.
  • the deposition can also be done beforehand in another process.
  • the insulating layer I is then removed in the region B complementary to the region B, so that a cutout is formed in the insulating layer I exposing the rear side RS of the semiconductor chip 1. Subsequently, the resist mask LM 'is removed or stripped.
  • the backside metallization layer MR is deposited within the recess V such that it is substantially planar with the insulating layer I.
  • FIG. Figs. 8a-c are schematic cross-sectional views for explaining one
  • a manufacturing method of a semiconductor device according to the third embodiment of the present invention is a manufacturing method of a semiconductor device according to the third embodiment of the present invention.
  • the mask LG can then either be left as an insulating layer I analogous to the embodiment according to FIG. 2, in which case it runs substantially planar with the remaining rear metallization layer MR ', or it can, as in FIG dashed line indicated removed, which leads to the embodiment of FIG.
  • semiconductor chip as used above can refer both to chips which have been sawn from a wafer and to entire wafers, wherein the semiconductor component is formed by the entire wafer.
  • semiconductor chips of the above-described embodiments have a polygonal shape, the invention is not limited to the angular chip shape, but is basically applicable to any chip geometries.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a semiconductor component and a corresponding production method. The semiconductor component comprises a semiconductor chip (1) having a first primary side (RS) and a second primary side (VS) and an edge (R). At least one of the first primary side (RS) and the second primary side (VS) is provided with a metallization layer (MR) for the planar installation of the semiconductor chip (1), wherein the metallization layer (MR) is removed or thinned out in a peripheral area (B) along the edge (R) of the semiconductor chip (1).

Description

Beschreibung Titel  Description title
Halbleiterbauelement und entsprechendes Herstellungsverfahren  Semiconductor component and corresponding manufacturing method
Die Erfindung betrifft ein Halbleiterbauelement und ein entsprechendes The invention relates to a semiconductor device and a corresponding
Herstellungsverfahren. Production method.
Obwohl auch beliebige Halbleiterbauelemente anwendbar, werden die vorliegende Erfindung und die ihr zugrundeliegende Problematik anhand von vertikalen Although any semiconductor devices applicable, the present invention and the underlying problems are based on vertical
Leistungshalbleiterbauelementen, wie z.B. IGBTs, erläutert. Stand der Technik Power semiconductor devices, such as e.g. IGBTs, explained. State of the art
Aus der WO 2001/015235 A1 ist ein vertikales Leistungshalbleiterbauelement bekannt, welches eine ganzflächige Rückseitenmetallisierung aufweist, die bis zum Chiprand reicht. From WO 2001/015235 A1 a vertical power semiconductor component is known, which has a full-surface backside metallization, which extends to the chip edge.
Derartige vertikale Leistungshalbleiterbauelemente werden beispielsweise durch Bonden, Löten oder Sintern bzw. Kleben auf ein Substrat, beispielsweise einDCB-Substrat oder ein IMS-Substrat oder ein AMB-Substrat oder ein Stanzgitter, aufgebracht. Unter Belastung, z. B. durch thermomechanische Wechselbelastung, dieser Verbindung bilden sich oft Risse ausgehend vom Rand des Halbleiterchips. Diese Risse weiten sich aus, was zurSuch vertical power semiconductor components are applied, for example, by bonding, soldering or sintering or bonding to a substrate, for example a DCB substrate or an IMS substrate or an AMB substrate or a stamped grid. Under load, z. B. by thermo-mechanical cycling, this compound often form cracks from the edge of the semiconductor chip. These cracks expand, leading to
Ablösung oder zur Zerstörung des Halbleiterchips führen kann. Dabei wirken sich Replacement or destruction of the semiconductor chip may result. This will affect
Unregelmäßigkeiten an der Chipkante, wie z. B. Sägeschäden durch das Vereinzeln, besonders negativ aus. Offenbarung der Erfindung Irregularities on the chip edge, such. B. Sägeschäden by separating, especially negative. Disclosure of the invention
Die Erfindung schafft ein Halbleiterbauelement nach Anspruch 1 und entsprechende Herstellungsverfahren nach Anspruch 10, 11 und 12. Bevorzugte Weiterbildungen sind Gegenstand der jeweiligen Unteransprüche. Vorteile der Erfindung The invention provides a semiconductor device according to claim 1 and corresponding manufacturing method according to claim 10, 11 and 12. Preferred developments are the subject of the respective subclaims. Advantages of the invention
Die der vorliegenden Erfindung zugrunde liegende Idee liegt darin, dass die The idea underlying the present invention is that the
Metallisierungsschicht zur flächigen Montage des Halbleiterchips in einem besipielsweise ringförmigen oder eckigen umlaufenden Bereich entlang des Randes des Halbleiterchips entweder vollständig entfernt oder abgedünnt wird. Metallisierungsschicht for planar mounting of the semiconductor chip in a besipielsweise annular or angular circumferential area along the edge of the semiconductor chip is either completely removed or thinned.
Damit lässt sich ereichen, dass es in dem ringförmigen Bereich keine Ankopplung des Halbleiterchips bei der Montage an ein Substrat mittels einer Verbindungsschicht gibt. Somit gelingt es, die defektbehaftete Kante des Halbleiterchips, an der üblicherweise die Rissbildung beginnt, kräftemäßig zu entkoppeln. Somit ist die Zuverlässigkeit des montierten Halbleiterbauelements wesentlich erhöht. In einer ersten Variante wird die Metallisierungsschicht in dem umlaufenden Bereich vollständig entfernt, beispielsweise mittels eines Ätzprozesses. It can thus be achieved that there is no coupling of the semiconductor chip during assembly to a substrate by means of a connection layer in the annular region. Thus, it is possible to decouple the defective edge of the semiconductor chip, at which usually the cracking begins, in terms of power. Thus, the reliability of the mounted semiconductor device is significantly increased. In a first variant, the metallization layer is completely removed in the circumferential region, for example by means of an etching process.
In einer zweiten Variante wird die Metallisierungsschicht am Rand nur abgedünnt, und zwar vorzugsweise stufenförmig, so dass der dicke Metallisierungsbereich als In a second variant, the metallization layer is only thinned at the edge, preferably in a stepped manner, such that the thick metallization region is
Abstandshalter fungiert. Spacer acts.
In einer Weiterbildung wird der entfernte oder abgedünnte umlaufende Bereich mit einer umlaufenden Isolierschicht derart ausgeglichen, dass er mit der übrigen In one embodiment, the removed or thinned circumferential area is compensated with a circumferential insulating layer so that it with the rest
Metallisierungsschicht im Wesentlichen planar verläuft. Zweckmäßigerweise ist das Material der Isolierschicht vom Material der Verbindungsschicht schlecht oder gar nicht benetzbar, wodurch die Verbindungsschicht bei der Verarbeitung schlecht oder gar nicht an der Isolierschicht haftet und somit auch bei dieser Variante keine Kräfte auf die Kante des Halbleiterchips ausgeübt werden. Es kann auch eine Abfolge von Schichten vorgesehen werden, bei der eine fehlendeMetallization layer is substantially planar. Conveniently, the material of the insulating layer of the material of the connecting layer is poorly or not wettable, whereby the bonding layer in the processing poor or not at the insulating layer adheres and thus no forces are exerted on the edge of the semiconductor chip in this variant. It can also be provided a sequence of layers in which a missing
Benetzung bzw. Anhaftung des Verbindungsmaterials am Rand mindestens der letzten den Halbleiterchip zugewandten Schicht eingebracht ist. Wetting or adhesion of the bonding material is introduced at the edge of at least the last layer facing the semiconductor chip.
Der Halbleiter kann auch beidseitig mit derartigen Metallisierungsschichten versehen werden, falls beispielsweise ein Sandwichaufbau zwischen zwei Substraten gewünscht ist. Ein weiterer Vorteil liegt darin, dass durch die kontrollierte Benetzung ein Herausquetschen des Materials der Verbindungsschicht vermieden wird, was das Risiko eines Kurzschlusses von ober- und Unterseite des Halbleiterchips bei der Fertigung minimiert. The semiconductor can also be provided on both sides with such metallization layers, if, for example, a sandwich construction between two substrates is desired. A further advantage is that controlled wetting avoids squeezing out of the material of the connecting layer, which minimizes the risk of a short circuit of the top and bottom sides of the semiconductor chip during manufacture.
Kurze Beschreibung der Zeichnungen Brief description of the drawings
Weitere Merkmale und Vorteile der vorliegenden Erfindung werden nachfolgend anhand von Ausführungsformen mit Bezug auf die Figuren erläutert. Es zeigen: Further features and advantages of the present invention will be explained below with reference to embodiments with reference to the figures. Show it:
Fig. 1 a eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer ersten Ausführungsform der vorliegenden Erfindung; Fig. 1 b einen Schnitt entlang der Linie A-A' in Fig. 1a; 1 a is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention; Fig. 1b is a section along the line A-A 'in Fig. 1a;
Fig. 2 eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer zweiten Ausführungsform der vorliegenden Erfindung; Fig. 3 eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer dritten Ausführungsform der vorliegenden Erfindung; FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention; FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention;
Fig. 4 eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer vierten Ausführungsform der vorliegenden Erfindung; eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer fünften Ausführungsform der vorliegenden Erfindung; 4 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention; a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention;
Fig. 6a-c schematische Querschnittsansichten zur Erläuterung eines 6a-c are schematic cross-sectional views for explaining a
Herstellungsverfahrens für ein Halbleiterbauelement gemäß der ersten Ausführungsform der vorliegenden Erfindung;  A manufacturing method of a semiconductor device according to the first embodiment of the present invention;
Fig. 7a-c schematische Querschnittsansichten zur Erläuterung eines Fig. 7a-c are schematic cross-sectional views for explaining a
Herstellungsverfahrens für ein Halbleiterbauelement gemäß der zweiten Ausführungsform der vorliegenden Erfindung; und Fig. 8a-c schematische Querschnittsansichten zur Erläuterung einesA manufacturing method of a semiconductor device according to the second embodiment of the present invention; and Fig. 8a-c are schematic cross-sectional views for explaining a
Herstellungsverfahrens für ein Halbleiterbauelement gemäß der dritten Ausführungsform der vorliegenden Erfindung. Ausführungsformen der Erfindung A manufacturing method of a semiconductor device according to the third embodiment of the present invention. Embodiments of the invention
Fig. 1 a zeigt eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer ersten Ausführungsform der vorliegenden Erfindung und Fig. 1 b einen Schnitt entlang der Linie A-A' in Fig. 1a. 1 a shows a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention and FIG. 1 b shows a section along the line A-A 'in FIG. 1 a.
In Fig. 1 bezeichnet Bezugszeichen 1 einen Halbleiterchip in Form eines vertikalen Leistungshalbleiterbauelements, beispielsweise eines IGBTs, welcher eine Vorderseite VS, eine Rückseite RS und einen Rand R aufweist. Bezugszeichen AR bezeichnet einen im Halbleiterchip 1 vorgesehenen rückseitigen Kontaktbereich, beispielsweise einen entsprechenden Diffusionsbereich. Weitere Details des Halbleiterchips sind aus Gründen der Klarheit nicht dargestellt. In Fig. 1, reference numeral 1 denotes a semiconductor chip in the form of a vertical power semiconductor device, for example, an IGBT, which has a front side VS, a back side RS, and an edge R. Reference symbol AR denotes a rear contact area provided in the semiconductor chip 1, for example a corresponding diffusion area. Further details of the semiconductor chip are not shown for reasons of clarity.
Auf der Rückseite RS vorgesehen ist eine Metallisierungsschicht MR, welche über eine Verbindungsschicht VR flächig mit einem Substrat S, beispielsweise einem DCB-Substrat, verbunden ist. Provided on the rear side RS is a metallization layer MR which is connected in a planar manner to a substrate S, for example a DCB substrate, via a connection layer VR.
Die rückseitige Metallisierungsschicht MR ist einem umlaufenden ringförmigen Bereich B entlang des Randes R vollständig entfernt, so dass bei der Montage im Bereich B ein Spalt SP zwischen der Verbindungsschicht VR und der Rückseite RS des Halbleiterchips 1 entsteht. The rear metallization layer MR is completely removed from a circumferential annular region B along the edge R, so that a gap SP arises between the connection layer VR and the rear side RS of the semiconductor chip 1 during assembly in the region B.
Folglich gibt es keine Krafteinkopplung auf die sägefehlerbehaftete Kante R des Consequently, there is no force coupling to the sawtooth edge R of the
Halbleiterchips 1 , was dessen Zuverlässigkeit erheblich steigert. Die Breite d des umlaufenden ringförmigen Bereichs B lässt sich anwendungsspezifisch ermitteln und beträgt üblicherweise einige Prozent des Durchmessers des Halbleiterchips 1. Semiconductor chips 1, which significantly increases its reliability. The width d of the circumferential annular region B can be determined application-specific and is usually a few percent of the diameter of the semiconductor chip 1.
Fig. 2 zeigt eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer zweiten Ausführungsform der vorliegenden Erfindung. Bei der Ausführungsform gemäß Fig. 2 ist der Aufbau identisch wie bei der ersten 2 shows a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. In the embodiment according to FIG. 2, the construction is identical to that of the first one
Ausführungsform gemäß Fig. 1 mit Ausnahme der Tatsache, dass zwischen der Embodiment according to FIG. 1 with the exception that between the
Verbindungsschicht VR und der Rückseite RS des Halbleiterchips 1 kein Spalt, sondern eine Isolierschicht I vorgesehen ist, welche vom Material der Verbindungsschicht VR, beispielsweise Lot, nicht benetzbar ist, sodass es auch bei dieser zweiten Connection layer VR and the back side RS of the semiconductor chip 1 no gap, but an insulating layer I is provided, which is not wettable by the material of the bonding layer VR, for example solder, so that it is also in this second
Ausführungsform keine Krafteinkopplung auf den sägedefektbehafteten Rand R des Halbleiterchips 1 gibt. Die Isolierschicht ist dabei oberflächig bündig mit der rückseitigen Metallisierungsschicht MR. Embodiment no force coupling on the sawing defective edge R of the semiconductor chip 1 are. The insulating layer is superficially flush with the rear metallization MR.
Fig. 3 zeigt eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer dritten Ausführungsform der vorliegenden Erfindung. 3 shows a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
Bei der dritten Ausführungsform gemäß Fig. 3 ist die rückseitige Metallisierungsschicht MR' im ringförmigen Bereich B nicht vollständig entfernt, sondern lediglich stufenförmig abgedünnt, sodass auch hier ein Spalt SP' zwischen der Verbindungsschicht VR und der Rückseite RS des Halbleiterchips 1 bei der Montage entsteht. Obwohl dieser Spalt SP' kleiner als der Spalt der oben beschriebenen ersten Ausführungsform ist, lässt er sich dennoch so dimensionieren, dass er eine Krafteinkopplung auf den Rand R des In the third embodiment according to FIG. 3, the backside metallization layer MR 'is not completely removed in the annular region B, but only thinned stepwise, so that here too a gap SP' arises between the connection layer VR and the backside RS of the semiconductor chip 1 during assembly. Although this gap SP 'is smaller than the gap of the above-described first embodiment, it can still be dimensioned so that it receives a force input to the edge R of the
Halbleiterchips 1 vermeiden kann. Zusätzlich wird die elektrische Einkopplung verbessert, wenn die rückseitige Metallisierungsschicht MR flächig auf der Waferrückseite RS liegt. Der Kontaktwiderstand und die Strombelastung pro Fläche sinken. Can avoid semiconductor chips 1. In addition, the electrical coupling is improved if the backside metallization layer MR lies flat on the wafer back side RS. The contact resistance and the current load per area decrease.
Fig. 4 zeigt eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer vierten Ausführungsform der vorliegenden Erfindung. 4 shows a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.
Bei der vierten Ausführungsform gemäß Fig. 4 weist der Halbleiterchip 1 zusätzlich einen vorderseitigen Kontaktbereich AV auf, welcher über eine vorderseitige In the fourth embodiment according to FIG. 4, the semiconductor chip 1 additionally has a front-side contact area AV, which has a front-side contact area AV
Metallisierungsschicht MV und eine Verbindungsschicht W mit einem weiteren Substrat S' verbunden ist, sodass ein Sandwichaufbau zwischen den Substraten S, S\ erreicht wird. Metallization layer MV and a connection layer W is connected to a further substrate S ', so that a sandwich structure between the substrates S, S \ is achieved.
Bei dieser Ausführungsform ist der ringförmige Bereich B auf der Rückseite R des Halbleiterchips 1 wie bei der zweiten Ausführungsform mit einer Isolierschicht I aufgefüllt, wohingegen der ringförmige Bereich B auf der Vorderseite VS des Halbleiterchips einen Spalt SP wie bei der ersten Ausführungsform aufweist. Selbstverständlich kann der Sandwichaufbau in dieser Hinsicht auch symmetrisch erfolgen, also entweder vorderseitig und rückseitig ein Spalt SP vorgesehen werden oder vorderseitig und rückseitig eine Isolierschicht I vorgesehen werden. In this embodiment, the annular region B on the back side R of the semiconductor chip 1 is filled with an insulating layer I as in the second embodiment, whereas the annular region B on the front side VS of the semiconductor chip has a gap SP as in the first embodiment. Of course, the sandwich structure in this regard can also be symmetrical, ie either front side and rear side, a gap SP can be provided or front and back an insulating layer I can be provided.
Fig. 5 zeigt eine schematische Querschnittsansicht eines Halbleiterbauelements gemäß einer fünften Ausführungsform der vorliegenden Erfindung. 5 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.
Bei der in Fig. 5 gezeigten fünften Ausführungsform ist auf der Rückseite RS des In the fifth embodiment shown in Fig. 5 is on the back of the RS
Halbleiterchips 1 die im Zusammenhang mit Fig. 3 beschriebene gestufte Semiconductor chips 1, the stepped described in connection with FIG
Metallisierungsschicht MR' vorgesehen, wohingegen auf der Vorderseite VS des Metallization MR 'provided, whereas on the front VS of
Halbleiterchips 1 eine entsprechende gestufte vorderseitige Metallisierungsschicht MV vorgesehen ist und wobei vorderseitig und rückseitig ein entsprechender Spalt SP' zwischen der Verbindungsschicht VR bzw. VS und der Rückseite RS bzw. der Vorderseite VS des Halbleiterchips zur Kraftentkopplung vorgesehen ist. Fig. 6a-c sind schematische Querschnittsansichten zur Erläuterung eines Semiconductor chips 1, a corresponding stepped front side metallization MV is provided and wherein the front side and rear side, a corresponding gap SP 'between the connection layer VR or VS and the back side RS and the front side VS of the semiconductor chip for force decoupling is provided. Figs. 6a-c are schematic cross-sectional views for explaining one
Herstellungsverfahrens für ein Halbleiterbauelement gemäß der ersten Ausführungsform der vorliegenden Erfindung.  A manufacturing method of a semiconductor device according to the first embodiment of the present invention.
Gemäß Fig. 6a wird auf der Rückseite RS des Halbleiterchips 1 zunächst ganzflächig die rückseitige Metallisierungsschicht MR aufgebracht. Dies kann beispielsweise durch Sputtern oder Aufdampfen und mit oder ohne zusätzliche galvanische Verstärkung geschehen. According to FIG. 6a, the rear side metallization layer MR is first applied over the full area on the rear side RS of the semiconductor chip 1. This can be done for example by sputtering or vapor deposition and with or without additional galvanic reinforcement.
Weiter mit Bezug auf Fig. 6b erfolgt dann das Aufbringen und Strukturieren einer Next with reference to FIG. 6b, the application and structuring of a
Lackmaske LM auf der rückseitigen Metallisierungsschicht MR, wobei die strukturierteLackmaske LM on the back metallization MR, the structured
Lackmaske LM nur im zum Bereich B komplementären Bereich AB der Rückseite RS des Halbleiterchips 1 vorliegt. Lackmaske LM only in the region B complementary region AB of the back side RS of the semiconductor chip 1 is present.
Mittels eines üblichen Ätzprozesses lässt sich dann die Metallisierungsschicht MR aus dem ringförmigen Bereich B unter Verwendung der strukturierten Lackmaske LM entfernen. By means of a conventional etching process, the metallization layer MR can then be removed from the annular region B using the structured resist mask LM.
Im Anschluss an den Ätzschritt zum Entfernen der Metallisierungsschicht MR aus dem ringförmigen Bereich B erfolgt schließlich das Entfernen bzw. Strippen der Lackmaske LM, was zum Prozesszustand gemäß Fig. 6c führt. Fig. 7a-c sind schematische Querschnittsansichten zur Erläuterung eines Herstellungsverfahrens für ein Halbleiterbauelement gemäß der zweiten Ausführungsform der vorliegenden Erfindung. Gemäß Fig. 7a wird zunächst die Isolierschicht I ganzflächig auf der Rückseite RS des Halbleiterchips 1 vorgesehen, beispielsweise durch Abscheiden eines entsprechenden Siliziumoxyds. Im Bereich B wird anschließend eine ringförmige Lackmaske LM' auf der Isolierschicht I vorgesehen Das Abscheiden kann auch schon vorher in einem anderen Prozess geschehen sein. Subsequent to the etching step for removing the metallization layer MR from the annular region B, the removal or stripping of the resist mask LM finally takes place, which leads to the process state according to FIG. 6c. FIGS. 7a-c are schematic cross-sectional views for explaining a manufacturing method of a semiconductor device according to the second embodiment of the present invention. According to FIG. 7a, first of all the insulating layer I is provided over the whole area on the rear side RS of the semiconductor chip 1, for example by depositing a corresponding silicon oxide. In area B, an annular resist mask LM 'is then provided on the insulating layer I. The deposition can also be done beforehand in another process.
Durch einen üblichen Ätzprozess wird dann mit Bezug auf Fig. 7b die Isolierschicht I hin zum Bereich B komplementären Bereich AB entfernt, sodass eine Aussparung in der Isolierschicht I gebildet wird, welche die Rückseite RS des Halbleiterchips 1 freilegt. Anschließend wird die Lackmaske LM' entfernt bzw. gestrippt. By means of a customary etching process, with reference to FIG. 7b, the insulating layer I is then removed in the region B complementary to the region B, so that a cutout is formed in the insulating layer I exposing the rear side RS of the semiconductor chip 1. Subsequently, the resist mask LM 'is removed or stripped.
Schließlich mit Bezug auf Fig. 7c wird die rückseitige Metallisierungsschicht MR innerhalb der Aussparung V aufgebracht, sodass sie im Wesentlichen planar mit der Isolierschicht I verläuft. Fig. 8a-c sind schematische Querschnittsansichten zur Erläuterung eines Finally, with reference to FIG. 7c, the backside metallization layer MR is deposited within the recess V such that it is substantially planar with the insulating layer I. As shown in FIG. Figs. 8a-c are schematic cross-sectional views for explaining one
Herstellungsverfahrens für ein Halbleiterbauelement gemäß der dritten Ausführungsform der vorliegenden Erfindung.  A manufacturing method of a semiconductor device according to the third embodiment of the present invention.
Gemäß dem Prozesszustand von Fig. 8a wird eine dünne rückseitige According to the process state of Fig. 8a, a thin backside
Metallisierungsschicht MR' auf die Rückseite RS des Halbleiterchips 1 aufgebracht. Metallization layer MR 'applied to the back RS of the semiconductor chip 1.
Anschließend erfolgt das Bilden einer Maske LG aus Galvanik-resistenten Material im Bereich B, was zum Prozesszustand gemäß Fig. 8b führt. Schließlich mit Bezug auf Fig. 8c, erfolgt dann ein selektives galvanisches Verstärken der rückseitigen Metallisierungsschicht MR' im zum Bereich B komplementären Bereich AB. Subsequently, the formation of a mask LG from electroplating-resistant material takes place in region B, which leads to the process state according to FIG. 8b. Finally, with reference to FIG. 8c, a selective galvanic amplification of the rear metallization layer MR 'in the region B complementary to the region AB takes place.
Die Maske LG kann dann entweder als Isolierschicht I analog zur Ausführungsform gemäß Fig. 2 belassen werden, wobei sie dann im Wesentlichen planar mit der übrigen rückseitigen Metallisierungsschicht MR' verläuft, oder sie kann, wie in Fig. 8c durch eine gestrichelte Linie angedeutet, entfernt werden was zur Ausführungsform gemäß Fig. 2 führt. The mask LG can then either be left as an insulating layer I analogous to the embodiment according to FIG. 2, in which case it runs substantially planar with the remaining rear metallization layer MR ', or it can, as in FIG dashed line indicated removed, which leads to the embodiment of FIG.
Obwohl die vorliegende Erfindung vorstehend anhand von zwei Ausführungsbeispielen erläutert wurde, ist sie nicht darauf beschränkt, sondern in vielfältiger Weise variierbar. Although the present invention has been explained above with reference to two embodiments, it is not limited thereto, but varied in many ways.
Obwohl die vorliegende Erfindung anhand von einem Leistungshalbleiterbauelement erläutert wurde, ist sie darauf nicht beschränkt, sondern für alle Halbleiterbauelemente anwendbar, die flächig auf ein Substrat geklebt, gebondet, gelötet, gesintert usw. werden. Although the present invention has been explained with reference to a power semiconductor device, it is not limited thereto, but applicable to all semiconductor devices which are adhered, bonded, soldered, sintered, etc., to a substrate.
Die vorstehend verwendete Bezeichnung Halbleiterchip kann sich sowohl auf Chips beziehen, die aus einem Wafer gesägt wurden, als auch auf ganze Wafer, wobei das Halbleiterbauelement durch den gesamten Wafer gebildet ist. Obwohl die Halbleiterchips der oben beschriebenen Ausführungsformen eine eckige Form aufwiesen, ist die Erfindung nicht auf die eckige Chipform beschränkt, sondern prinzipiell für beliebige Chipgeometrien anwendbar. The term semiconductor chip as used above can refer both to chips which have been sawn from a wafer and to entire wafers, wherein the semiconductor component is formed by the entire wafer. Although the semiconductor chips of the above-described embodiments have a polygonal shape, the invention is not limited to the angular chip shape, but is basically applicable to any chip geometries.

Claims

Ansprüche claims
5 1. Halbleiterbauelement mit: einem Halbleiterchip (1) mit einer ersten Hauptseite (RS) und einer zweiten Hauptseite (VS) und einem Rand (R); 0 wobei mindestens eine der ersten Hauptseite (RS) und der zweiten Hauptseite (VS) eine Metallisierungsschicht (MR; MR'; MV; MV) zur flächigen Montage des Halbleiterchip (1) aufweist; wobei die Metallisierungsschicht (MR; MR'; MV; MV) in einem umlaufenden Bereich (B)5 entlang des Randes (R) des Halbleiterchips (1) entfernt oder abgedünnt ist. A semiconductor device comprising: a semiconductor chip (1) having a first main side (RS) and a second main side (VS) and a rim (R); 0 wherein at least one of the first main side (RS) and the second main side (VS) has a metallization layer (MR; MR '; MV; MV) for planar mounting of the semiconductor chip (1); wherein the metallization layer (MR; MR '; MV; MV) is removed or thinned in a circumferential region (B) 5 along the edge (R) of the semiconductor chip (1).
2. Halbleiterbauelement nach Anspruch 1 , wobei der entfernte bzw. abgedünnte Bereich (B) mit einer Isolierschicht (I) derart ausgeglichen ist, dass er 2. A semiconductor device according to claim 1, wherein the removed or thinned region (B) with an insulating layer (I) is balanced such that it
mit der übrigen Metallisierungsschicht (MR; MR'; MV; MV) im wesentlichen planar o verläuft.  with the remaining metallization layer (MR; MR '; MV; MV) is substantially planar o.
3. Halbleiterbauelement nach Anspruch 1 , wobei die Metallisierungsschicht (MR; MR'; MV; MV) in dem Bereich (B) entlang der gesamten Randes (R) des Halbleiterchips (1) stufenförmig abgedünnt ist.3. The semiconductor device according to claim 1, wherein the metallization layer (MR; MR '; MV; MV) in the region (B) along the entire edge (R) of the semiconductor chip (1) is thinned stepwise.
5 5
4. Halbleiterbauelement nach Anspruch 1 , wobei die Metallisierungsschicht (MR; MR'; MV; MV) über eine Verbindungsschicht (VR; W) mit einem Substrat (S; S') verbunden ist.  4. The semiconductor device according to claim 1, wherein the metallization layer (MR; MR '; MV; MV) is connected to a substrate (S; S') via a connection layer (VR; W).
5. Halbleiterbauelement nach Anspruch 4, wobei in dem Bereich (B) zwischen der 5. A semiconductor device according to claim 4, wherein in the region (B) between the
0 Halbleiterchip (1) und der Verbindungsschicht (VR; W) ein Spalt (SP; SP') vorgesehen ist. 0 semiconductor chip (1) and the connection layer (VR; W) a gap (SP; SP ') is provided.
6. Halbleiterbauelement nach Anspruch 4, wobei in dem umlaufenden Bereich (B) zwischen dem Halbleiterchip (1) und der Verbindungsschicht (VR; VV) eine 6. A semiconductor device according to claim 4, wherein in the circumferential region (B) between the semiconductor chip (1) and the connection layer (VR; VV) a
Isolationsschicht (I) vorgesehen ist, welche vom Material der Verbindungsschicht (VR; W)5 nicht benetzt ist. Insulation layer (I) is provided, which is not wetted by the material of the bonding layer (VR; W) 5.
7. Halbleiterbauelement nach Anspruch 6, wobei die Isolationsschicht (I) aus Oxid besteht. 7. A semiconductor device according to claim 6, wherein the insulating layer (I) consists of oxide.
8. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, wobei der Halbleiterchip (1) ein vertikales Leistungshalbleiterbauelement aufweist. 8. Semiconductor component according to one of the preceding claims, wherein the semiconductor chip (1) has a vertical power semiconductor component.
9. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, wobei beide der ersten Hauptseite (RS) und der zweiten Hauptseite (VS) eine jeweilige 9. The semiconductor device according to one of the preceding claims, wherein both the first main side (RS) and the second main side (VS) a respective
Metallisierungsschicht (MR; MR'; MV; MV) zur flächigen Montage des Halbleiterchip (1) aufweisen und wobei die beiden Metallisierungsschichten (MR; MR'; MV; MV) in einem Bereich (B) entlang der gesamten Randes (R) des Halbleiterchips (1) entfernt oder abgedünnt sind. Metallization layer (MR; MR '; MV; MV) for planar mounting of the semiconductor chip (1) and wherein the two metallization layers (MR; MR'; MV; MV) in a region (B) along the entire edge (R) of the semiconductor chip (1) are removed or thinned.
10. Verfahren zur Herstellung eines Halbleiterbauelements nach Anspruch 1 mit den Schritten: ganzflächiges Aufbringen der Metallisierungsschicht (MR; MR'; MV; MV) auf die 10. A method of manufacturing a semiconductor device according to claim 1, comprising the steps of: applying the metallization layer (MR, MR, MV;
Hauptseite (RS; VS); Bilden einer Maske (LM) auf der Metallisierungsschicht (MR; MR'; MV; MV) in einem zum Bereich (B) komplementären Bereich (AB); Main page (RS; VS); Forming a mask (LM) on the metallization layer (MR; MR '; MV; MV) in a region (AB) complementary to the region (B);
Entfernen der Metallisierungsschicht (MR; MR'; MV; MV) aus dem Bereich (B) unter Verwendung der Maske (LM); und Removing the metallization layer (MR; MR '; MV; MV) from region (B) using the mask (LM); and
Entfernen der Maske (LM). Remove the mask (LM).
1 1. Verfahren zur Herstellung eines Halbleiterbauelements nach Anspruch 2 mit den Schritten: ganzflächiges Aufbringen der Isolierschicht (I) auf die Hauptseite (RS; VS); 1 1. A method for producing a semiconductor device according to claim 2, comprising the steps of: applying the insulating layer (I) to the main side over all surfaces (RS, VS);
Bilden einer Maske (LM1) auf der Isolierschicht im Bereich (B); Forming a mask (LM 1 ) on the insulating layer in the region (B);
Entfernen der Isolierschicht (I) in einem zum Bereich (B) komplementären Bereich (AB) unter Verwendung der Maske (LM1) zum Bilden einer entsprechenden Aussparung (V), innerhalb der die Hauptseite (RS; VS) freiliegt; Aufbringen der Metallisierungsschicht (MR; MR'; MV; MV) in der Aussparung (V); und Entfernen der Maske (Ι_Μ'). Removing the insulating layer (I) in a region (AB) complementary to the region (B) using the mask (LM 1 ) to form a corresponding recess (V) within which the main side (RS, VS) is exposed; Depositing the metallization layer (MR; MR ';MV; MV) in the recess (V); and removing the mask (Ι_Μ ').
12. Verfahren zur Herstellung eines Halbleiterbauelements nach Anspruch 2 oder 3 mit den Schritten: ganzflächiges Aufbringen der Metallisierungsschicht (MR; MR'; MV; MV) auf die Hauptseite (RS; VS); 12. A method for producing a semiconductor component according to claim 2 or 3, comprising the steps of: applying the metallization layer (MR, MR, MV, MV) over the whole area to the main side (RS, VS);
Bilden einer Maske (LG) auf der Metallisierungsschicht (MR; MR'; MV; MV) im Bereich (B), welche einen zum Bereich (B) komplementären Bereich (AB) der Forming a mask (LG) on the metallization layer (MR; MR '; MV; MV) in the region (B) which has a region (AB) complementary to the region (B) of FIG
Metallisierungsschicht (MR; MR"; MV; MV) freilegt; und Metallization layer (MR; MR "; MV; MV) exposed;
Erhöhen der Metallisierungsschicht (MR; MR'; MV; MV) im komplementären Bereich (AB). Increasing the metallization layer (MR; MR '; MV; MV) in the complementary region (AB).
13. Verfahren nach Anspruch 12, wobei das Erhöhen galvanisch durchgeführt wird und die Maske (LG) Galvanik-resistent ist. 13. The method of claim 12, wherein the elevation is performed galvanically and the mask (LG) is electroplated.
14. Verfahren nach Anspruch 12 oder 13, wobei die Maske (LG) entfernt wird. 14. The method of claim 12 or 13, wherein the mask (LG) is removed.
15. Verfahren nach Anspruch 12 oder 13, wobei die Maske (LG) belassen wird und mit der erhöhten Metallisierungsschicht (MR; MR'; MV; MV) im wesentlichen planar verläuft. The method of claim 12 or 13, wherein the mask (LG) is left and extends substantially planar with the raised metallization layer (MR; MR '; MV; MV).
PCT/EP2012/057370 2011-05-30 2012-04-23 Semiconductor component and corresponding production method WO2012163599A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011076662.6 2011-05-30
DE102011076662A DE102011076662A1 (en) 2011-05-30 2011-05-30 Semiconductor component and corresponding manufacturing method

Publications (1)

Publication Number Publication Date
WO2012163599A1 true WO2012163599A1 (en) 2012-12-06

Family

ID=46044655

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2012/057370 WO2012163599A1 (en) 2011-05-30 2012-04-23 Semiconductor component and corresponding production method

Country Status (2)

Country Link
DE (1) DE102011076662A1 (en)
WO (1) WO2012163599A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102022100969A1 (en) 2022-01-17 2023-07-20 Infineon Technologies Ag SEMICONDUCTOR CHIP, CHIP SYSTEM, METHOD OF MAKING A SEMICONDUCTOR CHIP AND METHOD OF MAKING A CHIP SYSTEM

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3896478A (en) * 1971-11-26 1975-07-22 Thomson Csf Mesa type junction inverted and bonded to a heat sink
JPS5816538A (en) * 1981-07-23 1983-01-31 Nec Corp Semiconductor device
USH434H (en) * 1985-02-15 1988-02-02 American Telephone And Telegraph Company, At&T Bell Laboratories Contacts to III-V semiconductors
WO2001015235A1 (en) 1999-08-19 2001-03-01 Infineon Technologies Ag Vertically structured semiconductor power module
US20030022464A1 (en) * 2001-07-26 2003-01-30 Naohiko Hirano Transfer-molded power device and method for manufacturing transfer-molded power device
US20080150128A1 (en) * 2006-12-25 2008-06-26 Siliconware Precision Industries Co., Ltd. Heat dissipating chip structure and fabrication method thereof and package having the same
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process
EP2075835A2 (en) * 2007-12-28 2009-07-01 Robert Bosch Gmbh Diode with stress reducing means

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914045A (en) * 1985-12-19 1990-04-03 Teccor Electronics, Inc. Method of fabricating packaged TRIAC and trigger switch
DE3826736A1 (en) * 1988-08-05 1990-02-08 Siemens Ag METHOD FOR SEPARATING LED CHIP ARRANGEMENTS MONOLITHICALLY PRODUCED ON A SEMICONDUCTOR SUB Wafer
DE10048859B4 (en) * 2000-10-02 2005-12-15 Infineon Technologies Ag Pressure contact arrangement and their use
DE10330571B8 (en) * 2003-07-07 2007-03-08 Infineon Technologies Ag Vertical power semiconductor devices with injection damping agent in the edge area and manufacturing method therefor
JP2008098529A (en) * 2006-10-13 2008-04-24 Toshiba Corp Semiconductor device, and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3896478A (en) * 1971-11-26 1975-07-22 Thomson Csf Mesa type junction inverted and bonded to a heat sink
JPS5816538A (en) * 1981-07-23 1983-01-31 Nec Corp Semiconductor device
USH434H (en) * 1985-02-15 1988-02-02 American Telephone And Telegraph Company, At&T Bell Laboratories Contacts to III-V semiconductors
WO2001015235A1 (en) 1999-08-19 2001-03-01 Infineon Technologies Ag Vertically structured semiconductor power module
US20030022464A1 (en) * 2001-07-26 2003-01-30 Naohiko Hirano Transfer-molded power device and method for manufacturing transfer-molded power device
US20080150128A1 (en) * 2006-12-25 2008-06-26 Siliconware Precision Industries Co., Ltd. Heat dissipating chip structure and fabrication method thereof and package having the same
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process
EP2075835A2 (en) * 2007-12-28 2009-07-01 Robert Bosch Gmbh Diode with stress reducing means

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"LEADLESS DECOUPLING CAPACITOR FABRICATED ON WAFER BACKSIDE", IBM TECHNICAL DISCLOSURE BULLETIN, INTERNATIONAL BUSINESS MACHINES CORP. (THORNWOOD), US, vol. 32, no. 3A, 1 August 1989 (1989-08-01), pages 403/404, XP000049418, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
DE102011076662A1 (en) 2012-12-06

Similar Documents

Publication Publication Date Title
DE60011702T2 (en) Method and structure for connecting layers in a semiconductor device
DE10164502B4 (en) Method for the hermetic encapsulation of a component
DE1965546C3 (en) Semiconductor component
DE102009044641B4 (en) Device with a semiconductor chip and metal foil and a method for producing the device
EP1547162A2 (en) Radiation-emitting semiconductor component and production method
DE2810054A1 (en) ELECTRONIC CIRCUIT DEVICE AND METHOD OF MANUFACTURING IT
DE102013216709B4 (en) SEMICONDUCTOR ARRANGEMENT, METHOD FOR MANUFACTURING A NUMBER OF CHIP ASSEMBLIES AND METHOD FOR MANUFACTURING A SEMICONDUCTOR ARRANGEMENT
DE102016104844B4 (en) Process for producing a chip assembly
DE102014115909B4 (en) Press-pack cell and method for operating a press-pack cell
DE112013006790B4 (en) Semiconductor devices and method of manufacturing a semiconductor device
WO2012034752A1 (en) Carrier substrate for an optoelectronic component, method for producing same and optoelectronic component
DE102016212506A1 (en) Semiconductor device and method of manufacturing a semiconductor device
DE102005009358B4 (en) Solderable Contact and Method of Manufacture
DE102012111520B4 (en) Leadframe-free and die-mounting process-material-free chip packages and methods of forming a leadframe-free and die-mounting process-material-free chip package
DE102017104752B4 (en) Process for transferring semiconductor bodies and semiconductor chip
DE102004027176B4 (en) Method for producing semiconductor components
DE102016103585B4 (en) Process for manufacturing a package with solderable electrical contact
DE102004047522B3 (en) Semiconductor chip having a metal coating structure and method of making the same
DE112012001078B4 (en) Carrier for an optoelectronic structure and optoelectronic semiconductor chip with such a carrier
WO2012163599A1 (en) Semiconductor component and corresponding production method
WO2019158416A1 (en) Method for producing a semiconductor component, and semiconductor component
DE102015218842A1 (en) Method for contacting a contact surface of a semiconductor device and electronic module
WO2009156382A2 (en) Method for production of a thermoelectric apparatus
DE102019209065B4 (en) Semiconductor device and method for producing the semiconductor device
DE102012213555B4 (en) Process for the production of a power semiconductor module

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12719314

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 12719314

Country of ref document: EP

Kind code of ref document: A1