WO2012163024A1 - 针对多步长非一致性内存访问numa架构的内存管理方法及装置 - Google Patents

针对多步长非一致性内存访问numa架构的内存管理方法及装置 Download PDF

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WO2012163024A1
WO2012163024A1 PCT/CN2011/081440 CN2011081440W WO2012163024A1 WO 2012163024 A1 WO2012163024 A1 WO 2012163024A1 CN 2011081440 W CN2011081440 W CN 2011081440W WO 2012163024 A1 WO2012163024 A1 WO 2012163024A1
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memory
node
node group
group
usage status
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PCT/CN2011/081440
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English (en)
French (fr)
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章晓峰
王伟
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华为技术有限公司
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Priority to CN2011800021962A priority Critical patent/CN102439570A/zh
Priority to PCT/CN2011/081440 priority patent/WO2012163024A1/zh
Publication of WO2012163024A1 publication Critical patent/WO2012163024A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture

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  • the present invention relates to the field of memory management technologies, and in particular, to a memory management method and apparatus for multi-step non-uniform memory access NUMA architecture.
  • non-uniform memory access Non-Uniform Memory Access
  • NUMA Non-Uniform Memory Access
  • the memory hierarchy structure is determined according to the memory topology in the BIOS of the basic input/output system during system initialization, and the allocation principle is determined before the memory allocation, that is, the principle of proximity (efficiency priority) or the principle of uniform distribution (bandwidth priority); If the principle of proximity is adopted, the memory is allocated on the node with the smallest access delay. If the memory of the node is full, try to release the memory first. If the requirement is still not met after the release, try to allocate on the node with the second smallest access delay. Memory until the memory is successfully allocated; if the principle of even distribution is adopted, the memory is evenly distributed on all nodes.
  • the memory access latency is non-uniformly distributed, assuming that the access delays are: 100ns, 140ns, 500ns, 900ns, 1040ns.
  • the simple use of the nearest allocation or the average allocation principle cannot balance the current situation of efficiency and bandwidth, that is, if the efficiency is prioritized, the nearest allocation principle is adopted, first in the The 100ns node fails to allocate memory. It needs to try to release the memory first, and then allocate the memory in the 140ns delay node. The difference between the 100ns delay and the 140ns delay has little effect on the performance, which makes the allocation overhead large and can only utilize the single node bandwidth.
  • Bandwidth priority using the principle of uniform distribution, requires a large number of cross-node access, affecting system efficiency.
  • the object of the invention is a memory management method and device for multi-step non-uniform memory access NUMA architecture, which can utilize the characteristics of multi-step non-uniform memory access architecture, effectively balance efficiency and bandwidth, and improve memory management performance of the system. .
  • a memory management method for a multi-step non-uniform memory access NUMA architecture comprising:
  • the node group is determined according to the memory access delay information of each node and the user configuration information;
  • the memory is allocated on the idle node group with the smallest memory access delay
  • memory is allocated to nodes within the node group according to the memory usage status of the nodes in the node group.
  • a memory management device for multi-step non-uniform memory access NUMA architecture comprising:
  • a node group setting module configured to determine a node group according to memory access delay information and user configuration information of each node during system initialization
  • a memory usage monitoring module configured to acquire a memory usage status of each node group and a node in the group, where the memory usage status includes a memory usage ratio and an idle status indication;
  • a node group selection module configured to allocate memory on a free node group with the smallest memory access delay according to the memory usage status of each node group when the system initiates a node memory allocation request;
  • a memory allocation module configured to allocate, in the selected node group, a memory to a node in the node group according to a memory usage status of a node in the node group.
  • the method includes: determining, during system initialization, a node group according to memory access delay information and user configuration information of each node; acquiring memory usage of each node group and nodes in the group a status, the memory usage status includes a memory usage ratio and an idle status indication; when the system initiates a node memory allocation request, according to the memory usage status of each node group, selecting to allocate memory on the idle node group with the smallest memory access delay; Within the selected node group, memory is allocated to nodes in the node group according to the memory usage status of the nodes in the node group.
  • FIG. 1 is a schematic flowchart of a memory management method for a multi-step non-uniform memory access NUMA architecture according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of an original memory topology in a specific example according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a topology structure of an improved node group in a specific example according to an embodiment of the present invention.
  • FIG. 4 is another schematic structural diagram of an improved node group topology in a specific example according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a memory management apparatus according to an embodiment of the present invention.
  • the embodiment of the invention provides a memory management method and device for multi-step non-uniform memory access NUMA architecture, and the method and the device can utilize the characteristics of the multi-step non-uniform memory access architecture to effectively balance efficiency and bandwidth. Improves the memory management performance of the system.
  • FIG. 1 is a schematic flowchart of a memory management method for a multi-step non-uniform memory access NUMA architecture according to an embodiment of the present invention. include:
  • Step 11 When the system is initialized, the node group is determined according to the memory access delay information of each node and the user configuration information.
  • the node group Node is determined according to the memory access delay information of each node and the user configuration information setting.
  • Group structure specifically:
  • the delay of the CPU accessing different memory is different, and different access delays will separate one node.
  • the memory delay information of each node is obtained, and then the nodes with similar delay differences are combined into one node group according to the configuration strategy of the user. For example, nodes with delay differences less than 50% can be combined into one node group.
  • FIG. 2 is a schematic diagram of an original memory topology in a specific example according to an embodiment of the present invention:
  • Example 1 The solution of the embodiment of the present invention can generate an optimized Node by using a configuration policy (Config user configuration or system initialization automatic configuration).
  • Group topology 1 FIG. 3 is a schematic diagram of an improved node group topology structure in a specific example of the embodiment of the present invention, if we formulate rules in the Config user configuration or system initialization policy: the access delay difference is 50%
  • the merge within is a node group.
  • the memory access delays are 100ns, 140ns, 900ns, and 1040ns respectively.
  • the nodes of 100ns and 140ns are merged into one node, and the nodes of 900ns and 1040ns are merged into one node, thus generating the graph as shown in Figure 3.
  • Node A Node B...Node H node has an access delay of 100 ns
  • Node Group AB Node Group CD
  • Node Group EF Node Group GH internal access delay is 140ns
  • Node Group ABCD Node The access delay in Group EFGH is 300ns
  • the access delay in Node Group ABCDEFGH is 1040ns.
  • Example 2 In the same manner as the first case, the embodiment of the present invention can generate the optimized topology structure 2 according to the configuration policy.
  • FIG. 4 is another schematic structural diagram of the improved node group topology in the specific example of the embodiment of the present invention. If the configuration strategy is set to: merge nodes with delay differences less than 3 times into one node group. The system memory latency is 100ns, 140ns, 300ns, and 1040ns, respectively. Then, according to the above configuration strategy, the nodes of 100 ns, 140 ns, and 300 ns are merged into one node group, thereby generating a topology as shown in FIG. 4, in FIG. 4: Node Group ABCD, Node Group The delay within EFGH is less than 300ns, and the delay within Node Group ABCDEFGH is less than 1040ns.
  • Step 12 Obtain the memory usage status of each node group and the nodes in the group.
  • each node group Node can be monitored through the memory usage monitoring module by setting a memory usage monitoring module in the memory management architecture.
  • the memory usage status includes the memory usage ratio and the idle status indication, such as the monitoring status shown in Table 1 below:
  • Step 13 When the system initiates a node memory allocation request, according to the memory usage status of each node group, the memory is allocated on the idle node group with the smallest memory access delay.
  • this step when the system initiates a node memory allocation request and needs to allocate memory to the nodes in the system, first select the corresponding node group according to the memory usage status of each node group, that is, select the idle node with the smallest memory access delay. Allocate memory on the group and then perform subsequent operations within the selected node group.
  • Step 14 In the selected node group, allocate memory to the nodes in the node group according to the memory usage status of the nodes in the node group.
  • a memory allocation policy may be selected according to the memory usage status of the nodes in the node group in the selected node group, and the memory is allocated to the node group. Inside the node.
  • the selected memory allocation policy is bandwidth priority
  • the memory is evenly distributed on each node according to the memory usage status of each node in the selected node group
  • the selected memory allocation policy is delay priority, the memory is allocated on the node with the smallest delay in the selected node group;
  • the selected memory allocation policy is the default Default, the memory is randomly assigned to the node within the selected node group.
  • the characteristics of the multi-step non-uniform memory access architecture can be utilized, the efficiency and bandwidth are effectively considered, and the memory management performance of the system is improved.
  • FIG. 5 is a schematic structural diagram of a memory management device according to an embodiment of the present invention, where the device includes:
  • the node group setting module is configured to determine a node group according to the memory access delay information and the user configuration information of each node during system initialization, and the specific implementation manner is as described in the foregoing method embodiment.
  • the memory usage monitoring module is configured to obtain a memory usage status of each node group and a node in the group, where the memory usage status includes a memory usage ratio and an idle state indication, and the specific implementation manner is as described in the foregoing method embodiment.
  • the node group selection module is configured to allocate memory on the idle node group with the smallest memory access delay according to the memory usage status of each node group when the system initiates the node memory allocation request, and the specific implementation manner is as described in the foregoing method embodiment. .
  • a memory allocation module configured to allocate a memory to a node in the node group according to a memory usage status of a node in the node group in a selected node group, as described in the foregoing method embodiment.
  • the memory allocation module may further include:
  • the bandwidth priority allocation module is configured to allocate the memory evenly on each node according to the memory usage status of each node in the selected node group when the selected memory allocation policy is bandwidth priority.
  • the delay priority allocation module is configured to allocate memory to the node with the smallest delay in the selected node group when the selected memory allocation policy is delay priority.
  • the default allocation module is configured to randomly allocate memory to the node within the selected node group when the selected memory allocation policy is the default Default.
  • each module included is only divided according to functional logic, but is not limited to the above division, as long as the corresponding function can be implemented; in addition, the specific name of each functional unit It is also for convenience of distinguishing from each other and is not intended to limit the scope of protection of the present invention.
  • the storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • the method and the device can utilize the characteristics of the multi-step non-uniform memory access architecture, effectively balancing efficiency and bandwidth, and improving the memory management performance of the system.

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Abstract

一种针对多步长非一致性内存访问NUMA架构的内存管理方法及装置，所述方法包括：在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组；获取各个节点组及组内节点的内存使用状况，所述内存使用状况包括内存使用比例和空闲状态指示；当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存；在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上。通过该方法，就能够利用多步长非一致性内存访问架构的特点，有效兼顾效率和带宽，提高了***的内存管理性能。

Description

针对多步长非一致性内存访问NUMA架构的内存管理方法及装置
技术领域
本发明涉及内存管理技术领域，尤其涉及一种针对多步长非一致性内存访问NUMA架构的内存管理方法及装置。
发明背景
目前，非一致性内存访问（Non-Uniform Memory Access，NUMA）架构已经成为服务器领域的主流***架构，为了解决Numa架构下远近端内存访问开销差别大的问题，新型的多步长层次型NUMA架构的应用越来越广泛。现有技术中，内存层级结构在***初始化时根据基础输入输出***BIOS中的内存拓扑结构来确定，内存分配前先确定分配原则，即就近原则（效率优先）或均匀分配原则（带宽优先）；若采取就近原则，则优先在访问延迟最小的节点上分配内存，若该节点内存已满，先尝试释放内存，若释放后仍达不到要求，再尝试在访问延迟第二小的节点上分配内存，直至成功分配内存；若采取平均分配的原则，则在所有的节点上平均分配内存。
在多步长Multi-hop的内存架构下，内存访问延迟是非均匀分布的，假设访问延迟分别为：100ns,140ns, 500ns, 900ns, 1040ns。现有技术方案中，若对每一步长均设置一个节点，则单纯的使用就近分配或平均分配原则就无法兼顾效率和带宽的现状，也就是说：若效率优先，采用就近分配原则，首先在100ns节点分配内存失败，需先尝试释放内存，再在140ns延迟节点分配内存，而100ns延迟和140ns延迟的差别对性能影响并不大，这样就使得分配开销大且仅能利用单节点带宽；若带宽优先，采用均匀分配原则，则需要大量的跨节点访问，影响了***效率。
发明内容
本发明的目的是针对多步长非一致性内存访问NUMA架构的内存管理方法及装置，能够利用多步长非一致性内存访问架构的特点，有效兼顾效率和带宽，提高了***的内存管理性能。
一种针对多步长非一致性内存访问NUMA架构的内存管理方法，所述方法包括：
在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组；
获取各个节点组及组内节点的内存使用状况，所述内存使用状况包括内存使用比例和空闲状态指示；
当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存；
在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上。
一种针对多步长非一致性内存访问NUMA架构的内存管理装置，所述装置包括：
节点组设置模块，用于在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组；
内存使用监控模块，用于获取各个节点组及组内节点的内存使用状况，所述内存使用状况包括内存使用比例和空闲状态指示；
节点组选择模块，用于当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存；
内存分配模块，用于在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上。
由上述所提供的技术方案可以看出，所述方法包括：在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组；获取各个节点组及组内节点的内存使用状况，所述内存使用状况包括内存使用比例和空闲状态指示；当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存；在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上。通过该方法，就能够利用多步长非一致性内存访问架构的特点，有效兼顾效率和带宽，提高了***的内存管理性能。
附图简要说明
图1为本发明实施例所提供的针对多步长非一致性内存访问NUMA架构的内存管理方法的流程示意图；
图2为本发明实施例所举出的具体实例中原有内存拓扑结构的示意图；
图3为本发明实施例所举出的具体实例中改进的节点组拓扑结构示意图；
图4为本发明实施例所举出的具体实例中改进的节点组拓扑另一结构示意图；
图5为本发明实施例所提供的内存管理装置的结构示意图。
实施本发明的方式
本发明实施方式提供了一种针对多步长非一致性内存访问NUMA架构的内存管理方法及装置，通过该方法及装置能够利用多步长非一致性内存访问架构的特点，有效兼顾效率和带宽，提高了***的内存管理性能。
下面结合附图来对本发明的具体实施例进行详细说明，如图1所示为本发明实施例所提供的针对多步长非一致性内存访问NUMA架构的内存管理方法的流程示意图，所述方法包括：
步骤11：在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组。
在该步骤中，在操作***初始化时，根据各节点的内存访问延时信息及用户配置信息设置，确定节点组Node Group结构，具体来说：
由于内存硬件所处位置的不同，CPU访问不同内存的延迟是不同的，不同的访问延迟就会独立出一个节点。首先获取各节点的内存延迟信息，然后根据用户的配置策略，将延迟差别相近的节点合并为一个节点组，例如可以将延迟差别小于50%的节点合并为一个节点组。
下面以具体的实例来进行说明，如图2所示为本发明实施例所举出的具体实例中原有内存拓扑结构的示意图：
若多步长Multi-hop架构下的原内存拓扑如图2所示，若Node A,Node B…Node H节点内访问延迟为100ns；Node Group AB,Node Group CD,Node Group EF,Node Group GH内访问延迟为140ns；Node Group ABCD,Node Group EFGH内访问延迟为900ns；Node Group ABCDEFGH内访问延迟为1040ns；现有技术中，不同的访问延迟就会独立出一个节点，这样就会生成如图2所示的原有内存拓扑结构。这里100ns和140ns,900ns和1040ns的访问延迟差别并不大，原有过于复杂的层级结构影响了分配效率，和管理复杂度。
实例1：本发明实施例的方案可通过配置策略(Config用户配置或***初始化自动配置)，生成优化后的Node Group拓扑结构1，图3所示为本发明实施例所举出的具体实例中改进的节点组拓扑结构示意图，假如我们在Config用户配置或***初始化策略里制定规则：将访问延迟差距在50%以内的合并为一个节点组。首先获得内存访问延迟分别为100ns,140ns,900ns,1040ns；再根据以上的策略规则，将100ns和140ns的节点合并为一个节点，将900ns和1040ns的节点合并为一个节点，从而生成如图3所示的拓扑结构，图3中：Node Group AB，Node Group CD, Node Group EF, Node Group GH内延迟为小于140ns, Node Group ABCDEFGH内延迟为小于1040ns。
在举一个例子，若 Node A,Node B…Node H节点内访问延迟为100ns；Node Group AB,Node Group CD,Node Group EF,Node Group GH内访问延迟为140ns；Node Group ABCD,Node Group EFGH内访问延迟为300ns；Node Group ABCDEFGH内访问延迟为1040ns。
实例2:同案例一，本发明实施例可根据配置策略生成优化后的拓扑结构2，如图4所示为本发明实施例所举出的具体实例中改进的节点组拓扑另一结构示意图，假如制定的配置策略为：将延迟差别小于3倍以内的节点合并成一个节点组。***内存延迟分别为100ns,140ns,300ns,1040ns。那么根据以上的配置策略，将100ns,140ns,300ns的节点合并成一个节点组，从而生成如图4所示的拓扑结构，图4中：Node Group ABCD,Node Group EFGH内延迟小于300ns,Node Group ABCDEFGH内延迟小于1040ns。
步骤12：获取各个节点组及组内节点的内存使用状况。
在该步骤中，可以通过在内存管理架构中设置内存使用状况监控模块，通过该内存使用状况监控模块来监控各个节点组Node Group和节点组内各个Node 的内存使用情况，所述内存使用状况包括内存使用比例和空闲状态指示，例如如下表1所示的监控状态：
Node ABCD Node EFGH Node AB Node CD Node EF Node GH ... Node G Node H
内存使用比例 40% 60% 20% 60% 80% 40% ... 10% 25%
表1
步骤13：当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存。
在该步骤中，当***发起节点内存分配请求，需要将内存分配到***内节点时，首先根据各个节点组的内存使用状况，先选择相应的节点组，即选择在内存访问延迟最小的空闲节点组上分配内存，然后在所选择的节点组内进行后继的操作。
步骤14：在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上。
在该步骤中，在进行上述步骤13的操作之后，就可以在所选择的节点组内，根据所述节点组内节点的内存使用状况，选择相应的内存分配策略将内存分配到所述节点组内的节点上。
具体来说，可以包括以下几种情况：
若选择的内存分配策略为带宽优先，则根据所选择的节点组内各节点的内存使用状况，将内存平均分配在各个节点上；
若选择的内存分配策略为延迟优先，则将内存分配在所选择的节点组内延迟最小的节点上；
若选择的内存分配策略为默认Default，则将内存在所选择的节点组内随机分配到节点上。
通过上述技术方案的实施，就可以利用多步长非一致性内存访问架构的特点，有效兼顾效率和带宽，提高了***的内存管理性能。
本发明实施方式还提供了一种针对多步长非一致性内存访问NUMA架构的内存管理装置，如图5所示为本发明实施例所提供的内存管理装置的结构示意图，所述装置包括：
节点组设置模块，用于在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组，具体实现方式见以上方法实施例中所述。
内存使用监控模块，用于获取各个节点组及组内节点的内存使用状况，所述内存使用状况包括内存使用比例和空闲状态指示，具体实现方式见以上方法实施例中所述。
节点组选择模块，用于当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存，具体实现方式见以上方法实施例中所述。
内存分配模块，用于在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上，具体实现方式见以上方法实施例中所述。
另外，在具体实现过程中，所述内存分配模块还可以包括：
带宽优先分配模块，用于当所选择的内存分配策略为带宽优先时，根据所选择的节点组内各节点的内存使用状况，将内存平均分配在各个节点上。
或，延迟优先分配模块，用于当所选择的内存分配策略为延迟优先时，将内存分配在所选择的节点组内延迟最小的节点上。
或，默认分配模块，用于当所选择的内存分配策略为默认Default时，将内存在所选择的节点组内随机分配到节点上。
值得注意的是，上述装置实施例中，所包括的各个模块只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本发明的保护范围。
另外，本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件完成，相应的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
综上所述，通过该方法及装置就能够利用多步长非一致性内存访问架构的特点，有效兼顾效率和带宽，提高了***的内存管理性能。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种针对多步长非一致性内存访问NUMA架构的内存管理方法，其特征在于，所述方法包括：
    在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组；
    获取各个节点组及组内节点的内存使用状况，所述内存使用状况包括内存使用比例和空闲状态指示；
    当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存；
    在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上。
  2. 根据权利要求1所述的方法，其特征在于，所述在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上，具体包括：
    若选择的内存分配策略为带宽优先，则根据所选择的节点组内各节点的内存使用状况，将内存平均分配在各个节点上；
    若选择的内存分配策略为延迟优先，则将内存分配在所选择的节点组内延迟最小的节点上；
    若选择的内存分配策略为默认Default，则将内存在所选择的节点组内随机分配到节点上。
  3. 根据权利要求1所述的方法，其特征在于，所述空闲节点组为内存分配为空的节点组。
  4. 根据权利要求1所述的方法，其特征在于，所述根据各节点的内存访问延时信息及用户配置信息，确定节点组，具体包括：
    获取各节点的内存访问延迟信息，将内存访问延迟差别相近的节点合并为一个节点组。
  5. 根据权利要求1所述的方法，其特征在于，所述获取各个节点组及组内节点的内存使用状况，具体包括：
    通过在***中所设置的内存使用监控模块来获取各个节点组及组内节点的内存使用状况。
  6. 根据权利要求1所述的方法，其特征在于，所述节点内存分配请求具体为：
    将内存分配到***内节点的请求。
  7. 一种针对多步长非一致性内存访问NUMA架构的内存管理装置，其特征在于，所述装置包括：
    节点组设置模块，用于在***初始化时，根据各节点的内存访问延时信息及用户配置信息，确定节点组；
    内存使用监控模块，用于获取各个节点组及组内节点的内存使用状况，所述内存使用状况包括内存使用比例和空闲状态指示；
    节点组选择模块，用于当***发起节点内存分配请求时，根据各个节点组的内存使用状况，选择在内存访问延迟最小的空闲节点组上分配内存；
    内存分配模块，用于在所选择的节点组内，根据所述节点组内节点的内存使用状况，将内存分配到所述节点组内的节点上。
  8. 如权利要求7所述的内存管理装置，其特征在于，所述内存分配模块包括：
    带宽优先分配模块，用于当所选择的内存分配策略为带宽优先时，根据所选择的节点组内各节点的内存使用状况，将内存平均分配在各个节点上。
  9. 如权利要求7所述的内存管理装置，其特征在于，所述内存分配模块包括：
    延迟优先分配模块，用于当所选择的内存分配策略为延迟优先时，将内存分配在所选择的节点组内延迟最小的节点上。
  10. 如权利要求7所述的内存管理装置，其特征在于，所述内存分配模块包括：
    默认分配模块，用于当所选择的内存分配策略为默认Default时，将内存在所选择的节点组内随机分配到节点上。
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