WO2012149724A1 - 一种快速通道互连链路监控方法和设备及*** - Google Patents
一种快速通道互连链路监控方法和设备及*** Download PDFInfo
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- WO2012149724A1 WO2012149724A1 PCT/CN2011/079326 CN2011079326W WO2012149724A1 WO 2012149724 A1 WO2012149724 A1 WO 2012149724A1 CN 2011079326 W CN2011079326 W CN 2011079326W WO 2012149724 A1 WO2012149724 A1 WO 2012149724A1
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- cyclic redundancy
- redundancy code
- code check
- routing table
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/16—Threshold monitoring
Definitions
- the embodiments of the present invention relate to the field of computer technologies, and in particular, to a fast channel interconnect link monitoring method, device, and system. Background technique
- the core technology of the minicomputer is the interconnection architecture between the central processing units (CPUs), and the stability of the interconnection architecture is mainly determined by the fast path interconnection (QPI, Quick Path). Interconnect) Signal integrity.
- the prior art uses the method of quantitative testing QPI signal integrity (SI, Signal Integrality), through Intel (Intel) QPI load detection board (QLB, QPI Load Board) with oscilloscope and Intel fast channel
- the monitoring tool kit (QTK, QuickPath Tool Kit) and sigtest software are used to test the signal integrity of the QPI signal.
- QLP detects the QPI signal transmission to the oscilloscope, then the oscilloscope outputs the waveform file to the sigtest software running in the computer, and finally by sigtest.
- the software outputs the test results.
- test solutions require separate test equipment (such as load test boards and oscilloscopes) and separate test software (such as QTK and sigtest) to perform the test, which requires higher test costs and is more complex to operate.
- Embodiments of the present invention provide a fast channel interconnect link monitoring method, device, and system, which can implement monitoring of a QPI link with low test cost, and is simple to operate.
- the fast channel interconnect link monitoring device acquires cyclic redundancy code check error information and routing table information of the system under test SUT, and the cyclic redundancy code check error information includes a cyclic redundancy code check error code number and Fast channel interconnect link retransmission times;
- the fast channel interconnect link monitoring device determines whether the number of times of the cyclic redundancy code check error exceeds a preset cyclic redundancy code check error threshold, and obtains a first judgment result; If the first determination result is that the cyclic redundancy code check error number exceeds the preset cyclic redundancy code check error threshold, the fast channel interconnect link monitoring device will be the first
- the determination result and the routing table information are mapped to a first graphical interface, and the first graphical interface is configured to display a fast between the nodes of the system to be tested according to the first determination result and the routing table information.
- the fast channel interconnect link monitoring device determines the fast Whether the number of retransmissions of the channel interconnection link exceeds a preset fast channel interconnection link retransmission threshold, and obtains a second judgment result;
- the fast channel interconnect link monitoring device maps the second determination result and the routing table information to a second graphical interface, and the second graphical interface is configured to use the second determination result and the The routing table information displays the fast channel interconnect link connection status between the nodes of the system under test.
- An acquiring unit configured to acquire cyclic redundancy code check error information and routing table information of the system SUT of the system to be tested, where the cyclic redundancy code check error information includes a cyclic redundancy code check error number and a fast channel mutual The number of link retransmissions;
- a first determining unit configured to determine whether the number of times of the cyclic redundancy code check error exceeds a preset cyclic redundancy code check error threshold, and obtain a first judgment result
- a first mapping unit configured to: when the first determination result is that the cyclic redundancy code check error number exceeds the preset cyclic redundancy code check error threshold, the first determining result And the routing table information is mapped to a first graphical interface, where the first graphical interface is configured to display, according to the first determination result and the routing table information, a fast channel interaction between nodes of the system to be tested. Link connection status;
- a second determining unit configured to determine, when the first determining result is that the cyclic redundancy code check error number does not exceed a preset cyclic redundancy code check error threshold, determine the fast channel interconnect chain Whether the number of retransmissions exceeds a preset fast channel interconnection link retransmission threshold, and obtains a second judgment result;
- a fast channel interconnection link monitoring system includes: a system to be tested SUT, and a fast channel interconnection chain capable of displaying a fast channel interconnection link connection state between nodes of the system to be tested Road monitoring equipment, wherein
- the fast channel interconnect link monitoring device is configured to acquire cyclic redundancy code check error information and routing table information of the system to be tested, and the cyclic redundancy code check error information includes a cyclic redundancy code.
- the first determination result is that the number of times of the cyclic redundancy code check error exceeds the preset cyclic redundancy code check error threshold, and the first judgment result and the routing table information are mapped to the first a graphical interface, the first graphical interface is configured to display a fast channel interconnection link connection state between nodes of the system under test according to the first determination result and the routing table information;
- the first judgment result is that the number of times of the cyclic redundancy code check error does not exceed the preset
- Fast channel interconnect link heavy Threshold obtaining a second determination result; mapping the second determination result and the routing table information to a second graphical interface, wherein the second graphical interface is configured to use the second determination result and the routing table
- the information shows the fast track interconnect link connection status between the nodes of the system under test.
- the embodiments of the present invention have the following advantages:
- the fast channel interconnect link monitoring device After the fast channel interconnect link monitoring device acquires the cyclic redundancy code check error information and the routing table information of the system to be tested, the fast channel interconnect link monitoring device is in the cyclic redundancy code school.
- the first judgment result and the routing table information are mapped to the first graphical interface, and the number of error corrections in the cyclic redundancy code does not exceed the pre-predicate
- the second judgment result is obtained by judging whether the fast channel interconnection link retransmission times exceed the preset fast channel interconnection link retransmission threshold, and the second judgment is obtained.
- the result and routing table information are mapped to a second graphical interface.
- the method for obtaining the cyclic redundancy code check error information and the routing table information of the system to be tested in the embodiment of the present invention can be obtained by using a software device (that is, the fast channel interconnect link monitoring device in the embodiment of the present invention).
- a software device that is, the fast channel interconnect link monitoring device in the embodiment of the present invention.
- the fast channel interconnect link monitoring device can be mapped by the first judgment result or the second judgment result in combination with the routing table information.
- the resulting graphical interface does not require a separate test device (ie, no need to add an oscilloscope) to convert the waveform file output to a test software sigtest.
- the embodiment of the invention can display the QPI link connection status in real time through the graphical interface, thereby reducing the test cost, and the operation process is simple and easy to implement.
- FIG. 1 is a schematic diagram of an embodiment of a fast channel interconnect link monitoring method according to an embodiment of the present invention
- FIG. 2 is a system networking diagram of a method for monitoring a fast-path interconnect link according to an embodiment of the present invention
- FIG. 3 is a schematic diagram of another embodiment of a method for monitoring a fast-path interconnect link according to an embodiment of the present invention
- FIG. 4 is a schematic diagram of real-time monitoring of a fast-path interconnect link according to an embodiment of the present invention
- FIG. 5 is a schematic diagram of an embodiment of a fast-channel interconnect link monitoring device according to an embodiment of the present invention.
- Embodiments of the present invention provide a fast channel interconnect link monitoring method, device, and system, which can implement monitoring of a QPI link with low test cost, and is simple to operate.
- the action main body of the fast channel interconnect link monitoring method is a fast channel interconnect link monitoring device.
- the fast channel interconnect link monitoring device may be integrated in a single The board administrator (OA, OnBoard Administrator) is implemented on the management software. Users can use the PC (Personal Computer) control machine to access the board management software through the network to realize real-time monitoring of the fast channel interconnection link.
- the fast channel interconnect link monitoring device can also be a stand-alone device installed in the single board manager service in the manner of software control hardware. On the device, the user can use the normal PC controller to realize real-time monitoring of the fast-channel interconnect link through the fast-channel interconnect link monitoring device.
- the fast channel interconnect link monitoring device can also be implemented as a stand-alone device installed on a common PC control machine in the manner of software control hardware. The specific implementation manner is not limited herein.
- the fast channel interconnect link monitoring device provided by the embodiment of the present invention is implemented in a fast channel interconnect link monitoring system.
- the monitoring system may specifically include: a fast channel interconnect link monitoring device, a general PC controller, a board administrator server, a system to be tested, and a switch.
- the ordinary PC control machine accesses the OA server through a network connection through a switch.
- an embodiment of a fast channel interconnect link monitoring method includes:
- the fast channel interconnect link monitoring device obtains cyclic redundancy code check error information and routing table information of the system to be tested.
- the cyclic redundancy code check error information includes the cyclic redundancy code check error code number and the fast channel interconnect link retransmission times.
- a fast channel interconnect link monitoring device (hereinafter referred to as a fast channel interconnect link monitoring device is simply referred to as a QPI link monitoring device)
- a QPI link monitoring device Obtain the cyclic redundancy check of the SUT (CRC, Cyclic Redundancy
- the system to be tested is a collection of nodes that the QPI link monitoring device needs to monitor.
- the system under test includes a master node and multiple nodes.
- the master node in the system to be tested and the central processing unit (CPU) of each node have active and local links.
- the other nodes in the connection establish a connection.
- the link layer parameters are exchanged between them.
- the master node and each node get the slot information and port information of other nodes and the transmission rate.
- the CPU of the primary node and each node enters a wait state.
- the CPU of the master node in the system under test will establish a routing table and store the routing table information.
- the routing table is used to record routing information of all nodes in the system under test (where all nodes include the master node and each node).
- all nodes include the master node and each node.
- the CPU of the master node can discover all the slots in the network through the breadth-first search algorithm to implement the routing table.
- QPI link retransmission times when the QPI link transmits data, if the link layer finds a CRC error After that, the CPU error count register in the system under test records the number of CRC errors. When the link layer finds the CRC error, the QPI link will try to self-heal and retransmit the data. The QPI link retransmission times register in the system under test records the number of QPI link retransmissions.
- the QPI link monitoring device can obtain multiple implementations of the CRC error information and the routing table information of the SUT.
- One implementation manner is as follows:
- the QPI link monitoring device obtains CRC error information and routing table information of the system to be tested through the OA server connected to itself.
- the OA server can obtain the CRC error information and the routing table information of the system to be tested, and can be implemented as follows:
- the OA server manages the board from the system to be tested through the Intelligent Platform Management Interface (IPMI).
- the BMC Board Base Management Controller
- the information transmission between the BMC and the OA server of the system under test is implemented by IPMI.
- the BMC of the system under test transmits CRC error information and routing table information to the OA server through IMPI.
- the BMC acquiring the routing table information of the system to be tested may adopt the following manner: first, after the primary node of the system to be tested exchanges the link layer parameters between all nodes of the system to be tested. Establish routing table information of the system to be tested. Then, the BMC of the system under test obtains routing table information from the primary node. The BMC of the system to be tested obtains the routing table information from the primary node, and may adopt multiple implementation manners. One achievable manner is: the basic input and output system (BIOS, Basic Input Output System) of the primary node passes through the keyboard.
- BIOS Basic Input Output System
- the controller specification interface (KCS, Keyboard Controller Style Interface) sends routing table information to the BMC of the system under test, and the BMC of the system under test can receive the routing table information sent by the BIOS of the primary node through the KCS.
- KCS Keyboard Controller Style Interface
- Another achievable way is that the BMC of the system under test reads the CPU-related registers of the master node through the system management bus (SMBUS, System Management Bus) and parses out the routing table information.
- the CPU related register refers to three registers included in each of the 12 QPI ports included in the CPU of the master node, and the three registers are the Router Table Configuration Register and the route read. Register (Reader Register), Router Write Register.
- the BMC of the system to be tested can obtain the CRC error information by using the following manner:
- the BMC of the system to be tested reads the CRC error information of the node of the system to be tested through the system management bus.
- the CRC error information in the embodiment of the present invention includes a CRC error code. Number and number of QPI link retransmissions.
- the fast channel interconnect link monitoring device determines whether the number of times of the cyclic redundancy code check error exceeds a preset cyclic redundancy code check error threshold, and obtains a first judgment result. If the first judgment result is that the cyclic redundancy code check error number exceeds the preset cyclic redundancy code check error threshold, the trigger operation 103 is performed, and if the first judgment result is that the cyclic redundancy code check error number is not Exceeding the preset cyclic redundancy code check error threshold, trigger operation 104 is performed.
- the QPI link monitoring device determines whether the CRC error number exceeds a preset CRC error threshold, and obtains The first judgment result.
- the first judgment result indicates a numerical relationship between the number of CRC errors acquired by the QPI link monitoring device and the preset CRC error threshold.
- the QPI link is abnormal, and the QPI link monitoring device triggers the operation 103, when the first judgment result is that the CRC error number does not exceed the CRC error threshold.
- the QPI link monitoring device triggers operation 104 to execute.
- the setting of the CRC error threshold may be preset according to a specific application scenario.
- the CRC error threshold may be set smaller according to the actual needs of the user, and the CRC error threshold may also be set. It is larger, but it cannot exceed the overflow value of the CPU error count register.
- the fast channel interconnect link monitoring device maps the first judgment result and the routing table information into a first graphical interface.
- the first graphical interface is configured to display a fast channel interconnection link connection state between nodes of the system under test according to the first determination result and the routing table information.
- an achievable implementation manner is that the fast channel interconnect link monitoring device mapping the first determination result and the routing table information to the first graphical interface may include the following operations:
- the fast channel interconnect link monitoring device parses out the topology structure relationship between each node in the system under test and other nodes in the system to be tested from the routing table information.
- the fast-path interconnect link monitoring device can obtain the topology relationship between all the nodes in the system to be tested through the routing table information, such as which nodes are connected to each node, and then the extension between all nodes can be obtained. Park structure relationship.
- the fast channel interconnect link monitoring device obtains, according to the first judgment result, whether there is a link fault between each node in the system under test and other nodes in the system to be tested.
- the fast channel interconnect link monitoring device can obtain the cyclic redundancy code check from the first judgment result. If the number of error times exceeds the preset cyclic redundancy code check error threshold, if it exceeds, it is considered that there is a link fault. If it is not exceeded, it is considered that there is no link fault.
- the fast channel interconnect link monitoring device displays the link with the link fault between the nodes in the topology relationship to obtain a first graphical interface.
- the fast channel interconnect link monitoring device can display the first graphical interface by displaying a link with a link failure between the nodes in the topology relationship between each node and other nodes in the system under test.
- the fast channel interconnect link monitoring device can analyze the topology structure and CRC error information between nodes through data analysis and form standard Extensible Markup Language (XML) data, and then Draw a dynamic vector diagram through a JavaScript function to get the first graphical interface.
- the ordinary PC controller can access the first graphical interface through a browser, and can periodically refresh the page on the browser to obtain the latest QPI link connection status, or manually refresh the button to obtain the latest QPI link connection status.
- an implementation manner is that the QPI link monitoring device displays an abnormal fast-path interconnect link through the first graphical interface.
- the embodiment of the present invention may further include the following optional implementation manner:
- the QPI link monitoring device performs abnormal nodes on the abnormal QPI link. Isolation and jump back to operation 102 begins execution 102 and subsequent steps.
- the embodiment of the present invention may further include the following implementation manner: the fast channel interconnect link monitoring device triggers the first An alarm.
- the QPI link monitoring device may trigger multiple first alarm modes, for example, sending a mail to a user, sending a mobile phone short message to the user, and displaying a special file on the QPI link monitoring device (such as popping up Warning box, play some audio file, play some video file, etc.
- a special file on the QPI link monitoring device such as popping up Warning box, play some audio file, play some video file, etc.
- the QPI link monitoring device obtains the CRC error information and the routing table information in 101, obtains the first judgment result at 102, and in 103, the QPI link monitoring device can determine the first judgment result and the route.
- the table information is mapped to the first graphical interface. On the graphical interface, it can be When the connection status of the QPI link is displayed, the QPI link monitoring device can obtain the connection status of the QPI link through the first graphical interface at any time, and the user can access the QPI link monitoring device to view the QPI link in real time by using a common PC control device. Connection Status.
- the fast channel interconnect link monitoring device determines whether the number of fast channel interconnect link retransmissions exceeds a preset fast channel interconnect link retransmission threshold, obtains a second determination result, and then triggers 105 to execute.
- the QPI link monitoring device can determine whether the QPI link retransmission times exceed the preset QPI link retransmission threshold, and obtain a second determination result.
- the second judgment result indicates a numerical relationship between the number of QPI link retransmissions acquired by the QPI link monitoring device and the preset QPI link retransmission threshold.
- the second judgment result is that the number of QPI link retransmissions exceeds the preset QPI link retransmission threshold, it indicates that the QPI link is abnormal.
- the second judgment result is that the number of QPI link retransmissions does not exceed the preset QPI link retransmission threshold, it indicates that the QPI link is not abnormal.
- the setting of the QPI link retransmission threshold may be preset according to a specific application scenario.
- the QPI link retransmission threshold may be set according to the actual needs of the user, and some may be The QPI link retransmission threshold is set to a larger value, but cannot exceed the overflow value of the QPI link retransmission count register.
- the fast channel interconnect link monitoring device maps the second judgment result and the routing table information into a second graphical interface.
- the second graphical interface is configured to display a fast channel interconnection link connection state between nodes of the system under test according to the second determination result and the routing table information.
- the QPI link monitoring device may map the second determination result and the routing table information to the second graphical interface.
- the connection status of the QPI link can be displayed in real time, and the QPI link monitoring device can obtain the connection status of the QPI link through the graphical interface at any time, and the user can access the QPI link by using a common PC control machine.
- the monitoring device checks the connection status of the QPI link in real time.
- an optional implementation manner is that the fast channel interconnect link monitoring device mapping the second determination result and the routing table information to the second graphical interface may include the following operations:
- the fast channel interconnect link monitoring device parses out the topology structure relationship between each node in the system to be tested and other nodes in the system to be tested from the routing table information.
- the fast-path interconnect link monitoring device can obtain the topology relationship between all the nodes in the system to be tested through the routing table information, such as which nodes are connected to each node, and then the extension between all nodes can be obtained. Park structure relationship. B2.
- the fast channel interconnect link monitoring device acquires, according to the second judgment result, whether there is a link fault between each node in the system under test and other nodes in the system to be tested.
- the fast channel interconnect link monitoring device can obtain, from the second judgment result, whether the number of times of the fast channel interconnect link retransmission exceeds the preset fast channel interconnect link retransmission threshold, and if it exceeds, the link fault is considered to be present. If it is not exceeded, it is considered that there is no link failure.
- the fast channel interconnect link monitoring device displays the link with the link fault between the nodes on the topology structure relationship, and obtains a second graphical interface.
- the fast channel interconnect link monitoring device can display the second graphical interface by displaying a link with a link failure between the nodes in the topology relationship between each node and other nodes in the system under test.
- the second graphical interface Specifically used to display abnormal fast-path interconnect links. If the second judgment result is that the number of fast channel interconnection retransmissions does not exceed the preset fast channel interconnection link retransmission threshold, the second graphical interface is specifically configured to display a normal fast lane interconnection link.
- the embodiment of the present invention may further include the following optional implementation manner: the QPI link monitoring device abnormal node on the abnormal QPI link Isolation is performed and jump back to operation 102 to begin execution 102 and subsequent steps.
- the embodiment of the present invention may further include the following implementation manner: Second alarm.
- the second alarm mode of the QPI link monitoring device may also be multiple, for example, sending a mail to a user, sending a mobile phone short message to the user, and displaying a special file on the QPI link monitoring device (such as popping up a warning box, playing an audio file, playing a certain video file, etc.
- a special file on the QPI link monitoring device Such as popping up a warning box, playing an audio file, playing a certain video file, etc.
- the fast channel interconnect link monitoring device may trigger the second alarm before the fast channel interconnect link monitoring device maps the second determination result and the routing table information to the second graphical interface.
- the manner of the first alarm may be the same as or different from the manner of the second alarm, which is not limited herein.
- the fast channel interconnect link monitoring device checks the cyclic redundancy code after the fast channel interconnect link monitoring device obtains the cyclic redundancy code check error information and the routing table information of the system to be tested.
- the first judgment result and the routing table information are mapped to the first graphical interface, and the number of error corrections in the cyclic redundancy code does not exceed the preset.
- the second judgment result is obtained by judging whether the fast channel interconnection link retransmission times exceed the preset fast channel interconnection link retransmission threshold, and the second judgment result is obtained.
- routing table information is mapped to a second graphical interface.
- the method for obtaining the cyclic redundancy code check error information and the routing table information of the system to be tested in the embodiment of the present invention can be obtained by using a software device (that is, the fast channel interconnect link monitoring device in the embodiment of the present invention). There is no need to add a separate test device (for example, no need to add a load detection board) to implement, and the fast channel interconnect link monitoring device can be mapped to a graphical interface by using the first judgment result or the second judgment result in combination with the routing table information.
- a software device that is, the fast channel interconnect link monitoring device in the embodiment of the present invention.
- test software sigtest 0 embodiment of the invention does not require a separate test equipment (i.e., without increasing the oscilloscope) conversion to output a test software sigtest 0 embodiment of the invention can be displayed in real time QPI link connection state through a graphical interface for the wave file, thereby reducing test Cost, and the operation process is simple and easy to implement.
- FIG. 2 it is a system networking diagram of a fast channel interconnect link monitoring system according to an embodiment of the present invention.
- the fast-channel interconnect link monitoring device is installed in the OA server as an example.
- the user can use the ordinary PC controller to access the fast-channel interconnect link monitoring device through the network to implement the fast-channel interconnect link. real time monitoring.
- the monitoring system may include: an OA server running a QPI link monitoring device, a normal PC controller used by the user, a system SUT to be tested, and a switch.
- the system to be tested includes: node 1, node 2, node 3, and master node.
- the ordinary PC controller accesses the OA server through a switch in a network connection manner.
- the BMCs of all nodes (all nodes refer to node 1, node 2, node 3, and master node) are connected to the OA server through switches.
- the master node can be connected to a display through a video graphics array ⁇ ij ( VGA, Video Graphics Array ).
- the ordinary PC control machine is connected to the main node of the system to be tested through a serial port.
- the fast channel interconnect link monitoring method includes:
- the master node of the system to be tested establishes routing table information.
- the BMC of the system to be tested obtains routing table information and CRC error information.
- the OA server receives the CRC error information and the routing table information obtained by the BMC of the system to be tested through the IMPI.
- the QPI link monitoring device obtains CRC error information and routing table information of the system to be tested through the OA server connected to itself.
- the QPI link monitoring device determines whether the CRC error number exceeds a preset CRC error threshold, and obtains a first judgment result. If the first judgment result is that the CRC error number exceeds the preset CRC error threshold, the triggering operation 306 is performed. If the first judgment result is that the CRC error number does not exceed the preset CRC error threshold, the triggering operation 309 is performed.
- the QPI link monitoring device triggers the first alarm, and then triggers 307 to execute.
- the QPI link monitoring device maps the first determination result and the routing table information to a first graphical interface, and then triggers 308 to execute.
- the QPI link monitoring device displays the abnormal fast channel interconnect link through the first graphical interface, and then triggers 314 to execute.
- the QPI link monitoring device determines whether the number of retransmissions of the QPI link exceeds a preset QPI link retransmission threshold, and obtains a second judgment result. If the second judgment result is that the QPI link retransmission times exceed the preset QPI chain. The path retransmits the threshold and trigger 310 is executed. If the second judgment result is that the number of QPI link retransmissions does not exceed the preset QPI link retransmission threshold, the trigger 311 is directly executed.
- the QPI link monitoring device triggers a second alarm, and then triggers 311 to execute.
- the QPI link monitoring device maps the second determination result and the routing table information to a second graphical interface. According to the second determination result, if the second determination result is that the fast channel interconnection link retransmission times exceed the preset fast The channel interconnect link retransmits the threshold, and the second graphical interface is specifically configured to display the abnormal fast channel interconnect link, and the trigger 312 is executed. According to the second determination result, if the second determination result is that the number of times of the fast channel interconnection link retransmission does not exceed the preset fast channel interconnection link retransmission threshold, the second graphical interface is specifically configured to display the normal fast channel mutual With the link, trigger 313 is executed.
- the QPI link monitoring device displays a normal fast channel interconnect link through the second graphical interface, and then ends the entire monitoring process. 313.
- the QPI link monitoring device displays an abnormal fast-path interconnect link through the second graphical interface, and triggers 314 to execute.
- the QPI link monitoring device isolates the abnormal node on the abnormal QPI link, and then may complete the entire monitoring process, or may re-trigger the operations after 305 and 305 to continue.
- the system under test includes four nodes Al, A2, A3, and A4, of which A1 is the master node.
- the BIOS of the master node A1 sends the routing table information to the BMC of the system under test through the KCS.
- the BMC of the system under test reads the CRC error information of the node of the system under test through the SMBUS.
- the BMC of the system under test sends the CRC error information and routing table information of the system to be tested to the OA server through IMPI.
- the QPI link monitoring device obtains CRC error information and routing table information from the OA server through a web connection.
- the QPI link monitoring device determines whether the CRC error number exceeds a preset CRC error threshold to obtain a first judgment result, and the QPI link monitoring device maps the first judgment result and the routing table information into a graphical interface.
- the QPI link monitoring device determines whether the number of QPI link retransmissions exceeds a preset QPI link retransmission threshold, and obtains a second judgment result, and the QPI link monitoring device maps the second judgment result and the routing table information into a graphical interface.
- the QPI link connection status of the system to be tested can be viewed in real time. Taking the failure of the link between the two nodes A1 and A2 as an example, the user can intuitively display an abnormality between the two nodes A1 and A2 of the system to be tested from the graphical interface.
- the above embodiment introduces the fast channel interconnect link monitoring method.
- a fast channel interconnect link monitoring device is introduced.
- the fast channel interconnect link monitoring device may be integrated into a single board manager management software, and the user may use the ordinary PC control machine to access the board administrator management software through the network to realize the fast channel mutual Real-time monitoring of links.
- the fast-channel interconnect link monitoring device can also be a stand-alone device installed on the board administrator server in the manner of software control hardware. The user can use the ordinary PC controller to achieve fast connection through the fast channel interconnect link monitoring device. Real-time monitoring of channel interconnect links.
- the fast channel interconnect link monitoring device can also be implemented as a stand-alone device installed on a normal PC control machine in the manner of software control hardware. The specific implementation manner is not limited herein.
- the QPI link monitoring device 500 includes: acquiring a single a 501, a first determining unit 502, a first mapping unit 503, a second determining unit 504, and a second mapping unit 505, where
- the obtaining unit 501 is configured to obtain CRC error information and routing table information of the system to be tested, where the CRC error information includes a CRC error number and a QPI link retransmission number.
- the first determining unit 502 is configured to determine whether the CRC error number exceeds a preset CRC error threshold, and obtain a first determination result. If the first judgment result is that the cyclic redundancy code check error number exceeds the preset cyclic redundancy code check error threshold, the first alarm unit 503 is triggered to execute, if the first judgment result is a cyclic redundancy code check error. The code number does not exceed the preset cyclic redundancy code check error threshold, and the second decision element 505 is triggered to execute.
- the first mapping unit 503 is configured to: when the first determination result is that the cyclic redundancy code check error number exceeds a preset cyclic redundancy code check error threshold, mapping the first judgment result and the routing table information to the first A graphical interface, wherein the first graphical interface is configured to display a fast channel interconnect link connection state between nodes of the system under test according to the first determination result and the routing table information.
- the second determining unit 504 is configured to determine, when the first determination result that the number of times of the cyclic redundancy code check error does not exceed the preset cyclic redundancy code check error threshold, determine whether the number of QPI link retransmissions exceeds a preset. The QPI link retransmits the threshold to obtain a second judgment result.
- the second mapping unit 505 is configured to map the second determination result and the routing table information into a graphical interface.
- the second graphical interface is configured to display a QPI link connection state between the nodes of the system to be tested according to the second determination result and the routing table information.
- the obtaining unit 501 is specifically configured to obtain the CRC error information and the routing table information of the system to be tested by using the board administrator server connected to itself.
- the CRC error information and the routing table information are obtained by the board management controller BMC of the system to be tested, and then sent by the board management controller to the board administrator server through the intelligent platform management interface IPMI.
- the first mapping unit 504 may specifically include:
- the parsing module is configured to parse, from the routing table information, a topology relationship between each node in the system to be tested and other nodes in the system to be tested.
- the first ear is used to acquire each node in the system to be tested according to the first judgment result. Whether there is a link fault between other nodes in the system under test.
- the first display module is configured to display a link with a link fault between the nodes on the topology structure relationship to obtain a first graphical interface.
- the second mapping unit 507 may specifically include:
- the parsing module is configured to parse, from the routing table information, a topology relationship between each node in the system to be tested and other nodes in the system to be tested.
- the second ear is configured to obtain, according to the second determination result, whether there is a link failure between each node in the system under test and other nodes in the system to be tested.
- the second display module is configured to display a link with a link fault between the nodes on the topology structure relationship to obtain a second graphical interface.
- the following units may also be included:
- the first alarm unit 506 is configured to trigger the first alarm when the first judgment result is that the cyclic redundancy code check error number exceeds a preset cyclic redundancy code check error threshold.
- the second alarm unit 507 is configured to trigger a second alarm when the second determination result is that the fast channel interconnection link retransmission number exceeds the preset fast channel interconnection link retransmission threshold.
- the following units may also be included:
- the first isolation unit 508 is configured to isolate an abnormal node on the abnormal fast-path interconnect link when the first graphical interface displays an abnormal fast-path interconnect link, and jump back to the first determining unit 502 to perform .
- the second isolation unit 509 is configured to isolate the abnormal node on the abnormal fast-path interconnect link when the second graphical interface displays the abnormal fast-path interconnect link, and jump back to the first determining unit 502 to perform .
- the first determining unit 502 determines whether the CRC error number exceeds a preset CRC error threshold.
- the first mapping unit 503 sets the first judgment result and the routing table information. Mapping to the first graphical interface, in the case that the cyclic redundancy code check error number does not exceed the preset cyclic redundancy code check error threshold, the second determining unit 504 determines the fast channel interconnect link retransmission Whether the number of times exceeds the preset fast-path interconnect link retransmission threshold to obtain a second determination result, the second mapping unit 505 maps the second determination result and the routing table information to a second graphical interface, so that the user can visually view the entire QPI link connection status of the system under test.
- the embodiment of the invention does not need to add a separate test device and separate test software, so that the test cost can be reduced, and the operation process is simple and easy to implement.
- a fast channel interconnect link monitoring system includes: a system to be tested, a fast channel interconnect link monitoring device capable of displaying a fast channel interconnect link connection state between nodes of the system to be tested . among them,
- a fast channel interconnect link monitoring device configured to obtain cyclic redundancy code check error information and routing table information of the system to be tested, and the cyclic redundancy code check error information includes a cyclic redundancy code check error code number and Fast channel interconnection link retransmission times; determining whether the cyclic redundancy code check error number exceeds a preset cyclic redundancy code check error threshold, and obtaining a first judgment result; if the first judgment result is cyclic redundancy The code check error number exceeds the preset cyclic redundancy code check error threshold, and the first judgment result and the routing table information are mapped into a first graphical interface, and the first graphical interface is used according to the first judgment result and The routing table information indicates the fast channel interconnection link connection state between the nodes of the system to be tested; if the first judgment result is that the cyclic redundancy code check error number does not exceed the preset cyclic redundancy code check error threshold And determining whether the number of retransmissions of the
- the fast-channel interconnect link monitoring system further includes: an OA server and a switch, the fast-channel interconnect link monitoring device is loaded on the OA server, and the switch is used to implement the OA server and Data interaction of the system under test.
- the system to be tested includes a master node and a board management controller.
- the master node is configured to establish routing table information of the system to be tested;
- the board management controller is configured to obtain routing table information from the master node, and read the cyclic redundancy code verification error of the node of the system to be tested through the system management bus SMBUS.
- the code information is sent to the OA server through the intelligent platform management interface IPMI to send cyclic redundancy code check error information and routing table information.
- the OA server is configured to receive the cyclic redundancy code check error information and the routing table information sent by the board management controller, and send the cyclic redundancy code check error information and the routing table information to the fast channel interconnect link monitoring. device.
- the fast-track interconnect link monitoring system further includes: an OA server, a general personal computer control unit and a switch, and a fast-channel interconnect link monitoring device is loaded in an ordinary personal computer control.
- the switch is used to implement data interaction between the OA server and the system under test, and the interaction between the OA server and the ordinary personal computer control machine.
- the system to be tested includes a master node and a board management controller.
- the master node is configured to establish routing table information of the system to be tested;
- the board management controller is configured to obtain routing table information from the master node, and read the cyclic redundancy code verification error of the node of the system to be tested through the system management bus SMBUS.
- the code information is sent to the OA server through the intelligent platform management interface IPMI to send cyclic redundancy code check error information and routing table information.
- the OA server is configured to receive the cyclic redundancy code check error information and the routing table information sent by the board management controller, and send the cyclic redundancy code check error information and the routing table information to the fast channel interconnect link monitoring. device.
- a common personal computer control machine for displaying a first graphical interface or a second graphical interface obtained by the fast track interconnect link monitoring device.
- the fast channel interconnect link monitoring device After the fast channel interconnect link monitoring device obtains the cyclic redundancy code check error information and the routing table information of the system to be tested, the fast channel interconnect link monitoring device checks the cyclic redundancy code. When the number of errors exceeds the preset cyclic redundancy code check error threshold, the first judgment result and the routing table information are mapped to the first graphical interface, and the number of error corrections in the cyclic redundancy code does not exceed the pre-pre When the cyclic redundancy code check error threshold is set, the second judgment result is obtained by judging whether the fast channel interconnection link retransmission times exceed the preset fast channel interconnection link retransmission threshold, and the second judgment is obtained.
- the result and routing table information are mapped to a second graphical interface.
- the method for obtaining the cyclic redundancy code check error information and the routing table information of the system to be tested in the embodiment of the present invention can be obtained by using a software device (that is, the fast channel interconnect link monitoring device in the embodiment of the present invention).
- a software device that is, the fast channel interconnect link monitoring device in the embodiment of the present invention.
- the fast channel interconnect link monitoring device can be mapped to a graphical interface by using the first judgment result or the second judgment result in combination with the routing table information.
- the embodiment of the invention can display the QPI link connection status in real time through the graphical interface, thereby reducing the test cost, and the operation process is simple and easy to implement.
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Abstract
一种快速通道互连链路监控方法和设备及***。方法包括:获取待测***SUT的循环冗余码校验误码信息和路由表信息;判断所述循环冗余码校验误码次数是否超过预置的循环冗余码校验误码阈值,得到第一判断结果;若所述第一判断结果为所述循环冗余码校验误码次数超过所述预置的循环冗余码校5验误码阈值,将所述第一判断结果和所述路由表信息映射为第一图形化界面;若所述第一判断结果为所述循环冗余码校验误码次数没有超过所述预置的循环冗余码校验误码阈值,判断所述快速通道互连链路重传次数是否超过预置的快速通道互连链路重传阈值,得到第二判断结果;将所述第二判断结果和所述路由表信息映射为第二图形化界面。
Description
一种快速通道互连链路监控方法和设备及***
技术械
本发明实施例涉及计算机技术领域,尤其涉及一种快速通道互连链路监控 方法和设备及***。 背景技术
在容错计算机的小型机项目中, 小型机核心技术就是中央处理器(CPU, Central Processing Unit )之间的互连架构, 而互连架构的稳定性重点取决于快 速通道互连(QPI, Quick Path Interconnect )信号的完整性。
为了测试 QPI信号的完整性, 现有技术中采用定量测试 QPI信号完整性 ( SI, Signal Integrality )的方法, 通过英特尔( Intel ) QPI负载检测板 ( QLB, QPI Load Board ) 配合示波器以及英特尔快速通道监测工具套件 ( QTK, QuickPath Tool Kit )和 sigtest等软件来测试 QPI信号的信号完整性, 首先由 QLB检测出 QPI信号传输到示波器, 然后示波器输出波形文件到计算机中运 行的 sigtest软件, 最后由 sigtest软件将测试结果输出。
但是, 现有的测试方案需要单独的测试设备 (如负载检测板和示波器 )和 单独的测试软件(如 QTK和 sigtest ) 才能进行测试, 所需的测试成本较高, 且操作起来也较复杂。 发明内容
本发明实施例提供了一种快速通道互连链路监控方法和设备及***,能够 以较低的测试成本实现对 QPI链路的监控, 操作简单。
本发明实施例提供的一种快速通道互连链路监控方法, 包括:
快速通道互连链路监控设备获取待测*** SUT的循环冗余码校验误码信 息和路由表信息,所述循环冗余码校验误码信息包括循环冗余码校验误码次数 和快速通道互连链路重传次数;
所述快速通道互连链路监控设备判断所述循环冗余码校验误码次数是否 超过预置的循环冗余码校验误码阈值, 得到第一判断结果;
若所述第一判断结果为所述循环冗余码校验误码次数超过所述预置的循 环冗余码校验误码阈值,所述快速通道互连链路监控设备将所述第一判断结果 和所述路由表信息映射为第一图形化界面,所述第一图形化界面用于根据所述 第一判断结果和所述路由表信息显示所述待测***的节点之间的快速通道互 连链路连接状态;
若所述第一判断结果为所述循环冗余码校验误码次数没有超过所述预置 的循环冗余码校验误码阈值,所述快速通道互连链路监控设备判断所述快速通 道互连链路重传次数是否超过预置的快速通道互连链路重传阈值,得到第二判 断结果;
所述快速通道互连链路监控设备将所述第二判断结果和所述路由表信息 映射为第二图形化界面,所述第二图形化界面用于根据所述第二判断结果和所 述路由表信息显示所述待测***的节点之间的快速通道互连链路连接状态。
本发明实施例提供的一种快速通道互连链路监控设备, 包括:
获取单元, 用于获取待测*** SUT的循环冗余码校验误码信息和路由表 信息,所述循环冗余码校验误码信息包括循环冗余码校验误码次数和快速通道 互连链路重传次数;
第一判断单元,用于判断所述循环冗余码校验误码次数是否超过预置的循 环冗余码校验误码阈值, 得到第一判断结果;
第一映射单元,用于当所述第一判断结果为所述循环冗余码校验误码次数 超过所述预置的循环冗余码校验误码阈值时 ,将所述第一判断结果和所述路由 表信息映射为第一图形化界面,所述第一图形化界面用于根据所述第一判断结 果和所述路由表信息显示所述待测***的节点之间的快速通道互连链路连接 状态;
第二判断单元,用于当所述第一判断结果为所述循环冗余码校验误码次数 没有超过预置的循环冗余码校验误码阈值时,判断所述快速通道互连链路重传 次数是否超过预置的快速通道互连链路重传阈值, 得到第二判断结果;
第二映射单元,用于将所述第二判断结果和所述路由表信息映射为第二图 形化界面,所述第二图形化界面用于根据所述第二判断结果和所述路由表信息 显示所述待测***的节点之间的快速通道互连链路连接状态。
本发明实施例提供的一种快速通道互连链路监控***, 包括: 待测*** SUT、能够显示所述待测***的节点之间的快速通道互连链路连接状态的快速 通道互连链路监控设备, 其中,
所述快速通道互连链路监控设备,用于获取所述待测***的循环冗余码校 验误码信息和路由表信息,所述循环冗余码校验误码信息包括循环冗余码校验 误码次数和快速通道互连链路重传次数;判断所述循环冗余码校验误码次数是 否超过预置的循环冗余码校验误码阈值,得到第一判断结果; 若所述第一判断 结果为所述循环冗余码校验误码次数超过所述预置的循环冗余码校验误码阈 值,将所述第一判断结果和所述路由表信息映射为第一图形化界面, 所述第一 图形化界面用于根据所述第一判断结果和所述路由表信息显示所述待测*** 的节点之间的快速通道互连链路连接状态;若所述第一判断结果为所述循环冗 余码校验误码次数没有超过所述预置的循环冗余码校验误码阈值,判断所述快 速通道互连链路重传次数是否超过预置的快速通道互连链路重传阈值,得到第 二判断结果; 将所述第二判断结果和所述路由表信息映射为第二图形化界面, 所述第二图形化界面用于根据所述第二判断结果和所述路由表信息显示所述 待测***的节点之间的快速通道互连链路连接状态。
从以上技术方案可以看出, 本发明实施例具有以下优点:
在本发明实施例中,快速通道互连链路监控设备获取到待测***的循环冗 余码校验误码信息和路由表信息之后,快速通道互连链路监控设备在循环冗余 码校验误码次数超过预置的循环冗余码校验误码阈值的情况下将第一判断结 果和路由表信息映射为第一图形化界面 ,在循环冗余码校验误码次数没有超过 预置的循环冗余码校验误码阈值的情况下,通过判断快速通道互连链路重传次 数是否超过预置的快速通道互连链路重传阈值得到第二判断结果,将第二判断 结果和路由表信息映射为第二图形化界面。通过第一图形化界面或者第二图形 化界面用户能够直观的查看到整个待测***的 QPI链路连接状态。本发明实施 例中获取待测***的循环冗余码校验误码信息和路由表信息可以由一个软件 装置(即本发明实施例中的快速通道互连链路监控设备)即可获取得到, 不需 要增加单独的测试设备 (例如不需要增加负载检测板 )去实现, 另外该快速通 道互连链路监控设备由第一判断结果或第二判断结果结合路由表信息就能映
射得到图形化界面, 也不需要单独的测试设备(即不需要增加示波器)转化为 波形文件输出到一个测试软件 sigtest。本发明实施例可以通过图形化界面就能 够实时的显示 QPI链路连接状态,从而能够降低测试成本,且操作过程简单容 易实现。 附图说明
图 1 为本发明实施例提供的快速通道互连链路监控方法一个实施例的示 意图;
图 2为本发明实施例提供的快速通道互连链路监控方法的***组网图; 图 3 为本发明实施例提供的快速通道互连链路监控方法另一个实施例的 示意图;
图 4为本发明实施例提供的快速通道互连链路实现实时监控的示意图; 图 5 为本发明实施例提供的快速通道互连链路监控设备一个实施例示意 图。 具体实施方式
本发明实施例提供了一种快速通道互连链路监控方法和设备及***,能够 以较低的测试成本实现对 QPI链路的监控, 操作简单。
为使得本发明的发明目的、 特征、优点能够更加的明显和易懂, 下面将结 合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、 完整地描 述,显然,下面所描述的实施例仅仅是本发明一部分实施例,而非全部实施例。 基于本发明中的实施例, 本领域的技术人员所获得的所有其他实施例,都属于 本发明保护的范围。
本发明实施例中,实现该快速通道互连链路监控方法的动作主体是快速通 道互连链路监控设备,在实际应用中, 快速通道互连链路监控设备具体可以是 集成在一种单板管理者( OA, OnBoard Administrator )管理软件上实现, 用户 可以使用普通个人电脑( PC , Personal Computer )控制机通过网络访问单板管 理者管理软件实现对快速通道互连链路的实时监控。快速通道互连链路监控设 备也可以是一种独立的设备按照软件控制硬件的方式安装在单板管理者服务
器上, 用户可以使用普通 PC控制机通过快速通道互连链路监控设备实现对快 速通道互连链路的实时监控。快速通道互连链路监控设备也可以是一种独立的 设备按照软件控制硬件的方式安装在普通 PC控制机上实现。 具体实现方式此 处不作限定。
需要说明的是,本发明实施例提供的快速通道互连链路监控设备在一个快 速通道互连链路监控***内执行。该监控***的系具体可以包括: 快速通道互 连链路监控设备、 普通 PC控制机、 单板管理者服务器、 待测***、 交换机。 其中, 普通 PC控制机通过交换机以网络连接的方式访问 OA服务器。
请参阅图 1 , 本发明实施例提供的快速通道互连链路监控方法一个实施例 包括:
101、 快速通道互连链路监控设备获取待测***的循环冗余码校验误码信 息和路由表信息。其中,循环冗余码校验误码信息包括循环冗余码校验误码次 数和快速通道互连链路重传次数。
在本发明实施例中, 为了能够实现对待测***( SUT, System Under Test ) 的监控, 快速通道互连链路监控设备 (以下将快速通道互连链路监控设备简称 为 QPI链路监控设备 )获取 SUT的循环冗余码校验( CRC, Cyclic Redundancy
Check )误码信息和路由表信息。
在本发明实施例中, 待测***是 QPI链路监控设备需要监控的节点的集 合。 其中, 待测***包括一个主节点和多个节点, 在监控***上电时, 待测系 统中的主节点和每一个节点的中央处理器( CPU, Central Processing Unit )都 会主动的和本地链路中的其它节点建立连接,在握手成功后, 它们之间会交换 链路层参数, 主节点和每一个节点都会得到其它节点的插槽(socket )信息和 端口信息以及传输速率等。 此时, 主节点和每一个节点的 CPU进入等待状态。 待测***中的主节点的 CPU将建立一路由表然后存储该路由表信息, 路由表 用于记录待测***中的所有节点(其中所有节点包括主节点和每一个节点)的 路由信息。 在实际应用中, 主节点的 CPU具体可以通过广度优先搜索算法发 现所有在网的插槽来实现建立路由表。
需要说明的是, 本发明实施例中的 CRC误码信息包括 CRC误码次数和
QPI链路重传次数。 其中, 在 QPI链路传输数据时, 若链路层发现 CRC误码
之后, 待测***中的 CPU误码次数寄存器会记录下 CRC误码次数。 当链路层 发现 CRC误码之后 QPI链路会尝试自愈,对数据进行重传,待测***中的 QPI 链路重传次数寄存器会记录下 QPI链路重传次数。
在本发明实施例中, QPI链路监控设备能够获取 SUT的 CRC误码信息和 路由表信息存在多种实现方式。 其中一种实现方式为: QPI链路监控设备通过 与自身连接的 OA服务器获取待测***的 CRC误码信息和路由表信息。其中, OA服务器能够获取到待测***的 CRC误码信息和路由表信息具体可以通过 如下方式实现: OA服务器通过智能平台管理接口 (IPMI, Intelligent Platform Management Interface ) 从待测***的单板管理控制器 (BMC , Boardbase Management Controller )获取到 CRC误码信息和路由表信息。待测***的 BMC 和 OA服务器之间信息传递通过 IPMI来实现,待测***的 BMC通过 IMPI向 OA服务器传递 CRC误码信息和路由表信息。
需要说明的是, 在本发明实施例中, 待测***的 BMC获取路由表信息具 体可以采用如下方式:首先由待测***的主节点在待测***的所有节点之间交 换链路层参数之后建立待测***的路由表信息。 然后, 待测***的 BMC从该 主节点处获取到路由表信息。 其中, 待测***的 BMC从该主节点处获取到路 由表信息具体可以采用多种实现方式,一种可实现的方式是: 主节点的基本输 入输出***( BIOS , Basic Input Output System )通过键盘控制器规格接口( KCS , Keyboard Controller Style Interface ) 向待测***的 BMC发送路由表信息, 则 待测***的 BMC可以通过该 KCS接收到主节点的 BIOS发送的路由表信息。 另一种可实现的方式是:待测***的 BMC通过***管理总线( SMBUS, System Management Bus )读取主节点的 CPU相关寄存器并解析出路由表信息。 其中, CPU相关寄存器指的是主节点的 CPU所包括的 12个 QPI端口中每个 QPI端 口所包括的 3个寄存器, 3个寄存器分别是路由表配置寄存器(Router Table Configuration Register )、 路由读取寄存器( Router Read Register ), 路由写入寄 存器( Router Write Register )。
需要说明的是, 在本发明实施例中, 待测***的 BMC获取 CRC误码信 息具体可以采用如下方式: 待测***的 BMC通过***管理总线读取待测*** 的节点的 CRC误码信息。 本发明实施例中的 CRC误码信息包括 CRC误码次
数和 QPI链路重传次数。
102、 快速通道互连链路监控设备判断循环冗余码校验误码次数是否超过 预置的循环冗余码校验误码阈值,得到第一判断结果。若第一判断结果为循环 冗余码校验误码次数超过预置的循环冗余码校验误码阈值, 触发操作 103 执 行,若第一判断结果为循环冗余码校验误码次数没有超过预置的循环冗余码校 验误码阈值, 触发操作 104执行。
在本发明实施例中, 当 QPI链路监控设备获取到待测***的 CRC误码信 息和路由表信息之后, QPI链路监控设备判断 CRC误码次数是否超过预置的 CRC误码阈值, 得到第一判断结果。 其中, 第一判断结果表示的是 QPI链路 监控设备获取到的 CRC误码次数与预置的 CRC误码阈值的数值关系。当第一 判断结果为 CRC误码次数超过了 CRC误码阈值时表示 QPI链路存在异常, QPI链路监控设备触发操作 103执行, 当第一判断结果为 CRC误码次数没有 超过 CRC误码阈值时, QPI链路监控设备触发操作 104执行。 需要说明的是, CRC误码阈值的设定可以根据具体的应用场景而预先设定, 例如可以根据用 户的实际需要将 CRC误码阈值设定的小一些,当然也可以将 CRC误码阈值设 定的大一些, 但不能超过 CPU误码次数寄存器的溢出值。
103、 快速通道互连链路监控设备将第一判断结果和路由表信息映射为第 一图形化界面。其中, 第一图形化界面用于根据第一判断结果和路由表信息显 示待测***的节点之间的快速通道互连链路连接状态。
在实际应用中, 一种可实现的实现方式是, 快速通道互连链路监控设备将 第一判断结果和路由表信息映射为第一图形化界面具体可以包括如下操作:
A1、 快速通道互连链路监控设备从路由表信息中解析出待测***中的每 一个节点和待测***中其它节点之间的拓朴结构关系。
快速通道互连链路监控设备通过路由表信息,可以得出待测***中的所有 节点之间的拓朴结构关系,如每一个节点都与哪些节点相连, 进而可以得到全 部节点之间的拓朴结构关系。
A2、 快速通道互连链路监控设备根据第一判断结果获取到待测***中的 每一个节点和待测***中其它节点之间是否存在链路故障。
快速通道互连链路监控设备从第一判断结果中可以得到循环冗余码校验
误码次数是否超过预置的循环冗余码校验误码阈值, 若超过, 则认为存在链路 故障, 若没有超过, 则认为不存在链路故障。
A3、 快速通道互连链路监控设备将节点之间存在链路故障的链路显示在 该拓朴结构关系上, 得到第一图形化界面。
快速通道互连链路监控设备在每一个节点和待测***中其它节点之间的 拓朴结构关系上显示节点之间存在链路故障的链路,就可以得到第一图形化界 面。
例如,快速通道互连链路监控设备可以通过分析函数将各节点之间的拓朴 结构关系和 CRC误码信息通过数据分析并形成标准的可扩展标记语言( XML, Extensible Markup Language )数据, 然后通过 JavaScript函数绘制成动态矢量 图,得到第一图形化界面。普通 PC控制机可以浏览器访问该第一图形化界面, 在浏览器端可以实现定时刷新页面以获取最新的 QPI链路连接状态,也可以通 过按钮手动刷新来获取最新的 QPI链路连接状况。
需要说明的是, 在本发明实施例中的操作 103中,一种实现方式是, QPI 链路监控设备通过该第一图形化界面显示异常的快速通道互连链路。
当 QPI链路监控设备通过该第一图形化界面显示异常的 QPI链路时, 本 发明实施例还可以包括如下可选实现方式: QPI链路监控设备对异常的 QPI 链路上的异常节点进行隔离,并跳回操作 102开始执行 102及其后续的操作步 骤。
若第一判断结果为循环冗余码校验误码次数超过预置的循环冗余码校验 误码阈值, 本发明实施例还可以包括如下实现方式: 快速通道互连链路监控设 备触发第一报警。 在本发明实施例中, QPI链路监控设备触发第一报警方式可 以有多种, 例如, 向用户发送邮件、 向用户发送手机短信、 在 QPI链路监控设 备上显示某种特殊文件(如弹出警告框、 播放某种音频文件、 播放某种视频文 件)等。只要是用于向用户显示 QPI链路异常的报警方式都可以作为第一报警 的方式由快速通道互连链路监控设备触发。
在本发明实施例中, QPI链路监控设备在 101中获取到 CRC误码信息和 路由表信息、在 102得到第一判断结果、在 103中 QPI链路监控设备可以将第 一判断结果和路由表信息映射为第一图形化界面。在该图形化界面上, 可以实
时的显示 QPI链路的连接状态, QPI链路监控设备可以随时通过第一图形化界 面得到 QPI链路的连接状态,用户可以使用普通 PC控制机访问 QPI链路监控 设备实时查看 QPI链路的连接状态。
104、 快速通道互连链路监控设备判断快速通道互连链路重传次数是否超 过预置的快速通道互连链路重传阈值,得到第二判断结果,然后触发 105执行。
在本发明实施例中, QPI链路监控设备可以判断 QPI链路重传次数是否超 过预置的 QPI链路重传阈值,得到第二判断结果。 其中, 第二判断结果表示的 是 QPI链路监控设备获取到的 QPI链路重传次数与预置的 QPI链路重传阈值 的数值关系。 当第二判断结果为 QPI链路重传次数超过了预置的 QPI链路重 传阈值时表示 QPI链路存在异常。 当第二判断结果为 QPI链路重传次数没有 超过预置的 QPI链路重传阈值时表示 QPI链路没有异常。 需要说明的是, QPI 链路重传阈值的设定可以根据具体的应用场景而预先设定,例如可以根据用户 的实际需要将 QPI链路重传阈值设定的 d、一些, 当然也可以将 QPI链路重传 阈值设定的大一些, 但不能超过 QPI链路重传次数寄存器的溢出值。
105、 快速通道互连链路监控设备将第二判断结果和路由表信息映射为第 二图形化界面。其中, 第二图形化界面用于根据第二判断结果和路由表信息显 示待测***的节点之间的快速通道互连链路连接状态。
在本发明实施例中, QPI链路监控设备可以将第二判断结果和路由表信息 映射为第二图形化界面。在该第二图形化界面上,可以实时的显示 QPI链路的 连接状态, QPI链路监控设备可以随时通过图形化界面得到 QPI链路的连接状 态,用户可以使用普通 PC控制机访问 QPI链路监控设备实时查看 QPI链路的 连接状态。
在实际应用中, 一种可选的实现方式是, 快速通道互连链路监控设备将第 二判断结果和路由表信息映射为第二图形化界面具体可以包括如下操作:
Bl、 快速通道互连链路监控设备从路由表信息中解析出待测***中的每 一个节点和待测***中其它节点之间的拓朴结构关系。
快速通道互连链路监控设备通过路由表信息,可以得出待测***中的所有 节点之间的拓朴结构关系,如每一个节点都与哪些节点相连, 进而可以得到全 部节点之间的拓朴结构关系。
B2、 快速通道互连链路监控设备根据第二判断结果获取到待测***中的 每一个节点和待测***中其它节点之间是否存在链路故障。
快速通道互连链路监控设备从第二判断结果中可以得到快速通道互连链 路重传次数是否超过预置的快速通道互连链路重传阈值, 若超过, 则认为存在 链路故障, 若没有超过, 则认为不存在链路故障。
B3、 快速通道互连链路监控设备将节点之间存在链路故障的链路显示在 该拓朴结构关系上, 得到第二图形化界面。
快速通道互连链路监控设备在每一个节点和待测***中其它节点之间的 拓朴结构关系上显示节点之间存在链路故障的链路,就可以得到第二图形化界 面。
需要说明的是, 在本发明实施例中的操作 10中, 若第二判断结果为快速 通道互连链路重传次数超过预置的快速通道互连链路重传阈值,第二图形化界 面具体用于显示异常的快速通道互连链路。若第二判断结果为快速通道互连链 路重传次数没有超过预置的快速通道互连链路重传阈值,第二图形化界面具体 用于显示正常的快速通道互连链路。
当 QPI链路监控设备通过该第二图形化界面显示异常的 QPI链路时, 本 发明实施例还可以包括如下可选实现方式: QPI链路监控设备对该异常的 QPI 链路上的异常节点进行隔离,并跳回操作 102开始执行 102及其后续的操作步 骤。
若第二判断结果为快速通道互连链路重传次数超过预置的快速通道互连 链路重传阈值, 本发明实施例还可以包括如下实现方式: 快速通道互连链路监 控设备触发第二报警。 在本发明实施例中, QPI链路监控设备的触发第二报警 方式也可以有多种, 例如, 向用户发送邮件、 向用户发送手机短信、 在 QPI 链路监控设备上显示某种特殊文件(如弹出警告框、播放某种音频文件、 播放 某种视频文件)等。只要是用于向用户显示 QPI链路异常的报警方式都可以作 为第二报警的方式由快速通道互连链路监控设备触发。 另外需要说明的是,在 快速通道互连链路监控设备将第二判断结果和所述路由表信息映射为第二图 形化界面之前, 快速通道互连链路监控设备可以触发第二报警。 第一报警的方 式可以和第二 警的方式可以相同也可以不相同, 此处不作限定。
本发明实施例中,快速通道互连链路监控设备获取到待测***的循环冗余 码校验误码信息和路由表信息之后,快速通道互连链路监控设备在循环冗余码 校验误码次数超过预置的循环冗余码校验误码阈值的情况下将第一判断结果 和路由表信息映射为第一图形化界面,在循环冗余码校验误码次数没有超过预 置的循环冗余码校验误码阈值的情况下,通过判断快速通道互连链路重传次数 是否超过预置的快速通道互连链路重传阈值得到第二判断结果,将第二判断结 果和路由表信息映射为第二图形化界面。通过第一图形化界面或者第二图形化 界面用户能够直观的查看到整个待测***的 QPI链路连接状态。本发明实施例 中获取待测***的循环冗余码校验误码信息和路由表信息可以由一个软件装 置(即本发明实施例中的快速通道互连链路监控设备 )即可获取得到, 不需要 增加单独的测试设备 (例如不需要增加负载检测板 )去实现, 另外该快速通道 互连链路监控设备由第一判断结果或第二判断结果结合路由表信息就能映射 得到图形化界面, 也不需要单独的测试设备 (即不需要增加示波器 )转化为波 形文件输出到一个测试软件 sigtest0 本发明实施例可以通过图形化界面就能够 实时的显示 QPI链路连接状态,从而能够降低测试成本,且操作过程简单容易 实现。
以上实施例介绍了本发明实施例提供的快速通道互连链路监控方法,接下 来以一个具体的应用场景来介绍该快速通道互连链路监控方法。 如图 2所示, 为本发明实施例提供的快速通道互连链路监控***的***组网图。 在图 2中, 以快速通道互连链路监控设备安装在 OA服务器为例进行说明,用户可以使用 普通 PC控制机通过网络访问快速通道互连链路监控设备实现对快速通道互连 链路的实时监控。该监控***可以包括:运行 QPI链路监控设备的 OA服务器、 用户使用的普通 PC控制机、 待测*** SUT、 交换机。 其中, 待测***包括: 节点 1、 节点 2、 节点 3、 主节点。 普通 PC控制机通过交换机以网络连接的方 式访问 OA服务器。 所有节点 (所有节点指的是节点 1、 节点 2、 节点 3、 主 节点) 的 BMC通过交换机与 OA服务器相连接。 为了能够显示待测***中的 主节点的操作***(OS, Operating System ), 可以将该主节点通过视频图形阵 歹 ij ( VGA, Video Graphics Array )与一显示器相连。 普通 PC控制机通过一串 口与待测***的主节点相连。
如图 3所示,在一个具体的应用场景下,快速通道互连链路监控方法包括:
301、 待测***的主节点建立路由表信息。
302、 待测***的 BMC获取路由表信息和 CRC误码信息。
303、 OA服务器通过 IMPI接收待测***的 BMC获取的 CRC误码信息和 路由表信息。
304、 QPI链路监控设备通过与自身连接的 OA服务器获取待测***的 CRC 误码信息和路由表信息。
305、 QPI链路监控设备判断 CRC误码次数是否超过预置的 CRC误码阈 值,得到第一判断结果。若第一判断结果为 CRC误码次数超过预置的 CRC误 码阈值, 触发操作 306执行, 若第一判断结果为 CRC误码次数没有超过预置 的 CRC误码阈值, 触发操作 309执行。
306、 QPI链路监控设备触发第一报警, 然后触发 307执行。
307、 QPI链路监控设备将第一判断结果和路由表信息映射为第一图形化 界面, 然后触发 308执行。
308、 QPI链路监控设备通过该第一图形化界面显示异常的快速通道互连 链路, 然后触发 314执行。
309、 QPI链路监控设备判断 QPI链路重传次数是否超过预置的 QPI链路 重传阈值,得到第二判断结果,若第二判断结果为 QPI链路重传次数超过预置 的 QPI链路重传阈值, 触发 310执行。 若第二判断结果为 QPI链路重传次数 没有超过预置的 QPI链路重传阈值, 直接触发 311执行。
310、 QPI链路监控设备触发第二报警, 然后触发 311执行。
311、 QPI链路监控设备将第二判断结果和路由表信息映射为第二图形化 界面,根据第二判断结果, 若第二判断结果为快速通道互连链路重传次数超过 预置的快速通道互连链路重传阈值,第二图形化界面具体用于显示异常的快速 通道互连链路, 触发 312执行。 根据第二判断结果, 若第二判断结果为快速通 道互连链路重传次数没有超过预置的快速通道互连链路重传阈值,第二图形化 界面具体用于显示正常的快速通道互连链路, 触发 313执行。
312、 QPI链路监控设备通过该第二图形化界面显示正常的快速通道互连 链路, 然后结束整个监控过程。
313、 QPI链路监控设备通过该第二图形化界面显示异常的快速通道互连 链路, 触发 314执行。
314、 QPI链路监控设备对异常 QPI链路上的异常节点进行隔离, 然后可 以结束整个监控过程, 也可以重新触发 305以及 305之后的操作继续执行。
为了更加清楚描述本发明实施例提供的快速通道互连链路监控方法,请参 阅图 4所示的 QPI互连链路实时监控的示意图。在图 4中,待测***包括四个 节点 Al、 A2、 A3、 A4, 其中, A1为主节点。 主节点 A1的 BIOS会通过 KCS 将路由表信息发送给待测***的 BMC,待测***的 BMC会通过 SMBUS读取 待测***的节点的 CRC误码信息。 待测***的 BMC将待测***的 CRC误码 信息和路由表信息通过 IMPI发送给 OA服务器。 QPI链路监控设备通过 web 连接从 OA服务器上获取到 CRC误码信息和路由表信息。 QPI链路监控设备 判断 CRC误码次数是否超过预置的 CRC误码阈值得到第一判断结果, QPI链 路监控设备将第一判断结果和路由表信息映射为图形化界面。 QPI链路监控设 备判断 QPI链路重传次数是否超过预置的 QPI链路重传阈值, 得到第二判断 结果, QPI链路监控设备将第二判断结果和路由表信息映射为图形化界面。 当用户使用普通 PC控制机访问 QPI链路监控设备可以实时查看到待测***的 QPI链路连接状态。 以两个节点 A1和 A2之间的链路出现故障为例, 用户可 以直观的从图形化界面显示出该待测***的两个节点 A1和 A2之间出现出现 异常。
以上实施例介绍了快速通道互连链路监控方法,接下来介绍一种快速通道 互连链路监控设备。在实际应用中, 快速通道互连链路监控设备具体可以是集 成在一种单板管理者管理软件上实现, 用户可以使用普通 PC控制机通过网络 访问单板管理者管理软件实现对快速通道互连链路的实时监控。快速通道互连 链路监控设备也可以是一种独立的设备按照软件控制硬件的方式安装在单板 管理者服务器上, 用户可以使用普通 PC控制机通过快速通道互连链路监控设 备实现对快速通道互连链路的实时监控。快速通道互连链路监控设备也可以是 一种独立的设备按照软件控制硬件的方式安装在普通 PC控制机上实现。 具体 实现方式此处不作限定。
如图 5所示, 本发明实施例提供的 QPI链路监控设备 500, 包括: 获取单
元 501、 第一判断单元 502、 第一映射单元 503、 第二判断单元 504、 第二映射 单元 505, 其中,
获取单元 501 , 用于获取待测***的 CRC误码信息和路由表信息, 其中, CRC误码信息包括 CRC误码次数和 QPI链路重传次数。
第一判断单元 502, 用于判断 CRC误码次数是否超过预置的 CRC误码阈 值,得到第一判断结果。若第一判断结果为循环冗余码校验误码次数超过预置 的循环冗余码校验误码阈值,触发第一报警单元 503执行, 若第一判断结果为 循环冗余码校验误码次数没有超过预置的循环冗余码校验误码阈值,触发第二 判断元 505执行。
第一映射单元 503 , 用于当第一判断结果为循环冗余码校验误码次数超过 预置的循环冗余码校验误码阈值时,将第一判断结果和路由表信息映射为第一 图形化界面, 其中, 第一图形化界面用于根据第一判断结果和路由表信息显示 待测***的节点之间的快速通道互连链路连接状态。
第二判断单元 504, 用于当第一判断结果为循环冗余码校验误码次数没有 超过预置的循环冗余码校验误码阈值时,判断 QPI链路重传次数是否超过预置 的 QPI链路重传阈值, 得到第二判断结果。
第二映射单元 505 , 用于将第二判断结果和路由表信息映射为图形化界 面。其中, 第二图形化界面用于根据第二判断结果和路由表信息显示该待测系 统的节点之间的 QPI链路连接状态。
需要说明的是, 对于获取单元 501而言, 一种具体的实现方式是, 获取单 元 501具体用于通过与自身连接的单板管理者服务器获取待测***的 CRC误 码信息和路由表信息, CRC误码信息以及路由表信息通过待测***的单板管 理控制器 BMC获得后, 再由单板管理控制器通过智能平台管理接口 IPMI发 送给单板管理者服务器。
需要说明的是, 对于第一映射单元 504而言, 一种具体的实现方式是, 第 一映射单元 504具体可以包括:
解析模块,用于从路由表信息中解析出待测***中的每一个节点和待测系 统中其它节点之间的拓朴结构关系。
第一获耳 4莫块,用于根据第一判断结果获取到待测***中的每一个节点和
待测***中其它节点之间是否存在链路故障。
第一显示模块,用于将节点之间存在链路故障的链路显示在拓朴结构关系 上, 得到第一图形化界面。
需要说明的是, 对于第二映射单元 507而言, 一种具体的实现方式是, 第 二映射单元 507具体可以包括:
解析模块,用于从路由表信息中解析出待测***中的每一个节点和待测系 统中其它节点之间的拓朴结构关系。
第二获耳 4莫块,用于根据第二判断结果获取到待测***中的每一个节点和 待测***中其它节点之间是否存在链路故障。
第二显示模块,用于将节点之间存在链路故障的链路显示在拓朴结构关系 上, 得到第二图形化界面。
需要说明的是, 对于 QPI链路监控设备 500而言, 可选的是, 还可以包括 如下单元:
第一报警单元 506, 用于当第一判断结果为循环冗余码校验误码次数超过 预置的循环冗余码校验误码阈值时, 触发第一报警。
第二报警单元 507, 用于当第二判断结果为快速通道互连链路重传次数超 过预置的快速通道互连链路重传阈值时, 触发第二报警。
需要说明的是, 对于 QPI链路监控设备 500而言, 可选的是, 还可以包括 如下单元:
第一隔离单元 508, 用于当第一图形化界面显示异常的快速通道互连链路 时,对异常的快速通道互连链路上的异常节点进行隔离, 并跳回第一判断单元 502执行。
第二隔离单元 509, 用于当第二图形化界面显示异常的快速通道互连链路 时,对异常的快速通道互连链路上的异常节点进行隔离, 并跳回第一判断单元 502执行。
需要说明的是, 上述装置各模块 /单元之间的信息交互、 执行过程等内容, 由于与本发明方法实施例基于同一构思,其带来的技术效果与本发明方法实施 例相同, 具体内容可参见本发明如图 1所示的方法实施例中的叙述, 此处不再 赘述。
本发明实施例中 ,获取单元 501获取到待测***的循环冗余码校验误码信 息和路由表信息之后, 第一判断单元 502判断 CRC误码次数是否超过预置的 CRC误码阈值, 得到第一判断结果, 当第一判断结果为循环冗余码校验误码 次数超过预置的循环冗余码校验误码阈值时,第一映射单元 503将第一判断结 果和路由表信息映射为第一图形化界面,在循环冗余码校验误码次数没有超过 预置的循环冗余码校验误码阈值的情况下,第二判断单元 504判断快速通道互 连链路重传次数是否超过预置的快速通道互连链路重传阈值得到第二判断结 果, 第二映射单元 505将第二判断结果和路由表信息映射为第二图形化界面, 以便用户能够直观查看到整个待测***的 QPI链路连接状态。本发明实施例不 需要增加单独的测试设备和单独的测试软件,从而能够降低测试成本,且操作 过程简单容易实现。
本发明实施例提供的一种快速通道互连链路监控***, 包括: 待测***、 能够显示待测***的节点之间的快速通道互连链路连接状态的快速通道互连 链路监控设备。 其中,
快速通道互连链路监控设备,用于获取待测***的循环冗余码校验误码信 息和路由表信息,循环冗余码校验误码信息包括循环冗余码校验误码次数和快 速通道互连链路重传次数;判断循环冗余码校验误码次数是否超过预置的循环 冗余码校验误码阈值,得到第一判断结果; 若第一判断结果为循环冗余码校验 误码次数超过预置的循环冗余码校验误码阈值,将第一判断结果和路由表信息 映射为第一图形化界面,第一图形化界面用于根据第一判断结果和路由表信息 显示待测***的节点之间的快速通道互连链路连接状态;若第一判断结果为循 环冗余码校验误码次数没有超过预置的循环冗余码校验误码阈值,判断快速通 道互连链路重传次数是否超过预置的快速通道互连链路重传阈值,得到第二判 断结果; 将第二判断结果和路由表信息映射为第二图形化界面, 第二图形化界 面用于根据第二判断结果和路由表信息显示待测***的节点之间的快速通道 互连链路连接状态。
在实际应用中,一种可实现的方式是,快速通道互连链路监控***还包括: OA服务器和交换机, 快速通道互连链路监控设备加载在 OA服务器上, 交换 机用于实现 OA服务器与待测***的数据交互。
待测***包括主节点和单板管理控制器。其中, 主节点用于建立待测*** 的路由表信息; 单板管理控制器用于从主节点处获取路由表信息,通过***管 理总线 SMBUS读取待测***的节点的循环冗余码校验误码信息,通过智能平 台管理接口 IPMI向 OA服务器发送循环冗余码校验误码信息和路由表信息。
OA服务器, 用于接收单板管理控制器发送的循环冗余码校验误码信息和 路由表信息;将循环冗余码校验误码信息和路由表信息发送给快速通道互连链 路监控设备。
在实际应用中, 另一种可实现的方式是, 快速通道互连链路监控***还包 括: OA服务器、 普通个人电脑控制机和交换机, 快速通道互连链路监控设备 加载在普通个人电脑控制机上,交换机用于实现 OA服务器与待测***的数据 交互、 OA服务器与普通个人电脑控制机的交互。
待测***包括主节点和单板管理控制器。其中, 主节点用于建立待测*** 的路由表信息; 单板管理控制器用于从主节点处获取路由表信息,通过***管 理总线 SMBUS读取待测***的节点的循环冗余码校验误码信息,通过智能平 台管理接口 IPMI向 OA服务器发送循环冗余码校验误码信息和路由表信息。
OA服务器, 用于接收单板管理控制器发送的循环冗余码校验误码信息和 路由表信息;将循环冗余码校验误码信息和路由表信息发送给快速通道互连链 路监控设备。
普通个人电脑控制机,用于显示快速通道互连链路监控设备得到的第一图 形化界面或第二图形化界面。
具体的***组网结构, 请参阅图 2所示, 此处不再赘述。
需要说明的是, 上述装置各模块 /单元之间的信息交互、 执行过程等内容, 由于与本发明方法实施例基于同一构思,其带来的技术效果与本发明方法实施 例相同, 具体内容可参见本发明如图 1和图 2所示的方法实施例中的叙述,此 处不再赘述。
本发明实施例中,快速通道互连链路监控设备获取到待测***的循环冗余 码校验误码信息和路由表信息之后,快速通道互连链路监控设备在循环冗余码 校验误码次数超过预置的循环冗余码校验误码阈值的情况下将第一判断结果 和路由表信息映射为第一图形化界面,在循环冗余码校验误码次数没有超过预
置的循环冗余码校验误码阈值的情况下,通过判断快速通道互连链路重传次数 是否超过预置的快速通道互连链路重传阈值得到第二判断结果,将第二判断结 果和路由表信息映射为第二图形化界面。通过第一图形化界面或者第二图形化 界面用户能够直观查看到整个待测***的 QPI链路连接状态。本发明实施例中 获取待测***的循环冗余码校验误码信息和路由表信息可以由一个软件装置 (即本发明实施例中的快速通道互连链路监控设备)即可获取得到, 不需要增 加单独的测试设备(例如不需要增加负载检测板)去实现, 另外该快速通道互 连链路监控设备由第一判断结果或第二判断结果结合路由表信息就能映射得 到图形化界面, 也不需要单独的测试设备 (即不需要增加示波器 )转化为波形 文件输出到一个测试软件 sigtest。本发明实施例可以通过图形化界面就能够实 时的显示 QPI链路连接状态,从而能够降低测试成本,且操作过程简单容易实 现。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤 是可以通过程序来指令相关的硬件完成,该程序可以存储于一种计算机可读存 储介质中, 上述提到的存储介质可以是只读存储器, 磁盘或光盘等。
以上对本发明所提供的一种快速通道互连链路监控方法和设备及***进 行了详细介绍, 对于本领域的一般技术人员, 依据本发明实施例的思想, 在具 体实施方式及应用范围上均会有改变之处, 因此, 本说明书内容不应理解为对 本发明的限制。
Claims
1、 一种快速通道互连链路监控方法, 其特征在于, 包括:
快速通道互连链路监控设备获取待测*** SUT的循环冗余码校验误码信 息和路由表信息,所述循环冗余码校验误码信息包括循环冗余码校验误码次数 和快速通道互连链路重传次数;
所述快速通道互连链路监控设备判断所述循环冗余码校验误码次数是否 超过预置的循环冗余码校验误码阈值, 得到第一判断结果;
若所述第一判断结果为所述循环冗余码校验误码次数超过所述预置的循 环冗余码校验误码阈值,所述快速通道互连链路监控设备将所述第一判断结果 和所述路由表信息映射为第一图形化界面,所述第一图形化界面用于根据所述 第一判断结果和所述路由表信息显示所述待测***的节点之间的快速通道互 连链路连接状态;
若所述第一判断结果为所述循环冗余码校验误码次数没有超过所述预置 的循环冗余码校验误码阈值,所述快速通道互连链路监控设备判断所述快速通 道互连链路重传次数是否超过预置的快速通道互连链路重传阈值,得到第二判 断结果;
所述快速通道互连链路监控设备将所述第二判断结果和所述路由表信息 映射为第二图形化界面,所述第二图形化界面用于根据所述第二判断结果和所 述路由表信息显示所述待测***的节点之间的快速通道互连链路连接状态。
2、 根据权利要求 1所述的快速通道互连链路监控方法, 其特征在于, 所 述快速通道互连链路监控设备获取待测***的循环冗余码校验误码信息和路 由表信息包括:
所述快速通道互连链路监控设备通过与自身连接的单板管理者服务器获 取所述循环冗余码校验误码信息和所述路由表信息,所述循环冗余码校验误码 信息以及所述路由表信息通过所述待测***的单板管理控制器 BMC获得后, 再由所述单板管理控制器通过智能平台管理接口 IPMI发送给所述单板管理者 服务器。
3、 根据权利要求 2所述的快速通道互连链路监控方法, 其特征在于, 所 述循环冗余码校验误码信息通过所述待测***的单板管理控制器获得, 包括: 所述单板管理控制器通过***管理总线 SMBUS 读取所述待测***的节 点的循环冗余码校验误码信息。
4、 根据权利要求 2所述的快速通道互连链路监控方法, 其特征在于, 所 述路由表信息通过所述待测***的单板管理控制器获得, 包括:
所述单板管理控制器从所述主节点处获取所述路由表信息,所述路由表信 息由所述待测***的主节点在所述待测***的所有节点之间交换链路层参数 之后建立。
5、 根据权利要求 4所述的快速通道互连链路监控方法, 其特征在于, 所 述单板管理控制器从所述主节点处获取所述路由表信息包括:
所述单板管理控制器通过键盘控制器规格接口 KCS接收所述主节点的基 本输入输出*** BIOS发送的所述路由表信息;
或,
所述单板管理控制器通过***管理总线读取所述主节点的中央处理单元 相关寄存器并解析出所述路由表信息。
6、 根据权利要求 1至 5中任一项所述的快速通道互连链路监控方法, 其 特征在于,若所述第一判断结果为所述循环冗余码校验误码次数超过所述预置 的循环冗余码校验误码阈值, 所述快速通道互连链路监控设备触发第一报警。
7、 根据权利要求 1至 5中任一项所述的快速通道互连链路监控方法, 其 特征在于,若所述第二判断结果为所述快速通道互连链路重传次数超过所述预 置的快速通道互连链路重传阈值,所述快速通道互连链路监控设备触发第二报
8、 根据权利要求 7所述的快速通道互连链路监控方法, 其特征在于, 在 所述快速通道互连链路监控设备将所述第二判断结果和所述路由表信息映射 为第二图形化界面之前, 所述快速通道互连链路监控设备触发第二报警。
9、 根据权利要求 1至 5中任一项所述的快速通道互连链路监控方法, 所 述方法还包括:
所述第一图形化界面显示异常的快速通道互连链路,所述快速通道互连链 路监控设备对所述异常的快速通道互连链路上的异常节点进行隔离,并跳回判 断所述循环冗余码校验误码次数是否超过预置的循环冗余码校验误码阈值的 步骤。
10、根据权利要求 1至 5中任一项所述的快速通道互连链路监控方法, 若 所述第二判断结果为所述快速通道互连链路重传次数超过所述预置的快速通 道互连链路重传阈值, 所述第二图形化界面显示异常的快速通道互连链路; 若所述第二判断结果为所述快速通道互连链路重传次数没有超过所述预 置的快速通道互连链路重传阈值,所述第二图形化界面显示正常的快速通道互 连链路。
11、 根据权利要求 10所述的快速通道互连链路监控方法, 其特征在于, 所述方法还包括:
当所述第二图形化界面显示异常的快速通道互连链路时,所述快速通道互 连链路监控设备对所述异常的快速通道互连链路上的异常节点进行隔离,并跳 回判断所述循环冗余码校验误码次数是否超过预置的循环冗余码校验误码阈 值的步骤。
12、根据权利要求 1至 5中任一项所述的快速通道互连链路监控方法, 其 特征在于,所述快速通道互连链路监控设备将所述第一判断结果和所述路由表 信息映射为第一图形化界面包括:
所述快速通道互连链路监控设备从所述路由表信息中解析出所述待测系 统中的每一个节点和待测***中其它节点之间的拓朴结构关系;
所述快速通道互连链路监控设备根据所述第一判断结果获取到所述待测 ***中的每一个节点和待测***中其它节点之间是否存在链路故障;
所述快速通道互连链路监控设备将节点之间存在链路故障的链路显示在 所述拓朴结构关系上, 得到所述第一图形化界面。
13、根据权利要求 1至 5中任一项所述的快速通道互连链路监控方法, 其 特征在于,所述快速通道互连链路监控设备将所述第二判断结果和所述路由表 信息映射为第二图形化界面包括:
所述快速通道互连链路监控设备从所述路由表信息中解析出所述待测系 统中的每一个节点和待测***中其它节点之间的拓朴结构关系;
所述快速通道互连链路监控设备根据所述第二判断结果获取到所述待测 ***中的每一个节点和待测***中其它节点之间是否存在链路故障; 所述快速通道互连链路监控设备将节点之间存在链路故障的链路显示在 所述拓朴结构关系上, 得到所述第二图形化界面。
14、 一种快速通道互连链路监控设备, 其特征在于, 包括:
获取单元, 用于获取待测*** SUT的循环冗余码校验误码信息和路由表 信息,所述循环冗余码校验误码信息包括循环冗余码校验误码次数和快速通道 互连链路重传次数;
第一判断单元,用于判断所述循环冗余码校验误码次数是否超过预置的循 环冗余码校验误码阈值, 得到第一判断结果;
第一映射单元,用于当所述第一判断结果为所述循环冗余码校验误码次数 超过所述预置的循环冗余码校验误码阈值时,将所述第一判断结果和所述路由 表信息映射为第一图形化界面,所述第一图形化界面用于根据所述第一判断结 果和所述路由表信息显示所述待测***的节点之间的快速通道互连链路连接 状态;
第二判断单元,用于当所述第一判断结果为所述循环冗余码校验误码次数 没有超过预置的循环冗余码校验误码阈值时,判断所述快速通道互连链路重传 次数是否超过预置的快速通道互连链路重传阈值, 得到第二判断结果;
第二映射单元,用于将所述第二判断结果和所述路由表信息映射为第二图 形化界面,所述第二图形化界面用于根据所述第二判断结果和所述路由表信息 显示所述待测***的节点之间的快速通道互连链路连接状态。
15、 根据权利要求 14所述的快速通道互连链路监控设备, 其特征在于, 所述获取单元具体用于通过与自身连接的单板管理者服务器获取所述循环冗 余码校验误码信息和所述路由表信息,所述循环冗余码校验误码信息以及所述 路由表信息通过所述待测***的单板管理控制器 BMC获得后, 再由所述单板 管理控制器通过智能平台管理接口 IPMI发送给所述单板管理者服务器。
16、根据权利要求 14或 15所述的快速通道互连链路监控设备, 其特征在 于, 所述设备还包括:
第一报警单元,用于当所述第一判断结果为所述循环冗余码校验误码次数 超过预置的循环冗余码校验误码阈值时, 触发第一报警。
17、根据权利要求 14或 15所述的快速通道互连链路监控设备, 其特征在 于, 所述设备还包括:
第二报警单元,用于当所述第二判断结果为所述快速通道互连链路重传次 数超过预置的快速通道互连链路重传阈值时, 触发第二报警。
18、根据权利要求 14或 15所述的快速通道互连链路监控设备, 其特征在 于, 所述设备还包括:
第一隔离单元,用于当所述第一图形化界面显示异常的快速通道互连链路 时,对所述异常的快速通道互连链路上的异常节点进行隔离, 并跳回所述第一 判断单元执行。
19、根据权利要求 14或 15所述的快速通道互连链路监控设备, 其特征在 于, 所述设备还包括:
第二隔离单元,用于当所述第二图形化界面显示异常的快速通道互连链路 时,对所述异常的快速通道互连链路上的异常节点进行隔离, 并跳回所述第一 判断单元执行。
20、根据权利要求 14或 15所述的快速通道互连链路监控设备, 其特征在 于, 所述第一映射单元包括:
解析模块,用于从所述路由表信息中解析出所述待测***中的每一个节点 和待测***中其它节点之间的拓朴结构关系;
第一获耳 4莫块 ,用于根据所述第一判断结果获取到所述待测***中的每一 个节点和待测***中其它节点之间是否存在链路故障;
第一显示模块,用于将节点之间存在链路故障的链路显示在所述拓朴结构 关系上, 得到所述第一图形化界面。
21、根据权利要求 14或 15所述的快速通道互连链路监控设备, 其特征在 于, 所述第二映射单元包括:
解析模块,用于从所述路由表信息中解析出所述待测***中的每一个节点 和待测***中其它节点之间的拓朴结构关系;
第二获耳 4莫块 ,用于根据所述第二判断结果获取到所述待测***中的每一 个节点和待测***中其它节点之间是否存在链路故障;
第二显示模块,用于将节点之间存在链路故障的链路显示在所述拓朴结构 关系上, 得到所述第二图形化界面。
22、一种快速通道互连链路监控***,其特征在于, 包括:待测*** SUT、 能够显示所述待测***的节点之间的快速通道互连链路连接状态的快速通道 互连链路监控设备, 其中,
所述快速通道互连链路监控设备,用于获取所述待测***的循环冗余码校 验误码信息和路由表信息,所述循环冗余码校验误码信息包括循环冗余码校验 误码次数和快速通道互连链路重传次数;判断所述循环冗余码校验误码次数是 否超过预置的循环冗余码校验误码阈值,得到第一判断结果; 若所述第一判断 结果为所述循环冗余码校验误码次数超过所述预置的循环冗余码校验误码阈 值,将所述第一判断结果和所述路由表信息映射为第一图形化界面, 所述第一 图形化界面用于根据所述第一判断结果和所述路由表信息显示所述待测*** 的节点之间的快速通道互连链路连接状态;若所述第一判断结果为所述循环冗 余码校验误码次数没有超过所述预置的循环冗余码校验误码阈值,判断所述快 速通道互连链路重传次数是否超过预置的快速通道互连链路重传阈值,得到第 二判断结果; 将所述第二判断结果和所述路由表信息映射为第二图形化界面, 所述第二图形化界面用于根据所述第二判断结果和所述路由表信息显示所述 待测***的节点之间的快速通道互连链路连接状态。
23、 根据权利要求 22所述的快速通道互连链路监控***, 其特征在于, 所述快速通道互连链路监控***还包括: 单板管理者 OA服务器和交换机, 所 述快速通道互连链路监控设备加载在所述 OA服务器上,所述交换机用于实现 所述 OA服务器与所述待测***的数据交互;
所述待测***包括主节点和单板管理控制器 BMC, 所述主节点用于建立 所述待测***的路由表信息;所述单板管理控制器用于从所述主节点处获取路 由表信息,通过***管理总线 SMBUS读取所述待测***的节点的循环冗余码 校验误码信息, 通过智能平台管理接口 IPMI向所述 OA服务器发送循环冗余 码校验误码信息和路由表信息;
所述 OA服务器,用于将接收所述单板管理控制器发送的循环冗余码校验 误码信息和路由表信息;将所述循环冗余码校验误码信息和路由表信息发送给 所述快速通道互连链路监控设备。
24、 根据权利要求 22所述的快速通道互连链路监控***, 其特征在于, 所述快速通道互连链路监控***还包括: OA服务器、 普通个人电脑控制机和 交换机, 所述快速通道互连链路监控设备加载在所述普通个人电脑控制机上, 所述交换机用于实现所述 OA服务器与所述待测***的数据交互、所述 OA服 务器与所述普通个人电脑控制机的数据交互;
所述待测***包括主节点和单板管理控制器 BMC, 所述主节点用于建立 所述待测***的路由表信息;所述单板管理控制器用于从所述主节点处获取路 由表信息,通过***管理总线 SMBUS读取所述待测***的节点的循环冗余码 校验误码信息, 通过智能平台管理接口 IPMI向所述 OA服务器发送循环冗余 码校验误码信息和路由表信息;
所述 OA服务器,用于接收所述单板管理控制器发送的循环冗余码校验误 码信息和路由表信息;将所述循环冗余码校验误码信息和路由表信息发送给所 述快速通道互连链路监控设备;
所述普通个人电脑控制机,用于显示所述快速通道互连链路监控设备通过 映射得到的第一图形化界面或第二图形化界面。
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US9384085B2 (en) | 2016-07-05 |
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