WO2012135363A2 - Integrated circuit having chemically modified spacer surface - Google Patents

Integrated circuit having chemically modified spacer surface Download PDF

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Publication number
WO2012135363A2
WO2012135363A2 PCT/US2012/030977 US2012030977W WO2012135363A2 WO 2012135363 A2 WO2012135363 A2 WO 2012135363A2 US 2012030977 W US2012030977 W US 2012030977W WO 2012135363 A2 WO2012135363 A2 WO 2012135363A2
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WO
WIPO (PCT)
Prior art keywords
dielectric material
sidewall spacers
spacers
gate stack
gate
Prior art date
Application number
PCT/US2012/030977
Other languages
French (fr)
Other versions
WO2012135363A3 (en
Inventor
Brian K. Kirkpatrick
Amitabh Jain
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/427,062 external-priority patent/US9496359B2/en
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2014502758A priority Critical patent/JP2014514757A/en
Publication of WO2012135363A2 publication Critical patent/WO2012135363A2/en
Publication of WO2012135363A3 publication Critical patent/WO2012135363A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • Disclosed embodiments relate to semiconductor processing and integrated circuit (IC) devices therefrom which include metal-oxide-semiconductor (MOS) transistors, including MOS transistors having multi-layer sidewall spacers.
  • MOS metal-oxide-semiconductor
  • Thin silicon nitride sidewall spacers are commonly used as an implant mask to provide a space between the lightly doped drain (LDD) implants into the semiconductor surface and the gate stack.
  • LDD lightly doped drain
  • a typical process flow has a first spacer layer that acts first as an offset spacer, then as an underlay er/etch- stop while additional films, such as disposable second sidewall spacer comprising SiGe, is deposited on top, used, which is then subsequently removed.
  • hot phosphoric acid (HP A) is used to remove the second sidewall spacer.
  • etch stop characteristics can be lost resulting in inadvertent removal of the silicon nitride offset sidewall spacer, and as a result subsequent shorting between the gate and source and/or drain, such as due to a subsequently deposited silicide ion the gate, source and drain.
  • semiconductor devices are shrunk in size, and the distance between the top of the gate stack and the top surface of the source/drain regions is reduced, the probability of electrical shorts due to the silicide forming on the sidewalls of the gate stack increases.
  • Disclosed embodiments describe solutions to the above-described inadvertent removal of thin sidewall spacers for metal-oxide-semiconductor (MOS) transistors that use multi-layer sidewall spacers.
  • MOS metal-oxide-semiconductor
  • the second material can substantially increase the etch resistance compared to the first spacer material.
  • the subsequent removal of a disposable second spacer on the first spacer will not remove the first spacer since the second dielectric material can act as an etch stop, or at least provide some etch protection for the first dielectric material of the first spacer.
  • One disclosed embodiment comprises a method of fabricating an integrated circuit that includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric.
  • the first dielectric material is etched, such as using RIE, to form sidewall spacers on sidewalls of the gate stack.
  • a top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers.
  • the second dielectric material is chemically bonded across a transition region to the first dielectric material.
  • ion implanting can follow to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack.
  • Second spacers are then formed on the surface converted sidewall spacers.
  • Sources and drains are then formed lateral to the gate stack.
  • Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers.
  • the second sidewall spacers can be used for a SiGe S/D process (e.g., where recesses are formed typically in the PMOS region and replaced with SiGe).
  • the second spacers can then be selective removed after the source/drain formation.
  • the surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
  • FIG. 1 is a flow chart that shows steps in an example method for fabricating an integrated circuit (IC) device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.
  • FIG. 2A-2F are cross-sectional diagrams depicting processing progression for an example method of forming an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing the results from the inadvertent removal of the nitride offset spacer.
  • FIG. 3 is a cross-sectional view of a portion of an IC device including MOS transistors having sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment.
  • FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer, according to an example embodiment.
  • FIG. 1 is a flow chart that shows steps in an example method 100 for fabricating an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.
  • Step 101 comprises depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon comprising a gate electrode on a gate dielectric.
  • Step 102 comprises etching the first dielectric material to form sidewall spacers on sidewalls of the gate stack, such as using RIE.
  • Step 103 comprises chemically converting a top surface of the first dielectric material to a second dielectric material by adding at least one element to provide surface converted sidewall spacers.
  • the second dielectric material is chemically bonded across a transition region to the first dielectric material.
  • the chemically converted top surface of the sidewall spacer becomes an etch stop by adding at least one element to form a second dielectric material, that substantially increases the wet etch resistance of the film as compared to the unconverted first dielectric material, such as to a hot phosphoric acid (HP A) etch.
  • the added element is carbon. In another embodiment both carbon and oxygen are added.
  • the first dielectric material comprises BTBAS- derived silicon nitride, and carbon is added to the top surface of the silicon nitride forming a thin layer, typically 10 to 20 Angstroms thick, of a second dielectric material comprising a silicon carbide (SiC), silicon carbonitride (SiCN) and/or silicon oxy-carbonitride (SiOCN) film.
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • SiOCN silicon oxy-carbonitride
  • SiC, SiCN, or SiOCN were formed, which were all found to be are largely impervious to HPA etch at temperatures below 215 °C. Since HPA is generally used at temperatures between 120 and 180 °C, the underlying silicon nitride sidewall spacer is protected by the second dielectric material.
  • the relationship of the second dielectric material to the first dielectric material for disclosed surface converted sidewall spacers being chemically bonded together is distinct from known arrangements resulting from the vapor deposition (e.g., chemical vapor deposition) of a second dielectric material on a first dielectric material, where the second dielectric material becomes attached to the first dielectric material by comparatively weak Vander walls forces.
  • the area of the second dielectric material matches the area of the first dielectric material.
  • the area of the second dielectric material will be different as compared to the area of the first dielectric material due to the etching process required for spacer formation.
  • Step 104 comprises ion implanting to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack.
  • LDDs lightly doped drains
  • the PMOS transistors and NMOS transistors generally each receive separate LDD implants.
  • Step 105 comprises forming second spacers on the surface converted sidewall spacers.
  • Step 106 comprises forming sources and drains lateral to the gate stack. Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers.
  • the PMOS transistors and NMOS transistors each receive separate source/drain implants.
  • Step 107 comprises selectively removing the second spacers after the source/drain formation (step 106).
  • the surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
  • FIG. 2A-2F are cross-sectional diagrams showing processing progression for an example method of fabricating an IC device having surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing inadvertent removal of the sidewall spacer.
  • FIG. 2A shows a gate stack comprising a gate electrode 211 on a gate dielectric 212 before any sidewall spacer is formed on a substrate 305.
  • Substrate 305 can comprise any substrate material, such as silicon, silicon-germanium, as well as II-VI and III-V substrates, as well as SOI substrates.
  • the gate electrode 211 can comprise polysilicon, or a variety of other gate electrode materials.
  • the gate dielectric 212 can comprise a variety of gate dielectrics, including optional high-k dielectrics defined hereon as having k >3.9, typically a k > 7. In one particular embodiment, the high-k dielectric comprises silicon oxynitride.
  • FIG. 2B shows the gate stack after a sidewall spacer (e.g., a nitride offset spacer) 215 is formed, such as a silicon nitride offset spacer by a RIE process.
  • a sidewall spacer e.g., a nitride offset spacer
  • FIG. 2C shows the results after an ion implantation process, such as LDD ion implantation to form LDD regions 225, that utilized implant blocking provided by the sidewall spacer 215.
  • FIG. 2D shows the resulting structure after disclosed chemical surface conversion step comprising flowing a hydrocarbon gas that forms the surface converted layer 216 shown.
  • FIG. 2E shows the gate stack 211/212 after a subsequent disposable second spacer 235 is formed, such as by chemical deposition followed by RIE. For a typical CMOS process the PMOS transistors and NMOS transistors each then receive separate source/drain implants.
  • FIG. 2F shows the gate stack 212/211 after the disposable second spacer 235 has been selectively removed, such as by a hot (e.g., 120 to 180 °C) HPA etch. Note the surface converted layer 216 remains intact after the etch, as does the sidewall spacer 215 protected by the surface converted layer 216. Without a disclosed surface converted layer, the sidewall spacer 215, such as it comprises silicon nitride, is subject to removal using the process used to remove the disposable second spacer 235.
  • FIG. 2G shows the resulting spacer structure after a known spacer process showing the results after inadvertent complete removal of the sidewall spacer 215. [0021] FIG.
  • IC 300 includes MOS transistors having surface converted sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment.
  • BEOL Back end of the line
  • IC 300 includes a substrate 305, such as a p-type silicon or p-type silicon-germanium substrate, having a semiconductor surface 306.
  • Optional trench isolation 308 is shown, such as shallow trench isolation (STI).
  • An n-channel MOS (NMOS) transistor 310 is shown, along with a p-channel MOS (PMOS) transistor 320 that is within an n-well 307.
  • NMOS transistor 310 includes a gate stack including a gate electrode 311 on a gate dielectric 312 having sidewall spacers on sidewalls of the gate stack.
  • the sidewall spacers comprise a second dielectric material 315a on a first dielectric material 315b, wherein the second dielectric material 315a is chemically bonded across a transition region 315c to the first dielectric material 315b.
  • the second dielectric material 315a comprises carbon and the first dielectric material does not comprise carbon, wherein "not comprising carbon” as used herein refers to a wt. % of C ⁇ 3 %.
  • NMOS transistor 310 includes source 321 and drain 322 regions lateral to the sidewall spacers, and include lightly doped extensions 321a and 322a.
  • a silicide layer 316 is shown on the gate electrode 311 and the source 321 and drain 322.
  • PMOS transistor 320 includes a gate stack including a gate electrode 331 on a gate dielectric 332 (which can be the same material as gate dielectric 312 under gate electrode 311) having sidewall spacers on sidewalls of the gate stack, comprising the second dielectric material 315a on a first dielectric material 315b, wherein the second dielectric material 315a is chemically bonded across a transition region 315c to the first dielectric material 315b.
  • the second dielectric material 315a comprises carbon and the first dielectric material does not comprise carbon.
  • PMOS transistor 320 includes source 341 and drain 342 regions lateral to the sidewall spacers, and include lightly doped extensions 341a and 342a.
  • Silicide layer 316 is shown on the gate electrode 331 and on the source 341 and drain 342.
  • the total thickness of the sidewall spacer 315a/315c/315b at its widest point at its base is generally ⁇ 100 Angstroms, such as 40 to 70 Angstroms thick.
  • second dielectric material 315a is about 5 to 10 angstroms thick
  • transition region 315c is 15 to 25 Angstroms thick
  • the first dielectric material 315b is 20 to 30 Angstroms thick.
  • FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer 400, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer 400, according to an example embodiment.
  • the surface converted sidewall spacer 400 includes a non-constant chemical composition profile across its thickness comprising a first dielectric material 315b on the sidewall of a gate stack material and a chemically converted top (outer) surface comprising a second dielectric material 315a chemically bonded across a transition region 315c to the first dielectric material 315b.
  • the first dielectric material 315b comprises silicon nitride (roughly Si 3 N 4 )
  • the second dielectric material 315a comprises silicon carbide (SiC)
  • the transition region 315c includes a material comprising Si, N and C, where the C content decreases and the N content increases as the distance to the second dielectric material 315a /gate stack is reduced.
  • Disclosed semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
  • the semiconductor die can be formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.

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Abstract

A method (100) of fabricating an integrated circuit includes depositing (101) a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched (102) to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted (103) to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

Description

INTEGRATED CIRCUIT HAVING CHEMICALLY MODIFIED SPACER SURFACE
[0001] Disclosed embodiments relate to semiconductor processing and integrated circuit (IC) devices therefrom which include metal-oxide-semiconductor (MOS) transistors, including MOS transistors having multi-layer sidewall spacers.
BACKGROUND
[0002] While processing semiconductor wafers it is often advantageous to deposit or form films that can later act as etch stop layers when subsequently deposited or formed films are removed. However, if the film does not have sufficient etch resistance during later processing, such films can be inadvertently removed.
[0003] One example of inadvertent removal involves thin silicon nitride sidewall (or offset) spacers for MOS transistors. Thin silicon nitride sidewall spacers are commonly used as an implant mask to provide a space between the lightly doped drain (LDD) implants into the semiconductor surface and the gate stack. A typical process flow has a first spacer layer that acts first as an offset spacer, then as an underlay er/etch- stop while additional films, such as disposable second sidewall spacer comprising SiGe, is deposited on top, used, which is then subsequently removed. In one process flow hot phosphoric acid (HP A) is used to remove the second sidewall spacer. However, even silicon nitride spacers formed from bis- tertiarybutylamino-silane (BTBAS) and ammonia reagents, where BTBAS-based silicon nitride is known to be the most wet etch resistant silicon nitride film to HP A, are not always capable of stopping the HPA etch when the disposable SiGe second sidewall spacer is removed. In particular, if the silicon nitride sidewall spacer has been exposed to reducing chemistries, such as plasmas containing H2 or N2, etch stop characteristics can be lost resulting in inadvertent removal of the silicon nitride offset sidewall spacer, and as a result subsequent shorting between the gate and source and/or drain, such as due to a subsequently deposited silicide ion the gate, source and drain. Moreover, as semiconductor devices are shrunk in size, and the distance between the top of the gate stack and the top surface of the source/drain regions is reduced, the probability of electrical shorts due to the silicide forming on the sidewalls of the gate stack increases.
SUMMARY
[0004] Disclosed embodiments describe solutions to the above-described inadvertent removal of thin sidewall spacers for metal-oxide-semiconductor (MOS) transistors that use multi-layer sidewall spacers. By chemically converting the top surface of a first sidewall spacer comprising a first material by adding at least one element to form a second dielectric material, the second material can substantially increase the etch resistance compared to the first spacer material. As a result, the subsequent removal of a disposable second spacer on the first spacer will not remove the first spacer since the second dielectric material can act as an etch stop, or at least provide some etch protection for the first dielectric material of the first spacer.
[0005] One disclosed embodiment comprises a method of fabricating an integrated circuit that includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched, such as using RIE, to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.
[0006] Following forming the surface converted sidewall spacers, ion implanting can follow to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack. Second spacers are then formed on the surface converted sidewall spacers. Sources and drains are then formed lateral to the gate stack. Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers. Alternatively, the second sidewall spacers can be used for a SiGe S/D process (e.g., where recesses are formed typically in the PMOS region and replaced with SiGe). The second spacers can then be selective removed after the source/drain formation. The surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a flow chart that shows steps in an example method for fabricating an integrated circuit (IC) device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.
[0010] FIG. 2A-2F are cross-sectional diagrams depicting processing progression for an example method of forming an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing the results from the inadvertent removal of the nitride offset spacer.
[0011] FIG. 3 is a cross-sectional view of a portion of an IC device including MOS transistors having sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment.
[0012] FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer, according to an example embodiment.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0013] FIG. 1 is a flow chart that shows steps in an example method 100 for fabricating an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment. Step 101 comprises depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon comprising a gate electrode on a gate dielectric. Step 102 comprises etching the first dielectric material to form sidewall spacers on sidewalls of the gate stack, such as using RIE.
[0014] Step 103 comprises chemically converting a top surface of the first dielectric material to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material. The chemically converted top surface of the sidewall spacer becomes an etch stop by adding at least one element to form a second dielectric material, that substantially increases the wet etch resistance of the film as compared to the unconverted first dielectric material, such as to a hot phosphoric acid (HP A) etch. In one embodiment the added element is carbon. In another embodiment both carbon and oxygen are added.
[0015] In one specific example, the first dielectric material comprises BTBAS- derived silicon nitride, and carbon is added to the top surface of the silicon nitride forming a thin layer, typically 10 to 20 Angstroms thick, of a second dielectric material comprising a silicon carbide (SiC), silicon carbonitride (SiCN) and/or silicon oxy-carbonitride (SiOCN) film. This can be accomplished by exposing a BTBAS silicon nitride film that was previously used as a gate stack sidewall to a flow of 30 to 3000 seem of ethylene, acetylene, or similar hydrocarbon gas at a temperature generally between 300 and 800 °C, and pressure between about 0.1 and 10 Torr, for 15 - 600 seconds or longer prior to depositing a subsequent disposable spacer film. In experiments performed, SiC, SiCN, or SiOCN were formed, which were all found to be are largely impervious to HPA etch at temperatures below 215 °C. Since HPA is generally used at temperatures between 120 and 180 °C, the underlying silicon nitride sidewall spacer is protected by the second dielectric material.
[0016] Besides clear process differences, the relationship of the second dielectric material to the first dielectric material for disclosed surface converted sidewall spacers being chemically bonded together is distinct from known arrangements resulting from the vapor deposition (e.g., chemical vapor deposition) of a second dielectric material on a first dielectric material, where the second dielectric material becomes attached to the first dielectric material by comparatively weak Vander walls forces. Moreover, inherently due to the disclosed chemical conversion process, the area of the second dielectric material matches the area of the first dielectric material. In contrast, for a known arrangements resulting from the vapor deposition of a second dielectric material on a first dielectric material, the area of the second dielectric material will be different as compared to the area of the first dielectric material due to the etching process required for spacer formation.
[0017] Step 104 comprises ion implanting to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack. For a CMOS process the PMOS transistors and NMOS transistors generally each receive separate LDD implants. Step 105 comprises forming second spacers on the surface converted sidewall spacers. Step 106 comprises forming sources and drains lateral to the gate stack. Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers. For a typical CMOS process the PMOS transistors and NMOS transistors each receive separate source/drain implants. However, alternatively, the second sidewall spacers can also be used for a SiGe S/D process (e.g., where recesses are formed typically in the PMOS region and replaced with SiGe). Step 107 comprises selectively removing the second spacers after the source/drain formation (step 106). The surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
[0018] FIG. 2A-2F are cross-sectional diagrams showing processing progression for an example method of fabricating an IC device having surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing inadvertent removal of the sidewall spacer. FIG. 2A shows a gate stack comprising a gate electrode 211 on a gate dielectric 212 before any sidewall spacer is formed on a substrate 305. Substrate 305 can comprise any substrate material, such as silicon, silicon-germanium, as well as II-VI and III-V substrates, as well as SOI substrates. The gate electrode 211 can comprise polysilicon, or a variety of other gate electrode materials. The gate dielectric 212 can comprise a variety of gate dielectrics, including optional high-k dielectrics defined hereon as having k >3.9, typically a k > 7. In one particular embodiment, the high-k dielectric comprises silicon oxynitride.
[0019] FIG. 2B shows the gate stack after a sidewall spacer (e.g., a nitride offset spacer) 215 is formed, such as a silicon nitride offset spacer by a RIE process. FIG. 2C shows the results after an ion implantation process, such as LDD ion implantation to form LDD regions 225, that utilized implant blocking provided by the sidewall spacer 215. FIG. 2D shows the resulting structure after disclosed chemical surface conversion step comprising flowing a hydrocarbon gas that forms the surface converted layer 216 shown. FIG. 2E shows the gate stack 211/212 after a subsequent disposable second spacer 235 is formed, such as by chemical deposition followed by RIE. For a typical CMOS process the PMOS transistors and NMOS transistors each then receive separate source/drain implants.
[0020] The disposable second spacer 235 is then selectively removed after source/drain formation. FIG. 2F shows the gate stack 212/211 after the disposable second spacer 235 has been selectively removed, such as by a hot (e.g., 120 to 180 °C) HPA etch. Note the surface converted layer 216 remains intact after the etch, as does the sidewall spacer 215 protected by the surface converted layer 216. Without a disclosed surface converted layer, the sidewall spacer 215, such as it comprises silicon nitride, is subject to removal using the process used to remove the disposable second spacer 235. FIG. 2G shows the resulting spacer structure after a known spacer process showing the results after inadvertent complete removal of the sidewall spacer 215. [0021] FIG. 3 is a cross-sectional view of a portion of an IC device 300 (e.g., a semiconductor die) including MOS transistors having surface converted sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment. Back end of the line (BEOL) metallization is not shown for simplicity. IC 300 includes a substrate 305, such as a p-type silicon or p-type silicon-germanium substrate, having a semiconductor surface 306. Optional trench isolation 308 is shown, such as shallow trench isolation (STI). An n-channel MOS (NMOS) transistor 310 is shown, along with a p-channel MOS (PMOS) transistor 320 that is within an n-well 307.
[0022] NMOS transistor 310 includes a gate stack including a gate electrode 311 on a gate dielectric 312 having sidewall spacers on sidewalls of the gate stack. The sidewall spacers comprise a second dielectric material 315a on a first dielectric material 315b, wherein the second dielectric material 315a is chemically bonded across a transition region 315c to the first dielectric material 315b. The second dielectric material 315a comprises carbon and the first dielectric material does not comprise carbon, wherein "not comprising carbon" as used herein refers to a wt. % of C < 3 %.
[0023] NMOS transistor 310 includes source 321 and drain 322 regions lateral to the sidewall spacers, and include lightly doped extensions 321a and 322a. A silicide layer 316 is shown on the gate electrode 311 and the source 321 and drain 322.
[0024] Similarly, PMOS transistor 320 includes a gate stack including a gate electrode 331 on a gate dielectric 332 (which can be the same material as gate dielectric 312 under gate electrode 311) having sidewall spacers on sidewalls of the gate stack, comprising the second dielectric material 315a on a first dielectric material 315b, wherein the second dielectric material 315a is chemically bonded across a transition region 315c to the first dielectric material 315b. The second dielectric material 315a comprises carbon and the first dielectric material does not comprise carbon. PMOS transistor 320 includes source 341 and drain 342 regions lateral to the sidewall spacers, and include lightly doped extensions 341a and 342a. Silicide layer 316 is shown on the gate electrode 331 and on the source 341 and drain 342. [0025] The total thickness of the sidewall spacer 315a/315c/315b at its widest point at its base is generally < 100 Angstroms, such as 40 to 70 Angstroms thick. For example, in one particular embodiment second dielectric material 315a is about 5 to 10 angstroms thick, transition region 315c is 15 to 25 Angstroms thick, and the first dielectric material 315b is 20 to 30 Angstroms thick.
[0026] FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer 400, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer 400, according to an example embodiment. The surface converted sidewall spacer 400 includes a non-constant chemical composition profile across its thickness comprising a first dielectric material 315b on the sidewall of a gate stack material and a chemically converted top (outer) surface comprising a second dielectric material 315a chemically bonded across a transition region 315c to the first dielectric material 315b. In the embodiment shown the first dielectric material 315b comprises silicon nitride (roughly Si3N4), the second dielectric material 315a comprises silicon carbide (SiC), and the transition region 315c includes a material comprising Si, N and C, where the C content decreases and the N content increases as the distance to the second dielectric material 315a /gate stack is reduced.
[0027] Disclosed semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.
[0028] Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.

Claims

CLAIMS What is claimed is:
1. A method of fabricating an integrated circuit, comprising:
depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric;
etching said first dielectric material to form sidewall spacers comprising said first dielectric material on sidewalls of said gate stack, and
chemically converting a top surface of said first dielectric material to a second dielectric material by adding at least one element thereto to provide surface converted sidewall spacers,
wherein said second dielectric material is chemically bonded across a transition region to said first dielectric material.
2. The method of claim 1, wherein said etching comprises reactive ion etching (RIE) and wherein said chemically converting comprises flowing a gas under conditions to generate a chemical reaction with said first dielectric material.
3. The method of claim 2, wherein said conditions comprise flowing a hydrocarbon gas at a temperature between 300 °C and 800 °C, wherein said element comprises carbon, and wherein said first dielectric material does not comprise carbon.
4. The method of claim 3, wherein said first dielectric material comprises silicon nitride and said second dielectric material comprises silicon carbide (SiC), silicon carbonitride (SiCN) or silicon oxy-carbonitride (SiOCN).
5. The method of claim 1, further comprising:
ion implanting to form lightly doped sources and drains in said semiconductor surface lateral to said gate stack;
forming second spacers on said surface converted sidewall spacers; forming sources and drains in said semiconductor surface lateral to said gate stack after said forming said second spacers, and
selectively removing said second spacers after said forming said sources and drains.
6. The method of claim 5, wherein said selective removing comprises a phosphoric acid (HP A) etch.
7. The method of claim 6, wherein a temperature for said HPA etch is between 120 and 180 °C.
8. The method of claim 1, wherein said first dielectric material comprises silicon nitride.
9. A method of fabricating an integrated circuit, comprising:
depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric;
reactive ion etching (RIE) said first dielectric material to form sidewall spacers comprising said first dielectric material on sidewalls of said gate stack;
chemically converting a top surface of said first dielectric material to a second dielectric material by adding at least one element thereto to provide surface converted sidewall spacers,
wherein said chemically converting comprises flowing a hydrocarbon gas at a temperature between 300 °C and 800 °C under conditions to generate a chemical reaction with said first dielectric material,
wherein said element comprises carbon, and wherein said first dielectric material does not comprise carbon, and
wherein said second dielectric material is chemically bonded across a transition region to said first dielectric material.
10. The method of claim 9, further comprising: forming second spacers on said surface converted sidewall spacers;
ion implanting to form sources and drains in said semiconductor surface lateral to said gate stack after forming said second spacers, and
selective removing said second spacers after said ion implanting using a phosphoric acid (HP A) etch at a temperature between 120 and 180 °C.
11. An integrated circuit (IC), comprising:
a substrate having a semiconductor surface,
at least one metal-oxide-semiconductor (MOS) transistor on said semiconductor surface, said MOS transistor comprising:
a gate stack including a gate electrode on a gate dielectric having sidewall spacers on sidewalls of said gate stack, said sidewall spacers comprising a second dielectric material on a first dielectric material, and
source and drain regions lateral to said sidewall spacers,
wherein said second dielectric material comprises carbon and said first dielectric material does not comprise carbon, and
wherein said second dielectric material is chemically bonded across a transition region to said first dielectric material.
12. The IC of claim 10, wherein said first dielectric material comprises silicon nitride and said second dielectric material comprises (SiC), silicon carbonitride (SiCN) or silicon oxy-carbonitride (SiOCN).
13. The IC of claim 10, wherein an area of said second dielectric material matches an area of said first dielectric material.
14. The IC of claim 10, wherein a total thickness of said sidewall spacers is < 100 Angstroms.
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