WO2012124699A1 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
WO2012124699A1
WO2012124699A1 PCT/JP2012/056445 JP2012056445W WO2012124699A1 WO 2012124699 A1 WO2012124699 A1 WO 2012124699A1 JP 2012056445 W JP2012056445 W JP 2012056445W WO 2012124699 A1 WO2012124699 A1 WO 2012124699A1
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WO
WIPO (PCT)
Prior art keywords
signal line
liquid crystal
substrate
pixel
holding member
Prior art date
Application number
PCT/JP2012/056445
Other languages
French (fr)
Japanese (ja)
Inventor
智 堀内
冨永　真克
祐子 久田
Original Assignee
シャープ株式会社
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Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP2013504743A priority Critical patent/JPWO2012124699A1/en
Publication of WO2012124699A1 publication Critical patent/WO2012124699A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars

Definitions

  • the present invention relates to a liquid crystal display device, and more particularly to a holding member (spacer) that holds a gap between a pair of substrates.
  • the liquid crystal display device includes a pair of substrates and a liquid crystal layer disposed between the substrates.
  • An example of a conventional liquid crystal display device will be given below.
  • FIG. 19 is a cross-sectional view showing a schematic configuration of a TN liquid crystal display device using a thin film transistor (TFT) as a switching element.
  • SUB1 is a lower substrate
  • SUB2 is an upper substrate
  • a multilayer structure film including a signal line, an electrode, an insulating layer, and other functional films is formed on the inner surface of each substrate.
  • the inner surface of the lower substrate SUB1 has a TFT
  • the inner surface of the upper substrate SUB2 has a common electrode COM and three color (red, green, blue) color filter layers FIL (FIL (R), FIL (G), FIL (B); FIL (B) is not shown).
  • the TFT has a gate electrode GT, a semiconductor layer AS, a source electrode SD1, and a drain electrode SD2 connected to a scanning signal line (not shown).
  • the source electrode SD1 is connected to the pixel electrode ITO1.
  • a gate insulating layer GI, a passivation layer PSV1, and the like are provided, and an alignment film ORI1 is applied to the entire surface including the TFT to form a multilayer structure film.
  • reference numerals d0, d1, d2, and d3 are metal films constituting each layer.
  • FIG. 20 is a plan view showing an example of a spacer installation position in a conventional liquid crystal display device.
  • FIG. 20 shows a state in which the lower substrate is viewed from the upper substrate (viewed in a plan view), and the multilayer structure film of the upper substrate shows the opening of the black matrix BM in outline.
  • Scan signal lines GL, data signal lines DL, TFTs, and pixel electrodes ITO1 are formed on the inner surface of the lower substrate SUB1.
  • the spacer SOC is fixedly provided on the inner surface of the upper substrate SUB2 so as to be positioned on the scanning signal line GL or the data signal line DL which is a portion outside the pixel region so as not to affect the display quality. Yes.
  • Japanese Patent Publication Japanese Laid-Open Patent Publication No. 2003-5190 (released on January 8, 2003)”
  • the spacer SOC is provided on a convex portion which is a raised portion of the multilayer structure film of the lower substrate SUB1. Therefore, in such a spacer arrangement, when an external force (arrows F1 and F2 in FIG. 21B) is applied to the substrate after the pair of substrates are bonded together (FIG. 21A), the spacer There is a possibility that the SOC slides down from the convex portion LYT of the multilayer structure film LY of the lower substrate to the concave portion LYB ((b) of FIG. 21). As a result, the positional relationship between the upper and lower substrates shifts, the set cell gap fluctuates, and the display quality deteriorates.
  • Patent Document 1 a method in which a spacer SOC is provided in advance in the recess LYB between the signal lines L has been proposed.
  • the external force is applied. Therefore, it is difficult to completely suppress the fluctuation of the cell gap.
  • the present invention proposes a liquid crystal display device capable of suppressing the fluctuation of the cell gap between a pair of substrates without reducing the transmittance.
  • the liquid crystal display device provides A first substrate including a first signal line and a second signal line arranged adjacent to each other in parallel; a second substrate disposed opposite to the first substrate and provided with a light shielding layer; and the first substrate A liquid crystal panel including a substrate and a liquid crystal layer disposed between the second substrate, A holding member is provided between the first substrate and the second substrate to hold a gap between the two substrates.
  • the holding member is partially provided between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan view,
  • the distance between the first signal line and the second signal line in the portion where the holding member is provided is equal to the first signal line in at least a part of the portion where the holding member is not provided. It is larger than the distance between the second signal lines.
  • the holding member in a portion where the holding member is provided (a region where the first signal line and the second signal line face each other through the holding member), at least a part of the portion where the holding member is not provided
  • the distance between both signal lines is larger than that.
  • the first signal line can be provided with a notch.
  • the distance between the first signal line and the second signal line and the width of the light shielding layer are maintained without increasing from the conventional configuration of FIG. 22 as in the configuration of FIG. 4A. Only the region where the member is arranged can be expanded.
  • the holding member does not have to be provided in all the notches, and may be provided in at least some of the notches.
  • the region in which the holding member is disposed can be equal to or greater than the region in which the holding member is disposed in the conventional configuration illustrated in FIG. Can be reliably suppressed.
  • the present liquid crystal display device it is possible to suppress the variation in the cell gap between the pair of substrates without reducing the transmittance.
  • the liquid crystal display device provides A first substrate including a first signal line and a second signal line arranged adjacent to each other in parallel; a second substrate disposed opposite to the first substrate and provided with a light shielding layer; and the first substrate A liquid crystal panel including a substrate and a liquid crystal layer disposed between the second substrate, A holding member is provided between the first substrate and the second substrate to hold a gap between the two substrates.
  • the holding member is partially provided between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan view,
  • a height adjusting portion is provided in an upper layer portion of each of the first signal line and the second signal line in a portion where the holding member is provided.
  • the holding member has the first signal line and the second signal in the region where the light shielding layer is formed when the liquid crystal panel is viewed in plan.
  • the part where the holding member is not provided is the distance between the first signal line and the second signal line in the part where the holding member is provided. Is configured to be larger than the distance between the first signal line and the second signal line in at least a part thereof.
  • the holding member is formed between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan.
  • a height adjustment portion is provided in each upper layer portion of the first signal line and the second signal line in the portion where the holding member is provided. is there.
  • FIG. 3 is a cross-sectional view taken along the line AB of FIG. It is a top view for demonstrating the relationship between a black matrix and a spacer, (a) shows the conventional structure, (b) shows this Embodiment. It is a top view which shows the example of arrangement
  • FIG. 11 is a cross-sectional view taken along the line AB of FIG.
  • FIG. 11 is a cross-sectional view taken along the line AB of FIG.
  • FIG. 4 is a top view which shows the modification 4 of the liquid crystal panel of FIG.
  • FIG. 10 is sectional drawing which shows the modification of the spacer which concerns on this Embodiment.
  • FIG. 10 is sectional drawing which shows the modification of the spacer which concerns on this Embodiment.
  • FIG. 10 is an equivalent circuit diagram showing a sixth modification of the liquid crystal panel constituting the liquid crystal display device of FIG. 1. It is a top view which shows the specific example of the liquid crystal panel of FIG. FIG. 18 is a cross-sectional view taken along the line AB of FIG. It is sectional drawing which shows schematic structure of the conventional liquid crystal display device. It is a top view which shows an example of the installation position of the spacer in the conventional liquid crystal display device. It is sectional drawing which shows typically the board
  • the extending direction of the scanning signal lines is hereinafter referred to as the row direction.
  • the scanning signal line may extend in the horizontal direction or in the vertical direction. Needless to say.
  • FIG. 1 is an equivalent circuit diagram showing a part of a liquid crystal panel 2 constituting the liquid crystal display device 1 according to the present embodiment.
  • the liquid crystal panel 2 includes data signal lines DL1 and DL2 extending in the column direction (up and down direction in the drawing), scanning signal lines GL1 and GL2 extending in the row direction (left and right direction in the drawing), and a storage capacitor.
  • Wiring CSL1, CSL2, pixels 101 to 104 arranged in the row and column directions, and a common electrode (counter electrode) com are provided.
  • Each pixel has the same structure. Note that a pixel column including the pixels 101 and 102 and a pixel column including the pixels 103 and 104 are adjacent to each other.
  • one data signal line DL, one scanning signal line GL, and one storage capacitor line CSL are provided corresponding to one pixel.
  • the pixel 101 is provided with a pixel electrode 16a
  • the pixel 102 is provided with a pixel electrode 16b
  • the pixel 103 is provided with a pixel electrode 16c
  • the pixel 104 is provided with one pixel electrode 16d.
  • two or more pixel electrodes may be provided in one pixel.
  • the pixel electrode 16a is connected to the data signal line DL1 via the transistor TFT1 connected to the scanning signal line GL1, and a storage capacitor Cha is formed between the pixel electrode 16a and the storage capacitor line CSL1, and the pixel electrode 16a.
  • a liquid crystal capacitor Cla is formed between the common electrodes com.
  • the pixel electrode 16b is connected to the data signal line DL1 via the transistor TFT2 connected to the scanning signal line GL2, and a storage capacitor Chb is formed between the pixel electrode 16b and the storage capacitor line CSL2, and the pixel electrode 16b.
  • a liquid crystal capacitance Clb is formed between the common electrodes com.
  • the pixel electrode 16c is connected to the data signal line DL2 via the transistor TFT3 connected to the scanning signal line GL1, and a storage capacitor Chc is formed between the pixel electrode 16c and the storage capacitor line CSL1, A liquid crystal capacitance Clc is formed between the pixel electrode 16c and the common electrode com.
  • the pixel electrode 16d is connected to the data signal line DL2 through the transistor TFT4 connected to the scanning signal line GL2, and a storage capacitor Chd is formed between the pixel electrode 16d and the storage capacitor line CSL2, and the pixel electrode 16d.
  • a liquid crystal capacitor Cld is formed between the common electrodes com.
  • the data signal line DL1 is provided along the pixel 101 and the pixel 102
  • the data signal line DL2 is provided along the pixel 103 and the pixel 104
  • the storage capacitor line CSL1 is connected to the pixel 101, 103
  • the storage capacitor line CSL2 crosses the pixels 102 and 104, respectively.
  • the scanning signal line GL1 is disposed on one end side of the pixel 101, and the storage capacitor line CSL1 is disposed on the other end side, and the pixel electrode is disposed between the scanning signal line GL1 and the storage capacitor line CSL1 in plan view. 16a is arranged. Similarly, the scanning signal line GL1 is disposed on one end side of the pixel 103, and the storage capacitor line CSL1 is disposed on the other end side, and when viewed in plan, between the scanning signal line GL1 and the storage capacitor line CSL1.
  • the pixel electrode 16c is arranged on the front side. As shown in FIG. 2, the storage capacitor line CSL1 may overlap the pixel electrodes 16a and 16c in plan view.
  • the scanning signal line GL1 is partially provided with a notch 24 in the region of the pixel 101.
  • the scanning signal line GL2 is disposed on one end side of the pixel 102, and the storage capacitor line CSL2 is disposed on the other end side, and when viewed in plan, between the scanning signal line GL2 and the storage capacitor line CSL2.
  • a pixel electrode 16b is disposed.
  • the scanning signal line GL2 is disposed on one end side of the pixel 104, and the storage capacitor line CSL2 is disposed on the other end side, and when viewed in plan, between the scanning signal line GL2 and the storage capacitor line CSL2.
  • the pixel electrode 16d is disposed on the front side. As shown in FIG. 2, the storage capacitor line CSL2 may overlap the pixel electrodes 16b and 16d in a plan view.
  • the scanning signal line GL2 is partially provided with a notch 24 in the region of the pixel 102.
  • FIG. 2 shows a formation region of the black matrix BM (light shielding layer).
  • BM black matrix
  • the liquid crystal panel 2 is shown in a transparent state as seen in a plan view, but the inside of the rectangle indicated by BM is an opening area (transmission area) of the black matrix, and the outside is a light shielding area.
  • the source electrode sa and the drain electrode da of the transistor TFT1 are formed on the scanning signal line GL1.
  • the source electrode sa is connected to the data signal line DL1
  • the drain electrode da is connected to a drain lead wiring (not shown), and the drain lead wiring is connected to the pixel electrode 16a via a contact hole ca.
  • the storage capacitor line CSL1 is connected to the capacitor electrode 12a, and the capacitor electrode 12a overlaps the pixel electrode 16a through the gate insulating film and the interlayer insulating film, thereby forming a storage capacitor Cha (see FIG. 1).
  • FIG. 3 is a cross-sectional view taken along the line AB of FIG.
  • the liquid crystal panel 2 includes an active matrix substrate 10 (first substrate), a color filter substrate 20 (second substrate) opposed thereto, and a liquid crystal layer disposed between the substrates 10 and 20. 30.
  • the liquid crystal panel 2 includes a spacer 22 (holding member) for holding (regulating) the gap (cell gap) between the substrates 10 and 20.
  • the scanning signal line GL1 and the capacitor electrodes 12a, 12b, and 12c are formed on the glass substrate 11, the storage capacitor line CSL2 is formed on the capacitor electrode 12b, and the inorganic gate insulating film 13 is formed so as to cover them.
  • the gate insulating film 13 is formed.
  • a data signal line DL2, a semiconductor layer 14, a source electrode sa and a drain electrode da (see FIG. 2) are formed on the gate insulating film 13, and an inorganic interlayer insulating film 15 (hereinafter referred to as an interlayer insulating film 15) is formed so as to cover them. Is formed).
  • Pixel electrodes 16a, 16b, and 16c are formed on the interlayer insulating film 15, and an alignment film (not shown) is formed so as to cover the pixel electrodes 16a, 16b, and 16c.
  • the spacer 22 is provided so as to be received in the notch 24 (see FIG. 2) of the scanning signal line GL1.
  • the interlayer insulating film 15 is penetrated, whereby the pixel electrode 16a and the drain electrode da are connected. Further, the capacitor electrode 12a overlaps the capacitor electrode 16a with the gate insulating film 13 and the interlayer insulating film 15 interposed therebetween, whereby a storage capacitor Cha (see FIG. 1) is formed, and the capacitor electrode 12b is connected to the gate insulating film 13 and The capacitor electrode 16b overlaps with the interlayer insulating film 15 interposed therebetween, whereby a storage capacitor Chb (see FIG. 1) is formed.
  • the black matrix BM is formed on the glass substrate 21
  • the color filter layer CF is formed on the upper layer
  • the common electrode com (see FIG. 2) is formed on the upper layer, and further covers this.
  • an alignment film (not shown) is formed.
  • CF (R) represents a red color filter layer
  • CF (G) represents a green color filter layer.
  • the spacer 22 is further formed on the color filter substrate 20.
  • the spacer 22 is provided in the formation region of the black matrix BM in order to prevent the display quality from being deteriorated due to a decrease in transmittance or the like.
  • One spacer 22 may be provided for each pixel, one spacer may be provided for three pixels (for example, RGB pixels), or a smaller ratio (one for a plurality of pixels). May be provided at a ratio of two). For example, a configuration in which one spacer 22 is provided for every R pixel, or a configuration in which spacers 22 are provided for every other pixel or every two or more, focusing on the R pixels arranged in the matrix direction.
  • the spacer 22 is alternately set to 1 for the R pixel, the G pixel, and the B pixel. It can be set as the structure provided one by one.
  • the types of pixels are not limited to R pixels, G pixels, and B pixels corresponding to R (red), G (green), and B (blue) colors, but Y (yellow) and W (white) ) Y and W pixels corresponding to colors may be included.
  • the spacer 22 is formed at a position that is received by the notch 24 of the scanning signal line GL when the active matrix substrate 10 and the color filter substrate 20 are bonded together. That is, the spacer 22 is provided so as to be received by the cutout portion 24 of the scanning signal line GL (first signal line) in the region where the black matrix BM is formed when the liquid crystal panel 2 is viewed in plan. ing.
  • the notch 24 of the scanning signal line GL is formed in a shape that can receive the spacer 22 and can be determined according to the shape of the spacer 22.
  • the shape of the spacer 22 is not limited to a circle, and may be an ellipse or a rectangle.
  • the manufacturing method of the liquid crystal panel 2 includes an active matrix substrate manufacturing process, a color filter substrate manufacturing process, and an assembling process in which both substrates are bonded together and filled with liquid crystal.
  • the manufacturing process of the active matrix substrate 10 will be described.
  • a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, copper, or an alloy film thereof or a laminate thereof is formed on a transparent insulating substrate (glass substrate 11 in FIG. 3) such as glass or plastic.
  • a transparent insulating substrate glass substrate 11 in FIG. 3
  • a scanning signal line functioning as a gate electrode of each transistor
  • a storage capacitor wiring or the like is formed.
  • the notch 24 is formed in the scanning signal line GL so that the spacer 22 can be received.
  • a plasma CVD (chemical vapor deposition) method is applied to a silicon nitride film (SiNx) serving as a gate insulating film, a high resistance semiconductor layer made of amorphous silicon, polysilicon, or the like, and a low resistance semiconductor layer such as n + amorphous silicon.
  • the low resistance semiconductor layer, the high resistance semiconductor layer, and the gate insulating film are patterned by a photoetching method. At this time, the gate insulating film in the contact hole is also formed.
  • the silicon nitride film as the gate insulating film has a thickness of about 3000 to 5000 mm, for example, and the amorphous silicon film as the high resistance semiconductor layer has a film thickness of about 1000 to 3000 mm, for example, and n + as the low resistance semiconductor layer.
  • the amorphous silicon film has a thickness of about 400 to 700 mm, for example.
  • a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, copper, or an alloy film thereof, or a laminated film thereof is formed to a thickness of 1000 to 3000 mm by a method such as sputtering, and photo
  • a data signal line, a source electrode, a drain electrode, and the like are formed by patterning into a necessary shape by an etching method or the like.
  • a pattern such as a data signal line, a source electrode, and a drain electrode is masked for a high resistance semiconductor layer (i layer) such as an amorphous silicon film and a low resistance semiconductor layer (n + layer) such as an n + amorphous silicon film.
  • a high resistance semiconductor layer i layer
  • a low resistance semiconductor layer n + layer
  • channel etching is performed by dry etching.
  • the film thickness of the i layer is optimized, and each transistor (channel region) is formed.
  • the semiconductor layer not covered with the mask is removed by etching, leaving the i-layer thickness necessary for the capability of each transistor.
  • an inorganic insulating film such as silicon nitride or silicon oxide is formed as an interlayer insulating film so as to cover the data signal line, the source electrode, the drain electrode, and the like.
  • a silicon nitride film having a thickness of about 2000 to 5000 mm is formed by plasma CVD or the like.
  • the interlayer insulating film is formed so as to have a film thickness of 10,000 mm or less.
  • the interlayer insulating film is etched to form a hole.
  • the photosensitive resist is patterned by photolithography (exposure and development), and etching is performed.
  • a transparent conductive film such as ITO (indium tin oxide), IZO, zinc oxide, tin oxide or the like is formed on the interlayer insulating film with a film thickness of about 1000 to 2000 mm by a sputtering method or the like.
  • a pixel electrode is formed in each pixel region by patterning it into a necessary shape by a photoetching method or the like.
  • polyimide resin is printed on the entire substrate on the pixel electrode with a thickness of 500 to 1000 mm, and then baked and rubbed in one direction with a rotating cloth to form an alignment film.
  • the active matrix substrate 10 is manufactured as described above.
  • a chromium thin film or a resin containing a black pigment is formed on a transparent insulating substrate (glass substrate 21 in FIG. 3) such as glass or plastic, and then patterned by photolithography to form a black matrix. .
  • red, green, and blue color filter layers are formed in a pattern on the gap and upper surface of the black matrix by using a pigment dispersion method or the like.
  • a transparent conductive film made of ITO, IZO, zinc oxide, tin oxide or the like is formed on the entire substrate on the color filter layer to form a common electrode (com).
  • polyimide resin is printed on the entire substrate on the common electrode with a thickness of 500 to 1000 mm, and then baked and rubbed in one direction with a rotating cloth to form an alignment film.
  • the color filter substrate 20 can be manufactured as described above.
  • a seal material made of a thermosetting epoxy resin or the like is applied to one of the active matrix substrate 10 and the color filter substrate 20 in a frame-like pattern lacking a liquid crystal injection port portion by screen printing.
  • the active matrix substrate 10 and the color filter substrate 20 are bonded together, and the sealing material is cured. At this time, the active matrix substrate 10 and the color filter substrate 20 are pasted so that the spacer 22 of the color filter substrate 20 is received in the cutout portion 24 of the scanning signal line GL when the liquid crystal panel 2 is viewed in plan. Combined.
  • a UV curable resin is applied to the liquid crystal injection port, and the liquid crystal material is sealed by UV irradiation.
  • the liquid crystal layer 30 is formed.
  • the liquid crystal panel 2 is manufactured as described above.
  • the cutout portion 24 of the scanning signal line GL is provided, the distance between the scanning signal line GL and the storage capacitor line CSL and the width of the black matrix BM are set as shown in FIG.
  • the region in which the spacer 22 is disposed can be expanded without increasing the configuration as in the configuration of FIG.
  • the region in which the spacer 22 is arranged is the spacer arrangement region (distance between the scanning signal line GL and the storage capacitor line CSL) in the conventional configuration shown in FIG. Since the region can be equal to or greater than that, the cell gap can be reliably suppressed.
  • the present liquid crystal display device it is possible to suppress the variation in the cell gap between the pair of substrates without reducing the transmittance.
  • the notch 24 is formed only in a portion corresponding to one pixel (R pixel in FIGS. 2 and 3) of the three pixels (RGB).
  • the influence on the wiring failure can be suppressed to about 1/3.
  • the present liquid crystal display device 1 is not limited to the configuration in which the spacers 22 are provided in all the cutout portions 24 (see FIG. 2), and the spacers 22 may be provided alternately in all the cutout portions 24.
  • the cutout portions 24 may be provided only in the R pixels, and the spacers 22 may be provided every other pixel paying attention to the R pixels arranged in the matrix direction. .
  • the distance between the scanning signal line GL and the storage capacitor line CSL in the R pixel provided with the spacer 22 among the R pixels is equal to the scanning signal line GL and the storage capacitor in the G pixel and B pixel. It is larger than the distance to the wiring CSL.
  • the distance between the scanning signal line GL and the storage capacitor line CSL in the R pixel in which the spacer 22 is provided among the R pixels is equal to the scanning signal in the R pixel in which the spacer 22 is not provided in the R pixel. This is equal to the distance between the line GL and the storage capacitor line CSL.
  • the configuration of FIG. 5 can also be applied to the following modifications.
  • the spacers 22 do not have to be provided for all of one kind of pixels (for example, R pixels). That is, taking FIG. 5 as an example, the spacer 22 is partially between the scanning signal line GL and the storage capacitor line CSL in the region where the black matrix BM is formed when the liquid crystal panel 2 is viewed in plan.
  • the distance between the scanning signal line GL and the storage capacitor line CSL in the portion where the spacer 22 is provided (some R pixels) is equal to the portion where the spacer 22 is not provided (other R pixels).
  • a pixel, a G pixel, a B pixel of at least some of the scanning signal lines GL and the storage capacitor wiring CSL may be larger.
  • the notch 24 may be formed in the storage capacitor line CSL, or may be formed in both the scanning signal line GL and the storage capacitor line CSL.
  • FIG. 6 is a plan view showing Modification 1 of the liquid crystal panel 2
  • FIG. 7 is a plan view schematically showing the width of the black matrix BM.
  • the scanning signal line GL1 is not provided with the notch 24, and a bent portion 25 is formed in a part of the storage capacitor line CSL2.
  • the spacer 22 corresponds to the bent portion 25, and is provided in a region between the bent portion 25 and the scanning signal line GL1.
  • the spacer 22 is provided only for the R pixel among the three RGB pixels. Therefore, the bent portion 25 of the storage capacitor line CSL is also formed only in the portion corresponding to the R pixel.
  • the black matrix BM is formed at a common position in each pixel.
  • the transmittance equivalent to the transmittance in the conventional configuration shown in FIG. 22 can be obtained, so that the display quality does not deteriorate.
  • the region where the spacer 22 is disposed is set to be equal to or larger than the spacer disposition region (distance between the scanning signal line GL and the storage capacitor line CSL) in the conventional configuration shown in FIG. Therefore, the cell gap fluctuation can be reliably suppressed.
  • the present liquid crystal display device it is possible to suppress the variation in the cell gap between the pair of substrates without reducing the transmittance.
  • the spacer 22 is provided in the R pixel corresponding to the bent portion 25 of the storage capacitor wiring CSL2, and is not provided in the G pixel and the B pixel.
  • the black matrix BM is formed in the same manner as the pixel where the spacer 22 is not provided. That is, as shown in FIG. 7, in the R pixel provided with the spacer 22, the bent portion 25 of the storage capacitor wiring CSL overlaps the opening of the black matrix BM.
  • the storage capacitor wiring CSL overlapping the opening of the black matrix BM is only a portion corresponding to one pixel (R) of the three pixels (RGB), the influence on the transmittance, yield, and wiring impossibility is 1 / 3 or so. Therefore, the transmittance is not substantially lowered as compared with the conventional case.
  • FIG. 8 is a plan view showing Modification Example 2 of the liquid crystal panel 2. Compared with the liquid crystal panel 2 of FIG. 2, in the liquid crystal panel 2 of FIG. 2, a bent portion 25 is further formed in a part of the storage capacitor wiring CSL2.
  • the bent portion 25 corresponds to the cutout portion 24 of the scanning signal line GL1, and the spacer 22 is provided in a region between the cutout portion 24 of the scanning signal line GL1 and the bent portion 25 of the storage capacitor wiring CSL2. ing.
  • the spacer 22 is provided only for the R pixel among the three pixels of RGB. Therefore, the cutout portion 24 of the scanning signal line GL1 and the bent portion 25 of the storage capacitor line CSL are also formed only in the portion corresponding to the R pixel.
  • the black matrix BM is formed corresponding to the storage capacitor wiring CSL provided in the G pixel and the B pixel where the spacer 22 is not provided.
  • the distance between the scanning signal line GL and the storage capacitor line CSL can be made smaller than the configuration in FIG. 2 while making the region in which the spacer 22 is disposed the same as the configuration in FIG. Therefore, the transmittance can be increased.
  • the spacer 22 is provided in the R pixel corresponding to the bent portion 25 of the storage capacitor wiring CSL ⁇ b> 2. Since it is not provided in the B pixel, in the R pixel, the bent portion 25 of the storage capacitor wiring CSL overlaps the opening of the black matrix BM. However, since the storage capacitor wiring CSL that overlaps the opening of the black matrix BM is only a portion corresponding to one pixel (R) of the three pixels (RGB), it affects the transmittance, yield, and wiring impossibility. Can be suppressed to about 1/3. Therefore, the transmittance does not substantially decrease compared to the conventional case.
  • Modification 3 10 is a plan view showing a third modification of the liquid crystal panel 2
  • FIG. 11 is a cross-sectional view taken along the line AB of FIG.
  • a height adjusting unit 23 is further formed in the liquid crystal panel 2 of FIG. 2.
  • the height adjusting unit 23 is formed on the cutout portion 24 of the scanning signal line GL1 and an upper layer portion of a part of the storage capacitor line CSL2 facing the cutout portion 24.
  • the height adjusting unit 23 is formed on the interlayer insulating film 15 in the upper layer portion of the scanning signal line GL1 or the storage capacitor line CSL2.
  • the height adjusting unit 23 of the third modification can also be applied to the liquid crystal panel 2 of the first and second modifications.
  • FIG. 12 is a plan view showing Modification Example 4 of the liquid crystal panel 2.
  • the cutout portion 24 is not provided in the scanning signal line GL1, and the bent portion 25 is not provided in the storage capacitor line CSL2.
  • a height adjustment unit 23 is formed in part of the upper layer portion of the scanning signal line GL1 and the storage capacitor line CSL2.
  • the spacer 22 is provided in a region between the height adjustment unit 23 of the scanning signal line GL1 and the height adjustment unit 23 of the storage capacitor line CSL2.
  • the spacer 22 does not run on the upper layer part of the scanning signal line GL1 or the storage capacitor line CSL2, so that the cell gap can be reliably suppressed. Further, since the distance between the scanning signal line GL1 and the storage capacitor line CSL2 can be made the same as that of the conventional configuration shown in FIG. 22, the transmittance is not lowered.
  • the height adjusting unit 23 is formed on the interlayer insulating film 15 in the upper layer portion of the scanning signal line GL1 or the storage capacitor line CSL2.
  • the spacers 22 may be formed on the black matrix BM as shown in FIG.
  • the spacer 22 may be formed of a color filter layer CF as shown in FIGS.
  • the spacer 22 is not limited to the color filter layer CF, and may be formed of an existing layer formed on the color filter substrate 20 such as a liquid crystal alignment control layer, or a plurality of these existing layers may be used. It may be formed by overlapping.
  • the spacer 22 is formed on the red color filter layer CF (R) formed on the black matrix BM by a photolithography method using the green color filter layer CF (G) and the spacer 22.
  • the blue color filter layer CF (B) can be formed by patterning in order.
  • it can function as the spacer 22 by appropriately setting the film thickness of each color filter layer CF.
  • the liquid crystal panel 2 constituting the liquid crystal display device 1 according to the embodiment of the present invention is not limited to the configuration of FIG. 1, and a known configuration can be applied.
  • An example of another form of the liquid crystal panel 2 is as shown in FIG.
  • the liquid crystal display device 1 including the liquid crystal panel 2 illustrated in FIG. 16 includes two data signal lines (left data signal line and right data signal line) in one pixel column, and odd-numbered pixels included in the same pixel column. Are connected to the left data signal line, while the pixel electrodes of the even-numbered pixels are connected to the right data signal line, and two consecutive scanning signal lines (the scanning signal lines connected to the odd-numbered pixels and the even-numbered pixels) The scanning signal line connected to the second pixel) is selected at the same time. According to this configuration, since the data signal potential can be simultaneously written in two pixels adjacent in the column direction, the screen rewriting speed can be increased, and the charging time of each pixel can be increased. Play.
  • a bent portion 25 is provided on two adjacent data signal lines DL1b and DL2a (first signal line and second signal line).
  • the spacer 22 can be arranged in the region between the bent portions 25. Further, it is also possible to provide a notch in at least one of the two data signal lines DL1b and DL2a so that the spacer 22 is received in the notch.
  • the combination of two signal lines adjacent via the spacer 22 includes (i) a scanning signal line and a storage capacitor line, (ii) two adjacent scanning signal lines, and (iii) A combination of two adjacent storage capacitor lines and (iv) two adjacent data signal lines can be used.
  • the liquid crystal panel includes at least R, G, and B pixel types corresponding to R, G, and B colors
  • the holding member is provided in at least one of the one type of pixels among the R pixel, the G pixel, and the B pixel, Among the one type of pixels, the distance between the first signal line and the second signal line in the pixel provided with the holding member is different in the type of pixel different from the one type of pixel.
  • a configuration in which the distance is larger than the distance between the first signal line and the second signal line may be employed.
  • the distance between the first signal line and the second signal line in the pixel provided with the holding member among the one type of pixels is A configuration in which the distance between the first signal line and the second signal line in a pixel in which the holding member is not provided among the one kind of pixels may be used.
  • the interlayer insulating film constituting the first substrate may be an inorganic interlayer insulating film.
  • the liquid crystal display device in which the first substrate is configured (laminated) in a concavo-convex shape, variation in the cell gap between the pair of substrates can be suppressed.
  • the holding member may be formed on the color filter layer or the light shielding layer in the second substrate.
  • the holding member may be formed of a color filter layer or a liquid crystal alignment control layer.
  • the holding member is not limited to the color filter layer or the liquid crystal alignment control layer, and may be formed of another existing layer formed on the second substrate (color filter substrate), or the color filter layer or It may be formed in a multilayer structure including a liquid crystal alignment control layer.
  • the first signal line may be a scanning signal line
  • the second signal line may be a storage capacitor line
  • At least one of the first signal line and the second signal line is formed with a notch or a bent part for receiving the holding member. May be.
  • the holding member since the holding member is received in the cutout portion or the bent portion, the distance between the first signal line and the second signal line can be reduced. Thereby, since the width
  • a height adjusting portion may be provided in the upper layer portion of each of the first signal line and the second signal line in the portion where the holding member is provided.
  • the holding member does not run on the upper layer portion of the first signal line or the second signal line, so that the cell gap can be reliably suppressed.
  • the liquid crystal display device of the present invention can be suitably used for various applications such as a liquid crystal television.

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Abstract

A spacer (22) maintains a gap between an active matrix substrate (10) and a color filter substrate (20); viewing a liquid crystal panel (2) in planar view, the color filter substrate (20) is arranged between a scanning signal line (GL1) and a holding capacity line (CSL2) in the formation region of a black matrix (BM). The distance between the scanning signal line (GL1) and the holding capacity line (CSL2) in the portion where the spacer (22) is arranged is greater than that in the portion where the spacer (22) is not arranged.

Description

液晶表示装置Liquid crystal display
　本発明は、液晶表示装置に関し、特に、一対の基板の間隙を保持する保持部材（スペーサ）に関するものである。 The present invention relates to a liquid crystal display device, and more particularly to a holding member (spacer) that holds a gap between a pair of substrates.
　液晶表示装置は、一対の基板と、両基板間に配される液晶層とを備えて構成されている。以下、従来の液晶表示装置の一例を挙げる。 The liquid crystal display device includes a pair of substrates and a liquid crystal layer disposed between the substrates. An example of a conventional liquid crystal display device will be given below.
　図１９は薄膜トランジスタ（ＴＦＴ）をスィッチング素子として用いたＴＮ型の液晶表示装置の概略構成を示す断面図である。図中、ＳＵＢ１は下側基板、ＳＵＢ２は上側基板であり、それぞれの基板の内面には、信号線、電極、絶縁層、その他の機能膜からなる多層構造膜が形成されている。下側基板ＳＵＢ１の内面には、ＴＦＴを有し、上側基板ＳＵＢ２の内面には共通電極ＣＯＭや３色（赤、緑、青）のカラーフィルタ層ＦＩＬ（ＦＩＬ（Ｒ）、ＦＩＬ（Ｇ）、ＦＩＬ（Ｂ）；ＦＩＬ（Ｂ）は図示されていない）が形成されている。 FIG. 19 is a cross-sectional view showing a schematic configuration of a TN liquid crystal display device using a thin film transistor (TFT) as a switching element. In the figure, SUB1 is a lower substrate, and SUB2 is an upper substrate, and a multilayer structure film including a signal line, an electrode, an insulating layer, and other functional films is formed on the inner surface of each substrate. The inner surface of the lower substrate SUB1 has a TFT, and the inner surface of the upper substrate SUB2 has a common electrode COM and three color (red, green, blue) color filter layers FIL (FIL (R), FIL (G), FIL (B); FIL (B) is not shown).
　ＴＦＴは、図示しない走査信号線に接続するゲート電極ＧＴ、半導体層ＡＳ、ソース電極ＳＤ１、ドレイン電極ＳＤ２を有している。ソース電極ＳＤ１は画素電極ＩＴＯ１に接続されている。その他、ゲート絶縁層ＧＩやパッシベーション層ＰＳＶ１などが設けられ、ＴＦＴを含めた全面には配向膜ＯＲＩ１が塗布されて多層構造膜となっている。図中、参照符号ｄ０、ｄ１、ｄ２、ｄ３は各層を構成する金属膜である。 The TFT has a gate electrode GT, a semiconductor layer AS, a source electrode SD1, and a drain electrode SD2 connected to a scanning signal line (not shown). The source electrode SD1 is connected to the pixel electrode ITO1. In addition, a gate insulating layer GI, a passivation layer PSV1, and the like are provided, and an alignment film ORI1 is applied to the entire surface including the TFT to form a multilayer structure film. In the figure, reference numerals d0, d1, d2, and d3 are metal films constituting each layer.
　また、上側基板ＳＵＢ２の内面には、遮光層であるブラックマトリクスＢＭで区画された３色のカラーフィルタ層ＦＩＬ（ＦＩＬ（Ｒ）、ＦＩＬ（Ｇ）、ＦＩＬ（Ｂ））、パッシベーション層ＰＳＶ２、ＩＴＯ２で示した共通電極ＣＯＭ、配向膜ＯＲＩ２による多層構造膜が形成されている。図示したように、下側基板ＳＵＢ１および上側基板ＳＵＢ２に形成される多層構造膜の表面には、凹凸が形成されている。これら一対の基板の間に液晶ＬＣが封入されて液晶表示装置が構成される。 Further, on the inner surface of the upper substrate SUB2, three color filter layers FIL (FIL (R), FIL (G), FIL (B)) partitioned by a black matrix BM that is a light shielding layer, a passivation layer PSV2, and ITO2 Is formed by the common electrode COM and the alignment film ORI2. As illustrated, irregularities are formed on the surfaces of the multilayer structure films formed on the lower substrate SUB1 and the upper substrate SUB2. A liquid crystal LC is sealed between the pair of substrates to constitute a liquid crystal display device.
　そして、画素電極ＩＴＯ１と共通電極ＩＴＯ２との間に電界をかけることにより、電極間にある液晶ＬＣの配向方向を変化させ、下側基板ＳＵＢ１の外表面に貼付された偏光板ＰＯＬ１を通して入射した光の偏光軸を変調させ、上側基板ＳＵＢ２の外表面に貼付した偏光板ＰＯＬ２から出射する光で画像を表示する。このとき、液晶層ＬＣの層厚であるセルギャップが変動すると所定の表示特性が得られなくなるため、上記一対の基板の貼り合わせ間隙（所謂、セルギャップ）には、スペーサと称する間隙規制部材（保持部材）を設けられている。 Then, by applying an electric field between the pixel electrode ITO1 and the common electrode ITO2, the orientation direction of the liquid crystal LC between the electrodes is changed, and the light incident through the polarizing plate POL1 attached to the outer surface of the lower substrate SUB1 The polarization axis is modulated, and an image is displayed with light emitted from the polarizing plate POL2 attached to the outer surface of the upper substrate SUB2. At this time, if the cell gap, which is the layer thickness of the liquid crystal layer LC, fluctuates, a predetermined display characteristic cannot be obtained. Holding member).
　図２０は、従来の液晶表示装置におけるスペーサの設置位置の一例を示す平面図である。図２０は上側基板から下側基板を見た（平面的に見た）状態を示し、上側基板の多層構造膜はブラックマトリクスＢＭの開口部を外形で示している。下側基板ＳＵＢ１の内面には、走査信号線ＧＬ、データ信号線ＤＬ、ＴＦＴ、画素電極ＩＴＯ１が形成されている。スペーサＳＯＣは、表示品位に影響を及ぼさないように、画素領域外の部分である走査信号線ＧＬあるいはデータ信号線ＤＬの上に位置するように、上側基板ＳＵＢ２の内面に固定的に設けられている。 FIG. 20 is a plan view showing an example of a spacer installation position in a conventional liquid crystal display device. FIG. 20 shows a state in which the lower substrate is viewed from the upper substrate (viewed in a plan view), and the multilayer structure film of the upper substrate shows the opening of the black matrix BM in outline. Scan signal lines GL, data signal lines DL, TFTs, and pixel electrodes ITO1 are formed on the inner surface of the lower substrate SUB1. The spacer SOC is fixedly provided on the inner surface of the upper substrate SUB2 so as to be positioned on the scanning signal line GL or the data signal line DL which is a portion outside the pixel region so as not to affect the display quality. Yes.
日本国公開特許公報「特開２００３－５１９０号公報（２００３年１月８日公開）」Japanese Patent Publication “Japanese Laid-Open Patent Publication No. 2003-5190 (released on January 8, 2003)”
　ここで、スペーサＳＯＣは、下側基板ＳＵＢ１の多層構造膜の盛り上がり部分である凸部に設けられている。そのため、このようなスペーサの配置では、一対の基板を貼り合わせた後（図２１の（ａ））に、基板に外力（図２１の（ｂ）の矢印Ｆ１、Ｆ２）が加わった場合、スペーサＳＯＣが、下側基板の多層構造膜ＬＹの凸部ＬＹＴから凹部ＬＹＢに滑り落ちるおそれがある（図２１の（ｂ））。これにより、上下基板間の位置関係がずれて、設定したセルギャップが変動し、表示品位が低下するという問題が生じる。 Here, the spacer SOC is provided on a convex portion which is a raised portion of the multilayer structure film of the lower substrate SUB1. Therefore, in such a spacer arrangement, when an external force (arrows F1 and F2 in FIG. 21B) is applied to the substrate after the pair of substrates are bonded together (FIG. 21A), the spacer There is a possibility that the SOC slides down from the convex portion LYT of the multilayer structure film LY of the lower substrate to the concave portion LYB ((b) of FIG. 21). As a result, the positional relationship between the upper and lower substrates shifts, the set cell gap fluctuates, and the display quality deteriorates.
　この問題を解決する方法として、図２２に示すように、スペーサＳＯＣを、予め信号線Ｌ間の凹部ＬＹＢに設ける方法（特許文献１）が提案されているが、この方法では、上記外力が加わると凸部ＬＹＴに乗り上げることが考えられ、セルギャップの変動を完全に抑えることは困難である。 As a method for solving this problem, as shown in FIG. 22, a method (Patent Document 1) in which a spacer SOC is provided in advance in the recess LYB between the signal lines L has been proposed. In this method, the external force is applied. Therefore, it is difficult to completely suppress the fluctuation of the cell gap.
　また、他の方法として、スペーサＳＯＣを設ける凹部ＬＹＢの幅を大きくすることも考えられる（図４の（ａ）参照）。しかし、この方法では、凹部ＬＹＢの幅（信号線Ｌ間の距離）すなわち画素領域外の部分が大きくなるため、これに伴ってブラックマトリクスＢＭの幅も太くしなければならない。そのため、透過率が低下し、表示品位の低下を招くことになる。このように、セルギャップの変動抑制と透過率の低下防止はトレードオフの関係にある。 As another method, it is conceivable to increase the width of the recess LYB in which the spacer SOC is provided (see FIG. 4A). However, in this method, since the width of the recess LYB (distance between the signal lines L), that is, the portion outside the pixel region is increased, the width of the black matrix BM must be increased accordingly. For this reason, the transmittance is lowered, and the display quality is lowered. As described above, suppression of cell gap fluctuation and prevention of reduction in transmittance are in a trade-off relationship.
　そこで、本発明では、透過率を低下させることなく、一対の基板間のセルギャップの変動を抑えることができる液晶表示装置を提案する。 Therefore, the present invention proposes a liquid crystal display device capable of suppressing the fluctuation of the cell gap between a pair of substrates without reducing the transmittance.
　本発明に係る液晶表示装置は、上記の課題を解決するために、
　互いに隣り合って並行するように配される第１信号線および第２信号線を含む第１基板と、該第１基板に対向配置され、遮光層が設けられた第２基板と、該第１基板および該第２基板の間に配された液晶層とを含む液晶パネルを備え、
　上記第１基板および上記第２基板の間には、両基板の間隙を保持する保持部材が設けられており、
　上記保持部材は、上記液晶パネルを平面的に見て、上記遮光層が形成されている領域において、上記第１信号線と上記第２信号線との間に部分的に設けられており、
　上記保持部材が設けられている部分における上記第１信号線と上記第２信号線との間の距離が、上記保持部材が設けられていない部分のうちの少なくとも一部における上記第１信号線と上記第２信号線との間の距離よりも大きいことを特徴とする。 In order to solve the above problems, the liquid crystal display device according to the present invention provides
A first substrate including a first signal line and a second signal line arranged adjacent to each other in parallel; a second substrate disposed opposite to the first substrate and provided with a light shielding layer; and the first substrate A liquid crystal panel including a substrate and a liquid crystal layer disposed between the second substrate,
A holding member is provided between the first substrate and the second substrate to hold a gap between the two substrates.
The holding member is partially provided between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan view,
The distance between the first signal line and the second signal line in the portion where the holding member is provided is equal to the first signal line in at least a part of the portion where the holding member is not provided. It is larger than the distance between the second signal lines.
　上記の構成では、保持部材が設けられている部分（保持部材を介して第１信号線と第２信号線とが対向する領域）では、保持部材が設けられていない部分のうちの少なくとも一部よりも両信号線間の距離が大きい。具体的には例えば、第１信号線に切り欠き部を設ける構成とすることができる。この構成によれば、第１信号線と第２信号線との間の距離および遮光層の幅を、従来の図２２の構成から図４の（ａ）の構成のように広げることなく、保持部材を配置する領域のみを広げることができる。なお、保持部材は、全ての切り欠き部に設けられている必要はなく、少なくとも一部の切り欠き部に設けられていればよい。 In the above configuration, in a portion where the holding member is provided (a region where the first signal line and the second signal line face each other through the holding member), at least a part of the portion where the holding member is not provided The distance between both signal lines is larger than that. Specifically, for example, the first signal line can be provided with a notch. According to this configuration, the distance between the first signal line and the second signal line and the width of the light shielding layer are maintained without increasing from the conventional configuration of FIG. 22 as in the configuration of FIG. 4A. Only the region where the member is arranged can be expanded. Note that the holding member does not have to be provided in all the notches, and may be provided in at least some of the notches.
　すなわち、上記の構成によれば、図２２に示す従来の構成と比較して、第１信号線と第２信号線との間の距離および遮光層の幅を広げる必要がないため、図２２に示す従来の構成における透過率と同等の透過率を得ることができる。そのため、表示品位が低下することはない。また、上記の構成によれば、保持部材を配置する領域を、図４の（ａ）に示す従来の構成における保持部材の配置領域と同等以上の領域とすることができるため、セルギャップの変動を確実に抑えることができる。 That is, according to the above configuration, it is not necessary to increase the distance between the first signal line and the second signal line and the width of the light shielding layer as compared with the conventional configuration shown in FIG. A transmittance equivalent to the transmittance in the conventional configuration shown can be obtained. For this reason, the display quality does not deteriorate. In addition, according to the above configuration, the region in which the holding member is disposed can be equal to or greater than the region in which the holding member is disposed in the conventional configuration illustrated in FIG. Can be reliably suppressed.
　よって、本液晶表示装置によれば、透過率を低下させることなく、一対の基板間のセルギャップの変動を抑えることができる。 Therefore, according to the present liquid crystal display device, it is possible to suppress the variation in the cell gap between the pair of substrates without reducing the transmittance.
　本発明に係る液晶表示装置は、上記の課題を解決するために、
　互いに隣り合って並行するように配される第１信号線および第２信号線を含む第１基板と、該第１基板に対向配置され、遮光層が設けられた第２基板と、該第１基板および該第２基板の間に配された液晶層とを含む液晶パネルを備え、
　上記第１基板および上記第２基板の間には、両基板の間隙を保持する保持部材が設けられており、
　上記保持部材は、上記液晶パネルを平面的に見て、上記遮光層が形成されている領域において、上記第１信号線と上記第２信号線との間に部分的に設けられており、
　上記保持部材が設けられている部分における上記第１信号線および上記第２信号線のそれぞれの上層部には、高さ調整部が設けられていることを特徴とする。 In order to solve the above problems, the liquid crystal display device according to the present invention provides
A first substrate including a first signal line and a second signal line arranged adjacent to each other in parallel; a second substrate disposed opposite to the first substrate and provided with a light shielding layer; and the first substrate A liquid crystal panel including a substrate and a liquid crystal layer disposed between the second substrate,
A holding member is provided between the first substrate and the second substrate to hold a gap between the two substrates.
The holding member is partially provided between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan view,
A height adjusting portion is provided in an upper layer portion of each of the first signal line and the second signal line in a portion where the holding member is provided.
　これにより、上述した液晶表示装置と同様の効果を得ることができる。 Thereby, the same effect as the above-described liquid crystal display device can be obtained.
　以上のように、本発明に係る液晶表示装置では、上記保持部材は、上記液晶パネルを平面的に見て、上記遮光層が形成されている領域において、上記第１信号線と上記第２信号線との間に部分的に設けられており、上記保持部材が設けられている部分における上記第１信号線と上記第２信号線との間の距離が、上記保持部材が設けられていない部分のうちの少なくとも一部における上記第１信号線と上記第２信号線との間の距離よりも大きい構成である。 As described above, in the liquid crystal display device according to the present invention, the holding member has the first signal line and the second signal in the region where the light shielding layer is formed when the liquid crystal panel is viewed in plan. The part where the holding member is not provided is the distance between the first signal line and the second signal line in the part where the holding member is provided. Is configured to be larger than the distance between the first signal line and the second signal line in at least a part thereof.
　また、本発明に係る液晶表示装置では、上記保持部材は、上記液晶パネルを平面的に見て、上記遮光層が形成されている領域において、上記第１信号線と上記第２信号線との間に部分的に設けられており、上記保持部材が設けられている部分における上記第１信号線および上記第２信号線のそれぞれの上層部には、高さ調整部が設けられている構成である。 Further, in the liquid crystal display device according to the present invention, the holding member is formed between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan. A height adjustment portion is provided in each upper layer portion of the first signal line and the second signal line in the portion where the holding member is provided. is there.
　これにより、透過率を低下させることなく、一対の基板間のセルギャップの変動を抑えることができる。 Thereby, the fluctuation of the cell gap between the pair of substrates can be suppressed without reducing the transmittance.
本実施の形態に係る液晶表示装置を構成する液晶パネルの一部を示す等価回路図である。It is an equivalent circuit diagram which shows a part of liquid crystal panel which comprises the liquid crystal display device which concerns on this Embodiment. 図１の液晶パネルの具体例を示す平面図である。It is a top view which shows the specific example of the liquid crystal panel of FIG. 図２のＡ－Ｂ断面図である。FIG. 3 is a cross-sectional view taken along the line AB of FIG. ブラックマトリクスとスペーサの関係を説明するための平面図であり、（ａ）は従来の構成を示し、（ｂ）は本実施の形態を示す。It is a top view for demonstrating the relationship between a black matrix and a spacer, (a) shows the conventional structure, (b) shows this Embodiment. 本実施の形態に係る液晶表示装置におけるスペーサの配置例を示す平面図である。It is a top view which shows the example of arrangement | positioning of the spacer in the liquid crystal display device which concerns on this Embodiment. 図２の液晶パネルの変形例１を示す平面図である。It is a top view which shows the modification 1 of the liquid crystal panel of FIG. 図６におけるブラックマトリクスとスペーサの関係を説明するための模式図である。It is a schematic diagram for demonstrating the relationship between the black matrix in FIG. 6, and a spacer. 図２の液晶パネルの変形例２を示す平面図である。It is a top view which shows the modification 2 of the liquid crystal panel of FIG. 図８におけるブラックマトリクスとスペーサの関係を説明するための模式図である。It is a schematic diagram for demonstrating the relationship between the black matrix in FIG. 8, and a spacer. 図２の液晶パネルの変形例３を示す平面図である。It is a top view which shows the modification 3 of the liquid crystal panel of FIG. 図１０のＡ－Ｂ断面図である。FIG. 11 is a cross-sectional view taken along the line AB of FIG. 図２の液晶パネルの変形例４を示す平面図である。It is a top view which shows the modification 4 of the liquid crystal panel of FIG. 本実施の形態に係るスペーサの変形例を示す断面図である。It is sectional drawing which shows the modification of the spacer which concerns on this Embodiment. 本実施の形態に係るスペーサの変形例を示す断面図である。It is sectional drawing which shows the modification of the spacer which concerns on this Embodiment. 本実施の形態に係るスペーサの変形例を示す断面図である。It is sectional drawing which shows the modification of the spacer which concerns on this Embodiment. 図１の液晶表示装置を構成する液晶パネルの変形例６を示す等価回路図である。FIG. 10 is an equivalent circuit diagram showing a sixth modification of the liquid crystal panel constituting the liquid crystal display device of FIG. 1. 図１６の液晶パネルの具体例を示す平面図である。It is a top view which shows the specific example of the liquid crystal panel of FIG. 図１７のＡ－Ｂ断面図である。FIG. 18 is a cross-sectional view taken along the line AB of FIG. 従来の液晶表示装置の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the conventional liquid crystal display device. 従来の液晶表示装置におけるスペーサの設置位置の一例を示す平面図である。It is a top view which shows an example of the installation position of the spacer in the conventional liquid crystal display device. 従来のスペーサの形成位置に起因する基板ずれ現象を模式的に示す断面図であり、（ａ）は外力が加わる前のスペーサの配置を示し、（ｂ）は外力が加わったときのスペーサの位置変動を示す。It is sectional drawing which shows typically the board | substrate deviation phenomenon resulting from the formation position of the conventional spacer, (a) shows arrangement | positioning of the spacer before external force is added, (b) is the position of the spacer when external force is applied. Showing fluctuations. 従来の液晶表示装置におけるスペーサの設置位置の他の例を示す断面図である。It is sectional drawing which shows the other example of the installation position of the spacer in the conventional liquid crystal display device.
　本発明に係る一実施の形態について図面を用いて説明すると以下のとおりである。なお、説明の便宜のため、以下では走査信号線の延伸方向を行方向とする。ただし、本液晶表示装置（あるいはこれに用いられる液晶パネルやアクティブマトリクス基板）の利用（視聴）状態において、その走査信号線が横方向に延伸していても縦方向に延伸していてもよいことはいうまでもない。 An embodiment according to the present invention will be described below with reference to the drawings. For convenience of explanation, the extending direction of the scanning signal lines is hereinafter referred to as the row direction. However, in the use (viewing) state of the present liquid crystal display device (or the liquid crystal panel or active matrix substrate used therein), the scanning signal line may extend in the horizontal direction or in the vertical direction. Needless to say.
　図１は、本実施の形態に係る液晶表示装置１を構成する液晶パネル２の一部を示す等価回路図である。図１に示すように、液晶パネル２は、列方向（図中上下方向）に延伸するデータ信号線ＤＬ１、ＤＬ２、行方向（図中左右方向）に延伸する走査信号線ＧＬ１、ＧＬ２、保持容量配線ＣＳＬ１、ＣＳＬ２、行および列方向に並べられた画素１０１～１０４、および共通電極（対向電極）ｃｏｍを備えている。各画素の構造は同一の構成である。なお、画素１０１、１０２が含まれる画素列と、画素１０３、１０４が含まれる画素列とが隣接している。 FIG. 1 is an equivalent circuit diagram showing a part of a liquid crystal panel 2 constituting the liquid crystal display device 1 according to the present embodiment. As shown in FIG. 1, the liquid crystal panel 2 includes data signal lines DL1 and DL2 extending in the column direction (up and down direction in the drawing), scanning signal lines GL1 and GL2 extending in the row direction (left and right direction in the drawing), and a storage capacitor. Wiring CSL1, CSL2, pixels 101 to 104 arranged in the row and column directions, and a common electrode (counter electrode) com are provided. Each pixel has the same structure. Note that a pixel column including the pixels 101 and 102 and a pixel column including the pixels 103 and 104 are adjacent to each other.
　液晶パネル２では、１つの画素に対応して、データ信号線ＤＬと走査信号線ＧＬと保持容量配線ＣＳＬとが１本ずつ設けられている。また、画素１０１には画素電極１６ａが設けられ、画素１０２には画素電極１６ｂが設けられ、画素１０３には画素電極１６ｃが設けられ、画素１０４には画素電極１６ｄが１つずつ設けられている。なお、画素電極は、１つの画素に２つ以上設けられていても良い。 In the liquid crystal panel 2, one data signal line DL, one scanning signal line GL, and one storage capacitor line CSL are provided corresponding to one pixel. The pixel 101 is provided with a pixel electrode 16a, the pixel 102 is provided with a pixel electrode 16b, the pixel 103 is provided with a pixel electrode 16c, and the pixel 104 is provided with one pixel electrode 16d. . Note that two or more pixel electrodes may be provided in one pixel.
　画素１０１では、画素電極１６ａが、走査信号線ＧＬ１に接続されたトランジスタＴＦＴ１を介してデータ信号線ＤＬ１に接続され、画素電極１６ａおよび保持容量配線ＣＳＬ１間に保持容量Ｃｈａが形成され、画素電極１６ａおよび共通電極ｃｏｍ間に液晶容量Ｃｌａが形成されている。画素１０２では、画素電極１６ｂが、走査信号線ＧＬ２に接続されたトランジスタＴＦＴ２を介してデータ信号線ＤＬ１に接続され、画素電極１６ｂおよび保持容量配線ＣＳＬ２間に保持容量Ｃｈｂが形成され、画素電極１６ｂおよび共通電極ｃｏｍ間に液晶容量Ｃｌｂが形成されている。 In the pixel 101, the pixel electrode 16a is connected to the data signal line DL1 via the transistor TFT1 connected to the scanning signal line GL1, and a storage capacitor Cha is formed between the pixel electrode 16a and the storage capacitor line CSL1, and the pixel electrode 16a. A liquid crystal capacitor Cla is formed between the common electrodes com. In the pixel 102, the pixel electrode 16b is connected to the data signal line DL1 via the transistor TFT2 connected to the scanning signal line GL2, and a storage capacitor Chb is formed between the pixel electrode 16b and the storage capacitor line CSL2, and the pixel electrode 16b. A liquid crystal capacitance Clb is formed between the common electrodes com.
　同様に、画素１０３では、画素電極１６ｃが、走査信号線ＧＬ１に接続されたトランジスタＴＦＴ３を介してデータ信号線ＤＬ２に接続され、画素電極１６ｃおよび保持容量配線ＣＳＬ１間に保持容量Ｃｈｃが形成され、画素電極１６ｃおよび共通電極ｃｏｍ間に液晶容量Ｃｌｃが形成されている。画素１０４では、画素電極１６ｄが、走査信号線ＧＬ２に接続されたトランジスタＴＦＴ４を介してデータ信号線ＤＬ２に接続され、画素電極１６ｄおよび保持容量配線ＣＳＬ２間に保持容量Ｃｈｄが形成され、画素電極１６ｄおよび共通電極ｃｏｍ間に液晶容量Ｃｌｄが形成されている。 Similarly, in the pixel 103, the pixel electrode 16c is connected to the data signal line DL2 via the transistor TFT3 connected to the scanning signal line GL1, and a storage capacitor Chc is formed between the pixel electrode 16c and the storage capacitor line CSL1, A liquid crystal capacitance Clc is formed between the pixel electrode 16c and the common electrode com. In the pixel 104, the pixel electrode 16d is connected to the data signal line DL2 through the transistor TFT4 connected to the scanning signal line GL2, and a storage capacitor Chd is formed between the pixel electrode 16d and the storage capacitor line CSL2, and the pixel electrode 16d. A liquid crystal capacitor Cld is formed between the common electrodes com.
　次に、液晶パネル２の具体例を図２に示す。図２の液晶パネル２では、画素１０１および画素１０２に沿うようにデータ信号線ＤＬ１が設けられ、画素１０３および画素１０４に沿うようにデータ信号線ＤＬ２が設けられ、保持容量配線ＣＳＬ１が画素１０１、１０３それぞれを横切り、保持容量配線ＣＳＬ２が画素１０２、１０４それぞれを横切っている。 Next, a specific example of the liquid crystal panel 2 is shown in FIG. In the liquid crystal panel 2 of FIG. 2, the data signal line DL1 is provided along the pixel 101 and the pixel 102, the data signal line DL2 is provided along the pixel 103 and the pixel 104, and the storage capacitor line CSL1 is connected to the pixel 101, 103, and the storage capacitor line CSL2 crosses the pixels 102 and 104, respectively.
　走査信号線ＧＬ１は画素１０１の一方の端部側に配され、保持容量配線ＣＳＬ１は他方の端部側に配され、平面的に見て、走査信号線ＧＬ１および保持容量配線ＣＳＬ１間に画素電極１６ａが配されている。同様に、走査信号線ＧＬ１は画素１０３の一方の端部側に配され、保持容量配線ＣＳＬ１は他方の端部側に配され、平面的に見て、走査信号線ＧＬ１および保持容量配線ＣＳＬ１間に画素電極１６ｃが配されている。なお、保持容量配線ＣＳＬ１は、図２に示すように、平面的に見て、画素電極１６ａ、１６ｃに重なっていても良い。なお、走査信号線ＧＬ１には、画素１０１の領域において、部分的に切り欠き部２４が設けられている。 The scanning signal line GL1 is disposed on one end side of the pixel 101, and the storage capacitor line CSL1 is disposed on the other end side, and the pixel electrode is disposed between the scanning signal line GL1 and the storage capacitor line CSL1 in plan view. 16a is arranged. Similarly, the scanning signal line GL1 is disposed on one end side of the pixel 103, and the storage capacitor line CSL1 is disposed on the other end side, and when viewed in plan, between the scanning signal line GL1 and the storage capacitor line CSL1. The pixel electrode 16c is arranged on the front side. As shown in FIG. 2, the storage capacitor line CSL1 may overlap the pixel electrodes 16a and 16c in plan view. The scanning signal line GL1 is partially provided with a notch 24 in the region of the pixel 101.
　また、走査信号線ＧＬ２は画素１０２の一方の端部側に配され、保持容量配線ＣＳＬ２は他方の端部側に配され、平面的に見て、走査信号線ＧＬ２および保持容量配線ＣＳＬ２間に画素電極１６ｂが配されている。同様に、走査信号線ＧＬ２は画素１０４の一方の端部側に配され、保持容量配線ＣＳＬ２は他方の端部側に配され、平面的に見て、走査信号線ＧＬ２および保持容量配線ＣＳＬ２間に画素電極１６ｄが配されている。なお、保持容量配線ＣＳＬ２は、図２に示すように、平面的に見て、画素電極１６ｂ、１６ｄに重なっていても良い。なお、走査信号線ＧＬ２には、画素１０２の領域において、部分的に切り欠き部２４が設けられている。 In addition, the scanning signal line GL2 is disposed on one end side of the pixel 102, and the storage capacitor line CSL2 is disposed on the other end side, and when viewed in plan, between the scanning signal line GL2 and the storage capacitor line CSL2. A pixel electrode 16b is disposed. Similarly, the scanning signal line GL2 is disposed on one end side of the pixel 104, and the storage capacitor line CSL2 is disposed on the other end side, and when viewed in plan, between the scanning signal line GL2 and the storage capacitor line CSL2. The pixel electrode 16d is disposed on the front side. As shown in FIG. 2, the storage capacitor line CSL2 may overlap the pixel electrodes 16b and 16d in a plan view. The scanning signal line GL2 is partially provided with a notch 24 in the region of the pixel 102.
　また、図２にはブラックマトリクスＢＭ（遮光層）の形成領域を示している。便宜上、液晶パネル２を平面的に見て透過した状態で示しているが、ＢＭで示す矩形の内側は、ブラックマトリクスの開口領域（透過領域）であり、その外側が遮光領域である。 Further, FIG. 2 shows a formation region of the black matrix BM (light shielding layer). For convenience, the liquid crystal panel 2 is shown in a transparent state as seen in a plan view, but the inside of the rectangle indicated by BM is an opening area (transmission area) of the black matrix, and the outside is a light shielding area.
　画素１０１の例に挙げると、走査信号線ＧＬ１上に、トランジスタＴＦＴ１のソース電極ｓａおよびドレイン電極ｄａが形成されている。ソース電極ｓａはデータ信号線ＤＬ１に接続され、ドレイン電極ｄａはドレイン引き出し配線（図示せず）に接続され、ドレイン引き出し配線はコンタクトホールｃａを介して画素電極１６ａに接続されている。保持容量配線ＣＳＬ１は容量電極１２ａに接続され、容量電極１２ａはゲート絶縁膜および層間絶縁膜を介して画素電極１６ａと重なっており、これにより保持容量Ｃｈａ（図１参照）が形成されている。 As an example of the pixel 101, the source electrode sa and the drain electrode da of the transistor TFT1 are formed on the scanning signal line GL1. The source electrode sa is connected to the data signal line DL1, the drain electrode da is connected to a drain lead wiring (not shown), and the drain lead wiring is connected to the pixel electrode 16a via a contact hole ca. The storage capacitor line CSL1 is connected to the capacitor electrode 12a, and the capacitor electrode 12a overlaps the pixel electrode 16a through the gate insulating film and the interlayer insulating film, thereby forming a storage capacitor Cha (see FIG. 1).
　図３は図２のＡ－Ｂ断面図である。同図に示すように、液晶パネル２は、アクティブマトリクス基板１０（第１基板）と、これに対向するカラーフィルタ基板２０（第２基板）と、両基板１０、２０間に配される液晶層３０とを備えている。また、液晶パネル２は、両基板１０、２０の間隙（セルギャップ）を保持（規制）するためのスペーサ２２（保持部材）を備えている。 FIG. 3 is a cross-sectional view taken along the line AB of FIG. As shown in the figure, the liquid crystal panel 2 includes an active matrix substrate 10 (first substrate), a color filter substrate 20 (second substrate) opposed thereto, and a liquid crystal layer disposed between the substrates 10 and 20. 30. The liquid crystal panel 2 includes a spacer 22 (holding member) for holding (regulating) the gap (cell gap) between the substrates 10 and 20.
　アクティブマトリクス基板１０では、ガラス基板１１上に走査信号線ＧＬ１および容量電極１２ａ、１２ｂ、１２ｃが形成され、容量電極１２ｂ上に保持容量配線ＣＳＬ２が形成され、これらを覆うように無機ゲート絶縁膜１３（以下、ゲート絶縁膜１３と称す）が形成されている。ゲート絶縁膜１３上には、データ信号線ＤＬ２、半導体層１４、ソース電極ｓａおよびドレイン電極ｄａ（図２参照）が形成され、これらを覆うように無機層間絶縁膜１５（以下、層間絶縁膜１５と称す）が形成されている。層間絶縁膜１５上には画素電極１６ａ、１６ｂ、１６ｃが形成され、さらに、これら画素電極１６ａ、１６ｂ、１６ｃを覆うように配向膜（図示せず）が形成されている。なお、スペーサ２２は、走査信号線ＧＬ１の切り欠き部２４（図２参照）に受容されるように設けられている。 In the active matrix substrate 10, the scanning signal line GL1 and the capacitor electrodes 12a, 12b, and 12c are formed on the glass substrate 11, the storage capacitor line CSL2 is formed on the capacitor electrode 12b, and the inorganic gate insulating film 13 is formed so as to cover them. (Hereinafter referred to as the gate insulating film 13) is formed. A data signal line DL2, a semiconductor layer 14, a source electrode sa and a drain electrode da (see FIG. 2) are formed on the gate insulating film 13, and an inorganic interlayer insulating film 15 (hereinafter referred to as an interlayer insulating film 15) is formed so as to cover them. Is formed). Pixel electrodes 16a, 16b, and 16c are formed on the interlayer insulating film 15, and an alignment film (not shown) is formed so as to cover the pixel electrodes 16a, 16b, and 16c. The spacer 22 is provided so as to be received in the notch 24 (see FIG. 2) of the scanning signal line GL1.
　ここで、コンタクトホールｃａ（図２参照）では、層間絶縁膜１５が刳り貫かれており、これにより、画素電極１６ａとドレイン電極ｄａとが接続される。また、容量電極１２ａがゲート絶縁膜１３および層間絶縁膜１５を介して容量電極１６ａと重なっており、これにより、保持容量Ｃｈａ（図１参照）が形成され、容量電極１２ｂがゲート絶縁膜１３および層間絶縁膜１５を介して容量電極１６ｂと重なっており、これにより、保持容量Ｃｈｂ（図１参照）が形成されている。 Here, in the contact hole ca (see FIG. 2), the interlayer insulating film 15 is penetrated, whereby the pixel electrode 16a and the drain electrode da are connected. Further, the capacitor electrode 12a overlaps the capacitor electrode 16a with the gate insulating film 13 and the interlayer insulating film 15 interposed therebetween, whereby a storage capacitor Cha (see FIG. 1) is formed, and the capacitor electrode 12b is connected to the gate insulating film 13 and The capacitor electrode 16b overlaps with the interlayer insulating film 15 interposed therebetween, whereby a storage capacitor Chb (see FIG. 1) is formed.
　一方、カラーフィルタ基板２０では、ガラス基板２１上にブラックマトリクスＢＭが形成され、その上層にカラーフィルタ層ＣＦが形成され、その上層に共通電極ｃｏｍ（図２参照）が形成され、さらにこれを覆うように配向膜（図示せず）が形成されている。なお、図３において、ＣＦ（Ｒ）は赤色のカラーフィルタ層を示し、ＣＦ（Ｇ）は緑色のカラーフィルタ層を示している。 On the other hand, in the color filter substrate 20, the black matrix BM is formed on the glass substrate 21, the color filter layer CF is formed on the upper layer, and the common electrode com (see FIG. 2) is formed on the upper layer, and further covers this. Thus, an alignment film (not shown) is formed. In FIG. 3, CF (R) represents a red color filter layer, and CF (G) represents a green color filter layer.
　カラーフィルタ基板２０には、さらに、スペーサ２２が形成されている。スペーサ２２は、透過率の低下などによる表示品位の低下を防ぐため、ブラックマトリクスＢＭの形成領域内に設けられている。また、スペーサ２２は、画素ごとに１つ設けられていてもよいし、３つの画素（例えばＲＧＢ画素）に１つの割合で設けられていてもよいし、それよりも少ない割合（複数画素に１つの割合）で設けられていてもよい。例えば、全てのＲ画素にスペーサ２２が１つずつ設けられている構成や、行列方向に配されたＲ画素に着目して、１つ置きあるいは２つ以上置きにスペーサ２２が設けられている構成（つまり、スペーサ２２が設けられているＲ画素と、スペーサ２２が設けられていないＲ画素とが交互に配されている構成）や、Ｒ画素、Ｇ画素およびＢ画素に交互にスペーサ２２が１つずつ設けられている構成とすることができる。以下では、便宜上、各Ｒ画素に１つずつスペーサ２２が設けられている構成について説明する。なお、画素の種類は、Ｒ（赤）色、Ｇ（緑）色およびＢ（青）色に対応する、Ｒ画素、Ｇ画素およびＢ画素に限定されず、Ｙ（黄）色およびＷ（白）色に対応する、Ｙ画素およびＷ画素を含んでいてもよい。 The spacer 22 is further formed on the color filter substrate 20. The spacer 22 is provided in the formation region of the black matrix BM in order to prevent the display quality from being deteriorated due to a decrease in transmittance or the like. One spacer 22 may be provided for each pixel, one spacer may be provided for three pixels (for example, RGB pixels), or a smaller ratio (one for a plurality of pixels). May be provided at a ratio of two). For example, a configuration in which one spacer 22 is provided for every R pixel, or a configuration in which spacers 22 are provided for every other pixel or every two or more, focusing on the R pixels arranged in the matrix direction. (That is, a configuration in which the R pixel provided with the spacer 22 and the R pixel not provided with the spacer 22 are alternately arranged), or the spacer 22 is alternately set to 1 for the R pixel, the G pixel, and the B pixel. It can be set as the structure provided one by one. Hereinafter, for convenience, a configuration in which one spacer 22 is provided for each R pixel will be described. Note that the types of pixels are not limited to R pixels, G pixels, and B pixels corresponding to R (red), G (green), and B (blue) colors, but Y (yellow) and W (white) ) Y and W pixels corresponding to colors may be included.
　また、スペーサ２２は、アクティブマトリクス基板１０とカラーフィルタ基板２０とが貼り合わされたときに、走査信号線ＧＬの切り欠き部２４に受容される位置に形成されている。すなわち、スペーサ２２は、液晶パネル２を平面的に見て、ブラックマトリクスＢＭが形成されている領域において、走査信号線ＧＬ（第１信号線）の切り欠き部２４に受容されるように設けられている。なお、走査信号線ＧＬの切り欠き部２４は、スペーサ２２を受容できる形状に形成されており、スペーサ２２の形状に応じて決定することができる。スペーサ２２の形状は、円形に限定されるものではなく、楕円形、矩形としてもよい。 Also, the spacer 22 is formed at a position that is received by the notch 24 of the scanning signal line GL when the active matrix substrate 10 and the color filter substrate 20 are bonded together. That is, the spacer 22 is provided so as to be received by the cutout portion 24 of the scanning signal line GL (first signal line) in the region where the black matrix BM is formed when the liquid crystal panel 2 is viewed in plan. ing. The notch 24 of the scanning signal line GL is formed in a shape that can receive the spacer 22 and can be determined according to the shape of the spacer 22. The shape of the spacer 22 is not limited to a circle, and may be an ellipse or a rectangle.
　（製造方法）
　次に、液晶パネル２の製造方法の一例について説明する。液晶パネル２の製造方法には、アクティブマトリクス基板製造工程と、カラーフィルタ基板製造工程と、両基板を貼り合わせて液晶を充填する組み立て工程とが含まれる。まず、アクティブマトリクス基板１０の製造工程について説明する。 (Production method)
Next, an example of a manufacturing method of the liquid crystal panel 2 will be described. The manufacturing method of the liquid crystal panel 2 includes an active matrix substrate manufacturing process, a color filter substrate manufacturing process, and an assembling process in which both substrates are bonded together and filled with liquid crystal. First, the manufacturing process of the active matrix substrate 10 will be described.
　初めに、ガラス、プラスチック等の透明絶縁性基板（図３ではガラス基板１１）上に、例えばチタン、クロム、アルミニウム、モリブデン、タンタル、タングステン、銅等の金属膜あるいはそれらの合金膜またはそれらの積層膜を１０００Å～３０００Åの膜厚でスパッタリング法等の方法にて成膜し、これをフォトエッチング法にて必要な形状にパターニングすることによって、（各トランジスタのゲート電極として機能する）走査信号線、保持容量配線等を形成する。なお、このとき、走査信号線ＧＬに、スペーサ２２を受容できるように切り欠き部２４を形成する。 First, a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, copper, or an alloy film thereof or a laminate thereof is formed on a transparent insulating substrate (glass substrate 11 in FIG. 3) such as glass or plastic. By forming a film with a thickness of 1000 to 3000 mm by a method such as a sputtering method and patterning the film into a necessary shape by a photoetching method, a scanning signal line (functioning as a gate electrode of each transistor), A storage capacitor wiring or the like is formed. At this time, the notch 24 is formed in the scanning signal line GL so that the spacer 22 can be received.
　次に、ゲート絶縁膜となる窒化シリコン膜（ＳｉＮｘ）、アモルファスシリコンやポリシリコン等からなる高抵抗半導体層、およびｎ＋アモルファスシリコン等の低抵抗半導体層を、プラズマＣＶＤ（化学的気相成長）法等により連続して成膜し、フォトエッチング法により低抵抗半導体層、高抵抗半導体層、およびゲート絶縁膜をパターニングする。このとき、コンタクトホールにおけるゲート絶縁膜の刳り抜きも形成される。なお、ゲート絶縁膜としての窒化シリコン膜は、例えば３０００Å～５０００Å程度の膜厚とし、高抵抗半導体層としてのアモルファスシリコン膜は、例えば１０００Å～３０００Å程度の膜厚とし、低抵抗半導体層としてのｎ＋アモルファスシリコン膜は、例えば４００Å～７００Å程度の膜厚とする。 Next, a plasma CVD (chemical vapor deposition) method is applied to a silicon nitride film (SiNx) serving as a gate insulating film, a high resistance semiconductor layer made of amorphous silicon, polysilicon, or the like, and a low resistance semiconductor layer such as n + amorphous silicon. The low resistance semiconductor layer, the high resistance semiconductor layer, and the gate insulating film are patterned by a photoetching method. At this time, the gate insulating film in the contact hole is also formed. The silicon nitride film as the gate insulating film has a thickness of about 3000 to 5000 mm, for example, and the amorphous silicon film as the high resistance semiconductor layer has a film thickness of about 1000 to 3000 mm, for example, and n + as the low resistance semiconductor layer. The amorphous silicon film has a thickness of about 400 to 700 mm, for example.
　次に、チタン、クロム、アルミニウム、モリブデン、タンタル、タングステン、銅等の金属膜あるいはそれらの合金膜、またはそれらの積層膜を１０００Å～３０００Åの膜厚でスパッタリング法等の方法にて形成し、フォトエッチング法等にて必要な形状にパターニングすることによって、データ信号線、ソース電極、およびドレイン電極等を形成する。 Next, a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, copper, or an alloy film thereof, or a laminated film thereof is formed to a thickness of 1000 to 3000 mm by a method such as sputtering, and photo A data signal line, a source electrode, a drain electrode, and the like are formed by patterning into a necessary shape by an etching method or the like.
　次に、アモルファスシリコン膜等の高抵抗半導体層（ｉ層）、ｎ＋アモルファスシリコン膜等の低抵抗半導体層（ｎ＋層）に対して、データ信号線、ソース電極、およびドレイン電極等のパターンをマスクにし、ドライエッチングにてチャネルエッチングを行う。このプロセスにてｉ層の膜厚が最適化され、各トランジスタ（チャネル領域）が形成される。ここでは、マスクで覆われていない半導体層がエッチング除去され、各トランジスタの能力に必要なｉ層膜厚が残される。 Next, a pattern such as a data signal line, a source electrode, and a drain electrode is masked for a high resistance semiconductor layer (i layer) such as an amorphous silicon film and a low resistance semiconductor layer (n + layer) such as an n + amorphous silicon film. Then, channel etching is performed by dry etching. In this process, the film thickness of the i layer is optimized, and each transistor (channel region) is formed. Here, the semiconductor layer not covered with the mask is removed by etching, leaving the i-layer thickness necessary for the capability of each transistor.
　次に、層間絶縁膜として、窒化シリコンや酸化シリコン等の無機絶縁膜（パッシベーション膜）を、データ信号線、ソース電極、およびドレイン電極等を覆うように形成する。ここでは、プラズマＣＶＤ法等によって２０００Å～５０００Å程度の膜厚の窒化シリコン膜（パッシベーション膜）を形成している。なお、本液晶表示装置１では、層間絶縁膜は、膜厚が１００００Å以下になるように形成されている。 Next, an inorganic insulating film (passivation film) such as silicon nitride or silicon oxide is formed as an interlayer insulating film so as to cover the data signal line, the source electrode, the drain electrode, and the like. Here, a silicon nitride film (passivation film) having a thickness of about 2000 to 5000 mm is formed by plasma CVD or the like. In the present liquid crystal display device 1, the interlayer insulating film is formed so as to have a film thickness of 10,000 mm or less.
　次に、コンタクトホールの位置に基づいて、層間絶縁膜をエッチングしてホールを形成する。ここでは、例えば、感光性レジストをフォトリソグラフィー法（露光および現像）によりパターニングし、エッチングを行う。 Next, based on the position of the contact hole, the interlayer insulating film is etched to form a hole. Here, for example, the photosensitive resist is patterned by photolithography (exposure and development), and etching is performed.
　次に、層間絶縁膜上に、例えば、ＩＴＯ（インジウム錫酸化物）、ＩＺＯ、酸化亜鉛、酸化スズ等の透明性を有する導電膜を、スパッタリング法等により１０００Å～２０００Å程度の膜厚で成膜し、これをフォトエッチング法等にて必要な形状にパターニングすることによって各画素領域に画素電極を形成する。 Next, a transparent conductive film such as ITO (indium tin oxide), IZO, zinc oxide, tin oxide or the like is formed on the interlayer insulating film with a film thickness of about 1000 to 2000 mm by a sputtering method or the like. A pixel electrode is formed in each pixel region by patterning it into a necessary shape by a photoetching method or the like.
　最後に、画素電極上の基板全体に、ポリイミド樹脂を厚さ５００Å～１０００Åで印刷し、その後、焼成して、回転布にて一方向にラビング処理を行って、配向膜を形成する。以上のようにして、アクティブマトリクス基板１０が製造される。 Finally, polyimide resin is printed on the entire substrate on the pixel electrode with a thickness of 500 to 1000 mm, and then baked and rubbed in one direction with a rotating cloth to form an alignment film. The active matrix substrate 10 is manufactured as described above.
　次に、カラーフィルタ基板２０の製造工程について説明する。 Next, the manufacturing process of the color filter substrate 20 will be described.
　まず、ガラス、プラスチック等の透明絶縁性基板（図３ではガラス基板２１）上に、クロム薄膜、または黒色顔料を含有する樹脂を成膜した後にフォトリソグラフィー法によってパターニングを行い、ブラックマトリクスを形成する。 First, a chromium thin film or a resin containing a black pigment is formed on a transparent insulating substrate (glass substrate 21 in FIG. 3) such as glass or plastic, and then patterned by photolithography to form a black matrix. .
　次に、ブラックマトリクスの間隙および上面に、顔料分散法などを用いて、赤、緑および青のカラーフィルタ層（厚さ２μｍ程度）をパターン形成する。 Next, red, green, and blue color filter layers (thickness of about 2 μm) are formed in a pattern on the gap and upper surface of the black matrix by using a pigment dispersion method or the like.
　次に、カラーフィルタ層上の基板全体に、ＩＴＯ、ＩＺＯ、酸化亜鉛、酸化スズなどからなる透明導電膜（厚さ１０００Å程度）を成膜し、共通電極（ｃｏｍ）を形成する。 Next, a transparent conductive film (thickness of about 1000 mm) made of ITO, IZO, zinc oxide, tin oxide or the like is formed on the entire substrate on the color filter layer to form a common electrode (com).
　次に、共通電極上の基板全体に、ポリイミド樹脂を厚さ５００Å～１０００Åで印刷し、その後、焼成して、回転布にて一方向にラビング処理を行って、配向膜を形成する。 Next, polyimide resin is printed on the entire substrate on the common electrode with a thickness of 500 to 1000 mm, and then baked and rubbed in one direction with a rotating cloth to form an alignment film.
　最後に、配向膜上に樹脂を成膜した後にフォトリソグラフィー法によってパターニングを行い、ブラックマトリクスの形成領域内にスペーサ２２を形成する。上記のようにして、カラーフィルタ基板２０を製造することができる。 Finally, after forming a resin on the alignment film, patterning is performed by a photolithography method to form spacers 22 in the black matrix formation region. The color filter substrate 20 can be manufactured as described above.
　次に、組み立て工程について、説明する。 Next, the assembly process will be described.
　まず、アクティブマトリクス基板１０およびカラーフィルタ基板２０の一方に、スクリーン印刷により、熱硬化性エポキシ樹脂などからなるシール材料を液晶注入口の部分を欠いた枠状パターンに塗布する。 First, a seal material made of a thermosetting epoxy resin or the like is applied to one of the active matrix substrate 10 and the color filter substrate 20 in a frame-like pattern lacking a liquid crystal injection port portion by screen printing.
　次に、アクティブマトリクス基板１０とカラーフィルタ基板２０とを貼り合わせ、シール材料を硬化させる。このとき、アクティブマトリクス基板１０とカラーフィルタ基板２０とは、液晶パネル２を平面的に見て、カラーフィルタ基板２０のスペーサ２２が走査信号線ＧＬの切り欠き部２４に受容されるように、貼り合わされる。 Next, the active matrix substrate 10 and the color filter substrate 20 are bonded together, and the sealing material is cured. At this time, the active matrix substrate 10 and the color filter substrate 20 are pasted so that the spacer 22 of the color filter substrate 20 is received in the cutout portion 24 of the scanning signal line GL when the liquid crystal panel 2 is viewed in plan. Combined.
　最後に、アクティブマトリクス基板１０およびカラーフィルタ基板２０並びにシール材料で囲まれる空間に、減圧法により液晶材料を注入した後、液晶注入口にＵＶ硬化樹脂を塗布し、ＵＶ照射によって液晶材料を封止することで液晶層３０を形成する。以上のようにして、液晶パネル２が製造される。 Finally, after injecting a liquid crystal material into the space surrounded by the active matrix substrate 10 and the color filter substrate 20 and the sealing material by a decompression method, a UV curable resin is applied to the liquid crystal injection port, and the liquid crystal material is sealed by UV irradiation. Thus, the liquid crystal layer 30 is formed. The liquid crystal panel 2 is manufactured as described above.
　上記の構成によれば、走査信号線ＧＬの切り欠き部２４が設けられているため、走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離およびブラックマトリクスＢＭの幅を、従来の図２２の構成から図４の（ａ）の構成のように広げることなく、スペーサ２２を配置する領域を広げることができる。 According to the above configuration, since the cutout portion 24 of the scanning signal line GL is provided, the distance between the scanning signal line GL and the storage capacitor line CSL and the width of the black matrix BM are set as shown in FIG. The region in which the spacer 22 is disposed can be expanded without increasing the configuration as in the configuration of FIG.
　すなわち、上記の構成によれば、図２２に示す従来の構成と比較して、走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離およびブラックマトリクスＢＭの幅を広げる必要がないため、図２２に示す従来の構成における透過率と同等の透過率を得ることができる。そのため、表示品位が低下することはない。なお、走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離およびブラックマトリクスＢＭの幅を、図２２に示す従来の構成よりも小さくすることもできるため、この場合は、従来よりも透過率を高めることができ、表示品位を向上させることができる。また、上記の構成によれば、スペーサ２２を配置する領域を、図４の（ａ）に示す従来の構成におけるスペーサの配置領域（走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離）と同等以上の領域とすることができるため、セルギャップの変動を確実に抑えることができる。 That is, according to the above configuration, it is not necessary to increase the distance between the scanning signal line GL and the storage capacitor line CSL and the width of the black matrix BM as compared with the conventional configuration shown in FIG. The transmittance equivalent to that in the conventional configuration shown in FIG. For this reason, the display quality does not deteriorate. Note that the distance between the scanning signal line GL and the storage capacitor line CSL and the width of the black matrix BM can be made smaller than those in the conventional configuration shown in FIG. The display quality can be improved. Further, according to the above configuration, the region in which the spacer 22 is arranged is the spacer arrangement region (distance between the scanning signal line GL and the storage capacitor line CSL) in the conventional configuration shown in FIG. Since the region can be equal to or greater than that, the cell gap can be reliably suppressed.
　以上のように、本液晶表示装置１によれば、透過率を低下させることなく、一対の基板間のセルギャップの変動を抑えることができる。 As described above, according to the present liquid crystal display device 1, it is possible to suppress the variation in the cell gap between the pair of substrates without reducing the transmittance.
　また、本実施の形態では、切り欠き部２４は、３つの画素（ＲＧＢ）のうちの１つの画素（図２および図３ではＲ画素）に相当する部分のみに形成されているため、歩留まりおよび配線不可への影響を１／３程度に抑えることができる。 In the present embodiment, the notch 24 is formed only in a portion corresponding to one pixel (R pixel in FIGS. 2 and 3) of the three pixels (RGB). The influence on the wiring failure can be suppressed to about 1/3.
　また、本液晶表示装置１では、スペーサ２２を全ての切り欠き部２４に設ける構成（図２参照）に限定されず、全ての切り欠き部２４において交互にスペーサ２２を設けてもよい。例えば、図５に示すように、切り欠き部２４がＲ画素のみに設けられ、スペーサ２２が、行列方向に配されたＲ画素に着目して、１つ置きに設けられている構成としてもよい。 Further, the present liquid crystal display device 1 is not limited to the configuration in which the spacers 22 are provided in all the cutout portions 24 (see FIG. 2), and the spacers 22 may be provided alternately in all the cutout portions 24. For example, as shown in FIG. 5, the cutout portions 24 may be provided only in the R pixels, and the spacers 22 may be provided every other pixel paying attention to the R pixels arranged in the matrix direction. .
　図５の構成では、Ｒ画素のうちのスペーサ２２が設けられているＲ画素における走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離が、Ｇ画素およびＢ画素における走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離よりも大きくなっている。また、Ｒ画素のうちのスペーサ２２が設けられているＲ画素における走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離が、Ｒ画素のうちのスペーサ２２が設けられていないＲ画素における走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離と等しくなっている。図５の構成は、以下の各変形例にも適用することができる。 In the configuration of FIG. 5, the distance between the scanning signal line GL and the storage capacitor line CSL in the R pixel provided with the spacer 22 among the R pixels is equal to the scanning signal line GL and the storage capacitor in the G pixel and B pixel. It is larger than the distance to the wiring CSL. The distance between the scanning signal line GL and the storage capacitor line CSL in the R pixel in which the spacer 22 is provided among the R pixels is equal to the scanning signal in the R pixel in which the spacer 22 is not provided in the R pixel. This is equal to the distance between the line GL and the storage capacitor line CSL. The configuration of FIG. 5 can also be applied to the following modifications.
　このように、本液晶表示装置１では、スペーサ２２が１つの種類の画素（例えばＲ画素）全てに設けられている必要はない。すなわち、図５を例に挙げると、スペーサ２２は、液晶パネル２を平面的に見て、ブラックマトリクスＢＭが形成されている領域において、走査信号線ＧＬと保持容量配線ＣＳＬとの間に部分的に設けられており、スペーサ２２が設けられている部分（一部のＲ画素）の走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離が、スペーサ２２が設けられていない部分（他のＲ画素、Ｇ画素、Ｂ画素）のうちの少なくとも一部の走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離よりも大きい構成であってもよい。 Thus, in the present liquid crystal display device 1, the spacers 22 do not have to be provided for all of one kind of pixels (for example, R pixels). That is, taking FIG. 5 as an example, the spacer 22 is partially between the scanning signal line GL and the storage capacitor line CSL in the region where the black matrix BM is formed when the liquid crystal panel 2 is viewed in plan. The distance between the scanning signal line GL and the storage capacitor line CSL in the portion where the spacer 22 is provided (some R pixels) is equal to the portion where the spacer 22 is not provided (other R pixels). (A pixel, a G pixel, a B pixel) of at least some of the scanning signal lines GL and the storage capacitor wiring CSL may be larger.
　なお、切り欠き部２４は、保持容量配線ＣＳＬに形成されていてもよいし、走査信号線ＧＬおよび保持容量配線ＣＳＬの両方に形成されていてもよい。 The notch 24 may be formed in the storage capacitor line CSL, or may be formed in both the scanning signal line GL and the storage capacitor line CSL.
　以下では、本発明に係る液晶表示装置１の変形例について説明する。 Hereinafter, a modification of the liquid crystal display device 1 according to the present invention will be described.
　（変形例１）
　図６は、液晶パネル２の変形例１を示す平面図であり、図７は、ブラックマトリクスＢＭの幅を模式的に示す平面図である。図２の液晶パネル２と比較すると、走査信号線ＧＬ１には切り欠き部２４が設けられておらず、保持容量配線ＣＳＬ２の一部に折り曲げ部２５が形成されている。スペーサ２２は、この折り曲げ部２５に対応しており、折り曲げ部２５と走査信号線ＧＬ１との間の領域に設けられている。また、本変形例１では、スペーサ２２は、ＲＧＢの３画素のうちＲ画素のみに設けられている。そのため、保持容量配線ＣＳＬの折り曲げ部２５もＲ画素に対応する部分のみに形成されている。さらに、ブラックマトリクスＢＭは、各画素で共通の位置に形成されている。 (Modification 1)
FIG. 6 is a plan view showing Modification 1 of the liquid crystal panel 2, and FIG. 7 is a plan view schematically showing the width of the black matrix BM. Compared to the liquid crystal panel 2 of FIG. 2, the scanning signal line GL1 is not provided with the notch 24, and a bent portion 25 is formed in a part of the storage capacitor line CSL2. The spacer 22 corresponds to the bent portion 25, and is provided in a region between the bent portion 25 and the scanning signal line GL1. In the first modification, the spacer 22 is provided only for the R pixel among the three RGB pixels. Therefore, the bent portion 25 of the storage capacitor line CSL is also formed only in the portion corresponding to the R pixel. Further, the black matrix BM is formed at a common position in each pixel.
　上記の構成によれば、図２の構成と同様、図２２に示す従来の構成における透過率と同等の透過率を得ることができるため、表示品位が低下することはない。また、スペーサ２２を配置する領域を、図４の（ａ）に示す従来の構成におけるスペーサの配置領域（走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離）と同等以上の領域とすることができるため、セルギャップの変動を確実に抑えることができる。 According to the above configuration, as in the configuration of FIG. 2, the transmittance equivalent to the transmittance in the conventional configuration shown in FIG. 22 can be obtained, so that the display quality does not deteriorate. Further, the region where the spacer 22 is disposed is set to be equal to or larger than the spacer disposition region (distance between the scanning signal line GL and the storage capacitor line CSL) in the conventional configuration shown in FIG. Therefore, the cell gap fluctuation can be reliably suppressed.
　以上のように、本液晶表示装置１によれば、透過率を低下させることなく、一対の基板間のセルギャップの変動を抑えることができる。 As described above, according to the present liquid crystal display device 1, it is possible to suppress the variation in the cell gap between the pair of substrates without reducing the transmittance.
　ここで、本変形例１では、スペーサ２２は、Ｒ画素において、保持容量配線ＣＳＬ２の折り曲げ部２５に対応して設けられており、Ｇ画素およびＢ画素には設けられていない。そして、ブラックマトリクスＢＭは、スペーサ２２が設けられていない画素と同じように形成されている。すなわち、図７に示すように、スペーサ２２が設けられているＲ画素では、ブラックマトリクスＢＭの開口部に保持容量配線ＣＳＬの折り曲げ部２５が重なることになる。しかし、ブラックマトリクスＢＭの開口部に重なる保持容量配線ＣＳＬは３画素（ＲＧＢ）のうちの１画素（Ｒ）に相当する部分のみであるため、透過率、歩留まり、および配線不可への影響を１／３程度に抑えることができる。よって、従来と比較して、実質的に透過率が低下することもない。 Here, in Modification 1, the spacer 22 is provided in the R pixel corresponding to the bent portion 25 of the storage capacitor wiring CSL2, and is not provided in the G pixel and the B pixel. The black matrix BM is formed in the same manner as the pixel where the spacer 22 is not provided. That is, as shown in FIG. 7, in the R pixel provided with the spacer 22, the bent portion 25 of the storage capacitor wiring CSL overlaps the opening of the black matrix BM. However, since the storage capacitor wiring CSL overlapping the opening of the black matrix BM is only a portion corresponding to one pixel (R) of the three pixels (RGB), the influence on the transmittance, yield, and wiring impossibility is 1 / 3 or so. Therefore, the transmittance is not substantially lowered as compared with the conventional case.
　（変形例２）
　図８は、液晶パネル２の変形例２を示す平面図である。図２の液晶パネル２と比較すると、図２の液晶パネル２において、さらに、保持容量配線ＣＳＬ２の一部に折り曲げ部２５が形成されている。 (Modification 2)
FIG. 8 is a plan view showing Modification Example 2 of the liquid crystal panel 2. Compared with the liquid crystal panel 2 of FIG. 2, in the liquid crystal panel 2 of FIG. 2, a bent portion 25 is further formed in a part of the storage capacitor wiring CSL2.
　折り曲げ部２５は、走査信号線ＧＬ１の切り欠き部２４に対応しており、スペーサ２２は、走査信号線ＧＬ１の切り欠き部２４と保持容量配線ＣＳＬ２の折り曲げ部２５との間の領域に設けられている。また、本変形例２では、スペーサ２２は、ＲＧＢの３画素のうちＲ画素のみに設けられている。そのため、走査信号線ＧＬ１の切り欠き部２４および保持容量配線ＣＳＬの折り曲げ部２５もＲ画素に対応する部分のみに形成されている。さらに、ブラックマトリクスＢＭは、スペーサ２２が設けられていないＧ画素およびＢ画素に設けられる保持容量配線ＣＳＬに対応して形成されている。 The bent portion 25 corresponds to the cutout portion 24 of the scanning signal line GL1, and the spacer 22 is provided in a region between the cutout portion 24 of the scanning signal line GL1 and the bent portion 25 of the storage capacitor wiring CSL2. ing. In the second modification, the spacer 22 is provided only for the R pixel among the three pixels of RGB. Therefore, the cutout portion 24 of the scanning signal line GL1 and the bent portion 25 of the storage capacitor line CSL are also formed only in the portion corresponding to the R pixel. Further, the black matrix BM is formed corresponding to the storage capacitor wiring CSL provided in the G pixel and the B pixel where the spacer 22 is not provided.
　上記の構成によれば、スペーサ２２を配置する領域を図２の構成と同等にしつつ、走査信号線ＧＬと保持容量配線ＣＳＬとの間の距離を、図２の構成よりも小さくすることができるため、透過率を高めることができる。 According to the above configuration, the distance between the scanning signal line GL and the storage capacitor line CSL can be made smaller than the configuration in FIG. 2 while making the region in which the spacer 22 is disposed the same as the configuration in FIG. Therefore, the transmittance can be increased.
　なお、本変形例２においても、図９に示すように、変形例１と同様、スペーサ２２は、Ｒ画素において、保持容量配線ＣＳＬ２の折り曲げ部２５に対応して設けられており、Ｇ画素およびＢ画素には設けられていないため、Ｒ画素では、ブラックマトリクスＢＭの開口部に保持容量配線ＣＳＬの折り曲げ部２５が重なることになる。しかし、ブラックマトリクスＢＭの開口部に重なる保持容量配線ＣＳＬは３つの画素（ＲＧＢ）のうちの１つの画素（Ｒ）に相当する部分のみであるため、透過率、歩留まり、および配線不可への影響を１／３程度に抑えることができる。よって、従来と比較して、実質的に透過率が低下することはない。 In the second modified example, as shown in FIG. 9, as in the first modified example, the spacer 22 is provided in the R pixel corresponding to the bent portion 25 of the storage capacitor wiring CSL <b> 2. Since it is not provided in the B pixel, in the R pixel, the bent portion 25 of the storage capacitor wiring CSL overlaps the opening of the black matrix BM. However, since the storage capacitor wiring CSL that overlaps the opening of the black matrix BM is only a portion corresponding to one pixel (R) of the three pixels (RGB), it affects the transmittance, yield, and wiring impossibility. Can be suppressed to about 1/3. Therefore, the transmittance does not substantially decrease compared to the conventional case.
　（変形例３）
　図１０は、液晶パネル２の変形例３を示す平面図であり、図１１は、図１０のＡ－Ｂ断面図である。図２の液晶パネル２と比較すると、図２の液晶パネル２において、さらに、高さ調整部２３が形成されている。高さ調整部２３は、走査信号線ＧＬ１の切り欠き部２４および切り欠き部２４に対向する保持容量配線ＣＳＬ２の一部の上層部に形成されている。 (Modification 3)
10 is a plan view showing a third modification of the liquid crystal panel 2, and FIG. 11 is a cross-sectional view taken along the line AB of FIG. Compared with the liquid crystal panel 2 of FIG. 2, a height adjusting unit 23 is further formed in the liquid crystal panel 2 of FIG. 2. The height adjusting unit 23 is formed on the cutout portion 24 of the scanning signal line GL1 and an upper layer portion of a part of the storage capacitor line CSL2 facing the cutout portion 24.
　これにより、液晶パネル２に外力が加わっても、スペーサ２２が、走査信号線ＧＬ１あるいは保持容量配線ＣＳＬ２の上端部に乗り上げることがないため、セルギャップの変動を確実に抑えることができる。なお、高さ調整部２３は、走査信号線ＧＬ１あるいは保持容量配線ＣＳＬ２の上層部の層間絶縁膜１５上に形成される。 Thus, even when an external force is applied to the liquid crystal panel 2, the spacer 22 does not run on the upper end portion of the scanning signal line GL1 or the storage capacitor line CSL2, so that the cell gap can be reliably suppressed. The height adjusting unit 23 is formed on the interlayer insulating film 15 in the upper layer portion of the scanning signal line GL1 or the storage capacitor line CSL2.
　本変形例３の高さ調整部２３は、変形例１，２の液晶パネル２に適用することもできる。 The height adjusting unit 23 of the third modification can also be applied to the liquid crystal panel 2 of the first and second modifications.
　（変形例４）
　図１２は、液晶パネル２の変形例４を示す平面図である。図１２の液晶パネル２では、走査信号線ＧＬ１に切り欠き部２４が設けられておらず、また、保持容量配線ＣＳＬ２に折り曲げ部２５が設けられていない。そして、走査信号線ＧＬ１および保持容量配線ＣＳＬ２の上層部の一部に高さ調整部２３が形成されている。スペーサ２２は、走査信号線ＧＬ１の高さ調整部２３と、保持容量配線ＣＳＬ２の高さ調整部２３との間の領域に設けられる。 (Modification 4)
FIG. 12 is a plan view showing Modification Example 4 of the liquid crystal panel 2. In the liquid crystal panel 2 of FIG. 12, the cutout portion 24 is not provided in the scanning signal line GL1, and the bent portion 25 is not provided in the storage capacitor line CSL2. A height adjustment unit 23 is formed in part of the upper layer portion of the scanning signal line GL1 and the storage capacitor line CSL2. The spacer 22 is provided in a region between the height adjustment unit 23 of the scanning signal line GL1 and the height adjustment unit 23 of the storage capacitor line CSL2.
　これにより、液晶パネル２に外力が加わっても、スペーサ２２が、走査信号線ＧＬ１あるいは保持容量配線ＣＳＬ２の上層部に乗り上げることがないため、セルギャップの変動を確実に抑えることができる。また、走査信号線ＧＬ１と保持容量配線ＣＳＬ２との間の距離を、図２２に示す従来の構成と同様とすることができるため、透過率が低下することもない。なお、高さ調整部２３は、走査信号線ＧＬ１あるいは保持容量配線ＣＳＬ２の上層部の層間絶縁膜１５上に形成される。 As a result, even when an external force is applied to the liquid crystal panel 2, the spacer 22 does not run on the upper layer part of the scanning signal line GL1 or the storage capacitor line CSL2, so that the cell gap can be reliably suppressed. Further, since the distance between the scanning signal line GL1 and the storage capacitor line CSL2 can be made the same as that of the conventional configuration shown in FIG. 22, the transmittance is not lowered. The height adjusting unit 23 is formed on the interlayer insulating film 15 in the upper layer portion of the scanning signal line GL1 or the storage capacitor line CSL2.
　（変形例５）
　次に、スペーサ２２の変形例について説明する。スペーサ２２は、図１３に示すように、ブラックマトリクスＢＭ上に形成されていてもよい。また、スペーサ２２は、図１４および図１５に示すように、カラーフィルタ層ＣＦにより形成されていてもよい。さらに、スペーサ２２は、カラーフィルタ層ＣＦに限定されず、液晶配向制御層など、カラーフィルタ基板２０上に形成される既存の層により形成されていてもよいし、これら既存の層を複数使って重ね合わせることにより形成されていてもよい。例えば、図１４および図１５に示すように、スペーサ２２は、ブラックマトリクスＢＭ上に形成された赤色カラーフィルタ層ＣＦ（Ｒ）の上に、フォトリソグラフィー法により、緑色カラーフィルタ層ＣＦ（Ｇ）および青色カラーフィルタ層ＣＦ（Ｂ）を順にパターニングすることにより形成することができる。なお、各カラーフィルタ層ＣＦの膜厚を適宜設定することにより、スペーサ２２として機能させることができる。 (Modification 5)
Next, a modified example of the spacer 22 will be described. The spacers 22 may be formed on the black matrix BM as shown in FIG. The spacer 22 may be formed of a color filter layer CF as shown in FIGS. Furthermore, the spacer 22 is not limited to the color filter layer CF, and may be formed of an existing layer formed on the color filter substrate 20 such as a liquid crystal alignment control layer, or a plurality of these existing layers may be used. It may be formed by overlapping. For example, as shown in FIGS. 14 and 15, the spacer 22 is formed on the red color filter layer CF (R) formed on the black matrix BM by a photolithography method using the green color filter layer CF (G) and the spacer 22. The blue color filter layer CF (B) can be formed by patterning in order. In addition, it can function as the spacer 22 by appropriately setting the film thickness of each color filter layer CF.
　（変形例６）
　本発明の実施の形態に係る液晶表示装置１を構成する液晶パネル２は、図１の構成に限定されるものではなく、周知の構成を適用することができる。液晶パネル２の他の形態について一例を挙げると、図１６に示すとおりである。 (Modification 6)
The liquid crystal panel 2 constituting the liquid crystal display device 1 according to the embodiment of the present invention is not limited to the configuration of FIG. 1, and a known configuration can be applied. An example of another form of the liquid crystal panel 2 is as shown in FIG.
　図１６に示す液晶パネル２を備える液晶表示装置１は、１つの画素列に２本のデータ信号線（左側データ信号線及び右側データ信号線）を設け、同一画素列に含まれる奇数番目の画素の画素電極を左側データ信号線に接続する一方、偶数番目の画素の画素電極を右側データ信号線に接続し、連続する２本の走査信号線（奇数番目の画素に接続する走査信号線及び偶数番目の画素に接続する走査信号線）を同時選択する構成である。この構成によれば、列方向に隣り合う２つの画素に同時にデータ信号電位を書き込むことができるため、画面の書き換え速度を高めることができ、各画素の充電時間を増加させることができるという効果を奏する。 The liquid crystal display device 1 including the liquid crystal panel 2 illustrated in FIG. 16 includes two data signal lines (left data signal line and right data signal line) in one pixel column, and odd-numbered pixels included in the same pixel column. Are connected to the left data signal line, while the pixel electrodes of the even-numbered pixels are connected to the right data signal line, and two consecutive scanning signal lines (the scanning signal lines connected to the odd-numbered pixels and the even-numbered pixels) The scanning signal line connected to the second pixel) is selected at the same time. According to this configuration, since the data signal potential can be simultaneously written in two pixels adjacent in the column direction, the screen rewriting speed can be increased, and the charging time of each pixel can be increased. Play.
　ここで、図１６の液晶表示装置１では、図１７および図１８に示すように、隣り合う２本のデータ信号線ＤＬ１ｂ、ＤＬ２ａ（第１信号線、第２信号線）に折り曲げ部２５を設け、折り曲げ部２５の間の領域にスペーサ２２を配置する構成とすることができる。また、２本のデータ信号線ＤＬ１ｂ、ＤＬ２ａの少なくとも一方に切り欠き部を設け、切り欠き部にスペーサ２２が受容されるように構成することもできる。 Here, in the liquid crystal display device 1 of FIG. 16, as shown in FIGS. 17 and 18, a bent portion 25 is provided on two adjacent data signal lines DL1b and DL2a (first signal line and second signal line). The spacer 22 can be arranged in the region between the bent portions 25. Further, it is also possible to provide a notch in at least one of the two data signal lines DL1b and DL2a so that the spacer 22 is received in the notch.
　また、本実施の形態においてスペーサ２２を介して隣り合う２本の信号線の組み合わせとしては、(i)走査信号線および保持容量配線、(ii)隣り合う２本の走査信号線、(iii)隣り合う２本の保持容量配線、(iv)隣り合う２本のデータ信号線、の組み合わせとすることができる。 In this embodiment, the combination of two signal lines adjacent via the spacer 22 includes (i) a scanning signal line and a storage capacitor line, (ii) two adjacent scanning signal lines, and (iii) A combination of two adjacent storage capacitor lines and (iv) two adjacent data signal lines can be used.
　本発明の実施の形態に係る液晶表示装置では、
　上記液晶パネルには、少なくとも、Ｒ色、Ｇ色およびＢ色に対応する、Ｒ画素、Ｇ画素およびＢ画素の種類の画素が含まれており、
　上記保持部材は、上記Ｒ画素、上記Ｇ画素および上記Ｂ画素のうちの１つの種類の画素のうち、少なくとも１つの画素に設けられており、
　上記１つの種類の画素のうちの上記保持部材が設けられている画素における上記第１信号線と上記第２信号線との間の距離は、上記１つの種類の画素とは異なる種類の画素における上記第１信号線と上記第２信号線との間の距離よりも大きい構成とすることもできる。 In the liquid crystal display device according to the embodiment of the present invention,
The liquid crystal panel includes at least R, G, and B pixel types corresponding to R, G, and B colors,
The holding member is provided in at least one of the one type of pixels among the R pixel, the G pixel, and the B pixel,
Among the one type of pixels, the distance between the first signal line and the second signal line in the pixel provided with the holding member is different in the type of pixel different from the one type of pixel. A configuration in which the distance is larger than the distance between the first signal line and the second signal line may be employed.
　本発明の実施の形態に係る液晶表示装置では、上記１つの種類の画素のうちの上記保持部材が設けられている画素における上記第１信号線と上記第２信号線との間の距離は、上記１つの種類の画素のうちの上記保持部材が設けられていない画素における上記第１信号線と上記第２信号線との間の距離と等しい構成とすることもできる。 In the liquid crystal display device according to the embodiment of the present invention, the distance between the first signal line and the second signal line in the pixel provided with the holding member among the one type of pixels is A configuration in which the distance between the first signal line and the second signal line in a pixel in which the holding member is not provided among the one kind of pixels may be used.
　本発明の実施の形態に係る液晶表示装置では、上記第１基板を構成する層間絶縁膜は、無機層間絶縁膜であってもよい。 In the liquid crystal display device according to the embodiment of the present invention, the interlayer insulating film constituting the first substrate may be an inorganic interlayer insulating film.
　これにより、第１基板が凹凸状に構成（積層）されている液晶表示装置において、一対の基板間のセルギャップの変動を抑えることができる。 Thereby, in the liquid crystal display device in which the first substrate is configured (laminated) in a concavo-convex shape, variation in the cell gap between the pair of substrates can be suppressed.
　本発明の実施の形態に係る液晶表示装置では、上記保持部材は、上記第２基板において、カラーフィルタ層上あるいは上記遮光層上に形成されている構成とすることもできる。 In the liquid crystal display device according to the embodiment of the present invention, the holding member may be formed on the color filter layer or the light shielding layer in the second substrate.
　本発明の実施の形態に係る液晶表示装置では、上記保持部材は、カラーフィルタ層あるいは液晶配向制御層により形成されている構成とすることもできる。 In the liquid crystal display device according to the embodiment of the present invention, the holding member may be formed of a color filter layer or a liquid crystal alignment control layer.
　これにより、既存の製造工程を利用することができるため、製造工程が複雑化することもない。なお、保持部材は、カラーフィルタ層あるいは液晶配向制御層に限定されず、第２基板（カラーフィルタ基板）上に形成される他の既存の層により形成されていてもよいし、カラーフィルタ層あるいは液晶配向制御層を含む多層構造に形成されていてもよい。 This makes it possible to use an existing manufacturing process, so that the manufacturing process is not complicated. The holding member is not limited to the color filter layer or the liquid crystal alignment control layer, and may be formed of another existing layer formed on the second substrate (color filter substrate), or the color filter layer or It may be formed in a multilayer structure including a liquid crystal alignment control layer.
　本発明の実施の形態に係る液晶表示装置では、上記第１信号線は走査信号線であり、上記第２信号線は保持容量配線であってもよい。 In the liquid crystal display device according to the embodiment of the present invention, the first signal line may be a scanning signal line, and the second signal line may be a storage capacitor line.
　これにより、遮光層の幅を大きくする必要がないため、透過率の低下を防ぐことができ、表示品位の低下を防ぐことができる。 Thereby, it is not necessary to increase the width of the light shielding layer, so that the transmittance can be prevented from being lowered and the display quality can be prevented from being lowered.
　本発明の実施の形態に係る液晶表示装置では、上記第１信号線および上記第２信号線の少なくとも何れか一方には、上記保持部材を受容するための切り欠き部あるいは折り曲げ部が形成されていてもよい。 In the liquid crystal display device according to the embodiment of the present invention, at least one of the first signal line and the second signal line is formed with a notch or a bent part for receiving the holding member. May be.
　上記の構成によれば、保持部材は切り欠き部あるいは折り曲げ部に受容されるため、第１信号線および第２信号線の間の距離を小さくすることができる。これにより、遮光層の幅を小さくすることができるため、透過率を高めることができる。 According to the above configuration, since the holding member is received in the cutout portion or the bent portion, the distance between the first signal line and the second signal line can be reduced. Thereby, since the width | variety of a light shielding layer can be made small, the transmittance | permeability can be raised.
　本発明の実施の形態に係る液晶表示装置では、
　上記保持部材が設けられている部分における上記第１信号線および上記第２信号線のそれぞれの上層部には、高さ調整部が設けられている構成とすることもできる。 In the liquid crystal display device according to the embodiment of the present invention,
A height adjusting portion may be provided in the upper layer portion of each of the first signal line and the second signal line in the portion where the holding member is provided.
　上記の構成によれば、液晶パネルに外力が加わっても、保持部材が、第１信号線あるいは第２信号線の上層部に乗り上げることがないため、セルギャップの変動を確実に抑えることができる。 According to the above configuration, even when an external force is applied to the liquid crystal panel, the holding member does not run on the upper layer portion of the first signal line or the second signal line, so that the cell gap can be reliably suppressed. .
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
　本発明の液晶表示装置は、液晶テレビ等の各種用途に好適に用いることができる。 The liquid crystal display device of the present invention can be suitably used for various applications such as a liquid crystal television.
１　　　液晶表示装置
２　　　液晶パネル
１０　　アクティブマトリクス基板（第１基板）
１１　　ガラス基板
１２　　容量電極
１３　　ゲート絶縁膜
１４　　半導体層
１５　　層間絶縁膜
１６　　画素電極
２０　　カラーフィルタ基板（第２基板）
２１　　ガラス基板
２２　　スペーサ（保持部材）
２３　　高さ調整部
２４　　切り欠き部
２５　　折り曲げ部
３０　　液晶層
ＧＬ　　走査信号線（第１信号線）
ＤＬ　　データ信号線（第１信号線、第２信号線）
ＣＳＬ　保持容量配線（第２信号線）
ＣＦ　　カラーフィルタ層
ＢＭ　　ブラックマトリクス（遮光層）
ｃｏｍ　共通電極 DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Liquid crystal panel 10 Active matrix board | substrate (1st board | substrate)
11 Glass substrate 12 Capacitance electrode 13 Gate insulating film 14 Semiconductor layer 15 Interlayer insulating film 16 Pixel electrode 20 Color filter substrate (second substrate)
21 Glass substrate 22 Spacer (holding member)
23 Height adjustment part 24 Notch part 25 Bending part 30 Liquid crystal layer GL Scanning signal line (1st signal line)
DL data signal line (first signal line, second signal line)
CSL retention capacitor wiring (second signal line)
CF color filter layer BM Black matrix (light shielding layer)
com common electrode

Claims (10)

  1. 　互いに隣り合って並行するように配される第１信号線および第２信号線を含む第１基板と、該第１基板に対向配置され、遮光層が設けられた第２基板と、該第１基板および該第２基板の間に配された液晶層とを含む液晶パネルを備え、
    　上記第１基板および上記第２基板の間には、両基板の間隙を保持する保持部材が設けられており、
    　上記保持部材は、上記液晶パネルを平面的に見て、上記遮光層が形成されている領域において、上記第１信号線と上記第２信号線との間に部分的に設けられており、
    　上記保持部材が設けられている部分における上記第１信号線と上記第２信号線との間の距離が、上記保持部材が設けられていない部分のうちの少なくとも一部における上記第１信号線と上記第２信号線との間の距離よりも大きいことを特徴とする液晶表示装置。     A first substrate including a first signal line and a second signal line arranged adjacent to each other in parallel; a second substrate disposed opposite to the first substrate and provided with a light shielding layer; and the first substrate A liquid crystal panel including a substrate and a liquid crystal layer disposed between the second substrate,
    A holding member is provided between the first substrate and the second substrate to hold a gap between the two substrates.
    The holding member is partially provided between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan view,
    The distance between the first signal line and the second signal line in the portion where the holding member is provided is equal to the first signal line in at least a part of the portion where the holding member is not provided. A liquid crystal display device, wherein the distance is larger than a distance between the second signal lines.
  2. 　互いに隣り合って並行するように配される第１信号線および第２信号線を含む第１基板と、該第１基板に対向配置され、遮光層が設けられた第２基板と、該第１基板および該第２基板の間に配された液晶層とを含む液晶パネルを備え、
    　上記第１基板および上記第２基板の間には、両基板の間隙を保持する保持部材が設けられており、
    　上記保持部材は、上記液晶パネルを平面的に見て、上記遮光層が形成されている領域において、上記第１信号線と上記第２信号線との間に部分的に設けられており、
    　上記保持部材が設けられている部分における上記第１信号線および上記第２信号線のそれぞれの上層部には、高さ調整部が設けられていることを特徴とする液晶表示装置。     A first substrate including a first signal line and a second signal line arranged adjacent to each other in parallel; a second substrate disposed opposite to the first substrate and provided with a light shielding layer; and the first substrate A liquid crystal panel including a substrate and a liquid crystal layer disposed between the second substrate,
    A holding member is provided between the first substrate and the second substrate to hold a gap between the two substrates.
    The holding member is partially provided between the first signal line and the second signal line in a region where the light shielding layer is formed when the liquid crystal panel is viewed in plan view,
    A liquid crystal display device, wherein a height adjusting portion is provided in an upper layer portion of each of the first signal line and the second signal line in a portion where the holding member is provided.
  3. 　上記液晶パネルには、少なくとも、Ｒ色、Ｇ色およびＢ色に対応する、Ｒ画素、Ｇ画素およびＢ画素の種類の画素が含まれており、
    　上記保持部材は、上記Ｒ画素、上記Ｇ画素および上記Ｂ画素のうちの１つの種類の画素のうち、少なくとも１つの画素に設けられており、
    　上記１つの種類の画素のうちの上記保持部材が設けられている画素における上記第１信号線と上記第２信号線との間の距離は、上記１つの種類の画素とは異なる種類の画素における上記第１信号線と上記第２信号線との間の距離よりも大きいことを特徴とする請求項１に記載の液晶表示装置。     The liquid crystal panel includes at least R, G, and B pixel types corresponding to R, G, and B colors,
    The holding member is provided in at least one of the one type of pixels among the R pixel, the G pixel, and the B pixel,
    Among the one type of pixels, the distance between the first signal line and the second signal line in the pixel provided with the holding member is different in the type of pixel different from the one type of pixel. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is larger than a distance between the first signal line and the second signal line.
  4. 　上記１つの種類の画素のうちの上記保持部材が設けられている画素における上記第１信号線と上記第２信号線との間の距離は、上記１つの種類の画素のうちの上記保持部材が設けられていない画素における上記第１信号線と上記第２信号線との間の距離と等しいことを特徴とする請求項３に記載の液晶表示装置。 The distance between the first signal line and the second signal line in the pixel provided with the holding member among the one type of pixels is determined by the holding member among the one type of pixels. 4. The liquid crystal display device according to claim 3, wherein a distance between the first signal line and the second signal line in a pixel that is not provided is equal to the distance between the first signal line and the second signal line.
  5. 　上記第１基板を構成する層間絶縁膜は、無機層間絶縁膜であることを特徴とする請求項１または２に記載の液晶表示装置。 3. The liquid crystal display device according to claim 1, wherein the interlayer insulating film constituting the first substrate is an inorganic interlayer insulating film.
  6. 　上記保持部材は、上記第２基板において、カラーフィルタ層上あるいは上記遮光層上に形成されていることを特徴とする請求項１または２に記載の液晶表示装置。 3. The liquid crystal display device according to claim 1, wherein the holding member is formed on the color filter layer or the light shielding layer in the second substrate.
  7. 　上記保持部材は、カラーフィルタ層あるいは液晶配向制御層により形成されていることを特徴とする請求項１または２に記載の液晶表示装置。 3. The liquid crystal display device according to claim 1, wherein the holding member is formed of a color filter layer or a liquid crystal alignment control layer.
  8. 　上記第１信号線は走査信号線であり、上記第２信号線は保持容量配線であることを特徴とする請求項１に記載の液晶表示装置。 2. The liquid crystal display device according to claim 1, wherein the first signal line is a scanning signal line, and the second signal line is a storage capacitor line.
  9. 　上記第１信号線および上記第２信号線の少なくとも何れか一方には、上記保持部材を受容するための切り欠き部あるいは折り曲げ部が形成されていることを特徴とする請求項１に記載の液晶表示装置。 2. The liquid crystal according to claim 1, wherein at least one of the first signal line and the second signal line is formed with a cutout portion or a bent portion for receiving the holding member. Display device.
  10. 　上記保持部材が設けられている部分における上記第１信号線および上記第２信号線のそれぞれの上層部には、高さ調整部が設けられていることを特徴とする請求項１に記載の液晶表示装置。 2. The liquid crystal according to claim 1, wherein a height adjusting portion is provided in an upper layer portion of each of the first signal line and the second signal line in a portion where the holding member is provided. Display device.
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CN103901660A (en) * 2012-12-26 2014-07-02 业鑫科技顾问股份有限公司 Liquid crystal display panel
WO2021208643A1 (en) * 2020-04-14 2021-10-21 京东方科技集团股份有限公司 Display panel and display device
WO2021238467A1 (en) * 2020-05-29 2021-12-02 京东方科技集团股份有限公司 Display apparatus
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