WO2012120788A1 - Boost pfc control device - Google Patents

Boost pfc control device Download PDF

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Publication number
WO2012120788A1
WO2012120788A1 PCT/JP2012/000950 JP2012000950W WO2012120788A1 WO 2012120788 A1 WO2012120788 A1 WO 2012120788A1 JP 2012000950 W JP2012000950 W JP 2012000950W WO 2012120788 A1 WO2012120788 A1 WO 2012120788A1
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Prior art keywords
voltage
switching element
terminal
current
source
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PCT/JP2012/000950
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French (fr)
Japanese (ja)
Inventor
修二 玉岡
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パナソニック株式会社
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Publication of WO2012120788A1 publication Critical patent/WO2012120788A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/0085—Partially controlled bridges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Definitions

  • the present invention relates to a high-input power factor and high-efficiency step-up PFC (Power Factor Correction) controller that rectifies an input AC voltage and outputs a DC voltage larger than the peak value of the AC voltage.
  • PFC Power Factor Correction
  • FIG. 13 is a circuit block diagram of a step-up PFC control device without a rectifier diode bridge described in Patent Document 1.
  • the step-up PFC control device 500 without a rectifier diode bridge described in FIG. 13 is intended to reduce the size and cost of the high-frequency block filter 502.
  • two sawtooth wave oscillators 514 and 515 having phases different from each other by 180 degrees are used, and the phase of the switching operation for boosting is shifted twice by 180 degrees. That is, the first switching operation by the switching elements T1 and T2 and the second switching operation by the switching elements T3 and T4. As a result, the ripple of the current flowing through the high-frequency blocking filter 502 has a second harmonic compared with the switching frequency. As a result, the high-frequency blocking filter 502 can be reduced in size and cost.
  • the above-described conventional step-up PFC control device 500 generates a loss due to a voltage drop due to the forward voltage VF of the diode D1 or D2 and the forward voltage VFP of the parasitic diode of the switching elements T1 to T4 made of silicon semiconductor. Have the problem of doing.
  • the switching loss during the turn-on operation of the switching elements T1 to T4 is large due to the recovery current of the parasitic diodes of the switching elements T1 to T4 made of silicon-based semiconductor. Further, the switching loss increases in proportion to the switching frequency of the PFC control device. Therefore, increasing the switching frequency in order to reduce the size of the magnetic induction means 504 causes an increase in switching loss.
  • the present invention provides a step-up PFC control device that realizes low power consumption and miniaturization by eliminating the parasitic diodes of the switching elements and the diodes D1 and D2 that occupy most of the power consumption in the PFC control device.
  • a step-up PFC control device is a step-up PFC control device including an AC / DC converter unit that rectifies and boosts an input single-phase AC voltage.
  • the AC / DC converter unit includes a plurality of AC switch units that are bridge-connected, a boosting coil, a smoothing capacitor, and a drive logic circuit.
  • the boosting coil stores magnetic energy corresponding to the bidirectional current that flows in response to the application of the single-phase AC voltage.
  • the smoothing capacitor stores a boosting coil and a charge corresponding to the magnetic energy stored in the boosting coil.
  • the drive logic circuit switches the current path of bidirectional current by controlling the on / off state of a plurality of AC switch units, and alternately stores magnetic energy in the boosting coil and charges in the smoothing capacitor. Make it.
  • Each of the plurality of AC switch units has a gate terminal, a drain terminal, and a source terminal.
  • the AC switch unit is composed of a switching element having FET characteristics, reverse FET characteristics, and reverse conduction characteristics.
  • the FET characteristic is a characteristic in which current flows from the drain terminal to the source terminal according to the polarity of the drain-source voltage when the gate-source voltage, which is the gate voltage with respect to the source voltage, is higher than the threshold voltage.
  • the reverse FET characteristic is a characteristic in which current flows from the source terminal to the drain terminal according to the polarity of the drain-source voltage when the gate-source voltage is higher than the threshold voltage.
  • Reverse conduction characteristics means that when the gate-source voltage is equal to or lower than the threshold voltage (hereinafter referred to as “below”), the current flowing from the drain terminal to the source terminal is cut off, and the gate voltage relative to the drain voltage is This is a characteristic in which a current flows from the source terminal to the drain terminal when it is equal to or higher than the threshold voltage (hereinafter referred to as “more”).
  • the plurality of AC switch units have first to fourth switching elements.
  • the first electrode of the boosting coil is connected to a first AC terminal to which a single-phase AC voltage is applied.
  • the drain terminal of the first switching element and the drain terminal of the third switching element are connected to the first electrode of the smoothing capacitor.
  • the source terminal of the second switching element and the source terminal of the fourth switching element are connected to the second electrode of the smoothing capacitor.
  • the source terminal of the first switching element and the drain terminal of the second switching element are connected to the second electrode of the boosting coil.
  • the source terminal of the third switching element and the drain terminal of the fourth switching element are connected to a second AC terminal to which a single-phase AC voltage is applied.
  • the gate terminals of the first to fourth switching elements are connected to the respective predrive circuits that shift the level of the control signal output from the drive logic circuit.
  • the drive logic circuit controls so that the first switching element and the second switching element are not turned on at the same time, or the third switching element and the fourth switching element are not turned on at the same time. May be.
  • the AC / DC converter unit is constituted by a basic bridge circuit in which four bidirectional switching elements are bridge-connected. Therefore, the AC / DC converter unit can control and boost the bidirectional current path simply and with high efficiency.
  • the drive logic circuit further includes a case where the current flowing between the AC power source that outputs a single-phase AC voltage and the AC / DC converter unit is zero (hereinafter, including substantially zero).
  • At least two of the plurality of AC switch units may be configured by two switching elements in which source terminals or drain terminals are connected in series.
  • step-up PFC control device like the step-up PFC control device described above, it is possible to reduce power consumption while maintaining the rectification step-up operation of the conventional step-up type PFC control device. Furthermore, a step-up PFC control device having high input voltage resistance can be realized. In addition, the step-up PFC control device can completely disconnect the load connected between the output terminal and the GND terminal of the step-up PFC control device from the input AC voltage source.
  • the switching element includes a stacked body formed of a plurality of nitride semiconductor layers formed on a semiconductor substrate, a gate terminal formed on the stacked body, and a gate terminal sandwiched between the gate terminals. It is desirable to provide a drain terminal and a source terminal formed on both sides.
  • the switching element is generally known as a heterojunction field effect transistor using a gallium nitride semiconductor and is called a GaN transistor.
  • a GaN transistor has FET characteristics and reverse FET characteristics when the gate / source voltage is higher than a certain threshold voltage, and has reverse conduction characteristics when the gate / source voltage is equal to or lower than the threshold voltage.
  • the GaN transistor also serves as a bidirectional switching element having high breakdown voltage characteristics, and is also an FET transistor having a very low on-resistance value in FET characteristics and reverse FET characteristics. The on-resistance is the resistance of the channel portion when a current flows through the switching element.
  • the switching frequency can be increased by reducing the switching loss, whereby the size of the boosting coil can be reduced, and as a result, the device can be reduced in size.
  • the present invention it is possible to provide a step-up PFC control device that does not include a diode and a parasitic diode of a switching element.
  • the power consumption of the conventional boost type PFC control device is largely due to the diode and the parasitic diode of the switching element, but the power consumption can be greatly reduced in the present invention.
  • the PFC control unit included in the boost type PFC control device can use the control unit of the conventional boost type PFC control device as it is, the conventional boost type PFC control device changes to the boost type PFC control device of the present invention. Is easy to replace.
  • FIG. 1 is a circuit block diagram of a step-up PFC control apparatus according to an embodiment of the present invention.
  • FIG. 2A is an IV characteristic diagram showing the FET characteristics of the bidirectional switching element used in the present invention.
  • FIG. 2B is an IV characteristic diagram showing the reverse FET characteristic of the bidirectional switching element used in the present invention.
  • FIG. 2C is an IV characteristic diagram showing reverse conduction characteristics of the bidirectional switching element used in the present invention.
  • FIG. 2D is a diagram for explaining equivalent conversion in an on-operation state of the switching element.
  • FIG. 2E is a diagram for explaining equivalent conversion in an OFF operation state of the switching element.
  • FIG. 3A is a circuit block diagram of the drive logic circuit according to the embodiment of the present invention.
  • FIG. 3A is a circuit block diagram of the drive logic circuit according to the embodiment of the present invention.
  • FIG. 3B is an operation timing chart of internal signals of the drive logic circuit according to the exemplary embodiment of the present invention.
  • FIG. 4A is a diagram illustrating a current path of the boost operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply is positive.
  • FIG. 4B is a diagram illustrating a current path of the boost operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply is negative.
  • FIG. 5 is a cross-sectional view of a bidirectional switching element included in the step-up PFC control device of the present invention.
  • FIG. 6 is a circuit block diagram of a step-up PFC control device according to a first modification of the embodiment of the present invention.
  • FIG. 7A is an equivalent circuit diagram illustrating a state of the AC switch according to the first modification example of the embodiment when the voltage polarity of the input AC power supply is positive.
  • FIG. 7B is an equivalent circuit diagram illustrating a state of the AC switch according to the first modification example of the embodiment when the voltage polarity of the input AC power supply is negative.
  • FIG. 8A is a circuit block diagram of a drive logic circuit according to a second modification example of the embodiment of the present invention.
  • FIG. 8B is an operation timing chart of internal signals of the drive logic circuit according to the second modification example of the exemplary embodiment of the present invention.
  • FIG. 9A is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit according to the second modification example of the embodiment when the voltage polarity of the input AC power supply is positive.
  • FIG. 9B is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit according to the second modification example of the embodiment when the voltage polarity of the input AC power supply is negative.
  • FIG. 10 is a circuit block diagram of a boost type PFC control device according to a comparative example.
  • FIG. 11A is an equivalent circuit diagram illustrating a state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive.
  • FIG. 11B is an equivalent circuit diagram illustrating a state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative.
  • FIG. 12A is a diagram illustrating transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive.
  • FIG. 12B is a diagram illustrating transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative.
  • FIG. 13 is a circuit block diagram of a step-up PFC control device described in Patent Document 1 without a rectifier diode bridge.
  • FIG. 1 is a circuit block diagram of a step-up PFC control apparatus according to an embodiment of the present invention.
  • a step-up PFC control device 100 shown in FIG. 1 includes an AC / DC converter unit 30, a current detection element 3, an output load 8, a second error amplifier 9, a multiplier circuit 10, and a second absolute value circuit 11. And a PWM comparator 12 and a sawtooth wave oscillator 14. Further, the step-up PFC control device 100 illustrated in FIG. 1 includes a differential amplifier 17, a reference voltage source 18, a first error amplifier 19, a comparator 20, and a first absolute value circuit 21.
  • the AC / DC converter unit 30 has a function of rectifying and boosting the AC voltage input from the input AC power supply 1.
  • the AC / DC converter unit 30 includes a boosting coil 4, a smoothing capacitor 7, AC switches S 1 to S 4, four pre-drive circuits 51, three power supplies 52, and a drive logic circuit 53.
  • the block configuration excluding the AC / DC converter unit 30 is the same as the block configuration of the conventional step-up PFC control device 500 shown in FIG. Therefore, in the description of the embodiment of the present invention, the AC / DC converter unit 30 will be mainly described.
  • the silicon-based semiconductor switching elements T1 and T2 shown in FIG. 13 are replaced with AC switches S1 and S2, which are bidirectional switching elements, respectively. Further, the diodes D1 and D2 shown in FIG. 13 are replaced with AC switches S3 and S4 using bidirectional switching elements.
  • AC switches S1 to S4 are bridge-connected as follows.
  • the input side electrode which is the first electrode of the boosting coil 4
  • the drain terminal of the AC switch S1 and the drain terminal of the AC switch S3 are connected to the first electrode of the smoothing capacitor 7.
  • the source terminal of the AC switch S2 and the source terminal of the AC switch S4 are connected to the ground electrode that is the second electrode of the smoothing capacitor 7. Further, the source terminal of the AC switch S1 and the drain terminal of the AC switch S2 are connected to the output side electrode that is the second electrode of the boosting coil 4.
  • the source terminal of the AC switch S3 and the drain terminal of the AC switch S4 are connected to the second AC terminal of the input AC power supply 1 to which the input AC voltage is applied.
  • the gate terminals of the AC switches S1 to S4 are connected to the respective predrive circuits 51 that shift the level of the control signal output from the drive logic circuit 53.
  • the boosting coil 4 stores magnetic energy corresponding to a bidirectional current that flows when a single-phase input AC voltage is applied by the input AC power source 1.
  • the smoothing capacitor 7 stores a charge corresponding to the magnetic energy stored in the boosting coil 4.
  • the bidirectional switching element is a bidirectional switching element having the IV characteristics shown in FIGS. 2A, 2B, and 2C. This characteristic will be described below.
  • FIG. 2A is an IV characteristic diagram showing an FET (Field Effect Transistor) characteristic of the bidirectional switching element used in the present invention.
  • FIG. 2B is an IV characteristic diagram showing the reverse FET characteristic of the bidirectional switching element used in the present invention.
  • FIG. 2C is an IV characteristic diagram showing reverse conduction characteristics of the bidirectional switching element used in the present invention.
  • the bidirectional switching element has a gate terminal, a drain terminal, and a source terminal.
  • the gate / source voltage Vgs is higher than the threshold voltage Vth, the current Ids from the drain terminal to the source terminal or from the source terminal to the drain terminal depending on the polarity of the differential voltage Vds between the drain terminal and the source terminal. Can flow.
  • the gate / source voltage Vgs is a differential voltage of the gate terminal voltage with respect to the source terminal voltage.
  • the current Ids is a positive value when flowing from the drain terminal to the source terminal.
  • the IV characteristic has a triode region and a saturation region like the IV characteristic of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • the triode region is a region in the vicinity of zero voltage until Vds reaches a certain voltage value from zero voltage, and the saturation region is a characteristic similar to a constant current characteristic in which Ids does not change much even if Vds changes. It is an area
  • the IV characteristic has linearity, and the slope of Vds with respect to Ids can be defined as the on-resistance Ron of the switching element.
  • the on-resistance Ron in the triode region is sufficiently smaller than the on-resistance in the saturation region.
  • the characteristics of the bidirectional switching element in the triode region are important as the operation characteristics of the AC switches S1 to S4. In the following description, the characteristics of the triode region are limited.
  • FIG. 2A is an IV characteristic diagram when the differential voltage Vds is positive, that is, when the drain voltage is higher than the source voltage. As can be seen from the IV characteristic diagram, the current Ids has a positive value, and the current flows from the drain terminal to the source terminal.
  • the IV characteristics shown in FIG. 2A will be referred to as FET characteristics.
  • FIG. 2B is an IV characteristic diagram when the differential voltage Vds is negative, that is, when the drain voltage is lower than the source voltage. As can be seen from the IV characteristic diagram, the current Ids has a negative value, and the current flows from the source terminal to the drain terminal.
  • the IV characteristics shown in FIG. 2B will be referred to as inverse FET characteristics.
  • the bidirectional switching element cannot flow the current Ids from the drain terminal to the source terminal when the gate / source voltage Vgs is lower than the threshold voltage Vth.
  • the bidirectional switching element even when the gate / source voltage Vgs is lower than the threshold voltage Vth, the drain terminal voltage is lower than the gate terminal voltage, and the difference voltage (Vgs ⁇ Vds) is higher than the threshold voltage Vth.
  • a current Ids can flow from the source terminal to the drain terminal.
  • This characteristic is called reverse conduction characteristic.
  • FIG. 2C is an IV characteristic diagram showing the reverse conduction characteristic. As can be seen from FIG.
  • the I ⁇ of the diode whose forward voltage is the threshold voltage Vth with the source terminal as the anode and the drain terminal as the cathode. It is the same as the V characteristic.
  • the bidirectional switching element performs FET operation and reverse FET operation when the gate / source voltage Vgs is equal to or higher than the threshold voltage Vth, and the on-resistance It can be regarded as a resistor having the value Ron.
  • the gate-source voltage Vgs is equal to or lower than the threshold voltage Vth
  • the operation is performed according to the reverse conduction characteristic, and it can be regarded as a diode having the source terminal as an anode and the drain terminal as a cathode.
  • the forward voltage of this diode is (Vth ⁇ Vgs).
  • the bidirectional switching element is equivalently converted as follows.
  • the switching element In the ON operation state of the bidirectional switching element in which the gate / source voltage Vgs is higher than the threshold voltage Vth, the switching element is regarded as a resistance having an ON resistance value Ron.
  • the switching element In the off operation state of the bidirectional switching element in which the gate terminal and the source terminal are short-circuited, the switching element is regarded as a diode having the source terminal as an anode and the drain terminal as a cathode.
  • FIG. 2D is a diagram for explaining equivalent conversion between the FET mode and the reverse FET mode in the on-operation state of the switching element
  • FIG. 2E is a diagram for explaining equivalent conversion in the reverse conduction mode in the off-operation state of the switching element. .
  • FIG. 3A is a circuit block diagram of the drive logic circuit 53 according to the embodiment of the present invention
  • FIG. 3B is an operation timing chart of internal signals of the drive logic circuit 53 according to the embodiment of the present invention.
  • the drive logic circuit 53 when a PWM (Pulse Width Modulation) signal is input, the drive logic circuit 53 outputs an LPWM signal for PWM driving one of the AC switches S1 and S2 and the other of the AC switches S1 and S2.
  • a UPWM signal for PWM driving is generated.
  • the PWM signal is a signal output from the PWM comparator 12 shown in FIG. 1, and is a signal for PWM control of the boosting operation.
  • One of the AC switches S1 and S2 drives the boosting coil 4 for the boosting operation by the LPWM signal, and the other of the AC switches S1 and S2 operates in synchronization with one of the AC switches S1 and S2 by the UPWM signal.
  • the LPWM signal has the same waveform as the PWM signal for PWM control of the boost operation, but is delayed from the PWM signal by a certain delay time DT.
  • the UPWM signal is a signal having a polarity opposite to that of the LPWM signal, and a waveform is generated so that a section in which the UPWM signal and the LPWM signal are simultaneously a low level signal (hereinafter referred to as “Low”) is provided for the delay time DT. ing.
  • a section in which these two signals are Low at the same time is called a dead time. Due to this dead time, as long as the two AC switches S1 and S2 are operating normally, they cannot be in the ON operation state at the same time.
  • the AC switch S1 or S2 operates as a boosting diode in the dead time interval (of course, not only in the dead time interval but also in the interval where the UPWM signal is Low) according to the rules of equivalent conversion described above.
  • the AC switch S1 or S2 operates as a resistor having an on-resistance value Ron in a section where the UPWM signal is a high level signal (hereinafter referred to as “High”).
  • the section in which current flows while the AC switches S1 and S2 are operating as boosting diodes is a very short period of time, which is only the dead time section. Therefore, the power consumption of the AC switches S1 and S2 is very small compared to the switching elements T1 and T2 of the conventional step-up PFC control device.
  • the four output signals G_S1 to G_S4 of the drive logic circuit 53 control the four AC switches S1 to S4.
  • the output signals G_S1 and G_S2 output the LPWM signal or the UPWM signal
  • the output signals G_S3 and G_S4 output the high or low level signal.
  • the DIR signal shown in FIG. 3B becomes a high level signal when the AC output of the input AC power supply 1 applies a positive voltage to the boosting coil 4, and the AC output is for boosting.
  • a negative voltage is applied to the coil 4, it becomes a Low level signal.
  • FIG. 4A is a diagram illustrating a current path of the step-up operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply is positive.
  • FIG. 4B is a diagram illustrating a current path of the boost operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply 1 is negative.
  • the boosting operation described in FIGS. 4A and 4B is realized by the PWM operation of the drive logic circuit 53 shown in FIG. 3A.
  • a current always flows through the smoothing capacitor 7 by the magnetic energy of the boosting coil 4 and the output voltage Vo is boosted regardless of whether the voltage polarity of the input AC power supply 1 is positive or negative. .
  • the DIR signal When the input AC power supply 1 is positive, the DIR signal is at a high level.
  • the AC switch S2 receives the LPWM signal for driving the boosting coil 4, and the AC switch S1 is the UPWM signal. Receive.
  • the AC switch S3 receives a Low level signal, and the AC switch S4 receives a High level signal.
  • the AC switches S1 to S4 receive these signals and enter the operating state shown in FIG. 4A.
  • the LPWM signal is described as a PWM signal for controlling the step-up PWM operation
  • the UPWM signal that is a synchronization signal is described as a PWM signal with a bar that represents an inverted signal of the PWM signal. ing.
  • the AC switch S2 performs a PWM operation to drive the boosting coil 4, and the AC switch S1 is in an operation state in which the PWM operation is inverted.
  • the AC switch S4 functions as a resistor having an on-resistance Ron and allows a current to flow.
  • the AC switch S3 can be regarded as a diode in terms of an equivalent circuit because of an off operation state, but no current flows.
  • the AC switch S1 functions as a boosting diode.
  • the current in the booster coil 4 is smoothed by the magnetic energy stored in the booster coil 4 via the AC switch S1 in the path (b) of FIG. 4A. It flows into the terminal of the capacitor 7 which is not grounded. This is because the AC switch S1 functions as a boosting diode in the dead time period, and the AC switch S1 functions as a resistor having an ON resistance Ron when the AC switch S1 is in the ON operation state.
  • the DIR signal is at a low level. From the timing waveform diagram of FIG. 3B, the movement of the AC switches S2 and S1 compared to the case where the input AC power supply 1 has a positive polarity. It can be seen that the movements of the AC switches S4 and S3 are switched.
  • the AC switch S1 performs a PWM operation to drive the boosting coil 4, and the AC switch S2 is in an operating state in which the PWM operation is inverted.
  • the AC switch S3 functions as a resistor having an on-resistance Ron, and a current flows.
  • the AC switch S4 is in an off operation state and can be regarded as a diode in terms of an equivalent circuit, but no current flows.
  • the aforementioned dead time section is provided in the PWM operation in which the AC switches S1 and S2 are operated in synchronization. Then, the AC switch S2 performs the same operation as the AC switch S1 when the input AC power supply 1 is positive, and the current of the boosting coil 4 is passed through the AC switch S2 through the path (b) of the smoothing capacitor 7. It flows into a terminal that is not grounded.
  • the drive logic circuit 53 switches the current path of the bidirectional current by controlling the on / off states of the AC switches S1 to S4 to accumulate magnetic energy in the boosting coil 4 and charge to the smoothing capacitor 7. Accumulate and alternate.
  • the step-up PFC control device 100 shown in FIG. 1 has a function of rectifying and stepping up the AC voltage of the input AC power supply 1 even though there is no rectifier diode bridge.
  • the hysteresis comparator shown in FIG. 3A detects that almost no current flows.
  • the hysteresis comparator compares the signal Sc obtained by converting the output signal of the current detection element 3 into a positive voltage signal by the second absolute value circuit 11 and the comparison reference voltage VRB, thereby obtaining the current flowing through the boosting coil 4.
  • the AC switch S1 or S2 operates as a resistor having an on-resistance value Ron in response to a high-level gate signal. However, the AC switch S1 or S2 changes to the diode operation by changing the gate signal from the High level to the Low level by the zero current detection operation of the hysteresis comparator.
  • the step-up PFC control apparatus 100 realizes a step-up PFC control apparatus without a diode and without a parasitic diode of a switching element.
  • the conduction loss and the switching loss influenced by the diode and the parasitic diode of the switching element occupy a large proportion of the power loss of the entire device.
  • the power consumption can be greatly reduced while maintaining the conventional rectification and step-up operation by eliminating the diode and the parasitic diode of the switching element.
  • the bidirectional switching element used as an AC switch does not have a parasitic diode, and therefore there is no recovery current due to the parasitic diode.
  • the switching loss of the step-up PFC controller does not increase significantly, and the step-up coil 4 can be made smaller by increasing the switching frequency.
  • the boost type PFC control device included in the boost type PFC control device can use the control unit of the conventional boost type PFC control device as it is, the boost type PFC control device of the present invention is changed from the conventional boost type PFC control device. Replacement is also easy.
  • the switching element described above includes a stacked body formed of a nitride semiconductor layer formed on a semiconductor substrate, a drain terminal and a source terminal formed on the stacked body at intervals, and a drain terminal and a source. And a gate terminal formed between the terminals. This switching element will be described with reference to FIG.
  • FIG. 5 is an example of a cross-sectional view of a bidirectional switching element included in the step-up PFC control device of the present invention.
  • the bidirectional switching element shown in the figure is a normally-off type heterojunction FET made of a nitride semiconductor formed on a semiconductor substrate. Specifically, the switching element is realized by forming a stacked body 203 of semiconductor layers on a silicon substrate 201 via a buffer layer 202.
  • the buffer layer 202 is formed by alternately stacking aluminum nitride and gallium nitride.
  • an n-type aluminum gallium nitride layer 205 is formed on an undoped gallium nitride layer 204, and an FET having a high carrier concentration called a two-dimensional electron gas is located in the vicinity of the heterointerface between the two layers. Channel regions are generated.
  • a source terminal ohmic electrode 206a, a drain terminal ohmic electrode 206b, and a wiring 210, which are in ohmic contact with the channel region, are arranged.
  • a control layer 209 which is a p-type semiconductor layer for controlling FET characteristics, is formed on the n-type aluminum gallium nitride layer 205.
  • a protective film 207 for protecting each part is formed so as to cover each part.
  • a gate electrode 208 is formed on the control layer 209 and is in ohmic contact with the control layer 209.
  • the electric signal supplied to the gate electrode 208 controls the current flowing between the drain terminal and the source terminal of the normally-off type heterojunction FET, that is, the bidirectional switching element.
  • the distance from the drain terminal ohmic electrode 206b to the gate electrode 208 is longer than the distance from the source terminal ohmic electrode 206a to the gate electrode 208 because the withstand voltage between the drain terminal and the gate terminal is higher than the source terminal. This is because it is required to be larger than the breakdown voltage between the gate terminals.
  • the bidirectional switching element formed as shown in FIG. 5 is called a GaN transistor, and is a device that can be driven with a high voltage and a large current, such as an IGBT (Insulated Gate Bipolar Transistor).
  • the switching element does not have an offset voltage due to the PN junction in the current-voltage characteristics of the IGBT, and has a characteristic of flowing a current to both as shown in FIGS. 2A and 2B.
  • the switching element has a very small on-resistance component Ron with respect to the chip area of the device.
  • the GaN transistor also has the reverse conduction characteristics shown in FIG. 2C.
  • the GaN transistor has almost no accumulation effect due to minority carriers, and almost no tail current effect during turn-off as in IGBTs and other silicon-based semiconductor elements.
  • the AC / DC converter unit 30 is composed of an AC switch using a GaN transistor as a bidirectional switching element. Therefore, the AC / DC converter unit 30 can greatly reduce power consumption by reducing conduction loss due to its very small on-resistance value Ron and reducing switching loss due to almost no minority carrier accumulation effect.
  • the apparatus can be miniaturized.
  • FIG. 6 is a circuit block diagram of the step-up PFC control apparatus according to the first modification of the embodiment of the present invention.
  • the step-up PFC control device 150 shown in the figure is different from the step-up PFC control device 100 shown in FIG. 1 in the configuration of a part of the AC switch of the AC / DC converter unit 31.
  • the description of the same points as the step-up PFC control apparatus 100 described in FIG. 1 will be omitted, and only different points will be described.
  • AC switches S2 and S4 are each composed of two bidirectional switching elements whose drain terminals are connected in series. With this configuration, it is possible to increase the withstand voltage of the AC switch, and it is possible to realize a step-up PFC control device with a higher input withstand voltage. Further, in the step-up type PFC control device 150, the output side can be disconnected from the input AC power supply 1 of the step-up type PFC control device 150 by giving a low level signal to the illustrated off signal (OFF).
  • FIG. 7A is an equivalent circuit diagram showing the state of the AC switch according to the first modification of the embodiment when the voltage polarity of the input AC power supply is positive.
  • FIG. 7B is an equivalent circuit diagram showing the state of the AC switch according to the first modification of the embodiment when the voltage polarity of the input AC power supply is negative. 7A and 7B, the PWM signal that is the output of the PWM comparator 12 is at the low level, and the off signal is also at the low level.
  • each of the AC switches S2 and S4 is constituted by a series connection of two bidirectional switching elements.
  • two bidirectional switching elements connected in series may be applied to the AC switches S1 and S3, and the AC switches S2 and S4 may be normal AC switches.
  • the AC switches S2 and S4 have a configuration in which the drain terminals of the two switching elements are connected to each other, but may be connected in series with the source terminals connected to each other.
  • FIG. 8A is a circuit block diagram of a drive logic circuit 63 according to a second modification of the embodiment of the present invention
  • FIG. 8B illustrates a drive logic circuit 63 according to the second modification of the embodiment of the present invention. It is an operation
  • the drive logic circuit 63 illustrated in FIG. 8A When the PWM signal is input, the drive logic circuit 63 illustrated in FIG. 8A generates an LPWM signal for PWM driving one of the AC switches S2 and S4, and PWM driving one of the AC switches S1 and S3.
  • the PWM signal is a signal output from the PWM comparator 12 shown in FIG. 1, and is a signal for PWM control of the boosting operation.
  • One of the AC switches S2 and S4 drives the boosting coil 4 for the boosting operation by the LPWM signal, and one of the AC switches S1 and S3 operates in synchronization with one of the AC switches S2 and S4 by the UPWM signal.
  • the relationship between the PWM signal, the UPWM signal, and the LPWM signal is the same as the relationship described in FIG. 3B.
  • a section in which these two signals are Low at the same time is called a dead time. Due to the dead time when the UPWM signal and the LPWM signal are simultaneously Low, as long as the two AC switches S1 and S2 or the AC switches S3 and S4 are operating normally, they cannot be in the ON operation state at the same time. .
  • the AC switch S3 or S4 that performs switching operation with the UPWM signal is boosted in the dead time interval (of course, not only in the dead time interval but also in the interval in which the UPWM signal is Low) according to the rules of equivalent conversion described above. Operates as a diode. Further, in a section where the UPWM signal is High, the AC switch S3 or S4 operates as a resistor having an on-resistance value Ron.
  • the period during which the current flows while the AC switches S1 and S3 are operating as boosting diodes is a very short period of only the dead time period. Therefore, the power consumption of the AC switches S1 and S3 is very small compared to the switching elements T3 and T4 of the conventional step-up PFC control device.
  • the output signals G_S1 to G_S4 control the AC switches S1 to S4, respectively.
  • the output signals G_S2 and G_S4 output an LPWM signal or a high level signal
  • the output signals G_S1 and G_S3 output a UPWM signal or a low level signal.
  • the DIR signal shown in FIG. 8B becomes a high level signal when the AC output of the input AC power supply 1 applies a positive voltage to the boosting coil 4.
  • the DIR signal is a Low level signal when the AC output of the input AC power supply 1 applies a negative voltage to the boosting coil 4.
  • FIG. 9A is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit when the voltage polarity of the input AC power supply is positive.
  • FIG. 9B is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit when the voltage polarity of the input AC power supply is negative.
  • the boosting operation described in FIGS. 9A and 9B is realized by the PWM operation of the drive logic circuit 63 shown in FIG. 8A.
  • a current always flows through the smoothing capacitor 7 by the magnetic energy of the boosting coil 4 and the output voltage Vo is boosted regardless of whether the voltage polarity of the input AC power supply 1 is positive or negative. .
  • the DIR signal When the input AC power supply 1 is positive, the DIR signal is at a high level.
  • the AC switch S2 receives the LPWM signal for driving the boosting coil 4, and the AC switch S1 is the UPWM signal. Receive.
  • the AC switch S3 receives a Low level signal, and the AC switch S4 receives a High level signal.
  • the AC switches S1 to S4 receive these signals and enter the operating state shown in FIG. 9A.
  • the LPWM signal is described as a PWM signal for controlling the step-up PWM operation
  • the UPWM signal that is a synchronization signal is described as a PWM signal with a bar that represents an inverted signal of the PWM signal. ing.
  • the AC switch S2 performs a PWM operation to drive the boosting coil 4, and the AC switch S1 is in an operation state in which the PWM operation is inverted.
  • the AC switch S4 functions as a resistor having an on-resistance Ron and allows a current to flow.
  • the AC switch S3 can be regarded as a diode in terms of an equivalent circuit because of an off operation state, but no current flows.
  • the DIR signal is at a low level. From the timing waveform diagram of FIG. 8B, the movement of the AC switches S2 and S4 compared to the case where the input AC power supply 1 has a positive polarity. It can be seen that the AC switches S1 and S3 are switched.
  • the AC switch S4 performs a PWM operation to drive the boosting coil 4, and the AC switch S3 is in an operating state in which the PWM operation is inverted.
  • the AC switch S2 passes a current as a resistor having an ON resistance Ron, and the AC switch S1 is in an OFF operation state, and can be regarded as a diode in terms of an equivalent circuit, but no current flows.
  • a current for exciting the boosting coil 4 flows through the path (a) in FIG. 9B.
  • the AC switch S4 is in the OFF operation state by the PWM operation, the current flows through the AC switch S3 in the path (b) of FIG. 9B due to the magnetic energy stored in the boosting coil 4. Then, the current is charged from the terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the step-up PFC control device 200 is stepped up.
  • the aforementioned dead time interval is provided in the PWM operation in which the AC switches S4 and S3 are operated synchronously. Then, the AC switch S3 performs the same operation as the AC switch S1 when the input AC power supply 1 is positive, and the current of the boosting coil 4 is passed through the AC switch S3 through the path (b) of the smoothing capacitor 7. It flows into a terminal that is not grounded.
  • the hysteresis comparator shown in FIG. 8A detects that almost no current flows.
  • the hysteresis comparator compares the signal Sc obtained by converting the output signal of the current detection element 3 into a positive voltage signal by the second absolute value circuit 11 and the comparison reference voltage VRB, thereby obtaining the current flowing through the boosting coil 4.
  • the AC switch S1 or S3 is operated synchronously with the UPWM signal with respect to the AC switch S2 or S4 that switches the boosting coil 4 with the LPWM signal.
  • the AC switch S1 or S3 has its gate signal changed to Low level by the zero current detection operation of the hysteresis comparator, and changes to diode operation.
  • the drive logic circuit 63 realizes a step-up PFC control device without a diode and without a parasitic diode of a switching element.
  • FIG. 10 is a circuit block diagram of a boost type PFC control device according to a comparative example.
  • the step-up type PFC control device 300 shown in the figure is a step-up type PFC circuit without a rectifier diode bridge.
  • a step-up PFC control apparatus 300 includes a pair of switching elements T3 and T4 and a high-frequency block filter 502 included in the step-up PFC control apparatus 500 of Patent Document 1 described in FIG. Excluded.
  • the pair of switching elements T3 and T4 is a mechanism for performing the switching operation twice while shifting the phase by 180 degrees for the boosting operation.
  • the pair of switching elements T1 and T2 that perform the switching operation included in the step-up PFC control device 500 are replaced with silicon-based semiconductor switching elements T5 and T6 such as an n-type MOSFET.
  • a pre-drive circuit 51 having a level shift function for driving the switching elements T5 and T6 and a power source 52 are added.
  • the first error amplifier 19 generates an error voltage Ve that is proportional to the difference between the output voltage Vo of the step-up PFC controller 300 and the voltage value Vref of the reference voltage source 18 that sets the output voltage.
  • a voltage signal Vina having a waveform similar to a voltage obtained by full-wave rectifying the AC voltage of the input AC power supply 1 is generated by the differential amplifier 17 and the first absolute value circuit 21.
  • the multiplier circuit 10 multiplies the error voltage Ve and the voltage signal Vina to generate a voltage signal Iref that becomes a current control command value.
  • the voltage signal Iref is proportional to the error voltage Ve and has the same pulsation waveform as Vina that is similar to the voltage waveform obtained by full-wave rectifying the AC voltage of the input AC power supply 1.
  • the current flowing from the input AC power source 1 to the boosting coil 4 by the switching operation of the switching elements T5 and T6 is detected by the current detection element 3, and converted to a positive voltage value signal by the second absolute value circuit 11. It is converted to a current-shaped waveform waveform Sc.
  • Second error amplifier 9 PWM comparator 12, sawtooth oscillator 14, switching element T5 or T6, boosting coil 4, diode D1 or D2, smoothing capacitor 7, output load 8, current detection element 3, and second absolute value
  • the circuit 11 forms a current control negative feedback loop.
  • the current waveform signal Sc is controlled to follow the voltage signal Iref by this current control negative feedback loop, and has substantially the same value as the voltage signal Iref.
  • the voltage signal Iref is a pulsation waveform similar to a voltage waveform obtained by full-wave rectification of the AC voltage of the input AC power supply 1. Therefore, the fact that the current waveform signal Sc follows the voltage signal Iref means that the AC voltage of the input AC power supply 1 and the AC current of the input AC power supply 1 have substantially the same phase and substantially the same waveform. Therefore, the power factor of the input AC power supply is approximately 1.
  • the error voltage Ve is a voltage obtained by amplifying the difference between the output voltage Vo and the voltage value Vref by the first error amplifier 19.
  • the error voltage Ve that is the output of the first error amplifier 19 is controlled to be a finite value by the PFC control loop including the first error amplifier 19, the multiplier circuit 10, and the above-described current control negative feedback loop. .
  • the error voltage Ve is described by the following equation, where A is the gain of the first error amplifier 19.
  • the output voltage Vo maintains the desired voltage set by the voltage value Vref of the reference voltage, and the power factor of the input AC power supply.
  • a step-up AC / DC converter with a high input power factor capable of reducing the power to approximately 1 is realized.
  • the differential amplifier 17, the comparator 20, the NOT logic circuit 13, the two AND logic circuits 16, the switching elements T5 and T6, and the diodes D1 and D2 realize a rectified boost switching operation without using a rectifier diode bridge. .
  • this point will be described.
  • the comparator 20 compares the output signal of the differential amplifier 17 to determine the polarity of the AC voltage of the input AC power supply 1 (the polarity of the AC voltage of the input AC power supply 1 is input to the boosting coil 4). When the AC power supply 1 applies a positive voltage, the polarity is positive). If the polarity of the alternating voltage is positive, the output signal of the comparator 20 is at a high level, and if the polarity of the alternating voltage is negative, the output is low.
  • the NOT logic circuit 13 and the two AND logic circuits 16 receive the output signal of the comparator 20 and control the switching elements T5 and T6. Specifically, if the polarity of the input AC voltage is positive, the NOT logic circuit 13 and the two AND logic circuits 16 are connected to the switching element T6 by the PWM signal output from the PWM comparator 12 for the boosting switching operation. PWM drive. Then, the NOT logic circuit 13 and the two AND logic circuits 16 set the gate voltage of the switching element T5 to the Low level to turn off the switching element T5. On the other hand, if the polarity of the input AC voltage is negative, the NOT logic circuit 13 and the two AND logic circuits 16 PWM drive the switching element T5 with a PWM signal. Then, the NOT logic circuit 13 and the two AND logic circuits 16 set the gate voltage of the switching element T6 to the Low level to turn off the switching element T6.
  • FIG. 11A is an equivalent circuit diagram showing the state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive.
  • FIG. 11B is an equivalent circuit diagram illustrating a state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative. That is, FIG. 11A and FIG. 11B show which is different depending on the PWM operation by the operation of the comparator 20, the NOT logic circuit 13, and the two AND logic circuits 16, depending on whether the voltage polarity of the input AC power supply 1 is positive or negative. It is a figure explaining how voltage
  • a current for exciting the boosting coil 4 flows through the path (a) in FIG. 11A. Further, when the switching element T6 is turned off by the PWM operation, a current flows by the magnetic energy stored in the boosting coil 4 through the path (b) of FIG. 11A. Then, a current is charged from a terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the boost PFC control device 300 is boosted. Since the switching elements T5 and T6 are silicon semiconductor switching elements such as n-type MOSFETs, there are parasitic diodes between the source terminal and the drain terminal as shown in FIG. Therefore, as shown in FIG. 11A, the current generated by the magnetic energy of the boosting coil 4 in the path (b) flows via the parasitic diode of the switching element T5.
  • the boost type PFC control device 300 according to the comparative example has the following two problems.
  • the problem (1) regarding the forward voltage VF of the diode and the forward voltage VFP of the parasitic diode will be described.
  • the forward voltage VF of the diode D2 is generated when a current flows through the path (a) in FIG. 11A.
  • a current flows through the path (b) in FIG. 11A a voltage drop due to the forward voltage VFP of the switching element T5 in the off operation state occurs in addition to the forward voltage VF of the diode D2.
  • Power consumption that is, loss occurs in the diode D2 and the switching element T5 due to these voltage drops and the current flowing through these diodes.
  • the forward voltage VF of the diode D1 is generated when a current flows through the path (a) in FIG. 11B. Further, when a current flows through the path (b) in FIG. 11B, a voltage drop due to the forward voltage VF of the diode D1 and the forward voltage VFP of the switching element T6 occurs, and loss occurs in the diode D1 and the switching element T6. To do.
  • the power consumption of the element due to the constant flow of current is called conduction loss.
  • the conduction loss when the current flows while the switching element T5 or T6 is in the on-operation state is very small compared to the conduction loss due to the voltage drop of the forward voltage VF or VFP of the diode because the on-resistance is small. Therefore, as can be seen from the current paths shown in FIGS. 11A and 11B, it can be seen that most of the conduction loss of the conventional boost type PFC control device is due to the forward voltages VF and VFP of the diode.
  • the conduction loss of the boost type PFC control device 300 can be greatly reduced.
  • the anode of the parasitic diode existing between the source terminal and the drain terminal of the switching elements T5 and T6 is at the source of the switching element, and the cathode of the parasitic diode is at the drain of the switching element.
  • FIG. 11A when the switching element T5 is in the OFF operation state, when a current flows through the path (b), a current flows from the anode to the cathode of the parasitic diode.
  • FIG. 11B when the switching element T6 is in the OFF operation state, when a current flows through the path (b), a current flows from the anode to the cathode of the parasitic diode.
  • the recovery current component due to the minority carrier accumulation effect in the diode is generated in the parasitic diode. That is, when the current starts to flow from the path (b) state to the path (a) state, the recovery current of the parasitic diode is also driven.
  • the path (b) is a state in which one of the switching elements T5 and T6 is in an off operation state and a current flows through the parasitic diode.
  • the other of the switching elements T5 and T6 is turned on to become the path (a), not only the current for driving the boosting coil 4 but also the unnecessary parasitic diode recovery current is generated by the turn-on operation. To drive.
  • FIG. 12A is a diagram illustrating the transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive.
  • FIG. 12B is a diagram illustrating transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative.
  • the current Ids (T6) flowing through the switching element T6 includes a drive current of the boosting coil 4 as indicated by a region R1 by a turn-on operation that is a change from the state (b) to the state (a).
  • the recovery current of the parasitic diode of the switching element T5 is superimposed.
  • the current Ids (T5) flowing through the switching element T5 is changed to the current Ids (T5) flowing from the state (b) to the state (a) as shown in the region R2, as shown in FIG.
  • the recovery current of the parasitic diode of the switching element T6 is superimposed.
  • the recovery current is a large one that cannot be ignored and affects the increase in switching loss, which means power consumption during switching operation of the switching element.
  • This switching loss increases in proportion to the switching frequency of the step-up PFC control device. Therefore, increasing the switching frequency for the purpose of reducing the size of the boosting coil 4 causes an increase in switching loss of the switching element. That is, it is difficult for the boost type PFC control apparatus 300 according to this comparative example to downsize the boost coil in the future.
  • a considerably large switching loss is generated, so that it is not suitable as a step-up PFC control device in the current continuous mode.
  • Appropriate conditions for using this boosting method must be based on the premise of so-called soft switching in which the switching element performs switching operation when no current flows. That is, in this boosting method, there is a limitation on the PFC control method.
  • the parasitic diode of the switching element is not only involved in the increase in power consumption due to the forward voltage VF of the parasitic diode itself, but also the different switching element. It also has a problem of affecting the switching loss.
  • the step-up PFC control device includes an AC / DC converter unit that rectifies and boosts an input single-phase AC voltage. Furthermore, the AC / DC converter unit includes a plurality of AC switch units that are bridge-connected, a boosting coil, a smoothing capacitor, and a drive logic circuit.
  • the boosting coil stores magnetic energy corresponding to the bidirectional current that flows in response to the application of the single-phase AC voltage.
  • the smoothing capacitor stores a charge corresponding to the magnetic energy stored in the boosting coil.
  • the drive logic circuit switches the current path of bidirectional current by controlling the on / off state of a plurality of AC switch units, and alternately stores magnetic energy in the boosting coil and charges in the smoothing capacitor. Make it.
  • Each of the plurality of AC switch units has a gate terminal, a drain terminal, and a source terminal.
  • the AC switch includes a bidirectional switching element having FET characteristics, reverse FET characteristics, and reverse conduction characteristics. FET characteristics means that when a gate / source voltage, which is a differential voltage of a gate terminal voltage with respect to a source terminal voltage, is higher than a threshold voltage, a current flows from the drain terminal to the source terminal according to the polarity of the drain / source voltage.
  • the reverse FET characteristic is a characteristic that allows a current to flow from the source terminal to the drain terminal according to the polarity of the drain / source voltage when the gate / source voltage is higher than the threshold voltage.
  • Reverse conduction characteristics means that when the gate-source voltage is less than or equal to the threshold voltage, the current from the drain terminal to the source terminal is cut off, but when the gate terminal voltage exceeds the threshold voltage with respect to the drain terminal voltage, the source terminal The current can flow from the drain terminal to the drain terminal.
  • the boosting PFC control unit for controlling the bidirectional current path can use the boosting PFC control unit of the conventional boosting PFC control device as it is, and the control operation as the boosting PFC control device is conventional. Is almost the same.
  • the drive logic circuit receives a control signal from a hysteresis comparator that detects that there is no current when the current flowing between the AC / DC converter unit and the input AC power supply is substantially zero. Then, control is performed so that the gate / source voltage of at least one of the plurality of AC switch units is equal to or lower than the threshold voltage.
  • At least two of the AC switch units are two bidirectional switching elements in which source terminals or drain terminals are connected in series. Composed.
  • step-up PFC control device like the step-up PFC control device described above, it is possible to reduce power consumption while maintaining the rectification step-up operation of the conventional step-up type PFC control device. Furthermore, a step-up PFC control device having high input voltage resistance can be realized. In addition, the step-up PFC control device can completely disconnect the load connected between the output terminal and the GND terminal of the PFC control device from the input AC voltage source.
  • the bidirectional switching element is formed on a stacked body including a nitride semiconductor layer formed on a semiconductor substrate, and on the stacked body. And a drain terminal and a source terminal formed on both sides of the gate terminal.
  • the bidirectional switching element is generally known as a heterojunction field effect transistor using a gallium nitride semiconductor and is called a GaN transistor.
  • a GaN transistor has FET characteristics and reverse FET characteristics when the gate / source voltage is higher than a certain threshold voltage, and has reverse conduction characteristics when the gate / source voltage is equal to or lower than the threshold voltage.
  • the GaN transistor also serves as a bidirectional switching element having high breakdown voltage characteristics, and is also an FET transistor having a very low on-resistance value in FET characteristics and reverse FET characteristics. Further, there is no minority carrier effect as in a silicon-based semiconductor element, and there is almost no influence of an increase in switching loss due to a recovery current. Therefore, by using a GaN transistor as a bidirectional switching element included in the step-up PFC control device of the present invention, a step-down PFC control device with lower power consumption can be realized.
  • the boost type PFC control device of the present invention has been described based on the embodiment, the boost type PFC control device according to the present invention is not limited to the above embodiment and its modifications. Another embodiment realized by combining arbitrary constituent elements in the embodiment and its modifications is also included in the present invention. Furthermore, the present invention also includes modifications obtained by making various modifications conceivable by those skilled in the art without departing from the spirit of the present invention to the embodiments and modifications thereof. Furthermore, various devices incorporating the boost type PFC control device according to the present invention are also included in the present invention.
  • the present invention can be applied to an AC / DC converter that outputs a DC voltage from an AC input, and is particularly useful as an AC / DC converter having a high-input power factor and high-efficiency step-up PFC controller that does not require a rectifier diode bridge. It is.

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Abstract

In this boost PFC control device (100), which rectifies and boosts a single-phase AC voltage, an AC/DC converter (30) is provided with: a plurality of AC switches (S1-S4); and a drive logic circuit (53) that alternatingly performs charge storage to a smoothing capacitor (7) and magnetic energy storage to a boost coil (4) by means of controlling the on/off state of the AC switches (S1-S4). When a gate-source voltage is greater than a threshold voltage, the AC switches (S1-S4) flow current between a drain and a source, and when the gate-source voltage is at or below the threshold voltage and the gate voltage with respect to a drain voltage is at least the threshold voltage, the AC switches (S1-S4) flow current from the source to the drain.

Description

昇圧型ＰＦＣ制御装置Boost PFC controller
　本発明は、入力交流電圧を整流して交流電圧のピーク値より大きい直流電圧を出力する高入力力率で高効率の昇圧型ＰＦＣ（Ｐｏｗｅｒ　Ｆａｃｔｏｒ　Ｃｏｒｒｅｃｔｉｏｎ）制御装置に関する。 The present invention relates to a high-input power factor and high-efficiency step-up PFC (Power Factor Correction) controller that rectifies an input AC voltage and outputs a DC voltage larger than the peak value of the AC voltage.
　図１３は、特許文献１に記載された、整流ダイオードブリッジのない昇圧型ＰＦＣ制御装置の回路ブロック図である。図１３に記載された整流ダイオードブリッジの無い昇圧型ＰＦＣ制御装置５００は、高域阻止フィルタ５０２の小型化及び低コスト化を目的としたものである。 FIG. 13 is a circuit block diagram of a step-up PFC control device without a rectifier diode bridge described in Patent Document 1. The step-up PFC control device 500 without a rectifier diode bridge described in FIG. 13 is intended to reduce the size and cost of the high-frequency block filter 502.
　この目的の実現の為に、位相が互いに１８０度異なる２つののこぎり波発振器５１４及び５１５を用いて、昇圧のためのスイッチング動作の位相を１８０度ずらして２回行うこととしている。つまり、スイッチング素子Ｔ１及びＴ２による第１のスイッチング動作と、スイッチング素子Ｔ３及びＴ４による第２のスイッチング動作である。その結果、高域阻止フィルタ５０２に流れる電流のリップルは、スイッチング周波数に比べ、２倍高調波を有するものとなる。これにより、高域阻止フィルタ５０２を小型化及び低コスト化できるとしている。 In order to realize this object, two sawtooth wave oscillators 514 and 515 having phases different from each other by 180 degrees are used, and the phase of the switching operation for boosting is shifted twice by 180 degrees. That is, the first switching operation by the switching elements T1 and T2 and the second switching operation by the switching elements T3 and T4. As a result, the ripple of the current flowing through the high-frequency blocking filter 502 has a second harmonic compared with the switching frequency. As a result, the high-frequency blocking filter 502 can be reduced in size and cost.
特開２００８-１２５３１０号公報JP 2008-125310 A
　しかしながら、前述した従来の昇圧型ＰＦＣ制御装置５００は、ダイオードＤ１またはＤ２の順方向電圧ＶＦとシリコン系半導体からなるスイッチング素子Ｔ１～Ｔ４の寄生ダイオードの順方向電圧ＶＦＰとによる電圧降下による損失が発生するという課題を有している。 However, the above-described conventional step-up PFC control device 500 generates a loss due to a voltage drop due to the forward voltage VF of the diode D1 or D2 and the forward voltage VFP of the parasitic diode of the switching elements T1 to T4 made of silicon semiconductor. Have the problem of doing.
　さらに、シリコン系半導体からなるスイッチング素子Ｔ１～Ｔ４の寄生ダイオードのリカバリー電流により、スイッチング素子Ｔ１～Ｔ４のターンオン動作時のスイッチング損失が大きいという課題を有している。また、スイッチング損失はＰＦＣ制御装置のスイッチング周波数に比例して増大する。その為、磁気誘導手段５０４のサイズを小さくする為にスイッチング周波数を上げることは、スイッチング損失の増大を招く。 Furthermore, there is a problem that the switching loss during the turn-on operation of the switching elements T1 to T4 is large due to the recovery current of the parasitic diodes of the switching elements T1 to T4 made of silicon-based semiconductor. Further, the switching loss increases in proportion to the switching frequency of the PFC control device. Therefore, increasing the switching frequency in order to reduce the size of the magnetic induction means 504 causes an increase in switching loss.
　本発明は、ＰＦＣ制御装置内の消費電力の大部分を占めるスイッチング素子の寄生ダイオードとダイオードＤ１及びＤ２を無くして低消費電力化及び小型化を実現する昇圧型ＰＦＣ制御装置を提供する。 The present invention provides a step-up PFC control device that realizes low power consumption and miniaturization by eliminating the parasitic diodes of the switching elements and the diodes D1 and D2 that occupy most of the power consumption in the PFC control device.
　本発明の一態様に係る昇圧型ＰＦＣ制御装置は、入力された単相交流電圧を整流して昇圧するＡＣ／ＤＣコンバータ部を備える昇圧型ＰＦＣ制御装置である。ＡＣ／ＤＣコンバータ部は、ブリッジ接続された複数の交流スイッチ部と、昇圧用コイルと、平滑用コンデンサと、ドライブロジック回路とを有する。昇圧用コイルは、単相交流電圧の印加に応じて流れる双方向電流に応じた磁気エネルギーを蓄える。平滑用コンデンサは、昇圧用コイルと、昇圧用コイルに蓄えられた磁気エネルギーに対応した電荷を蓄える。ドライブロジック回路は、複数の交流スイッチ部のオンオフ状態を制御することにより双方向電流の電流径路を切り換えて、昇圧用コイルへの磁気エネルギーの蓄積と平滑用コンデンサへの電荷蓄積とを交互に行わせる。複数の交流スイッチ部の各々は、ゲート端子とドレイン端子とソース端子とを有する。交流スイッチ部は、ＦＥＴ特性と、逆ＦＥＴ特性と、逆導通特性とを有する、スイッチング素子で構成される。ＦＥＴ特性とは、ソース電圧に対するゲート電圧であるゲート－ソース間電圧が閾値電圧より高い場合に、ドレイン－ソース間電圧の極性に応じてドレイン端子からソース端子へ電流を流す特性である。また、逆ＦＥＴ特性とは、ゲート－ソース間電圧が閾値電圧より高い場合に、ドレイン－ソース間電圧の極性に応じてソース端子からドレイン端子へ電流を流す特性である。逆導通特性とは、ゲート－ソース間電圧が閾値電圧と同じかそれより低い（以降。「以下」と記す）場合に、ドレイン端子からソース端子に流れる電流を遮断し、ドレイン電圧に対するゲート電圧が閾値電圧と同じかそれより高く（以降、「以上」と記す）なるとソース端子からドレイン端子へ電流を流す特性である。 A step-up PFC control device according to an aspect of the present invention is a step-up PFC control device including an AC / DC converter unit that rectifies and boosts an input single-phase AC voltage. The AC / DC converter unit includes a plurality of AC switch units that are bridge-connected, a boosting coil, a smoothing capacitor, and a drive logic circuit. The boosting coil stores magnetic energy corresponding to the bidirectional current that flows in response to the application of the single-phase AC voltage. The smoothing capacitor stores a boosting coil and a charge corresponding to the magnetic energy stored in the boosting coil. The drive logic circuit switches the current path of bidirectional current by controlling the on / off state of a plurality of AC switch units, and alternately stores magnetic energy in the boosting coil and charges in the smoothing capacitor. Make it. Each of the plurality of AC switch units has a gate terminal, a drain terminal, and a source terminal. The AC switch unit is composed of a switching element having FET characteristics, reverse FET characteristics, and reverse conduction characteristics. The FET characteristic is a characteristic in which current flows from the drain terminal to the source terminal according to the polarity of the drain-source voltage when the gate-source voltage, which is the gate voltage with respect to the source voltage, is higher than the threshold voltage. The reverse FET characteristic is a characteristic in which current flows from the source terminal to the drain terminal according to the polarity of the drain-source voltage when the gate-source voltage is higher than the threshold voltage. Reverse conduction characteristics means that when the gate-source voltage is equal to or lower than the threshold voltage (hereinafter referred to as “below”), the current flowing from the drain terminal to the source terminal is cut off, and the gate voltage relative to the drain voltage is This is a characteristic in which a current flows from the source terminal to the drain terminal when it is equal to or higher than the threshold voltage (hereinafter referred to as “more”).
　上記構成によれば、ＡＣ／ＤＣコンバータ部にダイオードが不要であり、また交流スイッチ部を構成するスイッチング素子には寄生ダイオードも無く、ダイオードの順方向電圧の電圧降下による消費電力を無くすことができる。また、従来には存在した寄生ダイオードのリカバリー電流によるスイッチング損失もなくなるので、大幅に消費電力を削減した昇圧型ＰＦＣ制御装置が実現できる。 According to the above configuration, no diode is required in the AC / DC converter unit, and there is no parasitic diode in the switching element configuring the AC switch unit, so that power consumption due to a voltage drop in the forward voltage of the diode can be eliminated. . In addition, since there is no switching loss due to the recovery current of the parasitic diode that has existed in the past, a step-up type PFC control device with significantly reduced power consumption can be realized.
　また、本発明の他の態様は、複数の交流スイッチ部は、第１～第４のスイッチング素子を有する。昇圧用コイルの第１の電極は、単相交流電圧が印加される第１交流端子に接続される。第１のスイッチング素子のドレイン端子と第３のスイッチング素子のドレイン端子とは、平滑用コンデンサの第１の電極に接続される。第２のスイッチング素子のソース端子と第４のスイッチング素子のソース端子とは、平滑用コンデンサの第２の電極に接続される。第１のスイッチング素子のソース端子と第２のスイッチング素子のドレイン端子とは、昇圧用コイルの第２の電極に接続される。第３のスイッチング素子のソース端子と第４のスイッチング素子のドレイン端子とは、単相交流電圧が印加される第２交流端子に接続される。第１～第４のスイッチング素子のゲート端子は、ドライブロジック回路から出力される制御信号をレベルシフトする各々のプリドライブ回路に接続される。ドライブロジック回路は、第１のスイッチング素子と第２のスイッチング素子とが同時にオン状態とならないように、または、第３のスイッチング素子と第４のスイッチング素子とが同時にオン状態とならないように制御してもよい。 Further, according to another aspect of the present invention, the plurality of AC switch units have first to fourth switching elements. The first electrode of the boosting coil is connected to a first AC terminal to which a single-phase AC voltage is applied. The drain terminal of the first switching element and the drain terminal of the third switching element are connected to the first electrode of the smoothing capacitor. The source terminal of the second switching element and the source terminal of the fourth switching element are connected to the second electrode of the smoothing capacitor. The source terminal of the first switching element and the drain terminal of the second switching element are connected to the second electrode of the boosting coil. The source terminal of the third switching element and the drain terminal of the fourth switching element are connected to a second AC terminal to which a single-phase AC voltage is applied. The gate terminals of the first to fourth switching elements are connected to the respective predrive circuits that shift the level of the control signal output from the drive logic circuit. The drive logic circuit controls so that the first switching element and the second switching element are not turned on at the same time, or the third switching element and the fourth switching element are not turned on at the same time. May be.
　これによれば、ＡＣ／ＤＣコンバータ部は、４つの双方向スイッチング素子がブリッジ接続された基本的なブリッジ回路で構成される。よって、ＡＣ／ＤＣコンバータ部は、簡潔かつ高効率に双方向電流の電流パスを制御して昇圧することが可能となる。 According to this, the AC / DC converter unit is constituted by a basic bridge circuit in which four bidirectional switching elements are bridge-connected. Therefore, the AC / DC converter unit can control and boost the bidirectional current path simply and with high efficiency.
　また、本発明の他の態様は、ドライブロジック回路は、さらに、単相交流電圧を出力する交流電源とＡＣ／ＤＣコンバータ部との間に流れる電流が零（以降、略零を含む）の場合には、複数の交流スイッチ部のうち少なくとも１つの交流スイッチ部を構成するスイッチング素子のゲート－ソース間電圧が閾値電圧以下になるようにスイッチング素子のゲート信号を制御することが好ましい。 According to another aspect of the present invention, the drive logic circuit further includes a case where the current flowing between the AC power source that outputs a single-phase AC voltage and the AC / DC converter unit is zero (hereinafter, including substantially zero). In this case, it is preferable to control the gate signal of the switching element so that the gate-source voltage of the switching element constituting at least one of the plurality of AC switch parts is equal to or lower than the threshold voltage.
　これにより、昇圧コイルに流れる電流が略零の場合は、昇圧用コイルの磁気エネルギーが無くなっても、昇圧型ＰＦＣ制御装置の出力側から入力交流電源へ電流が逆流しないようにすることが可能となる。 As a result, when the current flowing through the booster coil is substantially zero, it is possible to prevent the current from flowing backward from the output side of the booster type PFC control device to the input AC power supply even when the magnetic energy of the booster coil is lost. Become.
　また、本発明の他の態様は、複数の交流スイッチ部のうち少なくとも２個の交流スイッチ部は、ソース端子同士またはドレイン端子同士が直列接続された２つのスイッチング素子で構成されてもよい。 Further, according to another aspect of the present invention, at least two of the plurality of AC switch units may be configured by two switching elements in which source terminals or drain terminals are connected in series.
　これによれば、上述した昇圧型ＰＦＣ制御装置と同様に、従来の昇圧型ＰＦＣ制御装置の整流昇圧動作を維持しつつ消費電力を低減することができる。さらには、高入力耐圧性を有する昇圧型ＰＦＣ制御装置が実現できる。また、この昇圧型ＰＦＣ制御装置は、入力交流電圧源から、昇圧型ＰＦＣ制御装置の出力端子とＧＮＤ端子との間に接続される負荷を完全に切り離すことも可能である。 According to this, like the step-up PFC control device described above, it is possible to reduce power consumption while maintaining the rectification step-up operation of the conventional step-up type PFC control device. Furthermore, a step-up PFC control device having high input voltage resistance can be realized. In addition, the step-up PFC control device can completely disconnect the load connected between the output terminal and the GND terminal of the step-up PFC control device from the input AC voltage source.
　また、本発明の他の態様は、スイッチング素子は、半導体基板の上に形成された複数の窒化物半導体層からなる積層体と、積層体の上に形成されたゲート端子と、ゲート端子を挟んで両側方に形成されたドレイン端子及びソース端子とを備えることが望ましい。 In another aspect of the present invention, the switching element includes a stacked body formed of a plurality of nitride semiconductor layers formed on a semiconductor substrate, a gate terminal formed on the stacked body, and a gate terminal sandwiched between the gate terminals. It is desirable to provide a drain terminal and a source terminal formed on both sides.
　スイッチング素子は、一般的に、窒化ガリウム半導体を用いたヘテロ接合電界効果トランジスタとして知られていて、ＧａＮトランジスタと呼ばれている。ＧａＮトランジスタは、ゲート／ソース間電圧がある閾値電圧より高い場合にＦＥＴ特性と逆ＦＥＴ特性を有し、且つ、ゲート／ソース間電圧が閾値電圧以下の場合に逆導通特性を有する。また、ＧａＮトランジスタは、高耐圧特性を有する双方向スイッチング素子ともなり、ＦＥＴ特性及び逆ＦＥＴ特性において非常に低いオン抵抗値のＦＥＴトランジスタでもある。オン抵抗とは、スイッチング素子に電流が流れるときのチャンネル部の抵抗のことである。また、シリコン系半導体素子のような少数キャリア効果がなく、リカバリー電流によるスイッチング損失増大の影響もほとんど無い。従って、本発明の昇圧型ＰＦＣ制御装置が有する双方向スイッチング素子としてＧａＮトランジスタを用いることで、より低消費電力の昇圧型ＰＦＣ制御装置が実現できる。また、スイッチング損失の低減によりスイッチング周波数を上げることが可能となり、これにより昇圧用コイルのサイズを小さくでき、結果的に装置の小型化が可能となる。 The switching element is generally known as a heterojunction field effect transistor using a gallium nitride semiconductor and is called a GaN transistor. A GaN transistor has FET characteristics and reverse FET characteristics when the gate / source voltage is higher than a certain threshold voltage, and has reverse conduction characteristics when the gate / source voltage is equal to or lower than the threshold voltage. The GaN transistor also serves as a bidirectional switching element having high breakdown voltage characteristics, and is also an FET transistor having a very low on-resistance value in FET characteristics and reverse FET characteristics. The on-resistance is the resistance of the channel portion when a current flows through the switching element. Further, there is no minority carrier effect as in a silicon-based semiconductor element, and there is almost no influence of an increase in switching loss due to a recovery current. Therefore, by using a GaN transistor as a bidirectional switching element included in the step-up PFC control device of the present invention, a step-down PFC control device with lower power consumption can be realized. In addition, the switching frequency can be increased by reducing the switching loss, whereby the size of the boosting coil can be reduced, and as a result, the device can be reduced in size.
　本発明によれば、ダイオード及びスイッチング素子の寄生ダイオードの無い昇圧型ＰＦＣ制御装置を提供することができる。従来の昇圧型ＰＦＣ制御装置の消費電力は、ダイオード及びスイッチング素子の寄生ダイオードによるものが大きいが、本発明では消費電力を大幅に削減できる。また、昇圧型ＰＦＣ制御装置が有するＰＦＣ制御部は、従来の昇圧型ＰＦＣ制御装置の有する制御部をそのまま用いることができるので、従来の昇圧型ＰＦＣ制御装置から本発明の昇圧型ＰＦＣ制御装置への置き換えが容易である。 According to the present invention, it is possible to provide a step-up PFC control device that does not include a diode and a parasitic diode of a switching element. The power consumption of the conventional boost type PFC control device is largely due to the diode and the parasitic diode of the switching element, but the power consumption can be greatly reduced in the present invention. In addition, since the PFC control unit included in the boost type PFC control device can use the control unit of the conventional boost type PFC control device as it is, the conventional boost type PFC control device changes to the boost type PFC control device of the present invention. Is easy to replace.
図１は、本発明の実施の形態に係る昇圧型ＰＦＣ制御装置の回路ブロック図である。FIG. 1 is a circuit block diagram of a step-up PFC control apparatus according to an embodiment of the present invention. 図２Ａは、本発明に用いる双方向スイッチング素子のＦＥＴ特性を表すＩ－Ｖ特性図である。FIG. 2A is an IV characteristic diagram showing the FET characteristics of the bidirectional switching element used in the present invention. 図２Ｂは、本発明に用いる双方向スイッチング素子の逆ＦＥＴ特性を表すＩ－Ｖ特性図である。FIG. 2B is an IV characteristic diagram showing the reverse FET characteristic of the bidirectional switching element used in the present invention. 図２Ｃは、本発明に用いる双方向スイッチング素子の逆導通特性を表すＩ－Ｖ特性図である。FIG. 2C is an IV characteristic diagram showing reverse conduction characteristics of the bidirectional switching element used in the present invention. 図２Ｄは、スイッチング素子のオン動作状態における等価変換を説明する図である。FIG. 2D is a diagram for explaining equivalent conversion in an on-operation state of the switching element. 図２Ｅは、スイッチング素子のオフ動作状態における等価変換を説明する図である。FIG. 2E is a diagram for explaining equivalent conversion in an OFF operation state of the switching element. 図３Ａは、本発明の実施の形態に係るドライブロジック回路の回路ブロック図である。FIG. 3A is a circuit block diagram of the drive logic circuit according to the embodiment of the present invention. 図３Ｂは、本発明の実施の形態に係るドライブロジック回路の内部信号の動作タイミングチャートである。FIG. 3B is an operation timing chart of internal signals of the drive logic circuit according to the exemplary embodiment of the present invention. 図４Ａは、入力交流電源の電圧極性が正の場合における、実施の形態に係るＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。FIG. 4A is a diagram illustrating a current path of the boost operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply is positive. 図４Ｂは、入力交流電源の電圧極性が負の場合における、実施の形態に係るＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。FIG. 4B is a diagram illustrating a current path of the boost operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply is negative. 図５は、本発明の昇圧型ＰＦＣ制御装置が有する双方向スイッチング素子の断面図である。FIG. 5 is a cross-sectional view of a bidirectional switching element included in the step-up PFC control device of the present invention. 図６は、本発明の実施の形態の第１の変形例に係る昇圧型ＰＦＣ制御装置の回路ブロック図である。FIG. 6 is a circuit block diagram of a step-up PFC control device according to a first modification of the embodiment of the present invention. 図７Ａは、入力交流電源の電圧極性が正の場合における、実施の形態の第１の変形例に係る交流スイッチの状態を表す等価回路図である。FIG. 7A is an equivalent circuit diagram illustrating a state of the AC switch according to the first modification example of the embodiment when the voltage polarity of the input AC power supply is positive. 図７Ｂは、入力交流電源の電圧極性が負の場合における、実施の形態の第１の変形例に係る交流スイッチの状態を表す等価回路図である。FIG. 7B is an equivalent circuit diagram illustrating a state of the AC switch according to the first modification example of the embodiment when the voltage polarity of the input AC power supply is negative. 図８Ａは、本発明の実施の形態の第２の変形例に係るドライブロジック回路の回路ブロック図である。FIG. 8A is a circuit block diagram of a drive logic circuit according to a second modification example of the embodiment of the present invention. 図８Ｂは、本発明の実施の形態の第２の変形例に係るドライブロジック回路の内部信号の動作タイミングチャートである。FIG. 8B is an operation timing chart of internal signals of the drive logic circuit according to the second modification example of the exemplary embodiment of the present invention. 図９Ａは、入力交流電源の電圧極性が正の場合における、実施の形態の第２の変形例に係るＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。FIG. 9A is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit according to the second modification example of the embodiment when the voltage polarity of the input AC power supply is positive. 図９Ｂは、入力交流電源の電圧極性が負の場合における、実施の形態の第２の変形例に係るＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。FIG. 9B is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit according to the second modification example of the embodiment when the voltage polarity of the input AC power supply is negative. 図１０は、比較例に係る昇圧型ＰＦＣ制御装置の回路ブロック図である。FIG. 10 is a circuit block diagram of a boost type PFC control device according to a comparative example. 図１１Ａは、比較例に係る入力交流電源の電圧極性が正の場合におけるスイッチング素子の状態を表す等価回路図である。FIG. 11A is an equivalent circuit diagram illustrating a state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive. 図１１Ｂは、比較例に係る入力交流電源の電圧極性が負の場合におけるスイッチング素子の状態を表す等価回路図である。FIG. 11B is an equivalent circuit diagram illustrating a state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative. 図１２Ａは、比較例に係る入力交流電源の電圧極性が正の場合におけるスイッチング素子の過渡特性を表す図である。FIG. 12A is a diagram illustrating transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive. 図１２Ｂは、比較例に係る入力交流電源の電圧極性が負の場合におけるスイッチング素子の過渡特性を表す図である。FIG. 12B is a diagram illustrating transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative. 図１３は、特許文献１に記載された、整流ダイオードブリッジのない昇圧型ＰＦＣ制御装置の回路ブロック図である。FIG. 13 is a circuit block diagram of a step-up PFC control device described in Patent Document 1 without a rectifier diode bridge.
　以下に、本発明に係る昇圧型ＰＦＣ制御装置について、順次、好適な実施の形態を、添付の図面を参照しつつ詳細に説明する。なお、本発明は、以下の実施の形態に記載した具体的な構成に限定されるものではなく、実施の形態において説明する技術的思想と同様の技術的思想及び当技術分野における技術常識に基づいて構成されるものを含むものである。 Hereinafter, preferred embodiments of the boost PFC control apparatus according to the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the specific configurations described in the following embodiments, and is based on the same technical idea as the technical idea described in the embodiment and the common general technical knowledge in this technical field. Is included.
　（実施の形態）
　図１は、本発明の実施の形態に係る昇圧型ＰＦＣ制御装置の回路ブロック図である。図１に記載された昇圧型ＰＦＣ制御装置１００は、ＡＣ／ＤＣコンバータ部３０と、電流検出素子３と、出力負荷８、第２誤差増幅器９と、乗算回路１０と、第２絶対値回路１１と、ＰＷＭコンパレータ１２と、のこぎり波発振器１４とを有する。さらに、図１に記載された昇圧型ＰＦＣ制御装置１００は、差動増幅器１７と、基準電圧源１８と、第１誤差増幅器１９と、コンパレータ２０と、第１絶対値回路２１とを有する。また、ＡＣ／ＤＣコンバータ部３０は、入力交流電源１から入力された交流電圧を整流して昇圧する機能を有する。ＡＣ／ＤＣコンバータ部３０は、昇圧用コイル４と、平滑用コンデンサ７と、交流スイッチＳ１～Ｓ４と、４つのプリドライブ回路５１と、３つの電源５２と、ドライブロジック回路５３とを有する。 (Embodiment)
FIG. 1 is a circuit block diagram of a step-up PFC control apparatus according to an embodiment of the present invention. A step-up PFC control device 100 shown in FIG. 1 includes an AC / DC converter unit 30, a current detection element 3, an output load 8, a second error amplifier 9, a multiplier circuit 10, and a second absolute value circuit 11. And a PWM comparator 12 and a sawtooth wave oscillator 14. Further, the step-up PFC control device 100 illustrated in FIG. 1 includes a differential amplifier 17, a reference voltage source 18, a first error amplifier 19, a comparator 20, and a first absolute value circuit 21. The AC / DC converter unit 30 has a function of rectifying and boosting the AC voltage input from the input AC power supply 1. The AC / DC converter unit 30 includes a boosting coil 4, a smoothing capacitor 7, AC switches S 1 to S 4, four pre-drive circuits 51, three power supplies 52, and a drive logic circuit 53.
　ＡＣ／ＤＣコンバータ部３０を除くブロック構成は、図１３に示された従来の昇圧型ＰＦＣ制御装置５００のブロック構成と同じである。よって、本発明の実施の形態おける説明では、ＡＣ／ＤＣコンバータ部３０を中心に説明をする。 The block configuration excluding the AC / DC converter unit 30 is the same as the block configuration of the conventional step-up PFC control device 500 shown in FIG. Therefore, in the description of the embodiment of the present invention, the AC / DC converter unit 30 will be mainly described.
　ＡＣ／ＤＣコンバータ部３０では、図１３に示されたシリコン系半導体のスイッチング素子Ｔ１及びＴ２が、それぞれ、双方向スイッチング素子である交流スイッチＳ１及びＳ２に置き換えられている。また、図１３に示されたダイオードＤ１及びＤ２が、双方向スイッチング素子を用いた交流スイッチＳ３及びＳ４に置き換えられている。 In the AC / DC converter section 30, the silicon-based semiconductor switching elements T1 and T2 shown in FIG. 13 are replaced with AC switches S1 and S2, which are bidirectional switching elements, respectively. Further, the diodes D1 and D2 shown in FIG. 13 are replaced with AC switches S3 and S4 using bidirectional switching elements.
　交流スイッチＳ１～Ｓ４は、以下のようにブリッジ接続されている。昇圧用コイル４の第１の電極である入力側電極は、単相の入力交流電圧が印加される入力交流電源１の第１交流端子に接続されている。また、交流スイッチＳ１のドレイン端子と交流スイッチＳ３のドレイン端子とは、平滑用コンデンサ７の第１の電極に接続されている。また、交流スイッチＳ２のソース端子と交流スイッチＳ４のソース端子とは、平滑用コンデンサ７の第２の電極である接地電極に接続されている。また、交流スイッチＳ１のソース端子と交流スイッチＳ２のドレイン端子とは、昇圧用コイル４の第２の電極である出力側電極に接続されている。また、交流スイッチＳ３のソース端子と交流スイッチＳ４のドレイン端子とは、入力交流電圧が印加される入力交流電源１の第２交流端子に接続されている。また、交流スイッチＳ１～Ｓ４のゲート端子は、それぞれ、ドライブロジック回路５３から出力される制御信号をレベルシフトする各々のプリドライブ回路５１に接続されている。 AC switches S1 to S4 are bridge-connected as follows. The input side electrode, which is the first electrode of the boosting coil 4, is connected to the first AC terminal of the input AC power supply 1 to which a single-phase input AC voltage is applied. The drain terminal of the AC switch S1 and the drain terminal of the AC switch S3 are connected to the first electrode of the smoothing capacitor 7. The source terminal of the AC switch S2 and the source terminal of the AC switch S4 are connected to the ground electrode that is the second electrode of the smoothing capacitor 7. Further, the source terminal of the AC switch S1 and the drain terminal of the AC switch S2 are connected to the output side electrode that is the second electrode of the boosting coil 4. The source terminal of the AC switch S3 and the drain terminal of the AC switch S4 are connected to the second AC terminal of the input AC power supply 1 to which the input AC voltage is applied. The gate terminals of the AC switches S1 to S4 are connected to the respective predrive circuits 51 that shift the level of the control signal output from the drive logic circuit 53.
　昇圧用コイル４は、入力交流電源１による単相の入力交流電圧の印加によって流れる双方向電流に応じた磁気エネルギーを蓄える。 The boosting coil 4 stores magnetic energy corresponding to a bidirectional current that flows when a single-phase input AC voltage is applied by the input AC power source 1.
　平滑用コンデンサ７は、昇圧用コイル４に蓄えられた磁気エネルギーに対応した電荷を蓄える。 The smoothing capacitor 7 stores a charge corresponding to the magnetic energy stored in the boosting coil 4.
　ここで、双方向スイッチング素子の特性について説明する。 Here, the characteristics of the bidirectional switching element will be described.
　双方向スイッチング素子は、図２Ａ、図２Ｂ、及び図２Ｃに示されたＩ－Ｖ特性を持つ双方向スイッチング素子である。以下にこの特性について説明する。 The bidirectional switching element is a bidirectional switching element having the IV characteristics shown in FIGS. 2A, 2B, and 2C. This characteristic will be described below.
　図２Ａは、本発明に用いる双方向スイッチング素子のＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）特性を表すＩ－Ｖ特性図である。また、図２Ｂは、本発明に用いる双方向スイッチング素子の逆ＦＥＴ特性を表すＩ－Ｖ特性図である。また、図２Ｃは、本発明に用いる双方向スイッチング素子の逆導通特性を表すＩ－Ｖ特性図である。 FIG. 2A is an IV characteristic diagram showing an FET (Field Effect Transistor) characteristic of the bidirectional switching element used in the present invention. FIG. 2B is an IV characteristic diagram showing the reverse FET characteristic of the bidirectional switching element used in the present invention. FIG. 2C is an IV characteristic diagram showing reverse conduction characteristics of the bidirectional switching element used in the present invention.
　双方向スイッチング素子は、ゲート端子と、ドレイン端子と、ソース端子とを有する。そして、ゲート／ソース間電圧Ｖｇｓが、閾値電圧Ｖｔｈより高い場合に、ドレイン端子とソース端子間の差分電圧Ｖｄｓの極性に応じてドレイン端子からソース端子へ、または、ソース端子からドレイン端子へ電流Ｉｄｓを流すことができる。ゲート／ソース間電圧Ｖｇｓは、ソース端子電圧に対するゲート端子電圧の差分電圧である。 The bidirectional switching element has a gate terminal, a drain terminal, and a source terminal. When the gate / source voltage Vgs is higher than the threshold voltage Vth, the current Ids from the drain terminal to the source terminal or from the source terminal to the drain terminal depending on the polarity of the differential voltage Vds between the drain terminal and the source terminal. Can flow. The gate / source voltage Vgs is a differential voltage of the gate terminal voltage with respect to the source terminal voltage.
　図２Ａ及び図２Ｂでは、ゲート／ソース間電圧Ｖｇｓが閾値電圧Ｖｔｈより高いことによりスイッチング素子がオン動作状態となっている場合の、電流Ｉｄｓと差分電圧Ｖｄｓとの関係を表している。電流Ｉｄｓはドレイン端子からソース端子へ流れる場合を正の値とする。 2A and 2B show the relationship between the current Ids and the differential voltage Vds when the switching element is in the on-operation state because the gate / source voltage Vgs is higher than the threshold voltage Vth. The current Ids is a positive value when flowing from the drain terminal to the source terminal.
　上記Ｉ－Ｖ特性は、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）のＩ－Ｖ特性のように３極管領域と飽和領域とを有する。３極管領域とは、Ｖｄｓがゼロ電圧からある電圧値に達するまでのゼロ電圧近傍の領域であり、飽和領域とは、Ｖｄｓが変化してもＩｄｓがあまり変化しない定電流特性に類似した特性を示す領域である。３極管領域では、Ｉ－Ｖ特性に直線性がありＩｄｓに対するＶｄｓの傾きを、スイッチング素子のオン抵抗Ｒｏｎとして定義できる。３極管領域におけるオン抵抗Ｒｏｎは、飽和領域におけるオン抵抗に比べ十分小さい。この３極管領域における双方向スイッチング素子の特性が、交流スイッチＳ１～Ｓ４の動作特性として重要であり、以下の説明では３極管領域の特性について限定する。 The IV characteristic has a triode region and a saturation region like the IV characteristic of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The triode region is a region in the vicinity of zero voltage until Vds reaches a certain voltage value from zero voltage, and the saturation region is a characteristic similar to a constant current characteristic in which Ids does not change much even if Vds changes. It is an area | region which shows. In the triode region, the IV characteristic has linearity, and the slope of Vds with respect to Ids can be defined as the on-resistance Ron of the switching element. The on-resistance Ron in the triode region is sufficiently smaller than the on-resistance in the saturation region. The characteristics of the bidirectional switching element in the triode region are important as the operation characteristics of the AC switches S1 to S4. In the following description, the characteristics of the triode region are limited.
　図２Ａは、差分電圧Ｖｄｓが正の場合、つまりドレイン電圧がソース電圧より高い場合のＩ－Ｖ特性図である。このＩ－Ｖ特性図からわかるように電流Ｉｄｓは正の値となり、電流はドレイン端子からソース端子へ流れる。図２Ａに表されたＩ－Ｖ特性を、ＦＥＴ特性と呼ぶことにする。また、図２Ｂは、差分電圧Ｖｄｓが負の場合、つまりドレイン電圧がソース電圧より低い場合のＩ－Ｖ特性図である。このＩ－Ｖ特性図からわかるように電流Ｉｄｓは負の値となり、電流はソース端子からドレイン端子へ流れる。図２Ｂに表されたＩ－Ｖ特性を、逆ＦＥＴ特性と呼ぶことにする。 FIG. 2A is an IV characteristic diagram when the differential voltage Vds is positive, that is, when the drain voltage is higher than the source voltage. As can be seen from the IV characteristic diagram, the current Ids has a positive value, and the current flows from the drain terminal to the source terminal. The IV characteristics shown in FIG. 2A will be referred to as FET characteristics. FIG. 2B is an IV characteristic diagram when the differential voltage Vds is negative, that is, when the drain voltage is lower than the source voltage. As can be seen from the IV characteristic diagram, the current Ids has a negative value, and the current flows from the source terminal to the drain terminal. The IV characteristics shown in FIG. 2B will be referred to as inverse FET characteristics.
　双方向スイッチング素子は、ゲート／ソース間電圧Ｖｇｓが閾値電圧Ｖｔｈより低い場合、ドレイン端子からソース端子へは電流Ｉｄｓを流せない。但し、双方向スイッチング素子は、ゲート／ソース間電圧Ｖｇｓが閾値電圧Ｖｔｈより低い場合でも、ゲート端子電圧に対してドレイン端子電圧が低く、且つこの差電圧（Ｖｇｓ－Ｖｄｓ）が閾値電圧Ｖｔｈより高い場合には、ソース端子からドレイン端子に電流Ｉｄｓを流すことができる。この特性を逆導通特性と呼ぶことにする。図２Ｃは、この逆導通特性を示したＩ－Ｖ特性図である。図２Ｃからわかるように、Ｖｇｓ＝０Ｖの状態すなわちゲート端子とソース端子とがショートしたような状態では、ソース端子をアノードとしドレイン端子をカソードとして順方向電圧が閾値電圧ＶｔｈであるダイオードのＩ－Ｖ特性と同じである。 The bidirectional switching element cannot flow the current Ids from the drain terminal to the source terminal when the gate / source voltage Vgs is lower than the threshold voltage Vth. However, in the bidirectional switching element, even when the gate / source voltage Vgs is lower than the threshold voltage Vth, the drain terminal voltage is lower than the gate terminal voltage, and the difference voltage (Vgs−Vds) is higher than the threshold voltage Vth. In some cases, a current Ids can flow from the source terminal to the drain terminal. This characteristic is called reverse conduction characteristic. FIG. 2C is an IV characteristic diagram showing the reverse conduction characteristic. As can be seen from FIG. 2C, in a state where Vgs = 0V, that is, a state where the gate terminal and the source terminal are short-circuited, the I−− of the diode whose forward voltage is the threshold voltage Vth with the source terminal as the anode and the drain terminal as the cathode. It is the same as the V characteristic.
　以上のように、図２Ａ、図２Ｂ及び図２Ｃからわかることは、双方向スイッチング素子は、ゲート／ソース間電圧Ｖｇｓが閾値電圧Ｖｔｈ以上であれば、ＦＥＴ動作及び逆ＦＥＴ動作をし、オン抵抗値Ｒｏｎを持つ抵抗と見なすことができる。一方、ゲート／ソース間電圧Ｖｇｓが閾値電圧Ｖｔｈ以下であれば、逆導通特性による動作をし、ソース端子をアノードとしドレイン端子をカソードとするダイオードと見なせる。このダイオードの順方向電圧は（Ｖｔｈ－Ｖｇｓ）となる。 As can be seen from FIGS. 2A, 2B, and 2C, the bidirectional switching element performs FET operation and reverse FET operation when the gate / source voltage Vgs is equal to or higher than the threshold voltage Vth, and the on-resistance It can be regarded as a resistor having the value Ron. On the other hand, when the gate-source voltage Vgs is equal to or lower than the threshold voltage Vth, the operation is performed according to the reverse conduction characteristic, and it can be regarded as a diode having the source terminal as an anode and the drain terminal as a cathode. The forward voltage of this diode is (Vth−Vgs).
　今後、本発明の実施の形態においては、双方向スイッチング素子を以下のように等価変換する。 In the future, in the embodiment of the present invention, the bidirectional switching element is equivalently converted as follows.
　（１）ゲート／ソース間電圧Ｖｇｓが閾値電圧Ｖｔｈより高い状態の双方向スイッチング素子のオン動作状態では、スイッチング素子をオン抵抗値Ｒｏｎの抵抗と見なす。 (1) In the ON operation state of the bidirectional switching element in which the gate / source voltage Vgs is higher than the threshold voltage Vth, the switching element is regarded as a resistance having an ON resistance value Ron.
　（２）ゲート端子とソース端子とを短絡した双方向スイッチング素子のオフ動作状態では、スイッチング素子を、ソース端子をアノードとしドレイン端子をカソードとするダイオードと見なす。 (2) In the off operation state of the bidirectional switching element in which the gate terminal and the source terminal are short-circuited, the switching element is regarded as a diode having the source terminal as an anode and the drain terminal as a cathode.
　図２Ｄは、スイッチング素子のオン動作状態におけるＦＥＴモード及び逆ＦＥＴモードの等価変換を説明する図であり、図２Ｅは、スイッチング素子のオフ動作状態における逆導通モードの等価変換を説明する図である。 FIG. 2D is a diagram for explaining equivalent conversion between the FET mode and the reverse FET mode in the on-operation state of the switching element, and FIG. 2E is a diagram for explaining equivalent conversion in the reverse conduction mode in the off-operation state of the switching element. .
　次に、ＡＣ／ＤＣコンバータ部３０が有するドライブロジック回路５３について説明する。 Next, the drive logic circuit 53 included in the AC / DC converter unit 30 will be described.
　図３Ａは、本発明の実施の形態に係るドライブロジック回路５３の回路ブロック図であり、図３Ｂは、本発明の実施の形態に係るドライブロジック回路５３の内部信号の動作タイミングチャートである。 3A is a circuit block diagram of the drive logic circuit 53 according to the embodiment of the present invention, and FIG. 3B is an operation timing chart of internal signals of the drive logic circuit 53 according to the embodiment of the present invention.
　図３Ａに記載されたドライブロジック回路５３は、ＰＷＭ（Ｐｕｌｓｅ　Ｗｉｄｔｈ　Ｍｏｄｕｌａｔｉｏｎ）信号が入力されると、交流スイッチＳ１及びＳ２の一方をＰＷＭ駆動させるためのＬＰＷＭ信号と、交流スイッチＳ１及びＳ２の他方をＰＷＭ駆動させるためのＵＰＷＭ信号とを生成する。ここで、ＰＷＭ信号は、図１に示されたＰＷＭコンパレータ１２から出力された信号であり、昇圧動作をＰＷＭ制御するための信号である。ＬＰＷＭ信号により、交流スイッチＳ１及びＳ２の一方は昇圧動作のために昇圧用コイル４を駆動し、ＵＰＷＭ信号により、交流スイッチＳ１及びＳ２の他方は、交流スイッチＳ１及びＳ２の一方と同期動作する。 3A, when a PWM (Pulse Width Modulation) signal is input, the drive logic circuit 53 outputs an LPWM signal for PWM driving one of the AC switches S1 and S2 and the other of the AC switches S1 and S2. A UPWM signal for PWM driving is generated. Here, the PWM signal is a signal output from the PWM comparator 12 shown in FIG. 1, and is a signal for PWM control of the boosting operation. One of the AC switches S1 and S2 drives the boosting coil 4 for the boosting operation by the LPWM signal, and the other of the AC switches S1 and S2 operates in synchronization with one of the AC switches S1 and S2 by the UPWM signal.
　図３Ｂからわかるように、ＬＰＷＭ信号は、昇圧動作をＰＷＭ制御する為のＰＷＭ信号と同じ波形であるが、ある遅延時間ＤＴだけＰＷＭ信号から遅延している。同じくＵＰＷＭ信号は、ＬＰＷＭ信号とは逆極性の信号であり、ＵＰＷＭ信号とＬＰＷＭ信号とが同時に低レベル信号（以降、「Ｌｏｗ」と記す）である区間を遅延時間ＤＴだけ設けるように波形生成されている。この２つの信号が同時にＬｏｗである区間をデッドタイムとよぶことにする。このデッドタイムにより２つの交流スイッチＳ１及びＳ２は、正常動作している限りは、同時にオン動作状態になることは在り得なくなる。 As can be seen from FIG. 3B, the LPWM signal has the same waveform as the PWM signal for PWM control of the boost operation, but is delayed from the PWM signal by a certain delay time DT. Similarly, the UPWM signal is a signal having a polarity opposite to that of the LPWM signal, and a waveform is generated so that a section in which the UPWM signal and the LPWM signal are simultaneously a low level signal (hereinafter referred to as “Low”) is provided for the delay time DT. ing. A section in which these two signals are Low at the same time is called a dead time. Due to this dead time, as long as the two AC switches S1 and S2 are operating normally, they cannot be in the ON operation state at the same time.
　結果的には、交流スイッチＳ１及びＳ２が共にオン動作状態することで昇圧型ＰＦＣ制御装置の出力とグランド（以降、「ＧＮＤ」と記す）とが短絡状態となってしまう、いわゆる交流スイッチＳ１及びＳ２の貫通状態に陥ることが回避される。そして、昇圧用コイル４に蓄えられたエネルギーにより流れる電流は、ＬＰＷＭ信号とＵＰＷＭ信号により、交流スイッチＳ１及びＳ２のスイッチング動作を経由して、平滑用コンデンサ７に移され安定した昇圧動作が実現される。この昇圧動作において、交流スイッチＳ１またはＳ２は、前述した等価変換の規則により、デッドタイムの区間は（勿論、デッドタイム区間だけでなくＵＰＷＭ信号がＬｏｗである区間も）昇圧用ダイオードとして動作する。交流スイッチＳ１またはＳ２は、ＵＰＷＭ信号が高レベル信号（以降、「Ｈｉｇｈ」と記す）である区間は、オン抵抗値Ｒｏｎを有する抵抗として動作する。 As a result, when the AC switches S1 and S2 are both turned on, the output of the step-up PFC control device and the ground (hereinafter referred to as “GND”) are short-circuited. Falling into the penetrating state of S2 is avoided. The current flowing by the energy stored in the boosting coil 4 is transferred to the smoothing capacitor 7 by the LPWM signal and the UPWM signal via the switching operation of the AC switches S1 and S2, and a stable boosting operation is realized. The In this boosting operation, the AC switch S1 or S2 operates as a boosting diode in the dead time interval (of course, not only in the dead time interval but also in the interval where the UPWM signal is Low) according to the rules of equivalent conversion described above. The AC switch S1 or S2 operates as a resistor having an on-resistance value Ron in a section where the UPWM signal is a high level signal (hereinafter referred to as “High”).
　交流スイッチＳ１及びＳ２が昇圧用ダイオードとして動作している間で電流が流れる区間は、デッドタイム区間だけの非常に短い時間だけである。従って、従来の昇圧型ＰＦＣ制御装置のスイッチング素子Ｔ１及びＴ２に比べ、交流スイッチＳ１及びＳ２の消費電力は非常に小さくなる。 The section in which current flows while the AC switches S1 and S2 are operating as boosting diodes is a very short period of time, which is only the dead time section. Therefore, the power consumption of the AC switches S1 and S2 is very small compared to the switching elements T1 and T2 of the conventional step-up PFC control device.
　ドライブロジック回路５３の４つ出力信号Ｇ＿Ｓ１～Ｇ＿Ｓ４は、４つの交流スイッチＳ１～Ｓ４を制御する。図３Ｂのタイミング波形図のように、出力信号Ｇ＿Ｓ１及びＧ＿Ｓ２には、ＬＰＷＭ信号またはＵＰＷＭ信号が出力され、出力信号Ｇ＿Ｓ３及びＧ＿Ｓ４には、ＨｉｇｈまたはＬｏｗレベルの信号が出力される。なお、図３Ｂに記載されたＤＩＲ信号は、図１からわかるように、入力交流電源１の交流出力が昇圧用コイル４に正電圧を印加する場合にはＨｉｇｈレベル信号となり、交流出力が昇圧用コイル４に負電圧を印加する場合にはＬｏｗレベル信号となる。 The four output signals G_S1 to G_S4 of the drive logic circuit 53 control the four AC switches S1 to S4. As shown in the timing waveform diagram of FIG. 3B, the output signals G_S1 and G_S2 output the LPWM signal or the UPWM signal, and the output signals G_S3 and G_S4 output the high or low level signal. As can be seen from FIG. 1, the DIR signal shown in FIG. 3B becomes a high level signal when the AC output of the input AC power supply 1 applies a positive voltage to the boosting coil 4, and the AC output is for boosting. When a negative voltage is applied to the coil 4, it becomes a Low level signal.
　図４Ａは、入力交流電源の電圧極性が正の場合における、実施の形態に係るＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。また、図４Ｂは、入力交流電源１の電圧極性が負の場合における、実施の形態に係るＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。図４Ａ及び図４Ｂに記載された昇圧動作は、図３Ａに示されたドライブロジック回路５３がＰＷＭ動作をすることにより実現されるものである。ここで、入力交流電源１の電圧極性の正または負に依存せず、平滑用コンデンサ７には、常に昇圧用コイル４の磁気エネルギーによって電流が流れ、出力電圧Ｖｏが昇圧されることを説明する。 FIG. 4A is a diagram illustrating a current path of the step-up operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply is positive. FIG. 4B is a diagram illustrating a current path of the boost operation of the AC / DC converter unit according to the embodiment when the voltage polarity of the input AC power supply 1 is negative. The boosting operation described in FIGS. 4A and 4B is realized by the PWM operation of the drive logic circuit 53 shown in FIG. 3A. Here, it will be described that a current always flows through the smoothing capacitor 7 by the magnetic energy of the boosting coil 4 and the output voltage Vo is boosted regardless of whether the voltage polarity of the input AC power supply 1 is positive or negative. .
　入力交流電源１が正極性の時には、ＤＩＲ信号がＨｉｇｈレベルであり、図３Ｂのタイミング波形図から、交流スイッチＳ２が昇圧用コイル４を駆動するためのＬＰＷＭ信号を受け、交流スイッチＳ１がＵＰＷＭ信号を受ける。交流スイッチＳ３はＬｏｗレベル信号を受け、交流スイッチＳ４はＨｉｇｈレベル信号を受ける。交流スイッチＳ１～Ｓ４は、これらの信号を受け、図４Ａに表された動作状態となる。なお、図４Ａ及び図４Ｂでは、ＬＰＷＭ信号は昇圧用ＰＷＭ動作を制御するＰＷＭ信号として記述しており、同期信号であるＵＰＷＭ信号はＰＷＭ信号の反転信号を意味するバー付きのＰＷＭ信号として記述している。 When the input AC power supply 1 is positive, the DIR signal is at a high level. From the timing waveform diagram of FIG. 3B, the AC switch S2 receives the LPWM signal for driving the boosting coil 4, and the AC switch S1 is the UPWM signal. Receive. The AC switch S3 receives a Low level signal, and the AC switch S4 receives a High level signal. The AC switches S1 to S4 receive these signals and enter the operating state shown in FIG. 4A. In FIGS. 4A and 4B, the LPWM signal is described as a PWM signal for controlling the step-up PWM operation, and the UPWM signal that is a synchronization signal is described as a PWM signal with a bar that represents an inverted signal of the PWM signal. ing.
　図４Ａでは、交流スイッチＳ２がＰＷＭ動作をして昇圧用コイル４を駆動し、交流スイッチＳ１はＰＷＭ動作の反転した動作状態となる。交流スイッチＳ４はオン抵抗Ｒｏｎを有する抵抗として働いて電流を流し、交流スイッチＳ３はオフ動作状態のため等価回路的にはダイオードと見なせるが電流が流れない状態となっている。交流スイッチＳ２がＰＷＭ動作でオン動作状態の時は、図４Ａの経路（ａ）にて昇圧用コイル４を励磁させる電流が流れる。一方、交流スイッチＳ２がＰＷＭ動作でオフ動作状態の時は、昇圧用コイル４に蓄えられた磁気エネルギーにより、図４Ａの経路（ｂ）にて電流が交流スイッチＳ１を経由して流れる。そして、平滑用コンデンサ７の接地されていない端子から電流が充電され昇圧型ＰＦＣ制御装置１００の出力電圧Ｖｏが昇圧されていく。 In FIG. 4A, the AC switch S2 performs a PWM operation to drive the boosting coil 4, and the AC switch S1 is in an operation state in which the PWM operation is inverted. The AC switch S4 functions as a resistor having an on-resistance Ron and allows a current to flow. The AC switch S3 can be regarded as a diode in terms of an equivalent circuit because of an off operation state, but no current flows. When the AC switch S2 is in the ON operation state by the PWM operation, a current for exciting the boosting coil 4 flows through the path (a) in FIG. 4A. On the other hand, when the AC switch S2 is in the OFF operation state by PWM operation, current flows through the AC switch S1 in the path (b) of FIG. 4A due to the magnetic energy stored in the boosting coil 4. Then, a current is charged from a terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the step-up PFC control device 100 is stepped up.
　交流スイッチＳ２及びＳ１の同期動作したＰＷＭ動作では、前述のデッドタイム区間が設けられてあり、交流スイッチＳ１及びＳ２が貫通状態に陥ることはない。デッドタイム区間の非常に短い時間では、交流スイッチＳ１は昇圧用ダイオードとして働く。交流スイッチＳ２がオンからオフ動作状態になると、昇圧用コイル４に蓄えられた磁気エネルギーにより、昇圧用コイル４の電流は、交流スイッチＳ１を経由して図４Ａの経路（ｂ）にて平滑用コンデンサ７の接地されていない端子へ流入する。これは、デッドタイム区間では交流スイッチＳ１を昇圧用ダイオードとして、また、交流スイッチＳ１がオン動作状態では、交流スイッチＳ１を、オン抵抗Ｒｏｎを有する抵抗として働くためである。 In the PWM operation in which the AC switches S2 and S1 are operated synchronously, the above-described dead time interval is provided, and the AC switches S1 and S2 do not fall into the through state. In a very short time of the dead time interval, the AC switch S1 functions as a boosting diode. When the AC switch S2 is switched from ON to OFF, the current in the booster coil 4 is smoothed by the magnetic energy stored in the booster coil 4 via the AC switch S1 in the path (b) of FIG. 4A. It flows into the terminal of the capacitor 7 which is not grounded. This is because the AC switch S1 functions as a boosting diode in the dead time period, and the AC switch S1 functions as a resistor having an ON resistance Ron when the AC switch S1 is in the ON operation state.
　これに対して、入力交流電源１が負極性の時には、ＤＩＲ信号がＬｏｗレベルであり、図３Ｂのタイミング波形図から、入力交流電源１が正極性の場合と比べて交流スイッチＳ２及びＳ１の動きが入れ替わり、また交流スイッチＳ４及びＳ３の動きが入れ替わることが判る。 On the other hand, when the input AC power supply 1 has a negative polarity, the DIR signal is at a low level. From the timing waveform diagram of FIG. 3B, the movement of the AC switches S2 and S1 compared to the case where the input AC power supply 1 has a positive polarity. It can be seen that the movements of the AC switches S4 and S3 are switched.
　図４Ｂでは、交流スイッチＳ１がＰＷＭ動作をして昇圧用コイル４を駆動し、交流スイッチＳ２がＰＷＭ動作の反転した動作状態となっている。そして、交流スイッチＳ３がオン抵抗Ｒｏｎを有する抵抗として働き電流を流し、交流スイッチＳ４はオフ動作状態のため等価回路的にはダイオードと見なせるが電流が流れない状態となっている。交流スイッチＳ１がＰＷＭ動作でオン動作状態の時は、図４Ｂの経路（ａ）にて昇圧用コイル４を励磁させる電流が流れる。一方、交流スイッチＳ１がＰＷＭ動作でオフ動作状態の時は、昇圧用コイル４に蓄えられた磁気エネルギーにより、図４Ｂの経路（ｂ）にて電流が交流スイッチＳ２を経由して流れる。そして、平滑用コンデンサ７の接地されていない端子から電流が充電され昇圧型ＰＦＣ制御装置１００の出力電圧Ｖｏが昇圧されていく。 In FIG. 4B, the AC switch S1 performs a PWM operation to drive the boosting coil 4, and the AC switch S2 is in an operating state in which the PWM operation is inverted. The AC switch S3 functions as a resistor having an on-resistance Ron, and a current flows. The AC switch S4 is in an off operation state and can be regarded as a diode in terms of an equivalent circuit, but no current flows. When the AC switch S1 is in the ON operation state by PWM operation, a current for exciting the boosting coil 4 flows through the path (a) in FIG. 4B. On the other hand, when the AC switch S1 is in the OFF operation state by the PWM operation, the current flows through the AC switch S2 in the path (b) of FIG. 4B due to the magnetic energy stored in the boosting coil 4. Then, a current is charged from a terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the step-up PFC control device 100 is stepped up.
　この場合においても、交流スイッチＳ１及びＳ２の同期動作したＰＷＭ動作では、前述のデッドタイム区間が設けてある。そして、入力交流電源１が正極性である時の交流スイッチＳ１と同じ動作を交流スイッチＳ２が行い、昇圧用コイル４の電流は交流スイッチＳ２を経由して経路（ｂ）で平滑用コンデンサ７の接地されていない端子へ流入する。 Also in this case, the aforementioned dead time section is provided in the PWM operation in which the AC switches S1 and S2 are operated in synchronization. Then, the AC switch S2 performs the same operation as the AC switch S1 when the input AC power supply 1 is positive, and the current of the boosting coil 4 is passed through the AC switch S2 through the path (b) of the smoothing capacitor 7. It flows into a terminal that is not grounded.
　つまり、ドライブロジック回路５３は、交流スイッチＳ１～Ｓ４のオンオフ状態を制御することにより、双方向電流の電流径路を切り換えて、昇圧用コイル４への磁気エネルギーの蓄積と平滑用コンデンサ７への電荷蓄積とを交互に行わせる。 In other words, the drive logic circuit 53 switches the current path of the bidirectional current by controlling the on / off states of the AC switches S1 to S4 to accumulate magnetic energy in the boosting coil 4 and charge to the smoothing capacitor 7. Accumulate and alternate.
　以上の動作より、入力交流電源１の電圧極性が正であっても負であっても平滑用コンデンサ７の接地されていない端子には、常に昇圧用コイル４の磁気エネルギーによって電流が流れ、出力電圧Ｖｏは昇圧されることが判る。従って、図１に示された昇圧型ＰＦＣ制御装置１００は、整流ダイオードブリッジが無いにもかかわらず、入力交流電源１の交流電圧を整流し昇圧する機能を有することがわかる。 From the above operation, a current always flows through the terminal of the smoothing capacitor 7 that is not grounded regardless of whether the voltage polarity of the input AC power supply 1 is positive or negative, by the magnetic energy of the boosting coil 4, and output It can be seen that the voltage Vo is boosted. Therefore, it can be seen that the step-up PFC control device 100 shown in FIG. 1 has a function of rectifying and stepping up the AC voltage of the input AC power supply 1 even though there is no rectifier diode bridge.
　また、図１に示された昇圧用コイル４に流れる電流が略零の状態では、図３Ａに示されたヒステリシス比較器が、電流がほとんど流れていないことを検出する。ヒステリシス比較器は、電流検出素子３の出力信号を第２絶対値回路１１で正の電圧信号に変換した信号Ｓｃと、比較基準電圧ＶＲＢとを比較することにより、昇圧用コイル４に流れる電流を検出する。また、交流スイッチＳ１またはＳ２は、Ｈｉｇｈレベルのゲート信号を受けてオン抵抗値Ｒｏｎを有する抵抗として動作する。しかし、交流スイッチＳ１またはＳ２は、ヒステリシス比較器のゼロ電流検出動作により、そのゲート信号をＨｉｇｈレベルからＬｏｗレベルに変化させられることで、ダイオード動作へと変化する。 Further, when the current flowing through the boosting coil 4 shown in FIG. 1 is substantially zero, the hysteresis comparator shown in FIG. 3A detects that almost no current flows. The hysteresis comparator compares the signal Sc obtained by converting the output signal of the current detection element 3 into a positive voltage signal by the second absolute value circuit 11 and the comparison reference voltage VRB, thereby obtaining the current flowing through the boosting coil 4. To detect. The AC switch S1 or S2 operates as a resistor having an on-resistance value Ron in response to a high-level gate signal. However, the AC switch S1 or S2 changes to the diode operation by changing the gate signal from the High level to the Low level by the zero current detection operation of the hysteresis comparator.
　この機能は、昇圧用コイル４に流れる電流が略零の場合、昇圧用コイル４に蓄えられた磁気的なエネルギーがなくなるために、出力側から交流スイッチと昇圧用コイル４を介して入力交流電源１に電流が逆流することを回避するためのものである。 In this function, when the current flowing through the boosting coil 4 is substantially zero, the magnetic energy stored in the boosting coil 4 is lost, so that the input AC power source is connected from the output side through the AC switch and the boosting coil 4. This is to prevent the current from flowing back to 1.
　なお、昇圧用コイル４にて電流が流れなくなると、昇圧用コイル４の両端電圧がリンギング現象を起こすことがある。この場合は、図３Ａに図示されていないが、ヒステリシス比較器の出力信号がＬｏｗレベルになるとある一定期間Ｌｏｗレベルを維持する機能を、ヒステリシス比較器の後段に追加すればよい。 Note that if current stops flowing through the boosting coil 4, the voltage across the boosting coil 4 may cause a ringing phenomenon. In this case, although not shown in FIG. 3A, a function of maintaining the Low level for a certain period when the output signal of the hysteresis comparator becomes Low level may be added to the subsequent stage of the hysteresis comparator.
　以上、本発明の実施の形態に係る昇圧型ＰＦＣ制御装置１００により、ダイオードが無く、またスイッチング素子の寄生ダイオードも無い昇圧型ＰＦＣ制御装置が実現される。 As described above, the step-up PFC control apparatus 100 according to the embodiment of the present invention realizes a step-up PFC control apparatus without a diode and without a parasitic diode of a switching element.
　従来の昇圧型ＰＦＣ制御装置の消費電力において、ダイオードとスイッチング素子の寄生ダイオードとが影響する導通損失とスイッチング損失とが、装置全体の電力損失に対して大きな比重を占めていた。これに対して、本発明に係る昇圧型ＰＦＣ制御装置では、ダイオードとスイッチング素子の寄生ダイオードとを無くしたことで、従来の整流及び昇圧動作を維持しつつ消費電力を大幅に削減できる。 In the power consumption of the conventional boost type PFC control device, the conduction loss and the switching loss influenced by the diode and the parasitic diode of the switching element occupy a large proportion of the power loss of the entire device. In contrast, in the step-up PFC control device according to the present invention, the power consumption can be greatly reduced while maintaining the conventional rectification and step-up operation by eliminating the diode and the parasitic diode of the switching element.
　また、交流スイッチとして用いられる双方向スイッチング素子は、寄生ダイオードを持たず、そのため、寄生ダイオードによるリカバリー電流が無い。これにより、スイッチング周波数を上げても昇圧型ＰＦＣ制御装置のスイッチング損失の大幅な増加はなく、スイッチング周波数を上げて昇圧用コイル４を小さくすることが可能となる。 Also, the bidirectional switching element used as an AC switch does not have a parasitic diode, and therefore there is no recovery current due to the parasitic diode. As a result, even if the switching frequency is increased, the switching loss of the step-up PFC controller does not increase significantly, and the step-up coil 4 can be made smaller by increasing the switching frequency.
　また、昇圧型ＰＦＣ制御装置が有するＰＦＣ制御部は、従来からの昇圧型ＰＦＣ制御装置の制御部をそのまま用いることができるので、従来の昇圧型ＰＦＣ制御装置から本発明の昇圧型ＰＦＣ制御装置の置き換えも容易にできる。 Further, since the PFC control unit included in the boost type PFC control device can use the control unit of the conventional boost type PFC control device as it is, the boost type PFC control device of the present invention is changed from the conventional boost type PFC control device. Replacement is also easy.
　なお、上述したスイッチング素子は、半導体基板の上に形成された窒化物半導体層からなる積層体と、積層体の上に互いに間隔をおいて形成されたドレイン端子及びソース端子と、ドレイン端子及びソース端子の間に形成されたゲート端子とを備えることを特徴とするものであってもよい。このスイッチング素子について、図５を用いて説明する。 Note that the switching element described above includes a stacked body formed of a nitride semiconductor layer formed on a semiconductor substrate, a drain terminal and a source terminal formed on the stacked body at intervals, and a drain terminal and a source. And a gate terminal formed between the terminals. This switching element will be described with reference to FIG.
　図５は、本発明の昇圧型ＰＦＣ制御装置が有する双方向スイッチング素子の断面図の一例である。同図に記載された双方向スイッチング素子は、半導体基板の上に形成された窒化物半導体からなるノーマリオフ型のヘテロ接合ＦＥＴである。具体的には、スイッチング素子は、シリコン基板２０１の上にバッファ層２０２を介して半導体層の積層体２０３が形成されることにより実現される。 FIG. 5 is an example of a cross-sectional view of a bidirectional switching element included in the step-up PFC control device of the present invention. The bidirectional switching element shown in the figure is a normally-off type heterojunction FET made of a nitride semiconductor formed on a semiconductor substrate. Specifically, the switching element is realized by forming a stacked body 203 of semiconductor layers on a silicon substrate 201 via a buffer layer 202.
　バッファ層２０２は、窒化アルミニウムと窒化ガリウムとが交互に積層されたものである。 The buffer layer 202 is formed by alternately stacking aluminum nitride and gallium nitride.
　積層体２０３は、アンドープ窒化ガリウム層２０４の上にｎ型窒化アルミニウムガリウム層２０５が形成されたもので、この２つの層の間のヘテロ界面近傍には２次元電子ガスと呼ばれるキャリア濃度の高いＦＥＴのチャンネル領域が生成される。 In the stacked body 203, an n-type aluminum gallium nitride layer 205 is formed on an undoped gallium nitride layer 204, and an FET having a high carrier concentration called a two-dimensional electron gas is located in the vicinity of the heterointerface between the two layers. Channel regions are generated.
　積層体２０３の上に、ソース端子とドレイン端子とを形成するために、チャンネル領域とオーミック接合するするソース端子用オーミック電極２０６ａとドレイン端子用オーミック電極２０６ｂと配線２１０とが配置される。 On the laminate 203, in order to form a source terminal and a drain terminal, a source terminal ohmic electrode 206a, a drain terminal ohmic electrode 206b, and a wiring 210, which are in ohmic contact with the channel region, are arranged.
　ソース端子用オーミック電極２０６ａとドレイン端子用オーミック電極２０６ｂとの間の領域では、ＦＥＴ特性を制御するｐ型半導体層であるコントロール層２０９がｎ型窒化アルミニウムガリウム層２０５の上に形成される。そして、各部を保護するための保護膜２０７が各部を覆うように形成されている。 In the region between the source terminal ohmic electrode 206a and the drain terminal ohmic electrode 206b, a control layer 209, which is a p-type semiconductor layer for controlling FET characteristics, is formed on the n-type aluminum gallium nitride layer 205. A protective film 207 for protecting each part is formed so as to cover each part.
　コントロール層２０９の上にはゲート電極２０８が形成され、コントロール層２０９とはオーミック接触している。このゲート電極２０８に与えられる電気信号により、ノーマリオフ型のヘテロ接合ＦＥＴ、すなわち、双方向型のスイッチング素子のドレイン端子とソース端子の間に流れる電流が制御される。 A gate electrode 208 is formed on the control layer 209 and is in ohmic contact with the control layer 209. The electric signal supplied to the gate electrode 208 controls the current flowing between the drain terminal and the source terminal of the normally-off type heterojunction FET, that is, the bidirectional switching element.
　図５において、ドレイン端子用オーミック電極２０６ｂからゲート電極２０８までの距離が、ソース端子用オーミック電極２０６ａからゲート電極２０８までの距離より長いのは、ドレイン端子とゲート端子間の耐圧のほうがソース端子とゲート端子間の耐圧より大きいことが要求されるためである。 In FIG. 5, the distance from the drain terminal ohmic electrode 206b to the gate electrode 208 is longer than the distance from the source terminal ohmic electrode 206a to the gate electrode 208 because the withstand voltage between the drain terminal and the gate terminal is higher than the source terminal. This is because it is required to be larger than the breakdown voltage between the gate terminals.
　図５のように形成された双方向型のスイッチング素子は、ＧａＮトランジスタと呼ばれ、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）のように高耐圧で大電流駆動することができるデバイスである。また、スイッチング素子は、ＩＧＢＴの電流電圧特性におけるＰＮ接合によるオフセット電圧を持たずに、図２Ａ及び図２Ｂで示したような双方に電流を流す特性を有する。さらに、スイッチング素子は、デバイスのチップ面積に対してオン抵抗成分Ｒｏｎが非常に小さい。加えて、ＧａＮトランジスタは、図２Ｃに示した逆導通特性をも有する。 The bidirectional switching element formed as shown in FIG. 5 is called a GaN transistor, and is a device that can be driven with a high voltage and a large current, such as an IGBT (Insulated Gate Bipolar Transistor). In addition, the switching element does not have an offset voltage due to the PN junction in the current-voltage characteristics of the IGBT, and has a characteristic of flowing a current to both as shown in FIGS. 2A and 2B. Further, the switching element has a very small on-resistance component Ron with respect to the chip area of the device. In addition, the GaN transistor also has the reverse conduction characteristics shown in FIG. 2C.
　上述した特性に加え、ＧａＮトランジスタは、少数キャリアによる蓄積効果がほとんどなく、ＩＧＢＴや他のシリコン系半導体素子のようなターンオフ時のテール電流効果もほとんどない。 In addition to the characteristics described above, the GaN transistor has almost no accumulation effect due to minority carriers, and almost no tail current effect during turn-off as in IGBTs and other silicon-based semiconductor elements.
　ＡＣ／ＤＣコンバータ部３０は、ＧａＮトランジスタを双方向スイッチング素子として用いた交流スイッチで構成されている。そのため、ＡＣ／ＤＣコンバータ部３０は、その非常に小さなオン抵抗値Ｒｏｎによる導通損失の低減と少数キャリア蓄積効果がほとんど無いことによるスイッチング損失の低減により、消費電力を大幅に小さくできる。 The AC / DC converter unit 30 is composed of an AC switch using a GaN transistor as a bidirectional switching element. Therefore, the AC / DC converter unit 30 can greatly reduce power consumption by reducing conduction loss due to its very small on-resistance value Ron and reducing switching loss due to almost no minority carrier accumulation effect.
　また、双方向型のスイッチング素子にＧａＮトランジスタを適用することで、リカバリー電流によるスイッチング損失増大の影響もほとんど無く、スイッチング損失の低減によりスイッチング周波数を上げることが可能となる。これにより昇圧用コイル４のサイズを小さくでき、結果的に装置の小型化が可能となる。 Also, by applying a GaN transistor to the bidirectional switching element, there is almost no influence of an increase in switching loss due to the recovery current, and it becomes possible to increase the switching frequency by reducing the switching loss. Thereby, the size of the boosting coil 4 can be reduced, and as a result, the apparatus can be miniaturized.
　従って、本発明の実施の形態に係る昇圧型ＰＦＣ制御装置１００の双方向スイッチング素子としてＧａＮトランジスタを用いることで、より低消費電力の昇圧型ＰＦＣ制御装置が実現できる。 Therefore, by using a GaN transistor as the bidirectional switching element of the step-up PFC control apparatus 100 according to the embodiment of the present invention, a step-down PFC control apparatus with lower power consumption can be realized.
　図６は、本発明の実施の形態の第１の変形例に係る昇圧型ＰＦＣ制御装置の回路ブロック図である。同図に記載された昇圧型ＰＦＣ制御装置１５０は、図１に記載された昇圧型ＰＦＣ制御装置１００と比較して、ＡＣ／ＤＣコンバータ部３１の交流スイッチの一部が構成として異なる。以下、図１に記載された昇圧型ＰＦＣ制御装置１００と同じ点は説明を省略し、異なる点のみ説明する。 FIG. 6 is a circuit block diagram of the step-up PFC control apparatus according to the first modification of the embodiment of the present invention. The step-up PFC control device 150 shown in the figure is different from the step-up PFC control device 100 shown in FIG. 1 in the configuration of a part of the AC switch of the AC / DC converter unit 31. Hereinafter, the description of the same points as the step-up PFC control apparatus 100 described in FIG. 1 will be omitted, and only different points will be described.
　交流スイッチＳ２及びＳ４は、それぞれ、ドレイン端子同士が直列接続された２つの双方向スイッチング素子で構成されている。この構成により、交流スイッチの耐圧を上げることが可能となり、より高入力耐圧の昇圧型ＰＦＣ制御装置が実現できる。また、昇圧型ＰＦＣ制御装置１５０では、図示されているオフ信号（ＯＦＦ）にＬｏｗレベルの信号を与えることにより、昇圧型ＰＦＣ制御装置１５０の入力交流電源１から出力側を切り離すことができる。 AC switches S2 and S4 are each composed of two bidirectional switching elements whose drain terminals are connected in series. With this configuration, it is possible to increase the withstand voltage of the AC switch, and it is possible to realize a step-up PFC control device with a higher input withstand voltage. Further, in the step-up type PFC control device 150, the output side can be disconnected from the input AC power supply 1 of the step-up type PFC control device 150 by giving a low level signal to the illustrated off signal (OFF).
　図７Ａは、入力交流電源の電圧極性が正の場合における、実施の形態の第１の変形例に係る交流スイッチの状態を表す等価回路図である。また、図７Ｂは、入力交流電源の電圧極性が負の場合における、実施の形態の第１の変形例に係る交流スイッチの状態を表す等価回路図である。図７Ａ及び図７Ｂでは、ＰＷＭコンパレータ１２の出力であるＰＷＭ信号はＬｏｗレベルで、オフ信号もＬｏｗレベルとしている。 FIG. 7A is an equivalent circuit diagram showing the state of the AC switch according to the first modification of the embodiment when the voltage polarity of the input AC power supply is positive. FIG. 7B is an equivalent circuit diagram showing the state of the AC switch according to the first modification of the embodiment when the voltage polarity of the input AC power supply is negative. 7A and 7B, the PWM signal that is the output of the PWM comparator 12 is at the low level, and the off signal is also at the low level.
　なお、本変形例では、交流スイッチＳ２及びＳ４を、それぞれ、２つの双方向スイッチング素子の直列接続により構成されるものとした。それに対し、交流スイッチＳ１及びＳ３に、直列接続された２つの双方向スイッチング素子を適用し、交流スイッチＳ２及びＳ４を通常の交流スイッチとしてもよい。 In this modification, each of the AC switches S2 and S4 is constituted by a series connection of two bidirectional switching elements. On the other hand, two bidirectional switching elements connected in series may be applied to the AC switches S1 and S3, and the AC switches S2 and S4 may be normal AC switches.
　また、本変形例に係る交流スイッチＳ２及びＳ４は、２つの双方スイッチング素子の各ドレイン端子が接続された構成としているが、ソース端子同士が接続された形で直列接続されたものでもよい。 Further, the AC switches S2 and S4 according to the present modification have a configuration in which the drain terminals of the two switching elements are connected to each other, but may be connected in series with the source terminals connected to each other.
　図８Ａは、本発明の実施の形態の第２の変形例のドライブロジック回路６３の回路ブロック図であり、図８Ｂは、本発明の実施の形態の第２の変形例のドライブロジック回路６３の内部信号の動作タイミングチャートである。 FIG. 8A is a circuit block diagram of a drive logic circuit 63 according to a second modification of the embodiment of the present invention, and FIG. 8B illustrates a drive logic circuit 63 according to the second modification of the embodiment of the present invention. It is an operation | movement timing chart of an internal signal.
　図８Ａに記載されたドライブロジック回路６３は、ＰＷＭ信号が入力されると、交流スイッチＳ２及びＳ４の一方をＰＷＭ駆動させるためのＬＰＷＭ信号を生成し、交流スイッチＳ１及びＳ３の一方をＰＷＭ駆動させるためのＵＰＷＭ信号を生成する。ここで、ＰＷＭ信号は、図１に示されたＰＷＭコンパレータ１２から出力された信号であり、昇圧動作をＰＷＭ制御するための信号である。ＬＰＷＭ信号により、交流スイッチＳ２及びＳ４の一方は昇圧動作のために昇圧用コイル４を駆動し、ＵＰＷＭ信号により、交流スイッチＳ１及びＳ３の一方は、交流スイッチＳ２及びＳ４の一方と同期動作する。 When the PWM signal is input, the drive logic circuit 63 illustrated in FIG. 8A generates an LPWM signal for PWM driving one of the AC switches S2 and S4, and PWM driving one of the AC switches S1 and S3. For generating a UPWM signal. Here, the PWM signal is a signal output from the PWM comparator 12 shown in FIG. 1, and is a signal for PWM control of the boosting operation. One of the AC switches S2 and S4 drives the boosting coil 4 for the boosting operation by the LPWM signal, and one of the AC switches S1 and S3 operates in synchronization with one of the AC switches S2 and S4 by the UPWM signal.
　図８Ｂからわかるように、ＰＷＭ信号、ＵＰＷＭ信号及びＬＰＷＭ信号の関係は、図３Ｂで説明した関係と同じである。この２つの信号が同時にＬｏｗである区間をデッドタイムと呼ぶことにする。ＵＰＷＭ信号及びＬＰＷＭ信号が同時にＬｏｗであるデッドタイムにより、２つの交流スイッチＳ１及びＳ２、または、交流スイッチＳ３及びＳ４が、正常動作している限りは、同時にオン動作状態になることは在り得なくなる。 As can be seen from FIG. 8B, the relationship between the PWM signal, the UPWM signal, and the LPWM signal is the same as the relationship described in FIG. 3B. A section in which these two signals are Low at the same time is called a dead time. Due to the dead time when the UPWM signal and the LPWM signal are simultaneously Low, as long as the two AC switches S1 and S2 or the AC switches S3 and S4 are operating normally, they cannot be in the ON operation state at the same time. .
　結果的には、交流スイッチＳ１及びＳ２、または、交流スイッチＳ３及びＳ４が共にオン動作状態することで昇圧型ＰＦＣ制御装置２００の出力とＧＮＤとが短絡状態となってしまう、いわゆる貫通状態に陥ることが回避される。そして、昇圧用コイル４に蓄えられたエネルギーにより流れる電流は、交流スイッチＳ２またはＳ４がＬＰＷＭ信号によりスイッチング動作をすることで、交流スイッチＳ１またはＳ３のＵＰＷＭ信号によるスイッチング動作を経由して、平滑用コンデンサ７に移され安定した昇圧動作が実現される。この昇圧動作において、ＵＰＷＭ信号でスイッチング動作する交流スイッチＳ３またはＳ４は、前述した等価変換の規則により、デッドタイムの区間は（勿論、デッドタイム区間だけでなくＵＰＷＭ信号がＬｏｗである区間も）昇圧用ダイオードとして動作する。また、ＵＰＷＭ信号がＨｉｇｈである区間は、交流スイッチＳ３またはＳ４は、オン抵抗値Ｒｏｎを有する抵抗として動作する。 As a result, when the AC switches S1 and S2 or the AC switches S3 and S4 are both turned on, the output of the step-up PFC control device 200 and the GND are short-circuited, resulting in a so-called through state. It is avoided. The current flowing by the energy stored in the boosting coil 4 is smoothed via the switching operation of the AC switch S1 or S3 by the UPWM signal by the AC switch S2 or S4 performing the switching operation by the LPWM signal. It is transferred to the capacitor 7 to realize a stable boosting operation. In this boosting operation, the AC switch S3 or S4 that performs switching operation with the UPWM signal is boosted in the dead time interval (of course, not only in the dead time interval but also in the interval in which the UPWM signal is Low) according to the rules of equivalent conversion described above. Operates as a diode. Further, in a section where the UPWM signal is High, the AC switch S3 or S4 operates as a resistor having an on-resistance value Ron.
　交流スイッチＳ１及びＳ３が昇圧用ダイオードとして動作している間で電流が流れる区間は、デッドタイム区間だけの非常に短い時間だけである。従って、従来の昇圧型ＰＦＣ制御装置のスイッチング素子Ｔ３及びＴ４に比べ、交流スイッチＳ１及びＳ３の消費電力は非常に小さくなる。 The period during which the current flows while the AC switches S1 and S3 are operating as boosting diodes is a very short period of only the dead time period. Therefore, the power consumption of the AC switches S1 and S3 is very small compared to the switching elements T3 and T4 of the conventional step-up PFC control device.
　ドライブロジック回路６３の出力は実施の形態のものと同じく４つある。各出力信号Ｇ＿Ｓ１～Ｇ＿Ｓ４は、それぞれ、交流スイッチＳ１～Ｓ４を制御する。図８Ｂのタイミング波形図のように、出力信号Ｇ＿Ｓ２及びＧ＿Ｓ４には、ＬＰＷＭ信号またはＨｉｇｈレベルの信号が出力され、出力信号Ｇ＿Ｓ１及びＧ＿Ｓ３には、ＵＰＷＭ信号またはＬｏｗレベルの信号が出力される。なお、図８Ｂに記載されたＤＩＲ信号は、図１からわかるように、入力交流電源１の交流出力が昇圧用コイル４に正電圧を印加する場合にはＨｉｇｈレベル信号となる。また、ＤＩＲ信号は、入力交流電源１の交流出力が昇圧用コイル４に負電圧を印加する場合にはＬｏｗレベル信号となる。 There are four outputs from the drive logic circuit 63 as in the embodiment. The output signals G_S1 to G_S4 control the AC switches S1 to S4, respectively. As shown in the timing waveform diagram of FIG. 8B, the output signals G_S2 and G_S4 output an LPWM signal or a high level signal, and the output signals G_S1 and G_S3 output a UPWM signal or a low level signal. As can be seen from FIG. 1, the DIR signal shown in FIG. 8B becomes a high level signal when the AC output of the input AC power supply 1 applies a positive voltage to the boosting coil 4. The DIR signal is a Low level signal when the AC output of the input AC power supply 1 applies a negative voltage to the boosting coil 4.
　図９Ａは、入力交流電源の電圧極性が正の場合のＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。図９Ｂは、入力交流電源の電圧極性が負の場合のＡＣ／ＤＣコンバータ部の昇圧動作の電流パスを表す図である。図９Ａ及び図９Ｂに記載された昇圧動作は、図８Ａに示されたドライブロジック回路６３がＰＷＭ動作をすることにより実現されるものである。ここで、入力交流電源１の電圧極性の正または負に依存せず、平滑用コンデンサ７には、常に昇圧用コイル４の磁気エネルギーによって電流が流れ、出力電圧Ｖｏが昇圧されることを説明する。 FIG. 9A is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit when the voltage polarity of the input AC power supply is positive. FIG. 9B is a diagram illustrating a current path of the boosting operation of the AC / DC converter unit when the voltage polarity of the input AC power supply is negative. The boosting operation described in FIGS. 9A and 9B is realized by the PWM operation of the drive logic circuit 63 shown in FIG. 8A. Here, it will be described that a current always flows through the smoothing capacitor 7 by the magnetic energy of the boosting coil 4 and the output voltage Vo is boosted regardless of whether the voltage polarity of the input AC power supply 1 is positive or negative. .
　入力交流電源１が正極性の時には、ＤＩＲ信号がＨｉｇｈレベルであり、図８Ｂのタイミング波形図から、交流スイッチＳ２が昇圧用コイル４を駆動するためのＬＰＷＭ信号を受け、交流スイッチＳ１がＵＰＷＭ信号を受ける。交流スイッチＳ３はＬｏｗレベル信号を受け、交流スイッチＳ４はＨｉｇｈレベル信号を受ける。交流スイッチＳ１～Ｓ４は、これらの信号を受け、図９Ａに表された動作状態となる。なお、図９Ａ及び図９Ｂでは、ＬＰＷＭ信号は昇圧用ＰＷＭ動作を制御するＰＷＭ信号として記述しており、同期信号であるＵＰＷＭ信号はＰＷＭ信号の反転信号を意味するバー付きのＰＷＭ信号として記述している。 When the input AC power supply 1 is positive, the DIR signal is at a high level. From the timing waveform diagram of FIG. 8B, the AC switch S2 receives the LPWM signal for driving the boosting coil 4, and the AC switch S1 is the UPWM signal. Receive. The AC switch S3 receives a Low level signal, and the AC switch S4 receives a High level signal. The AC switches S1 to S4 receive these signals and enter the operating state shown in FIG. 9A. In FIGS. 9A and 9B, the LPWM signal is described as a PWM signal for controlling the step-up PWM operation, and the UPWM signal that is a synchronization signal is described as a PWM signal with a bar that represents an inverted signal of the PWM signal. ing.
　図９Ａでは、交流スイッチＳ２がＰＷＭ動作をして昇圧用コイル４を駆動し、交流スイッチＳ１はＰＷＭ動作の反転した動作状態となる。交流スイッチＳ４はオン抵抗Ｒｏｎを有する抵抗として働いて電流を流し、交流スイッチＳ３はオフ動作状態のため等価回路的にはダイオードと見なせるが電流が流れない状態となっている。交流スイッチＳ２がＰＷＭ動作でオン動作状態の時は、図９Ａの経路（ａ）にて昇圧用コイル４を励磁させる電流が流れる。一方、交流スイッチＳ２がＰＷＭ動作でオフ動作状態の時は、昇圧用コイル４に蓄えられた磁気エネルギーにより、図９Ａの経路（ｂ）にて電流が交流スイッチＳ１を経由して流れる。そして、平滑用コンデンサ７の接地されていない端子から電流が充電され昇圧型ＰＦＣ制御装置２００の出力電圧Ｖｏが昇圧されていく。 In FIG. 9A, the AC switch S2 performs a PWM operation to drive the boosting coil 4, and the AC switch S1 is in an operation state in which the PWM operation is inverted. The AC switch S4 functions as a resistor having an on-resistance Ron and allows a current to flow. The AC switch S3 can be regarded as a diode in terms of an equivalent circuit because of an off operation state, but no current flows. When the AC switch S2 is in the ON operation state by the PWM operation, a current for exciting the boosting coil 4 flows through the path (a) in FIG. 9A. On the other hand, when the AC switch S2 is in the OFF operation state by PWM operation, current flows through the AC switch S1 in the path (b) of FIG. 9A due to the magnetic energy stored in the boosting coil 4. Then, the current is charged from the terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the step-up PFC control device 200 is stepped up.
　交流スイッチＳ２及びＳ１の同期動作したＰＷＭ動作では、前述のデッドタイム期間が設けられており、交流スイッチＳ２及びＳ１が貫通状態に陥ることはない。交流スイッチＳ２がオンからオフ動作状態になると、昇圧用コイル４に蓄えられた磁気エネルギーにより、昇圧用コイル４の電流は、交流スイッチＳ１を経由して図９Ａの経路（ｂ）にて平滑用コンデンサ７の接地されていない端子へ流入する。これは、デッドタイム期間では交流スイッチＳ１を昇圧用ダイオードとして、また、交流スイッチＳ１がオン動作状態では、交流スイッチＳ１を、オン抵抗Ｒｏｎを有する抵抗として働くためである。 In the PWM operation in which the AC switches S2 and S1 are operated synchronously, the above-described dead time period is provided, and the AC switches S2 and S1 do not fall into the through state. When the AC switch S2 is switched from ON to OFF, the current in the booster coil 4 is smoothed by the magnetic energy stored in the booster coil 4 via the AC switch S1 in the path (b) of FIG. 9A. It flows into the terminal of the capacitor 7 which is not grounded. This is because the AC switch S1 functions as a boosting diode during the dead time period, and the AC switch S1 functions as a resistor having an ON resistance Ron when the AC switch S1 is in the ON operation state.
　これに対して、入力交流電源１が負極性の時には、ＤＩＲ信号がＬｏｗレベルであり、図８Ｂのタイミング波形図から、入力交流電源１が正極性の場合と比べて交流スイッチＳ２及びＳ４の動きが入れ替わり、また、交流スイッチＳ１及びＳ３の動きが入れ替わることが判る。 On the other hand, when the input AC power supply 1 has a negative polarity, the DIR signal is at a low level. From the timing waveform diagram of FIG. 8B, the movement of the AC switches S2 and S4 compared to the case where the input AC power supply 1 has a positive polarity. It can be seen that the AC switches S1 and S3 are switched.
　図９Ｂでは、交流スイッチＳ４がＰＷＭ動作をして昇圧用コイル４を駆動し、交流スイッチＳ３がＰＷＭ動作の反転した動作状態となっている。交流スイッチＳ２がオン抵抗Ｒｏｎを有する抵抗として電流を流し、交流スイッチＳ１はオフ動作状態のため等価回路的にはダイオードと見なせるが電流が流れない状態となっている。交流スイッチＳ４がＰＷＭ動作でオン動作状態の時は、図９Ｂの経路（ａ）にて昇圧用コイル４を励磁させる電流が流れる。一方、交流スイッチＳ４がＰＷＭ動作でオフ動作状態の時は、昇圧用コイル４に蓄えられた磁気エネルギーにより、図９Ｂの経路（ｂ）にて電流が交流スイッチＳ３を経由して流れる。そして、平滑用コンデンサ７の接地されていない端子から電流が充電され昇圧型ＰＦＣ制御装置２００の出力電圧Ｖｏが昇圧されていく。 In FIG. 9B, the AC switch S4 performs a PWM operation to drive the boosting coil 4, and the AC switch S3 is in an operating state in which the PWM operation is inverted. The AC switch S2 passes a current as a resistor having an ON resistance Ron, and the AC switch S1 is in an OFF operation state, and can be regarded as a diode in terms of an equivalent circuit, but no current flows. When the AC switch S4 is in the ON operation state by the PWM operation, a current for exciting the boosting coil 4 flows through the path (a) in FIG. 9B. On the other hand, when the AC switch S4 is in the OFF operation state by the PWM operation, the current flows through the AC switch S3 in the path (b) of FIG. 9B due to the magnetic energy stored in the boosting coil 4. Then, the current is charged from the terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the step-up PFC control device 200 is stepped up.
　この場合においても、交流スイッチＳ４及びＳ３の同期動作したＰＷＭ動作では、前述のデッドタイム区間が設けてある。そして、入力交流電源１が正極性である時の交流スイッチＳ１と同じ動作を交流スイッチＳ３が行い、昇圧用コイル４の電流は交流スイッチＳ３を経由して経路（ｂ）で平滑用コンデンサ７の接地されていない端子へ流入する。 Also in this case, the aforementioned dead time interval is provided in the PWM operation in which the AC switches S4 and S3 are operated synchronously. Then, the AC switch S3 performs the same operation as the AC switch S1 when the input AC power supply 1 is positive, and the current of the boosting coil 4 is passed through the AC switch S3 through the path (b) of the smoothing capacitor 7. It flows into a terminal that is not grounded.
　以上の動作より、入力交流電源１の電圧極性が正であっても負であっても平滑用コンデンサ７の接地されていない端子には、常に昇圧用コイル４の磁気エネルギーによって電流が流れ、出力電圧Ｖｏは昇圧されることが判る。従って、図１のドライブロジック回路５３を実施形態のもう一つの変形例のドライブロジック回路６３に置き換えても、結果的に同じ昇圧動作を実現していることがわかる。 From the above operation, a current always flows through the terminal of the smoothing capacitor 7 that is not grounded regardless of whether the voltage polarity of the input AC power supply 1 is positive or negative, by the magnetic energy of the boosting coil 4, and output It can be seen that the voltage Vo is boosted. Therefore, it can be seen that even if the drive logic circuit 53 of FIG. 1 is replaced with the drive logic circuit 63 of another modification of the embodiment, the same boosting operation is realized as a result.
　また、図１に示された昇圧用コイル４に流れる電流が略零の状態では、図８Ａに示されたヒステリシス比較器が、電流がほとんど流れていないことを検出する。ヒステリシス比較器は、電流検出素子３の出力信号を第２絶対値回路１１で正の電圧信号に変換した信号Ｓｃと、比較基準電圧ＶＲＢとを比較することにより、昇圧用コイル４に流れる電流を検出する。また、図８Ｂのように、ＬＰＷＭ信号で昇圧用コイル４をスイッチング駆動している交流スイッチＳ２またはＳ４に対して、交流スイッチＳ１またはＳ３は、ＵＰＷＭ信号により同期動作している。交流スイッチＳ１またはＳ３は、ヒステリシス比較器のゼロ電流検出動作により、そのゲート信号をＬｏｗレベルに変化させられ、ダイオード動作へと変化する。 Further, when the current flowing through the boosting coil 4 shown in FIG. 1 is substantially zero, the hysteresis comparator shown in FIG. 8A detects that almost no current flows. The hysteresis comparator compares the signal Sc obtained by converting the output signal of the current detection element 3 into a positive voltage signal by the second absolute value circuit 11 and the comparison reference voltage VRB, thereby obtaining the current flowing through the boosting coil 4. To detect. Further, as shown in FIG. 8B, the AC switch S1 or S3 is operated synchronously with the UPWM signal with respect to the AC switch S2 or S4 that switches the boosting coil 4 with the LPWM signal. The AC switch S1 or S3 has its gate signal changed to Low level by the zero current detection operation of the hysteresis comparator, and changes to diode operation.
　この機能は、昇圧用コイル４に流れる電流が略零の場合、昇圧用コイル４に蓄えられた磁気的なエネルギーがなくなるために、出力側から交流スイッチと昇圧用コイル４を介して入力交流電源１に電流が逆流することを回避するためのものである。 In this function, when the current flowing through the boosting coil 4 is substantially zero, the magnetic energy stored in the boosting coil 4 is lost, so that the input AC power source is connected from the output side through the AC switch and the boosting coil 4. This is to prevent the current from flowing back to 1.
　なお、昇圧用コイル４にて電流が流れなくなると、昇圧用コイル４の両端電圧がリンギング現象を起こすことがある。この場合は、図８Ａに図示されていないが、ヒステリシス比較器の出力信号がＬｏｗレベルになるとある一定期間Ｌｏｗレベルを維持する機能を、ヒステリシス比較器の後段に追加すればよい。 Note that if current stops flowing through the boosting coil 4, the voltage across the boosting coil 4 may cause a ringing phenomenon. In this case, although not shown in FIG. 8A, a function of maintaining the Low level for a certain period when the output signal of the hysteresis comparator becomes Low level may be added to the subsequent stage of the hysteresis comparator.
　以上、本発明の実施の形態の第２の変形例のドライブロジック回路６３により、ダイオードが無く、またスイッチング素子の寄生ダイオードも無い昇圧型ＰＦＣ制御装置が実現される。 As described above, the drive logic circuit 63 according to the second modification of the embodiment of the present invention realizes a step-up PFC control device without a diode and without a parasitic diode of a switching element.
　（比較例）
　以下では、本発明の実施の形態及びその変形例に対する比較例について説明する。 (Comparative example)
Below, the comparative example with respect to embodiment of this invention and its modification is demonstrated.
　図１０は、比較例に係る昇圧型ＰＦＣ制御装置の回路ブロック図である。同図に記載された昇圧型ＰＦＣ制御装置３００は、整流ダイオードブリッジのない昇圧型ＰＦＣ回路である。 FIG. 10 is a circuit block diagram of a boost type PFC control device according to a comparative example. The step-up type PFC control device 300 shown in the figure is a step-up type PFC circuit without a rectifier diode bridge.
　本比較例に係る昇圧型ＰＦＣ制御装置３００は、図１３に記載された特許文献１の昇圧型ＰＦＣ制御装置５００が有している、一対のスイッチング素子Ｔ３及びＴ４と高域阻止フィルタ５０２とが除外されている。一対のスイッチング素子Ｔ３及びＴ４は、昇圧動作のために１８０度位相をずらしてスイッチング動作を２回行うための仕組みである。また、昇圧型ＰＦＣ制御装置５００が有している、スイッチング動作を行う一対のスイッチング素子Ｔ１及びＴ２は、ｎ形ＭＯＳＦＥＴ等のシリコン系半導体のスイッチング素子Ｔ５及びＴ６に置き換えられている。さらに、スイッチング素子Ｔ５及びＴ６を駆動するためのレベルシフト機能を有するプリドライブ回路５１と電源５２とが付加されている。以後、図１３を基に、整流ダイオードブリッジのない昇圧型ＰＦＣ制御装置３００の動作及び課題を説明する。 A step-up PFC control apparatus 300 according to this comparative example includes a pair of switching elements T3 and T4 and a high-frequency block filter 502 included in the step-up PFC control apparatus 500 of Patent Document 1 described in FIG. Excluded. The pair of switching elements T3 and T4 is a mechanism for performing the switching operation twice while shifting the phase by 180 degrees for the boosting operation. In addition, the pair of switching elements T1 and T2 that perform the switching operation included in the step-up PFC control device 500 are replaced with silicon-based semiconductor switching elements T5 and T6 such as an n-type MOSFET. Further, a pre-drive circuit 51 having a level shift function for driving the switching elements T5 and T6 and a power source 52 are added. Hereinafter, the operation and problem of the step-up PFC control apparatus 300 without a rectifier diode bridge will be described with reference to FIG.
　図１０において、第１誤差増幅器１９は昇圧型ＰＦＣ制御装置３００の出力電圧Ｖｏと出力電圧を設定する基準電圧源１８の電圧値Ｖｒｅｆとの差分に比例した誤差電圧Ｖｅを生成する。差動増幅器１７及び第１絶対値回路２１により入力交流電源１の交流電圧を全波整流した電圧と相似形に波形生成された電圧信号Ｖｉｎａが生成される。乗算回路１０は、誤差電圧Ｖｅと電圧信号Ｖｉｎａとを乗算して、電流制御指令値となる電圧信号Ｉｒｅｆを生成する。この電圧信号Ｉｒｅｆは、誤差電圧Ｖｅに比例し、且つ、入力交流電源１の交流電圧を全波整流した電圧波形と相似形のＶｉｎａと同じ脈動波形となる。 10, the first error amplifier 19 generates an error voltage Ve that is proportional to the difference between the output voltage Vo of the step-up PFC controller 300 and the voltage value Vref of the reference voltage source 18 that sets the output voltage. A voltage signal Vina having a waveform similar to a voltage obtained by full-wave rectifying the AC voltage of the input AC power supply 1 is generated by the differential amplifier 17 and the first absolute value circuit 21. The multiplier circuit 10 multiplies the error voltage Ve and the voltage signal Vina to generate a voltage signal Iref that becomes a current control command value. The voltage signal Iref is proportional to the error voltage Ve and has the same pulsation waveform as Vina that is similar to the voltage waveform obtained by full-wave rectifying the AC voltage of the input AC power supply 1.
　一方で、スイッチング素子Ｔ５及びＴ６のスイッチング動作により、入力交流電源１から昇圧用コイル４に流れる電流は、電流検出素子３により検出され、第２絶対値回路１１により正の値の電圧値信号に波形整形された電流波形信号Ｓｃに変換される。 On the other hand, the current flowing from the input AC power source 1 to the boosting coil 4 by the switching operation of the switching elements T5 and T6 is detected by the current detection element 3, and converted to a positive voltage value signal by the second absolute value circuit 11. It is converted to a current-shaped waveform waveform Sc.
　第２誤差増幅器９、ＰＷＭコンパレータ１２、のこぎり波発振器１４、スイッチング素子Ｔ５又はＴ６、昇圧用コイル４、ダイオードＤ１又はＤ２、平滑用コンデンサ７、出力負荷８、電流検出素子３、及び第２絶対値回路１１により、電流制御負帰還ループが構成されている。電流波形信号Ｓｃは、この電流制御負帰還ループにより、電圧信号Ｉｒｅｆに追従するように制御され、電圧信号Ｉｒｅｆとほぼ同じ値となる。 Second error amplifier 9, PWM comparator 12, sawtooth oscillator 14, switching element T5 or T6, boosting coil 4, diode D1 or D2, smoothing capacitor 7, output load 8, current detection element 3, and second absolute value The circuit 11 forms a current control negative feedback loop. The current waveform signal Sc is controlled to follow the voltage signal Iref by this current control negative feedback loop, and has substantially the same value as the voltage signal Iref.
　電圧信号Ｉｒｅｆは、入力交流電源１の交流電圧を全波整流した電圧波形と相似形の脈動波形である。そのため、電流波形信号Ｓｃが電圧信号Ｉｒｅｆに追従するということは、入力交流電源１の交流電圧と入力交流電源１の交流電流とがほぼ同位相でかつほぼ同波形となるということである。従って、入力交流電源の力率はほぼ１となる。 The voltage signal Iref is a pulsation waveform similar to a voltage waveform obtained by full-wave rectification of the AC voltage of the input AC power supply 1. Therefore, the fact that the current waveform signal Sc follows the voltage signal Iref means that the AC voltage of the input AC power supply 1 and the AC current of the input AC power supply 1 have substantially the same phase and substantially the same waveform. Therefore, the power factor of the input AC power supply is approximately 1.
　また、誤差電圧Ｖｅは、出力電圧Ｖｏと電圧値Ｖｒｅｆとの差分が第１誤差増幅器１９により増幅された電圧である。第１誤差増幅器１９と乗算回路１０と上述した電流制御負帰還ループとで構成されるＰＦＣ制御ループにより、第１誤差増幅器１９の出力である誤差電圧Ｖｅは有限の値となるように制御される。誤差電圧Ｖｅは第１誤差増幅器１９のゲインをＡとすると、下記の式で記述される。 The error voltage Ve is a voltage obtained by amplifying the difference between the output voltage Vo and the voltage value Vref by the first error amplifier 19. The error voltage Ve that is the output of the first error amplifier 19 is controlled to be a finite value by the PFC control loop including the first error amplifier 19, the multiplier circuit 10, and the above-described current control negative feedback loop. . The error voltage Ve is described by the following equation, where A is the gain of the first error amplifier 19.
　　　　Ｖｅ　＝　Ａ×（Ｖｒｅｆ－Ｖｏ）　　・・・・・　（式１）
　従って、誤差電圧Ｖｅが有限の値であることは、第１誤差増幅器１９のゲインＡが十分に大きく設定されていれば、Ｖｒｅｆ＝Ｖｏとなる。つまり昇圧型ＰＦＣ制御装置３００の出力電圧Ｖｏは電圧値Ｖｒｅｆによって決まる固定電圧値となる。 Ve = A × (Vref−Vo) (Equation 1)
Therefore, if the error voltage Ve is a finite value, if the gain A of the first error amplifier 19 is set sufficiently large, Vref = Vo. That is, the output voltage Vo of the step-up PFC control device 300 becomes a fixed voltage value determined by the voltage value Vref.
　以上の説明からわかるように、本比較例に係る昇圧型ＰＦＣ制御装置３００では、その出力電圧Ｖｏは基準電圧の電圧値Ｖｒｅｆで設定された所望の電圧を維持しながら、入力交流電源の力率をほぼ１にできる高入力力率の昇圧型ＡＣ／ＤＣコンバータが実現される。 As can be seen from the above description, in the step-up PFC control device 300 according to this comparative example, the output voltage Vo maintains the desired voltage set by the voltage value Vref of the reference voltage, and the power factor of the input AC power supply. Thus, a step-up AC / DC converter with a high input power factor capable of reducing the power to approximately 1 is realized.
　また、差動増幅器１７、コンパレータ２０、ＮＯＴ論理回路１３、２つのＡＮＤ論理回路１６、スイッチング素子Ｔ５及びＴ６、及びダイオードＤ１及びＤ２により、整流ダイオードブリッジを用いない整流昇圧スイッチング動作が実現できている。以下、この点について説明する。 The differential amplifier 17, the comparator 20, the NOT logic circuit 13, the two AND logic circuits 16, the switching elements T5 and T6, and the diodes D1 and D2 realize a rectified boost switching operation without using a rectifier diode bridge. . Hereinafter, this point will be described.
　コンパレータ２０が差動増幅器１７の出力信号を比較することで、入力交流電源１の交流電圧の極性が判断される（この入力交流電源１の交流電圧の極性は、昇圧用コイル４に対して入力交流電源１が正の電圧を印加する時に、正の極性とする）。交流電圧の極性が正であればコンパレータ２０の出力信号はＨｉｇｈレベルとなり、交流電圧の極性が負であれば出力はＬｏｗとなる。 The comparator 20 compares the output signal of the differential amplifier 17 to determine the polarity of the AC voltage of the input AC power supply 1 (the polarity of the AC voltage of the input AC power supply 1 is input to the boosting coil 4). When the AC power supply 1 applies a positive voltage, the polarity is positive). If the polarity of the alternating voltage is positive, the output signal of the comparator 20 is at a high level, and if the polarity of the alternating voltage is negative, the output is low.
　ＮＯＴ論理回路１３と２つのＡＮＤ論理回路１６は、コンパレータ２０の出力信号を受けて、スイッチング素子Ｔ５及びＴ６を制御する。具体的には、入力交流電圧の極性が正であれば、ＮＯＴ論理回路１３と２つのＡＮＤ論理回路１６は、昇圧用スイッチング動作の為にＰＷＭコンパレータ１２から出力されるＰＷＭ信号でスイッチング素子Ｔ６がＰＷＭ駆動させる。そして、ＮＯＴ論理回路１３と２つのＡＮＤ論理回路１６は、スイッチング素子Ｔ５のゲート電圧をＬｏｗレベルにしてスイッチング素子Ｔ５をオフさせる。それに対し、入力交流電圧の極性が負であれば、ＮＯＴ論理回路１３及び２つのＡＮＤ論理回路１６は、ＰＷＭ信号でスイッチング素子Ｔ５をＰＷＭ駆動させる。そして、ＮＯＴ論理回路１３及び２つのＡＮＤ論理回路１６は、スイッチング素子Ｔ６のゲート電圧をＬｏｗレベルにしてスイッチング素子Ｔ６をオフさせる。 The NOT logic circuit 13 and the two AND logic circuits 16 receive the output signal of the comparator 20 and control the switching elements T5 and T6. Specifically, if the polarity of the input AC voltage is positive, the NOT logic circuit 13 and the two AND logic circuits 16 are connected to the switching element T6 by the PWM signal output from the PWM comparator 12 for the boosting switching operation. PWM drive. Then, the NOT logic circuit 13 and the two AND logic circuits 16 set the gate voltage of the switching element T5 to the Low level to turn off the switching element T5. On the other hand, if the polarity of the input AC voltage is negative, the NOT logic circuit 13 and the two AND logic circuits 16 PWM drive the switching element T5 with a PWM signal. Then, the NOT logic circuit 13 and the two AND logic circuits 16 set the gate voltage of the switching element T6 to the Low level to turn off the switching element T6.
　図１１Ａは、比較例に係る入力交流電源の電圧極性が正の場合におけるスイッチング素子の状態を表す等価回路図である。図１１Ｂは、比較例に係る入力交流電源の電圧極性が負の場合におけるスイッチング素子の状態を表す等価回路図である。つまり、図１１Ａ及び図１１Ｂは、入力交流電源１の電圧極性が正の場合と負の場合とで、コンパレータ２０、ＮＯＴ論理回路１３、及び２つのＡＮＤ論理回路１６の動作によるＰＷＭ動作によって、どのようにして昇圧動作がなされるかを説明する図である。 FIG. 11A is an equivalent circuit diagram showing the state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive. FIG. 11B is an equivalent circuit diagram illustrating a state of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative. That is, FIG. 11A and FIG. 11B show which is different depending on the PWM operation by the operation of the comparator 20, the NOT logic circuit 13, and the two AND logic circuits 16, depending on whether the voltage polarity of the input AC power supply 1 is positive or negative. It is a figure explaining how voltage | pressure | voltage rise operation | movement is made in this way.
　スイッチング素子Ｔ６がＰＷＭ動作でオン動作状態の時は、図１１Ａの経路（ａ）にて昇圧用コイル４を励磁させる電流が流れる。また、スイッチング素子Ｔ６がＰＷＭ動作でオフ動作をする時は、図１１Ａの経路（ｂ）にて昇圧用コイル４に蓄えられた磁気エネルギーにより電流が流れる。そして、平滑用コンデンサ７の接地されていない端子から電流が充電され昇圧型ＰＦＣ制御装置３００の出力電圧Ｖｏが昇圧される。なお、スイッチング素子Ｔ５及びＴ６は、ｎ型ＭＯＳＦＥＴ等のシリコン系半導体のスイッチング素子であるため、図１０に示されたように、ソース端子とドレイン端子との間に寄生ダイオードが存在している。よって、図１１Ａのように、経路（ｂ）にて昇圧用コイル４の磁気エネルギーにより発生する電流は、スイッチング素子Ｔ５の寄生ダイオードを経由して流れる。 When the switching element T6 is in the ON operation state by the PWM operation, a current for exciting the boosting coil 4 flows through the path (a) in FIG. 11A. Further, when the switching element T6 is turned off by the PWM operation, a current flows by the magnetic energy stored in the boosting coil 4 through the path (b) of FIG. 11A. Then, a current is charged from a terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the boost PFC control device 300 is boosted. Since the switching elements T5 and T6 are silicon semiconductor switching elements such as n-type MOSFETs, there are parasitic diodes between the source terminal and the drain terminal as shown in FIG. Therefore, as shown in FIG. 11A, the current generated by the magnetic energy of the boosting coil 4 in the path (b) flows via the parasitic diode of the switching element T5.
　一方、スイッチング素子Ｔ５がＰＷＭ動作でオン動作状態の時は、図１１Ｂの経路（ａ）にて昇圧用コイル４を励磁させる電流が流れる。また、スイッチング素子Ｔ５がＰＷＭ動作でオフ動作をする時は、図１１Ｂの経路（ｂ）にて昇圧用コイル４に蓄えられた磁気エネルギーにより電流が流れる。そして、この場合でも平滑用コンデンサ７の接地されていない端子から電流が充電され昇圧型ＰＦＣ制御装置３００の出力電圧Ｖｏが昇圧される。よって、図１１Ｂのように、経路（ｂ）にて昇圧用コイル４の磁気エネルギーにより流れる電流は、スイッチング素子Ｔ６の寄生ダイオードを経由して流れる。 On the other hand, when the switching element T5 is in the ON operation state by the PWM operation, a current for exciting the boosting coil 4 flows through the path (a) in FIG. 11B. Further, when the switching element T5 is turned off by the PWM operation, a current flows due to the magnetic energy stored in the boosting coil 4 through the path (b) in FIG. 11B. Even in this case, the current is charged from the terminal of the smoothing capacitor 7 that is not grounded, and the output voltage Vo of the step-up PFC control device 300 is stepped up. Therefore, as shown in FIG. 11B, the current that flows due to the magnetic energy of the boosting coil 4 in the path (b) flows through the parasitic diode of the switching element T6.
　しかしながら、比較例に係る昇圧型ＰＦＣ制御装置３００では、以下の２つの課題がある。 However, the boost type PFC control device 300 according to the comparative example has the following two problems.
　（１）ダイオードＤ１またはＤ２の順方向電圧ＶＦと、スイッチング素子Ｔ５またはＴ６の寄生ダイオードの順方向電圧ＶＦＰとによる電圧降下による損失が発生する。 (1) A loss due to a voltage drop due to the forward voltage VF of the diode D1 or D2 and the forward voltage VFP of the parasitic diode of the switching element T5 or T6 occurs.
　（２）スイッチング素子Ｔ５またはＴ６の寄生ダイオードのリカバリー電流により、スイッチング素子Ｔ５またはＴ６のターンオン動作時のスイッチング損失が大きい。 (2) Due to the recovery current of the parasitic diode of the switching element T5 or T6, the switching loss during the turn-on operation of the switching element T5 or T6 is large.
　この２点の課題について説明する。 こ の I will explain these two issues.
　まず、ダイオードの順方向電圧ＶＦ及び寄生ダイオードの順方向電圧ＶＦＰに関する課題（１）について説明する。入力交流電源１の交流電圧が正の場合、の図１１Ａの経路（ａ）にて電流が流れるときには、ダイオードＤ２の順方向電圧ＶＦが発生する。また、図１１Ａの経路（ｂ）にて電流が流れるときには、ダイオードＤ２の順方向電圧ＶＦに加え、オフ動作状態のスイッチング素子Ｔ５の順方向電圧ＶＦＰによる電圧降下が発生する。これらの電圧降下とこれらのダイオードに流れる電流とによって、ダイオードＤ２及びスイッチング素子Ｔ５に消費電力、すなわち損失が発生する。同様に、入力交流電源１の交流電圧が負の場合、図１１Ｂの経路（ａ）にて電流が流れるときは、ダイオードＤ１の順方向電圧ＶＦが発生する。また、図１１Ｂの経路（ｂ）にて電流が流れるときは、ダイオードＤ１の順方向電圧ＶＦ及びスイッチング素子Ｔ６の順方向電圧ＶＦＰによる電圧降下が発生し、ダイオードＤ１及びスイッチング素子Ｔ６に損失が発生する。 First, the problem (1) regarding the forward voltage VF of the diode and the forward voltage VFP of the parasitic diode will be described. When the AC voltage of the input AC power supply 1 is positive, the forward voltage VF of the diode D2 is generated when a current flows through the path (a) in FIG. 11A. When a current flows through the path (b) in FIG. 11A, a voltage drop due to the forward voltage VFP of the switching element T5 in the off operation state occurs in addition to the forward voltage VF of the diode D2. Power consumption, that is, loss occurs in the diode D2 and the switching element T5 due to these voltage drops and the current flowing through these diodes. Similarly, when the AC voltage of the input AC power supply 1 is negative, the forward voltage VF of the diode D1 is generated when a current flows through the path (a) in FIG. 11B. Further, when a current flows through the path (b) in FIG. 11B, a voltage drop due to the forward voltage VF of the diode D1 and the forward voltage VFP of the switching element T6 occurs, and loss occurs in the diode D1 and the switching element T6. To do.
　電流が定常的に流れることによる素子の消費電力は、導通損失と呼ばれる。スイッチング素子Ｔ５またはＴ６がオン動作状態で電流が流れた場合の導通損失は、オン抵抗が小さいために、ダイオードの順方向電圧ＶＦまたはＶＦＰの電圧降下による導通損失に比べ非常に小さなものとなる。従って、図１１Ａ及び図１１Ｂに示された電流経路からわかるように、従来の昇圧型ＰＦＣ制御装置の導通損失の大部分はダイオードの順方向電圧ＶＦ及びＶＦＰによるものであることがわかる。つまり、比較例に係る昇圧型ＰＦＣ制御装置３００のダイオードＤ１及びＤ２と、スイッチング素子Ｔ５及びＴ６の寄生ダイオードをなくすことができれば、昇圧型ＰＦＣ制御装置３００の導通損失を大幅に削減できる。 The power consumption of the element due to the constant flow of current is called conduction loss. The conduction loss when the current flows while the switching element T5 or T6 is in the on-operation state is very small compared to the conduction loss due to the voltage drop of the forward voltage VF or VFP of the diode because the on-resistance is small. Therefore, as can be seen from the current paths shown in FIGS. 11A and 11B, it can be seen that most of the conduction loss of the conventional boost type PFC control device is due to the forward voltages VF and VFP of the diode. That is, if the diodes D1 and D2 of the boost type PFC control device 300 according to the comparative example and the parasitic diodes of the switching elements T5 and T6 can be eliminated, the conduction loss of the boost type PFC control device 300 can be greatly reduced.
　次に、スイッチング損失の課題（２）について説明する。スイッチング素子Ｔ５及びＴ６のソース端子とドレイン端子の間に存在する寄生ダイオードのアノードはスイッチング素子のソースに、また、寄生ダイオードのカソードはスイッチング素子のドレインに存在する。図１１Ａでは、スイッチング素子Ｔ５がオフ動作状態のとき、経路（ｂ）にて電流が流れる場合に、寄生ダイオードのアノードからカソードに電流が流れている。また、図１１Ｂでは、スイッチング素子Ｔ６がオフ動作状態のとき、経路（ｂ）にて電流が流れる場合に、寄生ダイオードのアノードからカソードに電流が流れている。 Next, the problem (2) of switching loss will be described. The anode of the parasitic diode existing between the source terminal and the drain terminal of the switching elements T5 and T6 is at the source of the switching element, and the cathode of the parasitic diode is at the drain of the switching element. In FIG. 11A, when the switching element T5 is in the OFF operation state, when a current flows through the path (b), a current flows from the anode to the cathode of the parasitic diode. In FIG. 11B, when the switching element T6 is in the OFF operation state, when a current flows through the path (b), a current flows from the anode to the cathode of the parasitic diode.
　この時、寄生ダイオードにはダイオード内の少数キャリア蓄積効果によるリカバリー電流成分が発生する。つまり、経路（ｂ）状態から、経路（ａ）の状態にて電流が流れる始める時に、寄生ダイオードのリカバリー電流をも駆動する。具体的に説明すると、経路（ｂ）は、スイッチング素子Ｔ５及びＴ６の一方がオフ動作状態で寄生ダイオードに電流が流れている状態である。ここで、スイッチング素子Ｔ５及びＴ６の他方がターンオンして経路（ａ）になる際に、ターンオン動作により、昇圧用コイル４を駆動するための電流だけでなく、不要な寄生ダイオードのリカバリー電流をも駆動する。 At this time, the recovery current component due to the minority carrier accumulation effect in the diode is generated in the parasitic diode. That is, when the current starts to flow from the path (b) state to the path (a) state, the recovery current of the parasitic diode is also driven. Specifically, the path (b) is a state in which one of the switching elements T5 and T6 is in an off operation state and a current flows through the parasitic diode. Here, when the other of the switching elements T5 and T6 is turned on to become the path (a), not only the current for driving the boosting coil 4 but also the unnecessary parasitic diode recovery current is generated by the turn-on operation. To drive.
　図１２Ａは、比較例に係る入力交流電源の電圧極性が正の場合におけるスイッチング素子の過渡特性を表す図である。図１２Ｂは、比較例に係る入力交流電源の電圧極性が負の場合におけるスイッチング素子の過渡特性を表す図である。図１２Ａのように、スイッチング素子Ｔ６を流れる電流Ｉｄｓ（Ｔ６）には、状態（ｂ）から状態（ａ）の変化であるターンオン動作により、領域Ｒ１で示すように、昇圧用コイル４の駆動電流ＩＬ４に加えスイッチング素子Ｔ５の寄生ダイオードのリカバリー電流が重畳される。一方、図１２Ｂのように、スイッチング素子Ｔ５を流れる電流Ｉｄｓ（Ｔ５）には、状態（ｂ）から状態（ａ）の変化であるターンオン動作により、領域Ｒ２で示すように、昇圧用コイル４の駆動電流ＩＬ４に加えスイッチング素子Ｔ６の寄生ダイオードのリカバリー電流が重畳される。 FIG. 12A is a diagram illustrating the transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is positive. FIG. 12B is a diagram illustrating transient characteristics of the switching element when the voltage polarity of the input AC power supply according to the comparative example is negative. As shown in FIG. 12A, the current Ids (T6) flowing through the switching element T6 includes a drive current of the boosting coil 4 as indicated by a region R1 by a turn-on operation that is a change from the state (b) to the state (a). In addition to IL4, the recovery current of the parasitic diode of the switching element T5 is superimposed. On the other hand, as shown in the region R2, the current Ids (T5) flowing through the switching element T5 is changed to the current Ids (T5) flowing from the state (b) to the state (a) as shown in the region R2, as shown in FIG. In addition to the drive current IL4, the recovery current of the parasitic diode of the switching element T6 is superimposed.
　リカバリー電流は、無視できない大きなもので、スイッチング素子のスイッチング動作時の消費電力を意味するスイッチング損失の増大に影響を及ぼす。このスイッチング損失は、昇圧型ＰＦＣ制御装置のスイッチング周波数に比例して増大する。その為、昇圧用コイル４のサイズを小さくする目的で、スイッチング周波数を上げることは、スイッチング素子のスイッチング損失の増大を招く。つまり、本比較例に係る昇圧型ＰＦＣ制御装置３００では、将来的に昇圧コイルを小型化することが困難である。また現状の問題としても、かなり大きなスイッチング損失が発生するために電流連続モードでの昇圧型ＰＦＣ制御装置としては適切なものでない。この昇圧方式を使用する適切な条件は、電流が流れていない時にスイッチング素子がスイッチング動作する、いわゆるソフトスイッチングを前提にした条件でければならない。つまりこの昇圧方式では、ＰＦＣ制御方法について制限がある。 ∙ The recovery current is a large one that cannot be ignored and affects the increase in switching loss, which means power consumption during switching operation of the switching element. This switching loss increases in proportion to the switching frequency of the step-up PFC control device. Therefore, increasing the switching frequency for the purpose of reducing the size of the boosting coil 4 causes an increase in switching loss of the switching element. That is, it is difficult for the boost type PFC control apparatus 300 according to this comparative example to downsize the boost coil in the future. In addition, as a current problem, a considerably large switching loss is generated, so that it is not suitable as a step-up PFC control device in the current continuous mode. Appropriate conditions for using this boosting method must be based on the premise of so-called soft switching in which the switching element performs switching operation when no current flows. That is, in this boosting method, there is a limitation on the PFC control method.
　以上のように、本比較例に係る昇圧型ＰＦＣ制御装置３００では、スイッチング素子の寄生ダイオードが、寄生ダイオード自身の順方向電圧ＶＦによる消費電力の増大に関与しているだけでなく、異なるスイッチング素子のスイッチング損失にも影響を及ぼすという問題を有している。 As described above, in the step-up PFC control device 300 according to this comparative example, the parasitic diode of the switching element is not only involved in the increase in power consumption due to the forward voltage VF of the parasitic diode itself, but also the different switching element. It also has a problem of affecting the switching loss.
　（まとめ）
　実施の形態及びその変形例で説明したように、本発明に係る昇圧型ＰＦＣ制御装置は、入力された単相交流電圧を整流して昇圧するＡＣ／ＤＣコンバータ部を有する。さらに、ＡＣ／ＤＣコンバータ部は、ブリッジ接続された複数の交流スイッチ部と、昇圧用コイルと、平滑用コンデンサと、ドライブロジック回路とを有する。昇圧用コイルは、単相交流電圧の印加に応じて流れる双方向電流に応じた磁気エネルギーを蓄える。平滑用コンデンサは、昇圧用コイルに蓄えられた磁気エネルギーに対応した電荷を蓄える。ドライブロジック回路は、複数の交流スイッチ部のオンオフ状態を制御することにより双方向電流の電流径路を切り換えて、昇圧用コイルへの磁気エネルギーの蓄積と平滑用コンデンサへの電荷蓄積とを交互に行わせる。複数の交流スイッチ部の各々は、ゲート端子とドレイン端子とソース端子とを有する。交流スイッチは、ＦＥＴ特性と、逆ＦＥＴ特性と、逆導通特性とを有する、双方向スイッチング素子で構成される。ＦＥＴ特性とは、ソース端子電圧に対するゲート端子電圧の差分電圧であるゲート／ソース間電圧が閾値電圧より高い場合に、ドレイン／ソース間電圧の極性に応じてドレイン端子からソース端子へ電流を流すことができる特性である。また、逆ＦＥＴ特性とは、ゲート／ソース間電圧が閾値電圧より高い場合に、ドレイン／ソース間電圧の極性に応じてソース端子からドレイン端子へ電流を流すことができる特性である。逆導通特性とは、ゲート／ソース間電圧が閾値電圧以下の場合に、ドレイン端子からソース端子への電流は遮断されるがドレイン端子電圧を基準にしてゲート端子電圧が閾値電圧以上になるとソース端子からドレイン端子に電流を流すことができる特性である。 (Summary)
As described in the embodiment and the modification thereof, the step-up PFC control device according to the present invention includes an AC / DC converter unit that rectifies and boosts an input single-phase AC voltage. Furthermore, the AC / DC converter unit includes a plurality of AC switch units that are bridge-connected, a boosting coil, a smoothing capacitor, and a drive logic circuit. The boosting coil stores magnetic energy corresponding to the bidirectional current that flows in response to the application of the single-phase AC voltage. The smoothing capacitor stores a charge corresponding to the magnetic energy stored in the boosting coil. The drive logic circuit switches the current path of bidirectional current by controlling the on / off state of a plurality of AC switch units, and alternately stores magnetic energy in the boosting coil and charges in the smoothing capacitor. Make it. Each of the plurality of AC switch units has a gate terminal, a drain terminal, and a source terminal. The AC switch includes a bidirectional switching element having FET characteristics, reverse FET characteristics, and reverse conduction characteristics. FET characteristics means that when a gate / source voltage, which is a differential voltage of a gate terminal voltage with respect to a source terminal voltage, is higher than a threshold voltage, a current flows from the drain terminal to the source terminal according to the polarity of the drain / source voltage. It is a characteristic that can be The reverse FET characteristic is a characteristic that allows a current to flow from the source terminal to the drain terminal according to the polarity of the drain / source voltage when the gate / source voltage is higher than the threshold voltage. Reverse conduction characteristics means that when the gate-source voltage is less than or equal to the threshold voltage, the current from the drain terminal to the source terminal is cut off, but when the gate terminal voltage exceeds the threshold voltage with respect to the drain terminal voltage, the source terminal The current can flow from the drain terminal to the drain terminal.
　この構成によれば、ＡＣ／ＤＣコンバータ部にダイオードが不要であり、またスイッチング素子には寄生ダイオードも無く、ダイオードの順方向電圧の電圧降下による消費電力を無くすことができる。また、スイッチング素子の寄生ダイオードのリカバリー電流によるスイッチング損失もなくなるので、大幅に消費電力を削減した昇圧型ＰＦＣ制御装置が実現できる。 According to this configuration, no diode is required in the AC / DC converter section, and there is no parasitic diode in the switching element, so that power consumption due to a voltage drop in the forward voltage of the diode can be eliminated. In addition, since there is no switching loss due to the recovery current of the parasitic diode of the switching element, it is possible to realize a step-up PFC control device that significantly reduces power consumption.
　また、双方向の電流径路を制御する昇圧用ＰＦＣ制御部は、従来の昇圧型ＰＦＣ制御装置の昇圧用ＰＦＣ制御部をそのまま用いることができ、昇圧型ＰＦＣ制御装置としての制御動作は従来のものとほとんど同じとなる。 Further, the boosting PFC control unit for controlling the bidirectional current path can use the boosting PFC control unit of the conventional boosting PFC control device as it is, and the control operation as the boosting PFC control device is conventional. Is almost the same.
　また、ドライブロジック回路は、ＡＣ／ＤＣコンバータ部と入力交流電源との間に流れる電流が略零の場合には、電流がないことを検出するヒステリシス比較器からの制御信号を受ける。そして、複数の交流スイッチ部のうち少なくとも１つの交流スイッチ部のゲート／ソース間電圧が閾値電圧以下になるように制御をする。 The drive logic circuit receives a control signal from a hysteresis comparator that detects that there is no current when the current flowing between the AC / DC converter unit and the input AC power supply is substantially zero. Then, control is performed so that the gate / source voltage of at least one of the plurality of AC switch units is equal to or lower than the threshold voltage.
　これにより、昇圧コイルに流れる電流が略零の場合は、昇圧用コイルの磁気エネルギーが無くなっても、昇圧型ＰＦＣ制御装置の出力側から入力交流電源へ電流が逆流しないようにすることが可能となる。 As a result, when the current flowing through the booster coil is substantially zero, it is possible to prevent the current from flowing backward from the output side of the booster type PFC control device to the input AC power supply even when the magnetic energy of the booster coil is lost. Become.
　また、実施の形態の第１の変形例によれば、複数の交流スイッチ部のうち少なくとも２個の交流スイッチ部は、ソース端子同士またはドレイン端子同士が直列接続された２つの双方向スイッチング素子で構成される。 Further, according to the first modification of the embodiment, at least two of the AC switch units are two bidirectional switching elements in which source terminals or drain terminals are connected in series. Composed.
　これによれば、上述した昇圧型ＰＦＣ制御装置と同様に、従来の昇圧型ＰＦＣ制御装置の整流昇圧動作を維持しつつ消費電力を低減することができる。さらには、高入力耐圧性を有する昇圧型ＰＦＣ制御装置が実現できる。また、この昇圧型ＰＦＣ制御装置は、入力交流電圧源から、ＰＦＣ制御装置の出力端子とＧＮＤ端子との間に接続される負荷を完全に切り離すことも可能である。 According to this, like the step-up PFC control device described above, it is possible to reduce power consumption while maintaining the rectification step-up operation of the conventional step-up type PFC control device. Furthermore, a step-up PFC control device having high input voltage resistance can be realized. In addition, the step-up PFC control device can completely disconnect the load connected between the output terminal and the GND terminal of the PFC control device from the input AC voltage source.
　また、実施の形態及びその変形例に係る昇圧型ＰＦＣ制御装置において、双方向のスイッチング素子は、半導体基板の上に形成された窒化物半導体層からなる積層体と、積層体の上に形成されたゲート端子と、ゲート端子を挟んで両側方に形成されたドレイン端子及びソース端子とを備える。双方向のスイッチング素子は、一般的に、窒化ガリウム半導体を用いたヘテロ接合電界効果トランジスタとして知られていて、ＧａＮトランジスタと呼ばれている。 Further, in the step-up PFC control device according to the embodiment and the modification thereof, the bidirectional switching element is formed on a stacked body including a nitride semiconductor layer formed on a semiconductor substrate, and on the stacked body. And a drain terminal and a source terminal formed on both sides of the gate terminal. The bidirectional switching element is generally known as a heterojunction field effect transistor using a gallium nitride semiconductor and is called a GaN transistor.
　ＧａＮトランジスタは、ゲート／ソース間電圧がある閾値電圧より高い場合にＦＥＴ特性と逆ＦＥＴ特性を有し、且つ、ゲート／ソース間電圧が閾値電圧以下の場合に逆導通特性を有する。また、ＧａＮトランジスタは、高耐圧特性を有する双方向スイッチング素子ともなり、ＦＥＴ特性及び逆ＦＥＴ特性において非常に低いオン抵抗値のＦＥＴトランジスタでもある。また、シリコン系半導体素子のような少数キャリア効果がなく、リカバリー電流によるスイッチング損失増大の影響もほとんど無い。従って、本発明の昇圧型ＰＦＣ制御装置が有する双方向のスイッチング素子としてＧａＮトランジスタを用いることで、より低消費電力の昇圧型ＰＦＣ制御装置が実現できる。 A GaN transistor has FET characteristics and reverse FET characteristics when the gate / source voltage is higher than a certain threshold voltage, and has reverse conduction characteristics when the gate / source voltage is equal to or lower than the threshold voltage. The GaN transistor also serves as a bidirectional switching element having high breakdown voltage characteristics, and is also an FET transistor having a very low on-resistance value in FET characteristics and reverse FET characteristics. Further, there is no minority carrier effect as in a silicon-based semiconductor element, and there is almost no influence of an increase in switching loss due to a recovery current. Therefore, by using a GaN transistor as a bidirectional switching element included in the step-up PFC control device of the present invention, a step-down PFC control device with lower power consumption can be realized.
　以上、本発明の昇圧型ＰＦＣ制御装置について、実施の形態に基づいて説明してきたが、本発明に係る昇圧型ＰＦＣ制御装置は、上記実施の形態及びその変形例に限定されるものではない。実施の形態及びその変形例における任意の構成要素を組み合わせて実現される別の実施の形態も本発明に含まれる。さらに、実施の形態及びその変形例に対して本発明の主旨を逸脱しない範囲で当業者が思いつく各種変形を施して得られる変形例も本発明に含まれる。さらに、本発明に係る昇圧型ＰＦＣ制御装置を内蔵した各種機器も本発明に含まれる。 As mentioned above, although the boost type PFC control device of the present invention has been described based on the embodiment, the boost type PFC control device according to the present invention is not limited to the above embodiment and its modifications. Another embodiment realized by combining arbitrary constituent elements in the embodiment and its modifications is also included in the present invention. Furthermore, the present invention also includes modifications obtained by making various modifications conceivable by those skilled in the art without departing from the spirit of the present invention to the embodiments and modifications thereof. Furthermore, various devices incorporating the boost type PFC control device according to the present invention are also included in the present invention.
　本発明は、交流入力から直流電圧を出力するＡＣ／ＤＣコンバータに適用でき、特に、整流ダイオードブリッジが不要である高入力力率及び高効率の昇圧型ＰＦＣ制御装置を有するＡＣ／ＤＣコンバータとして有用である。 The present invention can be applied to an AC / DC converter that outputs a DC voltage from an AC input, and is particularly useful as an AC / DC converter having a high-input power factor and high-efficiency step-up PFC controller that does not require a rectifier diode bridge. It is.
　１　　入力交流電源
　３　　電流検出素子
　４　　昇圧用コイル
　７　　平滑用コンデンサ
　８　　出力負荷
　９　　第２誤差増幅器
　１０　　乗算回路
　１１　　第２絶対値回路
　１２　　ＰＷＭコンパレータ
　１４，５１４，５１５　　のこぎり波発振器
　１７　　差動増幅器
　１８　　基準電圧源
　１９　　第１誤差増幅器
　２０　　コンパレータ
　２１　　第１絶対値回路
　３０，３１　　ＡＣ／ＤＣコンバータ部
　５１　　プリドライブ回路
　５２　　電源
　５３　　ドライブロジック回路
　１００，１５０，２００，３００，５００　　昇圧型ＰＦＣ制御装置
　２０１　　シリコン基板
　２０２　　バッファ層
　２０３　　積層体
　２０４　　アンドープ窒化ガリウム層
　２０５　　ｎ型窒化アルミニウムガリウム層
　２０６ａ　　ソース端子用オーミック電極
　２０６ｂ　　ドレイン端子用オーミック電極
　２０８　　ゲート電極
　２０９　　コントロール層
　２１０　　配線
　５０２　　高域阻止フィルタ
　５０４　　磁気誘導手段
　Ｓ１，Ｓ２，Ｓ３，Ｓ４　　交流スイッチ
　Ｔ１，Ｔ２，Ｔ３，Ｔ４，Ｔ５，Ｔ６　　スイッチング素子
　Ｄ１，Ｄ２　　ダイオード DESCRIPTION OF SYMBOLS 1 Input alternating current power supply 3 Current detection element 4 Boosting coil 7 Smoothing capacitor 8 Output load 9 2nd error amplifier 10 Multiplication circuit 11 2nd absolute value circuit 12 PWM comparator 14,514,515 sawtooth wave oscillator 17 Differential amplifier 18 Reference | standard Voltage source 19 First error amplifier 20 Comparator 21 First absolute value circuit 30, 31 AC / DC converter section 51 Pre-drive circuit 52 Power supply 53 Drive logic circuit 100, 150, 200, 300, 500 Boost type PFC controller 201 Silicon substrate 202 Buffer layer 203 Stack 204 Undoped gallium nitride layer 205 N-type aluminum gallium nitride layer 206a Ohmic electrode for source terminal 206b Ohmic electrode for drain terminal 208 Gate electrode 209 Control Le layer 210 lines 502 high-pass rejection filter 504 the magnetic induction means S1, S2, S3, S4 AC switch T1, T2, T3, T4, T5, T6 switching elements D1, D2 diode

Claims (5)

  1. 　入力された単相交流電圧を整流して昇圧するＡＣ／ＤＣコンバータ部を備える昇圧型ＰＦＣ制御装置であって、
    　前記ＡＣ／ＤＣコンバータ部は、
    　ブリッジ接続された複数の交流スイッチ部と、
    　前記単相交流電圧の印加に応じて流れる双方向電流に応じた磁気エネルギーを蓄える昇圧用コイルと、
    　前記昇圧用コイルに蓄えられた前記磁気エネルギーに対応した電荷を蓄える平滑用コンデンサと、
    　前記複数の交流スイッチ部のオンオフ状態を制御することにより前記双方向電流の電流径路を切り換えて、前記昇圧用コイルへの前記磁気エネルギーの蓄積と前記平滑用コンデンサへの電荷蓄積とを交互に行わせるドライブロジック回路とを備え、
    　前記複数の交流スイッチ部の各々は、
    　ゲート端子とドレイン端子とソース端子とを有し、（１）ソース電圧に対するゲート電圧であるゲート－ソース間電圧が閾値電圧より高い場合に、ドレイン－ソース間電圧の極性に応じて前記ドレイン端子から前記ソース端子へ、または、前記ソース端子から前記ドレイン端子へ電流を流し、（２）前記ゲート－ソース間電圧が前記閾値電圧と同じかそれより低い場合に、前記ドレイン端子から前記ソース端子に流れる電流を遮断し、ドレイン電圧に対する前記ゲート電圧が前記閾値電圧と同じかそれより高くなると前記ソース端子から前記ドレイン端子へ電流を流すスイッチング素子で構成される
    　昇圧型ＰＦＣ制御装置。     A step-up PFC control device including an AC / DC converter unit that rectifies and boosts an input single-phase AC voltage,
    The AC / DC converter unit includes:
    A plurality of AC switches connected in a bridge;
    A boosting coil that stores magnetic energy according to a bidirectional current that flows in response to the application of the single-phase AC voltage;
    A smoothing capacitor for storing a charge corresponding to the magnetic energy stored in the boosting coil;
    The current path of the bidirectional current is switched by controlling the on / off state of the plurality of AC switch units, and the accumulation of the magnetic energy in the boosting coil and the charge accumulation in the smoothing capacitor are alternately performed. Drive logic circuit
    Each of the plurality of AC switch units is
    A gate terminal, a drain terminal, and a source terminal; (1) when the gate-source voltage, which is the gate voltage with respect to the source voltage, is higher than the threshold voltage, the drain terminal depends on the polarity of the drain-source voltage. A current is passed to the source terminal or from the source terminal to the drain terminal; and (2) when the gate-source voltage is equal to or lower than the threshold voltage, the current flows from the drain terminal to the source terminal. A step-up PFC control device comprising a switching element that cuts off a current and causes a current to flow from the source terminal to the drain terminal when the gate voltage with respect to the drain voltage is equal to or higher than the threshold voltage.
  2. 　前記複数の交流スイッチ部は、
    　第１～第４の前記スイッチング素子を備え、
    　前記昇圧用コイルの第１の電極は、前記単相交流電圧が印加される第１交流端子に接続され、
    　前記第１のスイッチング素子のドレイン端子と前記第３のスイッチング素子のドレイン端子とは、前記平滑用コンデンサの第１の電極に接続され、
    　前記第２のスイッチング素子のソース端子と前記第４のスイッチング素子のソース端子とは、前記平滑用コンデンサの第２の電極に接続され、
    　前記第１のスイッチング素子のソース端子と前記第２のスイッチング素子のドレイン端子とは、前記昇圧用コイルの第２の電極に接続され、
    　前記第３のスイッチング素子のソース端子と前記第４のスイッチング素子のドレイン端子とは、前記単相交流電圧が印加される第２交流端子に接続され、
    　前記第１～第４のスイッチング素子のゲート端子は、前記ドライブロジック回路から出力される制御信号をレベルシフトする各々のプリドライブ回路に接続されており、
    　前記ドライブロジック回路は、前記第１のスイッチング素子と前記第２のスイッチング素子とが、または、前記第３のスイッチング素子と前記第４のスイッチング素子とが同時にオン状態とならないように制御する
    　請求項１に記載の昇圧型ＰＦＣ制御装置。     The plurality of AC switch units are
    Comprising the first to fourth switching elements,
    A first electrode of the boosting coil is connected to a first AC terminal to which the single-phase AC voltage is applied;
    The drain terminal of the first switching element and the drain terminal of the third switching element are connected to the first electrode of the smoothing capacitor,
    The source terminal of the second switching element and the source terminal of the fourth switching element are connected to the second electrode of the smoothing capacitor,
    The source terminal of the first switching element and the drain terminal of the second switching element are connected to the second electrode of the boosting coil,
    The source terminal of the third switching element and the drain terminal of the fourth switching element are connected to a second AC terminal to which the single-phase AC voltage is applied,
    The gate terminals of the first to fourth switching elements are connected to respective pre-drive circuits that level-shift control signals output from the drive logic circuit,
    The drive logic circuit controls so that the first switching element and the second switching element or the third switching element and the fourth switching element are not turned on at the same time. 2. The step-up PFC control device according to 1.
  3. 　前記ドライブロジック回路は、さらに、前記単相交流電圧を出力する交流電源と前記ＡＣ／ＤＣコンバータ部との間に流れる電流が零の場合には、前記複数の交流スイッチ部のうち少なくとも１つの前記交流スイッチ部を構成する前記スイッチング素子の前記ゲート－ソース間電圧が前記閾値電圧と同じかそれより低くなるように前記スイッチング素子のゲート信号を制御する
    　請求項１に記載の昇圧型ＰＦＣ制御装置。     The drive logic circuit further includes at least one of the plurality of AC switch units when the current flowing between the AC power source that outputs the single-phase AC voltage and the AC / DC converter unit is zero. 2. The step-up PFC control device according to claim 1, wherein a gate signal of the switching element is controlled so that a voltage between the gate and the source of the switching element constituting the AC switch unit is equal to or lower than the threshold voltage.
  4. 　前記複数の交流スイッチ部のうち少なくとも２個の前記交流スイッチ部は、
    　ソース端子同士またはドレイン端子同士が直列接続された２つの前記スイッチング素子で構成される
    　請求項１に記載の昇圧型ＰＦＣ制御装置。     At least two of the plurality of AC switch units are AC switch units,
    The step-up PFC control device according to claim 1, comprising two switching elements in which source terminals or drain terminals are connected in series.
  5. 　前記スイッチング素子は、
    　半導体基板の上に形成された複数の窒化物半導体層からなる積層体と、
    　前記積層体の上に形成された前記ゲート端子と、
    　前記ゲート端子を挟んで両側方に形成された前記ドレイン端子及び前記ソース端子とを備える
    　請求項１～４のうちいずれか１項に記載の昇圧型ＰＦＣ制御装置。     The switching element is
    A laminate composed of a plurality of nitride semiconductor layers formed on a semiconductor substrate;
    The gate terminal formed on the laminate;
    The boost PFC control device according to any one of claims 1 to 4, further comprising: the drain terminal and the source terminal formed on both sides of the gate terminal.
PCT/JP2012/000950 2011-03-07 2012-02-14 Boost pfc control device WO2012120788A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-049700 2011-03-07
JP2011049700A JP2014099946A (en) 2011-03-07 2011-03-07 Step-up pfc control unit

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